]> jspc29.x-matter.uni-frankfurt.de Git - trbnet.git/commitdiff
*** empty log message ***
authorhadeshyp <hadeshyp>
Wed, 7 Jan 2009 14:56:41 +0000 (14:56 +0000)
committerhadeshyp <hadeshyp>
Wed, 7 Jan 2009 14:56:41 +0000 (14:56 +0000)
testbenches/testbench_all_channels_p2p.prj
testbenches/testbench_all_channels_p2p.vhd

index 6d5d325e112407fdabe448938c26e39712598bc6..3cca81a8be732bd474d239bb2c3de61f01d4d452 100644 (file)
@@ -1,14 +1,9 @@
-
 vhdl work "../trb_net_std.vhd"
 vhdl work "../trb_net16_term_buf.vhd"
 vhdl work "../xilinx/shift_lut_x16.vhd"
 vhdl work "../xilinx/xilinx_fifo_lut.vhd"
-
 vhdl work "../xilinx/virtex2/simulation/xilinx_fifo_18x1k.vhd"
--- vhdl work "../xilinx/virtex4/simulation/xilinx_fifo_dualport_18x1k.vhd"
 vhdl work "../xilinx/virtex2/trb_net16_fifo_arch.vhd"
--- vhdl work "../trb_net16_fifo.vhd"
-
 vhdl work "../trb_net_CRC.vhd"
 vhdl work "../trb_net_onewire.vhd"
 vhdl work "../basics/rom_16x8.vhd"
@@ -35,18 +30,12 @@ vhdl work "../trb_net16_api_base.vhd"
 vhdl work "../trb_net16_iobuf.vhd"
 vhdl work "../trb_net16_io_multiplexer.vhd"
 vhdl work "../testbench/trb_net16_dummy_apl.vhd"
--- vhdl work "../testbench/trb_net16_dummy_passive_apl.vhd"
 vhdl work "../trb_net16_ipudata.vhd"
 vhdl work "../trb_net16_trigger.vhd"
 vhdl work "../trb_net16_endpoint_hades_full.vhd"
 vhdl work "../trb_net16_endpoint_active_4_channel.vhd"
-
--- vhdl work "../trb_net16_endpoint_1_trg_0_api.vhd"
-
--- vhdl work "../trb_net16_endpoint_1_trg_0_api.vhd"
 -- vhdl work "../trb_net_med_8bit_slow.vhd"
-
-vhdl work "../trb_net16_hub_func.vhd"
-vhdl work "../trb_net16_hub_base.vhd"
-vhdl work "../trb_net16_hub_logic.vhd"
-vhdl work "single_testbench.vhd"
\ No newline at end of file
+-- vhdl work "../trb_net16_hub_func.vhd"
+-- vhdl work "../trb_net16_hub_base.vhd"
+-- vhdl work "../trb_net16_hub_logic.vhd"
+vhdl work "testbench_all_channels_p2p.vhd"
\ No newline at end of file
index 66fb1f36f6c53dfb173e916eaa06799ad596cf31..ee022418e654c2aaf4fab8c6a18cb3e7f64919ba 100644 (file)
@@ -329,7 +329,7 @@ begin
     generic map(
       TARGET_ADDRESS   => x"FFFF",
       PREFILL_LENGTH   => 3,
-      TRANSFER_LENGTH  => 3
+      TRANSFER_LENGTH  => 10
       )
     port map(
       CLK    => CLK,
@@ -357,7 +357,7 @@ begin
     generic map(
       TARGET_ADDRESS   => x"FFFF",
       PREFILL_LENGTH   => 3,
-      TRANSFER_LENGTH  => 3
+      TRANSFER_LENGTH  => 10
       )
     port map(
       CLK    => CLK,
@@ -392,7 +392,7 @@ begin
     generic map(
       TARGET_ADDRESS   => x"FFFF",
       PREFILL_LENGTH   => 3,
-      TRANSFER_LENGTH  => 3
+      TRANSFER_LENGTH  => 10
       )
     port map(
       CLK    => CLK,
@@ -557,7 +557,7 @@ APL_LENGTH_IN <= (others => '0');
       STAT_ONEWIRE              => open
       );
 
-MPLEX_CTRL <= x"00000000";
+MPLEX_CTRL <= x"00000100";
 
 LVL1_TRG_RELEASE_IN <= '1';
 LVL1_ERROR_PATTERN_IN <= (others => '0');