-
vhdl work "../trb_net_std.vhd"
vhdl work "../trb_net16_term_buf.vhd"
vhdl work "../xilinx/shift_lut_x16.vhd"
vhdl work "../xilinx/xilinx_fifo_lut.vhd"
-
vhdl work "../xilinx/virtex2/simulation/xilinx_fifo_18x1k.vhd"
--- vhdl work "../xilinx/virtex4/simulation/xilinx_fifo_dualport_18x1k.vhd"
vhdl work "../xilinx/virtex2/trb_net16_fifo_arch.vhd"
--- vhdl work "../trb_net16_fifo.vhd"
-
vhdl work "../trb_net_CRC.vhd"
vhdl work "../trb_net_onewire.vhd"
vhdl work "../basics/rom_16x8.vhd"
vhdl work "../trb_net16_iobuf.vhd"
vhdl work "../trb_net16_io_multiplexer.vhd"
vhdl work "../testbench/trb_net16_dummy_apl.vhd"
--- vhdl work "../testbench/trb_net16_dummy_passive_apl.vhd"
vhdl work "../trb_net16_ipudata.vhd"
vhdl work "../trb_net16_trigger.vhd"
vhdl work "../trb_net16_endpoint_hades_full.vhd"
vhdl work "../trb_net16_endpoint_active_4_channel.vhd"
-
--- vhdl work "../trb_net16_endpoint_1_trg_0_api.vhd"
-
--- vhdl work "../trb_net16_endpoint_1_trg_0_api.vhd"
-- vhdl work "../trb_net_med_8bit_slow.vhd"
-
-vhdl work "../trb_net16_hub_func.vhd"
-vhdl work "../trb_net16_hub_base.vhd"
-vhdl work "../trb_net16_hub_logic.vhd"
-vhdl work "single_testbench.vhd"
\ No newline at end of file
+-- vhdl work "../trb_net16_hub_func.vhd"
+-- vhdl work "../trb_net16_hub_base.vhd"
+-- vhdl work "../trb_net16_hub_logic.vhd"
+vhdl work "testbench_all_channels_p2p.vhd"
\ No newline at end of file
generic map(
TARGET_ADDRESS => x"FFFF",
PREFILL_LENGTH => 3,
- TRANSFER_LENGTH => 3
+ TRANSFER_LENGTH => 10
)
port map(
CLK => CLK,
generic map(
TARGET_ADDRESS => x"FFFF",
PREFILL_LENGTH => 3,
- TRANSFER_LENGTH => 3
+ TRANSFER_LENGTH => 10
)
port map(
CLK => CLK,
generic map(
TARGET_ADDRESS => x"FFFF",
PREFILL_LENGTH => 3,
- TRANSFER_LENGTH => 3
+ TRANSFER_LENGTH => 10
)
port map(
CLK => CLK,
STAT_ONEWIRE => open
);
-MPLEX_CTRL <= x"00000000";
+MPLEX_CTRL <= x"00000100";
LVL1_TRG_RELEASE_IN <= '1';
LVL1_ERROR_PATTERN_IN <= (others => '0');