\item[Bit 8] Enable Shower calibration trigger
\item[Bit 9] Enable test trigger 0xE
\item[Bit 14] Enable beam inhibit
+ \item[Bit 16] Enable TOF/RPC to be a Start signal
\item[Bit 31] Enable trigger line test, this works together with self trigger (set the requried frequency)
\end{description}
\item [0xA0C1] LVL1/LVL2 trigger settings:
\begin{description}
\item[Bit 7 -- 0] Selects the output signal for LVDS OUT(4) (the order like on the Fig.\ref{cts_logic})
\begin{description}
- \item 31 - 0 After one clock
- \item 63 - 32 After delay
- \item 95 - 64 After downscale
- \item 127 - 96 After set width
+ \item 35 - 0 After one clock
+ \item 71 - 36 After delay
+ \item 72 - 107 After set width
+ \item 126 - 108 empty
+ \item 127 - start signal used for anticoincidence logic (after OR)
+ \item 128 - veto signal used for anticoincidence logic (after Width S.)
+ \item 129 - antycoincidence signal
\end{description}
\item[Bit 15 -- 8] Selects the output signal for LVDS OUT(5) (the same values as for LVDS OUT(4))
\item [0xA0C6 -- 0xA0C5] TS gating disable
\item [0xA0C8 -- 0xA0C7] Enable outputs
\item [0xA0D0 -- 0xA0C9] Downscale registers - $2^{value}$
+ \item [0xA0E7 -- 0xA0E5] Large delay registers - $value * 5\,ns$
\item [0xA0D8 -- 0xA0D1] Delay registers - $value * 1,25\,ns$
- \item [0xA0E0 -- 0xA0D9] Width registers - $1,25 + value * 1,25\,ns$
- \item [0xA0E1] LVL2 EB IP table
- \begin{description}
- \item[Bit 15 -- 0] When writing to this register EB is chosen to be a receiver e.g. : 0x8103 then EB15,EB8,EB1 and EB0 is selected
- \end{description}
- \item [0xA0E2] LVL2 - events per EB
- \begin{description}
- \item[Bit 23 -- 0] Number of events per EB
- \end{description}
+ \item [0xA0EC -- 0xA0E8] Width registers - $5 + value * 4\,ns$
+
\item [0xA0E3] Self trigger
\begin{description}
\item[Bit 27 -- 0] When 0 the internal triggering is disabled, when different than 0 the internal trigger is enabled and $frequency = 1/Value*10ns $
\item[Bit 13 -- 8] LVL1 trigger information(13 -- 8)
\end{description}
\item [0xA0E7 -- 0xA0E5] Large delays - value * 5ns
-
+ \item [0xA0F0] LVL2 EB IP table and downscale factor for removing not needed data
+ \begin{description}
+ \item[Bit 15 -- 0] When writing to this register EB is chosen to be a receiver e.g. : 0x8103 then EB15,EB8,EB1 and EB0 is selected
+% \item[Bit 23 -- 16] Threshold for the rate detection in $1\,us$ time, when number of hits equals the threshold (or more) the per 1sec marker is set
+% \item[Bit 31 -- 24] Threshold for the rate detection in $100\,ns$ time, when number of hits equals the threshold (or more) the per 1sec marker is set
+ \item[Bit 31 -- 16] When 0 all headers and trailers from TRB TDCs are transported , when different then the value is downsacling factor (counted per event) for transporting headers and trailers (bit 14 of the LVL1 trigger information).
+ \end{description}
+ \item [0xA0F1] LVL2 - events per EB
+ \begin{description}
+ \item[Bit 23 -- 0] Number of events per EB
+ \end{description}
\end{description}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\item[0xA001: LVL1 information] Busy flags and current trigger number and type on LVL1 channel
\begin{description}
\item[Bit 19 -- 0] Accepted event rate
- \item[Bit 20] LVL2 CTS busy
- \item[Bit 21] LVL2 TrbNet busy
- \item[Bit 22] LVL2 local busy
+ \item[Bit 20] not used
+ \item[Bit 21] not used
+ \item[Bit 22] not used
\item[Bit 23] 0
\item[Bit 31 -- 24] LVL1 and LVL2 difference
\end{description}
\item[0xA002: Mixed information] LVL1 trigger rate, further busy flags for LVL1 and IPU channel
\begin{description}
- \item[Bit 15 -- 0] LVL2 trigger number
+ \item[Bit 15 -- 0] not used
\item[Bit 19 -- 16] Trigger fifo data counter lower 4 bits
\item[Bit 23 -- 20] LVL1 internal readout state machine :
\begin{description}
\item[Bit 25] unknown address set
\end{description}
- \item[0xA028 -- 0xA008 ] Input scalers
- \item[0xA037 -- 0xA029 ] Scalers after downscaling
- \item[0xA046 -- 0xA038 ] Scalers after trigger accepted
+ \item[0xA02B -- 0xA008 ] Input scalers
+ \item[0xA03E -- 0xA02C ] Scalers after downscaling
+ \item[0xA051 -- 0xA03F ] Scalers after trigger accepted
+
+% \item[0xA046] Rate markers for start detector
+% \begin{description}
+% \item[Bit 7 -- 0] If one of the bits is set then per $1\,us$ amount of hits excceeded given threshold (0xA0E1(23 -- 16)) (LSB corresponds to the input 0 of the start)
+% \item[Bit 23 -- 16] If one of the bits is set then per $100\,ns$ amount of hits excceeded given threshold (0xA0E1(31 -- 24)) (LSB corresponds to the input 0 of the start)
+% \end{description}
\end{description}
\item[bit 14] PT 4
\item[bit 31 -- 15] All 0
\end{description}
-\item[5 Currently empty]
-\item[13 -- 6 Start scalers]
-\item[21 -- 14 Veto scalers]
-\item[27 -- 22 TOF scalers]
-\item[33 -- 28 RPC scalers]
-\item[37 -- 34 PT scalers]
-\item[38 Start OR scaler]
-\item[39 Veto OR scaler]
-\item[43 -- 40 PT delayed scalers]
-\item[52 -- 44 Multiplicity scalers] The same order as for latches
-
-
+\item[5 Latches] All 0
+\item[6 - XX] The rest of the data is just copy of all R and RW registers (maximally up to the address 0xA0EF)
+ \begin{description}
+ \item[6] Register from 0xA000 address
+ \item[7] Register from 0xA001 address ....
+ \item[6+Numeber of read registers - 1] last read register (currently 0xA051)
+ \item[6+Numeber of read registers] first rw register (0xA0C0)
+ \item[6+Numeber of read registers + Number of read write registers] last rw register (currently 0xA0EC)
+ \end{description}
\end{description}
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