process(CLK)
begin
if rising_edge(CLK) then
+ dout1 <= ram(conv_integer(a1));
+ dout2 <= ram(conv_integer(a2));
if wr1 = '1' then
ram((conv_integer(a1))) <= din1;
+ dout1 <= din1;
end if;
- dout1 <= ram(conv_integer(a1));
- dout2 <= ram(conv_integer(a2));
+
end if;
end process;
if rising_edge(CLK) then
if wr1 = '1' then
ram((conv_integer(a1))) <= din1;
+ dout1 <= din1;
+ else
+ dout1 <= ram(conv_integer(a1));
end if;
- dout1 <= ram(conv_integer(a1));
dout2 <= ram(conv_integer(a2));
end if;
end process;
[Device]
Family=latticeecp2m
-PartType=LFE2M35E
-PartName=LFE2M35E-5F672C
+PartType=LFE2M20E
+PartName=LFE2M20E-5F256C
SpeedGrade=-5
-Package=FPBGA672
+Package=FPBGA256
OperatingCondition=COM
Status=P
CoreType=LPM
CoreStatus=Demo
CoreName=FIFO
-CoreRevision=4.3
+CoreRevision=4.4
ModuleName=lattice_ecp2m_fifo_18x1k
SourceFormat=Schematic/VHDL
ParameterFileVersion=1.0
-Date=11/04/2008
-Time=15:19:14
+Date=04/15/2009
+Time=19:42:20
[Parameters]
Verilog=0
PeMode=Static - Single Threshold
PeAssert=10
PeDeassert=12
-FullFlg=0
+FullFlg=1
PfMode=Static - Single Threshold
-PfAssert=508
+PfAssert=1020
PfDeassert=506
RDataCount=0
EnECC=0
-- VHDL netlist generated by SCUBA ispLever_v71_PROD_Build (58)
--- Module Version: 4.3
---/local/lattice/ispLever7.1/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 1024 -width 18 -depth 1024 -no_enable -pe -1 -pf -1 -e
+-- Module Version: 4.4
+--/opt/lattice/ispLEVER7.1/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 1024 -width 18 -depth 1024 -no_enable -pe -1 -pf 1020 -e
--- Tue Nov 4 15:19:14 2008
+-- Wed Apr 15 19:42:21 2009
library IEEE;
use IEEE.std_logic_1164.all;
Reset: in std_logic;
Q: out std_logic_vector(17 downto 0);
Empty: out std_logic;
- Full: out std_logic);
+ Full: out std_logic;
+ AlmostFull: out std_logic);
end lattice_ecp2m_fifo_18x1k;
architecture Structure of lattice_ecp2m_fifo_18x1k is
-- internal signal declarations
+ signal invout_2: std_logic;
signal invout_1: std_logic;
- signal invout_0: std_logic;
signal rden_i_inv: std_logic;
+ signal invout_0: std_logic;
+ signal r_nw_inv: std_logic;
+ signal r_nw: std_logic;
+ signal fcnt_en_inv: std_logic;
signal fcnt_en: std_logic;
signal empty_i: std_logic;
signal empty_d: std_logic;
signal co3: std_logic;
signal ifcount_10: std_logic;
signal co5: std_logic;
- signal cnt_con: std_logic;
signal co4: std_logic;
signal cmp_ci: std_logic;
signal rden_i: std_logic;
signal cmp_le_1: std_logic;
signal cmp_le_1_c: std_logic;
signal cmp_ci_1: std_logic;
- signal fcount_0: std_logic;
- signal fcount_1: std_logic;
signal co0_2: std_logic;
- signal fcount_2: std_logic;
- signal fcount_3: std_logic;
signal co1_2: std_logic;
- signal fcount_4: std_logic;
- signal fcount_5: std_logic;
signal co2_2: std_logic;
- signal fcount_6: std_logic;
- signal fcount_7: std_logic;
signal co3_2: std_logic;
signal wren_i: std_logic;
- signal fcount_8: std_logic;
- signal fcount_9: std_logic;
signal co4_2: std_logic;
signal wren_i_inv: std_logic;
- signal fcount_10: std_logic;
signal cmp_ge_d1: std_logic;
signal cmp_ge_d1_c: std_logic;
signal iwcount_0: std_logic;
signal co5_1: std_logic;
signal wcount_10: std_logic;
signal co4_3: std_logic;
- signal scuba_vhi: std_logic;
signal ircount_0: std_logic;
signal ircount_1: std_logic;
signal rcount_0: std_logic;
signal ircount_10: std_logic;
signal co5_2: std_logic;
signal rcount_10: std_logic;
- signal scuba_vlo: std_logic;
signal co4_4: std_logic;
+ signal cmp_ci_2: std_logic;
+ signal fcnt_en_inv_inv: std_logic;
+ signal cnt_con: std_logic;
+ signal fcount_0: std_logic;
+ signal fcount_1: std_logic;
+ signal co0_5: std_logic;
+ signal cnt_con_inv: std_logic;
+ signal fcount_2: std_logic;
+ signal fcount_3: std_logic;
+ signal co1_5: std_logic;
+ signal fcount_4: std_logic;
+ signal fcount_5: std_logic;
+ signal co2_5: std_logic;
+ signal fcount_6: std_logic;
+ signal fcount_7: std_logic;
+ signal co3_5: std_logic;
+ signal scuba_vhi: std_logic;
+ signal fcount_8: std_logic;
+ signal fcount_9: std_logic;
+ signal co4_5: std_logic;
+ signal fcount_10: std_logic;
+ signal af_d: std_logic;
+ signal af_d_c: std_logic;
+ signal scuba_vlo: std_logic;
-- local component declarations
component AGEB2
attribute REGMODE_A of pdp_ram_0_0_0 : label is "NOREG";
attribute DATA_WIDTH_B of pdp_ram_0_0_0 : label is "18";
attribute DATA_WIDTH_A of pdp_ram_0_0_0 : label is "18";
+ attribute GSR of FF_35 : label is "ENABLED";
attribute GSR of FF_34 : label is "ENABLED";
attribute GSR of FF_33 : label is "ENABLED";
attribute GSR of FF_32 : label is "ENABLED";
begin
-- component instantiation statements
- AND2_t3: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+ AND2_t4: AND2
+ port map (A=>WrEn, B=>invout_2, Z=>wren_i);
- INV_3: INV
- port map (A=>full_i, Z=>invout_1);
+ INV_8: INV
+ port map (A=>full_i, Z=>invout_2);
- AND2_t2: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+ AND2_t3: AND2
+ port map (A=>RdEn, B=>invout_1, Z=>rden_i);
- INV_2: INV
- port map (A=>empty_i, Z=>invout_0);
+ INV_7: INV
+ port map (A=>empty_i, Z=>invout_1);
- AND2_t1: AND2
+ AND2_t2: AND2
port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
- XOR2_t0: XOR2
+ XOR2_t1: XOR2
port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
- INV_1: INV
+ INV_6: INV
port map (A=>rden_i, Z=>rden_i_inv);
- INV_0: INV
+ INV_5: INV
port map (A=>wren_i, Z=>wren_i_inv);
LUT4_1: ROM16X1
port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
AD0=>full_i, DO0=>full_d);
+ AND2_t0: AND2
+ port map (A=>rden_i, B=>invout_0, Z=>r_nw);
+
+ INV_4: INV
+ port map (A=>wren_i, Z=>invout_0);
+
+ INV_3: INV
+ port map (A=>fcnt_en, Z=>fcnt_en_inv);
+
+ INV_2: INV
+ port map (A=>cnt_con, Z=>cnt_con_inv);
+
+ INV_1: INV
+ port map (A=>r_nw, Z=>r_nw_inv);
+
+ INV_0: INV
+ port map (A=>fcnt_en_inv, Z=>fcnt_en_inv_inv);
+
pdp_ram_0_0_0: DP16KB
-- synopsys translate_off
generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
DOB12=>Q(12), DOB13=>Q(13), DOB14=>Q(14), DOB15=>Q(15),
DOB16=>Q(16), DOB17=>Q(17));
- FF_34: FD1P3DX
+ FF_35: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_0);
- FF_33: FD1P3DX
+ FF_34: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_1);
- FF_32: FD1P3DX
+ FF_33: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_2);
- FF_31: FD1P3DX
+ FF_32: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_3);
- FF_30: FD1P3DX
+ FF_31: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_4);
- FF_29: FD1P3DX
+ FF_30: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_5);
- FF_28: FD1P3DX
+ FF_29: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_6);
- FF_27: FD1P3DX
+ FF_28: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_7);
- FF_26: FD1P3DX
+ FF_27: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_8);
- FF_25: FD1P3DX
+ FF_26: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_9);
- FF_24: FD1P3DX
+ FF_25: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_10);
- FF_23: FD1S3BX
+ FF_24: FD1S3BX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
- FF_22: FD1S3DX
+ FF_23: FD1S3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
- FF_21: FD1P3DX
+ FF_22: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_0);
- FF_20: FD1P3DX
+ FF_21: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_1);
- FF_19: FD1P3DX
+ FF_20: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_2);
- FF_18: FD1P3DX
+ FF_19: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_3);
- FF_17: FD1P3DX
+ FF_18: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_4);
- FF_16: FD1P3DX
+ FF_17: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_5);
- FF_15: FD1P3DX
+ FF_16: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_6);
- FF_14: FD1P3DX
+ FF_15: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_7);
- FF_13: FD1P3DX
+ FF_14: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_8);
- FF_12: FD1P3DX
+ FF_13: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_9);
- FF_11: FD1P3DX
+ FF_12: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_10);
- FF_10: FD1P3DX
+ FF_11: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_0);
- FF_9: FD1P3DX
+ FF_10: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_1);
- FF_8: FD1P3DX
+ FF_9: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_2);
- FF_7: FD1P3DX
+ FF_8: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_3);
- FF_6: FD1P3DX
+ FF_7: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_4);
- FF_5: FD1P3DX
+ FF_6: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_5);
- FF_4: FD1P3DX
+ FF_5: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_6);
- FF_3: FD1P3DX
+ FF_4: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_7);
- FF_2: FD1P3DX
+ FF_3: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_8);
- FF_1: FD1P3DX
+ FF_2: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_9);
- FF_0: FD1P3DX
+ FF_1: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_10);
+ FF_0: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>af_d, CK=>Clock, CD=>Reset, Q=>AlmostFull);
+
bdcnt_bctr_cia: FADD2B
port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con,
CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open);
port map (CI=>co4_3, PC0=>wcount_10, PC1=>scuba_vlo, CO=>co5_1,
NC0=>iwcount_10, NC1=>open);
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
r_ctr_cia: FADD2B
port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open,
port map (CI=>co3_4, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_4,
NC0=>ircount_8, NC1=>ircount_9);
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
r_ctr_5: CU2
port map (CI=>co4_4, PC0=>rcount_10, PC1=>scuba_vlo, CO=>co5_2,
NC0=>ircount_10, NC1=>open);
+ af_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open,
+ S1=>open);
+
+ af_cmp_0: AGEB2
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>fcnt_en_inv_inv,
+ B1=>cnt_con, CI=>cmp_ci_2, GE=>co0_5);
+
+ af_cmp_1: AGEB2
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con_inv,
+ B1=>scuba_vhi, CI=>co0_5, GE=>co1_5);
+
+ af_cmp_2: AGEB2
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>co1_5, GE=>co2_5);
+
+ af_cmp_3: AGEB2
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>co2_5, GE=>co3_5);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ af_cmp_4: AGEB2
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>co3_5, GE=>co4_5);
+
+ af_cmp_5: AGEB2
+ port map (A0=>fcount_10, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co4_5, GE=>af_d_c);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a2: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>af_d_c, COUT=>open, S0=>af_d, S1=>open);
+
Empty <= empty_i;
Full <= full_i;
end Structure;
--- /dev/null
+[Device]
+Family=latticeecp2m
+PartType=LFE2M20E
+PartName=LFE2M20E-5F256C
+SpeedGrade=-5
+Package=FPBGA256
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=4.1
+ModuleName=pll_in100_out200
+SourceFormat=Schematic/VHDL
+ParameterFileVersion=1.0
+Date=04/15/2009
+Time=17:19:05
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=None
+Order=None
+IO=0
+Type=ehxpllb
+mode=normal
+IFrq=100
+OFrq=200.000000
+KFrq=
+U_OFrq=200
+U_KFrq=50
+OP_Tol=0.0
+OK_Tol=0.0
+Div=1
+Mult=2
+Post=4
+SecD=2
+fb_mode=CLKOP
+PhaseDuty=Static
+DelayControl=AUTO_NO_DELAY
+External=DISABLED
+PCDR=0
+ClkOPBp=0
+EnCLKOS=0
+ClkOSBp=0
+Phase=0.0
+Duty=8
+DPD=50% Duty
+EnCLKOK=0
+ClkOKBp=0
+ClkRst=0
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v72_PROD_Build (44)
+-- Module Version: 4.2
+--/opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -n pll_in25_out100 -lang vhdl -synth synplify -arch ep5m00 -type pll -fin 25 -phase_cntl STATIC -fclkop 100 -fclkop_tol 0.0 -delay_cntl AUTO_NO_DELAY -fb_mode CLOCKTREE -extcap AUTO -noclkos -noclkok -norst -e
+
+-- Fri Mar 6 17:43:29 2009
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity pll_in25_out100 is
+ port (
+ CLK: in std_logic;
+ CLKOP: out std_logic;
+ LOCK: out std_logic);
+ attribute dont_touch : string;
+ attribute dont_touch of pll_in25_out100 : entity is "true";
+end pll_in25_out100;
+
+architecture Structure of pll_in25_out100 is
+
+ -- internal signal declarations
+ signal CLKOP_t: std_logic;
+ signal scuba_vlo: std_logic;
+ signal CLK_t: std_logic;
+
+ -- local component declarations
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component EPLLD
+ -- synopsys translate_off
+ generic (PLLCAP : in String; CLKOK_BYPASS : in String;
+ CLKOS_BYPASS : in String; CLKOP_BYPASS : in String;
+ DUTY : in Integer; PHASEADJ : in String;
+ PHASE_CNTL : in String; CLKOK_DIV : in Integer;
+ CLKFB_DIV : in Integer; CLKOP_DIV : in Integer;
+ CLKI_DIV : in Integer);
+ -- synopsys translate_on
+ port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic;
+ RSTK: in std_logic; DPAMODE: in std_logic; DRPAI3: in std_logic;
+ DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic;
+ DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic;
+ DFPAI0: in std_logic; CLKOP: out std_logic; CLKOS: out std_logic;
+ CLKOK: out std_logic; LOCK: out std_logic; CLKINTFB: out std_logic);
+ end component;
+ attribute PLLCAP : string;
+ attribute PLLTYPE : string;
+ attribute CLKOK_BYPASS : string;
+ attribute FREQUENCY_PIN_CLKOK : string;
+ attribute CLKOK_DIV : string;
+ attribute CLKOS_BYPASS : string;
+ attribute FREQUENCY_PIN_CLKOP : string;
+ attribute CLKOP_BYPASS : string;
+ attribute PHASE_CNTL : string;
+ attribute FDEL : string;
+ attribute DUTY : string;
+ attribute PHASEADJ : string;
+ attribute FREQUENCY_PIN_CLKI : string;
+ attribute CLKOP_DIV : string;
+ attribute CLKFB_DIV : string;
+ attribute CLKI_DIV : string;
+ attribute FIN : string;
+ attribute PLLCAP of PLLDInst_0 : label is "DISABLED";
+ attribute PLLTYPE of PLLDInst_0 : label is "GPLL";
+ attribute CLKOK_BYPASS of PLLDInst_0 : label is "DISABLED";
+ attribute FREQUENCY_PIN_CLKOK of PLLDInst_0 : label is "60.000000";
+ attribute CLKOK_DIV of PLLDInst_0 : label is "2";
+ attribute CLKOS_BYPASS of PLLDInst_0 : label is "DISABLED";
+ attribute FREQUENCY_PIN_CLKOP of PLLDInst_0 : label is "120.000000";
+ attribute CLKOP_BYPASS of PLLDInst_0 : label is "DISABLED";
+ attribute PHASE_CNTL of PLLDInst_0 : label is "STATIC";
+ attribute FDEL of PLLDInst_0 : label is "0";
+ attribute DUTY of PLLDInst_0 : label is "8";
+ attribute PHASEADJ of PLLDInst_0 : label is "0.0";
+ attribute FREQUENCY_PIN_CLKI of PLLDInst_0 : label is "30";
+ attribute CLKOP_DIV of PLLDInst_0 : label is "8";
+ attribute CLKFB_DIV of PLLDInst_0 : label is "4";
+ attribute CLKI_DIV of PLLDInst_0 : label is "1";
+ attribute FIN of PLLDInst_0 : label is "30";
+ attribute syn_keep : boolean;
+ attribute syn_noprune : boolean;
+ attribute syn_noprune of Structure : architecture is true;
+
+begin
+ -- component instantiation statements
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ PLLDInst_0: EPLLD
+ -- synopsys translate_off
+ generic map (PLLCAP=> "DISABLED", CLKOK_BYPASS=> "DISABLED",
+ CLKOK_DIV=> 2, CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED",
+ PHASE_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0", CLKOP_DIV=> 8,
+ CLKFB_DIV=> 4, CLKI_DIV=> 1)
+ -- synopsys translate_on
+ port map (CLKI=>CLK_t, CLKFB=>CLKOP_t, RST=>scuba_vlo,
+ RSTK=>scuba_vlo, DPAMODE=>scuba_vlo, DRPAI3=>scuba_vlo,
+ DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo,
+ DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo,
+ DFPAI0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open, CLKOK=>open,
+ LOCK=>LOCK, CLKINTFB=>open);
+
+ CLKOP <= CLKOP_t;
+ CLK_t <= CLK;
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of pll_in25_out100 is
+ for Structure
+ for all:VLO use entity ecp2m.VLO(V); end for;
+ for all:EPLLD use entity ecp2m.EPLLD(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
DATA_OUT <= dout(c_DATA_WIDTH - 1 downto 0);
PACKET_NUM_OUT <= dout(c_DATA_WIDTH + 1 downto c_DATA_WIDTH);
- gen_FIFO6 : if DEPTH = 6 generate
+-- gen_FIFO6 : if DEPTH = 6 generate
fifo:lattice_ecp2m_fifo_18x1k
port map (
Data => din,
Empty => EMPTY_OUT,
Full => FULL_OUT
);
- end generate;
+-- end generate;
-- gen_FIFO1 : if DEPTH = 1 generate
--- /dev/null
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+library work;
+use work.trb_net_std.all;
+
+
+entity trb_net_clock_generator is
+ generic(
+ FREQUENCY_IN : real := 100.0;
+ FREQUENCY_OUT : real := 300.0;
+ CLOCK_MULT : integer range 1 to 32 := 3;
+ CLOCK_DIV : integer range 1 to 32 := 1;
+ CLKIN_DIVIDE_BY_2 : boolean := true;
+ CLKIN_PERIOD : real := 20.0
+ );
+ port(
+ RESET : in std_logic;
+ CLK_IN : in std_logic;
+ CLK_OUT : out std_logic;
+ LOCKED : out std_logic
+ );
+
+end entity;
+
+
+architecture trb_net_clock_generator_arch of trb_net_clock_generator is
+
+ component pll_in100_out200 is
+ port (
+ CLK: in std_logic;
+ CLKOP: out std_logic;
+ LOCK: out std_logic);
+ end component;
+
+ signal FB_CLK, CLK0_Out, CLKFX : std_logic;
+begin
+
+ gen_pll100_200 : if FREQUENCY_IN = 100.0 and FREQUENCY_OUT = 200.0 generate
+ THE_PLL : pll_in100_out200
+ port map(
+ CLK => CLK_IN,
+ CLKOP => CLK_OUT,
+ LOCK => LOCKED
+ );
+ end generate;
+
+end architecture;
\ No newline at end of file
# end user to adjust the PCSC quad to the final design requirements.
DEVICE_NAME "LFE2M100E"
-PROTOCOL "G8B10B"
-CH0_MODE "SINGLE"
-CH1_MODE "DISABLE"
-CH2_MODE "DISABLE"
-CH3_MODE "DISABLE"
-PLL_SRC "CORE_TXREFCLK"
-DATARANGE "LOW"
-CH0_CDR_SRC "CORE_RXREFCLK"
-CH0_DATA_WIDTH "8"
-CH0_REFCK_MULT "10X"
+PROTOCOL "G8B10B"
+CH0_MODE "SINGLE"
+CH1_MODE "DISABLE"
+CH2_MODE "DISABLE"
+CH3_MODE "DISABLE"
+PLL_SRC "CORE_TXREFCLK"
+DATARANGE "LOW"
+CH0_CDR_SRC "CORE_RXREFCLK"
+CH0_DATA_WIDTH "8"
+CH0_REFCK_MULT "10X"
#REFCLK_RATE 25.0
#FPGAINTCLK_RATE 25.0
-CH0_TDRV_AMP "0"
-CH0_TX_PRE "DISABLE"
-CH0_RTERM_TX "50"
-CH0_RX_EQ "DISABLE"
-CH0_RTERM_RX "50"
-CH0_RX_DCC "AC"
-LOS_THRESHOLD "0"
-PLL_TERM "50"
-PLL_DCC "AC"
-PLL_LOL_SET "0"
-CH0_TX_SB "NORMAL"
-CH0_RX_SB "NORMAL"
-CH0_8B10B "NORMAL"
-COMMA_A "1100000101"
-COMMA_B "0011111010"
-COMMA_M "1111111111"
-CH0_COMMA_ALIGN "AUTO"
-CH0_CTC_BYP "BYPASS"
-CC_MATCH1 "0000000000"
-CC_MATCH2 "0000000000"
-CC_MATCH3 "0100011100"
-CC_MATCH4 "0100011100"
-CC_MATCH_MODE "MATCH_4"
-CC_MIN_IPG "0"
-CCHMARK "4"
-CCLMARK "4"
+CH0_TDRV_AMP "0"
+CH0_TX_PRE "DISABLE"
+CH0_RTERM_TX "50"
+CH0_RX_EQ "DISABLE"
+CH0_RTERM_RX "50"
+CH0_RX_DCC "AC"
+LOS_THRESHOLD "0"
+PLL_TERM "50"
+PLL_DCC "AC"
+PLL_LOL_SET "0"
+CH0_TX_SB "NORMAL"
+CH0_RX_SB "NORMAL"
+CH0_8B10B "NORMAL"
+COMMA_A "1100000101"
+COMMA_B "0011111010"
+COMMA_M "1111111111"
+CH0_COMMA_ALIGN "AUTO"
+CH0_CTC_BYP "BYPASS"
+CC_MATCH1 "0000000000"
+CC_MATCH2 "0000000000"
+CC_MATCH3 "0100011100"
+CC_MATCH4 "0100011100"
+CC_MATCH_MODE "MATCH_4"
+CC_MIN_IPG "0"
+CCHMARK "4"
+CCLMARK "4"
OS_REFCK2CORE "0"
OS_PLLQCLKPORTS "0"
OS_INT_ALL "0"
end if;
when others => NEXT_STATE <= QRST;
end case;
+ if ( (sfp_missing_in = '1') or (sfp_los_in = '1')) and CURRENT_STATE /= QRST then
+ NEXT_STATE <= SLEEP; -- wait for SFP present signal
+ next_ce_tctr <= '1';
+ next_rst_tctr <= '1';
+ next_lane_rst <= '1';
+ end if;
end process;
THE_DECODE_PROC: process( CURRENT_STATE, timing_ctr )
D_OUT : out std_logic_vector(WIDTH-1 downto 0) --Data output
);
end component;
-
- component lattice_ecp2m_fifo_8x8_dualport
- port (
- Data: in std_logic_vector(7 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(7 downto 0);
- Empty: out std_logic;
- Full: out std_logic
- );
- end component;
-
- component lattice_ecp2m_fifo_16x8_dualport
- port (
- Data: in std_logic_vector(15 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(15 downto 0);
- Empty: out std_logic;
- Full: out std_logic
+--
+-- component lattice_ecp2m_fifo_8x8_dualport
+-- port (
+-- Data: in std_logic_vector(7 downto 0);
+-- WrClock: in std_logic;
+-- RdClock: in std_logic;
+-- WrEn: in std_logic;
+-- RdEn: in std_logic;
+-- Reset: in std_logic;
+-- RPReset: in std_logic;
+-- Q: out std_logic_vector(7 downto 0);
+-- Empty: out std_logic;
+-- Full: out std_logic
+-- );
+-- end component;
+--
+-- component lattice_ecp2m_fifo_16x8_dualport
+-- port (
+-- Data: in std_logic_vector(15 downto 0);
+-- WrClock: in std_logic;
+-- RdClock: in std_logic;
+-- WrEn: in std_logic;
+-- RdEn: in std_logic;
+-- Reset: in std_logic;
+-- RPReset: in std_logic;
+-- Q: out std_logic_vector(15 downto 0);
+-- Empty: out std_logic;
+-- Full: out std_logic
+-- );
+-- end component;
+
+ component trb_net_fifo_16bit_bram_dualport is
+ generic(
+ USE_STATUS_FLAGS : integer := c_YES
+ );
+ port( read_clock_in : in std_logic;
+ write_clock_in : in std_logic;
+ read_enable_in : in std_logic;
+ write_enable_in : in std_logic;
+ fifo_gsr_in : in std_logic;
+ write_data_in : in std_logic_vector(17 downto 0);
+ read_data_out : out std_logic_vector(17 downto 0);
+ full_out : out std_logic;
+ empty_out : out std_logic;
+ fifostatus_out : out std_logic_vector(3 downto 0);
+ valid_read_out : out std_logic;
+ almost_empty_out : out std_logic;
+ almost_full_out : out std_logic
);
end component;
signal tx_allow : std_logic;
signal rx_data_reg : std_logic_vector(8-1 downto 0);
+ signal buf_rx_data_reg : std_logic_vector(8-1 downto 0);
signal buf_rx_data : std_logic_vector(8-1 downto 0);
signal buf_rx_k : std_logic;
signal rx_fifo_write_en : std_logic;
signal is_idle_word : std_logic;
signal rx_starting : std_logic;
signal rx_allow : std_logic;
+ signal rx_allow_qrx : std_logic;
signal sd_q : std_logic;
signal last_rx_fifo_read_en : std_logic;
signal last_rx_fifo_empty : std_logic;
+ signal last_last_rx_fifo_read_en : std_logic;
+ signal last_last_rx_fifo_empty : std_logic;
+ signal last_rx_fifo_dout : std_logic_vector(7 downto 0);
+
signal buf_med_dataready_out : std_logic;
signal buf_med_read_out : std_logic;
begin
+ --ff_rxfullclk <= clk_25;
+ --ff_rxfullclk <= ff_txfullclk;
+
THE_SERDES: serdes_fot_0
port map(
core_txrefclk => CLK_25,
--TX Control 25
---------------
- THE_TX_FIFO: lattice_ecp2m_fifo_16x8_dualport
+
+ THE_TX_FIFO: trb_net_fifo_16bit_bram_dualport
+ generic map(
+ USE_STATUS_FLAGS => c_NO
+ )
port map(
- Data => tx_fifo_data_in(16-1 downto 0),
- WrClock => CLK,
- RdClock => ff_txfullclk,
- WrEn => tx_fifo_write_en,
- RdEn => tx_fifo_read_en,
- Reset => fifo_reset,
- RPReset => fifo_reset,
- Q => tx_fifo_dout(15 downto 0),
- Empty => tx_fifo_empty,
- Full => tx_fifo_full
+ read_clock_in => ff_txfullclk,
+ write_clock_in => CLK,
+ read_enable_in => tx_fifo_read_en,
+ write_enable_in => tx_fifo_write_en,
+ fifo_gsr_in => fifo_reset,
+ write_data_in => "00" & tx_fifo_data_in(15 downto 0),
+ read_data_out(15 downto 0) => tx_fifo_dout(15 downto 0),
+ full_out => tx_fifo_full,
+ empty_out => tx_fifo_empty
);
+-- THE_TX_FIFO: lattice_ecp2m_fifo_16x8_dualport
+-- port map(
+-- Data => tx_fifo_data_in(16-1 downto 0),
+-- WrClock => CLK,
+-- RdClock => ff_txfullclk,
+-- WrEn => tx_fifo_write_en,
+-- RdEn => tx_fifo_read_en,
+-- Reset => fifo_reset,
+-- RPReset => fifo_reset,
+-- Q => tx_fifo_dout(15 downto 0),
+-- Empty => tx_fifo_empty,
+-- Full => tx_fifo_full
+-- );
+
THE_READ_TX_FIFO_PROC: process( ff_txfullclk )
begin
if( rising_edge(ff_txfullclk) ) then
end if;
end process;
- fifo_reset <= reset or quad_rst or not rx_allow;
+ fifo_reset <= reset or quad_rst or not rx_allow_qrx;
--RX Control (25)
---------------------
- THE_RX_FIFO: lattice_ecp2m_fifo_8x8_dualport
+ THE_FIFO_RX: trb_net_fifo_16bit_bram_dualport
+ generic map(
+ USE_STATUS_FLAGS => c_NO
+ )
port map(
- Data => rx_data_reg(7 downto 0),
- WrClock => ff_rxfullclk,
- RdClock => clk,
- WrEn => rx_fifo_write_en,
- RdEn => rx_fifo_read_en,
- Reset => fifo_reset,
- RPReset => fifo_reset,
- Q => rx_fifo_dout(7 downto 0),
- Empty => rx_fifo_empty,
- Full => rx_fifo_full
- );
+ read_clock_in => clk,
+ write_clock_in => ff_rxfullclk,
+ read_enable_in => rx_fifo_read_en,
+ write_enable_in => rx_fifo_write_en,
+ fifo_gsr_in => fifo_reset,
+ write_data_in => "00" & x"00" & rx_data_reg(7 downto 0),
+ read_data_out(7 downto 0) => rx_fifo_dout,
+ full_out => rx_fifo_full,
+ empty_out => rx_fifo_empty
+ );
+
+
+-- THE_RX_FIFO: lattice_ecp2m_fifo_8x8_dualport
+-- port map(
+-- Data => rx_data_reg(7 downto 0),
+-- WrClock => ff_rxfullclk,
+-- RdClock => clk,
+-- WrEn => rx_fifo_write_en,
+-- RdEn => rx_fifo_read_en,
+-- Reset => fifo_reset,
+-- RPReset => fifo_reset,
+-- Q => rx_fifo_dout(7 downto 0),
+-- Empty => rx_fifo_empty,
+-- Full => rx_fifo_full
+-- );
THE_WRITE_RX_FIFO_PROC: process( ff_rxfullclk )
begin
if( rising_edge(ff_rxfullclk) ) then
buf_rx_data(7 downto 0) <= rx_data(7 downto 0);
buf_rx_k <= rx_k;
- if( (reset = '1') or (rx_allow = '0') ) then
+ if( (reset = '1') or (rx_allow_qrx = '0') ) then
rx_fifo_write_en <= '0';
is_idle_word <= '1';
rx_starting <= '1';
else
rx_data_reg(7 downto 0) <= buf_rx_data(7 downto 0);
- if( rx_allow = '1' ) then
- if( (buf_rx_k = '0') and (is_idle_word = '0') and (rx_starting = '0') ) then
- rx_fifo_write_en <= '1';
- else
- rx_fifo_write_en <= '0';
- end if;
- if ( buf_rx_k = '1' ) then
- is_idle_word <= '1';
- rx_starting <= '0';
- elsif( (buf_rx_k = '0') and (is_idle_word = '1') ) then
- is_idle_word <= '0';
- end if;
+ if( (buf_rx_k = '0') and (is_idle_word = '0') and (rx_starting = '0') ) then
+ rx_fifo_write_en <= '1';
+ else
+ rx_fifo_write_en <= '0';
+ end if;
+ if ( buf_rx_k = '1' ) then
+ is_idle_word <= '1';
+ rx_starting <= '0';
+ elsif( (buf_rx_k = '0') and (is_idle_word = '1') ) then
+ is_idle_word <= '0';
end if;
end if;
end if;
last_rx_fifo_read_en <= '0';
else
last_rx_fifo_read_en <= rx_fifo_read_en;
+ last_rx_fifo_empty <= rx_fifo_empty;
+ last_last_rx_fifo_read_en <= last_rx_fifo_read_en;
+ last_last_rx_fifo_empty <= last_rx_fifo_empty;
+ last_rx_fifo_dout <= rx_fifo_dout;
buf_med_dataready_out <= '0';
- if( (last_rx_fifo_empty = '0') and (last_rx_fifo_read_en = '1') ) then
+ if( (last_last_rx_fifo_empty = '0') and (last_last_rx_fifo_read_en = '1') ) then
if( byte_select = '1' ) then
- buf_MED_DATA_OUT(15 downto 0) <= rx_fifo_dout(7 downto 0)
+ buf_MED_DATA_OUT(15 downto 0) <= last_rx_fifo_dout(7 downto 0)
& buf_MED_DATA_OUT(7 downto 0);
buf_MED_DATAREADY_OUT <= '1';
else
- buf_MED_DATA_OUT(15 downto 0) <= x"00" & rx_fifo_dout(7 downto 0);
+ buf_MED_DATA_OUT(15 downto 0) <= x"00" & last_rx_fifo_dout(7 downto 0);
end if;
byte_select <= not byte_select;
end if;
end if;
end process;
- rx_fifo_read_en <= rx_allow;
+ rx_fifo_read_en <= rx_allow and not rx_fifo_empty;
MED_DATA_OUT(15 downto 0) <= buf_MED_DATA_OUT(15 downto 0);
MED_DATAREADY_OUT <= buf_MED_DATAREADY_OUT;
MED_PACKET_NUM_OUT <= rx_counter;
THE_RX_PACKETS_PROC: process( clk )
begin
if( rising_edge(clk) ) then
- last_rx_fifo_empty <= rx_fifo_empty;
if( (reset = '1') or (rx_allow = '0') ) then
rx_counter <= c_H0;
else
D_OUT(0) => sd_q
);
+ THE_SFP_STATUS_SYNC: signal_sync
+ generic map(
+ DEPTH => 2,
+ WIDTH => 1
+ )
+ port map(
+ RESET => RESET,
+ D_IN(0) => rx_allow,
+ CLK0 => ff_rxfullclk,
+ CLK1 => ff_rxfullclk,
+ D_OUT(0) => rx_allow_qrx
+ );
+
--LED Signals
---------------------
THE_TX_RX_LED_PROC: process( clk )
STAT_OP(15 downto 12) <= FSM_STAT_OP(15 downto 12);
STAT_DEBUG(31 downto 0) <= FSM_STAT_DEBUG(31 downto 0);
- STAT_DEBUG(39 downto 32) <= rx_data_reg(7 downto 0);
+ STAT_DEBUG(39 downto 32) <= buf_rx_data_reg(7 downto 0);
STAT_DEBUG(40) <= rx_fifo_write_en;
- STAT_DEBUG(63 downto 41) <= (others => '0');
-
-
+ STAT_DEBUG(48 downto 41) <= last_rx_fifo_dout;
+ STAT_DEBUG(63 downto 49) <= (others => '0');
+
+ PROC_LED : process(CLK_25)
+ begin
+ if rising_edge(CLK_25) then
+ buf_rx_data_reg <= rx_data_reg;
+ end if;
+ end process;
THE_SFP_LSM: trb_net16_lsm_sfp
port map(
);
end component;
+ component trb_net_fifo_16bit_bram_dualport is
+ generic(
+ USE_STATUS_FLAGS : integer := c_YES
+ );
+ port( read_clock_in : in std_logic;
+ write_clock_in : in std_logic;
+ read_enable_in : in std_logic;
+ write_enable_in : in std_logic;
+ fifo_gsr_in : in std_logic;
+ write_data_in : in std_logic_vector(17 downto 0);
+ read_data_out : out std_logic_vector(17 downto 0);
+ full_out : out std_logic;
+ empty_out : out std_logic;
+ fifostatus_out : out std_logic_vector(3 downto 0);
+ valid_read_out : out std_logic;
+ almost_empty_out : out std_logic;
+ almost_full_out : out std_logic
+ );
+ end component;
+
type link_error_t is array(0 to 3) of std_logic_vector(7 downto 0);
signal link_error : link_error_t;
signal link_error_q: link_error_t;
signal link_ok : std_logic_vector(3 downto 0);
signal tx_data : std_logic_vector(8*4-1 downto 0);
signal rx_data : std_logic_vector(8*4-1 downto 0);
+ signal buf_rx_data_reg : std_logic_vector(8*4-1 downto 0);
signal ff_rxfullclk : std_logic_vector(3 downto 0);
signal ff_txfullclk : std_logic;
signal rx_k : std_logic_vector(3 downto 0);
signal is_idle_word : std_logic_vector(3 downto 0);
signal rx_starting : std_logic_vector(3 downto 0);
signal rx_allow : std_logic_vector(3 downto 0);
+ signal rx_allow_qrx : std_logic_vector(3 downto 0);
signal sd_q : std_logic_vector(3 downto 0);
signal last_rx_fifo_read_en : std_logic_vector(3 downto 0);
signal last_rx_fifo_empty : std_logic_vector(3 downto 0);
+ signal last_last_rx_fifo_read_en : std_logic_vector(3 downto 0);
+ signal last_last_rx_fifo_empty : std_logic_vector(3 downto 0);
+ signal last_rx_fifo_dout : std_logic_vector(4*8-1 downto 0);
signal buf_med_dataready_out : std_logic_vector(3 downto 0);
signal buf_med_read_out : std_logic_vector(3 downto 0);
gen_tx_fifos : for i in 0 to 3 generate
- THE_TX_FIFO: lattice_ecp2m_fifo_16x8_dualport
+ THE_TX_FIFO : trb_net_fifo_16bit_bram_dualport
+ generic map(
+ USE_STATUS_FLAGS => c_NO
+ )
port map(
- Data => tx_fifo_data_in((i+1)*16-1 downto i*16),
- WrClock => CLK,
- RdClock => ff_txfullclk,
- WrEn => tx_fifo_write_en(i),
- RdEn => tx_fifo_read_en(i),
- Reset => fifo_reset(i),
- RPReset => fifo_reset(i),
- Q => tx_fifo_dout((i+1)*16-1 downto i*16),
- Empty => tx_fifo_empty(i),
- Full => tx_fifo_full(i)
+ read_clock_in => ff_txfullclk,
+ write_clock_in => CLK,
+ read_enable_in => tx_fifo_read_en(i),
+ write_enable_in => tx_fifo_write_en(i),
+ fifo_gsr_in => fifo_reset(i),
+ write_data_in => "00" & tx_fifo_data_in((i+1)*16-1 downto i*16),
+ read_data_out(15 downto 0) => tx_fifo_dout((i+1)*16-1 downto i*16),
+ full_out => tx_fifo_full(i),
+ empty_out => tx_fifo_empty(i)
);
+-- THE_TX_FIFO: lattice_ecp2m_fifo_16x8_dualport
+-- port map(
+-- Data => tx_fifo_data_in((i+1)*16-1 downto i*16),
+-- WrClock => CLK,
+-- RdClock => ff_txfullclk,
+-- WrEn => tx_fifo_write_en(i),
+-- RdEn => tx_fifo_read_en(i),
+-- Reset => fifo_reset(i),
+-- RPReset => fifo_reset(i),
+-- Q => tx_fifo_dout((i+1)*16-1 downto i*16),
+-- Empty => tx_fifo_empty(i),
+-- Full => tx_fifo_full(i)
+-- );
+
THE_READ_TX_FIFO_PROC: process( ff_txfullclk )
begin
if( rising_edge(ff_txfullclk) ) then
end if;
end process;
- fifo_reset(i) <= reset or quad_rst(0);
+ fifo_reset(i) <= reset or quad_rst(0) or not rx_allow_qrx(i);
--RX Control (25)
---------------------
- THE_RX_FIFO: lattice_ecp2m_fifo_8x8_dualport
+
+
+ THE_FIFO_RX: trb_net_fifo_16bit_bram_dualport
+ generic map(
+ USE_STATUS_FLAGS => c_NO
+ )
port map(
- Data => rx_data_reg((i+1)*8-1 downto i*8),
- WrClock => ff_rxfullclk(i),
- RdClock => clk,
- WrEn => rx_fifo_write_en(i),
- RdEn => rx_fifo_read_en(i),
- Reset => fifo_reset(i),
- RPReset => fifo_reset(i),
- Q => rx_fifo_dout((i+1)*8-1 downto i*8),
- Empty => rx_fifo_empty(i),
- Full => rx_fifo_full(i)
- );
+ read_clock_in => clk,
+ write_clock_in => ff_rxfullclk(i),
+ read_enable_in => rx_fifo_read_en(i),
+ write_enable_in => rx_fifo_write_en(i),
+ fifo_gsr_in => fifo_reset(i),
+ write_data_in => "00" & x"00" & rx_data_reg((i+1)*8-1 downto i*8),
+ read_data_out(7 downto 0) => rx_fifo_dout((i+1)*8-1 downto i*8),
+ full_out => rx_fifo_full(i),
+ empty_out => rx_fifo_empty(i)
+ );
+
+
+-- THE_RX_FIFO: lattice_ecp2m_fifo_8x8_dualport
+-- port map(
+-- Data => rx_data_reg((i+1)*8-1 downto i*8),
+-- WrClock => ff_rxfullclk(i),
+-- RdClock => clk,
+-- WrEn => rx_fifo_write_en(i),
+-- RdEn => rx_fifo_read_en(i),
+-- Reset => fifo_reset(i),
+-- RPReset => fifo_reset(i),
+-- Q => rx_fifo_dout((i+1)*8-1 downto i*8),
+-- Empty => rx_fifo_empty(i),
+-- Full => rx_fifo_full(i)
+-- );
THE_WRITE_RX_FIFO_PROC: process( ff_rxfullclk )
begin
if( rising_edge(ff_rxfullclk(i)) ) then
buf_rx_data((i+1)*8-1 downto i*8) <= rx_data((i+1)*8-1 downto i*8);
buf_rx_k(i) <= rx_k(i);
- if( (reset = '1') or (rx_allow(i) = '0') ) then
+ if( (reset = '1') or (rx_allow_qrx(i) = '0') ) then
rx_fifo_write_en(i) <= '0';
is_idle_word(i) <= '1';
rx_starting(i) <= '1';
else
rx_data_reg((i+1)*8-1 downto i*8) <= buf_rx_data((i+1)*8-1 downto i*8);
- if( rx_allow(i) = '1' ) then
- if( (buf_rx_k(i) = '0') and (is_idle_word(i) = '0') and (rx_starting(i) = '0') ) then
- rx_fifo_write_en(i) <= '1';
- else
- rx_fifo_write_en(i) <= '0';
- end if;
- if ( buf_rx_k(i) = '1' ) then
- is_idle_word(i) <= '1';
- rx_starting(i) <= '0';
- elsif( (buf_rx_k(i) = '0') and (is_idle_word(i) = '1') ) then
- is_idle_word(i) <= '0';
- end if;
+ if( (buf_rx_k(i) = '0') and (is_idle_word(i) = '0') and (rx_starting(i) = '0') ) then
+ rx_fifo_write_en(i) <= '1';
+ else
+ rx_fifo_write_en(i) <= '0';
+ end if;
+ if ( buf_rx_k(i) = '1' ) then
+ is_idle_word(i) <= '1';
+ rx_starting(i) <= '0';
+ elsif( (buf_rx_k(i) = '0') and (is_idle_word(i) = '1') ) then
+ is_idle_word(i) <= '0';
end if;
end if;
end if;
byte_select(i) <= '0';
last_rx_fifo_read_en(i) <= '0';
else
- last_rx_fifo_read_en(i) <= rx_fifo_read_en(i);
- buf_med_dataready_out(i) <= '0';
- if( (last_rx_fifo_empty(i) = '0') and (last_rx_fifo_read_en(i) = '1') ) then
+ last_rx_fifo_read_en(i) <= rx_fifo_read_en(i);
+ last_rx_fifo_empty(i) <= rx_fifo_empty(i);
+ last_last_rx_fifo_read_en(i) <= last_rx_fifo_read_en(i);
+ last_last_rx_fifo_empty(i) <= last_rx_fifo_empty(i);
+ last_rx_fifo_dout(i*8+7 downto i*8) <= rx_fifo_dout(i*8+7 downto i*8);
+ buf_med_dataready_out(i) <= '0';
+ if( (last_last_rx_fifo_empty(i) = '0') and (last_last_rx_fifo_read_en(i) = '1') ) then
if( byte_select(i) = '1' ) then
- buf_MED_DATA_OUT((i+1)*16-1 downto i*16) <= rx_fifo_dout((i+1)*8-1 downto i*8)
+ buf_MED_DATA_OUT((i+1)*16-1 downto i*16) <= last_rx_fifo_dout((i+1)*8-1 downto i*8)
& buf_MED_DATA_OUT(i*16+7 downto i*16);
buf_MED_DATAREADY_OUT(i) <= '1';
else
- buf_MED_DATA_OUT((i+1)*16-1 downto i*16) <= x"00" & rx_fifo_dout((i+1)*8-1 downto i*8);
+ buf_MED_DATA_OUT((i+1)*16-1 downto i*16) <= x"00" & last_rx_fifo_dout((i+1)*8-1 downto i*8);
end if;
byte_select(i) <= not byte_select(i);
end if;
end if;
end process;
- rx_fifo_read_en(i) <= tx_allow(i);
+ rx_fifo_read_en(i) <= rx_allow(i) and not rx_fifo_empty(i);
MED_DATA_OUT((i+1)*16-1 downto i*16) <= buf_MED_DATA_OUT((i+1)*16-1 downto i*16);
MED_DATAREADY_OUT(i) <= buf_MED_DATAREADY_OUT(i);
MED_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= rx_counter((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH);
THE_RX_PACKETS_PROC: process( clk )
begin
if( rising_edge(clk) ) then
- last_rx_fifo_empty(i) <= rx_fifo_empty(i);
if( (reset = '1') or (rx_allow(i) = '0') ) then
rx_counter(i*3+2 downto i*3) <= c_H0;
else
D_OUT(0) => sd_q(i)
);
+ THE_SFP_STATUS_SYNC: signal_sync
+ generic map(
+ DEPTH => 2,
+ WIDTH => 1
+ )
+ port map(
+ RESET => RESET,
+ D_IN(0) => rx_allow(i),
+ CLK0 => ff_rxfullclk(i),
+ CLK1 => ff_rxfullclk(i),
+ D_OUT(0) => rx_allow_qrx(i)
+ );
+
--LED Signals
---------------------
THE_TX_RX_LED_PROC: process( clk )
STAT_OP(i*16+15 downto i*16+12) <= FSM_STAT_OP(i*16+15 downto i*16+12);
STAT_DEBUG(i*64+31 downto i*64+0) <= FSM_STAT_DEBUG(i*32+31 downto i*32);
- STAT_DEBUG(i*64+39 downto i*64+32) <= rx_data_reg(i*8+7 downto i*8);
+ STAT_DEBUG(i*64+39 downto i*64+32) <= buf_rx_data_reg(i*8+7 downto i*8);
STAT_DEBUG(i*64+40) <= rx_fifo_write_en(i);
- STAT_DEBUG(i*64+63 downto i*64+41) <= (others => '0');
+ STAT_DEBUG(i*64+48 downto i*64+41) <= last_rx_fifo_dout(i*8+7 downto i*8);
+ STAT_DEBUG(i*64+63 downto i*64+49) <= (others => '0');
+
+ PROC_LED : process(CLK_25)
+ begin
+ if rising_edge(CLK_25) then
+ buf_rx_data_reg <= rx_data_reg;
+ end if;
+ end process;
end generate;
BLOCK RESETPATHS ;\r
BLOCK ASYNCPATHS ;\r
\r
-#########################################\r
-# Constraints\r
-#########################################\r
- IOBUF ALLPORTS IO_TYPE=LVTTL33 PULLMODE=DOWN ;\r
-\r
- FREQUENCY PORT CLK100_P 100.000000 MHz ;\r
- FREQUENCY PORT ADO_CLK_OUT_P 100.000000 MHz ;\r
- FREQUENCY PORT CLK_F1_TO_F2_P 100.000000 MHz ;\r
- FREQUENCY PORT CLK_F2_TO_F1_P 100.000000 MHz ;\r
- FREQUENCY PORT FROM_TRB_TO_ADDON_CLK_P 100.000000 MHz ;\r
-\r
-\r
- LOCATE COMP "THE_HUB2/THE_MEDIA_INTERFACE_1/THE_SERDES/PCSC_INST" SITE "ULPCS" ;\r
- LOCATE COMP "THE_HUB2/THE_MEDIA_INTERFACE_2/THE_SERDES/PCSC_INST" SITE "LLPCS" ;\r
- LOCATE COMP "THE_HUB2/THE_MEDIA_INTERFACE_3/THE_SERDES/PCSC_INST" SITE "LRPCS" ;\r
- LOCATE COMP "THE_HUB2/THE_MEDIA_INTERFACE_4/THE_SERDES/PCSC_INST" SITE "URPCS" ;\r
-\r
#########################################\r
# Clocks & Reset\r
#########################################\r
\r
LOCATE COMP "CLK100_P" SITE "M29";\r
# LOCATE COMP "CLK100_N" SITE "M30";\r
+ IOBUF PORT "CLK100_P" IO_TYPE=LVDS25 PULLMODE=NONE ;\r
\r
LOCATE COMP "CLK_F2_TO_F1_P" SITE "N1";\r
# LOCATE COMP "CLK_F2_TO_F1_N" SITE "P1";\r
+ IOBUF PORT "CLK_F2_TO_F1_P" IO_TYPE=LVDS25 PULLMODE=NONE ;\r
+\r
LOCATE COMP "CLK_F1_TO_F2_P" SITE "M1";\r
# LOCATE COMP "CLK_F1_TO_F2_N" SITE "N2";\r
+ IOBUF PORT "CLK_F1_TO_F2_P" IO_TYPE=LVDS25 PULLMODE=NONE ;\r
+\r
+\r
\r
LOCATE COMP "ADO_CLK_OUT_P" SITE "L3";\r
# LOCATE COMP "ADO_CLK_OUT_N" SITE "L2";\r
+ IOBUF PORT "ADO_CLK_OUT_P" IO_TYPE=LVDS25 PULLMODE=NONE ;\r
+\r
LOCATE COMP "FROM_TRB_TO_ADDON_CLK_P" SITE "P5";\r
# LOCATE COMP "FROM_TRB_TO_ADDON_CLK_N" SITE "P4";\r
+ IOBUF PORT "FROM_TRB_TO_ADDON_CLK_P" IO_TYPE=LVDS25 PULLMODE=NONE ;\r
+\r
\r
- LOCATE COMP "RESET" SITE "B17";\r
- LOCATE COMP "SUPPL_RESET" SITE "A17";\r
+ LOCATE COMP "RESET_N" SITE "B17";\r
+ LOCATE COMP "SUPPL_RESET_N" SITE "A17";\r
\r
#########################################\r
# Connection to TRB\r
#########################################\r
# Optical Link Control Signals\r
# Names changed to be consistent to internal serdes numbers\r
-# Be aware that the numbering does not follow the location on the board for signals 9 to 12!\r
+# Be aware that the numbering does not follow the location on the board, but the internal connection must be reversed!\r
#########################################\r
LOCATE COMP "TX_DIS_1" SITE "U4";\r
LOCATE COMP "TX_DIS_2" SITE "U1";\r
LOCATE COMP "TX_DIS_6" SITE "AG8";\r
LOCATE COMP "TX_DIS_7" SITE "AD9";\r
LOCATE COMP "TX_DIS_8" SITE "AE10";\r
- LOCATE COMP "TX_DIS_12" SITE "AE11";\r
- LOCATE COMP "TX_DIS_11" SITE "AE18";\r
- LOCATE COMP "TX_DIS_10" SITE "AF19";\r
- LOCATE COMP "TX_DIS_9" SITE "AC19";\r
+ LOCATE COMP "TX_DIS_9" SITE "AE11";\r
+ LOCATE COMP "TX_DIS_10" SITE "AE18";\r
+ LOCATE COMP "TX_DIS_11" SITE "AF19";\r
+ LOCATE COMP "TX_DIS_12" SITE "AC19";\r
LOCATE COMP "TX_DIS_13" SITE "AC20";\r
LOCATE COMP "TX_DIS_14" SITE "AG21";\r
LOCATE COMP "TX_DIS_15" SITE "AC23";\r
LOCATE COMP "TX_FAULT_6" SITE "AE8";\r
LOCATE COMP "TX_FAULT_7" SITE "AG9";\r
LOCATE COMP "TX_FAULT_8" SITE "AD10";\r
- LOCATE COMP "TX_FAULT_12" SITE "AD11";\r
- LOCATE COMP "TX_FAULT_11" SITE "AB18";\r
- LOCATE COMP "TX_FAULT_10" SITE "AD18";\r
- LOCATE COMP "TX_FAULT_9" SITE "AG20";\r
+ LOCATE COMP "TX_FAULT_9" SITE "AD11";\r
+ LOCATE COMP "TX_FAULT_10" SITE "AB18";\r
+ LOCATE COMP "TX_FAULT_11" SITE "AD18";\r
+ LOCATE COMP "TX_FAULT_12" SITE "AG20";\r
LOCATE COMP "TX_FAULT_13" SITE "AE20";\r
LOCATE COMP "TX_FAULT_14" SITE "AF21";\r
LOCATE COMP "TX_FAULT_15" SITE "AD23";\r
LOCATE COMP "SFP_LOS_6" SITE "AF8";\r
LOCATE COMP "SFP_LOS_7" SITE "AF10";\r
LOCATE COMP "SFP_LOS_8" SITE "AG10";\r
- LOCATE COMP "SFP_LOS_12" SITE "AF11";\r
- LOCATE COMP "SFP_LOS_11" SITE "AC18";\r
- LOCATE COMP "SFP_LOS_10" SITE "AG19";\r
- LOCATE COMP "SFP_LOS_9" SITE "AD20";\r
+ LOCATE COMP "SFP_LOS_9" SITE "AF11";\r
+ LOCATE COMP "SFP_LOS_10" SITE "AC18";\r
+ LOCATE COMP "SFP_LOS_11" SITE "AG19";\r
+ LOCATE COMP "SFP_LOS_12" SITE "AD20";\r
LOCATE COMP "SFP_LOS_13" SITE "AE21";\r
LOCATE COMP "SFP_LOS_14" SITE "AG22";\r
LOCATE COMP "SFP_LOS_15" SITE "AE24";\r
LOCATE COMP "SFP_MOD0_6" SITE "H13";\r
LOCATE COMP "SFP_MOD0_7" SITE "D12";\r
LOCATE COMP "SFP_MOD0_8" SITE "C14";\r
- LOCATE COMP "SFP_MOD0_12" SITE "G13";\r
- LOCATE COMP "SFP_MOD0_11" SITE "H14";\r
- LOCATE COMP "SFP_MOD0_10" SITE "C15";\r
- LOCATE COMP "SFP_MOD0_9" SITE "H18";\r
+ LOCATE COMP "SFP_MOD0_9" SITE "G13";\r
+ LOCATE COMP "SFP_MOD0_10" SITE "H14";\r
+ LOCATE COMP "SFP_MOD0_11" SITE "C15";\r
+ LOCATE COMP "SFP_MOD0_12" SITE "H18";\r
LOCATE COMP "SFP_MOD0_13" SITE "D20";\r
LOCATE COMP "SFP_MOD0_14" SITE "D21";\r
LOCATE COMP "SFP_MOD0_15" SITE "E23";\r
LOCATE COMP "SFP_MOD1_6" SITE "H12";\r
LOCATE COMP "SFP_MOD1_7" SITE "E13";\r
LOCATE COMP "SFP_MOD1_8" SITE "B14";\r
- LOCATE COMP "SFP_MOD1_12" SITE "F13";\r
- LOCATE COMP "SFP_MOD1_11" SITE "G14";\r
- LOCATE COMP "SFP_MOD1_10" SITE "D15";\r
- LOCATE COMP "SFP_MOD1_9" SITE "G18";\r
+ LOCATE COMP "SFP_MOD1_9" SITE "F13";\r
+ LOCATE COMP "SFP_MOD1_10" SITE "G14";\r
+ LOCATE COMP "SFP_MOD1_11" SITE "D15";\r
+ LOCATE COMP "SFP_MOD1_12" SITE "G18";\r
LOCATE COMP "SFP_MOD1_13" SITE "E20";\r
LOCATE COMP "SFP_MOD1_14" SITE "F21";\r
LOCATE COMP "SFP_MOD1_15" SITE "G22";\r
LOCATE COMP "SFP_MOD2_6" SITE "H11";\r
LOCATE COMP "SFP_MOD2_7" SITE "E12";\r
LOCATE COMP "SFP_MOD2_8" SITE "A14";\r
- LOCATE COMP "SFP_MOD2_12" SITE "D13";\r
- LOCATE COMP "SFP_MOD2_11" SITE "F14";\r
- LOCATE COMP "SFP_MOD2_10" SITE "J14";\r
- LOCATE COMP "SFP_MOD2_9" SITE "D19";\r
+ LOCATE COMP "SFP_MOD2_9" SITE "D13";\r
+ LOCATE COMP "SFP_MOD2_10" SITE "F14";\r
+ LOCATE COMP "SFP_MOD2_11" SITE "J14";\r
+ LOCATE COMP "SFP_MOD2_12" SITE "D19";\r
LOCATE COMP "SFP_MOD2_13" SITE "E19";\r
LOCATE COMP "SFP_MOD2_14" SITE "E21";\r
LOCATE COMP "SFP_MOD2_15" SITE "D22";\r
LOCATE COMP "SFP_LED_GREEN_6" SITE "AC13";\r
LOCATE COMP "SFP_LED_GREEN_7" SITE "AG13";\r
LOCATE COMP "SFP_LED_GREEN_8" SITE "AC14";\r
- LOCATE COMP "SFP_LED_GREEN_12" SITE "AD15";\r
- LOCATE COMP "SFP_LED_GREEN_11" SITE "AK14";\r
- LOCATE COMP "SFP_LED_GREEN_10" SITE "AJ15";\r
- LOCATE COMP "SFP_LED_GREEN_9" SITE "AH16";\r
+ LOCATE COMP "SFP_LED_GREEN_9" SITE "AD15";\r
+ LOCATE COMP "SFP_LED_GREEN_10" SITE "AK14";\r
+ LOCATE COMP "SFP_LED_GREEN_11" SITE "AJ15";\r
+ LOCATE COMP "SFP_LED_GREEN_12" SITE "AH16";\r
LOCATE COMP "SFP_LED_GREEN_13" SITE "AD17";\r
LOCATE COMP "SFP_LED_GREEN_14" SITE "AJ17";\r
LOCATE COMP "SFP_LED_GREEN_15" SITE "AC17";\r
LOCATE COMP "SFP_LED_ORANGE_6" SITE "AD13";\r
LOCATE COMP "SFP_LED_ORANGE_7" SITE "AF13";\r
LOCATE COMP "SFP_LED_ORANGE_8" SITE "AE14";\r
- LOCATE COMP "SFP_LED_ORANGE_12" SITE "AC15";\r
- LOCATE COMP "SFP_LED_ORANGE_11" SITE "AJ14";\r
- LOCATE COMP "SFP_LED_ORANGE_10" SITE "AD16";\r
- LOCATE COMP "SFP_LED_ORANGE_9" SITE "AG16";\r
+ LOCATE COMP "SFP_LED_ORANGE_9" SITE "AC15";\r
+ LOCATE COMP "SFP_LED_ORANGE_10" SITE "AJ14";\r
+ LOCATE COMP "SFP_LED_ORANGE_11" SITE "AD16";\r
+ LOCATE COMP "SFP_LED_ORANGE_12" SITE "AG16";\r
LOCATE COMP "SFP_LED_ORANGE_13" SITE "AK17";\r
LOCATE COMP "SFP_LED_ORANGE_14" SITE "AH17";\r
LOCATE COMP "SFP_LED_ORANGE_15" SITE "AE17";\r
\r
\r
#########################################\r
-# Connection to ETRAX\r
+# Connection to Onewire\r
#########################################\r
LOCATE COMP "ONEWIRE" SITE "H1"; #To temperature sensor patch\r
IOBUF PORT "ONEWIRE" IO_TYPE=LVCMOS PULLMODE=UP;\r
LOCATE COMP "CLK_F1_TO_F2_N" SITE "P1";\r
\r
LOCATE COMP "ADDON_RESET" SITE "C17";\r
- LOCATE COMP "RESET" SITE "B17";\r
- LOCATE COMP "SUPPL_RESET" SITE "A17";\r
+ LOCATE COMP "RESET_N" SITE "B17";\r
+ LOCATE COMP "SUPPL_RESET_N" SITE "A17";\r
\r
\r
#########################################\r
BLOCK ASYNCPATHS ;
-#################################################################
-# Constraints
-#################################################################
- FREQUENCY PORT CLK 25.000000 MHz;
-
IOBUF ALLPORTS IO_TYPE=LVTTL33 PULLMODE=NONE ;
LOCATE COMP "TAD_8" SITE "R10";
-# LOCATE COMP "CMS" SITE "R2";
-# LOCATE COMP "GDE" SITE "F16";
-# LOCATE COMP "INITN" SITE "H11";
-# LOCATE COMP "MOD" SITE "P3";
-# LOCATE COMP "MRES" SITE "P1";
-# LOCATE COMP "PROGRAMN" SITE "N12";
-# LOCATE COMP "RDYI" SITE "P16";
-# LOCATE COMP "RES" SITE "P4";
-# LOCATE COMP "TACK" SITE "P14";
-# LOCATE COMP "TADS_0" SITE "N9";
-# LOCATE COMP "TADS_1" SITE "P10";
-# LOCATE COMP "TAOD" SITE "T5";
-# LOCATE COMP "TCDE_0" SITE "R13";
-# LOCATE COMP "TDRA" SITE "N10";
-# LOCATE COMP "TDRB" SITE "T14";
-# LOCATE COMP "TDRE" SITE "R11";
-# LOCATE COMP "TDST" SITE "R16";
-# LOCATE COMP "TENB" SITE "T11";
-# LOCATE COMP "TENR" SITE "T13";
-# LOCATE COMP "TOK" SITE "P2";
-# LOCATE COMP "TOR" SITE "R14";
-
-# LOCATE COMP "TRDYO" SITE "P15";
-# LOCATE COMP "TREN" SITE "T12";
-# LOCATE COMP "TRSV" SITE "T4";
-# LOCATE COMP "WRM" SITE "R15";
-# LOCATE COMP "ADI_0" SITE "L9";
-# LOCATE COMP "ADI_1" SITE "M9";
+ LOCATE COMP "CMS" SITE "R2";
+ LOCATE COMP "GDE" SITE "F16";
+ LOCATE COMP "INITN" SITE "H11";
+ LOCATE COMP "MOD" SITE "P3";
+ LOCATE COMP "MRES" SITE "P1";
+ LOCATE COMP "PROGRAMN" SITE "N12";
+ LOCATE COMP "RDYI" SITE "P16";
+ LOCATE COMP "RES" SITE "P4";
+ LOCATE COMP "TACK" SITE "P14";
+ LOCATE COMP "TADS_0" SITE "N9";
+ LOCATE COMP "TADS_1" SITE "P10";
+ LOCATE COMP "TAOD" SITE "T5";
+ LOCATE COMP "TCDE_0" SITE "R13";
+ LOCATE COMP "TDRA" SITE "N10";
+ LOCATE COMP "TDRB" SITE "T14";
+ LOCATE COMP "TDRE" SITE "R11";
+ LOCATE COMP "TDST" SITE "R16";
+ LOCATE COMP "TENB" SITE "T11";
+ LOCATE COMP "TENR" SITE "T13";
+ LOCATE COMP "TOK" SITE "P2";
+ LOCATE COMP "TOR" SITE "R14";
+
+ LOCATE COMP "TRDYO" SITE "P15";
+ LOCATE COMP "TREN" SITE "T12";
+ LOCATE COMP "TRSV" SITE "T4";
+ LOCATE COMP "WRM" SITE "R15";
+ LOCATE COMP "ADI_0" SITE "L9";
+ LOCATE COMP "ADI_1" SITE "M9";
#################################################################
#Logic Analyzer Connection (Jan)
#################################################################
- LOCATE COMP "LB_0" SITE "L9";
- LOCATE COMP "LB_1" SITE "M9";
- LOCATE COMP "LB_2" SITE "N10";
- LOCATE COMP "LB_3" SITE "T13";
- LOCATE COMP "LB_4" SITE "T14";
- LOCATE COMP "LB_5" SITE "T11";
- LOCATE COMP "LB_6" SITE "R11";
- LOCATE COMP "LB_7" SITE "T12";
+# LOCATE COMP "LB_0" SITE "L9";
+# LOCATE COMP "LB_1" SITE "M9";
+# LOCATE COMP "LB_2" SITE "N10";
+# LOCATE COMP "LB_3" SITE "T13";
+# LOCATE COMP "LB_4" SITE "T14";
+# LOCATE COMP "LB_5" SITE "T11";
+# LOCATE COMP "LB_6" SITE "R11";
+# LOCATE COMP "LB_7" SITE "T12";
-COMMERCIAL ;
-BLOCK RESETPATHS ;
-BLOCK ASYNCPATHS ;
-
-#################################################################
-# Clock constraints
-#################################################################
-FREQUENCY NET "clk_100m" 100.000000 MHz;
-FREQUENCY NET "clk_25m" 25.000000 MHz;
-FREQUENCY NET "THE_MED_INTERFACE_0/ff_txfullclk" 25.000000 MHz ;
-FREQUENCY NET "THE_MED_INTERFACE_0/ff_rxfullclk_0" 25.000000 MHz ;
-FREQUENCY NET "THE_MED_INTERFACE_0/ff_rxfullclk_1" 25.000000 MHz ;
-FREQUENCY NET "THE_MED_INTERFACE_0/ff_rxfullclk_2" 25.000000 MHz ;
-FREQUENCY NET "THE_MED_INTERFACE_0/ff_rxfullclk_3" 25.000000 MHz ;
-FREQUENCY NET "THE_MED_INTERFACE_0_ff_txfullclk" 25.000000 MHz ;
-FREQUENCY NET "THE_MED_INTERFACE_0_ff_rxfullclk_0" 25.000000 MHz ;
-FREQUENCY NET "THE_MED_INTERFACE_0_ff_rxfullclk_1" 25.000000 MHz ;
-FREQUENCY NET "THE_MED_INTERFACE_0_ff_rxfullclk_2" 25.000000 MHz ;
-FREQUENCY NET "THE_MED_INTERFACE_0_ff_rxfullclk_3" 25.000000 MHz ;
-
-FREQUENCY NET "THE_MED_INTERFACE_0_ff_rxfullclk" 25.000000 MHz ;
-
-
-FREQUENCY NET "THE_MED_INTERFACE_1/ff_txfullclk" 25.000000 MHz ;
-FREQUENCY NET "THE_MED_INTERFACE_1_ff_rxfullclk" 25.000000 MHz ;
-#placeholders don't seem to work
-#FREQUENCY NET "THE_MED_INTERFACE_0*fullclk*" 25.000000 MHz ;
-
-
-#################################################################
-# Placement
-#################################################################
-LOCATE COMP "THE_MED_INTERFACE_0/THE_SERDES/PCSC_INST" SITE "LLPCS" ;
-LOCATE COMP "THE_MED_INTERFACE_1/THE_SERDES/PCSC_INST" SITE "ULPCS" ;
-
-IOBUF ALLPORTS IO_TYPE=LVTTL33 PULLMODE=DOWN ;
-# USE PRIMARY NET "CLK_25" ;
-USE DIN FALSE CELL "THE_MED_INTERFACE_0_gen_tx_fifos_1_THE_SD_SYNC_sync_qio_1" ;
-USE DIN FALSE CELL "THE_MED_INTERFACE_0_gen_tx_fifos_3_THE_SD_SYNC_sync_qio_1" ;
-USE DIN FALSE CELL "THE_MED_INTERFACE_0_gen_tx_fifos_2_THE_SD_SYNC_sync_qio_1" ;
-USE DIN FALSE CELL "THE_MED_INTERFACE_0_gen_tx_fifos_0_THE_SD_SYNC_sync_qio_1" ;
-USE DIN FALSE CELL "THE_MED_INTERFACE_1_gen_tx_fifos_1_THE_SD_SYNC_sync_qio_1" ;
-USE DIN FALSE CELL "THE_MED_INTERFACE_1_gen_tx_fifos_3_THE_SD_SYNC_sync_qio_1" ;
-USE DIN FALSE CELL "THE_MED_INTERFACE_1_gen_tx_fifos_2_THE_SD_SYNC_sync_qio_1" ;
-USE DIN FALSE CELL "THE_MED_INTERFACE_1_gen_tx_fifos_0_THE_SD_SYNC_sync_qio_1" ;
-# PROHIBIT PRIMARY NET "THE_MED_INTERFACE_0*fullclk*" ;
-# PROHIBIT SECONDARY NET "THE_MED_INTERFACE_0*fullclk*" ;
-
-PROHIBIT PRIMARY NET "THE_MED_INTERFACE_0_ff_rxfullclk_0" ;
-PROHIBIT SECONDARY NET "THE_MED_INTERFACE_0_ff_rxfullclk_0" ;
-PROHIBIT PRIMARY NET "THE_MED_INTERFACE_0_ff_rxfullclk_1" ;
-PROHIBIT SECONDARY NET "THE_MED_INTERFACE_0_ff_rxfullclk_1" ;
-PROHIBIT PRIMARY NET "THE_MED_INTERFACE_0_ff_rxfullclk_2" ;
-PROHIBIT SECONDARY NET "THE_MED_INTERFACE_0_ff_rxfullclk_2" ;
-PROHIBIT PRIMARY NET "THE_MED_INTERFACE_0_ff_rxfullclk_3" ;
-PROHIBIT SECONDARY NET "THE_MED_INTERFACE_0_ff_rxfullclk_3" ;
-PROHIBIT PRIMARY NET "THE_MED_INTERFACE_1_ff_rxfullclk_0" ;
-PROHIBIT SECONDARY NET "THE_MED_INTERFACE_1_ff_rxfullclk_0" ;
-PROHIBIT PRIMARY NET "THE_MED_INTERFACE_1_ff_rxfullclk_1" ;
-PROHIBIT SECONDARY NET "THE_MED_INTERFACE_1_ff_rxfullclk_1" ;
-PROHIBIT PRIMARY NET "THE_MED_INTERFACE_1_ff_rxfullclk_2" ;
-PROHIBIT SECONDARY NET "THE_MED_INTERFACE_1_ff_rxfullclk_2" ;
-PROHIBIT PRIMARY NET "THE_MED_INTERFACE_1_ff_rxfullclk_3" ;
-
-PROHIBIT SECONDARY NET "THE_MED_INTERFACE_0_ff_rxfullclk" ;
-PROHIBIT PRIMARY NET "THE_MED_INTERFACE_0_ff_rxfullclk" ;
-PROHIBIT SECONDARY NET "THE_MED_INTERFACE_1_ff_rxfullclk" ;
-PROHIBIT PRIMARY NET "THE_MED_INTERFACE_1_ff_rxfullclk" ;
-
-
-REGION "REGION_PCS_LLC" "R95C2" 17 40 ;
-UGROUP "THE_MED_INTERFACE_0/GROUP_PCS" BLKNAME THE_MED_INTERFACE_0 ;
-LOCATE UGROUP "THE_MED_INTERFACE_0/GROUP_PCS" REGION "REGION_PCS_LLC" ;
-
-REGION "REGION_PCS_ULC" "R9C2" 18 27 ;
-UGROUP "THE_MED_INTERFACE_1/GROUP_PCS" BLKNAME THE_MED_INTERFACE_1 ;
-LOCATE UGROUP "THE_MED_INTERFACE_1/GROUP_PCS" REGION "REGION_PCS_ULC" ;
-
#################################################################
# Clock I/O
#################################################################
# AddOn-Connector Data Lines
#################################################################
-# LOCATE COMP "ADO_LV_16" SITE "R3";
-# LOCATE COMP "ADO_LV_17" SITE "R2";
-# LOCATE COMP "ADO_LV_18" SITE "T5";
-# LOCATE COMP "ADO_LV_19" SITE "T4";
-# LOCATE COMP "ADO_LV_20" SITE "U5";
-# LOCATE COMP "ADO_LV_21" SITE "U4";
-# LOCATE COMP "ADO_LV_22" SITE "Y9";
-# LOCATE COMP "ADO_LV_23" SITE "Y8";
-# LOCATE COMP "ADO_LV_24" SITE "AB2";
-# LOCATE COMP "ADO_LV_25" SITE "AB3";
-# LOCATE COMP "ADO_LV_26" SITE "AC7";
-# LOCATE COMP "ADO_LV_27" SITE "AC6";
-# LOCATE COMP "ADO_LV_44" SITE "T3";
-# LOCATE COMP "ADO_LV_45" SITE "T2";
-# LOCATE COMP "ADO_LV_46" SITE "U3";
-# LOCATE COMP "ADO_LV_47" SITE "U2";
-# LOCATE COMP "ADO_LV_48" SITE "Y1";
-# LOCATE COMP "ADO_LV_49" SITE "Y2";
-# LOCATE COMP "ADO_LV_50" SITE "AA1";
-# LOCATE COMP "ADO_LV_51" SITE "AA2";
-# LOCATE COMP "ADO_LV_52" SITE "AB4";
-# LOCATE COMP "ADO_LV_53" SITE "AB5";
-# LOCATE COMP "ADO_LV_54" SITE "AC1";
-# LOCATE COMP "ADO_LV_55" SITE "AC2";
-# LOCATE COMP "ADO_LV_56" SITE "U1";
-# LOCATE COMP "ADO_LV_57" SITE "V2";
-# LOCATE COMP "ADO_LV_58" SITE "V1";
-# LOCATE COMP "ADO_LV_59" SITE "W1";
-# LOCATE COMP "ADO_LV_60" SITE "W3";
-# LOCATE COMP "ADO_LV_61" SITE "W4";
-# IOBUF PORT "ADO_LV_16" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "ADO_LV_18" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "ADO_LV_20" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "ADO_LV_22" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "ADO_LV_24" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "ADO_LV_26" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "ADO_LV_44" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "ADO_LV_46" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "ADO_LV_48" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "ADO_LV_50" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "ADO_LV_52" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "ADO_LV_54" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "ADO_LV_56" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "ADO_LV_58" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "ADO_LV_60" IO_TYPE=LVDS25 PULLMODE=NONE ;
+LOCATE COMP "ADO_LV_16" SITE "R3";
+LOCATE COMP "ADO_LV_17" SITE "R2";
+LOCATE COMP "ADO_LV_18" SITE "T5";
+LOCATE COMP "ADO_LV_19" SITE "T4";
+LOCATE COMP "ADO_LV_20" SITE "U5";
+LOCATE COMP "ADO_LV_21" SITE "U4";
+LOCATE COMP "ADO_LV_22" SITE "Y9";
+LOCATE COMP "ADO_LV_23" SITE "Y8";
+LOCATE COMP "ADO_LV_24" SITE "AB2";
+LOCATE COMP "ADO_LV_25" SITE "AB3";
+LOCATE COMP "ADO_LV_26" SITE "AC7";
+LOCATE COMP "ADO_LV_27" SITE "AC6";
+LOCATE COMP "ADO_LV_44" SITE "T3";
+LOCATE COMP "ADO_LV_45" SITE "T2";
+LOCATE COMP "ADO_LV_46" SITE "U3";
+LOCATE COMP "ADO_LV_47" SITE "U2";
+LOCATE COMP "ADO_LV_48" SITE "Y1";
+LOCATE COMP "ADO_LV_49" SITE "Y2";
+LOCATE COMP "ADO_LV_50" SITE "AA1";
+LOCATE COMP "ADO_LV_51" SITE "AA2";
+LOCATE COMP "ADO_LV_52" SITE "AB4";
+LOCATE COMP "ADO_LV_53" SITE "AB5";
+LOCATE COMP "ADO_LV_54" SITE "AC1";
+LOCATE COMP "ADO_LV_55" SITE "AC2";
+LOCATE COMP "ADO_LV_56" SITE "U1";
+LOCATE COMP "ADO_LV_57" SITE "V2";
+LOCATE COMP "ADO_LV_58" SITE "V1";
+LOCATE COMP "ADO_LV_59" SITE "W1";
+LOCATE COMP "ADO_LV_60" SITE "W3";
+LOCATE COMP "ADO_LV_61" SITE "W4";
+DEFINE PORT GROUP "ADO_LV_group" "ADO_LV*" ;
+IOBUF GROUP "ADO_LV_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12;
+
LOCATE COMP "ADO_TTL_0" SITE "AF10" ;
LOCATE COMP "ADO_TTL_1" SITE "AE8" ;
LOCATE COMP "ADO_TTL_2" SITE "AE11" ;
LOCATE COMP "ADO_TTL_43" SITE "AK16" ;
LOCATE COMP "ADO_TTL_44" SITE "AF18" ;
LOCATE COMP "ADO_TTL_45" SITE "AD16" ;
-LOCATE COMP "ADO_TTL_46" SITE "AJ15" ;
-IOBUF PORT "ADO_TTL_0" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
-IOBUF PORT "ADO_TTL_1" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
-IOBUF PORT "ADO_TTL_2" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
-IOBUF PORT "ADO_TTL_3" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
-IOBUF PORT "ADO_TTL_4" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
-IOBUF PORT "ADO_TTL_5" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
-IOBUF PORT "ADO_TTL_6" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
-IOBUF PORT "ADO_TTL_7" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
-IOBUF PORT "ADO_TTL_8" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
-IOBUF PORT "ADO_TTL_9" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
-IOBUF PORT "ADO_TTL_10" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
-IOBUF PORT "ADO_TTL_11" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
-IOBUF PORT "ADO_TTL_12" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
-IOBUF PORT "ADO_TTL_13" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
-IOBUF PORT "ADO_TTL_14" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
-IOBUF PORT "ADO_TTL_15" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
-IOBUF PORT "ADO_TTL_16" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
-IOBUF PORT "ADO_TTL_17" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
-IOBUF PORT "ADO_TTL_18" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
-IOBUF PORT "ADO_TTL_19" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
-IOBUF PORT "ADO_TTL_20" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
-IOBUF PORT "ADO_TTL_21" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
-IOBUF PORT "ADO_TTL_22" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
-IOBUF PORT "ADO_TTL_23" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
-IOBUF PORT "ADO_TTL_24" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
-IOBUF PORT "ADO_TTL_25" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
-IOBUF PORT "ADO_TTL_26" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
-IOBUF PORT "ADO_TTL_27" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
-IOBUF PORT "ADO_TTL_28" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
-IOBUF PORT "ADO_TTL_29" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
-IOBUF PORT "ADO_TTL_30" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
-IOBUF PORT "ADO_TTL_31" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
-IOBUF PORT "ADO_TTL_32" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
-IOBUF PORT "ADO_TTL_33" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
-IOBUF PORT "ADO_TTL_34" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
-IOBUF PORT "ADO_TTL_35" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
-IOBUF PORT "ADO_TTL_36" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
-IOBUF PORT "ADO_TTL_37" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
-IOBUF PORT "ADO_TTL_38" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
-IOBUF PORT "ADO_TTL_39" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
-IOBUF PORT "ADO_TTL_40" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
-IOBUF PORT "ADO_TTL_41" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
-IOBUF PORT "ADO_TTL_42" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
-IOBUF PORT "ADO_TTL_43" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
-IOBUF PORT "ADO_TTL_44" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
-IOBUF PORT "ADO_TTL_45" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
-IOBUF PORT "ADO_TTL_46" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12 ;
+# LOCATE COMP "ADO_TTL_46" SITE "AJ15" ; occupied by onewire monitor
+DEFINE PORT GROUP "ADO_TTL_group" "ADO_TTL*" ;
+IOBUF GROUP "ADO_TTL_group" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12;
+
+LOCATE COMP "ONEWIRE_F1" SITE "AJ15";
+IOBUF PORT "ONEWIRE_F1" IO_TYPE=LVTTL33 PULLMODE=UP;
#################################################################
# LED next to FPGA
LOCATE COMP "LED_RX_30" SITE "AC20" ;
LOCATE COMP "LED_RX_31" SITE "AE21" ;
LOCATE COMP "LED_RX_32" SITE "AD23" ;
-IOBUF PORT "LED_NC_17" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "LED_NC_18" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "LED_NC_19" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "LED_NC_20" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "LED_NC_21" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "LED_NC_22" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "LED_NC_23" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "LED_NC_24" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "LED_NC_25" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "LED_NC_26" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "LED_NC_27" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "LED_NC_28" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "LED_NC_29" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "LED_NC_30" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "LED_NC_31" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "LED_NC_32" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "LED_RX_17" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "LED_RX_18" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "LED_RX_19" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "LED_RX_20" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "LED_RX_21" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "LED_RX_22" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "LED_RX_23" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "LED_RX_24" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "LED_RX_25" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "LED_RX_26" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "LED_RX_27" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "LED_RX_28" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "LED_RX_29" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "LED_RX_30" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "LED_RX_31" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "LED_RX_32" IO_TYPE=LVTTL33 PULLMODE=NONE ;
+DEFINE PORT GROUP "LED_group" "LED*" ;
+IOBUF GROUP "LED_group" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=12;
#################################################################
LOCATE COMP "F1_F3_TTL_6" SITE "AG21";
LOCATE COMP "F1_F3_TTL_7" SITE "AD24";
LOCATE COMP "F1_F3_TTL_8" SITE "AE24";
-IOBUF PORT "F1_F3_TTL_0" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "F1_F3_TTL_1" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "F1_F3_TTL_2" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "F1_F3_TTL_3" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "F1_F3_TTL_4" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "F1_F3_TTL_5" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "F1_F3_TTL_6" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "F1_F3_TTL_7" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "F1_F3_TTL_8" IO_TYPE=LVTTL33 PULLMODE=NONE ;
+DEFINE PORT GROUP "F1_F3_group" "F1_F3*" ;
+IOBUF GROUP "F1_F3_group" IO_TYPE=LVTTL33 PULLMODE=NONE;
#LVDS
# LOCATE COMP "F1_TO_OUT_0" SITE "K2";
# LOCATE COMP "F1_TO_OUTB_7" SITE "N2";
# LOCATE COMP "F1_TO_OUT_8" SITE "P3";
# LOCATE COMP "F1_TO_OUTB_8" SITE "P2";
-# IOBUF PORT "F1_TO_OUT_0" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "F1_TO_OUT_1" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "F1_TO_OUT_2" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "F1_TO_OUT_3" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "F1_TO_OUT_4" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "F1_TO_OUT_5" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "F1_TO_OUT_6" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "F1_TO_OUT_7" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "F1_TO_OUT_8" IO_TYPE=LVDS25 PULLMODE=NONE ;
+# DEFINE PORT GROUP "F1_TO_OUT_group" "F1_TO_OUT*" ;
+# IOBUF GROUP "F1_TO_OUT_group" IO_TYPE=LVDS25 ;
+
# LOCATE COMP "OUT_TO_F1_0" SITE "N9";
# LOCATE COMP "OUT_TO_F1B_0" SITE "N7";
# LOCATE COMP "OUT_TO_F1_1" SITE "N8";
# LOCATE COMP "OUT_TO_F1B_7" SITE "R4";
# LOCATE COMP "OUT_TO_F1_8" SITE "R8";
# LOCATE COMP "OUT_TO_F1B_8" SITE "T9";
-# IOBUF PORT "OUT_TO_F1__0" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "OUT_TO_F1__1" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "OUT_TO_F1__2" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "OUT_TO_F1__3" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "OUT_TO_F1__4" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "OUT_TO_F1__5" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "OUT_TO_F1__6" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "OUT_TO_F1__7" IO_TYPE=LVDS25 PULLMODE=NONE ;
+# DEFINE PORT GROUP "OUT_TO_F1_group" "OUT_TO_F1*" ;
+# IOBUF GROUP "OUT_TO_F1_group" IO_TYPE=LVDS25 ;
#TTL
LOCATE COMP "F1_TO_F3_15" SITE "N2";
LOCATE COMP "F1_TO_F3_16" SITE "P3";
LOCATE COMP "F1_TO_F3_17" SITE "P2";
-IOBUF PORT "F1_TO_F3_0" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-IOBUF PORT "F1_TO_F3_1" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-IOBUF PORT "F1_TO_F3_2" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-IOBUF PORT "F1_TO_F3_3" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-IOBUF PORT "F1_TO_F3_4" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-IOBUF PORT "F1_TO_F3_5" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-IOBUF PORT "F1_TO_F3_6" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-IOBUF PORT "F1_TO_F3_7" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-IOBUF PORT "F1_TO_F3_8" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-IOBUF PORT "F1_TO_F3_9" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-IOBUF PORT "F1_TO_F3_10" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-IOBUF PORT "F1_TO_F3_11" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-IOBUF PORT "F1_TO_F3_12" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-IOBUF PORT "F1_TO_F3_13" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-IOBUF PORT "F1_TO_F3_14" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-IOBUF PORT "F1_TO_F3_15" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-IOBUF PORT "F1_TO_F3_16" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-IOBUF PORT "F1_TO_F3_17" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
+DEFINE PORT GROUP "F1_TO_F3_group" "F1_TO_F3*" ;
+IOBUF GROUP "F1_TO_F3_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
+
LOCATE COMP "F3_TO_F1_0" SITE "N9";
LOCATE COMP "F3_TO_F1_1" SITE "N7";
LOCATE COMP "F3_TO_F1_2" SITE "N8";
LOCATE COMP "F3_TO_F1_15" SITE "R4";
LOCATE COMP "F3_TO_F1_16" SITE "R8";
LOCATE COMP "F3_TO_F1_17" SITE "T9";
-IOBUF PORT "F3_TO_F1_0" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-IOBUF PORT "F3_TO_F1_1" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-IOBUF PORT "F3_TO_F1_2" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-IOBUF PORT "F3_TO_F1_3" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-IOBUF PORT "F3_TO_F1_4" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-IOBUF PORT "F3_TO_F1_5" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-IOBUF PORT "F3_TO_F1_6" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-IOBUF PORT "F3_TO_F1_7" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-IOBUF PORT "F3_TO_F1_8" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-IOBUF PORT "F3_TO_F1_9" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-IOBUF PORT "F3_TO_F1_10" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-IOBUF PORT "F3_TO_F1_11" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-IOBUF PORT "F3_TO_F1_12" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-IOBUF PORT "F3_TO_F1_13" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-IOBUF PORT "F3_TO_F1_14" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-IOBUF PORT "F3_TO_F1_15" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-IOBUF PORT "F3_TO_F1_16" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-IOBUF PORT "F3_TO_F1_17" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
+DEFINE PORT GROUP "F3_TO_F1_group" "F3_TO_F1*" ;
+IOBUF GROUP "F3_TO_F1_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
+
#################################################################
# LOCATE COMP "FS_PE_8" SITE "D12";
# LOCATE COMP "FS_PE_9" SITE "E13";
# LOCATE COMP "FS_PE_10" SITE "J12";
-# IOBUF PORT "FS_PE_0" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-# IOBUF PORT "FS_PE_1" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-# IOBUF PORT "FS_PE_2" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-# IOBUF PORT "FS_PE_3" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-# IOBUF PORT "FS_PE_4" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-# IOBUF PORT "FS_PE_5" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-# IOBUF PORT "FS_PE_6" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-# IOBUF PORT "FS_PE_7" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-# IOBUF PORT "FS_PE_8" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-# IOBUF PORT "FS_PE_9" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-# IOBUF PORT "FS_PE_10" IO_TYPE=LVTTL33 PULLMODE=NONE ;
+# DEFINE PORT GROUP "FS_PE_group" "FS_PE*" ;
+# IOBUF GROUP "FS_PE_group" IO_TYPE=LVTTL33 PULLMODE=NONE ;
#################################################################
#Connection to FPGA2
#################################################################
-# LOCATE COMP "INTERLVDS__0" SITE "W28";
-# LOCATE COMP "INTERLVDS__1" SITE "V29";
-# LOCATE COMP "INTERLVDS__2" SITE "U26";
-# LOCATE COMP "INTERLVDS__3" SITE "U27";
-# LOCATE COMP "INTERLVDS__4" SITE "T28";
-# LOCATE COMP "INTERLVDS__5" SITE "R30";
-# LOCATE COMP "INTERLVDS__6" SITE "R29";
-# LOCATE COMP "INTERLVDS__7" SITE "P28";
-# LOCATE COMP "INTERLVDS__8" SITE "P26";
-# LOCATE COMP "INTERLVDS__9" SITE "P24";
-# LOCATE COMP "INTERLVDS__10" SITE "P22";
-# LOCATE COMP "INTERLVDS__11" SITE "N29";
-# LOCATE COMP "INTERLVDS__12" SITE "N23";
-# LOCATE COMP "INTERLVDS__13" SITE "M28";
-# LOCATE COMP "INTERLVDS__14" SITE "M26";
-# LOCATE COMP "INTERLVDS__15" SITE "M22";
-# LOCATE COMP "INTERLVDS__16" SITE "L27";
-# LOCATE COMP "INTERLVDS__17" SITE "L23";
-# LOCATE COMP "INTERLVDS__18" SITE "K25";
-# LOCATE COMP "INTERLVDS__19" SITE "K22";
-# LOCATE COMP "INTERLVDS__20" SITE "J28";
-# LOCATE COMP "INTERLVDS__21" SITE "H26";
-# LOCATE COMP "INTERLVDS__22" SITE "H24";
-# LOCATE COMP "INTERLVDS__23" SITE "H25";
-# LOCATE COMP "INTERLVDS__24" SITE "E29";
-# LOCATE COMP "INTERLVDS__25" SITE "W29";
-# LOCATE COMP "INTERLVDS__26" SITE "V25";
-# LOCATE COMP "INTERLVDS__27" SITE "U30";
-# LOCATE COMP "INTERLVDS__28" SITE "U24";
-# LOCATE COMP "INTERLVDS__29" SITE "V23";
-# LOCATE COMP "INTERLVDS__30" SITE "R22";
-# LOCATE COMP "INTERLVDS__31" SITE "T22";
-# LOCATE COMP "INTERLVDS__32" SITE "T26";
-# LOCATE COMP "INTERLVDS__33" SITE "R28";
-# LOCATE COMP "INTERLVDS__34" SITE "K29";
-# LOCATE COMP "INTERLVDS__35" SITE "P27";
-# LOCATE COMP "INTERLVDS__36" SITE "J29";
-# LOCATE COMP "INTERLVDS__37" SITE "N26";
-# LOCATE COMP "INTERLVDS__38" SITE "G30";
-# LOCATE COMP "INTERLVDS__39" SITE "L29";
-# LOCATE COMP "INTERLVDS__40" SITE "F29";
-# LOCATE COMP "INTERLVDS__41" SITE "G29";
-# LOCATE COMP "INTERLVDS__42" SITE "D29";
-# LOCATE COMP "INTERLVDS__43" SITE "K26";
-# LOCATE COMP "INTERLVDS__44" SITE "J23";
-# LOCATE COMP "INTERLVDS__45" SITE "G27";
-# LOCATE COMP "INTERLVDS__46" SITE "G26";
-# LOCATE COMP "INTERLVDS__47" SITE "E28";
-# LOCATE COMP "INTERLVDS__48" SITE "E27";
-# LOCATE COMP "INTERLVDS__49" SITE "L26";
-# LOCATE COMP "INTERLVDS__50" SITE "W26";
-# LOCATE COMP "INTERLVDS__51" SITE "Y26";
-# IOBUF PORT "INTERLVDS__0" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__1" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__2" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__3" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__4" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__5" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__6" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__7" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__8" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__9" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__10" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__11" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__12" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__13" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__14" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__15" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__16" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__17" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__18" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__19" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__20" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__21" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__22" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__23" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__24" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__25" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__26" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__27" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__28" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__29" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__30" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__31" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__32" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__33" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__34" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__35" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__36" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__37" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__38" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__39" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__40" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__41" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__42" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__43" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__44" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__45" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__46" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__47" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__48" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__49" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__50" IO_TYPE=LVDS25 PULLMODE=NONE ;
-# IOBUF PORT "INTERLVDS__51" IO_TYPE=LVDS25 PULLMODE=NONE ;
+# LOCATE COMP "INTERLVDS_0" SITE "W28";
+# LOCATE COMP "INTERLVDS_1" SITE "V29";
+# LOCATE COMP "INTERLVDS_2" SITE "U26";
+# LOCATE COMP "INTERLVDS_3" SITE "U27";
+# LOCATE COMP "INTERLVDS_4" SITE "T28";
+# LOCATE COMP "INTERLVDS_5" SITE "R30";
+# LOCATE COMP "INTERLVDS_6" SITE "R29";
+# LOCATE COMP "INTERLVDS_7" SITE "P28";
+# LOCATE COMP "INTERLVDS_8" SITE "P26";
+# LOCATE COMP "INTERLVDS_9" SITE "P24";
+# LOCATE COMP "INTERLVDS_10" SITE "P22";
+# LOCATE COMP "INTERLVDS_11" SITE "N29";
+# LOCATE COMP "INTERLVDS_12" SITE "N23";
+# LOCATE COMP "INTERLVDS_13" SITE "M28";
+# LOCATE COMP "INTERLVDS_14" SITE "M26";
+# LOCATE COMP "INTERLVDS_15" SITE "M22";
+# LOCATE COMP "INTERLVDS_16" SITE "L27";
+# LOCATE COMP "INTERLVDS_17" SITE "L23";
+# LOCATE COMP "INTERLVDS_18" SITE "K25";
+# LOCATE COMP "INTERLVDS_19" SITE "K22";
+# LOCATE COMP "INTERLVDS_20" SITE "J28";
+# LOCATE COMP "INTERLVDS_21" SITE "H26";
+# LOCATE COMP "INTERLVDS_22" SITE "H24";
+# LOCATE COMP "INTERLVDS_23" SITE "H25";
+# LOCATE COMP "INTERLVDS_24" SITE "E29";
+# LOCATE COMP "INTERLVDS_25" SITE "W29";
+# LOCATE COMP "INTERLVDS_26" SITE "V25";
+# LOCATE COMP "INTERLVDS_27" SITE "U30";
+# LOCATE COMP "INTERLVDS_28" SITE "U24";
+# LOCATE COMP "INTERLVDS_29" SITE "V23";
+# LOCATE COMP "INTERLVDS_30" SITE "R22";
+# LOCATE COMP "INTERLVDS_31" SITE "T22";
+# LOCATE COMP "INTERLVDS_32" SITE "T26";
+# LOCATE COMP "INTERLVDS_33" SITE "R28";
+# LOCATE COMP "INTERLVDS_34" SITE "K29";
+# LOCATE COMP "INTERLVDS_35" SITE "P27";
+# LOCATE COMP "INTERLVDS_36" SITE "J29";
+# LOCATE COMP "INTERLVDS_37" SITE "N26";
+# LOCATE COMP "INTERLVDS_38" SITE "G30";
+# LOCATE COMP "INTERLVDS_39" SITE "L29";
+# LOCATE COMP "INTERLVDS_40" SITE "F29";
+# LOCATE COMP "INTERLVDS_41" SITE "G29";
+# LOCATE COMP "INTERLVDS_42" SITE "D29";
+# LOCATE COMP "INTERLVDS_43" SITE "K26";
+# LOCATE COMP "INTERLVDS_44" SITE "J23";
+# LOCATE COMP "INTERLVDS_45" SITE "G27";
+# LOCATE COMP "INTERLVDS_46" SITE "G26";
+# LOCATE COMP "INTERLVDS_47" SITE "E28";
+# LOCATE COMP "INTERLVDS_48" SITE "E27";
+# LOCATE COMP "INTERLVDS_49" SITE "L26";
+# LOCATE COMP "INTERLVDS_50" SITE "W26";
+# LOCATE COMP "INTERLVDS_51" SITE "Y26";
+# DEFINE PORT GROUP "INTERLVDS_group" "INTERLVDS*" ;
+# IOBUF GROUP "INTERLVDS_group" IO_TYPE=LVDS25 ;
+
# LOCATE COMP "INTERTTL_0" SITE "C15";
# LOCATE COMP "INTERTTL_1" SITE "D15";
# LOCATE COMP "INTERTTL_2" SITE "C14";
# LOCATE COMP "INTERTTL_29" SITE "F16";
# LOCATE COMP "INTERTTL_30" SITE "J16";
# LOCATE COMP "INTERTTL_31" SITE "G15";
-# IOBUF PORT "INTERTTL_0" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-# IOBUF PORT "INTERTTL_1" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-# IOBUF PORT "INTERTTL_2" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-# IOBUF PORT "INTERTTL_3" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-# IOBUF PORT "INTERTTL_4" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-# IOBUF PORT "INTERTTL_5" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-# IOBUF PORT "INTERTTL_6" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-# IOBUF PORT "INTERTTL_7" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-# IOBUF PORT "INTERTTL_8" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-# IOBUF PORT "INTERTTL_9" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-# IOBUF PORT "INTERTTL_10" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-# IOBUF PORT "INTERTTL_11" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-# IOBUF PORT "INTERTTL_12" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-# IOBUF PORT "INTERTTL_13" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-# IOBUF PORT "INTERTTL_14" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-# IOBUF PORT "INTERTTL_15" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-# IOBUF PORT "INTERTTL_16" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-# IOBUF PORT "INTERTTL_17" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-# IOBUF PORT "INTERTTL_18" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-# IOBUF PORT "INTERTTL_19" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-# IOBUF PORT "INTERTTL_20" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-# IOBUF PORT "INTERTTL_21" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-# IOBUF PORT "INTERTTL_22" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-# IOBUF PORT "INTERTTL_23" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-# IOBUF PORT "INTERTTL_24" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-# IOBUF PORT "INTERTTL_25" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-# IOBUF PORT "INTERTTL_26" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-# IOBUF PORT "INTERTTL_27" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-# IOBUF PORT "INTERTTL_28" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-# IOBUF PORT "INTERTTL_29" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-# IOBUF PORT "INTERTTL_30" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-# IOBUF PORT "INTERTTL_31" IO_TYPE=LVTTL33 PULLMODE=NONE ;
+# DEFINE PORT GROUP "INTERTTL_group" "INTERTTL*" ;
+# IOBUF GROUP "INTERTTL_group" IO_TYPE=LVTTL33 PULLMODE=NONE ;
+
#################################################################
# Signal Detect from FOT
LOCATE COMP "SD_30" SITE "AG15" ;
LOCATE COMP "SD_31" SITE "AH14" ;
LOCATE COMP "SD_32" SITE "AH15" ;
-IOBUF PORT "SD_17" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "SD_18" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "SD_19" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "SD_20" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "SD_21" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "SD_22" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "SD_23" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "SD_24" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "SD_25" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "SD_26" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "SD_27" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "SD_28" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "SD_29" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "SD_30" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "SD_31" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-IOBUF PORT "SD_32" IO_TYPE=LVTTL33 PULLMODE=NONE ;
+DEFINE PORT GROUP "sd_group" "SD*" ;
+IOBUF GROUP "sd_group" IO_TYPE=LVTTL33 PULLMODE=NONE ;
-#################################################################
-# Old stuff
-#################################################################
-# LOCATE COMP "THE_MED_INTERFACE_0/THE_SERDES/PCSC_INST" SITE "LLPCS" ;
-# # LOCATE COMP "THE_MED_INTERFACE/THE_SERDES/PCSC_INST" SITE "LLPCS" ;
-# # LOCATE COMP "THE_MED_INTERFACE/THE_SERDES/PCSC_INST" SITE "URPCS" ;
-# # LOCATE COMP "THE_MED_INTERFACE/THE_SERDES/PCSC_INST" SITE "ULPCS" ;
-# FREQUENCY NET "THE_MED_INTERFACE_0/ff_txfullclk" 25.000000 MHz ;
-# FREQUENCY NET "THE_MED_INTERFACE_0/ff_rxfullclk_0" 25.000000 MHz ;
-# FREQUENCY NET "THE_MED_INTERFACE_0/ff_rxfullclk_1" 25.000000 MHz ;
-# FREQUENCY NET "THE_MED_INTERFACE_0/ff_rxfullclk_2" 25.000000 MHz ;
-# FREQUENCY NET "THE_MED_INTERFACE_0/ff_rxfullclk_3" 25.000000 MHz ;
-# FREQUENCY NET "THE_MED_INTERFACE_0_ff_txfullclk" 25.000000 MHz ;
-# FREQUENCY NET "THE_MED_INTERFACE_0_ff_rxfullclk_0" 25.000000 MHz ;
-# FREQUENCY NET "THE_MED_INTERFACE_0_ff_rxfullclk_1" 25.000000 MHz ;
-# FREQUENCY NET "THE_MED_INTERFACE_0_ff_rxfullclk_2" 25.000000 MHz ;
-# FREQUENCY NET "THE_MED_INTERFACE_0_ff_rxfullclk_3" 25.000000 MHz ;
-# IOBUF ALLPORTS IO_TYPE=LVTTL33 PULLMODE=DOWN ;
-# USE PRIMARY NET "CLK_25" ;
-# # USE PRIMARY NET "THE_MED_INTERFACE_0/ff_txfullclk" ;
-# # USE SECONDARY NET "THE_MED_INTERFACE_0/ff_rxfullclk_1" ;
-# # USE SECONDARY NET "THE_MED_INTERFACE_0/ff_rxfullclk_2" ;
-# # USE SECONDARY NET "THE_MED_INTERFACE_0/ff_rxfullclk_3" ;
-# # USE SECONDARY NET "THE_MED_INTERFACE_0/ff_rxfullclk_0" ;
-# # USE PRIMARY NET "THE_MED_INTERFACE_0_ff_txfullclk" ;
-# # USE SECONDARY NET "THE_MED_INTERFACE_0_ff_rxfullclk_1" ;
-# # USE SECONDARY NET "THE_MED_INTERFACE_0_ff_rxfullclk_2" ;
-# # USE SECONDARY NET "THE_MED_INTERFACE_0_ff_rxfullclk_3" ;
-# # USE SECONDARY NET "THE_MED_INTERFACE_0_ff_rxfullclk_0" ;
-# USE DIN FALSE CELL "THE_MED_INTERFACE_0_gen_tx_fifos_1_THE_SD_SYNC_sync_qio_1" ;
-# USE DIN FALSE CELL "THE_MED_INTERFACE_0_gen_tx_fifos_3_THE_SD_SYNC_sync_qio_1" ;
-# USE DIN FALSE CELL "THE_MED_INTERFACE_0_gen_tx_fifos_2_THE_SD_SYNC_sync_qio_1" ;
-# USE DIN FALSE CELL "THE_MED_INTERFACE_0_gen_tx_fifos_0_THE_SD_SYNC_sync_qio_1" ;
-# PROHIBIT PRIMARY NET "THE_MED_INTERFACE_0_ff_rxfullclk_0" ;
-# PROHIBIT SECONDARY NET "THE_MED_INTERFACE_0_ff_rxfullclk_0" ;
-# PROHIBIT PRIMARY NET "THE_MED_INTERFACE_0_ff_rxfullclk_1" ;
-# PROHIBIT SECONDARY NET "THE_MED_INTERFACE_0_ff_rxfullclk_1" ;
-# PROHIBIT PRIMARY NET "THE_MED_INTERFACE_0_ff_rxfullclk_2" ;
-# PROHIBIT SECONDARY NET "THE_MED_INTERFACE_0_ff_rxfullclk_2" ;
-# PROHIBIT PRIMARY NET "THE_MED_INTERFACE_0_ff_rxfullclk_3" ;
-# PROHIBIT SECONDARY NET "THE_MED_INTERFACE_0_ff_rxfullclk_3" ;
-# REGION "REGION_PCS_LLC" "R95C2" 17 30 ;
-# UGROUP "THE_MED_INTERFACE_0/GROUP_PCS" BLKNAME THE_MED_INTERFACE_0 ;
-# LOCATE UGROUP "THE_MED_INTERFACE_0/GROUP_PCS" REGION "REGION_PCS_LLC" ;
-# MULTICYCLE FROM CELL "reset" TO CLKNET "THE_MED_INTERFACE_0_ff_rxfullclk_0" 150.000000 ns ;
-# MULTICYCLE FROM CELL "reset" TO CLKNET "THE_MED_INTERFACE_0_ff_rxfullclk_1" 150.000000 ns ;
-# MULTICYCLE FROM CELL "reset" TO CLKNET "THE_MED_INTERFACE_0_ff_rxfullclk_2" 150.000000 ns ;
-# MULTICYCLE FROM CELL "reset" TO CLKNET "THE_MED_INTERFACE_0_ff_rxfullclk_3" 150.000000 ns ;
-# MULTICYCLE FROM CELL "reset" TO CLKNET "THE_MED_INTERFACE_0_ff_txfullclk" 150.000000 ns ;
\ No newline at end of file
LOCATE COMP "ADO_TTL_43" SITE "AK16";\r
LOCATE COMP "ADO_TTL_44" SITE "AF18";\r
LOCATE COMP "ADO_TTL_45" SITE "AD16";\r
-LOCATE COMP "ADO_TTL_46" SITE "AJ15";\r
+# LOCATE COMP "ADO_TTL_46" SITE "AJ15"; #occupied by 1-wire monitor!\r
DEFINE PORT GROUP "ado_ttl_group" "ADO_TTL*" ;\r
IOBUF GROUP "ado_ttl_group" IO_TYPE=LVTTL33 PULLMODE=NONE ;\r
\r
+LOCATE COMP "ONEWIRE_F1" SITE "AJ15";\r
+IOBUF PORT "ONEWIRE_F1" IO_TYPE=LVTTL33 PULLMODE=UP;\r
\r
#################################################################\r
#LED next to FPGA\r
# DEFINE PORT GROUP "interttl_group" "INTERTTL*" ;\r
# IOBUF GROUP "interttl_group" IO_TYPE=LVTTL33 PULLMODE=NONE ;\r
\r
+\r
+\r
#################################################################\r
#LED\r
#################################################################\r
#####################################################################\r
FREQUENCY PORT "FCLK3" 100.000000 MHz;\r
FREQUENCY NET "serdes/ff_txhalfclk" 100.000000 MHz ;\r
-FREQUENCY NET "serdes/ff_rxhalfclk" 100.000000 MHz ;\r
-\r
+FREQUENCY NET "serdes/ff_rxhalfclk_0" 100.000000 MHz ;\r
+FREQUENCY NET "serdes/ff_rxhalfclk_1" 100.000000 MHz ;\r
+FREQUENCY NET "serdes/ff_rxhalfclk_2" 100.000000 MHz ;\r
+FREQUENCY NET "serdes/ff_rxhalfclk_3" 100.000000 MHz ;\r
+FREQUENCY NET "serdes_ff_txhalfclk" 100.000000 MHz ;\r
+FREQUENCY NET "serdes_ff_rxhalfclk_0" 100.000000 MHz ;\r
+FREQUENCY NET "serdes_ff_rxhalfclk_1" 100.000000 MHz ;\r
+FREQUENCY NET "serdes_ff_rxhalfclk_2" 100.000000 MHz ;\r
+FREQUENCY NET "serdes_ff_rxhalfclk_3" 100.000000 MHz ;\r
\r
#####################################################################\r
#Clock\r
NET DGOOD LOC ="H34"| IOSTANDARD = "LVTTL";
NET DINT LOC ="L31"| IOSTANDARD = "LVTTL";
NET DWAIT LOC ="H33"| IOSTANDARD = "LVTTL";
- NET ADO_LV_IN<0> LOC ="AC9" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_IN<1> LOC ="AC8" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_IN<2> LOC ="AG3" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_IN<3> LOC ="AF3" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_IN<4> LOC ="AF6" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_IN<5> LOC ="AE6" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_IN<6> LOC ="AF5" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_IN<7> LOC ="AF4" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_IN<8> LOC ="AL1" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_IN<9> LOC ="AK1" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_IN<10> LOC ="AJ2" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_IN<11> LOC ="AJ1" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_IN<12> LOC ="AB6" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_IN<13> LOC ="AB5" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_IN<14> LOC ="AC3" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_IN<15> LOC ="AC2" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_IN<16> LOC ="Y11" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_IN<17> LOC ="AA11" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_IN<18> LOC ="AD2" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_IN<19> LOC ="AD1" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_IN<20> LOC ="Y14" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_IN<21> LOC ="AA13" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_IN<22> LOC ="AC5" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_IN<23> LOC ="AC4" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_IN<24> LOC ="AF1" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_IN<25> LOC ="AE1" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_OUT<26> LOC ="AE3" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_OUT<27> LOC ="AE2" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_OUT<28> LOC ="AD6" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_OUT<29> LOC ="AD5" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_OUT<30> LOC ="AC7" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_OUT<31> LOC ="AB8" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_OUT<32> LOC ="Y16" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_OUT<33> LOC ="AA15" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_OUT<34> LOC ="AE4" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_OUT<35> LOC ="AD4" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_OUT<36> LOC ="AH3" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_OUT<37> LOC ="AH2" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_OUT<38> LOC ="AG2" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_OUT<39> LOC ="AG1" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_OUT<40> LOC ="AK3" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_OUT<41> LOC ="AK2" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_OUT<42> LOC ="AF8" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_OUT<43> LOC ="AE8" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_OUT<44> LOC ="AH5" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_OUT<45> LOC ="AH4" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_OUT<46> LOC ="AB13" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_OUT<47> LOC ="AB12" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_OUT<48> LOC ="AM2" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_OUT<49> LOC ="AM1" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_OUT<50> LOC ="AG8" | IOSTANDARD = "LVDS_25";
- NET ADO_LV_OUT<51> LOC ="AG7" | IOSTANDARD = "LVDS_25";
-# NET ADO_LV_OUT<52> LOC ="AM3" | IOSTANDARD = "LVDS_25";
-# NET ADO_LV_OUT<53> LOC ="AL3" | IOSTANDARD = "LVDS_25";
-# NET ADO_LV_OUT<54> LOC ="AK22" | IOSTANDARD = "LVDS_25";
-# NET ADO_LV_OUT<55> LOC ="AK23" | IOSTANDARD = "LVDS_25";
-# NET ADO_LV_OUT<56> LOC ="AL28" | IOSTANDARD = "LVDS_25";
-# NET ADO_LV_OUT<57> LOC ="AL29" | IOSTANDARD = "LVDS_25";
+ NET ADO_LV_IN<0> LOC ="AC9" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_IN<1> LOC ="AC8" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_IN<2> LOC ="AG3" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_IN<3> LOC ="AF3" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_IN<4> LOC ="AF6" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_IN<5> LOC ="AE6" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_IN<6> LOC ="AF5" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_IN<7> LOC ="AF4" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_IN<8> LOC ="AL1" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_IN<9> LOC ="AK1" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_IN<10> LOC ="AJ2" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_IN<11> LOC ="AJ1" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_IN<12> LOC ="AB6" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_IN<13> LOC ="AB5" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_IN<14> LOC ="AC3" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_IN<15> LOC ="AC2" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_IN<16> LOC ="Y11" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_IN<17> LOC ="AA11" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_IN<18> LOC ="AD2" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_IN<19> LOC ="AD1" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_IN<20> LOC ="Y14" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_IN<21> LOC ="AA13" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_IN<22> LOC ="AC5" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_IN<23> LOC ="AC4" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_IN<24> LOC ="AF1" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_IN<25> LOC ="AE1" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_IN<26> LOC ="AE3" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_OUT<27> LOC ="AE2" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_OUT<28> LOC ="AD6" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_OUT<29> LOC ="AD5" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_OUT<30> LOC ="AC7" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_OUT<31> LOC ="AB8" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_OUT<32> LOC ="Y16" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_OUT<33> LOC ="AA15" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_OUT<34> LOC ="AE4" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_OUT<35> LOC ="AD4" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_OUT<36> LOC ="AH3" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_OUT<37> LOC ="AH2" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_OUT<38> LOC ="AG2" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_OUT<39> LOC ="AG1" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_OUT<40> LOC ="AK3" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_OUT<41> LOC ="AK2" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_OUT<42> LOC ="AF8" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_OUT<43> LOC ="AE8" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_OUT<44> LOC ="AH5" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_OUT<45> LOC ="AH4" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_OUT<46> LOC ="AB13" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_OUT<47> LOC ="AB12" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_OUT<48> LOC ="AM2" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_OUT<49> LOC ="AM1" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_OUT<50> LOC ="AG8" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_OUT<51> LOC ="AG7" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_OUT<52> LOC ="AM3" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_OUT<53> LOC ="AL3" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_OUT<54> LOC ="AK22" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_OUT<55> LOC ="AK23" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_OUT<56> LOC ="AL28" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
+ NET ADO_LV_OUT<57> LOC ="AL29" | IOSTANDARD = "LVTTL" | SLEW = "FAST";
# NET ADO_LV<58> LOC ="AP25";
# NET ADO_LV<59> LOC ="AP26";
# NET ADO_LV<60> LOC ="AJ27";
# NET ADO_LV<61> LOC ="AH27";
+#
+
NET "VIRT_CLK" TNM_NET = "VIRT_CLK";
TIMESPEC "TS_CLK" = PERIOD "VIRT_CLK" 10 ns HIGH 50 %;
-NET "TLK_CLK" TNM_NET = "TLK_CLK";
-TIMESPEC "TS_TLK_CLK" = PERIOD "TLK_CLK" 10 ns HIGH 50 %;
-NET "TLK_RX_CLK" TNM_NET = "TLK_RX_CLK";
-TIMESPEC "TS_TLK_RX_CLK" = PERIOD "TLK_RX_CLK" 10 ns HIGH 50 %;
+# NET "TLK_CLK" TNM_NET = "TLK_CLK";
+# TIMESPEC "TS_TLK_CLK" = PERIOD "TLK_CLK" 10 ns HIGH 50 %;
+# NET "TLK_RX_CLK" TNM_NET = "TLK_RX_CLK";
+# TIMESPEC "TS_TLK_RX_CLK" = PERIOD "TLK_RX_CLK" 10 ns HIGH 50 %;
# INST "TLK_TXD<*>" TNM = "TLK_TX";
# TIMEGRP "TLK_TX" OFFSET = OUT 7 ns AFTER "TLK_CLK" HIGH;
# TIMEGRP "TLK_RX" OFFSET = IN 3.2 ns VALID 6 ns BEFORE "TLK_RX_CLK";
+
+INST "ADO_LV_IN<*>" TNM = "VIRT_CLK_IN";
+INST "ADO_LV_OUT<*>" TNM = "VIRT_CLK_OUT";
+TIMEGRP "VIRT_CLK_OUT" OFFSET = OUT 9 ns AFTER "VIRT_CLK" HIGH;
+TIMEGRP "VIRT_CLK_IN" OFFSET = IN 3.2 ns VALID 6 ns BEFORE "VIRT_CLK";
\ No newline at end of file
--Register Map
--00 Control Register 0 Conversion Enable 1 single measurement 2 reset min/max/overview, 3 compare enable
--01 Overview 1 nibble for each channel: 0 Voltage ok, 1 Voltage too low, 2 Voltage too high
---10-17 Measurements 0-11 current value, 12-21 min value(10bit), 22-31 max value(10bit)
+--10-17 Measurements 0-11 current value
+--18-1F Measurements min/max 0-11 minimum, 16-27 maximum
--20-27 Voltage Range CTRL 0-11 min value 16-27 max value
CLOCK_FREQUENCY : integer := 100; --MHz
PRESET_RANGES_CH0 : std_logic_vector(23 downto 0) := x"A28_960" ; --5V/2 - 2.4-2.6
PRESET_RANGES_CH1 : std_logic_vector(23 downto 0) := x"A28_960" ; --5V/2 - 2.4-2.6
- PRESET_RANGES_CH2 : std_logic_vector(23 downto 0) := x"D48_ED8" ; --3.5 - 3.4-3.8
- PRESET_RANGES_CH3 : std_logic_vector(23 downto 0) := x"C80_D48" ; --3.3 - 3.2-3.4
- PRESET_RANGES_CH4 : std_logic_vector(23 downto 0) := x"510_6A0" ; --1.4 - 1.3-1.7
- PRESET_RANGES_CH5 : std_logic_vector(23 downto 0) := x"480_4E0" ; --1.2 - 1.15-1.25
- PRESET_RANGES_CH6 : std_logic_vector(23 downto 0) := x"B50_C10" ; --3.0 - 2.9-3.1
+ PRESET_RANGES_CH2 : std_logic_vector(23 downto 0) := x"ED8_D48" ; --3.5 - 3.4-3.8
+ PRESET_RANGES_CH3 : std_logic_vector(23 downto 0) := x"D48_C80" ; --3.3 - 3.2-3.4
+ PRESET_RANGES_CH4 : std_logic_vector(23 downto 0) := x"6A0_510" ; --1.4 - 1.3-1.7
+ PRESET_RANGES_CH5 : std_logic_vector(23 downto 0) := x"4E0_480" ; --1.2 - 1.15-1.25
+ PRESET_RANGES_CH6 : std_logic_vector(23 downto 0) := x"C10_B50" ; --3.0 - 2.9-3.1
PRESET_RANGES_CH7 : std_logic_vector(23 downto 0) := x"FFF_000" ---3.0 - ???-???
);
port(
signal ram_write : std_logic;
signal ram_addr : std_logic_vector(2 downto 0);
- signal ram_data : std_logic_vector(31 downto 0);
- signal ram_data_out : std_logic_vector(31 downto 0);
+ signal ram_data : std_logic_vector(35 downto 0);
+ signal ram_data_out : std_logic_vector(35 downto 0);
signal timecounter : unsigned(9 downto 0);
signal current_channel : std_logic_vector(2 downto 0);
signal last_channel : std_logic_vector(2 downto 0);
signal current_minimum : std_logic_vector(11 downto 0);
signal current_maximum : std_logic_vector(11 downto 0);
signal status_overview : std_logic_vector(31 downto 0);
- signal value_ram_data : std_logic_vector(31 downto 0);
+ signal value_ram_data : std_logic_vector(35 downto 0);
signal value_ram_addr : std_logic_vector(2 downto 0);
signal last_DAT_READ_EN_IN : std_logic;
+ signal last_last_DAT_READ_EN_IN : std_logic;
+
+ type value_ram_t is array(7 downto 0) of std_logic_vector(35 downto 0);
+ signal value_ram : value_ram_t := (x"000000000",x"000000001",x"000000002",x"000000003",x"000000004",
+ x"000000005",x"000000006",x"000000007");
type range_ram_t is array(7 downto 0) of std_logic_vector(23 downto 0);
- signal range_ram : range_ram_t ;--:= (PRESET_RANGES_CH7,PRESET_RANGES_CH6,PRESET_RANGES_CH5,PRESET_RANGES_CH4,
- -- PRESET_RANGES_CH3,PRESET_RANGES_CH2,PRESET_RANGES_CH1,PRESET_RANGES_CH0);
+ signal range_ram : range_ram_t := (PRESET_RANGES_CH7,PRESET_RANGES_CH6,PRESET_RANGES_CH5,PRESET_RANGES_CH4,
+ PRESET_RANGES_CH3,PRESET_RANGES_CH2,PRESET_RANGES_CH1,PRESET_RANGES_CH0);
signal first_sequence_after_stop : std_logic;
begin
state_bits(2) <= '1' when state = WAITING else '0';
- THE_VALUE_RAM : ram_dp
- generic map(
- depth => 3,
- width => 32
- )
- port map(
- CLK => CLK,
- wr1 => ram_write,
- a1 => ram_addr,
- din1 => ram_data,
- dout1 => ram_data_out,
- a2 => value_ram_addr,
- dout2 => value_ram_data
- );
+ THE_VALUE_RAM : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if ram_write = '1' then
+ value_ram(to_integer(unsigned(ram_addr))) <= ram_data;
+ end if;
+ ram_data_out <= value_ram(to_integer(unsigned(ram_addr)));
+ value_ram_data <= value_ram(to_integer(unsigned(value_ram_addr)));
+ end if;
+ end process;
- ram_addr <= std_logic_vector(unsigned(last_channel) - to_unsigned(1,1));
+-- THE_VALUE_RAM : ram_dp
+-- generic map(
+-- depth => 3,
+-- width => 36
+-- )
+-- port map(
+-- CLK => CLK,
+-- wr1 => ram_write,
+-- a1 => ram_addr,
+-- din1 => ram_data,
+-- dout1 => ram_data_out,
+-- a2 => value_ram_addr,
+-- dout2 => value_ram_data
+-- );
+
+ ram_addr <= std_logic_vector(unsigned(last_channel));
value_ram_addr <= range_ram_addr;
THE_RANGE_RAM : process(CLK)
begin
if rising_edge(CLK) then
- if range_ram_wr = '1' then
- range_ram(to_integer(unsigned(range_ram_addr))) <= range_ram_data;
- end if;
+-- if range_ram_wr = '1' then
+-- range_ram(to_integer(unsigned(range_ram_addr))) <= range_ram_data;
+-- end if;
range_ram_data_out <= range_ram(to_integer(unsigned(range_ram_addr)));
current_minimum <= range_ram(to_integer(unsigned(last_channel)))(11 downto 0);
current_maximum <= range_ram(to_integer(unsigned(last_channel)))(23 downto 12);
ram_data <= ram_data_out;
ram_write <= not first_sequence_after_stop;
ram_data(11 downto 0) <= input_data;
- if unsigned(input_data(11 downto 2)) < unsigned(ram_data_out(21 downto 12)) or real_conv_reset = '1' then
- ram_data(21 downto 12) <= input_data(11 downto 2);
+ if unsigned(input_data(11 downto 0)) < unsigned(ram_data_out(23 downto 12)) or real_conv_reset = '1' then
+ ram_data(23 downto 12) <= input_data(11 downto 0);
end if;
- if unsigned(input_data(11 downto 2)) > unsigned(ram_data_out(31 downto 22)) or real_conv_reset = '1' then
- ram_data(31 downto 22) <= input_data(11 downto 2);
+ if unsigned(input_data(11 downto 0)) > unsigned(ram_data_out(35 downto 24)) or real_conv_reset = '1' then
+ ram_data(35 downto 24) <= input_data(11 downto 0);
end if;
if conv_compare_enable = '1' and first_sequence_after_stop = '0' then
range_ram_wr <= '0';
conv_single <= conv_single and not conv_single_clr;
conv_reset <= conv_reset and not conv_reset_clr;
- range_ram_addr <= DAT_ADDR_IN(2 downto 0);
- range_ram_data <= DAT_DATA_IN(27 downto 16) & DAT_DATA_IN(11 downto 0);
last_DAT_READ_EN_IN <= '0';
+ last_last_DAT_READ_EN_IN <= '0';
+
+ if DAT_WRITE_EN_IN = '1' or DAT_READ_EN_IN = '1' then
+ range_ram_addr <= DAT_ADDR_IN(2 downto 0);
+ range_ram_data <= DAT_DATA_IN(27 downto 16) & DAT_DATA_IN(11 downto 0);
+ end if;
if DAT_WRITE_EN_IN = '1' then
if DAT_ADDR_IN = "000000" then
DAT_UNKNOWN_ADDR_OUT <= '1';
end if;
end if;
- if DAT_READ_EN_IN = '1' or last_DAT_READ_EN_IN = '1' then
+ if DAT_READ_EN_IN = '1' or last_DAT_READ_EN_IN = '1' or last_last_DAT_READ_EN_IN = '1' then
if DAT_ADDR_IN(5 downto 0) = "000000" then
- DAT_DATA_OUT <= (0 => conv_enabled, 1 => conv_single, 3 => conv_compare_enable, others => '0');
- DAT_DATAREADY_OUT <= '1';
+ DAT_DATA_OUT <= (0 => conv_enabled, 1 => conv_single, 3 => conv_compare_enable, others => '0');
+ DAT_DATAREADY_OUT <= '1';
elsif DAT_ADDR_IN(5 downto 0) = "000001" then
- DAT_DATA_OUT <= status_overview;
- DAT_DATAREADY_OUT <= '1';
+ DAT_DATA_OUT <= status_overview;
+ DAT_DATAREADY_OUT <= '1';
elsif DAT_ADDR_IN(5 downto 3) = "010" then --"010000"
- DAT_DATA_OUT(31 downto 0) <= value_ram_data;
- if DAT_READ_EN_IN = '1' then
- last_DAT_READ_EN_IN <= '1';
- else
- last_DAT_READ_EN_IN <= '0';
+ last_DAT_READ_EN_IN <= DAT_READ_EN_IN;
+ last_last_DAT_READ_EN_IN <= last_DAT_READ_EN_IN;
+ if last_last_DAT_READ_EN_IN = '1' then
+ DAT_DATAREADY_OUT <= '1';
+ DAT_DATA_OUT <= x"00000" & value_ram_data(11 downto 0);
+ end if;
+ elsif DAT_ADDR_IN(5 downto 3) = "011" then --"010000"
+ last_DAT_READ_EN_IN <= DAT_READ_EN_IN;
+ last_last_DAT_READ_EN_IN <= last_DAT_READ_EN_IN;
+ if last_last_DAT_READ_EN_IN = '1' then
DAT_DATAREADY_OUT <= '1';
+ DAT_DATA_OUT <= x"0" & value_ram_data(35 downto 24) & x"0" & value_ram_data(23 downto 12);
end if;
elsif DAT_ADDR_IN(5 downto 3) = "100" then --"100000"
- DAT_DATA_OUT(11 downto 0) <= range_ram_data_out(11 downto 0);
- DAT_DATA_OUT(15 downto 12) <= (others => '0');
- DAT_DATA_OUT(27 downto 16) <= range_ram_data_out(23 downto 12);
- DAT_DATA_OUT(31 downto 28) <= (others => '0');
- if DAT_READ_EN_IN = '1' then
- last_DAT_READ_EN_IN <= '1';
- else
- last_DAT_READ_EN_IN <= '0';
+ last_DAT_READ_EN_IN <= DAT_READ_EN_IN;
+ last_last_DAT_READ_EN_IN <= last_DAT_READ_EN_IN;
+ if last_last_DAT_READ_EN_IN = '1' then
DAT_DATAREADY_OUT <= '1';
+ DAT_DATA_OUT <= x"0" & range_ram_data_out(23 downto 12) & x"0" & range_ram_data_out(11 downto 0);
end if;
else
DAT_UNKNOWN_ADDR_OUT <= '1';
-- address <= x"0008";
-- reghigh <= x"DEAD";
-- reglow <= x"AFFE";
- reg_F0 <= x"5e1d"; --x"0001";
- reg_F1 <= x"1111";
- reg_F2 <= x"2222";--xor_all(APL_DATA_IN) & "000000000000011";
- reg_F3 <= x"3333";
- APL_DTYPE_OUT <= x"F";
- APL_TARGET_ADDRESS_OUT <= x"ffff"; --TARGET_ADDRESS;
+ reg_F0 <= x"8010"; --x"0001";
+ reg_F1 <= x"8004";
+ reg_F2 <= x"0000";--xor_all(APL_DATA_IN) & "000000000000011";
+ reg_F3 <= x"0000";
+ APL_DTYPE_OUT <= x"A";
+ APL_TARGET_ADDRESS_OUT <= x"f003"; --TARGET_ADDRESS;
process(current_state)
begin
end process;
- PROC_READ_OUT : process(timing, CLK)
- begin
- if timing < 3000 then
- buf_APL_READ_OUT <= '0';
- elsif rising_edge(CLK) then
- buf_APL_READ_OUT <= not buf_APL_READ_OUT;
- end if;
- end process;
+-- PROC_READ_OUT : process(timing, CLK)
+-- begin
+-- if timing < 3000 then
+-- buf_APL_READ_OUT <= '0';
+-- elsif rising_edge(CLK) then
+-- buf_APL_READ_OUT <= not buf_APL_READ_OUT;
+-- end if;
+-- end process;
- APL_READ_OUT <= buf_APL_READ_OUT;
+-- APL_READ_OUT <= buf_APL_READ_OUT;
+APL_READ_OUT <= '1';
APL_ERROR_PATTERN_OUT <= x"12345678";
--APL_DATA_OUT <= reg_counter;
end entity;
architecture trb_net16_addresses_arch of trb_net16_addresses is
+ -- Placer Directives
+ attribute HGROUP : string;
+ -- for whole architecture
+ attribute HGROUP of trb_net16_addresses_arch : architecture is "HUBLOCIG_group";
+
+
component ram_16x16_dp is
generic(
INIT0 : std_logic_vector(15 downto 0) := x"0000";
signal fifo_to_apl_read : std_logic;
signal fifo_to_apl_full : std_logic;
signal fifo_to_apl_empty : std_logic;
+ signal next_fifo_to_apl_data_out : std_logic_vector(15 downto 0);
+ signal next_fifo_to_apl_packet_num_out : std_logic_vector(1 downto 0);
+ signal next_fifo_to_apl_full : std_logic;
+ signal next_fifo_to_apl_empty : std_logic;
+ signal next_last_fifo_to_apl_read: std_logic;
signal saved_fifo_to_apl_packet_type : std_logic_vector(2 downto 0);
signal current_fifo_to_apl_packet_type : std_logic_vector(2 downto 0);
INT_SLAVE_PACKET_NUM_OUT <= (others => '0');
end generate;
----------------------------------------
--- fifo to internal
----------------------------------------
-
- CHECK_BUFFER3: if FIFO_TO_INT_DEPTH >0 generate
- FIFO_TO_INT: trb_net16_fifo
- generic map (
- DEPTH => FIFO_TO_INT_DEPTH,
- USE_VENDOR_CORES => USE_VENDOR_CORES)
- port map (
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- DATA_IN => fifo_to_int_data_in,
- PACKET_NUM_IN => fifo_to_int_packet_num_in,
- WRITE_ENABLE_IN => fifo_to_int_write,
- DATA_OUT => fifo_to_int_data_out,
- PACKET_NUM_OUT => fifo_to_int_packet_num_out,
- READ_ENABLE_IN => fifo_to_int_read,
- FULL_OUT => fifo_to_int_full,
- EMPTY_OUT => fifo_to_int_empty
- );
- end generate;
-
- CHECK_BUFFER4: if FIFO_TO_INT_DEPTH =0 generate
- FIFO_TO_INT: trb_net16_dummy_fifo
- port map (
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- DATA_IN => fifo_to_int_data_in,
- PACKET_NUM_IN => fifo_to_int_packet_num_in,
- WRITE_ENABLE_IN => fifo_to_int_write,
- DATA_OUT => fifo_to_int_data_out,
- PACKET_NUM_OUT => fifo_to_int_packet_num_out,
- READ_ENABLE_IN => fifo_to_int_read,
- FULL_OUT => fifo_to_int_full,
- EMPTY_OUT => fifo_to_int_empty
- );
- end generate;
-
STAT_FIFO_TO_INT(2 downto 0) <= fifo_to_int_data_in(2 downto 0);
STAT_FIFO_TO_INT(3) <= fifo_to_int_write;
STAT_FIFO_TO_INT(6 downto 4) <= buf_INT_MASTER_PACKET_NUM_OUT;
STAT_FIFO_TO_INT(25) <= next_INT_MASTER_DATAREADY_OUT;
STAT_FIFO_TO_INT(28 downto 26) <= state_bits_to_int;
STAT_FIFO_TO_INT(31 downto 29) <= state_bits_to_apl;
----------------------------------------
--- fifo to apl
----------------------------------------
-
- CHECK_BUFFER5: if FIFO_TO_APL_DEPTH >0 generate
- FIFO_TO_APL: trb_net16_fifo
- generic map (
- DEPTH => FIFO_TO_APL_DEPTH,
- USE_VENDOR_CORES => USE_VENDOR_CORES)
- port map (
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- DATA_IN => fifo_to_apl_data_in,
- PACKET_NUM_IN => fifo_to_apl_packet_num_in,
- WRITE_ENABLE_IN => fifo_to_apl_write,
- DATA_OUT => fifo_to_apl_data_out,
- PACKET_NUM_OUT => fifo_to_apl_packet_num_out,
- READ_ENABLE_IN => fifo_to_apl_read,
- FULL_OUT => fifo_to_apl_full,
- EMPTY_OUT => fifo_to_apl_empty
- );
- end generate;
-
- CHECK_BUFFER6: if FIFO_TO_APL_DEPTH =0 generate
- FIFO_TO_APL: trb_net16_dummy_fifo
- port map (
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- DATA_IN => fifo_to_apl_data_in,
- PACKET_NUM_IN => fifo_to_apl_packet_num_in,
- WRITE_ENABLE_IN => fifo_to_apl_write,
- DATA_OUT => fifo_to_apl_data_out,
- PACKET_NUM_OUT => fifo_to_apl_packet_num_out,
- READ_ENABLE_IN => fifo_to_apl_read,
- FULL_OUT => fifo_to_apl_full,
- EMPTY_OUT => fifo_to_apl_empty
- );
- end generate;
STAT_FIFO_TO_APL(2 downto 0) <= fifo_to_apl_data_in(2 downto 0);
STAT_FIFO_TO_APL(3) <= fifo_to_apl_write;
---------------------------------------
-- a sbuf (to_int direction)
---------------------------------------
- gen_int_sbuf : if SECURE_MODE_TO_INT = 1 generate
+-- gen_int_sbuf : if SECURE_MODE_TO_INT = 1 generate
SBUF: trb_net16_sbuf
generic map (
VERSION => SBUF_VERSION)
end if;
end if;
end process;
- end generate;
+-- end generate;
- gen_int_nonsbuf : if SECURE_MODE_TO_INT = 0 generate
- buf_INT_MASTER_DATAREADY_OUT <= next_INT_MASTER_DATAREADY_OUT;
- INT_MASTER_DATA_OUT <= next_INT_MASTER_DATA_OUT;
- buf_INT_MASTER_PACKET_NUM_OUT <= next_INT_MASTER_PACKET_NUM_OUT;
- sbuf_free <= INT_MASTER_READ_IN;
- end generate;
+-- gen_int_nonsbuf : if SECURE_MODE_TO_INT = 0 generate
+-- buf_INT_MASTER_DATAREADY_OUT <= next_INT_MASTER_DATAREADY_OUT;
+-- INT_MASTER_DATA_OUT <= next_INT_MASTER_DATA_OUT;
+-- buf_INT_MASTER_PACKET_NUM_OUT <= next_INT_MASTER_PACKET_NUM_OUT;
+-- sbuf_free <= INT_MASTER_READ_IN;
+-- end generate;
INT_MASTER_PACKET_NUM_OUT <= buf_INT_MASTER_PACKET_NUM_OUT;
INT_MASTER_DATAREADY_OUT <= buf_INT_MASTER_DATAREADY_OUT;
---------------------------------------
-- a sbuf (to_apl direction)
---------------------------------------
- gen_apl_sbuf : if SECURE_MODE_TO_APL = 1 generate
+-- gen_apl_sbuf : if SECURE_MODE_TO_APL = 1 generate
SBUF_TO_APL: trb_net16_sbuf
generic map (
VERSION => SBUF_VERSION)
end if;
end if;
end process;
- end generate;
+-- end generate;
- gen_apl_nonsbuf : if SECURE_MODE_TO_APL = 0 generate
- reg_APL_DATAREADY_OUT <= next_APL_DATAREADY_OUT;
- reg_APL_DATA_OUT <= next_APL_DATA_OUT;
- reg_APL_PACKET_NUM_OUT <= next_APL_PACKET_NUM_OUT;
- reg_APL_TYP_OUT <= next_APL_TYP_OUT;
- sbuf_to_apl_free <= APL_READ_IN;
- end generate;
+-- gen_apl_nonsbuf : if SECURE_MODE_TO_APL = 0 generate
+-- reg_APL_DATAREADY_OUT <= next_APL_DATAREADY_OUT;
+-- reg_APL_DATA_OUT <= next_APL_DATA_OUT;
+-- reg_APL_PACKET_NUM_OUT <= next_APL_PACKET_NUM_OUT;
+-- reg_APL_TYP_OUT <= next_APL_TYP_OUT;
+-- sbuf_to_apl_free <= APL_READ_IN;
+-- end generate;
next_APL_DATA_OUT <= fifo_to_apl_data_out;
next_APL_PACKET_NUM_OUT <= fifo_to_apl_long_packet_num_out;
end if;
end process;
+---------------------------------------
+-- fifo to apl
+---------------------------------------
+
+ GEN_FIFO_TO_APL: if FIFO_TO_APL_DEPTH >0 generate
+ FIFO_TO_APL: trb_net16_fifo
+ generic map (
+ DEPTH => FIFO_TO_APL_DEPTH,
+ USE_VENDOR_CORES => USE_VENDOR_CORES)
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ DATA_IN => fifo_to_apl_data_in,
+ PACKET_NUM_IN => fifo_to_apl_packet_num_in,
+ WRITE_ENABLE_IN => fifo_to_apl_write,
+ DATA_OUT => next_fifo_to_apl_data_out,
+ PACKET_NUM_OUT => next_fifo_to_apl_packet_num_out,
+ READ_ENABLE_IN => fifo_to_apl_read,
+ FULL_OUT => fifo_to_apl_full,
+ EMPTY_OUT => next_fifo_to_apl_empty
+ );
+ end generate;
+
+ GEN_DUMMY_FIFO_TO_APL: if FIFO_TO_APL_DEPTH = 0 generate
+ FIFO_TO_APL: trb_net16_dummy_fifo
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ DATA_IN => fifo_to_apl_data_in,
+ PACKET_NUM_IN => fifo_to_apl_packet_num_in,
+ WRITE_ENABLE_IN => fifo_to_apl_write,
+ DATA_OUT => next_fifo_to_apl_data_out,
+ PACKET_NUM_OUT => next_fifo_to_apl_packet_num_out,
+ READ_ENABLE_IN => fifo_to_apl_read,
+ FULL_OUT => fifo_to_apl_full,
+ EMPTY_OUT => next_fifo_to_apl_empty
+ );
+ end generate;
---------------------------------------
--- keep track of fifo read operations
+-- keep track of fifo to apl read operations
---------------------------------------
process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
fifo_to_apl_read_before <= '0';
- last_fifo_to_apl_read <= '0';
elsif CLK_EN = '1' then
- last_fifo_to_apl_read <= fifo_to_apl_read;
- if fifo_to_apl_read = '1' then
+ if next_last_fifo_to_apl_read = '1' then
fifo_to_apl_read_before <= '1';
elsif sbuf_to_apl_free = '1' or throw_away = '1' then
fifo_to_apl_read_before <= '0';
end if;
end process;
+
+ PROC_NEXT_LAST_FIFO_TO_APL_READ : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if (fifo_to_apl_read = '1' and next_fifo_to_apl_empty = '0') then
+ next_last_fifo_to_apl_read <= '1';
+ else
+ next_last_fifo_to_apl_read <= '0';
+ end if;
+ end if;
+ end process;
+
+
+ PROC_SYNC_FIFO_TO_APL_OUTPUTS : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if next_last_fifo_to_apl_read = '1' then
+ fifo_to_apl_data_out <= next_fifo_to_apl_data_out;
+ fifo_to_apl_packet_num_out <= next_fifo_to_apl_packet_num_out;
+ end if;
+ end if;
+ end process;
+
+ PROC_LAST_FIFO_TO_APL_READ : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ last_fifo_to_apl_read <= '0';
+ fifo_to_apl_empty <= '1';
+ else
+ last_fifo_to_apl_read <= next_last_fifo_to_apl_read;
+ fifo_to_apl_empty <= next_fifo_to_apl_empty;
+ end if;
+ end if;
+ end process;
+
+---------------------------------------
+-- fifo to internal
+---------------------------------------
+
+ GEN_FIFO_TO_INT: if FIFO_TO_INT_DEPTH >0 generate
+ FIFO_TO_INT: trb_net16_fifo
+ generic map (
+ DEPTH => FIFO_TO_INT_DEPTH,
+ USE_VENDOR_CORES => USE_VENDOR_CORES)
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ DATA_IN => fifo_to_int_data_in,
+ PACKET_NUM_IN => fifo_to_int_packet_num_in,
+ WRITE_ENABLE_IN => fifo_to_int_write,
+ DATA_OUT => fifo_to_int_data_out,
+ PACKET_NUM_OUT => fifo_to_int_packet_num_out,
+ READ_ENABLE_IN => fifo_to_int_read,
+ FULL_OUT => fifo_to_int_full,
+ EMPTY_OUT => fifo_to_int_empty
+ );
+ end generate;
+
+ GEN_DUMMY_FIFO_TO_INT: if FIFO_TO_INT_DEPTH =0 generate
+ FIFO_TO_INT: trb_net16_dummy_fifo
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ DATA_IN => fifo_to_int_data_in,
+ PACKET_NUM_IN => fifo_to_int_packet_num_in,
+ WRITE_ENABLE_IN => fifo_to_int_write,
+ DATA_OUT => fifo_to_int_data_out,
+ PACKET_NUM_OUT => fifo_to_int_packet_num_out,
+ READ_ENABLE_IN => fifo_to_int_read,
+ FULL_OUT => fifo_to_int_full,
+ EMPTY_OUT => fifo_to_int_empty
+ );
+ end generate;
+
+---------------------------------------
+-- keep track of fifo to int read operations
+---------------------------------------
+
process(CLK)
begin
if rising_edge(CLK) then
---------------------------------------
to_apl : process(fifo_to_apl_full, reg_INT_SLAVE_READ_OUT, INT_SLAVE_DATAREADY_IN, fifo_to_apl_empty,
fifo_to_apl_long_packet_num_out, state_to_apl, reg_APL_TYP_OUT, reg_APL_PACKET_NUM_OUT,
- sbuf_to_apl_free, INT_SLAVE_DATA_IN, INT_SLAVE_PACKET_NUM_IN, APL_MY_ADDRESS_IN,
+ sbuf_to_apl_free, INT_SLAVE_DATA_IN, INT_SLAVE_PACKET_NUM_IN, APL_MY_ADDRESS_IN, APL_READ_IN,
reg_APL_DATAREADY_OUT, slave_running, fifo_to_apl_read_before, throw_away,state_to_int,
- saved_fifo_to_apl_packet_type,master_start, last_fifo_to_apl_read)
+ saved_fifo_to_apl_packet_type,master_start, last_fifo_to_apl_read, sbuf_to_apl_next_READ)
begin
reg_INT_SLAVE_READ_OUT <= not fifo_to_apl_full;
fifo_to_apl_write <= reg_INT_SLAVE_READ_OUT and INT_SLAVE_DATAREADY_IN;
end if;
end if;
when sa_WRONG_ADDR =>
- fifo_to_apl_read <= not fifo_to_apl_empty;
+ fifo_to_apl_read <= '1'; --not fifo_to_apl_empty;
throw_away <= '1';
if saved_fifo_to_apl_packet_type = TYPE_TRM and fifo_to_apl_long_PACKET_NUM_OUT = c_F3 and last_fifo_to_apl_read = '1' then
next_state_to_apl <= sa_INACTIVE;
else
next_APL_DATAREADY_OUT <= fifo_to_apl_read_before and sbuf_to_apl_free;
end if;
- fifo_to_apl_read <= not fifo_to_apl_empty and not (fifo_to_apl_read_before and not (sbuf_to_apl_free or throw_away));
+ fifo_to_apl_read <= sbuf_to_apl_free and not ((next_last_fifo_to_apl_read or fifo_to_apl_read_before) and not APL_READ_IN);
+ --not ( (not sbuf_to_apl_free or not APL_READ_IN));-- sbuf_to_apl_free);
+ --fifo_to_apl_read <= not (fifo_to_apl_read_before and not sbuf_to_apl_free); --not fifo_to_apl_empty and not (fifo_to_apl_read_before and not (sbuf_to_apl_free or throw_away))
if reg_APL_TYP_OUT = TYPE_TRM and reg_APL_PACKET_NUM_OUT = c_F3 and sbuf_to_apl_free = '1' then
next_state_to_apl <= sa_INACTIVE;
slave_end <= '1';
REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";
REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";
- REGIO_USE_1WIRE_INTERFACE: integer := c_YES
+ REGIO_USE_1WIRE_INTERFACE: integer := c_YES --c_YES,c_NO,c_MONITOR
);
port(
REGIO_IDRAM_ADDR_IN : in std_logic_vector(2 downto 0) := "000";
REGIO_IDRAM_WR_IN : in std_logic := '0';
REGIO_ONEWIRE_INOUT : inout std_logic;
- --Additional r/w access to ctrl registers
- REGIO_EXT_REG_DATA_IN : in std_logic_vector(31 downto 0) := (others => '0');
- REGIO_EXT_REG_DATA_OUT : out std_logic_vector(31 downto 0);
- REGIO_EXT_REG_WRITE_IN : in std_logic := '0';
- REGIO_EXT_REG_ADDR_IN : in std_logic_vector(7 downto 0) := (others => '0');
-
+ REGIO_ONEWIRE_MONITOR_IN : in std_logic;
+ REGIO_ONEWIRE_MONITOR_OUT : out std_logic;
+ --Debugging & Status information
STAT_DEBUG_IPU : out std_logic_vector (31 downto 0);
STAT_DEBUG_1 : out std_logic_vector (31 downto 0);
STAT_DEBUG_2 : out std_logic_vector (31 downto 0);
architecture trb_net16_endpoint_hades_full_arch of trb_net16_endpoint_hades_full is
+ component trb_net_onewire_listener is
+ port(
+ CLK : in std_logic;
+ CLK_EN : in std_logic;
+ RESET : in std_logic;
+ MONITOR_IN : in std_logic;
+ DATA_OUT : out std_logic_vector(15 downto 0);
+ ADDR_OUT : out std_logic_vector(2 downto 0);
+ WRITE_OUT: out std_logic;
+ TEMP_OUT : out std_logic_vector(11 downto 0);
+ STAT : out std_logic_vector(31 downto 0)
+ );
+ end component;
+
component trb_net_onewire is
generic(
USE_TEMPERATURE_READOUT : integer range 0 to 1 := 1;
DAT_UNKNOWN_ADDR_IN : in std_logic;
DAT_TIMEOUT_OUT : out std_logic;
- --Additional write access to ctrl registers
- EXT_REG_DATA_IN : in std_logic_vector(31 downto 0);
- EXT_REG_DATA_OUT : out std_logic_vector(31 downto 0);
- EXT_REG_WRITE_IN : in std_logic;
- EXT_REG_ADDR_IN : in std_logic_vector(7 downto 0);
STAT : out std_logic_vector(31 downto 0);
STAT_ADDR_DEBUG : out std_logic_vector(15 downto 0)
);
DAT_UNKNOWN_ADDR_IN => REGIO_UNKNOWN_ADDR_IN,
DAT_TIMEOUT_OUT => REGIO_TIMEOUT_OUT,
DAT_WRITE_ACK_IN => REGIO_WRITE_ACK_IN,
- EXT_REG_DATA_IN => REGIO_EXT_REG_DATA_IN,
- EXT_REG_DATA_OUT => REGIO_EXT_REG_DATA_OUT,
- EXT_REG_WRITE_IN => REGIO_EXT_REG_WRITE_IN,
- EXT_REG_ADDR_IN => REGIO_EXT_REG_ADDR_IN,
STAT => REGIO_REGIO_STAT,
STAT_ADDR_DEBUG => STAT_ADDR_DEBUG
);
- gen_no1wire : if REGIO_USE_1WIRE_INTERFACE = 0 generate
+ gen_no1wire : if REGIO_USE_1WIRE_INTERFACE = c_NO generate
buf_IDRAM_DATA_IN <= REGIO_IDRAM_DATA_IN;
buf_IDRAM_ADDR_IN <= REGIO_IDRAM_ADDR_IN;
buf_IDRAM_WR_IN <= REGIO_IDRAM_WR_IN;
REGIO_IDRAM_DATA_OUT <= buf_IDRAM_DATA_OUT;
REGIO_ONEWIRE_INOUT <= '0';
+ REGIO_ONEWIRE_MONITOR_OUT <= '0';
buf_COMMON_STAT_REG_IN <= REGIO_COMMON_STAT_REG_IN;
end generate;
- gen_1wire : if REGIO_USE_1WIRE_INTERFACE = 1 generate
+ gen_1wire : if REGIO_USE_1WIRE_INTERFACE = c_YES generate
buf_COMMON_STAT_REG_IN(19 downto 0) <= REGIO_COMMON_STAT_REG_IN(19 downto 0);
buf_COMMON_STAT_REG_IN(REGIO_COMMON_STAT_REG_IN'left downto 32) <=
REGIO_COMMON_STAT_REG_IN(REGIO_COMMON_STAT_REG_IN'left downto 32);
RESET => RESET,
--connection to 1-wire interface
ONEWIRE => REGIO_ONEWIRE_INOUT,
- MONITOR_OUT => open,
+ MONITOR_OUT => REGIO_ONEWIRE_MONITOR_OUT,
+ --connection to id ram, according to memory map in TrbNetRegIO
+ DATA_OUT => buf_IDRAM_DATA_IN,
+ ADDR_OUT => buf_IDRAM_ADDR_IN,
+ WRITE_OUT=> buf_IDRAM_WR_IN,
+ TEMP_OUT => buf_COMMON_STAT_REG_IN(31 downto 20),
+ STAT => STAT_ONEWIRE
+ );
+ end generate;
+ gen_1wire_monitor : if REGIO_USE_1WIRE_INTERFACE = c_MONITOR generate
+ buf_COMMON_STAT_REG_IN(19 downto 0) <= REGIO_COMMON_STAT_REG_IN(19 downto 0);
+ buf_COMMON_STAT_REG_IN(REGIO_COMMON_STAT_REG_IN'left downto 32) <=
+ REGIO_COMMON_STAT_REG_IN(REGIO_COMMON_STAT_REG_IN'left downto 32);
+ REGIO_IDRAM_DATA_OUT <= (others => '0');
+ REGIO_ONEWIRE_MONITOR_OUT <= '0';
+
+ onewire_interface : trb_net_onewire_listener
+ port map(
+ CLK => CLK,
+ CLK_EN => CLK_EN,
+ RESET => RESET,
+ --connection to 1-wire interface
+ MONITOR_IN => REGIO_ONEWIRE_MONITOR_IN,
--connection to id ram, according to memory map in TrbNetRegIO
DATA_OUT => buf_IDRAM_DATA_IN,
ADDR_OUT => buf_IDRAM_ADDR_IN,
COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";
HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";
+ USE_ONEWIRE : integer range 0 to 2 := c_YES;
--media interfaces
- MII_NUMBER : integer range 2 to c_MAX_MII_PER_HUB := 3;
+ MII_NUMBER : integer range 2 to c_MAX_MII_PER_HUB := 12;
MII_IBUF_DEPTH : hub_iobuf_config_t := std_HUB_IBUF_DEPTH;
+ MII_IS_UPLINK : hub_mii_config_t := (others => c_YES);
+ MII_IS_DOWNLINK : hub_mii_config_t := (others => c_YES);
-- settings for external api connections
INT_NUMBER : integer range 0 to c_MAX_API_PER_HUB := 0;
INT_CHANNELS : hub_api_config_t := (3,3,3,3,3,3,3,3);
INT_REPLY_PACKET_NUM_IN : in std_logic_vector (INT_NUMBER*c_NUM_WIDTH downto 0) := (others => '0');
INT_REPLY_READ_OUT : out std_logic_vector (INT_NUMBER downto 0);
ONEWIRE : inout std_logic;
+ ONEWIRE_MONITOR_IN : in std_logic;
+ ONEWIRE_MONITOR_OUT : out std_logic;
--Fixed status and control ports
HUB_STAT_CHANNEL : out std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0);
HUB_STAT_GEN : out std_logic_vector (31 downto 0);
STAT_COMMON_CTRL_REGS : out std_logic_vector (std_COMCTRLREG*32-1 downto 0); --Status of common STAT regs
STAT_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom STAT regs
STAT_CTRL_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom CTRL regs
- --Additional access to registers
- REGIO_EXT_REG_DATA_IN : in std_logic_vector(31 downto 0);
- REGIO_EXT_REG_DATA_OUT: out std_logic_vector(31 downto 0);
- REGIO_EXT_REG_WRITE_IN: in std_logic;
- REGIO_EXT_REG_ADDR_IN : in std_logic_vector(7 downto 0);
+
--Debugging registers
STAT_DEBUG : out std_logic_vector (31 downto 0); --free status regs for debugging
end entity;
architecture trb_net16_hub_base_arch of trb_net16_hub_base is
+
+
+
constant total_point_num : integer := MII_NUMBER*2**(c_MUX_WIDTH-1) + INT_NUMBER + 1;
signal m_DATAREADY_OUT : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH)-1 downto 0);
signal m_DATA_OUT : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH)*c_DATA_WIDTH-1 downto 0);
signal HUB_REPLY_PACKET_NUM_IN : std_logic_vector (total_point_num*c_NUM_WIDTH-1 downto 0);
signal HUB_REPLY_READ_OUT : std_logic_vector (total_point_num-1 downto 0);
+ signal HUB_STAT_ERRORBITS : std_logic_vector (2**(c_MUX_WIDTH-1)*32-1 downto 0);
signal buf_HUB_STAT_CHANNEL : std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0);
signal buf_STAT_POINTS_locked : std_logic_vector (2**(c_MUX_WIDTH-1)*32-1 downto 0);
signal buf_HUB_STAT_GEN : std_logic_vector (31 downto 0);
signal IOBUF_STAT_REPLY_OBUF_DEBUG : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1))*32-1 downto 0);
signal resync : std_logic_vector(MII_NUMBER-1 downto 0);
+ signal reset_i : std_logic;
+ attribute syn_keep : boolean;
+ attribute syn_keep of reset_i : signal is true;
+
signal combined_resync : std_logic;
signal IDRAM_DATA_IN, IDRAM_DATA_OUT : std_logic_vector(15 downto 0);
signal IDRAM_WR_IN : std_logic;
signal IDRAM_ADDR_IN : std_logic_vector(2 downto 0);
signal TEMP_OUT : std_logic_vector(11 downto 0);
- component trb_net16_hub_logic is
- generic (
- --media interfaces
- POINT_NUMBER : integer range 2 to c_MAX_POINTS_PER_HUB := 2
- );
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- INIT_DATAREADY_IN : in std_logic_vector (POINT_NUMBER-1 downto 0);
- INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0);
- INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0);
- INIT_READ_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0);
- INIT_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0);
- INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0);
- INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0);
- INIT_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0);
- REPLY_HEADER_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0);
- REPLY_DATAREADY_IN : in std_logic_vector (POINT_NUMBER-1 downto 0);
- REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0);
- REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0);
- REPLY_READ_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0);
- REPLY_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0);
- REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0);
- REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0);
- REPLY_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0);
- STAT : out std_logic_vector (15 downto 0);
- STAT_POINTS_locked : out std_logic_vector (31 downto 0);
- STAT_ERRORBITS : out std_logic_vector (31 downto 0);
- CTRL : in std_logic_vector (15 downto 0);
- CTRL_activepoints : in std_logic_vector (31 downto 0)
- );
- end component;
-
- component trb_net16_hub_ipu_logic is
- generic (
- POINT_NUMBER : integer range 2 to 32 := 3
- );
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- --Internal interfaces to IOBufs
- INIT_DATAREADY_IN : in std_logic_vector (POINT_NUMBER-1 downto 0);
- INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0);
- INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0);
- INIT_READ_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0);
- INIT_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0);
- INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0);
- INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0);
- INIT_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0);
- REPLY_DATAREADY_IN : in std_logic_vector (POINT_NUMBER-1 downto 0);
- REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0);
- REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0);
- REPLY_READ_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0);
- REPLY_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0);
- REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0);
- REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0);
- REPLY_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0);
- MY_ADDRESS_IN : in std_logic_vector (15 downto 0);
- --Status ports
- STAT_DEBUG : out std_logic_vector (31 downto 0);
- STAT_POINTS_locked : out std_logic_vector (31 downto 0);
- STAT_ERRORBITS : out std_logic_vector (31 downto 0);
- CTRL : in std_logic_vector (15 downto 0);
- CTRL_activepoints : in std_logic_vector (31 downto 0) := (others => '1')
- );
- end component;
-
- component trb_net16_io_multiplexer is
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_DATAREADY_IN : in STD_LOGIC;
- MED_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);
- MED_READ_OUT : out STD_LOGIC;
- MED_DATAREADY_OUT : out STD_LOGIC;
- MED_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);
- MED_READ_IN : in STD_LOGIC;
- -- Internal direction port
- INT_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
- INT_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);
- INT_DATAREADY_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0);
- INT_READ_IN : in STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0);
- INT_DATAREADY_IN : in STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0);
- INT_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH*(2**c_MUX_WIDTH)-1 downto 0);
- INT_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH*(2**c_MUX_WIDTH)-1 downto 0);
- INT_READ_OUT : out STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0);
- -- Status and control port
- CTRL : in STD_LOGIC_VECTOR (31 downto 0);
- STAT : out STD_LOGIC_VECTOR (31 downto 0)
- );
- end component;
-
- component trb_net16_iobuf is
- generic (
- IBUF_DEPTH : integer range 0 to 6 := c_FIFO_BRAM;--std_FIFO_DEPTH;
- IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;--std_IBUF_SECURE_MODE;
- SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
- OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH;
- USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE;
- USE_CHECKSUM : integer range 0 to 1 := c_YES;
- USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
- INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES;
- REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_INIT_DATAREADY_OUT : out std_logic;
- MED_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_INIT_READ_IN : in std_logic;
- MED_REPLY_DATAREADY_OUT : out std_logic;
- MED_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_REPLY_READ_IN : in std_logic;
- MED_DATAREADY_IN : in std_logic;
- MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_READ_OUT : out std_logic;
- MED_ERROR_IN : in std_logic_vector (2 downto 0);
- -- Internal direction port
- INT_INIT_DATAREADY_OUT : out std_logic;
- INT_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_INIT_READ_IN : in std_logic;
- INT_INIT_DATAREADY_IN : in std_logic;
- INT_INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_INIT_READ_OUT : out std_logic;
- INT_REPLY_DATAREADY_OUT : out std_logic;
- INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_REPLY_READ_IN : in std_logic;
- INT_REPLY_DATAREADY_IN : in std_logic;
- INT_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_REPLY_READ_OUT : out std_logic;
- -- Status and control port
- STAT_GEN : out std_logic_vector (31 downto 0);
- STAT_IBUF_BUFFER : out std_logic_vector (31 downto 0);
- CTRL_GEN : in std_logic_vector (31 downto 0);
- STAT_INIT_OBUF_DEBUG : out std_logic_vector (31 downto 0);
- STAT_REPLY_OBUF_DEBUG : out std_logic_vector (31 downto 0)
- );
- end component;
-
-
- component trb_net16_api_base is
- generic (
- API_TYPE : integer range 0 to 1 := c_API_PASSIVE;
- FIFO_TO_INT_DEPTH : integer range 0 to 6 := 6;--std_FIFO_DEPTH;
- FIFO_TO_APL_DEPTH : integer range 1 to 6 := 6;--std_FIFO_DEPTH;
- FORCE_REPLY : integer range 0 to 1 := std_FORCE_REPLY;
- SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
- USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
- SECURE_MODE_TO_APL: integer range 0 to 1 := c_YES;
- SECURE_MODE_TO_INT: integer range 0 to 1 := c_YES;
- APL_WRITE_ALL_WORDS:integer range 0 to 1 := c_NO;
- BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF"
- );
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- -- APL Transmitter port
- APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- APL_DATAREADY_IN : in std_logic;
- APL_READ_OUT : out std_logic;
- APL_SHORT_TRANSFER_IN : in std_logic;
- APL_DTYPE_IN : in std_logic_vector (3 downto 0);
- APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0);
- APL_SEND_IN : in std_logic;
- APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0);-- the target (only for active APIs)
- -- Receiver port
- APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- APL_TYP_OUT : out std_logic_vector (2 downto 0);
- APL_DATAREADY_OUT : out std_logic;
- APL_READ_IN : in std_logic;
- -- APL Control port
- APL_RUN_OUT : out std_logic;
- APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0);
- APL_SEQNR_OUT : out std_logic_vector (7 downto 0);
- APL_LENGTH_IN : in std_logic_vector (15 downto 0);
- -- Internal direction port
- -- the ports with master or slave in their name are to be mapped by the active api
- -- to the init respectivly the reply path and vice versa in the passive api.
- -- lets define: the "master" path is the path that I send data on.
- -- master_data_out and slave_data_in are only used in active API for termination
- INT_MASTER_DATAREADY_OUT : out std_logic;
- INT_MASTER_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_MASTER_READ_IN : in std_logic;
- INT_MASTER_DATAREADY_IN : in std_logic;
- INT_MASTER_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_MASTER_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_MASTER_READ_OUT : out std_logic;
- INT_SLAVE_DATAREADY_OUT : out std_logic;
- INT_SLAVE_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_SLAVE_READ_IN : in std_logic;
- INT_SLAVE_DATAREADY_IN : in std_logic;
- INT_SLAVE_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_SLAVE_READ_OUT : out std_logic;
- -- Status and control port
- STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0);
- STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0)
- );
- end component;
-
- component trb_net16_term is
- generic (
- USE_APL_PORT : integer range 0 to 1 := c_YES;
- --even when 0, ERROR_PACKET_IN is used for automatic replys
- SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE
- --if secure_mode is not used, apl must provide error pattern and dtype until
- --next trigger comes in. In secure mode these need to be available while relase_trg is high
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- INT_DATAREADY_OUT : out std_logic;
- INT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_READ_IN : in std_logic;
- INT_DATAREADY_IN : in std_logic;
- INT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_READ_OUT : out std_logic;
- -- "mini" APL, just to see terminations coming in
- APL_DTYPE_OUT : out std_logic_vector (3 downto 0);
- APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0);
- APL_SEQNR_OUT : out std_logic_vector (7 downto 0);
- APL_GOT_TRM : out std_logic;
- APL_RELEASE_TRM : in std_logic;
- APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0)
- );
- end component;
-
- component trb_net16_regIO is
- generic (
- NUM_STAT_REGS : integer range 0 to 6 := 1; --log2 of number of status registers
- NUM_CTRL_REGS : integer range 0 to 6 := 2; --log2 of number of ctrl registers
- --standard values for output registers
- INIT_CTRL_REGS : std_logic_vector(2**(3)*32-1 downto 0) :=
- (others => '0');
- --set to 0 for unused ctrl registers to save resources
- USED_CTRL_REGS : std_logic_vector(2**(3)-1 downto 0) := "00000001";
- --set to 0 for each unused bit in a register
- USED_CTRL_BITMASK : std_logic_vector(2**(3)*32-1 downto 0) :=
- (others => '1');
- USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port
- INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";
- INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876";
- INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222";
- INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001";
- COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
- COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";
- HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Port to API
- API_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- API_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- API_DATAREADY_OUT : out std_logic;
- API_READ_IN : in std_logic;
- API_SHORT_TRANSFER_OUT : out std_logic;
- API_DTYPE_OUT : out std_logic_vector (3 downto 0);
- API_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
- API_SEND_OUT : out std_logic;
- -- Receiver port
- API_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- API_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- API_TYP_IN : in std_logic_vector (2 downto 0);
- API_DATAREADY_IN : in std_logic;
- API_READ_OUT : out std_logic;
- -- APL Control port
- API_RUN_IN : in std_logic;
- API_SEQNR_IN : in std_logic_vector (7 downto 0);
-
- --Port to write Unique ID
- IDRAM_DATA_IN : in std_logic_vector(15 downto 0);
- IDRAM_DATA_OUT : out std_logic_vector(15 downto 0);
- IDRAM_ADDR_IN : in std_logic_vector(2 downto 0);
- IDRAM_WR_IN : in std_logic;
- MY_ADDRESS_OUT : out std_logic_vector(15 downto 0);
-
- --Common Register in / out
- COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REGISTER_WIDTH-1 downto 0);
- COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*c_REGIO_REGISTER_WIDTH-1 downto 0);
- --Custom Register in / out
- REGISTERS_IN : in std_logic_vector(c_REGIO_REGISTER_WIDTH*2**(NUM_STAT_REGS)-1 downto 0);
- REGISTERS_OUT : out std_logic_vector(c_REGIO_REGISTER_WIDTH*2**(NUM_CTRL_REGS)-1 downto 0);
- --Internal Data Port
- DAT_ADDR_OUT : out std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0);
- DAT_READ_ENABLE_OUT : out std_logic;
- DAT_WRITE_ENABLE_OUT: out std_logic;
- DAT_DATA_OUT : out std_logic_vector(c_REGIO_REG_WIDTH-1 downto 0);
- DAT_DATA_IN : in std_logic_vector(c_REGIO_REG_WIDTH-1 downto 0);
- DAT_DATAREADY_IN : in std_logic;
- DAT_NO_MORE_DATA_IN : in std_logic;
- DAT_WRITE_ACK_IN : in std_logic;
- DAT_UNKNOWN_ADDR_IN : in std_logic;
- DAT_TIMEOUT_OUT : out std_logic;
-
- EXT_REG_DATA_IN : in std_logic_vector(31 downto 0);
- EXT_REG_DATA_OUT : out std_logic_vector(31 downto 0);
- EXT_REG_WRITE_IN : in std_logic;
- EXT_REG_ADDR_IN : in std_logic_vector(7 downto 0);
- STAT : out std_logic_vector(31 downto 0)
- );
- end component;
-
- component trb_net16_term_buf is
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- MED_INIT_DATAREADY_OUT : out std_logic;
- MED_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- MED_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_INIT_READ_IN : in std_logic;
- MED_REPLY_DATAREADY_OUT : out std_logic;
- MED_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- MED_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_REPLY_READ_IN : in std_logic;
- MED_DATAREADY_IN : in std_logic;
- MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_READ_OUT : out std_logic
- );
- end component;
-
- component trb_net_onewire is
- generic(
- USE_TEMPERATURE_READOUT : integer range 0 to 1 := 1;
- CLK_PERIOD : integer := 10 --clk period in ns
- );
- port(
- CLK : in std_logic;
- RESET : in std_logic;
- --connection to 1-wire interface
- ONEWIRE : inout std_logic;
- --connection to id ram, according to memory map in TrbNetRegIO
- DATA_OUT : out std_logic_vector(15 downto 0);
- ADDR_OUT : out std_logic_vector(2 downto 0);
- WRITE_OUT: out std_logic;
- TEMP_OUT : out std_logic_vector(11 downto 0);
- STAT : out std_logic_vector(31 downto 0)
- );
- end component;
begin
+ SYNC_RESET : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ reset_i <= RESET;
+ end if;
+ end process;
--generate media resync
gen_resync : for i in 0 to MII_NUMBER-1 generate
MPLEX: trb_net16_io_multiplexer
port map (
CLK => CLK,
- RESET => RESET,
+ RESET => reset_i,
CLK_EN => CLK_EN,
MED_DATAREADY_IN => MED_DATAREADY_IN(i),
MED_DATA_IN => MED_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
OBUF_DATA_COUNT_WIDTH => std_DATA_COUNT_WIDTH,
USE_ACKNOWLEDGE => cfg_USE_ACKNOWLEDGE(k),
USE_VENDOR_CORES => USE_VENDOR_CORES,
- INIT_CAN_SEND_DATA => c_YES,
- REPLY_CAN_SEND_DATA => c_YES
+ INIT_CAN_RECEIVE_DATA => MII_IS_UPLINK(j),
+ REPLY_CAN_RECEIVE_DATA=> MII_IS_DOWNLINK(j),
+ INIT_CAN_SEND_DATA => MII_IS_DOWNLINK(j),
+ REPLY_CAN_SEND_DATA => MII_IS_UPLINK(j)
)
port map (
-- Misc
CLK => CLK ,
- RESET => RESET,
+ RESET => reset_i,
CLK_EN => CLK_EN,
-- Media direction port
MED_INIT_DATAREADY_OUT => m_DATAREADY_OUT(i*2),
port map (
-- Misc
CLK => CLK ,
- RESET => RESET,
+ RESET => reset_i,
CLK_EN => CLK_EN,
-- Media direction port
MED_INIT_DATAREADY_OUT => m_DATAREADY_OUT(i*2),
port map(
-- Misc
CLK => CLK,
- RESET => RESET,
+ RESET => reset_i,
CLK_EN => CLK_EN,
-- APL Transmitter port
APL_DATA_IN => HC_DATA_IN(c_DATA_WIDTH-1 downto 0),
REPLY_READ_IN => HUB_REPLY_READ_IN(next_point_num-1 downto first_point_num),
STAT => buf_HUB_STAT_CHANNEL((i+1)*16-1 downto i*16),
STAT_POINTS_locked => buf_STAT_POINTS_locked((i+1)*32-1 downto i*32),
- STAT_ERRORBITS => open,
+ STAT_ERRORBITS => open, --HUB_STAT_ERRORBITS(i+1)*32-1 downto i*32),
CTRL => HUB_CTRL_CHANNEL((i+1)*16-1 downto i*16),
CTRL_activepoints => HUB_CTRL_final_activepoints((i+1)*32-1 downto i*32)
);
)
port map(
CLK => CLK,
- RESET => RESET,
+ RESET => reset_i,
CLK_EN => CLK_EN,
INIT_DATAREADY_IN => HUB_INIT_DATAREADY_IN(next_point_num-1 downto first_point_num),
INIT_DATA_IN => HUB_INIT_DATA_IN(next_point_num*c_DATA_WIDTH-1 downto first_point_num*c_DATA_WIDTH),
MY_ADDRESS_IN => HUB_ADDRESS,
STAT_DEBUG => HUBLOGIC_IPU_STAT_DEBUG(31 downto 0),
STAT_POINTS_locked => buf_STAT_POINTS_locked((i+1)*32-1 downto i*32),
- STAT_ERRORBITS => open,
+ STAT_ERRORBITS => open, --HUB_STAT_ERRORBITS(i+1)*32-1 downto i*32),
CTRL => HUB_CTRL_CHANNEL((i+1)*16-1 downto i*16),
CTRL_activepoints => HUB_CTRL_final_activepoints((i+1)*32-1 downto i*32)
);
)
port map(
CLK => CLK,
- RESET => RESET,
+ RESET => reset_i,
CLK_EN => CLK_EN,
-- Port to API
API_DATA_OUT => HC_DATA_IN,
DAT_NO_MORE_DATA_IN => '0',
DAT_UNKNOWN_ADDR_IN => '0',
DAT_TIMEOUT_OUT => open,
- DAT_WRITE_ACK_IN => '0',
- EXT_REG_DATA_IN => REGIO_EXT_REG_DATA_IN,
- EXT_REG_WRITE_IN => REGIO_EXT_REG_WRITE_IN,
- EXT_REG_ADDR_IN => REGIO_EXT_REG_ADDR_IN,
- EXT_REG_DATA_OUT => REGIO_EXT_REG_DATA_OUT
+ DAT_WRITE_ACK_IN => '0'
);
- onewire_interface : trb_net_onewire
- generic map(
- USE_TEMPERATURE_READOUT => 1,
- CLK_PERIOD => 10
- )
- port map(
- CLK => CLK,
- RESET => RESET,
- --connection to 1-wire interface
- ONEWIRE => ONEWIRE,
- --connection to id ram, according to memory map in TrbNetRegIO
- DATA_OUT => IDRAM_DATA_IN,
- ADDR_OUT => IDRAM_ADDR_IN,
- WRITE_OUT=> IDRAM_WR_IN,
- TEMP_OUT => TEMP_OUT,
- STAT => open
- );
+
+ gen_1wire : if USE_ONEWIRE = c_YES generate
+ onewire_interface : trb_net_onewire
+ generic map(
+ USE_TEMPERATURE_READOUT => c_YES,
+ CLK_PERIOD => 10
+ )
+ port map(
+ CLK => CLK,
+ RESET => reset_i,
+ --connection to 1-wire interface
+ ONEWIRE => ONEWIRE,
+ MONITOR_OUT => ONEWIRE_MONITOR_OUT,
+ --connection to id ram, according to memory map in TrbNetRegIO
+ DATA_OUT => IDRAM_DATA_IN,
+ ADDR_OUT => IDRAM_ADDR_IN,
+ WRITE_OUT=> IDRAM_WR_IN,
+ TEMP_OUT => TEMP_OUT,
+ STAT => open
+ );
+ end generate;
+ gen_1wire_monitor : if USE_ONEWIRE = c_MONITOR generate
+ onewire_interface : trb_net_onewire_listener
+ port map(
+ CLK => CLK,
+ CLK_EN => CLK_EN,
+ RESET => reset_i,
+ --connection to 1-wire interface
+ MONITOR_IN => ONEWIRE_MONITOR_IN,
+ --connection to id ram, according to memory map in TrbNetRegIO
+ DATA_OUT => IDRAM_DATA_IN,
+ ADDR_OUT => IDRAM_ADDR_IN,
+ WRITE_OUT=> IDRAM_WR_IN,
+ TEMP_OUT => TEMP_OUT,
+ STAT => open
+ );
+ end generate;
+
+
-- buf_STAT_DEBUG(17 downto 16) <= hub_to_buf_INIT_DATAREADY(1 downto 0);
-- buf_STAT_DEBUG(20 downto 18) <= hub_to_buf_INIT_PACKET_NUM(2 downto 0);
- buf_STAT_DEBUG(31 downto 16) <= IOBUF_STAT_INIT_OBUF_DEBUG(15 downto 0);
+ buf_STAT_DEBUG(18 downto 16) <= IOBUF_IBUF_BUFFER(20+32*6 downto 18+32*6);
+ buf_STAT_DEBUG(21 downto 19) <= IOBUF_IBUF_BUFFER(20+32*7 downto 18+32*7);
+ buf_STAT_DEBUG(25 downto 22) <= buf_to_hub_REPLY_DATA(6*c_DATA_WIDTH+3 downto 6*c_DATA_WIDTH);
+ buf_STAT_DEBUG(26) <= buf_to_hub_REPLY_DATAREADY(6);
+ buf_STAT_DEBUG(30 downto 27) <= buf_to_hub_REPLY_DATA(7*c_DATA_WIDTH+3 downto 7*c_DATA_WIDTH);
+ buf_STAT_DEBUG(31) <= buf_to_hub_REPLY_DATAREADY(7);
-- STAT_DEBUG(0) <= comb_dataready;
-- STAT_DEBUG(3 downto 1) <= transfer_counter;
type hub_api_config_t is array(0 to 7) of integer;
type hub_api_broadcast_t is array(0 to 7) of std_logic_vector(7 downto 0);
type hub_channel_config_t is array(0 to 2**(3-1)-1) of integer;
+ type hub_mii_config_t is array(0 to 16) of integer;
--hub constraints (only needed for generic configuration)
constant c_MAX_MII_PER_HUB : integer := 16;
1,6,6,6,
1,6,6,6); --MII 15
+ constant std_hub_mii_all_yes : hub_mii_config_t := (c_YES,c_YES,c_YES,c_YES,c_YES,c_YES,c_YES,c_YES,
+ c_YES,c_YES,c_YES,c_YES,c_YES,c_YES,c_YES,c_YES,c_YES);
+
function calc_point_number (MII_NUMBER : integer;
CHANNEL : integer;
HUB_CTRL_CHANNEL : integer;
function VAL(i : integer)
return integer;
+ component trb_net16_hub_logic is
+ generic (
+ --media interfaces
+ POINT_NUMBER : integer range 2 to c_MAX_POINTS_PER_HUB := 2
+ );
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ INIT_DATAREADY_IN : in std_logic_vector (POINT_NUMBER-1 downto 0);
+ INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0);
+ INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0);
+ INIT_READ_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0);
+ INIT_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0);
+ INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0);
+ INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0);
+ INIT_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0);
+ REPLY_HEADER_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0);
+ REPLY_DATAREADY_IN : in std_logic_vector (POINT_NUMBER-1 downto 0);
+ REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0);
+ REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0);
+ REPLY_READ_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0);
+ REPLY_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0);
+ REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0);
+ REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0);
+ REPLY_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0);
+ STAT : out std_logic_vector (15 downto 0);
+ STAT_POINTS_locked : out std_logic_vector (31 downto 0);
+ STAT_ERRORBITS : out std_logic_vector (31 downto 0);
+ CTRL : in std_logic_vector (15 downto 0);
+ CTRL_activepoints : in std_logic_vector (31 downto 0)
+ );
+ end component;
+
+ component trb_net16_hub_ipu_logic is
+ generic (
+ POINT_NUMBER : integer range 2 to 32 := 3
+ );
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ --Internal interfaces to IOBufs
+ INIT_DATAREADY_IN : in std_logic_vector (POINT_NUMBER-1 downto 0);
+ INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0);
+ INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0);
+ INIT_READ_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0);
+ INIT_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0);
+ INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0);
+ INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0);
+ INIT_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0);
+ REPLY_DATAREADY_IN : in std_logic_vector (POINT_NUMBER-1 downto 0);
+ REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0);
+ REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0);
+ REPLY_READ_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0);
+ REPLY_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0);
+ REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0);
+ REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0);
+ REPLY_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0);
+ MY_ADDRESS_IN : in std_logic_vector (15 downto 0);
+ --Status ports
+ STAT_DEBUG : out std_logic_vector (31 downto 0);
+ STAT_POINTS_locked : out std_logic_vector (31 downto 0);
+ STAT_ERRORBITS : out std_logic_vector (31 downto 0);
+ CTRL : in std_logic_vector (15 downto 0);
+ CTRL_activepoints : in std_logic_vector (31 downto 0) := (others => '1')
+ );
+ end component;
+
+ component trb_net16_io_multiplexer is
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- Media direction port
+ MED_DATAREADY_IN : in STD_LOGIC;
+ MED_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);
+ MED_READ_OUT : out STD_LOGIC;
+ MED_DATAREADY_OUT : out STD_LOGIC;
+ MED_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);
+ MED_READ_IN : in STD_LOGIC;
+ -- Internal direction port
+ INT_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
+ INT_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);
+ INT_DATAREADY_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0);
+ INT_READ_IN : in STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0);
+ INT_DATAREADY_IN : in STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0);
+ INT_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH*(2**c_MUX_WIDTH)-1 downto 0);
+ INT_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH*(2**c_MUX_WIDTH)-1 downto 0);
+ INT_READ_OUT : out STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0);
+ -- Status and control port
+ CTRL : in STD_LOGIC_VECTOR (31 downto 0);
+ STAT : out STD_LOGIC_VECTOR (31 downto 0)
+ );
+ end component;
+
+ component trb_net16_iobuf is
+ generic (
+ IBUF_DEPTH : integer range 0 to 6 := c_FIFO_BRAM;--std_FIFO_DEPTH;
+ IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;--std_IBUF_SECURE_MODE;
+ SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
+ OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH;
+ USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE;
+ USE_CHECKSUM : integer range 0 to 1 := c_YES;
+ USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
+ INIT_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES;
+ REPLY_CAN_RECEIVE_DATA: integer range 0 to 1 := c_YES;
+ INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES;
+ REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES
+ );
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- Media direction port
+ MED_INIT_DATAREADY_OUT : out std_logic;
+ MED_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ MED_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ MED_INIT_READ_IN : in std_logic;
+ MED_REPLY_DATAREADY_OUT : out std_logic;
+ MED_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ MED_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ MED_REPLY_READ_IN : in std_logic;
+ MED_DATAREADY_IN : in std_logic;
+ MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ MED_READ_OUT : out std_logic;
+ MED_ERROR_IN : in std_logic_vector (2 downto 0);
+ -- Internal direction port
+ INT_INIT_DATAREADY_OUT : out std_logic;
+ INT_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ INT_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ INT_INIT_READ_IN : in std_logic;
+ INT_INIT_DATAREADY_IN : in std_logic;
+ INT_INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ INT_INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ INT_INIT_READ_OUT : out std_logic;
+ INT_REPLY_DATAREADY_OUT : out std_logic;
+ INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ INT_REPLY_READ_IN : in std_logic;
+ INT_REPLY_DATAREADY_IN : in std_logic;
+ INT_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ INT_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ INT_REPLY_READ_OUT : out std_logic;
+ -- Status and control port
+ STAT_GEN : out std_logic_vector (31 downto 0);
+ STAT_IBUF_BUFFER : out std_logic_vector (31 downto 0);
+ CTRL_GEN : in std_logic_vector (31 downto 0);
+ STAT_INIT_OBUF_DEBUG : out std_logic_vector (31 downto 0);
+ STAT_REPLY_OBUF_DEBUG : out std_logic_vector (31 downto 0)
+ );
+ end component;
+
+
+ component trb_net16_api_base is
+ generic (
+ API_TYPE : integer range 0 to 1 := c_API_PASSIVE;
+ FIFO_TO_INT_DEPTH : integer range 0 to 6 := 6;--std_FIFO_DEPTH;
+ FIFO_TO_APL_DEPTH : integer range 1 to 6 := 6;--std_FIFO_DEPTH;
+ FORCE_REPLY : integer range 0 to 1 := std_FORCE_REPLY;
+ SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
+ USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
+ SECURE_MODE_TO_APL: integer range 0 to 1 := c_YES;
+ SECURE_MODE_TO_INT: integer range 0 to 1 := c_YES;
+ APL_WRITE_ALL_WORDS:integer range 0 to 1 := c_NO;
+ BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF"
+ );
+
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ -- APL Transmitter port
+ APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ APL_DATAREADY_IN : in std_logic;
+ APL_READ_OUT : out std_logic;
+ APL_SHORT_TRANSFER_IN : in std_logic;
+ APL_DTYPE_IN : in std_logic_vector (3 downto 0);
+ APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0);
+ APL_SEND_IN : in std_logic;
+ APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0);-- the target (only for active APIs)
+ -- Receiver port
+ APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ APL_TYP_OUT : out std_logic_vector (2 downto 0);
+ APL_DATAREADY_OUT : out std_logic;
+ APL_READ_IN : in std_logic;
+ -- APL Control port
+ APL_RUN_OUT : out std_logic;
+ APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0);
+ APL_SEQNR_OUT : out std_logic_vector (7 downto 0);
+ APL_LENGTH_IN : in std_logic_vector (15 downto 0);
+ -- Internal direction port
+ -- the ports with master or slave in their name are to be mapped by the active api
+ -- to the init respectivly the reply path and vice versa in the passive api.
+ -- lets define: the "master" path is the path that I send data on.
+ -- master_data_out and slave_data_in are only used in active API for termination
+ INT_MASTER_DATAREADY_OUT : out std_logic;
+ INT_MASTER_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ INT_MASTER_READ_IN : in std_logic;
+ INT_MASTER_DATAREADY_IN : in std_logic;
+ INT_MASTER_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ INT_MASTER_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ INT_MASTER_READ_OUT : out std_logic;
+ INT_SLAVE_DATAREADY_OUT : out std_logic;
+ INT_SLAVE_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ INT_SLAVE_READ_IN : in std_logic;
+ INT_SLAVE_DATAREADY_IN : in std_logic;
+ INT_SLAVE_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ INT_SLAVE_READ_OUT : out std_logic;
+ -- Status and control port
+ STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0);
+ STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0)
+ );
+ end component;
+
+ component trb_net16_term is
+ generic (
+ USE_APL_PORT : integer range 0 to 1 := c_YES;
+ --even when 0, ERROR_PACKET_IN is used for automatic replys
+ SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE
+ --if secure_mode is not used, apl must provide error pattern and dtype until
+ --next trigger comes in. In secure mode these need to be available while relase_trg is high
+ );
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ INT_DATAREADY_OUT : out std_logic;
+ INT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
+ INT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ INT_READ_IN : in std_logic;
+ INT_DATAREADY_IN : in std_logic;
+ INT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
+ INT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ INT_READ_OUT : out std_logic;
+ -- "mini" APL, just to see terminations coming in
+ APL_DTYPE_OUT : out std_logic_vector (3 downto 0);
+ APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0);
+ APL_SEQNR_OUT : out std_logic_vector (7 downto 0);
+ APL_GOT_TRM : out std_logic;
+ APL_RELEASE_TRM : in std_logic;
+ APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0)
+ );
+ end component;
+
+ component trb_net16_regIO is
+ generic (
+ NUM_STAT_REGS : integer range 0 to 6 := 1; --log2 of number of status registers
+ NUM_CTRL_REGS : integer range 0 to 6 := 2; --log2 of number of ctrl registers
+ --standard values for output registers
+ INIT_CTRL_REGS : std_logic_vector(2**(3)*32-1 downto 0) :=
+ (others => '0');
+ --set to 0 for unused ctrl registers to save resources
+ USED_CTRL_REGS : std_logic_vector(2**(3)-1 downto 0) := "00000001";
+ --set to 0 for each unused bit in a register
+ USED_CTRL_BITMASK : std_logic_vector(2**(3)*32-1 downto 0) :=
+ (others => '1');
+ USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port
+ INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";
+ INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876";
+ INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222";
+ INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001";
+ COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
+ COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";
+ HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"
+ );
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- Port to API
+ API_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ API_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ API_DATAREADY_OUT : out std_logic;
+ API_READ_IN : in std_logic;
+ API_SHORT_TRANSFER_OUT : out std_logic;
+ API_DTYPE_OUT : out std_logic_vector (3 downto 0);
+ API_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
+ API_SEND_OUT : out std_logic;
+ -- Receiver port
+ API_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ API_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ API_TYP_IN : in std_logic_vector (2 downto 0);
+ API_DATAREADY_IN : in std_logic;
+ API_READ_OUT : out std_logic;
+ -- APL Control port
+ API_RUN_IN : in std_logic;
+ API_SEQNR_IN : in std_logic_vector (7 downto 0);
+
+ --Port to write Unique ID
+ IDRAM_DATA_IN : in std_logic_vector(15 downto 0);
+ IDRAM_DATA_OUT : out std_logic_vector(15 downto 0);
+ IDRAM_ADDR_IN : in std_logic_vector(2 downto 0);
+ IDRAM_WR_IN : in std_logic;
+ MY_ADDRESS_OUT : out std_logic_vector(15 downto 0);
+
+ --Common Register in / out
+ COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REGISTER_WIDTH-1 downto 0);
+ COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*c_REGIO_REGISTER_WIDTH-1 downto 0);
+ --Custom Register in / out
+ REGISTERS_IN : in std_logic_vector(c_REGIO_REGISTER_WIDTH*2**(NUM_STAT_REGS)-1 downto 0);
+ REGISTERS_OUT : out std_logic_vector(c_REGIO_REGISTER_WIDTH*2**(NUM_CTRL_REGS)-1 downto 0);
+ --Internal Data Port
+ DAT_ADDR_OUT : out std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0);
+ DAT_READ_ENABLE_OUT : out std_logic;
+ DAT_WRITE_ENABLE_OUT: out std_logic;
+ DAT_DATA_OUT : out std_logic_vector(c_REGIO_REG_WIDTH-1 downto 0);
+ DAT_DATA_IN : in std_logic_vector(c_REGIO_REG_WIDTH-1 downto 0);
+ DAT_DATAREADY_IN : in std_logic;
+ DAT_NO_MORE_DATA_IN : in std_logic;
+ DAT_WRITE_ACK_IN : in std_logic;
+ DAT_UNKNOWN_ADDR_IN : in std_logic;
+ DAT_TIMEOUT_OUT : out std_logic;
+ STAT : out std_logic_vector(31 downto 0)
+ );
+ end component;
+
+ component trb_net16_term_buf is
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ MED_INIT_DATAREADY_OUT : out std_logic;
+ MED_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
+ MED_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ MED_INIT_READ_IN : in std_logic;
+ MED_REPLY_DATAREADY_OUT : out std_logic;
+ MED_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
+ MED_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ MED_REPLY_READ_IN : in std_logic;
+ MED_DATAREADY_IN : in std_logic;
+ MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
+ MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ MED_READ_OUT : out std_logic
+ );
+ end component;
+
+ component trb_net_onewire is
+ generic(
+ USE_TEMPERATURE_READOUT : integer range 0 to 1 := 1;
+ CLK_PERIOD : integer := 10 --clk period in ns
+ );
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ --connection to 1-wire interface
+ ONEWIRE : inout std_logic;
+ MONITOR_OUT : out std_logic;
+ --connection to id ram, according to memory map in TrbNetRegIO
+ DATA_OUT : out std_logic_vector(15 downto 0);
+ ADDR_OUT : out std_logic_vector(2 downto 0);
+ WRITE_OUT: out std_logic;
+ TEMP_OUT : out std_logic_vector(11 downto 0);
+ STAT : out std_logic_vector(31 downto 0)
+ );
+ end component;
+
+ component trb_net_onewire_listener is
+ port(
+ CLK : in std_logic;
+ CLK_EN : in std_logic;
+ RESET : in std_logic;
+ MONITOR_IN : in std_logic;
+ DATA_OUT : out std_logic_vector(15 downto 0);
+ ADDR_OUT : out std_logic_vector(2 downto 0);
+ WRITE_OUT: out std_logic;
+ TEMP_OUT : out std_logic_vector(11 downto 0);
+ STAT : out std_logic_vector(31 downto 0)
+ );
+ end component;
+
+
+
end package trb_net16_hub_func;
package body trb_net16_hub_func is
return tmp;
end function;
+
end package body;
\ No newline at end of file
end entity;
architecture trb_net16_hub_ipu_logic_arch of trb_net16_hub_ipu_logic is
+ -- Placer Directives
+ attribute HGROUP : string;
+ -- for whole architecture
+ attribute HGROUP of trb_net16_hub_ipu_logic_arch : architecture is "HUBIPULOGIC_group";
component trb_net16_sbuf is
generic (
signal REPLY_MUX_reading : std_logic_vector(POINT_NUMBER-1 downto 0);
signal reply_arbiter_result : std_logic_vector(POINT_NUMBER-1 downto 0);
- type state_type is (IDLE, WAIT_FOR_HDR_DATA, GEN_LENGTH, CHECK_DHDR, SENDING_DATA, SENDING_REPLY_TRM, SEND_PADDING, WAITING_FOR_INIT);
+ type state_type is (IDLE, WAIT_FOR_REPLY, WAIT_FOR_HDR_DATA, GEN_LENGTH, CHECK_DHDR, SENDING_DATA, SENDING_REPLY_TRM, SEND_PADDING, WAITING_FOR_INIT);
signal current_state, next_state : state_type;
signal packet_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0);
signal reply_data_counter : unsigned(15 downto 0);
signal reply_adder_start : std_logic;
signal reply_adder_overflow : std_logic;
signal reply_adder_ready : std_logic;
- signal reply_adder_val_enable : std_logic_vector(17-1 downto 0);
- signal reply_adder_result : std_logic_vector(15 downto 0);
+ signal reply_adder_val_enable : std_logic_vector(17-1 downto 0);
+ signal reply_adder_result : std_logic_vector(15 downto 0);
+ signal next_reply_adder_start : std_logic;
+ signal next_reply_compare_start : std_logic;
signal reply_compare_start : std_logic;
signal reply_compare_finished : std_logic;
signal last_dhdr_addr : std_logic_vector(2 downto 0);
signal last_dhdr_data : std_logic_vector(16*POINT_NUMBER-1 downto 0);
+ signal next_last_dhdr_data : std_logic_vector(16*POINT_NUMBER-1 downto 0);
signal current_point_length : unsigned(15 downto 0);
signal reply_mux_number : integer range 0 to POINT_NUMBER-1;
hdrram_write_enable(i) <= (current_reply_reading_HDR(i) and
(reply_reading_F0(i) or reply_reading_F1(i) or reply_reading_F2(i) or reply_reading_F3(i))) or
(current_reply_reading_DHDR(i) and
- (reply_reading_F0(i) or reply_reading_F1(i) or (REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH+1) and not
- REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH) and not REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH+2))));
+ (reply_reading_F0(i) or reply_reading_F1(i) or reply_reading_F2(i)
+-- (REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH+1) and not REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH) and not REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH+2))
+ ));
--read normal HDR_F0 to DHDR_F1 and DHDR_F2 without read='1'
hdrram_address(i*3+1 downto i*3) <= REPLY_PACKET_NUM_IN((i)*c_NUM_WIDTH+1 downto i*c_NUM_WIDTH);
hdrram_address(i*3+2) <= '1' when current_reply_reading_DHDR(i)='1' else '0';
a1 => hdrram_address(i*3+2 downto i*3),
din1 => REPLY_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
a2 => last_dhdr_addr,
- dout2 => last_dhdr_data((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH)
+ dout2 => next_last_dhdr_data((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH)
);
end generate;
+ PROC_REG_DHDR_RAM_OUT : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ last_dhdr_data <= next_last_dhdr_data;
+ end if;
+ end process;
+
the_ram_output_adder : wide_adder_17x16
generic map(
SIZE => 16,
READY_OUT => reply_adder_ready
);
+ PROC_LED : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ reply_adder_start <= '0';
+ reply_compare_start <= '0';
+ else
+ reply_adder_start <= next_reply_adder_start;
+ reply_compare_start <= next_reply_compare_start;
+ end if;
+ end if;
+ end process;
+
reply_adder_input(POINT_NUMBER*16-1 downto 0) <= last_dhdr_data;
gen_spare_bits : if POINT_NUMBER < 17 generate
reply_adder_input(reply_adder_input'left downto POINT_NUMBER*16) <= (others => '0');
if rising_edge(CLK) then
if RESET = '1' or reply_data_counter_reset = '1' then
reply_data_counter <= (others => '1');
- elsif comb_REPLY_POOL_DATAREADY = '1' and comb_REPLY_POOL_PACKET_NUM(0) = '0' and comb_REPLY_POOL_PACKET_NUM(2) = '0' then
+ elsif comb_REPLY_POOL_DATAREADY = '1' and packet_counter(0) = '1' then
reply_data_counter <= reply_data_counter + 1;
end if;
end if;
and not reply_reading_H0 and not saved_reading_padding)
and REPLY_POOL_next_read;
---temporary!
+--temporary! no real compare is done!
reply_compare_finished <= reply_compare_start;
and not (current_reply_reading_DHDR and reply_reading_F1);
last_dhdr_addr <= "000";
next_current_waiting_for_reply <= current_waiting_for_reply and not current_reply_reading_HDR and real_activepoints;
- reply_adder_start <= '0';
+ next_reply_adder_start <= '0';
reply_adder_val_enable(POINT_NUMBER-1 downto 0) <= (not locking_point and real_activepoints);
reply_adder_val_enable(reply_adder_val_enable'left downto POINT_NUMBER) <= (others => '0');
reply_arbiter_enable <= '0';
- reply_compare_start <= '0';
+ next_reply_compare_start <= '0';
reply_arbiter_CLK_EN <= '0';
reply_data_counter_reset <= '0';
start_read_padding <= (others => '0');
next_current_waiting_for_reply <= not (locking_point or not real_activepoints);
next_waiting_for_DHDR_word <= not (locking_point or not real_activepoints);
if locked = '1' then
+ next_state <= WAIT_FOR_REPLY; --WAIT_FOR_HDR_DATA;
+ end if;
+
+ when WAIT_FOR_REPLY =>
+ if got_all_reply_starts = '1' then
next_state <= WAIT_FOR_HDR_DATA;
end if;
when c_H0 =>
comb_REPLY_POOL_DATA <= (others => '0');
comb_REPLY_POOL_DATA(2 downto 0) <= TYPE_HDR;
- comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read and got_all_reply_starts;
+ comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read;
when c_F0 =>
comb_REPLY_POOL_DATA <= MY_ADDRESS_IN;
comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read;
comb_REPLY_POOL_DATAREADY <= '0';
if not_reading_HDR = '1' then --implicit not waiting_for_reply
next_state <= GEN_LENGTH;
- reply_adder_start <= '1';
+ next_reply_adder_start <= '1';
end if;
when others => null;
end case;
comb_REPLY_POOL_DATA(c_DATA_WIDTH-1 downto 3) <= (others => '0');
when c_F0 =>
last_dhdr_addr <= "100";
- reply_compare_start <= '1';
+ next_reply_compare_start <= '1';
if reply_compare_finished = '1' then
comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read;
comb_REPLY_POOL_DATA <= "0001" & evt_dtype & evt_random_code;
end if;
when c_F1 =>
last_dhdr_addr <= "101";
- reply_compare_start <= '1';
+ next_reply_compare_start <= '1';
comb_REPLY_POOL_DATA <= evt_number;
if reply_compare_finished = '1' then
comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read;
last_dhdr_addr <= "110";
end if;
when c_F2 =>
- reply_adder_start <= '1';
+ next_reply_adder_start <= '1';
last_dhdr_addr <= "110";
comb_REPLY_POOL_DATA <= std_logic_vector(unsigned(reply_adder_result) + number_of_replies);
if reply_adder_ready = '1' then
- reply_adder_start <= '0';
+ next_reply_adder_start <= '0';
comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read;
end if;
when others => --c_F3
end if;
if reply_data_counter = current_point_length then
- if packet_counter(0) = '0' then
+ if packet_counter(0) = '0' then --'0'
reply_arbiter_CLK_EN <= '1';
reply_data_counter_reset <= '1';
else
STAT_DEBUG(6) <= REPLY_DATA_IN(14);
STAT_DEBUG(7) <= REPLY_DATA_IN(30);
- STAT_DEBUG(8) <= '0';--REPLY_DATA_IN(46);
+ STAT_DEBUG(8) <= '0'; --REPLY_DATA_IN(46);
STAT_DEBUG(9) <= locked;
STAT_DEBUG(13 downto 10) <= reply_fsm_state(3 downto 0);
STAT_DEBUG(31 downto 14) <= (others => '0');
end entity;
architecture trb_net16_hub_logic_arch of trb_net16_hub_logic is
+ -- Placer Directives
+ attribute HGROUP : string;
+ -- for whole architecture
+ attribute HGROUP of trb_net16_hub_logic_arch : architecture is "HUBLOGIC_group";
+
component trb_net16_sbuf is
generic (
signal next_resending_header, resending_header : std_logic;
signal idle_counter : std_logic_vector(4 downto 0);
signal idle_time_exceeded : std_logic;
+ signal reset_i : std_logic;
+ attribute syn_keep : boolean;
+ attribute syn_keep of reset_i : signal is true;
+
+ signal reply_dataready_in_i : std_logic_vector(POINT_NUMBER-1 downto 0) := (others => '0');
+ signal reply_data_in_i : std_logic_vector(c_DATA_WIDTH*POINT_NUMBER-1 downto 0) := (others => '0');
+ signal reply_packet_num_in_i: std_logic_vector(c_NUM_WIDTH*POINT_NUMBER-1 downto 0) := (others => '0');
+ signal register_buf_REPLY_READ_OUT : std_logic_vector(POINT_NUMBER-1 downto 0) := (others => '0');
begin
REPLY_HEADER_OUT <= (others => '0');
STAT(0) <= got_trm(0);
STAT(1) <= got_trm(1);
STAT(2) <= REPLY_POOL_DATAREADY;
-STAT(3) <= REPLY_DATAREADY_IN(0);
+STAT(3) <= reply_dataready_in_i(0);
STAT(4) <= buf_REPLY_READ_OUT(0);
STAT(5) <= comb_REPLY_muxed_DATA(14);
-STAT(6) <= REPLY_DATA_IN(14);
-STAT(7) <= REPLY_DATA_IN(30);
-STAT(8) <= '0';--REPLY_DATA_IN(46);
+STAT(6) <= reply_data_in_i(14);
+STAT(7) <= reply_data_in_i(30);
+STAT(8) <= '0';--reply_data_in_i(46);
STAT(9) <= locked;
STAT(15 downto 10) <= (others => '0');
STAT_POINTS_locked(31 downto POINT_NUMBER) <= (others => '0');
STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2;
+ SYNC_RESET : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ reset_i <= RESET;
+ end if;
+ end process;
+
+ register_buf_REPLY_READ_OUT <= not reply_dataready_in_i or buf_REPLY_READ_OUT;
+
+ gen_reply_sync : for i in 0 to POINT_NUMBER-1 generate
+ SYNC_REPLY_DATA_INPUTS : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if reset_i = '1' then
+ reply_dataready_in_i(i) <= '0';
+ elsif register_buf_REPLY_READ_OUT(i) = '1' then --reply_dataready_in_i(i) = '0' or buf_REPLY_READ_OUT(i) = '1' then
+ reply_dataready_in_i(i) <= REPLY_DATAREADY_IN(i);
+ reply_data_in_i((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= REPLY_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH);
+ reply_packet_num_in_i((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= REPLY_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH);
+ end if;
+ end if;
+ end process;
+ end generate;
+
+
INIT_POOL_SBUF: trb_net16_sbuf
generic map (
Version => std_SBUF_VERSION
)
port map (
CLK => CLK,
- RESET => RESET,
+ RESET => reset_i,
CLK_EN => CLK_EN,
COMB_DATAREADY_IN => INIT_muxed_DATAREADY,
COMB_next_READ_OUT => comb_INIT_next_read,
process(CLK)
begin
if rising_edge(CLK) then
- if RESET = '1' then
+ if reset_i = '1' then
INIT_muxed_READ <= '0';
else
INIT_muxed_READ <= comb_INIT_next_read;
generic map (WIDTH => POINT_NUMBER)
port map (
CLK => CLK,
- RESET => RESET,
+ RESET => reset_i,
CLK_EN => init_arbiter_CLK_EN,
INPUT_IN => INIT_DATAREADY_IN,
RESULT_OUT => init_arbiter_read_out,
process(CLK)
begin
if rising_edge(CLK) then
- if RESET = '1' or INIT_POOL_READ = '1' then
+ if reset_i = '1' or INIT_POOL_READ = '1' then
init_has_read_from_pool(i) <= '0';
elsif INIT_POOL_DATAREADY = '1' and INIT_READ_IN(i) = '1' then
init_has_read_from_pool(i) <= '1';
process(CLK)
begin
if rising_edge(CLK) then
- if RESET = '1' then
+ if reset_i = '1' then
locked <= '0';
locking_point <= (others => '0');
init_locked <= '0';
buf_REPLY_READ_OUT <= REPLY_reading_trm or REPLY_MUX_reading when REPLY_POOL_next_read = '1' else
REPLY_reading_trm;
- REPLY_READ_OUT <= buf_REPLY_READ_OUT;
+ REPLY_READ_OUT <= register_buf_REPLY_READ_OUT;
REPLY_MUX_real_reading <= REPLY_POOL_next_read; --or_all(REPLY_MUX_reading) and
--REPLY_MUX_reading always contains a 1 (?)
save_INIT_TYPE : process(CLK)
begin
if rising_edge(CLK) then
- if RESET = '1' or (INIT_muxed_DATAREADY = '1' and INIT_muxed_PACKET_NUM = c_F3) then
+ if reset_i = '1' or (INIT_muxed_DATAREADY = '1' and INIT_muxed_PACKET_NUM = c_F3) then
saved_INIT_TYPE <= TYPE_ILLEGAL;
elsif INIT_muxed_DATAREADY = '1' and INIT_muxed_PACKET_NUM = c_H0 then
saved_INIT_TYPE <= INIT_muxed_DATA(2 downto 0);
save_REPLY_TYPE : process(CLK)
begin
if rising_edge(CLK) then
- if RESET = '1' or (REPLY_POOL_DATAREADY = '1' and REPLY_POOL_PACKET_NUM = c_F3) then
+ if reset_i = '1' or (REPLY_POOL_DATAREADY = '1' and REPLY_POOL_PACKET_NUM = c_F3) then
saved_REPLY_TYPE <= TYPE_ILLEGAL;
elsif REPLY_POOL_DATAREADY = '1' and REPLY_POOL_PACKET_NUM = c_H0 then
saved_REPLY_TYPE <= REPLY_POOL_DATA(2 downto 0);
save_SEQ_NR : process(CLK)
begin
if rising_edge(CLK) then
- if RESET = '1' then
+ if reset_i = '1' then
SEQ_NR <= (others => '0');
elsif INIT_POOL_PACKET_NUM = c_F3 and current_INIT_TYPE = TYPE_HDR then
SEQ_NR <= INIT_POOL_DATA(11 downto 4);
--REPLY reading and saving HDR
----------------------------------
gen_reading_hdr : for i in 0 to POINT_NUMBER-1 generate
- process(REPLY_reading_hdr, REPLY_PACKET_NUM_IN, REPLY_DATA_IN)
+ process(REPLY_reading_hdr, reply_packet_num_in_i, reply_data_in_i)
begin
next_REPLY_reading_hdr(i) <= REPLY_reading_hdr(i);
- if REPLY_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) = c_F3 then
+ if reply_packet_num_in_i((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) = c_F3 then
next_REPLY_reading_hdr(i) <= '0';
- elsif REPLY_DATA_IN(i*c_DATA_WIDTH+2 downto i*c_DATA_WIDTH) = TYPE_HDR
- and REPLY_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) = c_H0 then
+ elsif reply_data_in_i(i*c_DATA_WIDTH+2 downto i*c_DATA_WIDTH) = TYPE_HDR
+ and reply_packet_num_in_i((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) = c_H0 then
next_REPLY_reading_hdr(i) <= '1';
end if;
end process;
process(CLK)
begin
if rising_edge(CLK) then
- if RESET = '1' then
+ if reset_i = '1' then
REPLY_reading_hdr <= (others => '0');
else
REPLY_reading_hdr <= next_REPLY_reading_hdr;
port map(
CLK => CLK,
wr1 => current_REPLY_reading_hdr(i),
- a1 => REPLY_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- din1 => REPLY_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ a1 => reply_packet_num_in_i((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+ din1 => reply_data_in_i((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
dout1 => open,
a2 => last_header_addr,
dout2 => last_header_data((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH)
--REPLY reading and merging TRM
----------------------------------
gen_reading_trm : for i in 0 to POINT_NUMBER-1 generate
- process(REPLY_reading_trm, REPLY_PACKET_NUM_IN, REPLY_DATA_IN)
+ process(REPLY_reading_trm, reply_packet_num_in_i, reply_data_in_i)
begin
next_REPLY_reading_trm(i) <= REPLY_reading_trm(i);
- if REPLY_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) = c_F3 then
+ if reply_packet_num_in_i((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) = c_F3 then
next_REPLY_reading_trm(i) <= '0';
- elsif REPLY_DATA_IN(i*c_DATA_WIDTH+2 downto i*c_DATA_WIDTH) = TYPE_TRM
- and REPLY_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) = c_H0 then
+ elsif reply_data_in_i(i*c_DATA_WIDTH+2 downto i*c_DATA_WIDTH) = TYPE_TRM
+ and reply_packet_num_in_i((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) = c_H0 then
next_REPLY_reading_trm(i) <= '1';
end if;
end process;
process(CLK)
begin
if rising_edge(CLK) then
- if RESET = '1' then
+ if reset_i = '1' then
REPLY_reading_trm <= (others => '0');
else
REPLY_reading_trm <= next_REPLY_reading_trm;
gen_reading_trmFn : for i in 0 to POINT_NUMBER-1 generate
- reading_trmF0(i) <= not REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH+1) and not REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH)
- and not REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH+2) and REPLY_reading_trm(i) and REPLY_DATAREADY_IN(i);
- reading_trmF1(i) <= not REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH+1) and REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH)
- and REPLY_reading_trm(i) and REPLY_DATAREADY_IN(i);
- reading_trmF2(i) <= REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH+1) and not REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH)
- and REPLY_reading_trm(i) and REPLY_DATAREADY_IN(i);
- reading_trmF3(i) <= REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH+1) and REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH)
- and REPLY_reading_trm(i) and REPLY_DATAREADY_IN(i);
+ reading_trmF0(i) <= not reply_packet_num_in_i(i*c_NUM_WIDTH+1) and not reply_packet_num_in_i(i*c_NUM_WIDTH)
+ and not reply_packet_num_in_i(i*c_NUM_WIDTH+2) and REPLY_reading_trm(i) and reply_dataready_in_i(i);
+ reading_trmF1(i) <= not reply_packet_num_in_i(i*c_NUM_WIDTH+1) and reply_packet_num_in_i(i*c_NUM_WIDTH)
+ and REPLY_reading_trm(i) and reply_dataready_in_i(i);
+ reading_trmF2(i) <= reply_packet_num_in_i(i*c_NUM_WIDTH+1) and not reply_packet_num_in_i(i*c_NUM_WIDTH)
+ and REPLY_reading_trm(i) and reply_dataready_in_i(i);
+ reading_trmF3(i) <= reply_packet_num_in_i(i*c_NUM_WIDTH+1) and reply_packet_num_in_i(i*c_NUM_WIDTH)
+ and REPLY_reading_trm(i) and reply_dataready_in_i(i);
end generate;
gen_combining_trm : for j in 0 to c_DATA_WIDTH-1 generate
variable tmpF1, tmpF2, tmpF3, tmpF0 : std_logic;
begin
if rising_edge(CLK) then
- if RESET = '1' or locked = '0' then
+ if reset_i = '1' or locked = '0' then
REPLY_combined_trm_F0(j) <= '0';
REPLY_combined_trm_F1(j) <= '0';
REPLY_combined_trm_F2(j) <= '0';
tmpF2 := '0';
tmpF3 := '0';
for i in 0 to POINT_NUMBER-1 loop
- tmpF0 := tmpF0 or (REPLY_DATA_IN(i*c_DATA_WIDTH+j) and reading_trmF0(i));
- tmpF1 := tmpF1 or (REPLY_DATA_IN(i*c_DATA_WIDTH+j) and reading_trmF1(i));
- tmpF2 := tmpF2 or (REPLY_DATA_IN(i*c_DATA_WIDTH+j) and reading_trmF2(i));
- tmpF3 := tmpF3 or (REPLY_DATA_IN(i*c_DATA_WIDTH+j) and reading_trmF3(i));
+ tmpF0 := tmpF0 or (reply_data_in_i(i*c_DATA_WIDTH+j) and reading_trmF0(i));
+ tmpF1 := tmpF1 or (reply_data_in_i(i*c_DATA_WIDTH+j) and reading_trmF1(i));
+ tmpF2 := tmpF2 or (reply_data_in_i(i*c_DATA_WIDTH+j) and reading_trmF2(i));
+ tmpF3 := tmpF3 or (reply_data_in_i(i*c_DATA_WIDTH+j) and reading_trmF3(i));
end loop;
REPLY_combined_trm_F0(j) <= REPLY_combined_trm_F0(j) or tmpF0;
REPLY_combined_trm_F1(j) <= REPLY_combined_trm_F1(j) or tmpF1;
gen_got_trm : process(CLK)
begin
if rising_edge(CLK) then
- if RESET = '1' or send_reply_trm = '1' or locked = '0' then
+ if reset_i = '1' or send_reply_trm = '1' or locked = '0' then
got_trm <= (others => '0');
else
got_trm <= got_trm or locking_point or reading_trmF2 or not real_activepoints;
read_before_proc : process(CLK)
begin
if rising_edge(CLK) then
- if RESET = '1' or send_reply_trm = '1' or locked = '0' then
+ if reset_i = '1' or send_reply_trm = '1' or locked = '0' then
read_from_point_before <= (others => '0');
else
- read_from_point_before <= (REPLY_DATAREADY_IN and buf_REPLY_READ_OUT) or read_from_point_before;
+ read_from_point_before <= (reply_dataready_in_i and buf_REPLY_READ_OUT) or read_from_point_before;
end if;
end if;
end process;
gen_packet_counter : process(CLK)
begin
if rising_edge(CLK) then
- if RESET = '1' or locked = '0' then
+ if reset_i = '1' or locked = '0' then
packet_counter <= c_H0;
elsif comb_REPLY_POOL_DATAREADY = '1' then
if packet_counter = c_max_word_number then
gen_data_counter : process(CLK)
begin
if rising_edge(CLK) then
- if RESET = '1' or reply_point_lock = '0' then
+ if reset_i = '1' or reply_point_lock = '0' then
data_counter <= (others => '0');
elsif comb_REPLY_POOL_PACKET_NUM = c_H0 and comb_REPLY_POOL_DATAREADY = '1'
and comb_REPLY_POOL_DATA(2 downto 0) = TYPE_DAT then
gen_idle_count : process(CLK)
begin
if rising_edge(CLK) then
- if RESET = '1' or packet_counter = c_H0 then
+ if reset_i = '1' or packet_counter = c_H0 then
idle_counter <= (others => '0');
idle_time_exceeded <= '0';
- elsif or_all(REPLY_MUX_reading and REPLY_DATAREADY_IN) = '0' and idle_time_exceeded = '0' then
+ elsif or_all(REPLY_MUX_reading and reply_dataready_in_i) = '0' and idle_time_exceeded = '0' then
idle_counter <= idle_counter + 1;
if idle_counter = c_MAX_IDLE_TIME_PER_PACKET then
idle_time_exceeded <= '1';
)
port map (
CLK => CLK,
- RESET => RESET,
+ RESET => reset_i,
CLK_EN => reply_arbiter_CLK_EN,
INPUT_IN => reply_arbiter_input,
RESULT_OUT => reply_arbiter_result,
CTRL => (others => '0')
);
- reply_arbiter_input <= REPLY_DATAREADY_IN and not REPLY_reading_trm;
+ reply_arbiter_input <= reply_dataready_in_i and not REPLY_reading_trm;
-- we have to care to read multiples of four packets from every point
-- release is currently done after first packet of TRM
gen_reply_point_lock : process(reply_point_lock, comb_REPLY_muxed_PACKET_NUM,
- reply_arbiter_result, REPLY_DATAREADY_IN, comb_REPLY_muxed_DATA,
+ reply_arbiter_result, reply_dataready_in_i, comb_REPLY_muxed_DATA,
REPLY_MUX_reading, last_reply_arbiter_result, got_trm,
read_from_point_before, resending_header, comb_REPLY_muxed_DATAREADY)
begin
-- next_reading_last_hdr <= (others => '0');
-- next_resending_header <= '0';
--release lock if TRM is read
- if comb_REPLY_muxed_PACKET_NUM = c_H0 and or_all(REPLY_MUX_reading and REPLY_DATAREADY_IN) = '1' then
+ if comb_REPLY_muxed_PACKET_NUM = c_H0 and or_all(REPLY_MUX_reading and reply_dataready_in_i) = '1' then
if comb_REPLY_muxed_DATA(2 downto 0) = TYPE_TRM then
next_point_lock <= '0';
else
gen_point_lock : process(CLK)
begin
if rising_edge(CLK) then
- if RESET = '1' then
+ if reset_i = '1' then
reply_point_lock <= '0';
else
reply_point_lock <=next_point_lock;
--REPLY mux
----------------------------------
gen_reply_mux1 : for i in 0 to c_DATA_WIDTH-1 generate
- data_mux : process(REPLY_DATA_IN, REPLY_MUX_reading,last_header_data, reading_last_hdr)
+ data_mux : process(reply_data_in_i, REPLY_MUX_reading,last_header_data, reading_last_hdr)
variable tmp_data : std_logic;
begin
tmp_data := '0';
gen_data_mux : for j in 0 to POINT_NUMBER-1 loop
- tmp_data := tmp_data or (REPLY_DATA_IN(j*c_DATA_WIDTH+i) and REPLY_MUX_reading(j))
+ tmp_data := tmp_data or (reply_data_in_i(j*c_DATA_WIDTH+i) and REPLY_MUX_reading(j))
or (last_header_data(j*c_DATA_WIDTH+i) and reading_last_hdr(j));
end loop;
comb_REPLY_muxed_DATA(i) <= tmp_data;
end generate;
gen_reply_mux2 : for i in 0 to c_NUM_WIDTH-1 generate
- packet_num_mux : process(REPLY_PACKET_NUM_IN, REPLY_MUX_reading,packet_counter, reading_last_hdr)
+ packet_num_mux : process(reply_packet_num_in_i, REPLY_MUX_reading,packet_counter, reading_last_hdr)
variable tmp_pm : std_logic;
begin
tmp_pm := '0';
gen_pm_mux : for j in 0 to POINT_NUMBER-1 loop
- tmp_pm := tmp_pm or (REPLY_PACKET_NUM_IN(j*c_NUM_WIDTH+i) and REPLY_MUX_reading(j))
+ tmp_pm := tmp_pm or (reply_packet_num_in_i(j*c_NUM_WIDTH+i) and REPLY_MUX_reading(j))
or (packet_counter(i) and reading_last_hdr(j));
end loop;
comb_REPLY_muxed_PACKET_NUM(i) <= tmp_pm;
end process;
end generate;
- comb_REPLY_muxed_DATAREADY <= (or_all(REPLY_MUX_reading and REPLY_DATAREADY_IN and not current_REPLY_reading_trm) or or_all(reading_last_hdr)) and REPLY_MUX_real_reading;
+ comb_REPLY_muxed_DATAREADY <= (or_all(REPLY_MUX_reading and reply_dataready_in_i and not current_REPLY_reading_trm) or or_all(reading_last_hdr)) and REPLY_MUX_real_reading;
--REPLY POOL state machine
end if;
case packet_counter is
when c_F0 =>
- comb_REPLY_POOL_DATA <= REPLY_combined_trm_F0;
+ comb_REPLY_POOL_DATA <= x"0000"; --REPLY_combined_trm_F0;
when c_F1 =>
comb_REPLY_POOL_DATA <= REPLY_combined_trm_F1;
when c_F2 =>
process(CLK)
begin
if rising_edge(CLK) then
- if RESET = '1' then
+ if reset_i = '1' then
current_state <= SENDING_DATA;
REPLY_POOL_next_read <= '0';
waiting_for_init_finish <= '0';
)
port map (
CLK => CLK,
- RESET => RESET,
+ RESET => reset_i,
CLK_EN => CLK_EN,
COMB_DATAREADY_IN => comb_REPLY_POOL_DATAREADY,
COMB_next_READ_OUT => comb_REPLY_POOL_next_read,
USE_CHECKSUM : integer range 0 to 1 := c_YES;
SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
SECURE_MODE : integer range 0 to 1 := c_NO;
+ INIT_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES;
REPLY_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES
);
port(
end entity;
architecture trb_net16_ibuf_arch of trb_net16_ibuf is
+ -- Placer Directives
+ attribute HGROUP : string;
+ -- for whole architecture
+ attribute HGROUP of trb_net16_ibuf_arch : architecture is "IBUF_group";
component trb_net_CRC is
port(
end component;
-
signal fifo_data_in : std_logic_vector(c_DATA_WIDTH-1 downto 0);
signal fifo_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0);
signal fifo_packet_num_in : std_logic_vector(1 downto 0);
signal saved_packet_type : std_logic_vector(3 downto 0);
signal current_fifo_packet_type : std_logic_vector(3 downto 0);
signal saved_fifo_packet_type : std_logic_vector(3 downto 0);
-
+ signal next_fifo_data_out : std_logic_vector(15 downto 0);
+ signal next_fifo_packet_num_out : std_logic_vector(1 downto 0);
+ signal next_last_fifo_read : std_logic;
+ signal next_fifo_empty : std_logic;
signal next_read_out, reg_read_out : std_logic;
signal got_ack_init_internal, reg_ack_init_internal : std_logic;
signal counter_match : std_logic;
signal init_buffer_number : std_logic_vector(15 downto 0);
signal reply_buffer_number : std_logic_vector(15 downto 0);
+ signal next_fifo_full : std_logic;
+ signal fifo_value_waiting : std_logic;
+
+ signal reg_med_data_in : std_logic_vector(15 downto 0);
+ signal reg_med_dataready_in : std_logic;
+ signal reg_med_packet_num_in : std_logic_vector(2 downto 0);
+
+ attribute syn_preserve : boolean;
+ attribute syn_keep : boolean;
+ attribute syn_preserve of fifo_data_in : signal is true;
+ attribute syn_preserve of fifo_packet_num_in : signal is true;
+ attribute syn_keep of fifo_data_in : signal is true;
+ attribute syn_keep of fifo_packet_num_in : signal is true;
+ attribute syn_sharing : string;
+ attribute syn_sharing of trb_net16_ibuf_arch : architecture is "off";
begin
counter_match <= '1';
DATA_IN => fifo_data_in,
PACKET_NUM_IN => fifo_packet_num_in,
WRITE_ENABLE_IN => fifo_write,
- DATA_OUT => fifo_data_out,
- PACKET_NUM_OUT => fifo_packet_num_out,
+ DATA_OUT => next_fifo_data_out,
+ PACKET_NUM_OUT => next_fifo_packet_num_out,
READ_ENABLE_IN => fifo_read,
- FULL_OUT => fifo_full,
- EMPTY_OUT => fifo_empty
+ FULL_OUT => next_fifo_full,
+ EMPTY_OUT => next_fifo_empty
);
- fifo_data_in <= MED_DATA_IN;
- fifo_packet_num_in <= MED_PACKET_NUM_IN(2) & MED_PACKET_NUM_IN(0);
+ PROC_NEXT_LAST_FIFO_READ : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if (fifo_read = '1' and next_fifo_empty = '0') or fifo_value_waiting = '1' then
+ if (comb_next_init_read = '1' and comb_next_reply_read = '1') then
+ next_last_fifo_read <= '1';
+ fifo_value_waiting <= '0';
+ else
+ fifo_value_waiting <= '1';
+ next_last_fifo_read <= '0';
+ end if;
+ else
+ fifo_value_waiting <= '0';
+ next_last_fifo_read <= '0';
+ end if;
+ end if;
+ end process;
+
+
+ PROC_SYNC_FIFO_OUTPUTS : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if next_last_fifo_read = '1' and (sbuf_init_free = '1' and sbuf_reply_free = '1') then
+ fifo_data_out <= next_fifo_data_out;
+ fifo_packet_num_out <= next_fifo_packet_num_out;
+ end if;
+ end if;
+ end process;
+
+ PROC_LAST_FIFO_READ : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ last_fifo_read <= '0';
+ fifo_empty <= '1';
+ fifo_full <= '0';
+ else
+ last_fifo_read <= next_last_fifo_read;
+ fifo_empty <= next_fifo_empty;
+ fifo_full <= next_fifo_full; --if full it's already too late
+ end if;
+ end if;
+ end process;
+
+ PROC_FIFO_READ_BEFORE : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ fifo_read_before <= '0';
+ else
+ if next_last_fifo_read = '1' then
+ fifo_read_before <= '1';
+ elsif ( (sbuf_INIT_free and not current_fifo_packet_type(3))
+ or (sbuf_REPLY_free and current_fifo_packet_type(3)) or throw_away) = '1' then
+ fifo_read_before <= '0';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ PROC_LED : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ reg_med_data_in <= MED_DATA_IN;
+ reg_med_packet_num_in <= MED_PACKET_NUM_IN;
+ reg_med_dataready_in <= MED_DATAREADY_IN;
+ end if;
+ end process;
+
+ fifo_data_in <= reg_med_data_in;
+ fifo_packet_num_in <= reg_med_packet_num_in(2) & reg_med_packet_num_in(0);
--regenerate long packet numbers
- fifo_long_packet_num_out(2) <= fifo_packet_num_out(1);
- fifo_long_packet_num_out(0) <= fifo_packet_num_out(0);
- fifo_long_packet_num_out(1) <= not saved_fifo_long_packet_num_out(1) when last_fifo_read = '1' and not saved_fifo_long_packet_num_out(2) = '1' and saved_fifo_long_packet_num_out(0) = '1' else saved_fifo_long_packet_num_out(1);
+-- fifo_long_packet_num_out(2) <= fifo_packet_num_out(1);
+-- fifo_long_packet_num_out(0) <= fifo_packet_num_out(0);
+-- fifo_long_packet_num_out(1) <= not saved_fifo_long_packet_num_out(1) when last_fifo_read = '1' and not saved_fifo_long_packet_num_out(2) = '1' and saved_fifo_long_packet_num_out(0) = '1' else saved_fifo_long_packet_num_out(1);
process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
- saved_fifo_long_packet_num_out <= (others => '0');
- elsif last_fifo_read = '1' then
- saved_fifo_long_packet_num_out <= fifo_long_packet_num_out;
+ fifo_long_packet_num_out <= (others => '0');
+ elsif next_last_fifo_read = '1' then
+-- saved_fifo_long_packet_num_out <= fifo_long_packet_num_out;
+ fifo_long_packet_num_out(2) <= next_fifo_packet_num_out(1);
+ fifo_long_packet_num_out(0) <= next_fifo_packet_num_out(0);
+ if fifo_long_packet_num_out(2) = '0' and fifo_long_packet_num_out(0) = '1' then
+ fifo_long_packet_num_out(1) <= not fifo_long_packet_num_out(1);
+ else
+ fifo_long_packet_num_out(1) <= fifo_long_packet_num_out(1);
+ end if;
end if;
end if;
end process;
end if;
end process;
--create comb. real packet type
- current_packet_type <= MED_DATA_IN(3 downto 0) when (MED_PACKET_NUM_IN = c_H0)
- else saved_packet_type;
- current_fifo_packet_type <= fifo_data_out(3 downto 0) when (fifo_long_packet_num_out = c_H0)
+-- current_packet_type <= MED_DATA_IN(3 downto 0) when (MED_PACKET_NUM_IN = c_H0)
+-- else saved_packet_type;
+ current_fifo_packet_type <= fifo_data_out(3 downto 0) when (fifo_packet_num_out(1)='1')--fifo_long_packet_num_out = c_H0
else saved_fifo_packet_type;
gen_crc : if USE_CHECKSUM = 1 generate
process(last_fifo_read, fifo_long_packet_num_out, current_fifo_packet_type)
begin
- CRC_enable <= last_fifo_read and not fifo_long_packet_num_out(2);
+ CRC_enable <= last_fifo_read and not fifo_packet_num_out(1); --not fifo_long_packet_num_out(2);
if current_fifo_packet_type(2 downto 0) = TYPE_TRM or (current_fifo_packet_type(2 downto 0) = TYPE_EOB) then
CRC_enable <= '0';
end if;
if (current_fifo_packet_type(2 downto 0) = TYPE_EOB or current_fifo_packet_type(2 downto 0) = TYPE_TRM) and fifo_long_packet_num_out = c_F0 then
- CRC_enable <= '1';
+ CRC_enable <= last_fifo_read;
end if;
end process;
end generate;
------------------------
--control incoming data
------------------------
- FILTER_DATA_IN : process(MED_DATA_IN, MED_DATAREADY_IN, MED_PACKET_NUM_IN,
+ FILTER_DATA_IN : process(reg_MED_DATA_IN, reg_MED_DATAREADY_IN, reg_MED_PACKET_NUM_IN,
fifo_full, current_rec_buffer_size_out,
- current_error_state, reg_read_out, current_packet_type)
+ current_error_state, reg_read_out, saved_packet_type)
begin -- process
got_ack_init_internal <= '0';
got_ack_reply_internal <= '0';
fifo_write <= '0';
next_rec_buffer_size_out <= current_rec_buffer_size_out;
next_error_state <= current_error_state;
- if MED_DATAREADY_IN = '1' and reg_read_out= '1' then
- if current_packet_type(2 downto 0) = TYPE_ACK and USE_ACKNOWLEDGE = 1 then
- if MED_PACKET_NUM_IN = c_H0 and current_error_state /= GOT_OVERFLOW_ERROR then
- got_ack_init_internal <= not current_packet_type(3);
- got_ack_reply_internal <= current_packet_type(3);
+ if reg_MED_DATAREADY_IN = '1' and reg_read_out= '1' then
+ if saved_packet_type(2 downto 0) = TYPE_ACK and USE_ACKNOWLEDGE = 1 then
+ if reg_MED_PACKET_NUM_IN = c_H0 and current_error_state /= GOT_OVERFLOW_ERROR then
+ got_ack_init_internal <= not saved_packet_type(3);
+ got_ack_reply_internal <= saved_packet_type(3);
end if;
- if MED_PACKET_NUM_IN = c_F1 then
+ if reg_MED_PACKET_NUM_IN = c_F1 then
next_rec_buffer_size_out <= MED_DATA_IN(3 downto 0);
end if;
- elsif not (current_packet_type(2 downto 0) = TYPE_ILLEGAL) then
+ elsif not (saved_packet_type(2 downto 0) = TYPE_ILLEGAL) then
fifo_write <= '1';
if fifo_full = '1' then
next_error_state <= GOT_OVERFLOW_ERROR;
------------------------
--generate output logic
------------------------
- gensecure : if SECURE_MODE = 1 generate
- SBUF_INIT: trb_net16_sbuf
- generic map (
- Version => SBUF_VERSION
- )
- port map (
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- COMB_DATAREADY_IN => tmp_INT_INIT_DATAREADY_OUT,
- COMB_next_READ_OUT => comb_next_init_read,
- COMB_READ_IN => '1',
- COMB_DATA_IN => tmp_INT_DATA_OUT,
- COMB_PACKET_NUM_IN => tmp_INT_PACKET_NUM_OUT,
- SYN_DATAREADY_OUT => INT_INIT_DATAREADY_OUT,
- SYN_DATA_OUT => INT_INIT_DATA_OUT,
- SYN_PACKET_NUM_OUT => INT_INIT_PACKET_NUM_OUT,
- SYN_READ_IN => INT_INIT_READ_IN,
- STAT_BUFFER => stat_sbufs(0)
- );
- process(CLK)
- begin
- if rising_edge(CLK) then
- sbuf_init_free <= comb_next_init_read;
- end if;
- end process;
+-- gensecure : if SECURE_MODE = 1 generate
+ gen_init_sbuf : if INIT_CAN_RECEIVE_DATA = c_YES generate
+ SBUF_INIT: trb_net16_sbuf
+ generic map (
+ Version => SBUF_VERSION
+ )
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ COMB_DATAREADY_IN => tmp_INT_INIT_DATAREADY_OUT,
+ COMB_next_READ_OUT => comb_next_init_read,
+ COMB_READ_IN => '1',
+ COMB_DATA_IN => tmp_INT_DATA_OUT,
+ COMB_PACKET_NUM_IN => tmp_INT_PACKET_NUM_OUT,
+ SYN_DATAREADY_OUT => INT_INIT_DATAREADY_OUT,
+ SYN_DATA_OUT => INT_INIT_DATA_OUT,
+ SYN_PACKET_NUM_OUT => INT_INIT_PACKET_NUM_OUT,
+ SYN_READ_IN => INT_INIT_READ_IN,
+ STAT_BUFFER => stat_sbufs(0)
+ );
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ sbuf_init_free <= comb_next_init_read;
+ end if;
+ end process;
+ end generate;
+ gen_no_init_sbuf : if INIT_CAN_RECEIVE_DATA = c_NO generate
+ sbuf_init_free <= '1';
+ INT_INIT_DATA_OUT <= (others => '0');
+ INT_INIT_PACKET_NUM_OUT <= (others => '0');
+ INT_INIT_DATAREADY_OUT <= '0';
+ stat_sbufs(0) <= '0';
+ comb_next_init_read <= '1';
+ end generate;
gen_reply_sbuf : if REPLY_CAN_RECEIVE_DATA = c_YES generate
SBUF_REPLY: trb_net16_sbuf
stat_sbufs(1) <= '0';
comb_next_reply_read <= '1';
end generate;
- end generate;
- gen_notsecure : if SECURE_MODE = 0 generate
- INT_INIT_DATA_OUT <= tmp_INT_DATA_OUT;
- INT_INIT_PACKET_NUM_OUT <= tmp_INT_PACKET_NUM_OUT;
- INT_INIT_DATAREADY_OUT <= tmp_INT_INIT_DATAREADY_OUT;
- sbuf_INIT_free <= INT_INIT_READ_IN;
- INT_REPLY_DATA_OUT <= tmp_INT_DATA_OUT;
- INT_REPLY_PACKET_NUM_OUT <= tmp_INT_PACKET_NUM_OUT;
- INT_REPLY_DATAREADY_OUT <= tmp_INT_REPLY_DATAREADY_OUT;
- sbuf_REPLY_free <= INT_REPLY_READ_IN;
- comb_next_init_read <= '1';
- comb_next_reply_read <= '1';
- stat_sbufs <= (others => '0');
- end generate;
+-- end generate;
+-- gen_notsecure : if SECURE_MODE = 0 generate
+-- INT_INIT_DATA_OUT <= tmp_INT_DATA_OUT;
+-- INT_INIT_PACKET_NUM_OUT <= tmp_INT_PACKET_NUM_OUT;
+-- INT_INIT_DATAREADY_OUT <= tmp_INT_INIT_DATAREADY_OUT;
+-- sbuf_INIT_free <= INT_INIT_READ_IN;
+-- INT_REPLY_DATA_OUT <= tmp_INT_DATA_OUT;
+-- INT_REPLY_PACKET_NUM_OUT <= tmp_INT_PACKET_NUM_OUT;
+-- INT_REPLY_DATAREADY_OUT <= tmp_INT_REPLY_DATAREADY_OUT;
+-- sbuf_REPLY_free <= INT_REPLY_READ_IN;
+-- comb_next_init_read <= '1';
+-- comb_next_reply_read <= '1';
+-- stat_sbufs <= (others => '0');
+-- end generate;
process(fifo_data_out, fifo_long_packet_num_out, sbuf_init_free, RESET,
fifo_empty, sbuf_reply_free, last_fifo_read, current_fifo_packet_type,
- fifo_read_before, CRC_match, throw_away)
+ fifo_read_before, CRC_match, throw_away, comb_next_init_read, comb_next_reply_read)
begin
tmp_INT_DATA_OUT <= fifo_data_out;
got_eob_init_out <= '0';
got_eob_reply_out <= '0';
throw_away <= '0';
- if RESET = '1' then
- CRC_RESET <= '1';
- else
- CRC_RESET <= '0';
- end if;
+ CRC_RESET <= RESET;
+
if USE_CHECKSUM = 1 then
if current_fifo_packet_type(2 downto 0) = TYPE_TRM and fifo_long_packet_num_out = c_F2 and CRC_active = '1' then
tmp_INT_DATA_OUT(3) <= fifo_data_out(3) or not CRC_match;
CRC_RESET <= '1';
end if;
end if;
- if REPLY_CAN_RECEIVE_DATA = c_NO then
- tmp_INT_REPLY_DATAREADY_OUT <= '0';
- end if;
- fifo_read <= not fifo_empty and not (fifo_read_before and not
- ((sbuf_init_free and not current_fifo_packet_type(3))
- or (sbuf_reply_free and current_fifo_packet_type(3))
- ));
+-- fifo_read <= not fifo_empty and not (fifo_read_before and not
+-- ((sbuf_init_free and not current_fifo_packet_type(3))
+-- or (sbuf_reply_free and current_fifo_packet_type(3))
+-- ));
+ fifo_read <= ((not fifo_read_before and not next_last_fifo_read) or (sbuf_init_free and sbuf_reply_free)) and not fifo_value_waiting;
if (fifo_read_before = '1' and (current_fifo_packet_type(2 downto 0) /= TYPE_EOB)) then
- if SECURE_MODE = 1 then
- tmp_INT_INIT_DATAREADY_OUT <= (sbuf_init_free) and not current_fifo_packet_type(3);
- if REPLY_CAN_RECEIVE_DATA = c_YES then
- tmp_INT_REPLY_DATAREADY_OUT <= (sbuf_reply_free ) and current_fifo_packet_type(3);
+-- if SECURE_MODE = 1 then
+ if INIT_CAN_RECEIVE_DATA = c_YES then
+ tmp_INT_INIT_DATAREADY_OUT <= (sbuf_init_free and sbuf_reply_free) and not current_fifo_packet_type(3);
end if;
- else
- tmp_INT_INIT_DATAREADY_OUT <= not current_fifo_packet_type(3);
if REPLY_CAN_RECEIVE_DATA = c_YES then
- tmp_INT_REPLY_DATAREADY_OUT <= current_fifo_packet_type(3);
+ tmp_INT_REPLY_DATAREADY_OUT <= (sbuf_reply_free and sbuf_init_free) and current_fifo_packet_type(3);
end if;
- end if;
+-- else
+-- tmp_INT_INIT_DATAREADY_OUT <= not current_fifo_packet_type(3);
+-- if REPLY_CAN_RECEIVE_DATA = c_YES then
+-- tmp_INT_REPLY_DATAREADY_OUT <= current_fifo_packet_type(3);
+-- end if;
+-- end if;
end if;
if last_fifo_read = '1' then
end if;
end process;
- process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- last_fifo_read <= '0';
- else
- last_fifo_read <= fifo_read;
- end if;
- end if;
- end process;
-
- process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- fifo_read_before <= '0';
- else
- if fifo_read = '1' then
- fifo_read_before <= '1';
- elsif ( (sbuf_INIT_free and not current_fifo_packet_type(3))
- or (sbuf_REPLY_free and current_fifo_packet_type(3)) or throw_away) = '1' then
- fifo_read_before <= '0';
- end if;
- end if;
- end if;
- end process;
+-- process(CLK)
+-- begin
+-- if rising_edge(CLK) then
+-- if RESET = '1' then
+-- last_fifo_read <= '0';
+-- else
+-- last_fifo_read <= fifo_read;
+-- end if;
+-- end if;
+-- end process;
+--
+-- process(CLK)
+-- begin
+-- if rising_edge(CLK) then
+-- if RESET = '1' then
+-- fifo_read_before <= '0';
+-- else
+-- if fifo_read = '1' then
+-- fifo_read_before <= '1';
+-- elsif ( (sbuf_INIT_free and not current_fifo_packet_type(3))
+-- or (sbuf_REPLY_free and current_fifo_packet_type(3)) or throw_away) = '1' then
+-- fifo_read_before <= '0';
+-- end if;
+-- end if;
+-- end if;
+-- end process;
gen_ack1 : if USE_ACKNOWLEDGE = 1 generate
proc_reg_eob_out: process(CLK)
init_buffer_number <= (others => '1');
reply_buffer_number <= (others => '1');
elsif CLK_EN = '1' then
- if got_eob_init_out = '1' then
+ if reg_eob_init_out = '1' then
init_buffer_number <= init_buffer_number + 1;
end if;
- if got_eob_reply_out = '1' then
+ if reg_eob_reply_out = '1' then
reply_buffer_number <= reply_buffer_number + 1;
end if;
end if;
end process;
STAT_BUFFER(14) <= fifo_write;
- STAT_BUFFER(17 downto 15) <= current_packet_type(2 downto 0);
- STAT_BUFFER(31 downto 18) <= (others => '0');
+ STAT_BUFFER(17 downto 15) <= saved_packet_type(2 downto 0);
+ STAT_BUFFER(18) <= CRC_match;
+ STAT_BUFFER(19) <= CRC_enable;
+ STAT_BUFFER(20) <= CRC_RESET;
+ STAT_BUFFER(31 downto 21) <= (others => '0');
INT_ERROR_OUT <= MED_ERROR_IN;
USE_CHECKSUM : integer range 0 to 1 := c_YES;
USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES;
+ INIT_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES;
REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES;
REPLY_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES
);
end entity;
architecture trb_net16_iobuf_arch of trb_net16_iobuf is
+ -- Placer Directives
+ attribute HGROUP : string;
+ -- for whole architecture
+ attribute HGROUP of trb_net16_iobuf_arch : architecture is "IOBUF_group";
+
component trb_net16_obuf is
generic (
USE_CHECKSUM : integer range 0 to 1 := c_YES;
SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
SECURE_MODE : integer range 0 to 1 := c_YES;
+ INIT_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES;
REPLY_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES
);
port(
USE_CHECKSUM => USE_CHECKSUM,
SBUF_VERSION => SBUF_VERSION,
SECURE_MODE => IBUF_SECURE_MODE,
+ INIT_CAN_RECEIVE_DATA => INIT_CAN_RECEIVE_DATA,
REPLY_CAN_RECEIVE_DATA => REPLY_CAN_RECEIVE_DATA
)
port map (
--- /dev/null
+--media interface with 16 data lines, single data rate and oversampling of RX input
+--oversampling running at 250 MHz
+
+
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+
+library work;
+use work.trb_net_std.all;
+
+entity trb_net16_med_8_DDR_OS is
+ generic(
+ TRANSMISSION_CLOCK_DIV: integer range 1 to 10 := 1
+ );
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ INT_DATAREADY_OUT : out std_logic;
+ INT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ INT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ INT_READ_IN : in std_logic;
+
+ INT_DATAREADY_IN : in std_logic;
+ INT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ INT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ INT_READ_OUT : out std_logic;
+
+ -- Media direction port
+ TX_DATA_OUT : out std_logic_vector (7 downto 0);
+ TX_CLK_OUT : out std_logic;
+ TX_CTRL_OUT : out std_logic_vector (1 downto 0);
+ RX_DATA_IN : in std_logic_vector (7 downto 0);
+ RX_CLK_IN : in std_logic;
+ RX_CTRL_IN : in std_logic_vector (1 downto 0);
+
+ -- Status and control port
+ STAT_OP: out std_logic_vector (15 downto 0);
+ CTRL_OP: in std_logic_vector (15 downto 0);
+
+ STAT: out std_logic_vector (31 downto 0);
+ CTRL: in std_logic_vector (31 downto 0)
+ );
+end entity;
+
+architecture trb_net16_med_8_DDR_OS_arch of trb_net16_med_8_DDR_OS is
+
+ component trb_net_clock_generator is
+ generic(
+ FREQUENCY_IN : real;
+ FREQUENCY_OUT : real;
+ CLOCK_MULT : integer range 1 to 32;
+ CLOCK_DIV : integer range 1 to 32;
+ CLKIN_DIVIDE_BY_2 : boolean;
+ CLKIN_PERIOD : real
+ );
+ port(
+ RESET : in std_logic;
+ CLK_IN : in std_logic;
+ CLK_OUT : out std_logic;
+ LOCKED : out std_logic
+ );
+ end component;
+
+ component trb_net_fifo_16bit_bram_dualport is
+ generic(
+ USE_STATUS_FLAGS : integer := c_YES
+ );
+ port (
+ read_clock_in: IN std_logic;
+ write_clock_in: IN std_logic;
+ read_enable_in: IN std_logic;
+ write_enable_in: IN std_logic;
+ fifo_gsr_in: IN std_logic;
+ write_data_in: IN std_logic_vector(17 downto 0);
+ read_data_out: OUT std_logic_vector(17 downto 0);
+ full_out: OUT std_logic;
+ empty_out: OUT std_logic;
+ fifostatus_out: OUT std_logic_vector(3 downto 0);
+ valid_read_out: OUT std_logic;
+ almost_empty_out:OUT std_logic;
+ almost_full_out :OUT std_logic
+ );
+ end component;
+
+ component signal_sync is
+ generic(
+ WIDTH : integer := 1; --
+ DEPTH : integer := 3
+ );
+ port(
+ RESET : in std_logic; --Reset is neceessary to avoid optimization to shift register
+ CLK0 : in std_logic; --clock for first FF
+ CLK1 : in std_logic; --Clock for other FF
+ D_IN : in std_logic_vector(WIDTH-1 downto 0); --Data input
+ D_OUT : out std_logic_vector(WIDTH-1 downto 0) --Data output
+ );
+ end component;
+
+ signal RECV_CLK, recv_clk_locked : std_logic;
+ signal reg_RX_CLK, buf_RX_CLK, last_RX_CLK : std_logic;
+ signal reg_RX_CTRL, buf_RX_CTRL : std_logic_vector(1 downto 0);
+ signal reg_RX_DATA, buf_RX_DATA : std_logic_vector(7 downto 0);
+
+ signal rx_datavalid : std_logic;
+ signal rx_reset : std_logic;
+
+ signal rx_fifo_read_enable : std_logic;
+ signal rx_fifo_write_enable, next_rx_fifo_write_enable: std_logic;
+ signal rx_fifo_data_in, next_rx_fifo_data_in : std_logic_vector(17 downto 0);
+ signal rx_fifo_data_out : std_logic_vector(17 downto 0);
+ signal rx_fifo_full : std_logic;
+ signal rx_fifo_empty : std_logic;
+ signal rx_fifostatus_out : std_logic_vector(3 downto 0);
+ signal rx_valid_read_out : std_logic;
+ signal rx_almost_empty_out : std_logic;
+ signal rx_almost_full_out : std_logic;
+ signal saved_fifo_data_out : std_logic_vector(7 downto 0);
+
+ signal buf_INT_DATAREADY_OUT : std_logic;
+
+ signal rx_packet_counter : std_logic_vector(3 downto 0);
+ signal wait_for_startup : std_logic;
+ signal wait_for_startup_slow : std_logic;
+ signal rx_CLK_counter : std_logic_vector(4 downto 0);
+ signal rx_clock_detect : std_logic;
+
+ signal med_reset : std_logic;
+
+ signal tx_datavalid, tx_first_packet, tx_reset, tx_parity : std_logic;
+ signal buf_INT_DATA_IN : std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ signal buf_INT_READ_OUT : std_logic;
+ signal tx_clock_enable : std_logic;
+ signal next_tx_reset : std_logic;
+ signal buf_tx_reset : std_logic;
+ signal buf_tx_clk : std_logic;
+ signal recv_clk_real_locked : std_logic;
+ signal locked_counter : std_logic_vector(19 downto 0);
+
+ signal led_counter : std_logic_vector(18 downto 0);
+ signal rx_led, tx_led, link_led : std_logic;
+ signal med_error : std_logic_vector(2 downto 0);
+
+ signal tx_data : std_logic_vector(7 downto 0);
+ signal tx_word_waiting : std_logic;
+ signal tx_data_buffer : std_logic_vector(7 downto 0);
+ signal next_recv_clk_locked : std_logic;
+ signal recv_clk_real_locked_q : std_logic;
+begin
+
+
+--Transmitter (full speed only)
+-------------------------
+ INT_READ_OUT <= buf_INT_READ_OUT;
+
+
+
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ TX_CLK_OUT <= buf_tx_clk;
+ TX_DATA_OUT <= tx_data;
+ TX_CTRL_OUT(0) <= tx_datavalid;
+ TX_CTRL_OUT(1) <= buf_tx_reset;
+ end if;
+ end process;
+
+
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if med_reset = '1' then
+ buf_tx_reset <= '1';
+ buf_tx_clk <= '0';
+ else
+ buf_tx_reset <= (recv_clk_real_locked_q and wait_for_startup_slow);
+ buf_tx_clk <= not buf_tx_clk;
+ end if;
+ end if;
+ end process;
+
+
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if med_reset = '1' then
+ tx_datavalid <= '0';
+ buf_INT_DATA_IN <= (others => '0');
+ buf_INT_READ_OUT <= '0';
+ tx_data <= (others => '0');
+ tx_word_waiting <= '0';
+ else
+ if tx_word_waiting = '1' then
+ tx_data <= tx_data_buffer;
+ tx_datavalid <= '1';
+ buf_INT_READ_OUT <= not wait_for_startup_slow and not buf_tx_reset;
+ tx_word_waiting <= '0';
+ elsif INT_DATAREADY_IN = '1' and buf_INT_READ_OUT = '1' then
+ tx_data <= INT_DATA_IN(15 downto 8);
+ tx_data_buffer <= INT_DATA_IN(7 downto 0);
+ tx_datavalid <= '1';
+ tx_word_waiting <= '1';
+ buf_INT_READ_OUT <= '0';
+ else
+ tx_datavalid <= '0';
+ buf_INT_READ_OUT <= not wait_for_startup_slow and not buf_tx_reset;
+ end if;
+ end if;
+ end if;
+ end process;
+
+
+
+--Receiver
+-------------------------
+ RECV_CLOCK_GEN : trb_net_clock_generator
+ generic map(
+ FREQUENCY_IN => 100.0,
+ FREQUENCY_OUT => 200.0,
+ CLOCK_MULT => 2,
+ CLOCK_DIV => 1,
+ CLKIN_DIVIDE_BY_2 => false,
+ CLKIN_PERIOD => 10.0
+ )
+ port map(
+ RESET => RESET,
+ CLK_IN => CLK,
+ CLK_OUT => RECV_CLK,
+ LOCKED => recv_clk_locked
+ );
+
+-- THE_SYNC_TO_CLK : signal_sync
+-- generic map(
+-- DEPTH => 2,
+-- WIDTH => 1
+-- )
+-- port map(
+-- RESET => RESET,
+-- D_IN(0) => next_recv_clk_locked,
+-- CLK0 => CLK,
+-- CLK1 => CLK,
+-- D_OUT(0) => recv_clk_locked
+-- );
+
+ THE_SYNC_TO_CLK_0 : signal_sync
+ generic map(
+ DEPTH => 3,
+ WIDTH => 1
+ )
+ port map(
+ RESET => RESET,
+ D_IN(0) => recv_clk_real_locked,
+ CLK0 => CLK,
+ CLK1 => CLK,
+ D_OUT(0) => recv_clk_real_locked_q
+ );
+
+process(CLK)
+ begin
+ if rising_edge(RECV_CLK) then
+ if recv_clk_locked = '0' then
+ locked_counter <= (others => '0');
+ recv_clk_real_locked <= '0';
+ else
+ if locked_counter /= x"0000F" then
+ locked_counter <= locked_counter + 1;
+ else
+ recv_clk_real_locked <= '1';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ RX_INPUT_REG : process(RECV_CLK)
+ begin
+ if rising_edge(RECV_CLK) then
+ reg_RX_CLK <= RX_CLK_IN;
+ reg_RX_CTRL <= RX_CTRL_IN;
+ reg_RX_DATA <= RX_DATA_IN;
+ end if;
+ end process;
+
+ RX_REG : process(RECV_CLK, recv_clk_real_locked)
+ begin
+ if rising_edge(RECV_CLK) then
+ if recv_clk_real_locked = '0' then
+ buf_RX_CTRL <= (others => '0');
+ buf_RX_CLK <= '0';
+ last_RX_CLK <= '0';
+ buf_RX_DATA <= (others => '0');
+ else
+ buf_RX_CLK <= reg_RX_CLK;
+ buf_RX_DATA <= reg_RX_DATA;
+ buf_RX_CTRL <= reg_RX_CTRL;
+ last_RX_CLK <= buf_RX_CLK;
+ end if;
+ end if;
+ end process;
+
+ rx_datavalid <= buf_RX_CTRL(0);
+ rx_reset <= buf_RX_CTRL(1);
+
+ next_rx_fifo_write_enable <= (buf_RX_CLK xor last_RX_CLK) and rx_datavalid;
+ next_rx_fifo_data_in <= x"00" & '0' & '0' & buf_RX_DATA;
+
+ reg_fifo_in : process(RECV_CLK)
+ begin
+ if rising_edge(RECV_CLK) then
+ rx_fifo_write_enable <= next_rx_fifo_write_enable;
+ rx_fifo_data_in <= next_rx_fifo_data_in;
+ end if;
+ end process;
+
+ RX_FIFO : trb_net_fifo_16bit_bram_dualport
+ port map(
+ read_clock_in => CLK,
+ write_clock_in => RECV_CLK,
+ read_enable_in => rx_fifo_read_enable,
+ write_enable_in => rx_fifo_write_enable,
+ fifo_gsr_in => med_reset,
+ write_data_in => rx_fifo_data_in,
+ read_data_out => rx_fifo_data_out,
+ full_out => rx_fifo_full,
+ empty_out => rx_fifo_empty,
+ fifostatus_out => rx_fifostatus_out,
+ valid_read_out => rx_valid_read_out,
+ almost_empty_out => rx_almost_empty_out,
+ almost_full_out => rx_almost_full_out
+ );
+
+ rx_fifo_read_enable <= INT_READ_IN;
+
+ proc_rx_dataoutput : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ INT_DATA_OUT <= saved_fifo_data_out(7 downto 0) & rx_fifo_data_out(7 downto 0);
+ INT_PACKET_NUM_OUT <= rx_packet_counter(3 downto 1);
+ INT_DATAREADY_OUT <= buf_INT_DATAREADY_OUT;
+ end if;
+ end process;
+
+ packet_counter_p : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if med_reset = '1' then
+ rx_packet_counter <= "0111";
+ elsif rx_fifo_read_enable = '1' and rx_fifo_empty = '0' then
+ if rx_packet_counter = c_max_word_number & '1' then
+ rx_packet_counter <= (others => '0');
+ else
+ rx_packet_counter <= rx_packet_counter + 1;
+ end if;
+ end if;
+ end if;
+ end process;
+
+
+ rx_dataready_p : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if med_reset = '1' then
+ buf_INT_DATAREADY_OUT <= '0';
+ saved_fifo_data_out <= (others => '0');
+ else
+ buf_INT_DATAREADY_OUT <= rx_fifo_read_enable and not rx_fifo_empty and not rx_packet_counter(0);
+ if rx_fifo_read_enable = '1' and rx_fifo_empty = '0' and rx_packet_counter(0) = '1' then
+ saved_fifo_data_out <= rx_fifo_data_out(7 downto 0);
+ end if;
+ end if;
+ end if;
+ end process;
+
+
+--monitor link
+-------------------------
+
+ THE_SYNCTOCLK : signal_sync
+ generic map(
+ DEPTH => 3,
+ WIDTH => 1
+ )
+ port map(
+ RESET => RESET,
+ D_IN(0) => wait_for_startup,
+ CLK0 => CLK,
+ CLK1 => CLK,
+ D_OUT(0) => wait_for_startup_slow
+ );
+
+
+ process(RECV_CLK, recv_clk_real_locked,med_reset)
+ begin
+ if rising_edge(RECV_CLK) then
+ if recv_clk_real_locked = '0' or med_reset = '1' or rx_clock_detect = '0' then
+ wait_for_startup <= '1';
+ elsif rx_reset = '1' and recv_clk_real_locked = '1' then --
+ wait_for_startup <= '0';
+ end if;
+ end if;
+ end process;
+
+
+ ERROR_OUT_gen : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if recv_clk_real_locked = '0' or rx_clock_detect = '0' then -- or wait_for_startup_slow = '1'
+ med_error <= ERROR_NC;
+ else
+ med_error <= ERROR_OK;
+ end if;
+ end if;
+ end process;
+
+
+ rx_clk_detect_counter: process (RECV_CLK, recv_clk_real_locked)
+ begin
+ if rising_edge(RECV_CLK) then
+ if recv_clk_real_locked = '0' then
+ rx_CLK_counter <= (others => '0');
+ rx_clock_detect <= '0';
+ elsif buf_RX_CLK = '1' and last_RX_CLK = '0' then
+ rx_CLK_counter <= (others => '0');
+ rx_clock_detect <= '1';
+ elsif rx_CLK_counter /= 31 then
+ rx_CLK_counter <= rx_CLK_counter + 1;
+ elsif rx_CLK_counter = 31 then
+ rx_clock_detect <= '0';
+ end if;
+ end if;
+ end process;
+
+
+--STAT & CTRL Ports
+-------------------------
+
+--LED
+ link_led <= rx_clock_detect and not wait_for_startup_slow;
+
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if led_counter(18) = '1' then
+ led_counter <= (others => '0');
+ else
+ led_counter <= led_counter + 1;
+ end if;
+ if rx_fifo_empty = '0' then
+ rx_led <= '1';
+ elsif led_counter(18) = '1' then
+ rx_led <= '0';
+ end if;
+ if tx_datavalid = '1' then
+ tx_led <= '1';
+ elsif led_counter(18) = '1' then
+ tx_led <= '0';
+ end if;
+ end if;
+ end process;
+
+
+ STAT_OP(2 downto 0) <= med_error;
+ STAT_OP(8 downto 3) <= (others => '0');
+ STAT_OP(9) <= link_led;
+ STAT_OP(10) <= rx_led;
+ STAT_OP(11) <= tx_led;
+ STAT_OP(12) <= '0';
+ STAT_OP(13) <= '0'; --trbnet_reset;
+ STAT_OP(14) <= rx_clock_detect;
+ STAT_OP(15) <= '1' when rx_reset = '1' and wait_for_startup_slow = '0' else '0';
+
+
+ STAT(7 downto 0) <= buf_RX_DATA;
+ STAT(9 downto 8) <= buf_RX_CTRL;
+ STAT(10) <= buf_RX_CLK;
+ STAT(11) <= wait_for_startup_slow;
+ STAT(12) <= rx_fifo_empty;
+ STAT(13) <= rx_fifo_read_enable;
+ STAT(14) <= rx_fifo_write_enable;
+ STAT(15) <= rx_clock_detect;
+ STAT(31 downto 16) <= (others => '0');
+
+ med_reset <= RESET;
+-- trbnet_reset <= rx_reset or not recv_clk_real_locked;
+
+
+end architecture;
\ No newline at end of file
+++ /dev/null
---Media interface for Lattice ECP2M using PCS at 2GHz
-
---Still missing: fifo full error handling
-
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.std_logic_ARITH.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-
-entity trb_net16_med_ecp_sfp is
- generic(
- SERDES_NUM : integer range 0 to 3 := 0
- );
- port(
- CLK : in std_logic;
- RESET : in std_logic; -- synchronous reset
- CLK_EN : in std_logic;
- --Internal Connection
- MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
- MED_DATAREADY_IN : in std_logic;
- MED_READ_OUT : out std_logic;
- MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
- MED_DATAREADY_OUT : out std_logic;
- MED_READ_IN : in std_logic;
- --SFP Connection
- SD_RXD_P_IN : in std_logic;
- SD_RXD_N_IN : in std_logic;
- SD_TXD_P_OUT : out std_logic;
- SD_TXD_N_OUT : out std_logic;
- SD_REFCLK_P_IN : in std_logic;
- SD_REFCLK_N_IN : in std_logic;
- SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
- SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
- -- Status and control port
- STAT_OP : out std_logic_vector (15 downto 0);
- CTRL_OP : in std_logic_vector (15 downto 0);
- STAT_DEBUG : out std_logic_vector (63 downto 0);
- CTRL_DEBUG : in std_logic_vector (63 downto 0)
- );
-end entity;
-
-architecture med_ecp_sfp of trb_net16_med_ecp_sfp is
-
- component serdes_0
- port(
- core_txrefclk : in std_logic;
- core_rxrefclk : in std_logic;
--- refclkp : IN std_logic;
--- refclkn : IN std_logic;
- hdinp0 : in std_logic;
- hdinn0 : in std_logic;
- ff_rxiclk_ch0 : in std_logic;
- ff_txiclk_ch0 : in std_logic;
- ff_ebrd_clk_0 : in std_logic;
- ff_txdata_ch0 : in std_logic_vector(15 downto 0);
- ff_tx_k_cntrl_ch0 : in std_logic_vector(1 downto 0);
- ff_force_disp_ch0 : in std_logic_vector(1 downto 0);
- ff_disp_sel_ch0 : in std_logic_vector(1 downto 0);
- ff_correct_disp_ch0 : in std_logic_vector(1 downto 0);
- ffc_rrst_ch0 : in std_logic;
- ffc_lane_tx_rst_ch0 : in std_logic;
- ffc_lane_rx_rst_ch0 : in std_logic;
- ffc_txpwdnb_ch0 : in std_logic;
- ffc_rxpwdnb_ch0 : in std_logic;
- ffc_macro_rst : in std_logic;
- ffc_quad_rst : in std_logic;
- ffc_trst : in std_logic;
- hdoutp0 : out std_logic;
- hdoutn0 : out std_logic;
- ff_rxdata_ch0 : out std_logic_vector(15 downto 0);
- ff_rx_k_cntrl_ch0 : out std_logic_vector(1 downto 0);
- ff_rxfullclk_ch0 : out std_logic;
- ff_rxhalfclk_ch0 : out std_logic;
- ff_disp_err_ch0 : out std_logic_vector(1 downto 0);
- ff_cv_ch0 : out std_logic_vector(1 downto 0);
- ffs_rlos_lo_ch0 : out std_logic;
- ffs_ls_sync_status_ch0 : out std_logic;
- ffs_cc_underrun_ch0 : out std_logic;
- ffs_cc_overrun_ch0 : out std_logic;
- ffs_txfbfifo_error_ch0 : out std_logic;
- ffs_rxfbfifo_error_ch0 : out std_logic;
- ffs_rlol_ch0 : out std_logic;
- oob_out_ch0 : out std_logic;
- ff_txfullclk : out std_logic;
- ff_txhalfclk : out std_logic;
- ffs_plol : out std_logic
- );
- end component;
-
- component serdes_1
- port(
- core_txrefclk : in std_logic;
- core_rxrefclk : in std_logic;
- hdinp1 : in std_logic;
- hdinn1 : in std_logic;
- ff_rxiclk_ch1 : in std_logic;
- ff_txiclk_ch1 : in std_logic;
- ff_ebrd_clk_1 : in std_logic;
- ff_txdata_ch1 : in std_logic_vector(15 downto 0);
- ff_tx_k_cntrl_ch1 : in std_logic_vector(1 downto 0);
- ff_force_disp_ch1 : in std_logic_vector(1 downto 0);
- ff_disp_sel_ch1 : in std_logic_vector(1 downto 0);
- ff_correct_disp_ch1 : in std_logic_vector(1 downto 0);
- ffc_rrst_ch1 : in std_logic;
- ffc_lane_tx_rst_ch1 : in std_logic;
- ffc_lane_rx_rst_ch1 : in std_logic;
- ffc_txpwdnb_ch1 : in std_logic;
- ffc_rxpwdnb_ch1 : in std_logic;
- ffc_macro_rst : in std_logic;
- ffc_quad_rst : in std_logic;
- ffc_trst : in std_logic;
- hdoutp1 : out std_logic;
- hdoutn1 : out std_logic;
- ff_rxdata_ch1 : out std_logic_vector(15 downto 0);
- ff_rx_k_cntrl_ch1 : out std_logic_vector(1 downto 0);
- ff_rxfullclk_ch1 : out std_logic;
- ff_rxhalfclk_ch1 : out std_logic;
- ff_disp_err_ch1 : out std_logic_vector(1 downto 0);
- ff_cv_ch1 : out std_logic_vector(1 downto 0);
- ffs_rlos_lo_ch1 : out std_logic;
- ffs_ls_sync_status_ch1 : out std_logic;
- ffs_cc_underrun_ch1 : out std_logic;
- ffs_cc_overrun_ch1 : out std_logic;
- ffs_txfbfifo_error_ch1 : out std_logic;
- ffs_rxfbfifo_error_ch1 : out std_logic;
- ffs_rlol_ch1 : out std_logic;
- oob_out_ch1 : out std_logic;
- ff_txfullclk : out std_logic;
- ff_txhalfclk : out std_logic;
- ffs_plol : out std_logic
- );
- end component;
-
-
- component serdes_2
- port(
- core_txrefclk : in std_logic;
- core_rxrefclk : in std_logic;
- hdinp2 : in std_logic;
- hdinn2 : in std_logic;
- ff_rxiclk_ch2 : in std_logic;
- ff_txiclk_ch2 : in std_logic;
- ff_ebrd_clk_2 : in std_logic;
- ff_txdata_ch2 : in std_logic_vector(15 downto 0);
- ff_tx_k_cntrl_ch2 : in std_logic_vector(1 downto 0);
- ff_force_disp_ch2 : in std_logic_vector(1 downto 0);
- ff_disp_sel_ch2 : in std_logic_vector(1 downto 0);
- ff_correct_disp_ch2 : in std_logic_vector(1 downto 0);
- ffc_rrst_ch2 : in std_logic;
- ffc_lane_tx_rst_ch2 : in std_logic;
- ffc_lane_rx_rst_ch2 : in std_logic;
- ffc_txpwdnb_ch2 : in std_logic;
- ffc_rxpwdnb_ch2 : in std_logic;
- ffc_macro_rst : in std_logic;
- ffc_quad_rst : in std_logic;
- ffc_trst : in std_logic;
- hdoutp2 : out std_logic;
- hdoutn2 : out std_logic;
- ff_rxdata_ch2 : out std_logic_vector(15 downto 0);
- ff_rx_k_cntrl_ch2 : out std_logic_vector(1 downto 0);
- ff_rxfullclk_ch2 : out std_logic;
- ff_rxhalfclk_ch2 : out std_logic;
- ff_disp_err_ch2 : out std_logic_vector(1 downto 0);
- ff_cv_ch2 : out std_logic_vector(1 downto 0);
- ffs_rlos_lo_ch2 : out std_logic;
- ffs_ls_sync_status_ch2 : out std_logic;
- ffs_cc_underrun_ch2 : out std_logic;
- ffs_cc_overrun_ch2 : out std_logic;
- ffs_txfbfifo_error_ch2 : out std_logic;
- ffs_rxfbfifo_error_ch2 : out std_logic;
- ffs_rlol_ch2 : out std_logic;
- oob_out_ch2 : out std_logic;
- ff_txfullclk : out std_logic;
- ff_txhalfclk : out std_logic;
- ffs_plol : out std_logic
- );
- end component;
-
- component serdes_3
- port(
- core_txrefclk : in std_logic;
- core_rxrefclk : in std_logic;
- hdinp3 : in std_logic;
- hdinn3 : in std_logic;
- ff_rxiclk_ch3 : in std_logic;
- ff_txiclk_ch3 : in std_logic;
- ff_ebrd_clk_3 : in std_logic;
- ff_txdata_ch3 : in std_logic_vector(15 downto 0);
- ff_tx_k_cntrl_ch3 : in std_logic_vector(1 downto 0);
- ff_force_disp_ch3 : in std_logic_vector(1 downto 0);
- ff_disp_sel_ch3 : in std_logic_vector(1 downto 0);
- ff_correct_disp_ch3 : in std_logic_vector(1 downto 0);
- ffc_rrst_ch3 : in std_logic;
- ffc_lane_tx_rst_ch3 : in std_logic;
- ffc_lane_rx_rst_ch3 : in std_logic;
- ffc_txpwdnb_ch3 : in std_logic;
- ffc_rxpwdnb_ch3 : in std_logic;
- ffc_macro_rst : in std_logic;
- ffc_quad_rst : in std_logic;
- ffc_trst : in std_logic;
- hdoutp3 : out std_logic;
- hdoutn3 : out std_logic;
- ff_rxdata_ch3 : out std_logic_vector(15 downto 0);
- ff_rx_k_cntrl_ch3 : out std_logic_vector(1 downto 0);
- ff_rxfullclk_ch3 : out std_logic;
- ff_rxhalfclk_ch3 : out std_logic;
- ff_disp_err_ch3 : out std_logic_vector(1 downto 0);
- ff_cv_ch3 : out std_logic_vector(1 downto 0);
- ffs_rlos_lo_ch3 : out std_logic;
- ffs_ls_sync_status_ch3 : out std_logic;
- ffs_cc_underrun_ch3 : out std_logic;
- ffs_cc_overrun_ch3 : out std_logic;
- ffs_txfbfifo_error_ch3 : out std_logic;
- ffs_rxfbfifo_error_ch3 : out std_logic;
- ffs_rlol_ch3 : out std_logic;
- oob_out_ch3 : out std_logic;
- ff_txfullclk : out std_logic;
- ff_txhalfclk : out std_logic;
- ffs_plol : out std_logic
- );
- end component;
-
- component trb_net_fifo_16bit_bram_dualport is
- generic(
- USE_STATUS_FLAGS : integer := c_YES
- );
- port(
- read_clock_in : in std_logic;
- write_clock_in : in std_logic;
- read_enable_in : in std_logic;
- write_enable_in : in std_logic;
- fifo_gsr_in : in std_logic;
- write_data_in : in std_logic_vector(17 downto 0);
- read_data_out : out std_logic_vector(17 downto 0);
- full_out : out std_logic;
- empty_out : out std_logic;
- fifostatus_out : out std_logic_vector(3 downto 0);
- valid_read_out : out std_logic;
- almost_empty_out : out std_logic;
- almost_full_out : out std_logic
- );
- end component;
-
- component signal_sync is
- generic(
- WIDTH : integer := 1; --
- DEPTH : integer := 3
- );
- port(
- RESET : in std_logic;
- CLK0 : in std_logic;
- CLK1 : in std_logic;
- D_IN : in std_logic_vector(WIDTH-1 downto 0);
- D_OUT : out std_logic_vector(WIDTH-1 downto 0)
- );
- end component;
-
- --reset signals
- signal ffc_quad_rst : std_logic;
- signal ffc_lane_tx_rst : std_logic;
- signal ffc_lane_rx_rst : std_logic;
- --serdes connections
- signal tx_data : std_logic_vector(15 downto 0);
- signal tx_k : std_logic_vector(1 downto 0);
- signal rx_data : std_logic_vector(15 downto 0);
- signal rx_k : std_logic_vector(1 downto 0);
- signal link_ok : std_logic_vector(0 downto 0);
- signal link_error : std_logic_vector(8 downto 0);
- signal ff_rxhalfclk : std_logic;
- signal ff_txhalfclk : std_logic;
- --rx fifo signals
- signal fifo_rx_rd_en : std_logic;
- signal fifo_rx_wr_en : std_logic;
- signal fifo_rx_reset : std_logic;
- signal fifo_rx_din : std_logic_vector(17 downto 0);
- signal fifo_rx_dout : std_logic_vector(17 downto 0);
- signal fifo_rx_full : std_logic;
- signal fifo_rx_empty : std_logic;
- --tx fifo signals
- signal fifo_tx_rd_en : std_logic;
- signal fifo_tx_wr_en : std_logic;
- signal fifo_tx_reset : std_logic;
- signal fifo_tx_din : std_logic_vector(17 downto 0);
- signal fifo_tx_dout : std_logic_vector(17 downto 0);
- signal fifo_tx_full : std_logic;
- signal fifo_tx_empty : std_logic;
- --rx path
- signal rx_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0);
- signal buf_med_dataready_out : std_logic;
- signal buf_med_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0);
- signal buf_med_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0);
- signal last_rx : std_logic_vector(8 downto 0);
- signal last_fifo_rx_empty : std_logic;
- --tx path
- signal last_fifo_tx_empty : std_logic;
- --link status
- signal link_led : std_logic;
-
-
- -- state machine signals
- type STATES is ( SLEEP, QRST, WPAR, WLOS, ALIGN, WRXA, WTXA, LINK );
- signal CURRENT_STATE, NEXT_STATE: STATES;
- signal state_bits : std_logic_vector(3 downto 0);
- signal clock : std_logic;
-
- signal med_error_x : std_logic_vector(2 downto 0);
- signal med_error : std_logic_vector(2 downto 0);
-
- signal timing_ctr : std_logic_vector(28 downto 0);
- signal ce_ctr_x : std_logic;
- signal ce_ctr : std_logic;
- signal rst_ctr_x : std_logic;
- signal rst_ctr : std_logic;
- signal quad_rst_x : std_logic;
- signal quad_rst : std_logic;
- signal lane_rst_x : std_logic;
- signal lane_rst : std_logic;
- signal rx_allow_x : std_logic;
- signal rx_allow : std_logic;
- signal tx_allow_x : std_logic;
- signal tx_allow : std_logic;
- signal align_me_x : std_logic;
- signal align_me : std_logic;
- signal resync_x : std_logic;
- signal resync : std_logic;
- signal reset_me_x : std_logic;
- signal reset_me : std_logic;
-
- signal rx_k_q : std_logic_vector(1 downto 0);
-
- signal info_led : std_logic;
-
- signal rx_allow_q : std_logic; -- clock domain changed signal
- signal tx_allow_q : std_logic;
- signal swap_bytes : std_logic;
-
- -- status inputs from SFP
- signal sfp_prsnt_n : std_logic; -- synchronized input signals
- signal sfp_los : std_logic; -- synchronized input signals
-
- signal buf_STAT_OP : std_logic_vector(15 downto 15);
- signal buf_RESET_TRBNET_OUT : std_logic;
- signal resync_counter : std_logic_vector(2 downto 0);
- signal send_resync_counter : std_logic_vector(11 downto 0);
- signal next_send_resync : std_logic;
- signal send_resync : std_logic;
-
- signal led_counter : std_logic_vector(17 downto 0);
- signal rx_led, tx_led : std_logic;
-
-begin
-
---------------------------------------------------------------------------
--- Main control state machine, startup control for SFP
---------------------------------------------------------------------------
-clock <= CLK;
-
--- Input synchronizer
-
-THE_SFP_STATUS_SYNC: signal_sync
- generic map(
- DEPTH => 3,
- WIDTH => 2
- )
- port map(
- RESET => RESET,
- D_IN(1) => SD_PRSNT_N_IN,
- D_IN(0) => SD_LOS_IN,
- CLK0 => clock,
- CLK1 => clock,
- D_OUT(0) => sfp_prsnt_n,
- D_OUT(1) => sfp_los
- );
-
--- Transfering the komma delimiter in the *training* phase
-THE_RX_K_SYNC: signal_sync
- generic map(
- DEPTH => 3,
- WIDTH => 2
- )
- port map(
- RESET => RESET,
- D_IN => rx_k,
- CLK0 => ff_rxhalfclk,
- CLK1 => clock,
- D_OUT => rx_k_q
- );
-
-
-
-
--- "Swap Bytes" indicator
-THE_SWAP_BYTES_PROC: process( clock )
-begin
- if( rising_edge(clock) ) then
- if ( (align_me = '1') and (rx_k_q = "10") ) then
- swap_bytes <= '1';
- elsif( (align_me = '1') and (rx_k_q = "01") ) then
- swap_bytes <= '0';
- end if;
- end if;
-end process THE_SWAP_BYTES_PROC;
-
--- Timing counter for reset sequencing
-THE_TIMING_COUNTER_PROC: process( clock )
-begin
- if( rising_edge(clock) ) then
- if ( rst_ctr = '1' ) then
- timing_ctr <= (others => '0');
- elsif( ce_ctr = '1' ) then
- timing_ctr <= timing_ctr + 1;
- end if;
- end if;
-end process THE_TIMING_COUNTER_PROC;
-
--- State machine
--- state registers
-STATE_MEM: process( clock, RESET )
-begin
- if( RESET = '1' ) then
- CURRENT_STATE <= SLEEP;
- ce_ctr <= '0';
- rst_ctr <= '0';
- quad_rst <= '1';
- lane_rst <= '1';
- rx_allow <= '0';
- tx_allow <= '0';
- align_me <= '0';
- reset_me <= '1';
- resync <= '1';
- med_error <= ERROR_NC;
- elsif( rising_edge(clock) ) then
- CURRENT_STATE <= NEXT_STATE;
- ce_ctr <= ce_ctr_x;
- rst_ctr <= rst_ctr_x;
- quad_rst <= quad_rst_x;
- lane_rst <= lane_rst_x;
- rx_allow <= rx_allow_x;
- tx_allow <= tx_allow_x;
- align_me <= align_me_x;
- reset_me <= reset_me_x;
- resync <= resync_x;
- med_error <= med_error_x;
- end if;
-end process STATE_MEM;
-
--- state transitions
-PROC_STATE_TRANSFORM: process( CURRENT_STATE, sfp_prsnt_n, sfp_los, timing_ctr, link_error, rst_ctr,
- link_ok, rx_k_q, send_resync )
-begin
- NEXT_STATE <= SLEEP; -- avoid latches
- ce_ctr_x <= '0';
- rst_ctr_x <= '0';
- quad_rst_x <= '0';
- lane_rst_x <= '0';
- rx_allow_x <= '0';
- tx_allow_x <= '0';
- align_me_x <= '0';
- reset_me_x <= '1';
- resync_x <= '1';
- med_error_x <= ERROR_NC;
- case CURRENT_STATE is
- when SLEEP => if( sfp_prsnt_n = '0' ) then
- NEXT_STATE <= QRST; -- do a correctly timed QUAD reset (about 150ns)
- rst_ctr_x <= '1';
- quad_rst_x <= '1';
- lane_rst_x <= '1';
- else
- NEXT_STATE <= SLEEP; -- wait for SFP present signal
- ce_ctr_x <= '1';
- quad_rst_x <= '1';
- lane_rst_x <= '1';
- end if;
- when QRST => if( (timing_ctr(4) = '1') and (rst_ctr = '0') ) then
- NEXT_STATE <= WPAR; -- release QUAD_RST, wait for RLOL and PLOL deassertation
- lane_rst_x <= '1';
- else
- NEXT_STATE <= QRST; -- count delay
- ce_ctr_x <= '1';
- quad_rst_x <= '1';
- lane_rst_x <= '1';
- end if;
- when WPAR => if ( sfp_prsnt_n = '1' ) then
- NEXT_STATE <= SLEEP; -- taking out SFP during operation must be taken into account
- quad_rst_x <= '1';
- lane_rst_x <= '1';
- ce_ctr_x <= '1';
- elsif( (link_error(4) = '0') and (link_error(5) = '0') and (sfp_los = '0') ) then
- NEXT_STATE <= WLOS;
- rst_ctr_x <= '1';
- else
- NEXT_STATE <= WPAR; -- wait for RLOL and PLOL and incoming signal from SFP
- lane_rst_x <= '1';
- ce_ctr_x <= '1';
- end if;
- when WLOS => if ( (timing_ctr(27) = '0') and (timing_ctr(26) = '0') and (rst_ctr = '0') ) then
- NEXT_STATE <= WLOS;
- resync_x <= '0';
- ce_ctr_x <= '1';
- elsif( (timing_ctr(27) = '1') and (rst_ctr = '0') ) then
- NEXT_STATE <= ALIGN; -- debounce before aligning
- align_me_x <= '1';
- reset_me_x <= '0';
- ce_ctr_x <= '1';
- else
- NEXT_STATE <= WLOS; -- no fibre, no alignment
- ce_ctr_x <= '1';
- end if;
- when ALIGN => if( (rx_k_q = "10") or (rx_k_q = "01") ) then
- NEXT_STATE <= WRXA; -- one komma character has been received
- --rst_ctr_x <= '1';
- reset_me_x <= '0';
- med_error_x <= ERROR_WAIT;
- else
- NEXT_STATE <= ALIGN; -- wait for komma character
- ce_ctr_x <= '1';
- align_me_x <= '1';
- reset_me_x <= '0';
- med_error_x <= ERROR_WAIT;
- end if;
- when WRXA => if( (timing_ctr(28) = '1') and (rst_ctr = '0') ) then
- NEXT_STATE <= WTXA; -- wait cycle done, allow reception of data
- rst_ctr_x <= '1';
- rx_allow_x <= '1';
- reset_me_x <= '0';
- med_error_x <= ERROR_WAIT;
- else
- NEXT_STATE <= WRXA; -- wait one complete cycle (2^27 x 10ns = 1.3s)
- ce_ctr_x <= '1';
- reset_me_x <= '0';
- med_error_x <= ERROR_WAIT;
- end if;
- when WTXA => if( (timing_ctr(28) = '1') and (rst_ctr = '0') ) then
- NEXT_STATE <= LINK; -- wait cycle done, allow transmission of data
- rst_ctr_x <= '1';
- rx_allow_x <= '1';
- tx_allow_x <= '1';
- ce_ctr_x <= '1';
- reset_me_x <= '0';
- med_error_x <= ERROR_OK;
- else
- NEXT_STATE <= WTXA; -- wait one complete cycle (2^27 x 10ns = 1.3s)
- ce_ctr_x <= '1';
- rx_allow_x <= '1';
- reset_me_x <= '0';
- med_error_x <= ERROR_WAIT;
- end if;
- when LINK => if( (sfp_prsnt_n = '1') or (sfp_los = '1')) then
- NEXT_STATE <= SLEEP;
- quad_rst_x <= '1';
- lane_rst_x <= '1';
- rst_ctr_x <= '1';
- elsif send_resync = '1' then
- NEXT_STATE <= WRXA;
- reset_me_x <= '0';
- med_error_x <= ERROR_WAIT;
- else
- NEXT_STATE <= LINK;
- rx_allow_x <= '1';
- tx_allow_x <= '1';
- ce_ctr_x <= '1';
- reset_me_x <= '0';
- med_error_x <= ERROR_OK;
- end if;
- when others => NEXT_STATE <= SLEEP;
- end case;
-end process;
-
-THE_DECODE_PROC: process( CURRENT_STATE )
-begin
- case CURRENT_STATE is
- when SLEEP => state_bits <= "0000";
- when QRST => state_bits <= "0001";
- when WPAR => state_bits <= "0010";
- when WLOS => state_bits <= "0011";
- when ALIGN => state_bits <= "0100";
- when WRXA => state_bits <= "0101";
- when WTXA => state_bits <= "0110";
- when LINK => state_bits <= "0111";
- when others => state_bits <= "1111";
- end case;
-end process THE_DECODE_PROC;
-
-THE_RX_ALLOW_SYNC: signal_sync
- generic map(
- DEPTH => 2,
- WIDTH => 2
- )
- port map(
- RESET => RESET,
- D_IN(0) => rx_allow,
- D_IN(1) => tx_allow,
- CLK0 => clock, --ff_rxhalfclk,
- CLK1 => clock, --ff_rxhalfclk,
- D_OUT(0) => rx_allow_q,
- D_OUT(1) => tx_allow_q
- );
-
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-
-ffc_quad_rst <= quad_rst;
-ffc_lane_tx_rst <= lane_rst;
-ffc_lane_rx_rst <= lane_rst;
-
-
--- Instantiation of serdes module
- gen_serdes_0 : if SERDES_NUM = 0 generate
- THE_SERDES: serdes_0
- port map(
- core_txrefclk => clk,
- core_rxrefclk => clk,
--- refclkp => SD_REFCLK_P_IN,
--- refclkn => SD_REFCLK_N_IN,
- hdinp0 => sd_rxd_p_in,
- hdinn0 => sd_rxd_n_in,
- ff_rxiclk_ch0 => ff_rxhalfclk,
- ff_txiclk_ch0 => ff_txhalfclk,
- ff_ebrd_clk_0 => ff_rxhalfclk, -- not used, just for completeness
- ff_txdata_ch0 => tx_data,
- ff_tx_k_cntrl_ch0 => tx_k,
- ff_force_disp_ch0 => "00",
- ff_disp_sel_ch0 => "00",
- ff_correct_disp_ch0 => "00",
- ffc_rrst_ch0 => '0',
- ffc_lane_tx_rst_ch0 => ffc_lane_tx_rst,
- ffc_lane_rx_rst_ch0 => ffc_lane_rx_rst,
- ffc_txpwdnb_ch0 => '1',
- ffc_rxpwdnb_ch0 => '1',
- ffc_macro_rst => '0',
- ffc_quad_rst => ffc_quad_rst,
- ffc_trst => '0',
- hdoutp0 => sd_txd_p_out,
- hdoutn0 => sd_txd_n_out,
- ff_rxdata_ch0 => rx_data, --comb_rx_data,
- ff_rx_k_cntrl_ch0 => rx_k, --comb_rx_k,
- ff_rxfullclk_ch0 => open,
- ff_rxhalfclk_ch0 => ff_rxhalfclk,
- ff_disp_err_ch0 => open,
- ff_cv_ch0 => link_error(7 downto 6),
- ffs_rlos_lo_ch0 => link_error(8),
- ffs_ls_sync_status_ch0 => link_ok(0),
- ffs_cc_underrun_ch0 => link_error(0),
- ffs_cc_overrun_ch0 => link_error(1),
- ffs_txfbfifo_error_ch0 => link_error(2),
- ffs_rxfbfifo_error_ch0 => link_error(3),
- ffs_rlol_ch0 => link_error(4),
- oob_out_ch0 => open,
- ff_txfullclk => open,
- ff_txhalfclk => ff_txhalfclk,
- ffs_plol => link_error(5)
- );
- end generate;
- gen_serdes_1 : if SERDES_NUM = 1 generate
- THE_SERDES: serdes_1
- port map(
- core_txrefclk => clk,
- core_rxrefclk => clk,
- hdinp1 => sd_rxd_p_in,
- hdinn1 => sd_rxd_n_in,
- ff_rxiclk_ch1 => ff_rxhalfclk,
- ff_txiclk_ch1 => ff_txhalfclk,
- ff_ebrd_clk_1 => ff_rxhalfclk, -- not used, just for completeness
- ff_txdata_ch1 => tx_data,
- ff_tx_k_cntrl_ch1 => tx_k,
- ff_force_disp_ch1 => "00",
- ff_disp_sel_ch1 => "00",
- ff_correct_disp_ch1 => "00",
- ffc_rrst_ch1 => '0',
- ffc_lane_tx_rst_ch1 => ffc_lane_tx_rst,
- ffc_lane_rx_rst_ch1 => ffc_lane_rx_rst,
- ffc_txpwdnb_ch1 => '1',
- ffc_rxpwdnb_ch1 => '1',
- ffc_macro_rst => '0',
- ffc_quad_rst => ffc_quad_rst,
- ffc_trst => '0',
- hdoutp1 => sd_txd_p_out,
- hdoutn1 => sd_txd_n_out,
- ff_rxdata_ch1 => rx_data, --comb_rx_data,
- ff_rx_k_cntrl_ch1 => rx_k, --comb_rx_k,
- ff_rxfullclk_ch1 => open,
- ff_rxhalfclk_ch1 => ff_rxhalfclk,
- ff_disp_err_ch1 => open,
- ff_cv_ch1 => link_error(7 downto 6),
- ffs_rlos_lo_ch1 => link_error(8),
- ffs_ls_sync_status_ch1 => link_ok(0),
- ffs_cc_underrun_ch1 => link_error(0),
- ffs_cc_overrun_ch1 => link_error(1),
- ffs_txfbfifo_error_ch1 => link_error(2),
- ffs_rxfbfifo_error_ch1 => link_error(3),
- ffs_rlol_ch1 => link_error(4),
- oob_out_ch1 => open,
- ff_txfullclk => open,
- ff_txhalfclk => ff_txhalfclk,
- ffs_plol => link_error(5)
- );
- end generate;
- gen_serdes_2 : if SERDES_NUM = 2 generate
- THE_SERDES: serdes_2
- port map(
- core_txrefclk => clk,
- core_rxrefclk => clk,
- hdinp2 => sd_rxd_p_in,
- hdinn2 => sd_rxd_n_in,
- ff_rxiclk_ch2 => ff_rxhalfclk,
- ff_txiclk_ch2 => ff_txhalfclk,
- ff_ebrd_clk_2 => ff_rxhalfclk, -- not used, just for completeness
- ff_txdata_ch2 => tx_data,
- ff_tx_k_cntrl_ch2 => tx_k,
- ff_force_disp_ch2 => "00",
- ff_disp_sel_ch2 => "00",
- ff_correct_disp_ch2 => "00",
- ffc_rrst_ch2 => '0',
- ffc_lane_tx_rst_ch2 => ffc_lane_tx_rst,
- ffc_lane_rx_rst_ch2 => ffc_lane_rx_rst,
- ffc_txpwdnb_ch2 => '1',
- ffc_rxpwdnb_ch2 => '1',
- ffc_macro_rst => '0',
- ffc_quad_rst => ffc_quad_rst,
- ffc_trst => '0',
- hdoutp2 => sd_txd_p_out,
- hdoutn2 => sd_txd_n_out,
- ff_rxdata_ch2 => rx_data, --comb_rx_data,
- ff_rx_k_cntrl_ch2 => rx_k, --comb_rx_k,
- ff_rxfullclk_ch2 => open,
- ff_rxhalfclk_ch2 => ff_rxhalfclk,
- ff_disp_err_ch2 => open,
- ff_cv_ch2 => link_error(7 downto 6),
- ffs_rlos_lo_ch2 => link_error(8),
- ffs_ls_sync_status_ch2 => link_ok(0),
- ffs_cc_underrun_ch2 => link_error(0),
- ffs_cc_overrun_ch2 => link_error(1),
- ffs_txfbfifo_error_ch2 => link_error(2),
- ffs_rxfbfifo_error_ch2 => link_error(3),
- ffs_rlol_ch2 => link_error(4),
- oob_out_ch2 => open,
- ff_txfullclk => open,
- ff_txhalfclk => ff_txhalfclk,
- ffs_plol => link_error(5)
- );
- end generate;
- gen_serdes_3 : if SERDES_NUM = 3 generate
- THE_SERDES: serdes_3
- port map(
- core_txrefclk => clk,
- core_rxrefclk => clk,
- hdinp3 => sd_rxd_p_in,
- hdinn3 => sd_rxd_n_in,
- ff_rxiclk_ch3 => ff_rxhalfclk,
- ff_txiclk_ch3 => ff_txhalfclk,
- ff_ebrd_clk_3 => ff_rxhalfclk, -- not used, just for completeness
- ff_txdata_ch3 => tx_data,
- ff_tx_k_cntrl_ch3 => tx_k,
- ff_force_disp_ch3 => "00",
- ff_disp_sel_ch3 => "00",
- ff_correct_disp_ch3 => "00",
- ffc_rrst_ch3 => '0',
- ffc_lane_tx_rst_ch3 => ffc_lane_tx_rst,
- ffc_lane_rx_rst_ch3 => ffc_lane_rx_rst,
- ffc_txpwdnb_ch3 => '1',
- ffc_rxpwdnb_ch3 => '1',
- ffc_macro_rst => '0',
- ffc_quad_rst => ffc_quad_rst,
- ffc_trst => '0',
- hdoutp3 => sd_txd_p_out,
- hdoutn3 => sd_txd_n_out,
- ff_rxdata_ch3 => rx_data, --comb_rx_data,
- ff_rx_k_cntrl_ch3 => rx_k, --comb_rx_k,
- ff_rxfullclk_ch3 => open,
- ff_rxhalfclk_ch3 => ff_rxhalfclk,
- ff_disp_err_ch3 => open,
- ff_cv_ch3 => link_error(7 downto 6),
- ffs_rlos_lo_ch3 => link_error(8),
- ffs_ls_sync_status_ch3 => link_ok(0),
- ffs_cc_underrun_ch3 => link_error(0),
- ffs_cc_overrun_ch3 => link_error(1),
- ffs_txfbfifo_error_ch3 => link_error(2),
- ffs_rxfbfifo_error_ch3 => link_error(3),
- ffs_rlol_ch3 => link_error(4),
- oob_out_ch3 => open,
- ff_txfullclk => open,
- ff_txhalfclk => ff_txhalfclk,
- ffs_plol => link_error(5)
- );
- end generate;
-
-
--------------------------------------------------------------------------
--- RX Fifo & Data output
--------------------------------------------------------------------------
-THE_FIFO_SFP_TO_FPGA: trb_net_fifo_16bit_bram_dualport
- generic map(
- USE_STATUS_FLAGS => c_NO
- )
- port map(
- read_clock_in => clock,
- write_clock_in => ff_rxhalfclk,
- read_enable_in => fifo_rx_rd_en,
- write_enable_in => fifo_rx_wr_en,
- fifo_gsr_in => fifo_rx_reset,
- write_data_in => fifo_rx_din,
- read_data_out => fifo_rx_dout,
- full_out => fifo_rx_full,
- empty_out => fifo_rx_empty
- );
-
-fifo_rx_reset <= RESET;
-fifo_rx_rd_en <= '1';
-
--- Received bytes need to be swapped if the SerDes is "off by one" in its internal 8bit path
-THE_BYTE_SWAP_PROC: process( ff_rxhalfclk )
-begin
- if( rising_edge(ff_rxhalfclk) ) then
- last_rx <= rx_k(1) & rx_data(15 downto 8);
- if( swap_bytes = '0' ) then
- fifo_rx_din <= rx_k(1) & rx_k(0) & rx_data(15 downto 8) & rx_data(7 downto 0);
- fifo_rx_wr_en <= not rx_k(0) and rx_allow and link_ok(0);
- else
- fifo_rx_din <= rx_k(0) & last_rx(8) & rx_data(7 downto 0) & last_rx(7 downto 0);
- fifo_rx_wr_en <= not last_rx(8) and rx_allow and link_ok(0);
- end if;
- end if;
-end process THE_BYTE_SWAP_PROC;
-
-buf_med_data_out <= fifo_rx_dout(15 downto 0);
-buf_med_dataready_out <= not fifo_rx_dout(17) and not fifo_rx_dout(16) and not last_fifo_rx_empty and rx_allow_q;
-buf_med_packet_num_out <= rx_counter;
-med_read_out <= tx_allow_q;
-
-THE_SYNC_PROC: process( clock )
-begin
- if( rising_edge(clock) ) then
- if RESET = '1' then
- med_dataready_out <= '0';
- else
- med_dataready_out <= buf_med_dataready_out;
- med_data_out <= buf_med_data_out;
- med_packet_num_out <= buf_med_packet_num_out;
- end if;
- end if;
-end process THE_SYNC_PROC;
-
---rx packet counter
----------------------
-THE_RX_PACKETS_PROC: process( clock )
-begin
- if( rising_edge(clock) ) then
- last_fifo_rx_empty <= fifo_rx_empty;
- if RESET = '1' or rx_allow_q = '0' then
- rx_counter <= c_H0;
- else
- if( buf_med_dataready_out = '1' ) then
- if( rx_counter = c_max_word_number ) then
- rx_counter <= (others => '0');
- else
- rx_counter <= rx_counter + 1;
- end if;
- end if;
- end if;
- end if;
-end process;
-
-
---Detect resync (incl. SFP_LOS)
----------------
-
-
- process(clock)
- begin
- if rising_edge(clock) then
- buf_STAT_OP(15) <= '0';
- buf_RESET_TRBNET_OUT <= '0';
- if reset_me = '1' then
- buf_RESET_TRBNET_OUT <= '0';
- end if;
- if buf_MED_DATAREADY_OUT = '1' then
- if fifo_rx_dout(15 downto 0) = x"7F7F" then
- resync_counter <= resync_counter + 1;
- else
- resync_counter <= "000";
- end if;
- end if;
- if resync_counter(2) = '1' or sfp_los = '1' or link_error(7 downto 6) /= "00" then
- resync_counter <= resync_counter + 1;
- buf_STAT_OP(15) <= '1';
- buf_RESET_TRBNET_OUT <= '1';
- end if;
- if resync_counter = "111" then
- buf_STAT_OP(15) <= '0';
- buf_RESET_TRBNET_OUT <= '0';
- end if;
- end if;
- end process;
-
- process(clock)
- begin
- if rising_edge(clock) then
- if reset_me = '1' then
- next_send_resync <= '0';
- send_resync_counter <= (others => '0');
- else
- if not (send_resync_counter = 0) then
- send_resync_counter <= send_resync_counter + 1;
- end if;
- if CTRL_OP(15) = '1' and send_resync_counter = 0 then
- next_send_resync <= '1';
- send_resync_counter <= send_resync_counter + 1;
- end if;
- if send_resync_counter = x"00F" then
- next_send_resync <= '0';
- end if;
- end if;
- end if;
- end process;
-
- INST_SYNC_RESYNC : signal_sync
- generic map(
- WIDTH => 1,
- DEPTH => 2
- )
- port map(
- RESET => RESET,
- CLK0 => ff_txhalfclk,
- CLK1 => ff_txhalfclk,
- D_IN(0) => next_send_resync,
- D_OUT(0) => send_resync
- );
-
---TX Fifo & Data output to Serdes
----------------------
-THE_FIFO_FPGA_TO_SFP: trb_net_fifo_16bit_bram_dualport
- generic map(
- USE_STATUS_FLAGS => c_NO
- )
- port map(
- read_clock_in => ff_txhalfclk,
- write_clock_in => clock,
- read_enable_in => fifo_tx_rd_en,
- write_enable_in => fifo_tx_wr_en,
- fifo_gsr_in => fifo_tx_reset,
- write_data_in => fifo_tx_din,
- read_data_out => fifo_tx_dout,
- full_out => fifo_tx_full,
- empty_out => fifo_tx_empty
- );
-
-fifo_tx_reset <= RESET;
-fifo_tx_din <= med_packet_num_in(2) & med_packet_num_in(0)& med_data_in;
-fifo_tx_wr_en <= med_dataready_in and tx_allow_q;
-fifo_tx_rd_en <= tx_allow;
-
-
-THE_SERDES_INPUT_PROC: process( ff_txhalfclk )
-begin
- if( rising_edge(ff_txhalfclk) ) then
- last_fifo_tx_empty <= fifo_tx_empty;
- if( (last_fifo_tx_empty = '1') or (tx_allow = '0') ) then
- tx_data <= x"c5bc";
- tx_k <= "01";
- elsif send_resync = '1' then
- tx_data <= x"7F7F";
- tx_k <= "00";
- else
- tx_data <= fifo_tx_dout(15 downto 0);
- tx_k <= "00";
- end if;
- end if;
-end process THE_SERDES_INPUT_PROC;
-
-
-
---Generate LED signals
-----------------------
-process(clock)
- begin
- if rising_edge(clock) then
- led_counter <= led_counter + 1;
-
- if buf_med_dataready_out = '1' then
- rx_led <= '1';
- elsif led_counter = 0 then
- rx_led <= '0';
- end if;
-
- if tx_k(0) = '0' then
- tx_led <= '1';
- elsif led_counter = 0 then
- tx_led <= '0';
- end if;
-
- end if;
- end process;
-
-link_led <= (timing_ctr(24) or tx_allow_q) and not sfp_los;
-
-
-stat_op(2 downto 0) <= med_error;
-stat_op(8 downto 3) <= (others => '0'); -- unused
-stat_op(9) <= link_led;
-stat_op(10) <= rx_led; --rx led
-stat_op(11) <= tx_led; --tx led
-stat_op(12) <= '0'; -- unused
-stat_op(13) <= buf_RESET_TRBNET_OUT;
-stat_op(14) <= reset_me; -- reset out
-stat_op(15) <= buf_STAT_OP(15); -- protocol error
-
--- Debug output
-stat_debug(3 downto 0) <= state_bits;
-stat_debug(4) <= align_me;
-stat_debug(5) <= sfp_prsnt_n;
-stat_debug(6) <= rx_k(0);
-stat_debug(7) <= rx_k(1);
-stat_debug(8) <= rx_k_q(0);
-stat_debug(9) <= rx_k_q(1);
-stat_debug(18 downto 10) <= link_error;
-stat_debug(19) <= '0';
-stat_debug(20) <= link_ok(0);
-stat_debug(38 downto 21) <= fifo_rx_din;
-stat_debug(39) <= swap_bytes;
-stat_debug(40) <= fifo_rx_wr_en;
-stat_debug(41) <= info_led;
-stat_debug(42) <= resync;
-stat_debug(43) <= ff_rxhalfclk;
-stat_debug(44) <= ff_txhalfclk;
-stat_debug(59 downto 45) <= (others => '0');
-stat_debug(63 downto 60) <= link_error(3 downto 0);
-
-end architecture;
\ No newline at end of file
signal crc_match : std_logic;
signal buffer_number : std_logic_vector(15 downto 0);
+ signal buf_INT_READ_OUT : std_logic;
+ signal int_dataready_in_i : std_logic;
+ signal int_data_in_i : std_logic_vector(15 downto 0);
+ signal int_packet_num_in_i: std_logic_vector(2 downto 0);
begin
+
+ INT_READ_OUT <= buf_INT_READ_OUT;
+ buf_INT_READ_OUT <= not int_dataready_in_i or reg_INT_READ_OUT;
+
+ SYNC_INT_DATA_INPUTS : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ int_dataready_in_i <= '0';
+ elsif buf_INT_READ_OUT = '1' then --reply_dataready_in_i(i) = '0' or buf_REPLY_READ_OUT(i) = '1' then
+ int_dataready_in_i <= INT_DATAREADY_IN;
+ int_data_in_i <= INT_DATA_IN;
+ int_packet_num_in_i <= INT_PACKET_NUM_IN;
+ end if;
+ end if;
+ end process;
+
-- gen_sbuf : if SECURE_MODE = 1 generate
SBUF:trb_net16_sbuf
generic map (
-- sbuf_free <= MED_READ_IN;
-- end generate;
- INT_READ_OUT <= reg_INT_READ_OUT;
gen1 : if USE_ACKNOWLEDGE = 1 generate
max_DATA_COUNT_minus_one <= (others => '0');
end generate;
- GENERATE_WORDS : process(transfer_counter, SEND_BUFFER_SIZE_IN, INT_DATA_IN,
+ GENERATE_WORDS : process(transfer_counter, SEND_BUFFER_SIZE_IN, int_data_in_i,
CURRENT_DATA_COUNT, CRC, saved_packet_type,buffer_number, CTRL_BUFFER)
begin
current_NOP_word <= (others => '0');
current_ACK_word <= (others => '0');
current_EOB_word <= (others => '0');
- current_DATA_word <= INT_DATA_IN;
+ current_DATA_word <= int_data_in_i;
if transfer_counter = c_F0 then
current_EOB_word <= CRC;
if saved_packet_type = TYPE_TRM and USE_CHECKSUM = c_YES then
CLK => CLK,
RESET => CRC_RESET,
CLK_EN => CRC_enable,
- DATA_IN => INT_DATA_IN,
+ DATA_IN => int_data_in_i,
CRC_OUT => CRC,
CRC_match => crc_match
);
--the EOB and ACK flags must be available when the last packet is sent.
--full buffers (despite the sbuf) can only occur on the last packet.
COMB_NEXT_TRANSFER : process(comb_dataready, transfer_counter, current_NOP_word,
- INT_DATAREADY_IN,
- reg_INT_READ_OUT, saved_packet_type, sending_state,
+ int_dataready_in_i, reg_INT_READ_OUT,
+ buf_INT_READ_OUT, saved_packet_type, sending_state,
current_DATA_word, send_ACK, send_EOB, sbuf_free, RESET,
- current_ACK_word, current_EOB_word, INT_PACKET_NUM_IN,
+ current_ACK_word, current_EOB_word, int_packet_num_in_i,
TRANSMITTED_BUFFERS, send_DATA, comb_next_read)
begin
current_output_data_buffer <= current_NOP_word;
next_SEND_ACK_IN <= send_ACK;
comb_dataready <= '0';
next_sending_state <= sending_state;
- CRC_enable <= reg_INT_READ_OUT and INT_DATAREADY_IN and not INT_PACKET_NUM_IN(2);
+ CRC_enable <= reg_INT_READ_OUT and int_dataready_in_i and not int_packet_num_in_i(2);
CRC_RESET <= RESET;
--only data words are CRC'ed
- if (reg_INT_READ_OUT = '1' and INT_DATAREADY_IN = '1') then
+ if (reg_INT_READ_OUT = '1' and int_dataready_in_i = '1') then
--can only happen if idle or sending_data
current_output_data_buffer <= current_DATA_word;
comb_dataready <= '1';
end if;
end if;
- if send_EOB = '1' and transfer_counter = c_H0 and (reg_INT_READ_OUT and INT_DATAREADY_IN) = '0' then
+ if send_EOB = '1' and transfer_counter = c_H0 and (reg_INT_READ_OUT and int_dataready_in_i) = '0' then
next_sending_state <= sending_eob;
next_INT_READ_OUT <= '0';
end if;
- if send_ACK = '1' and transfer_counter = c_H0 and (reg_INT_READ_OUT and INT_DATAREADY_IN) = '0' then
+ if send_ACK = '1' and transfer_counter = c_H0 and (reg_INT_READ_OUT and int_dataready_in_i) = '0' then
next_sending_state <= sending_ack;
next_INT_READ_OUT <= '0';
end if;
if buf_MED_PACKET_NUM_OUT = c_F3 and MED_READ_IN = '1' then
transfer_counter := c_H0;
buf_MED_DATA_OUT(2 downto 0) <= TYPE_ACK;
+ buf_MED_DATAREADY_OUT <= '0';
end if;
buf_MED_PACKET_NUM_OUT <= transfer_counter;
- if transfer_counter = c_F3 then
+ if buf_MED_PACKET_NUM_OUT = c_F3 and MED_READ_IN = '1' then
reg_SEND_ACK_IN <= reg_SEND_ACK_IN_2 or SEND_ACK_IN;
reg_SEND_ACK_IN_2 <= reg_SEND_ACK_IN_2 and SEND_ACK_IN;
else
API_RUN_IN : in std_logic;
API_SEQNR_IN : in std_logic_vector (7 downto 0);
- --Port to write Unique ID
+ --Port to write Unique ID (-> 1-wire)
IDRAM_DATA_IN : in std_logic_vector(15 downto 0);
IDRAM_DATA_OUT : out std_logic_vector(15 downto 0);
IDRAM_ADDR_IN : in std_logic_vector(2 downto 0);
IDRAM_WR_IN : in std_logic;
+
+ --Informations
MY_ADDRESS_OUT : out std_logic_vector(15 downto 0);
+ GLOBAL_TIME : out std_logic_vector(31 downto 0);--global time, microseconds
+ LOCAL_TIME : out std_logic_vector(7 downto 0); --local time running with chip frequency
+ TIMER_US_TICK : out std_logic; --1 tick every microsecond
--Common Register in / out
COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REG_WIDTH-1 downto 0);
DAT_TIMEOUT_OUT : out std_logic;
--Additional write access to ctrl registers
- EXT_REG_DATA_IN : in std_logic_vector(31 downto 0);
- EXT_REG_DATA_OUT : out std_logic_vector(31 downto 0);
- EXT_REG_WRITE_IN : in std_logic;
- EXT_REG_ADDR_IN : in std_logic_vector(7 downto 0);
STAT : out std_logic_vector(31 downto 0);
STAT_ADDR_DEBUG : out std_logic_vector(15 downto 0)
);
elsif REGISTERS_OUT_write_enable(i) = '1' then
tmp := saved_Reg_high & saved_Reg_low;
buf_REGISTERS_OUT(j) <= tmp(j-i*c_REGIO_REG_WIDTH);
- elsif EXT_REG_WRITE_IN = '1' and EXT_REG_ADDR_IN = (conv_std_logic_vector(i,8) or x"D0") then
- buf_REGISTERS_OUT(j) <= EXT_REG_DATA_IN(j-i*c_REGIO_REG_WIDTH);
+-- elsif EXT_REG_WRITE_IN = '1' and EXT_REG_ADDR_IN = (conv_std_logic_vector(i,8) or x"D0") then
+-- buf_REGISTERS_OUT(j) <= EXT_REG_DATA_IN(j-i*c_REGIO_REG_WIDTH);
end if;
end if;
end process;
elsif COMMON_REGISTERS_OUT_write_enable(i) = '1' then
tmp := saved_Reg_high & saved_Reg_low;
buf_COMMON_CTRL_REG_OUT(j) <= tmp(j-i*c_REGIO_REG_WIDTH);
- elsif EXT_REG_WRITE_IN = '1' and EXT_REG_ADDR_IN = (conv_std_logic_vector(i,8) or x"20") then
- buf_COMMON_CTRL_REG_OUT(j) <= EXT_REG_DATA_IN(j-i*c_REGIO_REG_WIDTH);
+-- elsif EXT_REG_WRITE_IN = '1' and EXT_REG_ADDR_IN = (conv_std_logic_vector(i,8) or x"20") then
+-- buf_COMMON_CTRL_REG_OUT(j) <= EXT_REG_DATA_IN(j-i*c_REGIO_REG_WIDTH);
end if;
end if;
end process;
end generate;
- ext_data_output : process(CLK)
- variable regnum_STAT : integer range 0 to 2**NUM_STAT_REGS-1;
- variable regnum_CTRL : integer range 0 to 2**NUM_CTRL_REGS-1;
- variable regnum_cSTAT : integer range 0 to std_COMSTATREG-1;
- variable regnum_cCTRL : integer range 0 to std_COMCTRLREG-1;
- begin
- regnum_STAT := conv_integer(EXT_REG_ADDR_IN(NUM_STAT_REGS-1 downto 0));
- regnum_CTRL := conv_integer(EXT_REG_ADDR_IN(NUM_CTRL_REGS-1 downto 0));
- regnum_cSTAT := conv_integer(EXT_REG_ADDR_IN(std_COMneededwidth-1 downto 0));
- regnum_cCTRL := conv_integer(EXT_REG_ADDR_IN(std_COMneededwidth-1 downto 0));
- if rising_edge(CLK) then
- if RESET = '1' then
- EXT_REG_DATA_OUT <= (others => '0');
- elsif EXT_REG_ADDR_IN(7 downto 6) = "01" then
- EXT_REG_DATA_OUT <= (others => '0');
- elsif EXT_REG_ADDR_IN(7 downto 6) = "10" then
- EXT_REG_DATA_OUT <= REGISTERS_IN(regnum_STAT*c_REGIO_REG_WIDTH+31 downto regnum_STAT*c_REGIO_REG_WIDTH);
- elsif EXT_REG_ADDR_IN(7 downto 6) = "11" then
- EXT_REG_DATA_OUT <= buf_REGISTERS_OUT(regnum_CTRL*c_REGIO_REG_WIDTH+31 downto regnum_CTRL*c_REGIO_REG_WIDTH);
- elsif EXT_REG_ADDR_IN(5) = '0' then
- EXT_REG_DATA_OUT <= COMMON_STAT_REG_IN(regnum_cSTAT*c_REGIO_REG_WIDTH+31 downto regnum_cSTAT*c_REGIO_REG_WIDTH);
- else --if EXT_CTRL_ADDR_IN(5) = '1' then
- EXT_REG_DATA_OUT <= buf_COMMON_CTRL_REG_OUT(regnum_cCTRL*c_REGIO_REG_WIDTH+31 downto regnum_cCTRL*c_REGIO_REG_WIDTH);
- end if;
- end if;
- end process;
+-- ext_data_output : process(CLK)
+-- variable regnum_STAT : integer range 0 to 2**NUM_STAT_REGS-1;
+-- variable regnum_CTRL : integer range 0 to 2**NUM_CTRL_REGS-1;
+-- variable regnum_cSTAT : integer range 0 to std_COMSTATREG-1;
+-- variable regnum_cCTRL : integer range 0 to std_COMCTRLREG-1;
+-- begin
+-- regnum_STAT := conv_integer(EXT_REG_ADDR_IN(NUM_STAT_REGS-1 downto 0));
+-- regnum_CTRL := conv_integer(EXT_REG_ADDR_IN(NUM_CTRL_REGS-1 downto 0));
+-- regnum_cSTAT := conv_integer(EXT_REG_ADDR_IN(std_COMneededwidth-1 downto 0));
+-- regnum_cCTRL := conv_integer(EXT_REG_ADDR_IN(std_COMneededwidth-1 downto 0));
+-- if rising_edge(CLK) then
+-- if RESET = '1' then
+-- EXT_REG_DATA_OUT <= (others => '0');
+-- elsif EXT_REG_ADDR_IN(7 downto 6) = "01" then
+-- EXT_REG_DATA_OUT <= (others => '0');
+-- elsif EXT_REG_ADDR_IN(7 downto 6) = "10" then
+-- EXT_REG_DATA_OUT <= REGISTERS_IN(regnum_STAT*c_REGIO_REG_WIDTH+31 downto regnum_STAT*c_REGIO_REG_WIDTH);
+-- elsif EXT_REG_ADDR_IN(7 downto 6) = "11" then
+-- EXT_REG_DATA_OUT <= buf_REGISTERS_OUT(regnum_CTRL*c_REGIO_REG_WIDTH+31 downto regnum_CTRL*c_REGIO_REG_WIDTH);
+-- elsif EXT_REG_ADDR_IN(5) = '0' then
+-- EXT_REG_DATA_OUT <= COMMON_STAT_REG_IN(regnum_cSTAT*c_REGIO_REG_WIDTH+31 downto regnum_cSTAT*c_REGIO_REG_WIDTH);
+-- else --if EXT_CTRL_ADDR_IN(5) = '1' then
+-- EXT_REG_DATA_OUT <= buf_COMMON_CTRL_REG_OUT(regnum_cCTRL*c_REGIO_REG_WIDTH+31 downto regnum_cCTRL*c_REGIO_REG_WIDTH);
+-- end if;
+-- end if;
+-- end process;
process(CLK)
begin
--simple logic
constant c_YES : integer := 1;
constant c_NO : integer := 0;
+ constant c_MONITOR : integer := 2;
--standard values
constant c_F3_next : std_logic_vector(2 downto 0) := "010";
constant c_max_word_number : std_logic_vector(2 downto 0) := "100";
-
+ constant VERSION_NUMBER_TIME : std_logic_vector(31 downto 0) := conv_std_logic_vector(1234567890,32);
--function declarations
function and_all (arg : std_logic_vector)
PSCLK => '0',
RST => RESET,
CLK0 => CLK0_Out, -- for feedback
- CLKFX => CLKFX,
+ CLKFX180 => CLKFX,
LOCKED => LOCKED
);
U0_BUFG: BUFG
jspc29 / trbnet.git / commitdiff