Bugfix regarding Output MUX

diff --git a/cts/source/cts.vhd b/cts/source/cts.vhd
index 613a331d8c880942dda8036e100b641290b28648..43bc12d9e2cb786fb2487e3e1f84147a4361eda5 100755 (executable)
--- a/cts/source/cts.vhd
+++ b/cts/source/cts.vhd
@@ -691,7 +691,7 @@ begin
             eb_aggr_counter_i   <= x"00";
             eb_selection_i <= x"0";
          
-         elsif eb_mask_buf_i = x"00" or eb_regio_updated_i = '1'then
+         elsif eb_mask_buf_i = x"0000" or eb_regio_updated_i = '1'then
             -- we already unmasked all active ebs, so let's start over and again select all active ebs
             eb_mask_buf_i <= eb_mask_i;
             
@@ -703,7 +703,7 @@ begin
                -- we can switch to a sequential process instead of a parallel priority encoder
                eb_sel_loop: for i in 0 to 15 loop
                   if eb_mask_buf_i(i) = '1' then
-                     if OR_ALL(eb_mask_buf_i(15 downto i+1)) = '0' then
+                     if i=15 or OR_ALL(eb_mask_buf_i(15 downto i+1)) = '0' then
                         eb_mask_buf_i <= eb_mask_i;
                      else
                         eb_mask_buf_i(i downto 0) <= (others => '0');
@@ -1059,4 +1059,6 @@ begin
 
      STAT_DEBUG            => open
  );
+ 
+ cts_regio_no_more_data_out_i <= '0';
 end architecture;

diff --git a/cts/source/cts_trigger.vhd b/cts/source/cts_trigger.vhd
index a8aa9f5f545b70811ed07b14477acdbad7ee3aad..755457e872c335e85e48aabeb3202e8bbccc459f 100755 (executable)
--- a/cts/source/cts_trigger.vhd
+++ b/cts/source/cts_trigger.vhd
@@ -128,7 +128,6 @@ architecture RTL of CTS_TRIGGER is
    type   pulser_interval_t is array(MAX(0, TRIGGER_PULSER_COUNT - 1) downto 0) of std_logic_vector(31 downto 0);
    signal pulser_interval_i : pulser_interval_t;
    signal pulser_counter_i  : pulser_interval_t := (others => (others => '0'));
-   signal pulser_1us_i  : std_logic;
    
 -- Random Pulser
    type   rand_pulser_threshold_t is array(MAX(0, TRIGGER_RAND_PULSER - 1) downto 0) of std_logic_vector(31 downto 0);
@@ -147,7 +146,7 @@ architecture RTL of CTS_TRIGGER is
    
    type output_multiplexer_configs_t is array(MAX(0,OUTPUT_MULTIPLEXERS - 1) downto 0) of std_logic_vector(7 downto 0);
    signal output_multiplexer_configs_i : output_multiplexer_configs_t;
-   signal output_multiplexer_ins_i : std_logic_vector(16 + 2*TRIGGER_INPUT_COUNT + ADDON_LINE_COUNT + TRIGGER_ADDON_COUNT - 1 downto 0);
+   signal output_multiplexer_ins_i : std_logic_vector(16 + 2*TRIGGER_INPUT_COUNT + ADDON_LINE_COUNT + TRIGGER_ADDON_COUNT downto 0);
    
 -- Trigger Type Assoc 
    type trigger_type_assoc_t is array(0 to 15) of std_logic_vector(3 downto 0);
@@ -185,8 +184,7 @@ begin
       channels_i(ITC_BASE_EXT) <= EXT_TRIGGER_IN;
    end generate;
    
-   proc_output_mux_ins: process(channels_i, TRIGGERS_IN, ADDON_TRIGGERS_IN, trigger_inputs_i, 
-     output_multiplexer_configs_i) is
+   proc_output_mux_ins: process (channels_i, TRIGGERS_IN, ADDON_TRIGGERS_IN, trigger_inputs_i, output_multiplexer_configs_i, CLK_IN) is
       variable i : integer := 0;
    begin
       i := 0;
@@ -206,18 +204,21 @@ begin
       
       output_multiplexer_ins_i(trigger_inputs_i'high + i downto i) <= trigger_inputs_i;
       i := i + EFFECTIVE_INPUT_COUNT;
+      
+      output_multiplexer_ins_i(i) <= CLK_IN;
+      i := i + 1;
    end process;
    
-   proc_out_mux: process(output_multiplexer_ins_i, output_multiplexer_configs_i) is
+   proc_out_mux: process (output_multiplexer_ins_i, output_multiplexer_configs_i) is
       variable tmp : integer range 0 to 255 := 0;
       variable idx : integer range 0 to output_multiplexer_ins_i'high := 0;
       variable test : std_logic_vector(31 downto 0);
    begin
       for j in 0 to output_multiplexers - 1 loop
-          output_multiplexers_out(j) <= test(to_integer( unsigned( output_multiplexer_configs_i(j)))); --output_multiplexer_ins_i(idx);
+          output_multiplexers_out(j) <= output_multiplexer_ins_i(to_integer( unsigned( output_multiplexer_configs_i(j))));
       end loop;   
    end process;
-         
+   
    gen_trigger_inputs: for i in 0 to EFFECTIVE_INPUT_COUNT-1 generate
       my_trigger_input: CTS_TRG_INPUT port map (
          CLK_IN => CLK_IN,

diff --git a/cts/trb3_central.vhd b/cts/trb3_central.vhd
index daf15785f28b0cd36853b1ac16ba5c71e443cf05..30c98eb9a52baa2e1ca277dff44a7f6a43c430c7 100644 (file)
--- a/cts/trb3_central.vhd
+++ b/cts/trb3_central.vhd
@@ -599,6 +599,7 @@ begin
    JOUT1    <= cts_output_multiplexers_i(3 downto 0);
    JOUT2    <= cts_output_multiplexers_i(7 downto 4);
    JOUTLVDS <= cts_output_multiplexers_i(7 downto 0);
+   --LED_BANK <= cts_output_multiplexers_i(7 downto 0);
    
 ---------------------------------------------------------------------------
 -- Reset Generation
@@ -1450,9 +1451,9 @@ end process;
 ---------------------------------------------------------------------------
     PWM_OUT                        <= "00";
     
-    JOUT1                          <= x"0";
-    JOUT2                          <= x"0";
-    JOUTLVDS                       <= x"00";
+--  JOUT1                          <= x"0";
+--  JOUT2                          <= x"0";
+--  JOUTLVDS                       <= x"00";
     JTTL                           <= x"0000";
     
     LED_BANK(5 downto 0)           <= (others => '0');