signal rx_komma_sync : std_logic_vector(3 downto 0);
-- fifo signals
+ signal fifo_enable_i : std_logic_vector(3 downto 0) := (others => '0');
signal fifo_data_ii : std_logic_vector(c_links*c_mupixhitsize - 1 downto 0);
signal fifo_wren_i : std_logic_vector(c_links - 1 downto 0) := (others => '0');
constant fifo_depth : integer := 11; -- fifo depth (change when regenerating FIFO IP core)
signal komma_counter : t_vector32_array(0 to 3) := (others => (others => '0'));
-- unpacker signals
- signal unpacker_valid_i : std_logic_vector(c_links - 1 downto 0) := (others => '0');
+ signal unpacker_valid_i : std_logic_vector(c_links - 1 downto 0) := (others => '0');
+ signal unpacker_hit_en_i : std_logic_vector(3 downto 0);
-- slow control resets
signal reset_counters_i : std_logic := '0';
komma => rx_komma_sync(j),
valid => unpacker_valid_i(j),
hit_out => fifo_data_ii((j + 1)*c_mupixhitsize - 1 downto j*c_mupixhitsize),
- hit_enable => fifo_wren_i(j),
+ hit_enable => unpacker_hit_en_i(j),
link_flag => open,
errorcounter_gray => unpacker_error_counter(j),
errorcounter => open);
end generate generate_unpacker;
+ fifo_wren_i <= unpacker_hit_en_i and fifo_enable_i;
generate_fifo : for j in 0 to c_links - 1 generate
fifo : entity work.serdes_fifo
port map (
slv_no_more_data_out <= '0';
slv_unknown_addr_out <= '0';
serdes_channel_select <= 0;
+ fifo_enable_i <= (others => '0');
else
slv_data_out <= (others => '0');
slv_ack_out <= '0';
when x"0163" =>
slv_ack_out <= '1';
serdes_channel_select <= to_integer(unsigned(slv_data_in(1 downto 0)));
+ when x"016c" =>
+ fifo_enable_i <= slv_data_in(3 downto 0);
+ slv_ack_out <= '1';
when others =>
slv_unknown_addr_out <= '1';
end case;