STAT_RESET(15 downto 10) <= (others => '0');
STAT_RESET(16) <= RX_CDR_LOL;
STAT_RESET(17) <= RX_LOS;
-STAT_RESET(18) <= RX_PCS_RST;
+STAT_RESET(18) <= '0'; --RX_PCS_RST;
STAT_RESET(19) <= '0';
STAT_RESET(31 downto 20) <= start_timer(start_timer'left downto start_timer'left - 11);
DEBUG_OUT(0) <= tx_allow;
DEBUG_OUT(1) <= rx_allow;
DEBUG_OUT(2) <= sd_los_i;
-DEBUG_OUT(3) <= DEBUG_RX_CONTROL(4);
+DEBUG_OUT(3) <= '0'; --DEBUG_RX_CONTROL(4);
end architecture;
-- STAT_REG_OUT(7 downto 0) <= std_logic_vector(ram_fill_level);
STAT_REG_OUT(3 downto 0) <= state_bits;
- STAT_REG_OUT(7) <= TX_K_OUT;
- STAT_REG_OUT(15 downto 8) <= TX_DATA_OUT;
--- STAT_REG_OUT(15 downto 8) <= std_logic_vector(ram_read_addr);
+-- STAT_REG_OUT(7) <= TX_K_OUT;
+-- STAT_REG_OUT(15 downto 8) <= TX_DATA_OUT;
+ STAT_REG_OUT(15 downto 8) <= std_logic_vector(ram_read_addr);
-- STAT_REG_OUT(16) <= ram_afull;
STAT_REG_OUT(17) <= ram_empty;
STAT_REG_OUT(18) <= tx_allow_qtx;
CLK_RX_HALF_OUT : out std_logic;
CLK_RX_FULL_OUT : out std_logic;
--SFP Connection
- SD_RXD_P_IN : in std_logic;
- SD_RXD_N_IN : in std_logic;
- SD_TXD_P_OUT : out std_logic;
- SD_TXD_N_OUT : out std_logic;
+-- SD_RXD_P_IN : in std_logic;
+-- SD_RXD_N_IN : in std_logic;
+-- SD_TXD_P_OUT : out std_logic;
+-- SD_TXD_N_OUT : out std_logic;
SD_REFCLK_P_IN : in std_logic := '0';
SD_REFCLK_N_IN : in std_logic := '0';
SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
attribute syn_keep of reset_i : signal is true;
attribute syn_preserve of reset_i : signal is true;
+signal hdinp, hdinn, hdoutp, hdoutn : std_logic;
+attribute nopad : string;
+attribute nopad of hdinp, hdinn, hdoutp, hdoutn : signal is "true";
+
+
begin
gen_serdes_0_200_ctc : if SERDES_NUM = 0 and EXT_CLOCK = c_NO and USE_200_MHZ = c_YES and USE_CTC = c_YES generate
THE_SERDES: sfp_0_200_ctc
port map(
- HDINP_CH0 => sd_rxd_p_in,
- HDINN_CH0 => sd_rxd_n_in,
- HDOUTP_CH0 => sd_txd_p_out,
- HDOUTN_CH0 => sd_txd_n_out,
+ HDINP_CH0 => hdinp,
+ HDINN_CH0 => hdinn,
+ HDOUTP_CH0 => hdoutp,
+ HDOUTN_CH0 => hdoutn,
RXICLK_CH0 => clk_rx,
TXICLK_CH0 => clk_tx,
gen_serdes_0_200 : if SERDES_NUM = 0 and EXT_CLOCK = c_NO and USE_200_MHZ = c_YES and USE_CTC = c_NO generate
THE_SERDES: sfp_0_200_int
port map(
- HDINP_CH0 => sd_rxd_p_in,
- HDINN_CH0 => sd_rxd_n_in,
- HDOUTP_CH0 => sd_txd_p_out,
- HDOUTN_CH0 => sd_txd_n_out,
+ HDINP_CH0 => hdinp,
+ HDINN_CH0 => hdinn,
+ HDOUTP_CH0 => hdoutp,
+ HDOUTN_CH0 => hdoutn,
RXICLK_CH0 => clk_rx,
TXICLK_CH0 => clk_tx,
gen_serdes_1_200 : if SERDES_NUM = 1 and EXT_CLOCK = c_NO and USE_200_MHZ = c_YES and USE_CTC = c_NO generate
THE_SERDES: sfp_1_200_int
port map(
- HDINP_CH1 => sd_rxd_p_in,
- HDINN_CH1 => sd_rxd_n_in,
- HDOUTP_CH1 => sd_txd_p_out,
- HDOUTN_CH1 => sd_txd_n_out,
+ HDINP_CH1 => hdinp,
+ HDINN_CH1 => hdinn,
+ HDOUTP_CH1 => hdoutp,
+ HDOUTN_CH1 => hdoutn,
RXICLK_CH1 => clk_rx,
TXICLK_CH1 => clk_tx,
gen_serdes_1_125 : if SERDES_NUM = 1 and EXT_CLOCK = c_NO and USE_125_MHZ = c_YES and USE_CTC = c_NO generate
THE_SERDES: sfp_1_125_int
port map(
- HDINP_CH1 => sd_rxd_p_in,
- HDINN_CH1 => sd_rxd_n_in,
- HDOUTP_CH1 => sd_txd_p_out,
- HDOUTN_CH1 => sd_txd_n_out,
+ HDINP_CH1 => hdinp,
+ HDINN_CH1 => hdinn,
+ HDOUTP_CH1 => hdoutp,
+ HDOUTN_CH1 => hdoutn,
RXICLK_CH1 => clk_rx,
TXICLK_CH1 => clk_tx,
--stat_debug(59 downto 43) <= (others => '0');
--stat_debug(63 downto 60) <= link_error(3 downto 0);
-end architecture;
\ No newline at end of file
+end architecture;