%\subsection{Memory Map}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-Register addresses from 0xA000 to 0xA0ef is SCM FPGA (1)
-Register addresses from 0xA0f0 to 0xA0ff is ECP2M FPGA (2)
-Register addresses from 0xA100 to 0xA100 + 26*500 which is number of samples per beam structure, the histograms are created in the SCM FPGA (1) see fig. \ref{ctsbeam}. First 8 is START next 8 is also START but perpendicularstripes. Next 8 is Veto and for the last two the source is selected by 0xA0C2 register.
+Register addresses from 0xA000 to 0xA0ef is SCM FPGA (1) \nw
+Register addresses from 0xA0f0 to 0xA0ff is ECP2M FPGA (2) \nw
+Register addresses from 0xA100 to 0xA100 + 26*500 (500 is number of samples per beam structure), the histograms are created in the SCM FPGA (1) see fig. \ref{ctsbeam}. First 8 is START next 8 is also START but perpendicular stripes. Next 8 is Veto and for the last two the source is selected by 0xA0C2 register.
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{CTS Control Registers}
\begin{description}
\item [0xA0C0] LVL1 trigger settings:
\begin{description}
- \item[Bit 4 -- 0] If bit 4 = 0 then standard trigger selection, else trigger code = bits 3 down to 0
+ \item[Bit 4 -- 0] If bit 4 = 0 then standard trigger selection, else trigger type = bits 3 down to 0
\item[Bit 5] MDC calibration trigger enable - send each second
\item[Bit 6] Force update Shower pedestals trigger (write 1..0)
\item[Bit 7] Disable Shower pedestals update (update is generated once during each spill off)
\item[Bit 8] Enable Shower calibration trigger
- \item[Bit 9] Enable test trigger 0xE which is send each second
+ \item[Bit 9] Enable test trigger 0xE, which is sent each second
\item[Bit 10] Disable all triggers
- \item[Bit 14] Enable beam inhibit for generation of Shower trigger - look into beam inhibit signal settings register 0xA0DD
+ \item[Bit 14] Enable beam inhibit for generation of Shower trigger - look into beam inhibit signal settings register 0xA0D9
\item[Bit 15] Enable beam inhibit to make system silent when there is no beam (only cal trigger are accepted) - look into beam inhibit signal settings register 0xA0DD
- \item[Bit 16] Enable TOF/RPC multiplicity signnals to be treated as a Start signal see Fig.\ref{cts_logic}
- \item[Bit 23 -- 20] Set width for VETO signal used for anti cincoincidence logic - $value * 1.25\,ns$
- \item[Bit 28] Select source for beam structure A - 0 Start, 1 RPC/TOF
- \item[Bit 29] Select source for beam structure B - 0 Start, 1 RPC/TOF
+ \item[Bit 16] Enable TOF/RPC multiplicity signals to be treated as a Start signal see Fig.\ref{cts_logic}
+ \item[Bit 23 -- 20] Set width for VETO signal used for anti coincidence logic - $value * 1.25\,ns$
+ \item[Bit 28 -- 29] not used
\item[Bit 30] When set to '1' it generates RICH special APV trigger (double pulse on RICH connector) - edge sensitive 0 -> 1
\item[Bit 31] Enable trigger line test, this works together with self trigger pulser (set the required frequency)
\end{description}
\item [0xA0C1] LVL1/LVL2 trigger settings:
\begin{description}
- \item[Bit 16 -- 12] Delay (from the fastes trigger) of MDCB (MDC 3/4) trigger = value * 20 ns
+ \item[Bit 16 -- 12] Delay of MDCB (MDC 3/4) trigger = value * 20 ns
\item[Bit 21 -- 17] Delay of MDCA (MDC 1/2) trigger = value * 20 ns
\item[Bit 31 -- 28] LVL1 trigger width, when value < 7 then width = 105 + Value*5 ns else width = Value*5ns
\end{description}
\item [0xA0C2] Multiplexers output select - this output is also used for histograms (24th histogram - counting from 0) :
\begin{description}
- \item[Bit 7 -- 0] Selects the output signal for LVDS OUT(4) (the order like on the fig.\ref{cts_logic}) to see internal FPGA signals after diferent stages of signal processing
+ \item[Bit 7 -- 0] Selects the output signal for LVDS OUT(4) (the order like on the fig.\ref{cts_logic}) to see internal FPGA signals after different stages of signal processing
\begin{description}
\item 7 - 0, After one clock Start 7 - 0 (first address 0x0)
\item 15 - 8 After one clock Veto 7 - 0 (0x8)
\item 57 - 52 After delay TOF 6 - 1 (0x34)
\item 63 - 58 After delay RPC 6 - 1 (0x3A)
\item 71 - 64 After delay PT 8 - 1 (0x40)
- \item 80 - 72 Multiplicity 2 opposite sectors, 3 no neighbour, 2 no neighbour, 6, 5, 4, ..1 (0x48)
+ \item 80 - 72 Multiplicity 2 opposite sectors, 3 no neighbor, 2 no neighbor, 6, 5, 4, ..1 (0x48)
\item 87 - 81 Empty
\item 93 - 88 TOF sectors after width (0x58)
\item 99 - 94 RPC sectors after width (0x5E)
\item 107 - 100 PT signals after width (0x64)
\item 126 - 108 not used (reserved for output) (0x6C)
\item 127 - start signal used for anti coincidence (0x7F)
- \item 128 - veto signal (after setting witdh 0xA0C0(23 -- 20)) used for anti coincidence (0x80)
+ \item 128 - veto signal (after setting width 0xA0C0(23 -- 20)) used for anti coincidence (0x80)
\item 129 - anti coincidence signal (0x81)
\item 255 - 130 not used
\end{description}
\item[Bit 31 -- 28] Data version set into the data stream from the CTS (see a CTS data structure chapter)
\end{description}
\item [0xA0C4 -- 0xA0C3] Enable CTS trigger inputs (order as on the Fig.\ref{cts_logic})
- \item [0xA0C5] TS gating disable
- \item [0xA0C6] Global time offset for all signals used for beam structure
+ \item [0xA0C5] Anticoincidence gating disable
+ \item [0xA0C6] Global time offset for all signals used for histograms see fig.\ref{ctsbeam}
\item [0xA0C7] Enable trigger outputs
\item [0xA0C8] Sample period for signals being histogrammed - $value*100ns$. See fig. \ref{ctsbeam}
\item [0xA0D0 -- 0xA0C9] Registers for downscaling incoming signals, only $2^{value}$ is passing.
- \item [0xA0D8 -- 0xA0D1] Registers for making a delay of the signal - $value * 1,25\,ns$
- \item [0xA0D9] -- Length of the beam itself after this time the beam inhibit signal is set till next START BEAM signal - $value*100ns$
+ \item [0xA0D6 -- 0xA0D1] Registers for making a delay of the signal - $value * 1,25\,ns$
+ \item [0xA0D8 -- 0xA0D7] not used
+ \item [0xA0D9] -- Length of the beam itself. After this time the beam inhibit signal is set till next START BEAM signal - $value*100ns$
\item [0xA0DA] -- use different parts of the START detector for histograms
\begin{description}
\item [Bit 1 -- 0] when '00' inputs 7 - 0 from the Start detector are used, '01' 11 - 4, '10' 15 - 8
% \item[Bit 23 -- 16] Threshold for the rate detection in $1\,us$ time, when number of hits equals the threshold (or more) the per 1sec marker is set
% \item[Bit 31 -- 24] Threshold for the rate detection in $100\,ns$ time, when number of hits equals the threshold (or more) the per 1sec marker is set
- \item [0xA0F0] LVL2 EB IP table and downscale factor for removing not needed data
+ \item [0xA0F0] LVL2 EB selection table and downscale factor for removing not needed data
\begin{description}
\item[Bit 15 -- 0] When writing to this register EB is chosen to be a receiver e.g. : 0x8103 then EB15,EB8,EB1 and EB0 is selected
\item[Bit 31 -- 16] When 0 all headers and trailers from TRB TDCs are transported , when different then the value is downscaling factor (counted per event) for transporting headers and trailers (bit 17 of the LVL1 trigger information).
\item[Bit 15 -- 0] LVL1 trigger number
\item[Bit 16] trigger buffer FIFO full
\item[Bit 17] trigger buffer FIFO empty
- \item[Bit 18] event rate bit 13
- \item[Bit 19] event rate bit 15
+ \item[Bit 18] accepted event rate bit 13
+ \item[Bit 19] accepted event rate bit 15
\item[Bit 20] LVL1 trigger buffer busy
\item[Bit 21] LVL1 TrbNet busy
\item[Bit 22] LVL1 local busy
\item[0x4] Data sending
\item[0x5] Data finished send
\end{description}
- \item[Bit 4] Beam inhibit signal created on base of START BEAM signal and register settings (0xA0DD)
+ \item[Bit 4] Beam inhibit signal created on base of START BEAM signal and register settings (0xA0D9)
\item[Bit 8 -- 5] PT 8 -- 5 polarity, if '1' then the polarity is not OK (expecting signals which most of the time are logically '0')
\end{description}
\item[0xA003: Polarity information]
\begin{description}
- \item[Bit 31 -- 0] Polarity of input signals in order which corresponds to the Fig.\ref{cts_logic} (Start1, Start2, Start3,...Veto1,... ). If it is set to '1' then the polarity is not OK (expecting signals which most of the time are logically '0'). The polarity check is done already after inversion of signals in the FPGA (inverted polarities physically on the CTS trigger input)
+ \item[Bit 31 -- 0] Polarity of input signals in order which corresponds to the Fig.\ref{cts_logic} (Start1, Start2, Start3,...Veto1,... ). If it is set to '1' then the polarity is not OK (expecting signals which most of the time are logically '0'). The polarity check is done already after inversion of signals in the FPGA. Inverted polarities also are inverted on the CTS trigger input already from the detector FEE.
\end{description}
\item[0xA004 : CTS readout to TrbNet]
\end{description}
\item[0xA005: CTS readout information] Busy flags and current trigger number and type on LVL1 channel
\begin{description}
- \item[Bit 13 -- 0] Data word counter
- \item[Bit 29 -- 16] Header word counter
+ \item[Bit 13 -- 0] Data from the CTS word counter
+ \item[Bit 29 -- 16] Header from the CTS word counter
\end{description}
\item[0xA006: CTS readout information]
\item[Bit 31 -- 24] counter how many times second state machine finished
\end{description}
- \item[0xA007: R/W registers debug information]
+ \item[0xA007: R/W registers debug information. Only used when r/w interface to the Etrax FS is activated]
\begin{description}
\item[Bit 15 -- 0] saved data for the registers
\item[Bit 23 -- 16] saved address for the registers
\item[15 -- 0] LVL2 trigger number
\item[19 -- 16] LVL2 trigger buffer counter 3 -- 0
\item[29--20] LVL1 triggers number -- lvl2 triggers number
- \item[30] LVL2 -> LVL1 back pressure busy (when LVL2 trigger FIFO goes almost full)
+ \item[30] LVL2 -> LVL1 back pressure busy, when LVL2 trigger FIFO goes almost full. This due to the fact that each LVL1 request automatically creates LVL2.
\item[31] Locally created LVL2 busy based on IPU TRBnet busy
\end{description}
\item[0xA0F9] -- LVL1 information sent back from the endpoints
\begin{description}
\item[0] There is a LVL1 busy based on LVL1 information sent back from the endpoints
\end{description}
- \item[0xA131 - 0xA100] - beam structure A
- \item[0xA163 - 0xA132] - beam structure B
- \item[0xA195 - 0xA164] - beam structure B
- \item[0xA1C7 - 0xA195] - Start structure input 1
- \item[0xA1F9 - 0xA1C8] - Start structure input 2
- \item[0xA22B - 0xA1FA] - Start structure input 3
- \item[0xA25D - 0xA22C] - Start structure input 4
- \item[0xA28F - 0xA25E] - Start structure input 5
- \item[0xA2C1 - 0xA290] - Start structure input 6
- \item[0xA2F3 - 0xA2C2] - Start structure input 7
-
+ \item [0xA100 - 0xA100 + 26*500] The memory reserved for the histograms. 500 is number of samples per each histogram. The histograms are created in the SCM FPGA (1) see fig. \ref{ctsbeam}. First 8 is START (first connector) next 8 is also START but perpendicular stripes (second connector). Next 8 is Veto and for the last two the source is selected by 0xA0C2 register.
\end{description}
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