some debug additions to uart

diff --git a/special/uart.vhd b/special/uart.vhd
index 5c33cbfcb4682da2069e8503b0ca426c88073a21..8acbc6316e11d1706597ca98914680f08e40a5a6 100644 (file)
--- a/special/uart.vhd
+++ b/special/uart.vhd
@@ -17,8 +17,8 @@ entity uart is
   port(
     CLK     : in  std_logic;
     RESET   : in  std_logic;
-    UART_RX : in  std_logic_vector(0 to OUTPUTS-1);
-    UART_TX : out std_logic_vector(0 to OUTPUTS-1);
+    UART_RX : in  std_logic_vector(OUTPUTS-1 downto 0);
+    UART_TX : out std_logic_vector(OUTPUTS-1 downto 0);
     
     BUS_RX  : in CTRLBUS_RX;
     BUS_TX  : out CTRLBUS_TX
@@ -32,7 +32,7 @@ signal rx_data   : std_logic_vector(7 downto 0);
 signal rx_ready  : std_logic;
 signal tx_send   : std_logic;
 signal tx_ready  : std_logic;
-signal out_sel   : integer range 0 to 15 := 0;
+signal out_sel   : integer range 0 to OUTPUTS-1 := 0;
 signal uart_sel_rx : std_logic;
 signal uart_sel_tx : std_logic;
 
@@ -51,6 +51,9 @@ signal tx_fifo_write : std_logic;
 signal next2_tx_send, next_tx_send : std_logic;
 signal last2_rx_read, last_rx_read : std_logic;
 
+signal rx_debug : std_logic_vector(3 downto 0);
+signal tx_debug : std_logic_vector(3 downto 0);
+
 begin
 
 
@@ -61,7 +64,8 @@ THE_RX : entity work.uart_rec
     RST          => RESET,
     RX           => uart_sel_rx,
     DATA_OUT     => rx_data,
-    DATA_WAITING => rx_ready
+    DATA_WAITING => rx_ready,
+    DEBUG        => rx_debug
     );
 
 THE_TX : entity work.uart_trans
@@ -72,7 +76,8 @@ THE_TX : entity work.uart_trans
     DATA_IN      => tx_fifo_out(7 downto 0),
     SEND         => tx_send,
     READY        => tx_ready,
-    TX           => uart_sel_tx
+    TX           => uart_sel_tx,
+    DEBUG        => tx_debug
     );
 
     
@@ -140,6 +145,19 @@ PROC_REGS : process begin
       BUS_TX.ack  <= '1';
     elsif BUS_RX.addr(3 downto 0) = x"2" then
       BUS_TX.data(3 downto 0) <= std_logic_vector(to_unsigned(out_sel,4));
+      BUS_TX.ack  <= '1';
+    elsif BUS_RX.addr(3 downto 0) = x"3" then  
+      BUS_TX.data(0) <= rx_fifo_full;
+      BUS_TX.data(1) <= rx_fifo_empty;
+      BUS_TX.data(2) <= tx_fifo_full;
+      BUS_TX.data(3) <= tx_fifo_empty;
+      BUS_TX.data(7 downto 4)  <= rx_debug;
+      BUS_TX.data(11 downto 8) <= tx_debug;
+      BUS_TX.data(12) <= next_tx_send;
+      BUS_TX.data(13) <= tx_fifo_read;
+      BUS_TX.data(14) <= uart_sel_tx;
+      BUS_TX.data(15) <= uart_sel_rx;
+      
       BUS_TX.ack  <= '1';
     else
       BUS_TX.unknown <= '1';

diff --git a/special/uart_rec.vhd b/special/uart_rec.vhd
index 5edbaf06d05ea543ca19d98c4743efa3210fceb1..3d2ab2d363c5bc9961bfd4d70a7406563b9e75bc 100644 (file)
--- a/special/uart_rec.vhd
+++ b/special/uart_rec.vhd
@@ -73,7 +73,7 @@ DEBUG(3) <= '0';
   clock_division : process begin
     wait until rising_edge(CLK);
     -- scaling down the main clock to the desired baudrate
-    if clk_div_counter = CLK_DIV-1 then
+    if clk_div_counter = to_unsigned(CLK_DIV,16)-1 then
       clk_div_counter <= x"0000";
     else
       clk_div_counter <= clk_div_counter + 1;
@@ -82,7 +82,7 @@ DEBUG(3) <= '0';
     -- in contrast to the transceiver module, the symbol pulse is generated in the middle of the
     -- symbol period
     --  if clk_div_counter = '0' & CLK_DIV(15 downto 1) then  -- CLK_DIV/2 by >> (right shifting)
-    if clk_div_counter = CLK_DIV/2 then 
+    if clk_div_counter =  to_unsigned(CLK_DIV/2,16) then 
       symbol_pulse <= '1';
     else 
       symbol_pulse <= '0';

diff --git a/special/uart_trans.vhd b/special/uart_trans.vhd
index 8ea2c0d6129df2a1aef84974316c1edc96733702..3b5f3ab8b21b08856e9d595fc3804baea40cd3b0 100644 (file)
--- a/special/uart_trans.vhd
+++ b/special/uart_trans.vhd
@@ -78,7 +78,7 @@ DEBUG(3) <= '0';
   clock_division : process begin
     wait until rising_edge(CLK);
     -- scaling down the main clock to the desired baudrate
-    if clk_div_counter = CLK_DIV-1 then
+    if clk_div_counter = to_unsigned(CLK_DIV,16)-1 then
       clk_div_counter <= x"0000";
     else
       clk_div_counter <= clk_div_counter + 1;