THE_CLK_OUT : ddr_off
port map(
Clk => CLK,
- Data(0) => DATA_CLK_OUT_PHASE,
- Data(1) => not DATA_CLK_OUT_PHASE,
+ Data(0) => not DATA_CLK_OUT_PHASE,
+ Data(1) => DATA_CLK_OUT_PHASE,
Q(0) => DATA_CLK_OUT
);
STAT_DEBUG(6) <= buf_MED_READ_OUT;
STAT_DEBUG(7) <= resync_received;
STAT_DEBUG(15 downto 8) <= reg_DATA_IN(7 downto 0);
- STAT_DEBUG(31 downto 16) <= buf_DATA_OUT;
+ STAT_DEBUG(18 downto 16) <= state_bits;
+ STAT_DEBUG(31 downto 19) <= buf_DATA_OUT(12 downto 0);
STAT_DEBUG(63 downto 32) <= (others => '0');