include sctrl bus into hub in CTS for fpgasettings and debug uart

diff --git a/cts/config_compile_frankfurt.pl b/cts/config_compile_frankfurt.pl
index 24aac7c9a7adff6b1f779bf5c83c38c14bf9c278..c16d10fb4de903511a569d046f1ec834628bad8a 100644 (file)
--- a/cts/config_compile_frankfurt.pl
+++ b/cts/config_compile_frankfurt.pl
@@ -2,7 +2,7 @@ TOPNAME                      => "trb3sc_cts",
 lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de";
 lm_license_file_for_par      => "1702\@hadeb05.gsi.de",
 lattice_path                 => '/d/jspc29/lattice/diamond/3.12',
-synplify_path                => '/d/jspc29/lattice/synplify/S-2021.09-SP2',
+synplify_path                => '/d/jspc29/lattice/synplify/T-2022.09-SP2',
 #synplify_command             => "/d/jspc29/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options",
 #synplify_command             => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp",
 

diff --git a/cts/trb3sc_cts.vhd b/cts/trb3sc_cts.vhd
index 6c546e2317210597ff190a565a49996b53915862..124d62a4be20899221fa2715880b8d13d1d6938d 100644 (file)
--- a/cts/trb3sc_cts.vhd
+++ b/cts/trb3sc_cts.vhd
@@ -133,7 +133,7 @@ architecture trb3sc_arch of trb3sc_cts is
   signal int2med           : int2med_array_t(0 to INTERFACE_NUM-1);
   
   signal ctrlbus_rx, bussci1_rx, bussci2_rx, bussci3_rx, bustools_rx, buscts_rx, busr3b_rx,
-         bustc_rx, busgbeip_rx, busgbereg_rx, bus_master_out, handlerbus_rx, bustdc_rx  : CTRLBUS_RX;
+         bustc_rx, busgbeip_rx, busgbereg_rx, bus_master_out, bustdc_rx  : CTRLBUS_RX;
   signal ctrlbus_tx, bussci1_tx, bussci2_tx, bussci3_tx, bustools_tx, buscts_tx, busr3b_tx,
          bustc_tx, busgbeip_tx, busgbereg_tx, bus_master_in, bustdc_tx : CTRLBUS_TX;
   
@@ -280,8 +280,7 @@ THE_CLOCK_RESET :  entity work.clock_reset_handler
     if(reset_via_gbe = '1') then
       reset_via_gbe_long <= '1';
       reset_via_gbe_timer <= '1';
-    end if;
-    if timer.tick_us = '1' then
+    elsif timer.tick_us = '1' then  --BUG else!
       reset_via_gbe_timer <= '0';
       reset_via_gbe_long  <= reset_via_gbe_timer;
     end if;
@@ -795,6 +794,9 @@ end generate;
       ONEWIRE_MONITOR_IN  => open,
       MY_ADDRESS_OUT      => timer.network_address,
       UNIQUE_ID_OUT       => timer.uid,
+      BUS_MASTER_IN             => bus_master_in,
+      BUS_MASTER_OUT            => bus_master_out,
+      BUS_MASTER_ACTIVE         => bus_master_active,      
       TIMER_TICKS_OUT(0)  => timer.tick_us,
       TIMER_TICKS_OUT(1)  => timer.tick_ms,
       TEMPERATURE_OUT     => timer.temperature,
@@ -1063,7 +1065,7 @@ end generate;
       CLK   => clk_sys,
       RESET => reset_i,
 
-      REGIO_RX  => handlerbus_rx,
+      REGIO_RX  => ctrlbus_rx,
       REGIO_TX  => ctrlbus_tx,
       
       BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED
@@ -1089,7 +1091,7 @@ end generate;
       STAT_DEBUG => open
       );
 
-  handlerbus_rx <= ctrlbus_rx when bus_master_active = '0' else bus_master_out;         
+  --handlerbus_rx <= ctrlbus_rx when bus_master_active = '0' else bus_master_out;         
       
 ---------------------------------------------------------------------------
 -- Control Tools
@@ -1130,7 +1132,7 @@ end generate;
       BUS_RX     => bustools_rx,
       BUS_TX     => bustools_tx,
       --Control master for default settings
-      BUS_MASTER_IN  => ctrlbus_tx,
+      BUS_MASTER_IN  => bus_master_in,
       BUS_MASTER_OUT => bus_master_out,
       BUS_MASTER_ACTIVE => bus_master_active,        
       DEBUG_OUT  => open