when x"08" => stored_src_mac(31 downto 24) <= MAC_RXD_IN;\r
when x"09" => stored_src_mac(39 downto 32) <= MAC_RXD_IN;\r
when x"0a" => stored_src_mac(47 downto 40) <= MAC_RXD_IN;\r
- when x"0b" => stored_ethertype(15 downto 8) <= MAC_RXD_IN;\r
- when x"0c" => stored_ethertype(7 downto 0) <= MAC_RXD_IN;\r
+ when x"0b" => stored_ethertype(7 downto 0) <= MAC_RXD_IN;\r
+ when x"0c" => stored_ethertype(15 downto 8) <= MAC_RXD_IN;\r
when x"0d" => stored_version <= MAC_RXD_IN;\r
when x"16" => stored_protocol <= MAC_RXD_IN;\r
when x"19" => stored_src_ip(7 downto 0) <= MAC_RXD_IN;\r
when x"1e" => stored_dst_ip(15 downto 8) <= MAC_RXD_IN;\r
when x"1f" => stored_dst_ip(23 downto 16) <= MAC_RXD_IN;\r
when x"20" => stored_dst_ip(31 downto 24) <= MAC_RXD_IN;\r
- when x"21" => stored_src_port(15 downto 8) <= MAC_RXD_IN;\r
- when x"22" => stored_src_port(7 downto 0) <= MAC_RXD_IN;\r
- when x"23" => stored_dst_port(15 downto 8) <= MAC_RXD_IN;\r
- when x"24" => stored_dst_port(7 downto 0) <= MAC_RXD_IN;\r
+ when x"21" => stored_src_port(7 downto 0) <= MAC_RXD_IN;\r
+ when x"22" => stored_src_port(15 downto 8) <= MAC_RXD_IN;\r
+ when x"23" => stored_dst_port(7 downto 0) <= MAC_RXD_IN;\r
+ when x"24" => stored_dst_port(15 downto 8) <= MAC_RXD_IN;\r
when others => null;\r
end case;\r
end if;\r
-- checks to filter frames, and distribute them to the correct handlers\r
is_my_mac_x <= '1' when (stored_dst_mac = MY_MAC_IN) else '0';\r
is_broadcast_x <= '1' when (stored_dst_mac = x"ffffffffffff") else '0';\r
- is_arp_x <= '1' when (stored_ethertype = x"0806") else '0';\r
- is_ipv4_x <= '1' when (stored_ethertype = x"0800") else '0';\r
+ is_arp_x <= '1' when (stored_ethertype = x"0608") else '0'; -- bytes mirrored\r
+ is_ipv4_x <= '1' when (stored_ethertype = x"0008") else '0'; -- bytes mirrored\r
is_version_x <= '1' when (stored_version = x"45") else '0';\r
is_udp_x <= '1' when (stored_protocol = x"11") else '0';\r
is_icmp_x <= '1' when (stored_protocol = x"01") else '0';\r
- is_dhcp_x <= '1' when (stored_dst_port = x"0044") else '0';\r
- is_sctrl_x <= '1' when (stored_dst_port = x"6590") else '0';\r
- is_discovery_x <= '1' when (stored_dst_port = x"d903") else '0';\r
+ is_dhcp_x <= '1' when (stored_dst_port = x"4400") else '0'; -- bytes mirrored\r
+ is_sctrl_x <= '1' when (stored_dst_port = x"9065") else '0'; -- bytes mirrored\r
+ is_discovery_x <= '1' when (stored_dst_port = x"03d9") else '0'; -- bytes mirrored\r
is_my_ip_x <= '1' when (stored_dst_ip = MY_IP_IN) else '0';\r
is_broadcast_ip_x <= '1' when (stored_dst_ip = x"ffffffff") else '0';\r
is_empty_payload_x <= '1' when (rx_bytes_ctr = 0) else '0';\r
if( rising_edge(CLK) ) then\r
if ( select_current_state = IDLE ) then\r
index <= 0;\r
- elsif( select_current_state = LOOP_OVER and resp_ready(index) = '0' ) then\r
+ elsif( (select_current_state = LOOP_OVER) and (resp_ready(index) = '0') ) then\r
index <= index + 1;\r
end if;\r
end if;\r
PROC_SELECTOR: process( CLK )\r
begin\r
if( rising_edge(CLK) ) then\r
- if( select_current_state = SELECT_ONE or select_current_state = PROCESS_REQUEST ) then\r
+ if( (select_current_state = SELECT_ONE) or (select_current_state = PROCESS_REQUEST) ) then\r
TC_DATA_OUT <= tc_data((index + 1) * 9 - 1 downto index * 9);\r
TC_FRAME_SIZE_OUT <= tc_size((index + 1) * 16 - 1 downto index * 16);\r
TC_FRAME_TYPE_OUT <= tc_type((index + 1) * 16 - 1 downto index * 16);\r
--- /dev/null
+[Device]\r
+Family=latticeecp3\r
+PartType=LFE3-150EA\r
+PartName=LFE3-150EA-6FN672C\r
+SpeedGrade=6\r
+Package=FPBGA672\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=DDR_GENERIC\r
+CoreRevision=6.0\r
+ModuleName=ddr_out\r
+SourceFormat=VHDL\r
+ParameterFileVersion=1.0\r
+Date=11/12/2022\r
+Time=17:51:26\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+mode=Transmit\r
+trioddr=0\r
+io_type=LVCMOS25\r
+num_int=1\r
+width=1\r
+freq_in=125\r
+bandwidth=250\r
+aligned=Edge-to-Edge\r
+pre-configuration=ENABLED\r
+mode2=Transmit\r
+trioddr2=0\r
+io_type2=LVCMOS25\r
+freq_in2=125\r
+gear=1x\r
+aligned2=Edge-to-Edge\r
+num_int2=1\r
+width2=1\r
+Interface=GDDRX1_TX.SCLK.Aligned\r
+Delay=\r
+Number=\r
+dqs1=\r
+dqs2=\r
+dqs3=\r
+dqs4=\r
+dqs5=\r
+dqs6=\r
+dqs7=\r
+dqs8=\r
+val=\r
+Phase=TRDLLB/DLLDELB\r
+Divider=CLKDIVB\r
+Multiplier=2\r
+PllFreq=62\r
+\r
+[Command]\r
+cmd_line= -w -n ddr_out -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type iol -mode out -io_type LVCMOS25 -width 1 -freq_in 125 -gear 1 -clk sclk -aligned\r
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454
+-- Module Version: 5.8
+--C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n ddr_out -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type iol -mode out -io_type LVCMOS25 -width 1 -freq_in 125 -gear 1 -clk sclk -aligned
+
+-- Sat Nov 12 17:51:26 2022
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity ddr_out is
+ port (
+ clk: in std_logic;
+ clkout: out std_logic;
+ da: in std_logic_vector(0 downto 0);
+ db: in std_logic_vector(0 downto 0);
+ q: out std_logic_vector(0 downto 0));
+end ddr_out;
+
+architecture Structure of ddr_out is
+
+ -- internal signal declarations
+ signal buf_clkout: std_logic;
+ signal scuba_vlo: std_logic;
+ signal scuba_vhi: std_logic;
+ signal clkos: std_logic;
+ signal clkop: std_logic;
+ signal buf_qo0: std_logic;
+
+ -- local component declarations
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component OB
+ port (I: in std_logic; O: out std_logic);
+ end component;
+ component ODDRXD1
+ port (DA: in std_logic; DB: in std_logic; SCLK: in std_logic;
+ Q: out std_logic);
+ end component;
+ attribute ODDRAPPS : string;
+ attribute IO_TYPE : string;
+ attribute IO_TYPE of Inst3_OB : label is "LVCMOS25";
+ attribute ODDRAPPS of Inst_ODDRXD1_0_0 : label is "SCLK_ALIGNED";
+ attribute ODDRAPPS of Inst2_ODDRXD1 : label is "SCLK_ALIGNED";
+ attribute IO_TYPE of Inst1_OB0 : label is "LVCMOS25";
+ attribute syn_keep : boolean;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ Inst3_OB: OB
+ port map (I=>buf_clkout, O=>clkout);
+
+ Inst_ODDRXD1_0_0: ODDRXD1
+ port map (DA=>da(0), DB=>db(0), SCLK=>clkop, Q=>buf_qo0);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ Inst2_ODDRXD1: ODDRXD1
+ port map (DA=>scuba_vhi, DB=>scuba_vlo, SCLK=>clkos,
+ Q=>buf_clkout);
+
+ Inst1_OB0: OB
+ port map (I=>buf_qo0, O=>q(0));
+
+ clkos <= clk;
+ clkop <= clk;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of ddr_out is
+ for Structure
+ for all:VHI use entity ecp3.VHI(V); end for;
+ for all:VLO use entity ecp3.VLO(V); end for;
+ for all:OB use entity ecp3.OB(V); end for;
+ for all:ODDRXD1 use entity ecp3.ODDRXD1(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+[Device]\r
+Family=latticeecp3\r
+PartType=LFE3-150EA\r
+PartName=LFE3-150EA-6FN672C\r
+SpeedGrade=6\r
+Package=FPBGA672\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=SDR\r
+CoreRevision=6.0\r
+ModuleName=odr_dbg\r
+SourceFormat=VHDL\r
+ParameterFileVersion=1.0\r
+Date=11/12/2022\r
+Time=18:59:59\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+mode=Transmit\r
+io_type=LVCMOS25\r
+width=32\r
+freq_in=125\r
+bandwidth=4000\r
+interface=GOREG_TX.SCLK\r
+negedge=DISABLED\r
+del=\r
+fdel=\r
+\r
+[Command]\r
+cmd_line= -w -n odr_dbg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type iol -mode out -io_type LVCMOS25 -width 32 -freq_in 125 -clk sclk -aligned -gear 0\r
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454
+-- Module Version: 5.8
+--C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n odr_dbg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type iol -mode out -io_type LVCMOS25 -width 32 -freq_in 125 -clk sclk -aligned -gear 0
+
+-- Sat Nov 12 18:59:59 2022
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity odr_dbg is
+ port (
+ clk: in std_logic;
+ clkout: out std_logic;
+ reset: in std_logic;
+ d: in std_logic_vector(31 downto 0);
+ dout: out std_logic_vector(31 downto 0));
+end odr_dbg;
+
+architecture Structure of odr_dbg is
+
+ -- internal signal declarations
+ signal buf_clkout: std_logic;
+ signal scuba_vlo: std_logic;
+ signal scuba_vhi: std_logic;
+ signal buf_douto31: std_logic;
+ signal buf_douto30: std_logic;
+ signal buf_douto29: std_logic;
+ signal buf_douto28: std_logic;
+ signal buf_douto27: std_logic;
+ signal buf_douto26: std_logic;
+ signal buf_douto25: std_logic;
+ signal buf_douto24: std_logic;
+ signal buf_douto23: std_logic;
+ signal buf_douto22: std_logic;
+ signal buf_douto21: std_logic;
+ signal buf_douto20: std_logic;
+ signal buf_douto19: std_logic;
+ signal buf_douto18: std_logic;
+ signal buf_douto17: std_logic;
+ signal buf_douto16: std_logic;
+ signal buf_douto15: std_logic;
+ signal buf_douto14: std_logic;
+ signal buf_douto13: std_logic;
+ signal buf_douto12: std_logic;
+ signal buf_douto11: std_logic;
+ signal buf_douto10: std_logic;
+ signal buf_douto9: std_logic;
+ signal buf_douto8: std_logic;
+ signal buf_douto7: std_logic;
+ signal buf_douto6: std_logic;
+ signal buf_douto5: std_logic;
+ signal buf_douto4: std_logic;
+ signal buf_douto3: std_logic;
+ signal buf_douto2: std_logic;
+ signal buf_douto1: std_logic;
+ signal buf_douto0: std_logic;
+
+ -- local component declarations
+ component OFS1P3DX
+ port (D: in std_logic; SP: in std_logic; SCLK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component OB
+ port (I: in std_logic; O: out std_logic);
+ end component;
+ component ODDRXD1
+ port (DA: in std_logic; DB: in std_logic; SCLK: in std_logic;
+ Q: out std_logic);
+ end component;
+ attribute ODDRAPPS : string;
+ attribute IO_TYPE : string;
+ attribute IO_TYPE of Inst4_OB : label is "LVCMOS25";
+ attribute ODDRAPPS of Inst3_ODDRXD1 : label is "SCLK_ALIGNED";
+ attribute IO_TYPE of Inst1_OB31 : label is "LVCMOS25";
+ attribute IO_TYPE of Inst1_OB30 : label is "LVCMOS25";
+ attribute IO_TYPE of Inst1_OB29 : label is "LVCMOS25";
+ attribute IO_TYPE of Inst1_OB28 : label is "LVCMOS25";
+ attribute IO_TYPE of Inst1_OB27 : label is "LVCMOS25";
+ attribute IO_TYPE of Inst1_OB26 : label is "LVCMOS25";
+ attribute IO_TYPE of Inst1_OB25 : label is "LVCMOS25";
+ attribute IO_TYPE of Inst1_OB24 : label is "LVCMOS25";
+ attribute IO_TYPE of Inst1_OB23 : label is "LVCMOS25";
+ attribute IO_TYPE of Inst1_OB22 : label is "LVCMOS25";
+ attribute IO_TYPE of Inst1_OB21 : label is "LVCMOS25";
+ attribute IO_TYPE of Inst1_OB20 : label is "LVCMOS25";
+ attribute IO_TYPE of Inst1_OB19 : label is "LVCMOS25";
+ attribute IO_TYPE of Inst1_OB18 : label is "LVCMOS25";
+ attribute IO_TYPE of Inst1_OB17 : label is "LVCMOS25";
+ attribute IO_TYPE of Inst1_OB16 : label is "LVCMOS25";
+ attribute IO_TYPE of Inst1_OB15 : label is "LVCMOS25";
+ attribute IO_TYPE of Inst1_OB14 : label is "LVCMOS25";
+ attribute IO_TYPE of Inst1_OB13 : label is "LVCMOS25";
+ attribute IO_TYPE of Inst1_OB12 : label is "LVCMOS25";
+ attribute IO_TYPE of Inst1_OB11 : label is "LVCMOS25";
+ attribute IO_TYPE of Inst1_OB10 : label is "LVCMOS25";
+ attribute IO_TYPE of Inst1_OB9 : label is "LVCMOS25";
+ attribute IO_TYPE of Inst1_OB8 : label is "LVCMOS25";
+ attribute IO_TYPE of Inst1_OB7 : label is "LVCMOS25";
+ attribute IO_TYPE of Inst1_OB6 : label is "LVCMOS25";
+ attribute IO_TYPE of Inst1_OB5 : label is "LVCMOS25";
+ attribute IO_TYPE of Inst1_OB4 : label is "LVCMOS25";
+ attribute IO_TYPE of Inst1_OB3 : label is "LVCMOS25";
+ attribute IO_TYPE of Inst1_OB2 : label is "LVCMOS25";
+ attribute IO_TYPE of Inst1_OB1 : label is "LVCMOS25";
+ attribute IO_TYPE of Inst1_OB0 : label is "LVCMOS25";
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ Inst4_OB: OB
+ port map (I=>buf_clkout, O=>clkout);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ Inst3_ODDRXD1: ODDRXD1
+ port map (DA=>scuba_vhi, DB=>scuba_vlo, SCLK=>clk, Q=>buf_clkout);
+
+ Inst2_OFS1P3DX31: OFS1P3DX
+ port map (D=>d(31), SP=>scuba_vhi, SCLK=>clk, CD=>reset,
+ Q=>buf_douto31);
+
+ Inst2_OFS1P3DX30: OFS1P3DX
+ port map (D=>d(30), SP=>scuba_vhi, SCLK=>clk, CD=>reset,
+ Q=>buf_douto30);
+
+ Inst2_OFS1P3DX29: OFS1P3DX
+ port map (D=>d(29), SP=>scuba_vhi, SCLK=>clk, CD=>reset,
+ Q=>buf_douto29);
+
+ Inst2_OFS1P3DX28: OFS1P3DX
+ port map (D=>d(28), SP=>scuba_vhi, SCLK=>clk, CD=>reset,
+ Q=>buf_douto28);
+
+ Inst2_OFS1P3DX27: OFS1P3DX
+ port map (D=>d(27), SP=>scuba_vhi, SCLK=>clk, CD=>reset,
+ Q=>buf_douto27);
+
+ Inst2_OFS1P3DX26: OFS1P3DX
+ port map (D=>d(26), SP=>scuba_vhi, SCLK=>clk, CD=>reset,
+ Q=>buf_douto26);
+
+ Inst2_OFS1P3DX25: OFS1P3DX
+ port map (D=>d(25), SP=>scuba_vhi, SCLK=>clk, CD=>reset,
+ Q=>buf_douto25);
+
+ Inst2_OFS1P3DX24: OFS1P3DX
+ port map (D=>d(24), SP=>scuba_vhi, SCLK=>clk, CD=>reset,
+ Q=>buf_douto24);
+
+ Inst2_OFS1P3DX23: OFS1P3DX
+ port map (D=>d(23), SP=>scuba_vhi, SCLK=>clk, CD=>reset,
+ Q=>buf_douto23);
+
+ Inst2_OFS1P3DX22: OFS1P3DX
+ port map (D=>d(22), SP=>scuba_vhi, SCLK=>clk, CD=>reset,
+ Q=>buf_douto22);
+
+ Inst2_OFS1P3DX21: OFS1P3DX
+ port map (D=>d(21), SP=>scuba_vhi, SCLK=>clk, CD=>reset,
+ Q=>buf_douto21);
+
+ Inst2_OFS1P3DX20: OFS1P3DX
+ port map (D=>d(20), SP=>scuba_vhi, SCLK=>clk, CD=>reset,
+ Q=>buf_douto20);
+
+ Inst2_OFS1P3DX19: OFS1P3DX
+ port map (D=>d(19), SP=>scuba_vhi, SCLK=>clk, CD=>reset,
+ Q=>buf_douto19);
+
+ Inst2_OFS1P3DX18: OFS1P3DX
+ port map (D=>d(18), SP=>scuba_vhi, SCLK=>clk, CD=>reset,
+ Q=>buf_douto18);
+
+ Inst2_OFS1P3DX17: OFS1P3DX
+ port map (D=>d(17), SP=>scuba_vhi, SCLK=>clk, CD=>reset,
+ Q=>buf_douto17);
+
+ Inst2_OFS1P3DX16: OFS1P3DX
+ port map (D=>d(16), SP=>scuba_vhi, SCLK=>clk, CD=>reset,
+ Q=>buf_douto16);
+
+ Inst2_OFS1P3DX15: OFS1P3DX
+ port map (D=>d(15), SP=>scuba_vhi, SCLK=>clk, CD=>reset,
+ Q=>buf_douto15);
+
+ Inst2_OFS1P3DX14: OFS1P3DX
+ port map (D=>d(14), SP=>scuba_vhi, SCLK=>clk, CD=>reset,
+ Q=>buf_douto14);
+
+ Inst2_OFS1P3DX13: OFS1P3DX
+ port map (D=>d(13), SP=>scuba_vhi, SCLK=>clk, CD=>reset,
+ Q=>buf_douto13);
+
+ Inst2_OFS1P3DX12: OFS1P3DX
+ port map (D=>d(12), SP=>scuba_vhi, SCLK=>clk, CD=>reset,
+ Q=>buf_douto12);
+
+ Inst2_OFS1P3DX11: OFS1P3DX
+ port map (D=>d(11), SP=>scuba_vhi, SCLK=>clk, CD=>reset,
+ Q=>buf_douto11);
+
+ Inst2_OFS1P3DX10: OFS1P3DX
+ port map (D=>d(10), SP=>scuba_vhi, SCLK=>clk, CD=>reset,
+ Q=>buf_douto10);
+
+ Inst2_OFS1P3DX9: OFS1P3DX
+ port map (D=>d(9), SP=>scuba_vhi, SCLK=>clk, CD=>reset,
+ Q=>buf_douto9);
+
+ Inst2_OFS1P3DX8: OFS1P3DX
+ port map (D=>d(8), SP=>scuba_vhi, SCLK=>clk, CD=>reset,
+ Q=>buf_douto8);
+
+ Inst2_OFS1P3DX7: OFS1P3DX
+ port map (D=>d(7), SP=>scuba_vhi, SCLK=>clk, CD=>reset,
+ Q=>buf_douto7);
+
+ Inst2_OFS1P3DX6: OFS1P3DX
+ port map (D=>d(6), SP=>scuba_vhi, SCLK=>clk, CD=>reset,
+ Q=>buf_douto6);
+
+ Inst2_OFS1P3DX5: OFS1P3DX
+ port map (D=>d(5), SP=>scuba_vhi, SCLK=>clk, CD=>reset,
+ Q=>buf_douto5);
+
+ Inst2_OFS1P3DX4: OFS1P3DX
+ port map (D=>d(4), SP=>scuba_vhi, SCLK=>clk, CD=>reset,
+ Q=>buf_douto4);
+
+ Inst2_OFS1P3DX3: OFS1P3DX
+ port map (D=>d(3), SP=>scuba_vhi, SCLK=>clk, CD=>reset,
+ Q=>buf_douto3);
+
+ Inst2_OFS1P3DX2: OFS1P3DX
+ port map (D=>d(2), SP=>scuba_vhi, SCLK=>clk, CD=>reset,
+ Q=>buf_douto2);
+
+ Inst2_OFS1P3DX1: OFS1P3DX
+ port map (D=>d(1), SP=>scuba_vhi, SCLK=>clk, CD=>reset,
+ Q=>buf_douto1);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ Inst2_OFS1P3DX0: OFS1P3DX
+ port map (D=>d(0), SP=>scuba_vhi, SCLK=>clk, CD=>reset,
+ Q=>buf_douto0);
+
+ Inst1_OB31: OB
+ port map (I=>buf_douto31, O=>dout(31));
+
+ Inst1_OB30: OB
+ port map (I=>buf_douto30, O=>dout(30));
+
+ Inst1_OB29: OB
+ port map (I=>buf_douto29, O=>dout(29));
+
+ Inst1_OB28: OB
+ port map (I=>buf_douto28, O=>dout(28));
+
+ Inst1_OB27: OB
+ port map (I=>buf_douto27, O=>dout(27));
+
+ Inst1_OB26: OB
+ port map (I=>buf_douto26, O=>dout(26));
+
+ Inst1_OB25: OB
+ port map (I=>buf_douto25, O=>dout(25));
+
+ Inst1_OB24: OB
+ port map (I=>buf_douto24, O=>dout(24));
+
+ Inst1_OB23: OB
+ port map (I=>buf_douto23, O=>dout(23));
+
+ Inst1_OB22: OB
+ port map (I=>buf_douto22, O=>dout(22));
+
+ Inst1_OB21: OB
+ port map (I=>buf_douto21, O=>dout(21));
+
+ Inst1_OB20: OB
+ port map (I=>buf_douto20, O=>dout(20));
+
+ Inst1_OB19: OB
+ port map (I=>buf_douto19, O=>dout(19));
+
+ Inst1_OB18: OB
+ port map (I=>buf_douto18, O=>dout(18));
+
+ Inst1_OB17: OB
+ port map (I=>buf_douto17, O=>dout(17));
+
+ Inst1_OB16: OB
+ port map (I=>buf_douto16, O=>dout(16));
+
+ Inst1_OB15: OB
+ port map (I=>buf_douto15, O=>dout(15));
+
+ Inst1_OB14: OB
+ port map (I=>buf_douto14, O=>dout(14));
+
+ Inst1_OB13: OB
+ port map (I=>buf_douto13, O=>dout(13));
+
+ Inst1_OB12: OB
+ port map (I=>buf_douto12, O=>dout(12));
+
+ Inst1_OB11: OB
+ port map (I=>buf_douto11, O=>dout(11));
+
+ Inst1_OB10: OB
+ port map (I=>buf_douto10, O=>dout(10));
+
+ Inst1_OB9: OB
+ port map (I=>buf_douto9, O=>dout(9));
+
+ Inst1_OB8: OB
+ port map (I=>buf_douto8, O=>dout(8));
+
+ Inst1_OB7: OB
+ port map (I=>buf_douto7, O=>dout(7));
+
+ Inst1_OB6: OB
+ port map (I=>buf_douto6, O=>dout(6));
+
+ Inst1_OB5: OB
+ port map (I=>buf_douto5, O=>dout(5));
+
+ Inst1_OB4: OB
+ port map (I=>buf_douto4, O=>dout(4));
+
+ Inst1_OB3: OB
+ port map (I=>buf_douto3, O=>dout(3));
+
+ Inst1_OB2: OB
+ port map (I=>buf_douto2, O=>dout(2));
+
+ Inst1_OB1: OB
+ port map (I=>buf_douto1, O=>dout(1));
+
+ Inst1_OB0: OB
+ port map (I=>buf_douto0, O=>dout(0));
+
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of odr_dbg is
+ for Structure
+ for all:OFS1P3DX use entity ecp3.OFS1P3DX(V); end for;
+ for all:VHI use entity ecp3.VHI(V); end for;
+ for all:VLO use entity ecp3.VLO(V); end for;
+ for all:OB use entity ecp3.OB(V); end for;
+ for all:ODDRXD1 use entity ecp3.ODDRXD1(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
\r
signal state : std_logic_vector(3 downto 0);\r
\r
- signal test_ff : std_logic;\r
+-- signal test_ff : std_logic;\r
\r
attribute syn_preserve : boolean;\r
attribute syn_keep : boolean;\r
attribute syn_keep of state : signal is true;\r
attribute syn_preserve of state : signal is true;\r
\r
+ signal stored_magic : std_logic_vector(31 downto 0);\r
+ signal stored_opcode : std_logic_vector(7 downto 0);\r
+ signal stored_random : std_logic_vector(7 downto 0);\r
+ signal stored_length : std_logic_vector(15 downto 0);\r
+ signal stored_address : std_logic_vector(31 downto 0);\r
+ signal stored_data : std_logic_vector(31 downto 0);\r
+ \r
+ signal ps_response_ready : std_logic;\r
+ signal ps_busy : std_logic;\r
+ signal tc_data_q : std_logic_vector(8 downto 0);\r
+ \r
begin\r
\r
DEBUG_OUT(63 downto 32) <= (others => '0');\r
- DEBUG_OUT(31) <= test_ff;\r
- DEBUG_OUT(30 downto 4) <= (others => '0');\r
- DEBUG_OUT(3 downto 0) <= state;\r
+ DEBUG_OUT(31 downto 28) <= state;\r
+ DEBUG_OUT(27 downto 24) <= std_logic_vector(dissect_ctr(3 downto 0));\r
+ DEBUG_OUT(23) <= TC_RD_EN_IN;\r
+ DEBUG_OUT(22) <= ps_response_ready;\r
+ DEBUG_OUT(21) <= ps_busy;\r
+ DEBUG_OUT(20) <= PS_SELECTED_IN;\r
+ DEBUG_OUT(19) <= PS_WR_EN_IN;\r
+ DEBUG_OUT(18) <= PS_ACTIVATE_IN;\r
+ DEBUG_OUT(17 downto 9) <= tc_data_q;\r
+ DEBUG_OUT(8 downto 0) <= PS_DATA_IN;\r
\r
- PROC_TEST_FF: process( CLK, RESET )\r
- begin\r
- if ( RESET = '1' ) then\r
- test_ff <= '0';\r
- elsif( rising_edge(CLK) ) then\r
- if( DISSECT_CS = DELAY ) then\r
- test_ff <= not test_ff;\r
- end if;\r
- end if;\r
- end process PROC_TEST_FF;\r
+-- -- simple toggle FF for testing\r
+-- PROC_TEST_FF: process( CLK, RESET )\r
+-- begin\r
+-- if ( RESET = '1' ) then\r
+-- test_ff <= '0';\r
+-- elsif( rising_edge(CLK) ) then\r
+-- if( DISSECT_CS = DELAY ) then\r
+-- test_ff <= not test_ff;\r
+-- end if;\r
+-- end if;\r
+-- end process PROC_TEST_FF;\r
\r
+ -- statemachine\r
PROC_DISSECT_FSM: process( CLK, RESET )\r
begin\r
if ( RESET = '1' ) then\r
case DISSECT_CS is\r
\r
when IDLE =>\r
- state <= x"1";\r
+ state <= x"0";\r
if( (PS_WR_EN_IN = '1') and (PS_ACTIVATE_IN = '1') ) then\r
DISSECT_NS <= READ_FRAME;\r
else\r
end if;\r
\r
when READ_FRAME =>\r
- state <= x"2";\r
+ state <= x"1";\r
-- BUG: fails on empty payload\r
if( PS_DATA_IN(8) = '1' ) then\r
DISSECT_NS <= DELAY;\r
end if;\r
\r
when DELAY =>\r
+ state <= x"2";\r
DISSECT_NS <= DECIDE;\r
\r
when DECIDE =>\r
state <= x"3";\r
-- if( saved_target_ip = MY_IP_IN ) then\r
--- DISSECT_NS <= WAIT_FOR_LOAD;\r
+ DISSECT_NS <= WAIT_FOR_LOAD;\r
-- -- in case the request is not for me, drop it\r
-- else\r
- DISSECT_NS <= IDLE;\r
+-- DISSECT_NS <= IDLE;\r
-- end if;\r
\r
when WAIT_FOR_LOAD =>\r
\r
when LOAD_FRAME =>\r
state <= x"5";\r
- if( dissect_ctr = x"1c" ) then\r
+ if( dissect_ctr = x"14" ) then\r
DISSECT_NS <= CLEANUP;\r
else\r
DISSECT_NS <= LOAD_FRAME;\r
end if;\r
\r
when CLEANUP =>\r
- state <= x"e";\r
+ state <= x"6";\r
DISSECT_NS <= IDLE;\r
\r
end case;\r
end process PROC_DISSECT_TRANSITIONS;\r
\r
+ -- counter for parsing received data and contructing frame\r
PROC_DISSEC_CTR: process( CLK, RESET )\r
begin\r
if ( RESET = '1' ) then\r
PROC_SAVE_VALUES: process( CLK, RESET )\r
begin\r
if ( RESET = '1' ) then\r
- saved_opcode <= (others => '0');\r
- saved_sender_ip <= (others => '0');\r
- saved_target_ip <= (others => '0');\r
+ stored_magic <= (others => '0');\r
+ stored_opcode <= (others => '0');\r
+ stored_random <= (others => '0');\r
+ stored_length <= (others => '0');\r
+ stored_address <= (others => '0');\r
+ stored_data <= (others => '0');\r
elsif( rising_edge(CLK) ) then\r
- if( DISSECT_CS = READ_FRAME ) then\r
+ if( ((DISSECT_CS = IDLE) or (DISSECT_CS = READ_FRAME)) and (PS_WR_EN_IN = '1') ) then\r
case dissect_ctr is\r
-\r
- when x"06" =>\r
- saved_opcode(7 downto 0) <= PS_DATA_IN(7 downto 0);\r
- when x"07" =>\r
- saved_opcode(15 downto 8) <= PS_DATA_IN(7 downto 0);\r
- when x"0e" =>\r
- saved_sender_ip(7 downto 0) <= PS_DATA_IN(7 downto 0);\r
- when x"0f" =>\r
- saved_sender_ip(15 downto 8) <= PS_DATA_IN(7 downto 0);\r
- when x"10" =>\r
- saved_sender_ip(23 downto 16) <= PS_DATA_IN(7 downto 0);\r
- when x"11" =>\r
- saved_sender_ip(31 downto 24) <= PS_DATA_IN(7 downto 0);\r
- when x"18" =>\r
- saved_target_ip(7 downto 0) <= PS_DATA_IN(7 downto 0);\r
- when x"19" =>\r
- saved_target_ip(15 downto 8) <= PS_DATA_IN(7 downto 0);\r
- when x"1a" =>\r
- saved_target_ip(23 downto 16) <= PS_DATA_IN(7 downto 0);\r
- when x"1b" =>\r
- saved_target_ip(31 downto 24) <= PS_DATA_IN(7 downto 0);\r
-\r
+ when x"00" => stored_magic(7 downto 0) <= PS_DATA_IN(7 downto 0);\r
+ when x"01" => stored_magic(15 downto 8) <= PS_DATA_IN(7 downto 0);\r
+ when x"02" => stored_magic(23 downto 16) <= PS_DATA_IN(7 downto 0);\r
+ when x"03" => stored_magic(31 downto 24) <= PS_DATA_IN(7 downto 0);\r
+ when x"04" => stored_opcode <= PS_DATA_IN(7 downto 0);\r
+ when x"05" => stored_random <= PS_DATA_IN(7 downto 0);\r
+ when x"06" => stored_length(7 downto 0) <= PS_DATA_IN(7 downto 0);\r
+ when x"07" => stored_length(15 downto 8) <= PS_DATA_IN(7 downto 0);\r
+ when x"08" => stored_address(7 downto 0) <= PS_DATA_IN(7 downto 0);\r
+ when x"09" => stored_address(15 downto 8) <= PS_DATA_IN(7 downto 0);\r
+ when x"0a" => stored_address(23 downto 16) <= PS_DATA_IN(7 downto 0);\r
+ when x"0b" => stored_address(31 downto 24) <= PS_DATA_IN(7 downto 0);\r
+ when x"0c" => stored_data(7 downto 0) <= PS_DATA_IN(7 downto 0);\r
+ when x"0d" => stored_data(15 downto 8) <= PS_DATA_IN(7 downto 0);\r
+ when x"0e" => stored_data(23 downto 16) <= PS_DATA_IN(7 downto 0);\r
+ when x"0f" => stored_data(31 downto 24) <= PS_DATA_IN(7 downto 0);\r
when others => null;\r
end case;\r
end if;\r
if( rising_edge(CLK) ) then\r
tc_data(8) <= '0';\r
tc_data(7 downto 0) <= x"00";\r
- if( DISSECT_CS = LOAD_FRAME ) then\r
+ if( (DISSECT_CS = LOAD_FRAME) ) then\r
case dissect_ctr is\r
- when x"00" => tc_data(7 downto 0) <= x"00"; -- HWTYPE\r
- when x"01" => tc_data(7 downto 0) <= x"01";\r
- when x"02" => tc_data(7 downto 0) <= x"08"; -- PTYPE\r
- when x"03" => tc_data(7 downto 0) <= x"00";\r
- when x"04" => tc_data(7 downto 0) <= x"06"; -- HLEN\r
- when x"05" => tc_data(7 downto 0) <= x"04"; -- PLEN\r
- when x"06" => tc_data(7 downto 0) <= x"00"; -- OPER\r
- when x"07" => tc_data(7 downto 0) <= x"02";\r
- when x"08" => tc_data(7 downto 0) <= MY_MAC_IN(7 downto 0); -- SHA\r
+ when x"00" => tc_data(7 downto 0) <= stored_magic(7 downto 0);\r
+ when x"01" => tc_data(7 downto 0) <= stored_magic(15 downto 8);\r
+ when x"02" => tc_data(7 downto 0) <= stored_magic(23 downto 16);\r
+ when x"03" => tc_data(7 downto 0) <= stored_magic(31 downto 24);\r
+ when x"04" => tc_data(7 downto 0) <= x"1d"; -- ID\r
+ when x"05" => tc_data(7 downto 0) <= stored_random;\r
+ when x"06" => tc_data(7 downto 0) <= x"00";\r
+ when x"07" => tc_data(7 downto 0) <= x"0c"; -- length\r
+ when x"08" => tc_data(7 downto 0) <= MY_MAC_IN(7 downto 0);\r
when x"09" => tc_data(7 downto 0) <= MY_MAC_IN(15 downto 8);\r
when x"0a" => tc_data(7 downto 0) <= MY_MAC_IN(23 downto 16);\r
when x"0b" => tc_data(7 downto 0) <= MY_MAC_IN(31 downto 24);\r
when x"0c" => tc_data(7 downto 0) <= MY_MAC_IN(39 downto 32);\r
when x"0d" => tc_data(7 downto 0) <= MY_MAC_IN(47 downto 40);\r
- when x"0e" => tc_data(7 downto 0) <= MY_IP_IN(7 downto 0); -- SPA\r
- when x"0f" => tc_data(7 downto 0) <= MY_IP_IN(15 downto 8);\r
- when x"10" => tc_data(7 downto 0) <= MY_IP_IN(23 downto 16);\r
- when x"11" => tc_data(7 downto 0) <= MY_IP_IN(31 downto 24);\r
- when x"12" => tc_data(7 downto 0) <= PS_SRC_MAC_ADDRESS_IN(7 downto 0); -- THA\r
- when x"13" => tc_data(7 downto 0) <= PS_SRC_MAC_ADDRESS_IN(15 downto 8);\r
- when x"14" => tc_data(7 downto 0) <= PS_SRC_MAC_ADDRESS_IN(23 downto 16);\r
- when x"15" => tc_data(7 downto 0) <= PS_SRC_MAC_ADDRESS_IN(31 downto 24);\r
- when x"16" => tc_data(7 downto 0) <= PS_SRC_MAC_ADDRESS_IN(39 downto 32);\r
- when x"17" => tc_data(7 downto 0) <= PS_SRC_MAC_ADDRESS_IN(47 downto 40);\r
- when x"18" => tc_data(7 downto 0) <= saved_sender_ip(7 downto 0); -- TPA\r
- when x"19" => tc_data(7 downto 0) <= saved_sender_ip(15 downto 8);\r
- when x"1a" => tc_data(7 downto 0) <= saved_sender_ip(23 downto 16);\r
- when x"1b" => tc_data(7 downto 0) <= saved_sender_ip(31 downto 24); tc_data(8) <= '1';\r
+ when x"0e" => tc_data(7 downto 0) <= x"00";\r
+ when x"0f" => tc_data(7 downto 0) <= x"00";\r
+ when x"10" => tc_data(7 downto 0) <= MY_IP_IN(7 downto 0);\r
+ when x"11" => tc_data(7 downto 0) <= MY_IP_IN(15 downto 8);\r
+ when x"12" => tc_data(7 downto 0) <= MY_IP_IN(23 downto 16);\r
+ when x"13" => tc_data(7 downto 0) <= MY_IP_IN(31 downto 24); tc_data(8) <= '1';\r
when others => tc_data(7 downto 0) <= x"00";\r
end case;\r
- TC_DATA_OUT <= tc_data; -- delay once clock cycle\r
+-- TC_DATA_OUT <= tc_data; -- delay once clock cycle\r
+ tc_data_q <= tc_data; -- delay once clock cycle\r
end if;\r
end if;\r
end process PROC_TC_DATA;\r
\r
+ TC_DATA_OUT <= tc_data_q;\r
+ \r
PROC_PS_RESPONSE_SYNC: process( CLK )\r
begin\r
if( rising_edge(CLK) ) then\r
if( (DISSECT_CS = WAIT_FOR_LOAD) or (DISSECT_CS = LOAD_FRAME) or (DISSECT_CS = CLEANUP) ) then\r
- PS_RESPONSE_READY_OUT <= '1';\r
+-- PS_RESPONSE_READY_OUT <= '1';\r
+ ps_response_ready <= '1';\r
else\r
- PS_RESPONSE_READY_OUT <= '0';\r
+-- PS_RESPONSE_READY_OUT <= '0';\r
+ ps_response_ready <= '0';\r
end if;\r
\r
if( DISSECT_CS = IDLE ) then\r
- PS_BUSY_OUT <= '0';\r
+-- PS_BUSY_OUT <= '0';\r
+ ps_busy <= '0';\r
else\r
- PS_BUSY_OUT <= '1';\r
+-- PS_BUSY_OUT <= '1';\r
+ ps_busy <= '1';\r
end if;\r
end if;\r
end process PROC_PS_RESPONSE_SYNC;\r
\r
- TC_FRAME_SIZE_OUT <= x"001c"; -- fixed frame size\r
- TC_FRAME_TYPE_OUT <= x"0608";\r
+ PS_RESPONSE_READY_OUT <= ps_response_ready;\r
+ PS_BUSY_OUT <= ps_busy;\r
+ \r
+ TC_FRAME_SIZE_OUT <= x"0014"; -- fixed frame size\r
+ TC_FRAME_TYPE_OUT <= x"0008"; -- byte swapped\r
TC_DEST_MAC_OUT <= PS_SRC_MAC_ADDRESS_IN;\r
- TC_DEST_IP_OUT <= x"00000000"; -- doesnt matter\r
- TC_DEST_UDP_OUT <= x"0000"; -- doesnt matter\r
+ TC_DEST_IP_OUT <= PS_SRC_IP_ADDRESS_IN;\r
+ TC_DEST_UDP_OUT <= PS_SRC_UDP_PORT_IN;\r
TC_SRC_MAC_OUT <= MY_MAC_IN;\r
- TC_SRC_IP_OUT <= x"00000000"; -- doesnt matter\r
- TC_SRC_UDP_OUT <= x"0000"; -- doesnt matter\r
- TC_IP_PROTOCOL_OUT <= x"00"; -- doesnt matter\r
+ TC_SRC_IP_OUT <= MY_IP_IN;\r
+ TC_SRC_UDP_OUT <= x"03d9"; -- byte swapped\r
+ TC_IP_PROTOCOL_OUT <= x"11"; \r
TC_IDENT_OUT <= (others => '0'); -- doesn't matter\r
\r
end gbe_response_constructor_Discovery_arch;\r
end if;\r
end process PS_RESPONSE_SYNC;\r
\r
- TC_FRAME_TYPE_OUT <= x"0008";\r
--- TC_DEST_MAC_OUT <= PS_SRC_MAC_ADDRESS_IN;\r
- TC_DEST_MAC_OUT <= saved_dst_mac;\r
- TC_DEST_IP_OUT <= PS_SRC_IP_ADDRESS_IN;\r
- TC_DEST_UDP_OUT(7 downto 0) <= PS_SRC_UDP_PORT_IN(15 downto 8);\r
- TC_DEST_UDP_OUT(15 downto 8) <= PS_SRC_UDP_PORT_IN(7 downto 0);\r
- TC_SRC_MAC_OUT <= MY_MAC_IN;\r
- TC_SRC_IP_OUT <= MY_IP_IN;\r
- TC_SRC_UDP_OUT <= x"9065"; --x"a861"; -- BUG?!? shouldn't we use the SRC UDP port?\r
- TC_IP_PROTOCOL_OUT <= x"11";\r
- TC_IDENT_OUT <= x"3" & std_logic_vector(reply_ctr(11 downto 0));\r
+ TC_FRAME_TYPE_OUT <= x"0008"; -- byte swapped\r
+-- TC_DEST_MAC_OUT <= PS_SRC_MAC_ADDRESS_IN;\r
+ TC_DEST_MAC_OUT <= saved_dst_mac;\r
+ TC_DEST_IP_OUT <= PS_SRC_IP_ADDRESS_IN;\r
+ TC_DEST_UDP_OUT <= PS_SRC_UDP_PORT_IN;\r
+-- TC_DEST_UDP_OUT(7 downto 0) <= PS_SRC_UDP_PORT_IN(15 downto 8);\r
+-- TC_DEST_UDP_OUT(15 downto 8) <= PS_SRC_UDP_PORT_IN(7 downto 0);\r
+ TC_SRC_MAC_OUT <= MY_MAC_IN;\r
+ TC_SRC_IP_OUT <= MY_IP_IN;\r
+ TC_SRC_UDP_OUT <= x"9065"; -- byte swapped\r
+ TC_IP_PROTOCOL_OUT <= x"11";\r
+ TC_IDENT_OUT <= x"3" & std_logic_vector(reply_ctr(11 downto 0));\r
\r
TC_FRAME_SIZE_OUT <= std_logic_vector(tx_data_ctr);\r
\r
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