signal word_i : std_logic_vector(31 downto 0);
signal word_valid : std_logic;
- signal businp_rx, busword_rx : CTRLBUS_RX;
- signal businp_tx, busword_tx : CTRLBUS_TX;
+ signal businp_rx, busword_rx, busmimosis_rx : CTRLBUS_RX;
+ signal businp_tx, busword_tx, busmimosis_tx : CTRLBUS_TX;
signal ct_fifo_afull, ct_fifo_full, ct_fifo_empty : std_logic;
signal ct_fifo_read, ct_fifo_valid, ct_fifo_nextvalid : std_logic;
signal buffer_din, buffer_dout : std_logic_vector(31 downto 0);
signal buffer_fill : std_logic_vector(13 downto 0);
- type state_t is (IDLE,START_COPY, COPY,FINISH,DONE);
+ type state_t is (IDLE,START_COPY, START_COPY2, COPY,FINISH,DONE);
signal state : state_t;
signal word_count : integer range 0 to 8191;
+ signal frame_number : std_logic_vector(31 downto 0);
+ signal frame_length : std_logic_vector(15 downto 0);
+ signal count_words : unsigned(15 downto 0);
+ signal count_header : unsigned(31 downto 0);
+ signal count_trailer : unsigned(31 downto 0);
+ signal count_fe : unsigned(31 downto 0);
+ signal count_ff : unsigned(31 downto 0);
+ signal count_oof : unsigned(31 downto 0);
+ signal buffer_blocked : std_logic;
+ type frame_state_t is (IDLE,HDR1,WRITING);
+ signal frame_state : frame_state_t;
+
begin
----------------------------------------------------------------------
-- Frame Copy
----------------------------------------------------------------------
- buffer_write <= ct_fifo_valid;
- buffer_din <= ct_fifo_data_out;
+
+PROC_FRAMES : process begin
+ wait until rising_edge(CLK_SYS);
+ buffer_write <= '0';
+ buffer_din <= ct_fifo_data_out;
+
+ if ct_fifo_valid = '1' then
+ count_words <= count_words + 1;
+ end if;
+
+ if ct_fifo_valid = '1' and ct_fifo_data_out(31 downto 24) = x"FE" then
+ count_fe <= count_fe + 1;
+ end if;
+
+ if ct_fifo_valid = '1' and ct_fifo_data_out(31 downto 24) = x"FF" then
+ count_ff <= count_ff + 1;
+ end if;
+
+ if ct_fifo_valid = '1' and ct_fifo_data_out(31 downto 24) < x"FC" and frame_state = IDLE then
+ count_oof <= count_oof + 1;
+ end if;
+
+ case frame_state is
+ when IDLE =>
+ count_words <= (others => '0');
+ if ct_fifo_valid = '1' and ct_fifo_data_out(31 downto 24) = x"FE" then
+ frame_state <= HDR1;
+ frame_number(15 downto 0) <= ct_fifo_data_out(7 downto 0) & ct_fifo_data_out(23 downto 16);
+ buffer_write <= not buffer_full;
+ buffer_blocked <= buffer_full;
+ count_header <= count_header + 1;
+ end if;
+ when HDR1 =>
+ if ct_fifo_valid = '1' then
+ frame_state <= WRITING;
+ frame_number(31 downto 16) <= ct_fifo_data_out(7 downto 0) & ct_fifo_data_out(23 downto 16);
+ buffer_write <= not buffer_blocked;
+ end if;
+
+ when WRITING =>
+ buffer_write <= ct_fifo_valid and not buffer_blocked;
+ if ct_fifo_valid = '1' and ct_fifo_data_out(31 downto 24) = x"FF" then
+ frame_state <= IDLE;
+ frame_length <= std_logic_vector(count_words);
+ count_trailer <= count_trailer + 1;
+ end if;
+ if ct_fifo_valid = '1' and ct_fifo_data_out(31 downto 24) = x"FE" and count_words >= x"0004" then
+ frame_state <= HDR1;
+ count_header <= count_header + 1;
+ frame_number(15 downto 0) <= ct_fifo_data_out(7 downto 0) & ct_fifo_data_out(23 downto 16);
+ buffer_write <= not buffer_full;
+ buffer_blocked <= buffer_full;
+ end if;
+ end case;
+
+ end process;
+
+
----------------------------------------------------------------------
-- Main Fifo
WrEn => buffer_write,
RdEn => buffer_read,
Reset => RESET,
- AmFullThresh => "1111111110000",
+ AmFullThresh => "1000000000000",
Q(31 downto 0) => buffer_dout,
WCNT => buffer_fill,
Empty => buffer_empty,
---------------------------------------------------------------------------
PROC_RDO : process begin
wait until rising_edge(CLK_SYS);
- if state = IDLE and buffer_full = '1' then
- buffer_read <= '1';
- else
+-- if state = IDLE and buffer_full = '1' then
+-- buffer_read <= '1';
+-- else
buffer_read <= '0';
- end if;
+-- end if;
BUSRDO_TX.busy_release <= '0';
if BUSRDO_RX.invalid_trg = '1' then
state <= FINISH;
end if;
+
when START_COPY =>
- state <= COPY;
+ state <= START_COPY2;
buffer_read <= '1';
word_count <= word_count + 1;
+ when START_COPY2 =>
+ state <= COPY;
+ buffer_read <= '1';
+ word_count <= word_count + 1;
+
when COPY =>
if word_count = WORD_LIMIT or buffer_valid = '0' then
THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
generic map(
- PORT_NUMBER => 2,
+ PORT_NUMBER => 3,
PORT_ADDRESSES => (0 => x"0000", 1 => x"0100", 2 => x"0200", others => x"0000"),
- PORT_ADDR_MASK => (0 => 5, 1 => 5, 2 => 1, others => 0),
+ PORT_ADDR_MASK => (0 => 5, 1 => 5, 2 => 4, others => 0),
PORT_MASK_ENABLE => 1
)
port map(
BUS_RX(0) => businp_rx,
BUS_RX(1) => busword_rx,
+ BUS_RX(2) => busmimosis_rx,
BUS_TX(0) => businp_tx,
BUS_TX(1) => busword_tx,
+ BUS_TX(2) => busmimosis_tx,
STAT_DEBUG => open
);
-
+PROC_REGS : process
+ variable addr : integer range 0 to 7;
+begin
+ wait until rising_edge(CLK_SYS);
+ busmimosis_tx.ack <= '0';
+ busmimosis_tx.unknown <= '0';
+ busmimosis_tx.nack <= '0';
+ busmimosis_tx.data <= (others => '0');
+
+ if busmimosis_rx.write = '1' then
+ busmimosis_tx.unknown <= '1';
+ elsif busmimosis_rx.read = '1' then
+ busmimosis_tx.ack <= '1';
+ if busmimosis_rx.addr = x"0000" then
+ busmimosis_tx.data <= std_logic_vector(count_header);
+ elsif busmimosis_rx.addr = x"0001" then
+ busmimosis_tx.data <= std_logic_vector(count_trailer);
+ elsif busmimosis_rx.addr = x"0002" then
+ busmimosis_tx.data <= x"0000" & frame_length;
+ elsif busmimosis_rx.addr = x"0003" then
+ busmimosis_tx.data <= frame_number;
+ elsif busmimosis_rx.addr = x"0004" then
+ busmimosis_tx.data <= x"0000" & std_logic_vector(count_words);
+ elsif busmimosis_rx.addr = x"0005" then
+ busmimosis_tx.data <= x"0000" & "00" & buffer_fill;
+ elsif busmimosis_rx.addr = x"0006" then
+ busmimosis_tx.data <= std_logic_vector(count_fe);
+ elsif busmimosis_rx.addr = x"0007" then
+ busmimosis_tx.data <= std_logic_vector(count_ff);
+ elsif busmimosis_rx.addr = x"0008" then
+ busmimosis_tx.data <= std_logic_vector(count_oof);
+ else
+ busmimosis_tx.ack <= '0';
+ busmimosis_tx.unknown <= '1';
+
+ end if;
+ end if;
+end process;
end architecture;
jspc29 / trb5sc.git / commitdiff