A_RDO_OUT : out std_logic; --ready FROM first motherboard
ROC1_WRITTEN_OUT : out std_logic;
- DATA_TYPE_SELECT_IN : in std_logic_vector(3 downto 0);
+ DATA_TYPE_SELECT_IN : in std_logic_vector(19 downto 0);
DIRECTION_DATA_LINE_OUT : out std_logic_vector(3 downto 0);
MOTHERBOARD_TYPE_IN : in std_logic_vector(3 downto 0);
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- tdc_readout_and_trb_interface
-------------------------------------------------------------------------------
- DATA_TYPE_SELECT_IN : in std_logic_vector(3 downto 0);
+ DATA_TYPE_SELECT_IN : in std_logic_vector(19 downto 0);
TOKEN_TO_TRB_OUT : out std_logic;
REINIT_ROC1_IN : in std_logic;
REINIT_ROC1_OUT : out std_logic;
D : out std_logic_vector(6 downto 0);
A_RDO_OUT : out std_logic;
ROC1_WRITTEN_OUT : out std_logic;
- DATA_TYPE_SELECT_IN : in std_logic_vector(3 downto 0);
+ DATA_TYPE_SELECT_IN : in std_logic_vector(19 downto 0);
DIRECTION_DATA_LINE_OUT : out std_logic_vector(3 downto 0);
MOTHERBOARD_TYPE_IN : in std_logic_vector(3 downto 0);
ACKNOWLEDGE_TRB_INTERFACE_IN : in std_logic_vector(3 downto 0);
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
--- library UNISIM;
--- use UNISIM.VComponents.all;
+use ieee.numeric_std.all;
entity tdc_readout is
port(
INIT_TDC_READOUT_IN : in std_logic_vector(3 downto 0); --from common stop generator
--x"0"debug, x"1" 2 hit in one word, x"2" test data,
- DATA_TYPE_SELECT_IN : in std_logic_vector(3 downto 0);
+ DATA_TYPE_SELECT_IN : in std_logic_vector(19 downto 0);
DEBUG_REGISTER_OUT : out std_logic_vector(3 downto 0));
end tdc_readout;
signal clear_counter_check_hit,up_counter_check_hit : STD_LOGIC;
signal counter_check_hit : std_logic_vector(3 downto 0);
signal reg_data_type_select_in : std_logic_vector(3 downto 0);
+signal reg_test_data_maximun_word_number : std_logic_vector(15 downto 0);
signal clear_counter_check_hit_calibration,up_counter_check_hit_calibration : STD_LOGIC;
signal counter_check_hit_calibration : std_logic_vector(3 downto 0);
signal clear_saved_data_new_format_hit_0_1_cal : std_logic;
if (rising_edge(CLK)) then
if (RESET = '1') then
reg_data_type_select_in <= (others => '0');
+ reg_test_data_maximun_word_number <= (others => '0');
else
- reg_data_type_select_in <= DATA_TYPE_SELECT_IN;
+ reg_data_type_select_in <= DATA_TYPE_SELECT_IN(3 downto 0);
+ reg_test_data_maximun_word_number <= DATA_TYPE_SELECT_IN(19 downto 4);
end if;
end if;
end process;
-- purpose: built test data and send to fifo
-------------------------------------------------------------------------------
process(current_state_test_data, INIT_TDC_READOUT_IN, counter_test_data)
-
+
+-- variable index : integer range 0 to conv_integer(reg_test_data_maximun_word_number);
+--std_logic_vector (19 downto 0);
+
begin
next_data_valid_out_test_data <= '0';
next_debug_register_test_data <= (others => '0');
next_token_tdc_readout_i_test_data <= (others => '0');
---send constant pattern
+
next_data_bus_out_test_data(35 downto 32) <= x"1";
- next_data_bus_out_test_data(31 downto 0) <= x"babecafe";
+ next_data_bus_out_test_data(31 downto 16) <= x"babe";
+ next_data_bus_out_test_data(15 downto 0) <= (others => '0');
up_counter_test_data <= '0';
clear_counter_test_data <= '0';
when idle_state_test_data =>
next_debug_register_test_data <= x"0";
+ next_data_bus_out_test_data(15 downto 0) <= std_logic_vector(TO_UNSIGNED(conv_integer(counter_test_data), reg_test_data_maximun_word_number'Length));
if (INIT_TDC_READOUT_IN = x"1") then
next_state_test_data <= send_data_with_valid_test_data;
else
next_debug_register_test_data <= x"1";
up_counter_test_data <= '1';
next_data_valid_out_test_data <= '1';
+ next_data_bus_out_test_data(15 downto 0) <= std_logic_vector(TO_UNSIGNED(conv_integer(counter_test_data), reg_test_data_maximun_word_number'Length));
next_state_test_data <= send_data_with_valid_next_test_data;
-
when send_data_with_valid_next_test_data =>
next_debug_register_test_data <= x"2";
next_data_valid_out_test_data <= '0';
+ next_data_bus_out_test_data(15 downto 0) <= std_logic_vector(TO_UNSIGNED(conv_integer(counter_test_data), reg_test_data_maximun_word_number'Length));
next_state_test_data <= check_dataword_number_test_data;
when check_dataword_number_test_data =>
next_debug_register_test_data <= x"3";
- next_data_valid_out_test_data <= '0';
- if (conv_integer(counter_test_data) >= 10) then
- next_state_test_data <= send_token_state_test_data;
+ next_data_valid_out_test_data <= '0';
+ next_data_bus_out_test_data(15 downto 0) <= std_logic_vector(TO_UNSIGNED(conv_integer(counter_test_data), reg_test_data_maximun_word_number'Length));
+ if (conv_integer(counter_test_data) >= reg_test_data_maximun_word_number) then
+ next_state_test_data <= send_token_state_test_data;
else
next_state_test_data <= send_data_with_valid_test_data;
end if;
--- send token here it is simulated after a constant number of dataword
+--send token here it is simulated after a constant number of dataword
when send_token_state_test_data =>
next_debug_register_test_data <= x"4";
next_token_tdc_readout_i_test_data <= x"1";
clear_counter_test_data <= '1';
+ next_data_bus_out_test_data(15 downto 0) <= std_logic_vector(TO_UNSIGNED(conv_integer(counter_test_data), reg_test_data_maximun_word_number'Length));
next_state_test_data <= idle_state_test_data;
when others =>
end if;
end if;
end process;
+
-------------------------------------------------------------------------------
-- TEST DATA: END
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- tdc_readout_and_trb_interface
-------------------------------------------------------------------------------
- DATA_TYPE_SELECT_IN : in std_logic_vector(3 downto 0);
+ DATA_TYPE_SELECT_IN : in std_logic_vector(19 downto 0);
TOKEN_TO_TRB_OUT : out std_logic;
REINIT_ROC1_IN : in std_logic;
REINIT_ROC1_OUT : out std_logic;
DATA_VALID_OUT : out std_logic;
FULL_FIFO_IN : in std_logic;
INIT_TDC_READOUT_IN : in std_logic_vector(3 downto 0);
- DATA_TYPE_SELECT_IN : in std_logic_vector(3 downto 0); --x"0"debug,
+ DATA_TYPE_SELECT_IN : in std_logic_vector(19 downto 0); --x"0"debug,
--x"1" 2 hit in one word
DEBUG_REGISTER_OUT : out std_logic_vector(3 downto 0));
end component;
read_fee_data_fifo <= (IPU_READ_IN and reg_read_fee_data_fifo_i) or
pulse_not_empty_flag_fee_data_fifo_i;
--- push_read_fee_data_i or push_read_fee_data_1_i;
--------------------------------------------------------------------------------
+
HEADER_FIFO: fifo_fall_through_512depth_52width_reg_out
port map (
Data => reg_first_header,
Full => full_flag_header_data_fifo_i,
AlmostEmpty => almost_empty_flag_header_data_fifo_i,
AlmostFull => almost_full_flag_header_data_fifo_i);
+
-------------------------------------------------------------------------------
-- reg_ipu_read is setted by TRBNET,
-- reg_read_header_fifo_i is defined by the state machine
end if;
end process a_add_data_counter;
-
-
--register input
process (CLK, RESET)
begin
else
next_state <= busy_header_state;
end if;
-
when others =>
next_debug_register_fsm_header <= x"00";
if RESET = '1' then
current_state_fsm_multiplexer <= idle_state_fsm_multiplexer;
reg_debug_register_fsm_multiplexer <= (others => '0');
- --next_data_to_trb_net <= (others => '0');
reg_read_fee_data_fifo_i <= '0';
reg_read_header_fifo_i <= '0';
reg_lvl1_error_pattern <= (others => '0');
reg_ipu_data_ready <= '0';
reg_ipu_finished <= '0';
reg_pseudo_token <= '0';
- -- reg_ipu_length <= (others => '0');
else
current_state_fsm_multiplexer <= next_state_fsm_multiplexer;
reg_debug_register_fsm_multiplexer <= next_debug_register_fsm_multiplexer;
- -- reg_data_to_trb_net <= next_data_to_trb_net;
reg_read_fee_data_fifo_i <= next_read_fee_data_fifo_i;
reg_read_header_fifo_i <= next_read_header_fifo_i;
reg_lvl1_error_pattern <= next_lvl1_error_pattern;
reg_ipu_data_ready <= next_ipu_data_ready;
reg_ipu_finished <= next_ipu_finished;
reg_pseudo_token <= next_pseudo_token;
- -- reg_ipu_length <= next_ipu_length;
end if;
end if;
end process;
next_ipu_data <= (others => '0');
next_ipu_data_ready <= '0';
next_ipu_finished <= '0';
- -- next_ipu_length <= (others => '0');
clear_counter_word_read_from_trbnet <= '0';
push_read_fee_data_1_i <= '0';
next_pseudo_token <= '0';
--- push_read_fee_data_i <= '0';
--- push_read_header_data_i <= '0';
case current_state_fsm_multiplexer is
next_ipu_data_ready <= '0'; --trbnet cannot read
next_data_to_trb_net <= fee_data_fifo_out_i(31 downto 0);
next_state_fsm_multiplexer <= send_data_state_fsm_multiplexer;
-
+
-------------------------------------------------------------------------------
-- Connect fee_data_fifo to trbnet.
-- I leave connected till the flag change to next event
--number of dataword are counter in differet way if test data is enabled
-words_in_event_first_header <= words_in_event_test_data when (DATA_TYPE_SELECT_IN = x"2")
+words_in_event_first_header <= words_in_event_test_data when (DATA_TYPE_SELECT_IN(3 downto 0) = x"2")
else words_in_event;
--register header
end if;
end process;
-
DEBUG_REGISTER_0 <= x"0" & reg_debug_register_fsm_multiplexer(3 downto 0);
-------------------------------------------------------------------------------
signal direction_data_line_out_i : std_logic_vector(3 downto 0);
signal motherboard_type_in_i : std_logic_vector(3 downto 0);
signal pulse_begin_run_trigger_i : std_logic;
- signal data_type_select_in_i : std_logic_vector(3 downto 0);
+ signal data_type_select_in_i : std_logic_vector(19 downto 0);
-
signal datbus_data_out : std_logic_vector(31 downto 0);
signal datbus_addr_out : std_logic_vector(15 downto 0);
signal datbus_timeout_out : std_logic;
-
signal test_debug_i : std_logic_vector(7 downto 0);
signal counter_led : unsigned(31 downto 0);
signal reset_counter_led : std_logic;
-- 0xc0 0x0000 -> select verbose mode data
-- 0xc0 0x1000 -> select compact mode data
-- 0xc0 0x2000 -> select test data
-
+
PROC_GEN_TIMING : process(CLK_100)
begin
if rising_edge(CLK_100) then
motherboard_type_in_i <= REGIO_REGISTERS_OUT(7 downto 4);
cal_trigger_register_in_i <= x"000" & REGIO_REGISTERS_OUT(11 downto 8);
- data_type_select_in_i <= REGIO_REGISTERS_OUT(15 downto 12);
+ data_type_select_in_i <= REGIO_REGISTERS_OUT(31 downto 12);
end if;
end process;
jspc29 / mdcoep.git / commitdiff