Update documentation

diff --git a/docu/main.pdf b/docu/main.pdf
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diff --git a/docu/main.tex b/docu/main.tex
index bf5e44ce459d268aa357b55a7488412d5af52a38..a0f107bc119a7e1690f021546644b458e15db94a 100644 (file)
--- a/docu/main.tex
+++ b/docu/main.tex
@@ -200,10 +200,10 @@ When used with an FPGA, several signal processing modes are available, based on
 \item[8] like 0, input signals are stretched by adding 14 - 21 ns
 \item[9] like 1, input signals are stretched by adding 14 - 21 ns
 \item[A] like 2, input signals are stretched by adding 14 - 21 ns
-\item[B] not used
-\item[C] not used
+\item[B] output 0 is 'and', output 2 is 'or' of all not disabled inputs
+\item[C] like B, but with inverted inputs
 \item[D] not used
-\item[E] Basic pulser, 0,5 Hz - 66,5 MHz, pulslength in 7,5 nSec steps
+\item[E] Basic pulser, 0.5 Hz - 66.5 MHz, pulslength in 7.5 ns steps
 \item[F] like E, but inverted
 \end{description*}
 \begin{itemize*}
@@ -211,6 +211,22 @@ When used with an FPGA, several signal processing modes are available, based on
 \item All modes preserve the timing of the signal edges. Trailing edge is synchronous to clock in stretched and edge detect modes
 \end{itemize*}
 
+\subsubsection{Registers}
+
+\begin{tabularx}{\textwidth}{ c| c|l|X}
+Addr & Mode & Name & Description \\
+\hline
+0x00 & RO & Config & Setting of the on-board switch \\
+0x10 & RW & Disable & 4 Bit, disable each of the 4 inputs for 'and' and 'or' logic \\
+0x20 & RW & Pulser Period & Period of the pulser in clock cycles of 133 MHz \\
+0x21 & RW & Pulser Length & Length of the pulser signal in clock cycles of 133 MHz \\
+0x3n & R  & Counter & 4 registers with 24 Bit counters for each input channel \\
+0x30 & W  & Counter Reset & Writing to this register resets the input counters \\
+0x5X &    & Flash ROM & Access to Flash ROM. See Padiwa documentation for details \\
+0xee & RW & SED & Control and Status of the Soft Error Detection circuit (not in all designs) \\
+\end{tabularx}
+
+
 \subsection{Pulse Generator}
 
 In pulse generator mode, the FPGA is loaded with a design that can produce up to 8 different pulser signals, available on both AddOn connectors.
@@ -234,7 +250,7 @@ In pulse generator mode, the FPGA is loaded with a design that can produce up to
 \end{itemize*}
 
 
-\subsection{Registers}
+\subsubsection{Registers}
 \begin{description*}
 \item[0x00 - Config] Bit 0: Enable streaming read-out. Bit 7-4 read status of config switch
 \item[0x01 - Input] 8 Bit of current status of the inputs
@@ -242,7 +258,7 @@ In pulse generator mode, the FPGA is loaded with a design that can produce up to
 \item[0xd0 - Data] Read TDC data when not in streaming mode
 \end{description*}
 
-\subsection{Data Format}
+\subsubsection{Data Format}
 \begin{description*}
 \item[Bit 0-2] Fine time (8 bins)
 \item[Bit 3] fine time decoding error
@@ -255,75 +271,33 @@ In pulse generator mode, the FPGA is loaded with a design that can produce up to
 
 
 \section{Operation}
-The FPGA based versions of the Logic Box can be controlled over a RS232 interface. Settings can be loaded from and stored to flashmemory.
-
-\subsection{Control over RS232}
-The Logic Box can be controlled over a terminal program. Settings may be changed and also saved or loaded. The generell structure of RS232 commands is shown in Table \ref{tabRS232Writecommand} and \ref{tabRS232ReadCommand}. If a Read-Command is send the reply is formed as follows: RDDDDDDDD (wherein D..D is the 32-bit data consisting of 8 Hexnumbers). Table \ref{tabRS232LoadSaveCommands} shows the commands for saving and loading settings.
-
-\begin{table}[h]
-\begin{tabular}{ l| l}
-  \multicolumn{2}{l}{\textbf{W-XX-DDDD-DDDD} (actual commands without hyphens)} \\   \hline
-Designator & Command/Data\\ \hline
-XX & Registeradress consisting of 2 Hexnumbers\\
-D..D & 32-bit data consisting of 8 Hexnumbers\\
-\end{tabular}
-  \caption{RS232 Write Command}
- \label{tabRS232Writecommand}
-\end{table}
-
-\begin{table}[h]
-\begin{tabular}{ l| l}
-  \multicolumn{2}{l}{\textbf{R-XX} (actual commands without hyphens)} \\   \hline
-Designator & Command/Data\\ \hline
-XX & Registeradress consisting of 2 Hexnumbers\\
-\end{tabular}
-  \caption{RS232 Read Command}
- \label{tabRS232ReadCommand}
-\end{table}
-
-\begin{table}[h]
-\begin{tabular}{ l| l}
-
-Description & Command\\ \hline
-Load & W0200000000\\
-Save & W02FFFFFFFF\\
-\end{tabular}
-  \caption{RS232 Load/Save Commands}
- \label{tabRS232LoadSaveCommands}
-\end{table}
+The FPGA based versions of the Logic Box can be controlled over USB like a serial device. Settings can be loaded from and stored to the built-in Flash.
 
+\subsection{Commands}
+In the common daqtools.git repository a tool (tools/logicbox.pl) to read, write and program the Logicbox can be found. 
 
+The general structure of commands is as follows. All addresses and data are given in hex.\\
 
-
-
-\subsection{Level Converter}
-
-\subsection{Logic Box}
-As already mentioned different modes can be selected by using the on-board switch. Furthermore the pulswidth and frequency of the basic pulser can be adjusted over RS232. Table \ref{tabRS232BasicPulserCommands} shows the associated commands. Here D..D is the 28-bit or 7-digit Hexnumber that defines the pulslength/periodlength. -I- can be an arbitrary number since it will be ignored. The puls- and periodlength are adjusted as multiples of approximately 7,5 nSec.
-
-\begin{table}[h]
-\begin{tabular}{ l| l}
-
-Description & Command (actual commands without hyphens)\\ \hline
-Adjust periodlength & W20-I-DDD-DDDD\\
-Read periodlength &  R20\\
-Adjust pulslength & W21-I-DDD-DDDD\\
-Read pulslength & R21\\
+\begin{tabular}{ l| l|l}
+Write & WXXDDDDDDDD & XX: register address, D: 32 Bit data word \\
+Read  & RXX         & XX: register address \\
+Answer & RDDDDDDDD  & D: 32 Bit data word \\
 \end{tabular}
-  \caption{RS232 Basic Pulser Commands}
- \label{tabRS232BasicPulserCommands}
-\end{table}
 
+\subsection{FPGA Flash programming}
+The FPGA design can be changed via USB. The tool logicbox.pl is available from the daqtools repository. Please replace /dev/Logicbox with the appropriate device name.
 
-\subsection{Pulse Generator}
-
-\subsection{TDC}
+\begin{description}
+\item[Convert jed to dump]  \verb!./jed_to_dump.pl filename.jed!
+\item[Enable Flash]  \verb!./logicbox.pl /dev/Logicbox writereg 0x50 0x8000!
+\item[Enable Configuration Flash] \verb!./logicbox.pl /dev/Logicbox writereg 0x5c 0x1!
+\item[Program]  \verb!./logicbox.pl /dev/Logicbox writecfg filename.dump!
+\item[Read back] \verb!./logicbox.pl /dev/Logicbox dumpcfg  > readback.dump!
+\item[Verify]  \verb!diff filename.dump readback.dump!
+\item[Reboot] unplug the device to allow the FPGA to reload its configuration
+\end{description}
 
-% \cleardoublepage
-% \begin{appendices}
-% \end{appendices}
-% \cleardoublepage
-% \bibliography{biblio}
+Verify will typically result in few lines difference at the very end, but not more. If more errors are detected, make sure to reprogram the Flash before you cut the power - otherwise you'll need a dedicated progamming cable to revive the FPGA.
 \end{document}
 
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