trbnet fifos are generated for ecp5

diff --git a/lattice/ecp5/FIFO/FIFO.sbx b/lattice/ecp5/FIFO/FIFO.sbx
new file mode 100644 (file)
index 0000000..beca0a3
--- /dev/null
+++ b/lattice/ecp5/FIFO/FIFO.sbx
@@ -0,0 +1,2011 @@
+<!DOCTYPE FIFO>
+<lattice:project>
+    <spirit:component>
+        <spirit:vendor>LATTICE</spirit:vendor>
+        <spirit:library>LOCAL</spirit:library>
+        <spirit:name>FIFO</spirit:name>
+        <spirit:version>1.0</spirit:version>
+        <spirit:fileSets>
+            <spirit:fileset>
+                <spirit:name>Diamond_Synthesis</spirit:name>
+                <spirit:group>synthesis</spirit:group>
+            </spirit:fileset>
+            <spirit:fileset>
+                <spirit:name>Diamond_Simulation</spirit:name>
+                <spirit:group>simulation</spirit:group>
+            </spirit:fileset>
+        </spirit:fileSets>
+        <spirit:componentGenerators/>
+        <spirit:model>
+            <spirit:views/>
+            <spirit:ports>
+                <spirit:port>
+                    <spirit:name>FIFO_36x128_OutReg_Clock</spirit:name>
+                    <spirit:displayName>FIFO_36x128_OutReg_Clock</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">FIFO_36x128_OutReg.Clock</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>FIFO_36x128_OutReg_Empty</spirit:name>
+                    <spirit:displayName>FIFO_36x128_OutReg_Empty</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">FIFO_36x128_OutReg.Empty</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>FIFO_36x128_OutReg_Full</spirit:name>
+                    <spirit:displayName>FIFO_36x128_OutReg_Full</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">FIFO_36x128_OutReg.Full</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>FIFO_36x128_OutReg_RdEn</spirit:name>
+                    <spirit:displayName>FIFO_36x128_OutReg_RdEn</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">FIFO_36x128_OutReg.RdEn</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>FIFO_36x128_OutReg_Reset</spirit:name>
+                    <spirit:displayName>FIFO_36x128_OutReg_Reset</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">FIFO_36x128_OutReg.Reset</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>FIFO_36x128_OutReg_WrEn</spirit:name>
+                    <spirit:displayName>FIFO_36x128_OutReg_WrEn</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">FIFO_36x128_OutReg.WrEn</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>FIFO_DC_36x128_DynThr_OutReg_AlmostFull</spirit:name>
+                    <spirit:displayName>FIFO_DC_36x128_DynThr_OutReg_AlmostFull</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">FIFO_DC_36x128_DynThr_OutReg.AlmostFull</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>FIFO_DC_36x128_DynThr_OutReg_Empty</spirit:name>
+                    <spirit:displayName>FIFO_DC_36x128_DynThr_OutReg_Empty</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">FIFO_DC_36x128_DynThr_OutReg.Empty</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>FIFO_DC_36x128_DynThr_OutReg_Full</spirit:name>
+                    <spirit:displayName>FIFO_DC_36x128_DynThr_OutReg_Full</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">FIFO_DC_36x128_DynThr_OutReg.Full</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>FIFO_DC_36x128_DynThr_OutReg_RPReset</spirit:name>
+                    <spirit:displayName>FIFO_DC_36x128_DynThr_OutReg_RPReset</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">FIFO_DC_36x128_DynThr_OutReg.RPReset</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>FIFO_DC_36x128_DynThr_OutReg_RdClock</spirit:name>
+                    <spirit:displayName>FIFO_DC_36x128_DynThr_OutReg_RdClock</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">FIFO_DC_36x128_DynThr_OutReg.RdClock</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>FIFO_DC_36x128_DynThr_OutReg_RdEn</spirit:name>
+                    <spirit:displayName>FIFO_DC_36x128_DynThr_OutReg_RdEn</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">FIFO_DC_36x128_DynThr_OutReg.RdEn</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>FIFO_DC_36x128_DynThr_OutReg_Reset</spirit:name>
+                    <spirit:displayName>FIFO_DC_36x128_DynThr_OutReg_Reset</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">FIFO_DC_36x128_DynThr_OutReg.Reset</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>FIFO_DC_36x128_DynThr_OutReg_WrClock</spirit:name>
+                    <spirit:displayName>FIFO_DC_36x128_DynThr_OutReg_WrClock</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">FIFO_DC_36x128_DynThr_OutReg.WrClock</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>FIFO_DC_36x128_DynThr_OutReg_WrEn</spirit:name>
+                    <spirit:displayName>FIFO_DC_36x128_DynThr_OutReg_WrEn</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">FIFO_DC_36x128_DynThr_OutReg.WrEn</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>FIFO_36x128_OutReg_Data</spirit:name>
+                    <spirit:displayName>FIFO_36x128_OutReg_Data</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                        <spirit:vector>
+                            <spirit:left>35</spirit:left>
+                            <spirit:right>0</spirit:right>
+                        </spirit:vector>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">FIFO_36x128_OutReg.Data</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>FIFO_36x128_OutReg_Q</spirit:name>
+                    <spirit:displayName>FIFO_36x128_OutReg_Q</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                        <spirit:vector>
+                            <spirit:left>35</spirit:left>
+                            <spirit:right>0</spirit:right>
+                        </spirit:vector>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">FIFO_36x128_OutReg.Q</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>FIFO_DC_36x128_DynThr_OutReg_AmFullThresh</spirit:name>
+                    <spirit:displayName>FIFO_DC_36x128_DynThr_OutReg_AmFullThresh</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                        <spirit:vector>
+                            <spirit:left>6</spirit:left>
+                            <spirit:right>0</spirit:right>
+                        </spirit:vector>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">FIFO_DC_36x128_DynThr_OutReg.AmFullThresh</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>FIFO_DC_36x128_DynThr_OutReg_Data</spirit:name>
+                    <spirit:displayName>FIFO_DC_36x128_DynThr_OutReg_Data</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                        <spirit:vector>
+                            <spirit:left>35</spirit:left>
+                            <spirit:right>0</spirit:right>
+                        </spirit:vector>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">FIFO_DC_36x128_DynThr_OutReg.Data</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>FIFO_DC_36x128_DynThr_OutReg_Q</spirit:name>
+                    <spirit:displayName>FIFO_DC_36x128_DynThr_OutReg_Q</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                        <spirit:vector>
+                            <spirit:left>35</spirit:left>
+                            <spirit:right>0</spirit:right>
+                        </spirit:vector>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">FIFO_DC_36x128_DynThr_OutReg.Q</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+            </spirit:ports>
+        </spirit:model>
+        <spirit:vendorExtensions>
+            <lattice:device>LFE5UM-85F-8MG285C</lattice:device>
+            <lattice:synthesis>synplify</lattice:synthesis>
+            <lattice:date>2015-03-17.15:26:04</lattice:date>
+            <lattice:modified>2015-03-17.15:29:04</lattice:modified>
+            <lattice:diamond>3.4.0.80</lattice:diamond>
+            <lattice:language>VHDL</lattice:language>
+            <lattice:attributes>
+                <lattice:attribute lattice:name="AddComponent">true</lattice:attribute>
+                <lattice:attribute lattice:name="Change4to5">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeConnect">true</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangePack">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangePart">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute>
+                <lattice:attribute lattice:name="Migrate">false</lattice:attribute>
+                <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute>
+            </lattice:attributes>
+            <lattice:elements/>
+            <lattice:lpc/>
+            <lattice:groups/>
+        </spirit:vendorExtensions>
+    </spirit:component>
+    <spirit:design>
+        <spirit:vendor>LATTICE</spirit:vendor>
+        <spirit:library>LOCAL</spirit:library>
+        <spirit:name>FIFO</spirit:name>
+        <spirit:version>1.0</spirit:version>
+        <spirit:componentInstances>
+            <spirit:componentInstance>
+                <spirit:instanceName>FIFO_36x128_OutReg</spirit:instanceName>
+                <spirit:componentRef>
+                    <spirit:vendor>Lattice Semiconductor Corporation</spirit:vendor>
+                    <spirit:library>LEGACY</spirit:library>
+                    <spirit:name>FIFO</spirit:name>
+                    <spirit:version>5.0</spirit:version>
+                    <spirit:fileSets>
+                        <spirit:fileset>
+                            <spirit:name>Diamond_Simulation</spirit:name>
+                            <spirit:group>simulation</spirit:group>
+                            <spirit:file>
+                                <spirit:name>./FIFO_36x128_OutReg/FIFO_36x128_OutReg.vhd</spirit:name>
+                                <spirit:fileType>vhdlSource</spirit:fileType>
+                            </spirit:file>
+                        </spirit:fileset>
+                        <spirit:fileset>
+                            <spirit:name>Diamond_Synthesis</spirit:name>
+                            <spirit:group>synthesis</spirit:group>
+                            <spirit:file>
+                                <spirit:name>./FIFO_36x128_OutReg/FIFO_36x128_OutReg.vhd</spirit:name>
+                                <spirit:fileType>vhdlSource</spirit:fileType>
+                            </spirit:file>
+                        </spirit:fileset>
+                    </spirit:fileSets>
+                    <spirit:componentGenerators>
+                        <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                            <spirit:name>Configuration</spirit:name>
+                            <spirit:apiType>none</spirit:apiType>
+                            <spirit:generatorExe>${sbp_path}/${instance}/generate_core.tcl</spirit:generatorExe>
+                            <spirit:group>CONFIG</spirit:group>
+                        </spirit:componentGenerator>
+                        <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                            <spirit:name>CreateNGD</spirit:name>
+                            <spirit:apiType>none</spirit:apiType>
+                            <spirit:generatorExe>${sbp_path}/${instance}/generate_ngd.tcl</spirit:generatorExe>
+                            <spirit:group>CONFIG</spirit:group>
+                        </spirit:componentGenerator>
+                    </spirit:componentGenerators>
+                    <spirit:model>
+                        <spirit:views/>
+                        <spirit:ports>
+                            <spirit:port>
+                                <spirit:name>Clock</spirit:name>
+                                <spirit:displayName>Clock</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>Empty</spirit:name>
+                                <spirit:displayName>Empty</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>Full</spirit:name>
+                                <spirit:displayName>Full</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>RdEn</spirit:name>
+                                <spirit:displayName>RdEn</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>Reset</spirit:name>
+                                <spirit:displayName>Reset</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>WrEn</spirit:name>
+                                <spirit:displayName>WrEn</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>Data</spirit:name>
+                                <spirit:displayName>Data</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>35</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>Q</spirit:name>
+                                <spirit:displayName>Q</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>35</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                        </spirit:ports>
+                    </spirit:model>
+                    <spirit:vendorExtensions>
+                        <lattice:synthesis>synplify</lattice:synthesis>
+                        <lattice:modified>2015-03-17.15:29:04</lattice:modified>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="AddComponent">false</lattice:attribute>
+                            <lattice:attribute lattice:name="BBox">false</lattice:attribute>
+                            <lattice:attribute lattice:name="Change4to5">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeConnect">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangePack">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangePart">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute>
+                            <lattice:attribute lattice:name="CoreType">LPM</lattice:attribute>
+                            <lattice:attribute lattice:name="DCU_RXREFCLK">PRIMARY</lattice:attribute>
+                            <lattice:attribute lattice:name="DCU_TXREFCLK">PRIMARY</lattice:attribute>
+                            <lattice:attribute lattice:name="Migrate">false</lattice:attribute>
+                            <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute>
+                        </lattice:attributes>
+                        <lattice:elements/>
+                        <lattice:lpc>
+                            <lattice:lpcsection lattice:name="Device"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Family</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">ecp5um</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>OperatingCondition</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">COM</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Package</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">CSFBGA285</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PartName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F-8MG285C</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PartType</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>SpeedGrade</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Status</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">C</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcsection lattice:name="IP"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">FIFO</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreRevision</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">5.0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreStatus</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Demo</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreType</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">LPM</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Date</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">03/17/2015</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>ModuleName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">FIFO_36x128_OutReg</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>ParameterFileVersion</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1.0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>SourceFormat</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">vhdl</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Time</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">15:27:43</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>VendorName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Lattice Semiconductor Corporation</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcsection lattice:name="Parameters"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CtrlByRdEn</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Depth</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">128</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Destination</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Synplicity</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>EDIF</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>EmpFlg</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>EnECC</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>EnFWFT</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Expression</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">BusA(0 to 7)</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>FIFOImp</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">EBR Based</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>FullFlg</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>IO</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Order</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Big Endian [MSB:LSB]</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PeAssert</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">10</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PeDeassert</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">12</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PeMode</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Static - Dual Threshold</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PfAssert</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">508</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PfDeassert</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">506</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PfMode</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Static - Dual Threshold</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RDataCount</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Reset</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Sync</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Reset1</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Sync</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>VHDL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Verilog</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Width</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">36</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>regout</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcsection lattice:name="Command"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>cmd_line</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">-w -n FIFO_36x128_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 128 -width 36 -regout -no_enable -pe -1 -pf -1 -sync_reset</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                        </lattice:lpc>
+                        <lattice:groups/>
+                    </spirit:vendorExtensions>
+                </spirit:componentRef>
+            </spirit:componentInstance>
+            <spirit:componentInstance>
+                <spirit:instanceName>FIFO_DC_36x128_DynThr_OutReg</spirit:instanceName>
+                <spirit:componentRef>
+                    <spirit:vendor>Lattice Semiconductor Corporation</spirit:vendor>
+                    <spirit:library>LEGACY</spirit:library>
+                    <spirit:name>FIFO_DC</spirit:name>
+                    <spirit:version>5.7</spirit:version>
+                    <spirit:fileSets>
+                        <spirit:fileset>
+                            <spirit:name>Diamond_Simulation</spirit:name>
+                            <spirit:group>simulation</spirit:group>
+                            <spirit:file>
+                                <spirit:name>./FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.vhd</spirit:name>
+                                <spirit:fileType>vhdlSource</spirit:fileType>
+                            </spirit:file>
+                        </spirit:fileset>
+                        <spirit:fileset>
+                            <spirit:name>Diamond_Synthesis</spirit:name>
+                            <spirit:group>synthesis</spirit:group>
+                            <spirit:file>
+                                <spirit:name>./FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.vhd</spirit:name>
+                                <spirit:fileType>vhdlSource</spirit:fileType>
+                            </spirit:file>
+                        </spirit:fileset>
+                    </spirit:fileSets>
+                    <spirit:componentGenerators>
+                        <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                            <spirit:name>Configuration</spirit:name>
+                            <spirit:apiType>none</spirit:apiType>
+                            <spirit:generatorExe>${sbp_path}/${instance}/generate_core.tcl</spirit:generatorExe>
+                            <spirit:group>CONFIG</spirit:group>
+                        </spirit:componentGenerator>
+                        <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                            <spirit:name>CreateNGD</spirit:name>
+                            <spirit:apiType>none</spirit:apiType>
+                            <spirit:generatorExe>${sbp_path}/${instance}/generate_ngd.tcl</spirit:generatorExe>
+                            <spirit:group>CONFIG</spirit:group>
+                        </spirit:componentGenerator>
+                    </spirit:componentGenerators>
+                    <spirit:model>
+                        <spirit:views/>
+                        <spirit:ports>
+                            <spirit:port>
+                                <spirit:name>AlmostFull</spirit:name>
+                                <spirit:displayName>AlmostFull</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>Empty</spirit:name>
+                                <spirit:displayName>Empty</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>Full</spirit:name>
+                                <spirit:displayName>Full</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>RPReset</spirit:name>
+                                <spirit:displayName>RPReset</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>RdClock</spirit:name>
+                                <spirit:displayName>RdClock</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>RdEn</spirit:name>
+                                <spirit:displayName>RdEn</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>Reset</spirit:name>
+                                <spirit:displayName>Reset</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>WrClock</spirit:name>
+                                <spirit:displayName>WrClock</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>WrEn</spirit:name>
+                                <spirit:displayName>WrEn</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>AmFullThresh</spirit:name>
+                                <spirit:displayName>AmFullThresh</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>6</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>Data</spirit:name>
+                                <spirit:displayName>Data</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>35</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>Q</spirit:name>
+                                <spirit:displayName>Q</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>35</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                        </spirit:ports>
+                    </spirit:model>
+                    <spirit:vendorExtensions>
+                        <lattice:synthesis>synplify</lattice:synthesis>
+                        <lattice:modified>2015-03-17.15:29:04</lattice:modified>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="AddComponent">false</lattice:attribute>
+                            <lattice:attribute lattice:name="BBox">false</lattice:attribute>
+                            <lattice:attribute lattice:name="Change4to5">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeConnect">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangePack">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangePart">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute>
+                            <lattice:attribute lattice:name="CoreType">LPM</lattice:attribute>
+                            <lattice:attribute lattice:name="DCU_RXREFCLK">PRIMARY</lattice:attribute>
+                            <lattice:attribute lattice:name="DCU_TXREFCLK">PRIMARY</lattice:attribute>
+                            <lattice:attribute lattice:name="Migrate">false</lattice:attribute>
+                            <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute>
+                        </lattice:attributes>
+                        <lattice:elements/>
+                        <lattice:lpc>
+                            <lattice:lpcsection lattice:name="Device"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Family</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">ecp5um</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>OperatingCondition</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">COM</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Package</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">CSFBGA285</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PartName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F-8MG285C</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PartType</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>SpeedGrade</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Status</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">C</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcsection lattice:name="IP"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">FIFO_DC</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreRevision</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">5.7</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreStatus</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Demo</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreType</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">LPM</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Date</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">03/17/2015</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>ModuleName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">FIFO_DC_36x128_DynThr_OutReg</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>ParameterFileVersion</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1.0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>SourceFormat</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">vhdl</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Time</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">15:27:13</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>VendorName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Lattice Semiconductor Corporation</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcsection lattice:name="Parameters"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>ClockEn</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CtrlByRdEn</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Depth</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">128</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Destination</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Synplicity</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>EDIF</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>EmpFlg</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>EnECC</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Expression</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">BusA(0 to 7)</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>FIFOImp</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">EBR Based</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>FullFlg</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>IO</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Order</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Big Endian [MSB:LSB]</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PeAssert</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">10</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PeDeassert</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">12</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PeMode</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Static - Dual Threshold</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PfAssert</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">508</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PfDeassert</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">506</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PfMode</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Dynamic - Single Threshold</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RDataCount</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RDepth</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">128</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RWidth</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">36</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Reset</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Sync</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Reset1</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Sync</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>VHDL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Verilog</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>WDataCount</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Width</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">36</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>regout</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcsection lattice:name="Command"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>cmd_line</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">-w -n FIFO_DC_36x128_DynThr_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 128 -width 36 -rwidth 36 -regout -no_enable -sync_reset -pe -1 -pf 0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                        </lattice:lpc>
+                        <lattice:groups/>
+                    </spirit:vendorExtensions>
+                </spirit:componentRef>
+            </spirit:componentInstance>
+        </spirit:componentInstances>
+        <spirit:adHocConnections>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_36x128_OutReg_Clock</spirit:name>
+                <spirit:displayName>FIFO_36x128_OutReg_Clock</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="Clock" spirit:componentRef="FIFO_36x128_OutReg"/>
+                <spirit:externalPortReference spirit:portRef="FIFO_36x128_OutReg_Clock"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_36x128_OutReg_Empty</spirit:name>
+                <spirit:displayName>FIFO_36x128_OutReg_Empty</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="Empty" spirit:componentRef="FIFO_36x128_OutReg"/>
+                <spirit:externalPortReference spirit:portRef="FIFO_36x128_OutReg_Empty"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_36x128_OutReg_Full</spirit:name>
+                <spirit:displayName>FIFO_36x128_OutReg_Full</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="Full" spirit:componentRef="FIFO_36x128_OutReg"/>
+                <spirit:externalPortReference spirit:portRef="FIFO_36x128_OutReg_Full"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_36x128_OutReg_RdEn</spirit:name>
+                <spirit:displayName>FIFO_36x128_OutReg_RdEn</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="RdEn" spirit:componentRef="FIFO_36x128_OutReg"/>
+                <spirit:externalPortReference spirit:portRef="FIFO_36x128_OutReg_RdEn"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_36x128_OutReg_Reset</spirit:name>
+                <spirit:displayName>FIFO_36x128_OutReg_Reset</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="Reset" spirit:componentRef="FIFO_36x128_OutReg"/>
+                <spirit:externalPortReference spirit:portRef="FIFO_36x128_OutReg_Reset"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_36x128_OutReg_WrEn</spirit:name>
+                <spirit:displayName>FIFO_36x128_OutReg_WrEn</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="WrEn" spirit:componentRef="FIFO_36x128_OutReg"/>
+                <spirit:externalPortReference spirit:portRef="FIFO_36x128_OutReg_WrEn"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_DC_36x128_DynThr_OutReg_AlmostFull</spirit:name>
+                <spirit:displayName>FIFO_DC_36x128_DynThr_OutReg_AlmostFull</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="AlmostFull" spirit:componentRef="FIFO_DC_36x128_DynThr_OutReg"/>
+                <spirit:externalPortReference spirit:portRef="FIFO_DC_36x128_DynThr_OutReg_AlmostFull"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_DC_36x128_DynThr_OutReg_Empty</spirit:name>
+                <spirit:displayName>FIFO_DC_36x128_DynThr_OutReg_Empty</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="Empty" spirit:componentRef="FIFO_DC_36x128_DynThr_OutReg"/>
+                <spirit:externalPortReference spirit:portRef="FIFO_DC_36x128_DynThr_OutReg_Empty"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_DC_36x128_DynThr_OutReg_Full</spirit:name>
+                <spirit:displayName>FIFO_DC_36x128_DynThr_OutReg_Full</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="Full" spirit:componentRef="FIFO_DC_36x128_DynThr_OutReg"/>
+                <spirit:externalPortReference spirit:portRef="FIFO_DC_36x128_DynThr_OutReg_Full"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_DC_36x128_DynThr_OutReg_RPReset</spirit:name>
+                <spirit:displayName>FIFO_DC_36x128_DynThr_OutReg_RPReset</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="RPReset" spirit:componentRef="FIFO_DC_36x128_DynThr_OutReg"/>
+                <spirit:externalPortReference spirit:portRef="FIFO_DC_36x128_DynThr_OutReg_RPReset"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_DC_36x128_DynThr_OutReg_RdClock</spirit:name>
+                <spirit:displayName>FIFO_DC_36x128_DynThr_OutReg_RdClock</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="RdClock" spirit:componentRef="FIFO_DC_36x128_DynThr_OutReg"/>
+                <spirit:externalPortReference spirit:portRef="FIFO_DC_36x128_DynThr_OutReg_RdClock"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_DC_36x128_DynThr_OutReg_RdEn</spirit:name>
+                <spirit:displayName>FIFO_DC_36x128_DynThr_OutReg_RdEn</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="RdEn" spirit:componentRef="FIFO_DC_36x128_DynThr_OutReg"/>
+                <spirit:externalPortReference spirit:portRef="FIFO_DC_36x128_DynThr_OutReg_RdEn"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_DC_36x128_DynThr_OutReg_Reset</spirit:name>
+                <spirit:displayName>FIFO_DC_36x128_DynThr_OutReg_Reset</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="Reset" spirit:componentRef="FIFO_DC_36x128_DynThr_OutReg"/>
+                <spirit:externalPortReference spirit:portRef="FIFO_DC_36x128_DynThr_OutReg_Reset"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_DC_36x128_DynThr_OutReg_WrClock</spirit:name>
+                <spirit:displayName>FIFO_DC_36x128_DynThr_OutReg_WrClock</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="WrClock" spirit:componentRef="FIFO_DC_36x128_DynThr_OutReg"/>
+                <spirit:externalPortReference spirit:portRef="FIFO_DC_36x128_DynThr_OutReg_WrClock"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_DC_36x128_DynThr_OutReg_WrEn</spirit:name>
+                <spirit:displayName>FIFO_DC_36x128_DynThr_OutReg_WrEn</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="WrEn" spirit:componentRef="FIFO_DC_36x128_DynThr_OutReg"/>
+                <spirit:externalPortReference spirit:portRef="FIFO_DC_36x128_DynThr_OutReg_WrEn"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_36x128_OutReg_Data</spirit:name>
+                <spirit:displayName>FIFO_36x128_OutReg_Data</spirit:displayName>
+                <spirit:internalPortReference spirit:right="0" spirit:portRef="Data" spirit:componentRef="FIFO_36x128_OutReg" spirit:left="35"/>
+                <spirit:externalPortReference spirit:right="0" spirit:portRef="FIFO_36x128_OutReg_Data" spirit:left="35"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_36x128_OutReg_Data[0]</spirit:name>
+                <spirit:displayName>FIFO_36x128_OutReg_Data[0]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="FIFO_36x128_OutReg_Data[0]"/>
+                <spirit:internalPortReference spirit:portRef="Data[0]" spirit:componentRef="FIFO_36x128_OutReg"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_36x128_OutReg_Data[10]</spirit:name>
+                <spirit:displayName>FIFO_36x128_OutReg_Data[10]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="FIFO_36x128_OutReg_Data[10]"/>
+                <spirit:internalPortReference spirit:portRef="Data[10]" spirit:componentRef="FIFO_36x128_OutReg"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_36x128_OutReg_Data[11]</spirit:name>
+                <spirit:displayName>FIFO_36x128_OutReg_Data[11]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="FIFO_36x128_OutReg_Data[11]"/>
+                <spirit:internalPortReference spirit:portRef="Data[11]" spirit:componentRef="FIFO_36x128_OutReg"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_36x128_OutReg_Data[12]</spirit:name>
+                <spirit:displayName>FIFO_36x128_OutReg_Data[12]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="FIFO_36x128_OutReg_Data[12]"/>
+                <spirit:internalPortReference spirit:portRef="Data[12]" spirit:componentRef="FIFO_36x128_OutReg"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_36x128_OutReg_Data[13]</spirit:name>
+                <spirit:displayName>FIFO_36x128_OutReg_Data[13]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="FIFO_36x128_OutReg_Data[13]"/>
+                <spirit:internalPortReference spirit:portRef="Data[13]" spirit:componentRef="FIFO_36x128_OutReg"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_36x128_OutReg_Data[14]</spirit:name>
+                <spirit:displayName>FIFO_36x128_OutReg_Data[14]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="FIFO_36x128_OutReg_Data[14]"/>
+                <spirit:internalPortReference spirit:portRef="Data[14]" spirit:componentRef="FIFO_36x128_OutReg"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_36x128_OutReg_Data[15]</spirit:name>
+                <spirit:displayName>FIFO_36x128_OutReg_Data[15]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="FIFO_36x128_OutReg_Data[15]"/>
+                <spirit:internalPortReference spirit:portRef="Data[15]" spirit:componentRef="FIFO_36x128_OutReg"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_36x128_OutReg_Data[16]</spirit:name>
+                <spirit:displayName>FIFO_36x128_OutReg_Data[16]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="FIFO_36x128_OutReg_Data[16]"/>
+                <spirit:internalPortReference spirit:portRef="Data[16]" spirit:componentRef="FIFO_36x128_OutReg"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_36x128_OutReg_Data[17]</spirit:name>
+                <spirit:displayName>FIFO_36x128_OutReg_Data[17]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="FIFO_36x128_OutReg_Data[17]"/>
+                <spirit:internalPortReference spirit:portRef="Data[17]" spirit:componentRef="FIFO_36x128_OutReg"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_36x128_OutReg_Data[18]</spirit:name>
+                <spirit:displayName>FIFO_36x128_OutReg_Data[18]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="FIFO_36x128_OutReg_Data[18]"/>
+                <spirit:internalPortReference spirit:portRef="Data[18]" spirit:componentRef="FIFO_36x128_OutReg"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_36x128_OutReg_Data[19]</spirit:name>
+                <spirit:displayName>FIFO_36x128_OutReg_Data[19]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="FIFO_36x128_OutReg_Data[19]"/>
+                <spirit:internalPortReference spirit:portRef="Data[19]" spirit:componentRef="FIFO_36x128_OutReg"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_36x128_OutReg_Data[1]</spirit:name>
+                <spirit:displayName>FIFO_36x128_OutReg_Data[1]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="FIFO_36x128_OutReg_Data[1]"/>
+                <spirit:internalPortReference spirit:portRef="Data[1]" spirit:componentRef="FIFO_36x128_OutReg"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_36x128_OutReg_Data[20]</spirit:name>
+                <spirit:displayName>FIFO_36x128_OutReg_Data[20]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="FIFO_36x128_OutReg_Data[20]"/>
+                <spirit:internalPortReference spirit:portRef="Data[20]" spirit:componentRef="FIFO_36x128_OutReg"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_36x128_OutReg_Data[21]</spirit:name>
+                <spirit:displayName>FIFO_36x128_OutReg_Data[21]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="FIFO_36x128_OutReg_Data[21]"/>
+                <spirit:internalPortReference spirit:portRef="Data[21]" spirit:componentRef="FIFO_36x128_OutReg"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_36x128_OutReg_Data[22]</spirit:name>
+                <spirit:displayName>FIFO_36x128_OutReg_Data[22]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="FIFO_36x128_OutReg_Data[22]"/>
+                <spirit:internalPortReference spirit:portRef="Data[22]" spirit:componentRef="FIFO_36x128_OutReg"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_36x128_OutReg_Data[23]</spirit:name>
+                <spirit:displayName>FIFO_36x128_OutReg_Data[23]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="FIFO_36x128_OutReg_Data[23]"/>
+                <spirit:internalPortReference spirit:portRef="Data[23]" spirit:componentRef="FIFO_36x128_OutReg"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_36x128_OutReg_Data[24]</spirit:name>
+                <spirit:displayName>FIFO_36x128_OutReg_Data[24]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="FIFO_36x128_OutReg_Data[24]"/>
+                <spirit:internalPortReference spirit:portRef="Data[24]" spirit:componentRef="FIFO_36x128_OutReg"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_36x128_OutReg_Data[25]</spirit:name>
+                <spirit:displayName>FIFO_36x128_OutReg_Data[25]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="FIFO_36x128_OutReg_Data[25]"/>
+                <spirit:internalPortReference spirit:portRef="Data[25]" spirit:componentRef="FIFO_36x128_OutReg"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_36x128_OutReg_Data[26]</spirit:name>
+                <spirit:displayName>FIFO_36x128_OutReg_Data[26]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="FIFO_36x128_OutReg_Data[26]"/>
+                <spirit:internalPortReference spirit:portRef="Data[26]" spirit:componentRef="FIFO_36x128_OutReg"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_36x128_OutReg_Data[27]</spirit:name>
+                <spirit:displayName>FIFO_36x128_OutReg_Data[27]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="FIFO_36x128_OutReg_Data[27]"/>
+                <spirit:internalPortReference spirit:portRef="Data[27]" spirit:componentRef="FIFO_36x128_OutReg"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_36x128_OutReg_Data[28]</spirit:name>
+                <spirit:displayName>FIFO_36x128_OutReg_Data[28]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="FIFO_36x128_OutReg_Data[28]"/>
+                <spirit:internalPortReference spirit:portRef="Data[28]" spirit:componentRef="FIFO_36x128_OutReg"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_36x128_OutReg_Data[29]</spirit:name>
+                <spirit:displayName>FIFO_36x128_OutReg_Data[29]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="FIFO_36x128_OutReg_Data[29]"/>
+                <spirit:internalPortReference spirit:portRef="Data[29]" spirit:componentRef="FIFO_36x128_OutReg"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_36x128_OutReg_Data[2]</spirit:name>
+                <spirit:displayName>FIFO_36x128_OutReg_Data[2]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="FIFO_36x128_OutReg_Data[2]"/>
+                <spirit:internalPortReference spirit:portRef="Data[2]" spirit:componentRef="FIFO_36x128_OutReg"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_36x128_OutReg_Data[30]</spirit:name>
+                <spirit:displayName>FIFO_36x128_OutReg_Data[30]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="FIFO_36x128_OutReg_Data[30]"/>
+                <spirit:internalPortReference spirit:portRef="Data[30]" spirit:componentRef="FIFO_36x128_OutReg"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_36x128_OutReg_Data[31]</spirit:name>
+                <spirit:displayName>FIFO_36x128_OutReg_Data[31]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="FIFO_36x128_OutReg_Data[31]"/>
+                <spirit:internalPortReference spirit:portRef="Data[31]" spirit:componentRef="FIFO_36x128_OutReg"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_36x128_OutReg_Data[32]</spirit:name>
+                <spirit:displayName>FIFO_36x128_OutReg_Data[32]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="FIFO_36x128_OutReg_Data[32]"/>
+                <spirit:internalPortReference spirit:portRef="Data[32]" spirit:componentRef="FIFO_36x128_OutReg"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_36x128_OutReg_Data[33]</spirit:name>
+                <spirit:displayName>FIFO_36x128_OutReg_Data[33]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="FIFO_36x128_OutReg_Data[33]"/>
+                <spirit:internalPortReference spirit:portRef="Data[33]" spirit:componentRef="FIFO_36x128_OutReg"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_36x128_OutReg_Data[34]</spirit:name>
+                <spirit:displayName>FIFO_36x128_OutReg_Data[34]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="FIFO_36x128_OutReg_Data[34]"/>
+                <spirit:internalPortReference spirit:portRef="Data[34]" spirit:componentRef="FIFO_36x128_OutReg"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_36x128_OutReg_Data[35]</spirit:name>
+                <spirit:displayName>FIFO_36x128_OutReg_Data[35]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="FIFO_36x128_OutReg_Data[35]"/>
+                <spirit:internalPortReference spirit:portRef="Data[35]" spirit:componentRef="FIFO_36x128_OutReg"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_36x128_OutReg_Data[3]</spirit:name>
+                <spirit:displayName>FIFO_36x128_OutReg_Data[3]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="FIFO_36x128_OutReg_Data[3]"/>
+                <spirit:internalPortReference spirit:portRef="Data[3]" spirit:componentRef="FIFO_36x128_OutReg"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_36x128_OutReg_Data[4]</spirit:name>
+                <spirit:displayName>FIFO_36x128_OutReg_Data[4]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="FIFO_36x128_OutReg_Data[4]"/>
+                <spirit:internalPortReference spirit:portRef="Data[4]" spirit:componentRef="FIFO_36x128_OutReg"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_36x128_OutReg_Data[5]</spirit:name>
+                <spirit:displayName>FIFO_36x128_OutReg_Data[5]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="FIFO_36x128_OutReg_Data[5]"/>
+                <spirit:internalPortReference spirit:portRef="Data[5]" spirit:componentRef="FIFO_36x128_OutReg"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_36x128_OutReg_Data[6]</spirit:name>
+                <spirit:displayName>FIFO_36x128_OutReg_Data[6]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="FIFO_36x128_OutReg_Data[6]"/>
+                <spirit:internalPortReference spirit:portRef="Data[6]" spirit:componentRef="FIFO_36x128_OutReg"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_36x128_OutReg_Data[7]</spirit:name>
+                <spirit:displayName>FIFO_36x128_OutReg_Data[7]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="FIFO_36x128_OutReg_Data[7]"/>
+                <spirit:internalPortReference spirit:portRef="Data[7]" spirit:componentRef="FIFO_36x128_OutReg"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_36x128_OutReg_Data[8]</spirit:name>
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+                <spirit:name>FIFO_DC_36x128_DynThr_OutReg_Q[22]</spirit:name>
+                <spirit:displayName>FIFO_DC_36x128_DynThr_OutReg_Q[22]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="Q[22]" spirit:componentRef="FIFO_DC_36x128_DynThr_OutReg"/>
+                <spirit:externalPortReference spirit:portRef="FIFO_DC_36x128_DynThr_OutReg_Q[22]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_DC_36x128_DynThr_OutReg_Q[23]</spirit:name>
+                <spirit:displayName>FIFO_DC_36x128_DynThr_OutReg_Q[23]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="Q[23]" spirit:componentRef="FIFO_DC_36x128_DynThr_OutReg"/>
+                <spirit:externalPortReference spirit:portRef="FIFO_DC_36x128_DynThr_OutReg_Q[23]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_DC_36x128_DynThr_OutReg_Q[24]</spirit:name>
+                <spirit:displayName>FIFO_DC_36x128_DynThr_OutReg_Q[24]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="Q[24]" spirit:componentRef="FIFO_DC_36x128_DynThr_OutReg"/>
+                <spirit:externalPortReference spirit:portRef="FIFO_DC_36x128_DynThr_OutReg_Q[24]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_DC_36x128_DynThr_OutReg_Q[25]</spirit:name>
+                <spirit:displayName>FIFO_DC_36x128_DynThr_OutReg_Q[25]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="Q[25]" spirit:componentRef="FIFO_DC_36x128_DynThr_OutReg"/>
+                <spirit:externalPortReference spirit:portRef="FIFO_DC_36x128_DynThr_OutReg_Q[25]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_DC_36x128_DynThr_OutReg_Q[26]</spirit:name>
+                <spirit:displayName>FIFO_DC_36x128_DynThr_OutReg_Q[26]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="Q[26]" spirit:componentRef="FIFO_DC_36x128_DynThr_OutReg"/>
+                <spirit:externalPortReference spirit:portRef="FIFO_DC_36x128_DynThr_OutReg_Q[26]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_DC_36x128_DynThr_OutReg_Q[27]</spirit:name>
+                <spirit:displayName>FIFO_DC_36x128_DynThr_OutReg_Q[27]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="Q[27]" spirit:componentRef="FIFO_DC_36x128_DynThr_OutReg"/>
+                <spirit:externalPortReference spirit:portRef="FIFO_DC_36x128_DynThr_OutReg_Q[27]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_DC_36x128_DynThr_OutReg_Q[28]</spirit:name>
+                <spirit:displayName>FIFO_DC_36x128_DynThr_OutReg_Q[28]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="Q[28]" spirit:componentRef="FIFO_DC_36x128_DynThr_OutReg"/>
+                <spirit:externalPortReference spirit:portRef="FIFO_DC_36x128_DynThr_OutReg_Q[28]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_DC_36x128_DynThr_OutReg_Q[29]</spirit:name>
+                <spirit:displayName>FIFO_DC_36x128_DynThr_OutReg_Q[29]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="Q[29]" spirit:componentRef="FIFO_DC_36x128_DynThr_OutReg"/>
+                <spirit:externalPortReference spirit:portRef="FIFO_DC_36x128_DynThr_OutReg_Q[29]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_DC_36x128_DynThr_OutReg_Q[2]</spirit:name>
+                <spirit:displayName>FIFO_DC_36x128_DynThr_OutReg_Q[2]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="Q[2]" spirit:componentRef="FIFO_DC_36x128_DynThr_OutReg"/>
+                <spirit:externalPortReference spirit:portRef="FIFO_DC_36x128_DynThr_OutReg_Q[2]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_DC_36x128_DynThr_OutReg_Q[30]</spirit:name>
+                <spirit:displayName>FIFO_DC_36x128_DynThr_OutReg_Q[30]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="Q[30]" spirit:componentRef="FIFO_DC_36x128_DynThr_OutReg"/>
+                <spirit:externalPortReference spirit:portRef="FIFO_DC_36x128_DynThr_OutReg_Q[30]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_DC_36x128_DynThr_OutReg_Q[31]</spirit:name>
+                <spirit:displayName>FIFO_DC_36x128_DynThr_OutReg_Q[31]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="Q[31]" spirit:componentRef="FIFO_DC_36x128_DynThr_OutReg"/>
+                <spirit:externalPortReference spirit:portRef="FIFO_DC_36x128_DynThr_OutReg_Q[31]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_DC_36x128_DynThr_OutReg_Q[32]</spirit:name>
+                <spirit:displayName>FIFO_DC_36x128_DynThr_OutReg_Q[32]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="Q[32]" spirit:componentRef="FIFO_DC_36x128_DynThr_OutReg"/>
+                <spirit:externalPortReference spirit:portRef="FIFO_DC_36x128_DynThr_OutReg_Q[32]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_DC_36x128_DynThr_OutReg_Q[33]</spirit:name>
+                <spirit:displayName>FIFO_DC_36x128_DynThr_OutReg_Q[33]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="Q[33]" spirit:componentRef="FIFO_DC_36x128_DynThr_OutReg"/>
+                <spirit:externalPortReference spirit:portRef="FIFO_DC_36x128_DynThr_OutReg_Q[33]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_DC_36x128_DynThr_OutReg_Q[34]</spirit:name>
+                <spirit:displayName>FIFO_DC_36x128_DynThr_OutReg_Q[34]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="Q[34]" spirit:componentRef="FIFO_DC_36x128_DynThr_OutReg"/>
+                <spirit:externalPortReference spirit:portRef="FIFO_DC_36x128_DynThr_OutReg_Q[34]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_DC_36x128_DynThr_OutReg_Q[35]</spirit:name>
+                <spirit:displayName>FIFO_DC_36x128_DynThr_OutReg_Q[35]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="Q[35]" spirit:componentRef="FIFO_DC_36x128_DynThr_OutReg"/>
+                <spirit:externalPortReference spirit:portRef="FIFO_DC_36x128_DynThr_OutReg_Q[35]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_DC_36x128_DynThr_OutReg_Q[3]</spirit:name>
+                <spirit:displayName>FIFO_DC_36x128_DynThr_OutReg_Q[3]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="Q[3]" spirit:componentRef="FIFO_DC_36x128_DynThr_OutReg"/>
+                <spirit:externalPortReference spirit:portRef="FIFO_DC_36x128_DynThr_OutReg_Q[3]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_DC_36x128_DynThr_OutReg_Q[4]</spirit:name>
+                <spirit:displayName>FIFO_DC_36x128_DynThr_OutReg_Q[4]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="Q[4]" spirit:componentRef="FIFO_DC_36x128_DynThr_OutReg"/>
+                <spirit:externalPortReference spirit:portRef="FIFO_DC_36x128_DynThr_OutReg_Q[4]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_DC_36x128_DynThr_OutReg_Q[5]</spirit:name>
+                <spirit:displayName>FIFO_DC_36x128_DynThr_OutReg_Q[5]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="Q[5]" spirit:componentRef="FIFO_DC_36x128_DynThr_OutReg"/>
+                <spirit:externalPortReference spirit:portRef="FIFO_DC_36x128_DynThr_OutReg_Q[5]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_DC_36x128_DynThr_OutReg_Q[6]</spirit:name>
+                <spirit:displayName>FIFO_DC_36x128_DynThr_OutReg_Q[6]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="Q[6]" spirit:componentRef="FIFO_DC_36x128_DynThr_OutReg"/>
+                <spirit:externalPortReference spirit:portRef="FIFO_DC_36x128_DynThr_OutReg_Q[6]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_DC_36x128_DynThr_OutReg_Q[7]</spirit:name>
+                <spirit:displayName>FIFO_DC_36x128_DynThr_OutReg_Q[7]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="Q[7]" spirit:componentRef="FIFO_DC_36x128_DynThr_OutReg"/>
+                <spirit:externalPortReference spirit:portRef="FIFO_DC_36x128_DynThr_OutReg_Q[7]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_DC_36x128_DynThr_OutReg_Q[8]</spirit:name>
+                <spirit:displayName>FIFO_DC_36x128_DynThr_OutReg_Q[8]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="Q[8]" spirit:componentRef="FIFO_DC_36x128_DynThr_OutReg"/>
+                <spirit:externalPortReference spirit:portRef="FIFO_DC_36x128_DynThr_OutReg_Q[8]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>FIFO_DC_36x128_DynThr_OutReg_Q[9]</spirit:name>
+                <spirit:displayName>FIFO_DC_36x128_DynThr_OutReg_Q[9]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="Q[9]" spirit:componentRef="FIFO_DC_36x128_DynThr_OutReg"/>
+                <spirit:externalPortReference spirit:portRef="FIFO_DC_36x128_DynThr_OutReg_Q[9]"/>
+            </spirit:adHocConnection>
+        </spirit:adHocConnections>
+    </spirit:design>
+</lattice:project>

diff --git a/lattice/ecp5/FIFO/archv/FIFO_36x128_OutReg.zip b/lattice/ecp5/FIFO/archv/FIFO_36x128_OutReg.zip
new file mode 100644 (file)
index 0000000..6e075d0
Binary files /dev/null and b/lattice/ecp5/FIFO/archv/FIFO_36x128_OutReg.zip differ

diff --git a/lattice/ecp5/FIFO/archv/FIFO_DC_36x128_DynThr_OutReg.zip b/lattice/ecp5/FIFO/archv/FIFO_DC_36x128_DynThr_OutReg.zip
new file mode 100644 (file)
index 0000000..0ac65d1
Binary files /dev/null and b/lattice/ecp5/FIFO/archv/FIFO_DC_36x128_DynThr_OutReg.zip differ

diff --git a/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.cst b/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.cst
new file mode 100644 (file)
index 0000000..bfbf105
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.cst
@@ -0,0 +1,3 @@
+Date=03/18/2015
+Time=14:32:07
+

diff --git a/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.edn b/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.edn
new file mode 100644 (file)
index 0000000..6246675
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.edn
@@ -0,0 +1,3014 @@
+(edif fifo_18x1k_oreg
+  (edifVersion 2 0 0)
+  (edifLevel 0)
+  (keywordMap (keywordLevel 0))
+  (status
+    (written
+      (timestamp 2015 3 18 14 32 11)
+      (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80"))))
+      (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_18x1k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 1024 -width 18 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.fdc ")
+  (library ORCLIB
+    (edifLevel 0)
+    (technology
+      (numberDefinition))
+    (cell CCU2C
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
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+            (direction INPUT))
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+    (cell AND2
+      (cellType GENERIC)
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+            (direction INPUT))
+          (port Clock
+            (direction INPUT))
+          (port WrEn
+            (direction INPUT))
+          (port RdEn
+            (direction INPUT))
+          (port Reset
+            (direction INPUT))
+          (port (array (rename AmFullThresh "AmFullThresh(9:0)") 10)
+            (direction INPUT))
+          (port (array (rename Q "Q(17:0)") 18)
+            (direction OUTPUT))
+          (port (array (rename WCNT "WCNT(10:0)") 11)
+            (direction OUTPUT))
+          (port Empty
+            (direction OUTPUT))
+          (port Full
+            (direction OUTPUT))
+          (port AlmostFull
+            (direction OUTPUT)))
+        (property NGD_DRC_MASK (integer 1))
+        (contents
+          (instance AND2_t5
+            (viewRef view1 
+              (cellRef AND2)))
+          (instance INV_5
+            (viewRef view1 
+              (cellRef INV)))
+          (instance AND2_t4
+            (viewRef view1 
+              (cellRef AND2)))
+          (instance INV_4
+            (viewRef view1 
+              (cellRef INV)))
+          (instance AND2_t3
+            (viewRef view1 
+              (cellRef AND2)))
+          (instance XOR2_t2
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance INV_3
+            (viewRef view1 
+              (cellRef INV)))
+          (instance INV_2
+            (viewRef view1 
+              (cellRef INV)))
+          (instance LUT4_1
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x3232")))
+          (instance LUT4_0
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x3232")))
+          (instance AND2_t1
+            (viewRef view1 
+              (cellRef AND2)))
+          (instance INV_1
+            (viewRef view1 
+              (cellRef INV)))
+          (instance XOR2_t0
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance INV_0
+            (viewRef view1 
+              (cellRef INV)))
+          (instance pdp_ram_0_0_0
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_18x1k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b000"))
+            (property CSDECODE_A
+              (string "0b000"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "18"))
+            (property DATA_WIDTH_A
+              (string "18")))
+          (instance FF_68
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_67
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_66
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_65
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_64
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_63
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_62
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_61
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_60
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_59
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_58
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_57
+            (viewRef view1 
+              (cellRef FD1S3BX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_56
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_55
+            (viewRef view1 
+              (cellRef FD1P3BX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_54
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_53
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_52
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_51
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_50
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_49
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_48
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_47
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_46
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_45
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_44
+            (viewRef view1 
+              (cellRef FD1P3BX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_43
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_42
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_41
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_40
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_39
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_38
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_37
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_36
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_35
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_34
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_33
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_32
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_31
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_30
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_29
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_28
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_27
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_26
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_25
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_24
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_23
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_22
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_21
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_20
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_19
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_18
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_17
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_16
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_15
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_14
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_13
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_12
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_11
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_10
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_9
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_8
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_7
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_6
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_5
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_4
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_3
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_2
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_1
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_0
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance bdcnt_bctr_cia
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance bdcnt_bctr_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_ci_a
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance e_cmp_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance a0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance g_cmp_ci_a
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance g_cmp_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance a1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_cia
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_cia
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance precin_inst234
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x0000"))
+            (property INIT0
+              (string "0x0000")))
+          (instance wcnt_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcntd
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance af_set_cmp_ci_a
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance af_set_cmp_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance scuba_vhi_inst
+            (viewRef view1 
+              (cellRef VHI)))
+          (instance scuba_vlo_inst
+            (viewRef view1 
+              (cellRef VLO)))
+          (instance a2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (net invout_2
+            (joined
+              (portRef Z (instanceRef INV_5))
+              (portRef B (instanceRef AND2_t5))))
+          (net invout_1
+            (joined
+              (portRef Z (instanceRef INV_4))
+              (portRef B (instanceRef AND2_t4))))
+          (net rden_i_inv
+            (joined
+              (portRef Z (instanceRef INV_3))
+              (portRef B (instanceRef AND2_t3))))
+          (net invout_0
+            (joined
+              (portRef Z (instanceRef INV_1))
+              (portRef B (instanceRef AND2_t1))))
+          (net r_nw
+            (joined
+              (portRef Z (instanceRef AND2_t1))))
+          (net fcnt_en
+            (joined
+              (portRef SP (instanceRef FF_58))
+              (portRef Z (instanceRef XOR2_t2))
+              (portRef SP (instanceRef FF_68))
+              (portRef SP (instanceRef FF_67))
+              (portRef SP (instanceRef FF_66))
+              (portRef SP (instanceRef FF_65))
+              (portRef SP (instanceRef FF_64))
+              (portRef SP (instanceRef FF_63))
+              (portRef SP (instanceRef FF_62))
+              (portRef SP (instanceRef FF_61))
+              (portRef SP (instanceRef FF_60))
+              (portRef SP (instanceRef FF_59))))
+          (net empty_d
+            (joined
+              (portRef D (instanceRef FF_57))
+              (portRef DO0 (instanceRef LUT4_1))))
+          (net full_d
+            (joined
+              (portRef D (instanceRef FF_56))
+              (portRef DO0 (instanceRef LUT4_0))))
+          (net wptr_0
+            (joined
+              (portRef Q (instanceRef FF_33))
+              (portRef ADA4 (instanceRef pdp_ram_0_0_0))))
+          (net wptr_1
+            (joined
+              (portRef Q (instanceRef FF_32))
+              (portRef ADA5 (instanceRef pdp_ram_0_0_0))))
+          (net wptr_2
+            (joined
+              (portRef Q (instanceRef FF_31))
+              (portRef ADA6 (instanceRef pdp_ram_0_0_0))))
+          (net wptr_3
+            (joined
+              (portRef Q (instanceRef FF_30))
+              (portRef ADA7 (instanceRef pdp_ram_0_0_0))))
+          (net wptr_4
+            (joined
+              (portRef Q (instanceRef FF_29))
+              (portRef ADA8 (instanceRef pdp_ram_0_0_0))))
+          (net wptr_5
+            (joined
+              (portRef Q (instanceRef FF_28))
+              (portRef ADA9 (instanceRef pdp_ram_0_0_0))))
+          (net wptr_6
+            (joined
+              (portRef Q (instanceRef FF_27))
+              (portRef ADA10 (instanceRef pdp_ram_0_0_0))))
+          (net wptr_7
+            (joined
+              (portRef Q (instanceRef FF_26))
+              (portRef ADA11 (instanceRef pdp_ram_0_0_0))))
+          (net wptr_8
+            (joined
+              (portRef Q (instanceRef FF_25))
+              (portRef ADA12 (instanceRef pdp_ram_0_0_0))))
+          (net wptr_9
+            (joined
+              (portRef Q (instanceRef FF_24))
+              (portRef ADA13 (instanceRef pdp_ram_0_0_0))))
+          (net wptr_10
+            (joined
+              (portRef Q (instanceRef FF_23))))
+          (net rptr_10
+            (joined
+              (portRef Q (instanceRef FF_12))
+              (portRef B (instanceRef XOR2_t0))))
+          (net ifcount_0
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_0))
+              (portRef D (instanceRef FF_68))))
+          (net ifcount_1
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_0))
+              (portRef D (instanceRef FF_67))))
+          (net bdcnt_bctr_ci
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_0))
+              (portRef COUT (instanceRef bdcnt_bctr_cia))))
+          (net ifcount_2
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_1))
+              (portRef D (instanceRef FF_66))))
+          (net ifcount_3
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_1))
+              (portRef D (instanceRef FF_65))))
+          (net co0
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_1))
+              (portRef COUT (instanceRef bdcnt_bctr_0))))
+          (net ifcount_4
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_2))
+              (portRef D (instanceRef FF_64))))
+          (net ifcount_5
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_2))
+              (portRef D (instanceRef FF_63))))
+          (net co1
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_2))
+              (portRef COUT (instanceRef bdcnt_bctr_1))))
+          (net ifcount_6
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_3))
+              (portRef D (instanceRef FF_62))))
+          (net ifcount_7
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_3))
+              (portRef D (instanceRef FF_61))))
+          (net co2
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_3))
+              (portRef COUT (instanceRef bdcnt_bctr_2))))
+          (net ifcount_8
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_4))
+              (portRef D (instanceRef FF_60))))
+          (net ifcount_9
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_4))
+              (portRef D (instanceRef FF_59))))
+          (net co3
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_4))
+              (portRef COUT (instanceRef bdcnt_bctr_3))))
+          (net ifcount_10
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_5))
+              (portRef D (instanceRef FF_58))))
+          (net co5
+            (joined
+              (portRef COUT (instanceRef bdcnt_bctr_5))))
+          (net co4
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_5))
+              (portRef COUT (instanceRef bdcnt_bctr_4))))
+          (net cmp_ci
+            (joined
+              (portRef CIN (instanceRef e_cmp_0))
+              (portRef COUT (instanceRef e_cmp_ci_a))))
+          (net rden_i
+            (joined
+              (portRef A0 (instanceRef e_cmp_0))
+              (portRef Z (instanceRef AND2_t4))
+              (portRef B (instanceRef XOR2_t2))
+              (portRef A (instanceRef INV_3))
+              (portRef AD1 (instanceRef LUT4_0))
+              (portRef A (instanceRef AND2_t1))
+              (portRef CEB (instanceRef pdp_ram_0_0_0))
+              (portRef SP (instanceRef FF_44))
+              (portRef SP (instanceRef FF_43))
+              (portRef SP (instanceRef FF_42))
+              (portRef SP (instanceRef FF_41))
+              (portRef SP (instanceRef FF_40))
+              (portRef SP (instanceRef FF_39))
+              (portRef SP (instanceRef FF_38))
+              (portRef SP (instanceRef FF_37))
+              (portRef SP (instanceRef FF_36))
+              (portRef SP (instanceRef FF_35))
+              (portRef SP (instanceRef FF_34))
+              (portRef SP (instanceRef FF_22))
+              (portRef SP (instanceRef FF_21))
+              (portRef SP (instanceRef FF_20))
+              (portRef SP (instanceRef FF_19))
+              (portRef SP (instanceRef FF_18))
+              (portRef SP (instanceRef FF_17))
+              (portRef SP (instanceRef FF_16))
+              (portRef SP (instanceRef FF_15))
+              (portRef SP (instanceRef FF_14))
+              (portRef SP (instanceRef FF_13))
+              (portRef SP (instanceRef FF_12))))
+          (net co0_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_1))
+              (portRef COUT (instanceRef e_cmp_0))))
+          (net co1_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_2))
+              (portRef COUT (instanceRef e_cmp_1))))
+          (net co2_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_3))
+              (portRef COUT (instanceRef e_cmp_2))))
+          (net co3_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_4))
+              (portRef COUT (instanceRef e_cmp_3))))
+          (net co4_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_5))
+              (portRef COUT (instanceRef e_cmp_4))))
+          (net cmp_le_1
+            (joined
+              (portRef S0 (instanceRef a0))
+              (portRef AD2 (instanceRef LUT4_1))))
+          (net cmp_le_1_c
+            (joined
+              (portRef CIN (instanceRef a0))
+              (portRef COUT (instanceRef e_cmp_5))))
+          (net cmp_ci_1
+            (joined
+              (portRef CIN (instanceRef g_cmp_0))
+              (portRef COUT (instanceRef g_cmp_ci_a))))
+          (net co0_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_1))
+              (portRef COUT (instanceRef g_cmp_0))))
+          (net co1_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_2))
+              (portRef COUT (instanceRef g_cmp_1))))
+          (net co2_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_3))
+              (portRef COUT (instanceRef g_cmp_2))))
+          (net co3_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_4))
+              (portRef COUT (instanceRef g_cmp_3))))
+          (net co4_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_5))
+              (portRef COUT (instanceRef g_cmp_4))))
+          (net wren_i_inv
+            (joined
+              (portRef B0 (instanceRef g_cmp_5))
+              (portRef Z (instanceRef INV_2))))
+          (net cmp_ge_d1
+            (joined
+              (portRef S0 (instanceRef a1))
+              (portRef AD2 (instanceRef LUT4_0))))
+          (net cmp_ge_d1_c
+            (joined
+              (portRef CIN (instanceRef a1))
+              (portRef COUT (instanceRef g_cmp_5))))
+          (net iwcount_0
+            (joined
+              (portRef S0 (instanceRef w_ctr_0))
+              (portRef D (instanceRef FF_55))))
+          (net iwcount_1
+            (joined
+              (portRef S1 (instanceRef w_ctr_0))
+              (portRef D (instanceRef FF_54))))
+          (net w_ctr_ci
+            (joined
+              (portRef CIN (instanceRef w_ctr_0))
+              (portRef COUT (instanceRef w_ctr_cia))))
+          (net iwcount_2
+            (joined
+              (portRef S0 (instanceRef w_ctr_1))
+              (portRef D (instanceRef FF_53))))
+          (net iwcount_3
+            (joined
+              (portRef S1 (instanceRef w_ctr_1))
+              (portRef D (instanceRef FF_52))))
+          (net co0_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_1))
+              (portRef COUT (instanceRef w_ctr_0))))
+          (net iwcount_4
+            (joined
+              (portRef S0 (instanceRef w_ctr_2))
+              (portRef D (instanceRef FF_51))))
+          (net iwcount_5
+            (joined
+              (portRef S1 (instanceRef w_ctr_2))
+              (portRef D (instanceRef FF_50))))
+          (net co1_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_2))
+              (portRef COUT (instanceRef w_ctr_1))))
+          (net iwcount_6
+            (joined
+              (portRef S0 (instanceRef w_ctr_3))
+              (portRef D (instanceRef FF_49))))
+          (net iwcount_7
+            (joined
+              (portRef S1 (instanceRef w_ctr_3))
+              (portRef D (instanceRef FF_48))))
+          (net co2_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_3))
+              (portRef COUT (instanceRef w_ctr_2))))
+          (net iwcount_8
+            (joined
+              (portRef S0 (instanceRef w_ctr_4))
+              (portRef D (instanceRef FF_47))))
+          (net iwcount_9
+            (joined
+              (portRef S1 (instanceRef w_ctr_4))
+              (portRef D (instanceRef FF_46))))
+          (net co3_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_4))
+              (portRef COUT (instanceRef w_ctr_3))))
+          (net iwcount_10
+            (joined
+              (portRef S0 (instanceRef w_ctr_5))
+              (portRef D (instanceRef FF_45))))
+          (net co5_1
+            (joined
+              (portRef COUT (instanceRef w_ctr_5))))
+          (net co4_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_5))
+              (portRef COUT (instanceRef w_ctr_4))))
+          (net wcount_10
+            (joined
+              (portRef A0 (instanceRef w_ctr_5))
+              (portRef A (instanceRef XOR2_t0))
+              (portRef Q (instanceRef FF_45))
+              (portRef D (instanceRef FF_23))))
+          (net ircount_0
+            (joined
+              (portRef S0 (instanceRef r_ctr_0))
+              (portRef D (instanceRef FF_44))))
+          (net ircount_1
+            (joined
+              (portRef S1 (instanceRef r_ctr_0))
+              (portRef D (instanceRef FF_43))))
+          (net r_ctr_ci
+            (joined
+              (portRef CIN (instanceRef r_ctr_0))
+              (portRef COUT (instanceRef r_ctr_cia))))
+          (net rcount_0
+            (joined
+              (portRef A0 (instanceRef r_ctr_0))
+              (portRef Q (instanceRef FF_44))
+              (portRef D (instanceRef FF_22))))
+          (net rcount_1
+            (joined
+              (portRef A1 (instanceRef r_ctr_0))
+              (portRef Q (instanceRef FF_43))
+              (portRef D (instanceRef FF_21))))
+          (net ircount_2
+            (joined
+              (portRef S0 (instanceRef r_ctr_1))
+              (portRef D (instanceRef FF_42))))
+          (net ircount_3
+            (joined
+              (portRef S1 (instanceRef r_ctr_1))
+              (portRef D (instanceRef FF_41))))
+          (net co0_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_1))
+              (portRef COUT (instanceRef r_ctr_0))))
+          (net rcount_2
+            (joined
+              (portRef A0 (instanceRef r_ctr_1))
+              (portRef Q (instanceRef FF_42))
+              (portRef D (instanceRef FF_20))))
+          (net rcount_3
+            (joined
+              (portRef A1 (instanceRef r_ctr_1))
+              (portRef Q (instanceRef FF_41))
+              (portRef D (instanceRef FF_19))))
+          (net ircount_4
+            (joined
+              (portRef S0 (instanceRef r_ctr_2))
+              (portRef D (instanceRef FF_40))))
+          (net ircount_5
+            (joined
+              (portRef S1 (instanceRef r_ctr_2))
+              (portRef D (instanceRef FF_39))))
+          (net co1_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_2))
+              (portRef COUT (instanceRef r_ctr_1))))
+          (net rcount_4
+            (joined
+              (portRef A0 (instanceRef r_ctr_2))
+              (portRef Q (instanceRef FF_40))
+              (portRef D (instanceRef FF_18))))
+          (net rcount_5
+            (joined
+              (portRef A1 (instanceRef r_ctr_2))
+              (portRef Q (instanceRef FF_39))
+              (portRef D (instanceRef FF_17))))
+          (net ircount_6
+            (joined
+              (portRef S0 (instanceRef r_ctr_3))
+              (portRef D (instanceRef FF_38))))
+          (net ircount_7
+            (joined
+              (portRef S1 (instanceRef r_ctr_3))
+              (portRef D (instanceRef FF_37))))
+          (net co2_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_3))
+              (portRef COUT (instanceRef r_ctr_2))))
+          (net rcount_6
+            (joined
+              (portRef A0 (instanceRef r_ctr_3))
+              (portRef Q (instanceRef FF_38))
+              (portRef D (instanceRef FF_16))))
+          (net rcount_7
+            (joined
+              (portRef A1 (instanceRef r_ctr_3))
+              (portRef Q (instanceRef FF_37))
+              (portRef D (instanceRef FF_15))))
+          (net ircount_8
+            (joined
+              (portRef S0 (instanceRef r_ctr_4))
+              (portRef D (instanceRef FF_36))))
+          (net ircount_9
+            (joined
+              (portRef S1 (instanceRef r_ctr_4))
+              (portRef D (instanceRef FF_35))))
+          (net co3_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_4))
+              (portRef COUT (instanceRef r_ctr_3))))
+          (net rcount_8
+            (joined
+              (portRef A0 (instanceRef r_ctr_4))
+              (portRef Q (instanceRef FF_36))
+              (portRef D (instanceRef FF_14))))
+          (net rcount_9
+            (joined
+              (portRef A1 (instanceRef r_ctr_4))
+              (portRef Q (instanceRef FF_35))
+              (portRef D (instanceRef FF_13))))
+          (net ircount_10
+            (joined
+              (portRef S0 (instanceRef r_ctr_5))
+              (portRef D (instanceRef FF_34))))
+          (net co5_2
+            (joined
+              (portRef COUT (instanceRef r_ctr_5))))
+          (net co4_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_5))
+              (portRef COUT (instanceRef r_ctr_4))))
+          (net rcount_10
+            (joined
+              (portRef A0 (instanceRef r_ctr_5))
+              (portRef Q (instanceRef FF_34))
+              (portRef D (instanceRef FF_12))))
+          (net wcnt_sub_0
+            (joined
+              (portRef S1 (instanceRef wcnt_0))
+              (portRef D (instanceRef FF_11))))
+          (net rptr_0
+            (joined
+              (portRef B1 (instanceRef wcnt_0))
+              (portRef ADB4 (instanceRef pdp_ram_0_0_0))
+              (portRef Q (instanceRef FF_22))))
+          (net cnt_con_inv
+            (joined
+              (portRef B0 (instanceRef wcnt_0))
+              (portRef Z (instanceRef INV_0))))
+          (net wcount_0
+            (joined
+              (portRef A1 (instanceRef wcnt_0))
+              (portRef Q (instanceRef FF_55))
+              (portRef D (instanceRef FF_33))
+              (portRef A0 (instanceRef w_ctr_0))))
+          (net cnt_con
+            (joined
+              (portRef A0 (instanceRef wcnt_0))
+              (portRef Z (instanceRef AND2_t3))
+              (portRef A (instanceRef INV_0))
+              (portRef B1 (instanceRef bdcnt_bctr_cia))
+              (portRef A1 (instanceRef bdcnt_bctr_cia))
+              (portRef B1 (instanceRef bdcnt_bctr_0))
+              (portRef B0 (instanceRef bdcnt_bctr_0))
+              (portRef B1 (instanceRef bdcnt_bctr_1))
+              (portRef B0 (instanceRef bdcnt_bctr_1))
+              (portRef B1 (instanceRef bdcnt_bctr_2))
+              (portRef B0 (instanceRef bdcnt_bctr_2))
+              (portRef B1 (instanceRef bdcnt_bctr_3))
+              (portRef B0 (instanceRef bdcnt_bctr_3))
+              (portRef B1 (instanceRef bdcnt_bctr_4))
+              (portRef B0 (instanceRef bdcnt_bctr_4))
+              (portRef B1 (instanceRef bdcnt_bctr_5))
+              (portRef B0 (instanceRef bdcnt_bctr_5))))
+          (net precin
+            (joined
+              (portRef CIN (instanceRef wcnt_0))
+              (portRef COUT (instanceRef precin_inst234))))
+          (net wcnt_sub_1
+            (joined
+              (portRef S0 (instanceRef wcnt_1))
+              (portRef D (instanceRef FF_10))))
+          (net wcnt_sub_2
+            (joined
+              (portRef S1 (instanceRef wcnt_1))
+              (portRef D (instanceRef FF_9))))
+          (net rptr_2
+            (joined
+              (portRef B1 (instanceRef wcnt_1))
+              (portRef ADB6 (instanceRef pdp_ram_0_0_0))
+              (portRef Q (instanceRef FF_20))))
+          (net rptr_1
+            (joined
+              (portRef B0 (instanceRef wcnt_1))
+              (portRef ADB5 (instanceRef pdp_ram_0_0_0))
+              (portRef Q (instanceRef FF_21))))
+          (net wcount_2
+            (joined
+              (portRef A1 (instanceRef wcnt_1))
+              (portRef Q (instanceRef FF_53))
+              (portRef D (instanceRef FF_31))
+              (portRef A0 (instanceRef w_ctr_1))))
+          (net wcount_1
+            (joined
+              (portRef A0 (instanceRef wcnt_1))
+              (portRef Q (instanceRef FF_54))
+              (portRef D (instanceRef FF_32))
+              (portRef A1 (instanceRef w_ctr_0))))
+          (net co0_5
+            (joined
+              (portRef CIN (instanceRef wcnt_1))
+              (portRef COUT (instanceRef wcnt_0))))
+          (net wcnt_sub_3
+            (joined
+              (portRef S0 (instanceRef wcnt_2))
+              (portRef D (instanceRef FF_8))))
+          (net wcnt_sub_4
+            (joined
+              (portRef S1 (instanceRef wcnt_2))
+              (portRef D (instanceRef FF_7))))
+          (net rptr_4
+            (joined
+              (portRef B1 (instanceRef wcnt_2))
+              (portRef ADB8 (instanceRef pdp_ram_0_0_0))
+              (portRef Q (instanceRef FF_18))))
+          (net rptr_3
+            (joined
+              (portRef B0 (instanceRef wcnt_2))
+              (portRef ADB7 (instanceRef pdp_ram_0_0_0))
+              (portRef Q (instanceRef FF_19))))
+          (net wcount_4
+            (joined
+              (portRef A1 (instanceRef wcnt_2))
+              (portRef Q (instanceRef FF_51))
+              (portRef D (instanceRef FF_29))
+              (portRef A0 (instanceRef w_ctr_2))))
+          (net wcount_3
+            (joined
+              (portRef A0 (instanceRef wcnt_2))
+              (portRef Q (instanceRef FF_52))
+              (portRef D (instanceRef FF_30))
+              (portRef A1 (instanceRef w_ctr_1))))
+          (net co1_5
+            (joined
+              (portRef CIN (instanceRef wcnt_2))
+              (portRef COUT (instanceRef wcnt_1))))
+          (net wcnt_sub_5
+            (joined
+              (portRef S0 (instanceRef wcnt_3))
+              (portRef D (instanceRef FF_6))))
+          (net wcnt_sub_6
+            (joined
+              (portRef S1 (instanceRef wcnt_3))
+              (portRef D (instanceRef FF_5))))
+          (net rptr_6
+            (joined
+              (portRef B1 (instanceRef wcnt_3))
+              (portRef ADB10 (instanceRef pdp_ram_0_0_0))
+              (portRef Q (instanceRef FF_16))))
+          (net rptr_5
+            (joined
+              (portRef B0 (instanceRef wcnt_3))
+              (portRef ADB9 (instanceRef pdp_ram_0_0_0))
+              (portRef Q (instanceRef FF_17))))
+          (net wcount_6
+            (joined
+              (portRef A1 (instanceRef wcnt_3))
+              (portRef Q (instanceRef FF_49))
+              (portRef D (instanceRef FF_27))
+              (portRef A0 (instanceRef w_ctr_3))))
+          (net wcount_5
+            (joined
+              (portRef A0 (instanceRef wcnt_3))
+              (portRef Q (instanceRef FF_50))
+              (portRef D (instanceRef FF_28))
+              (portRef A1 (instanceRef w_ctr_2))))
+          (net co2_5
+            (joined
+              (portRef CIN (instanceRef wcnt_3))
+              (portRef COUT (instanceRef wcnt_2))))
+          (net wcnt_sub_7
+            (joined
+              (portRef S0 (instanceRef wcnt_4))
+              (portRef D (instanceRef FF_4))))
+          (net wcnt_sub_8
+            (joined
+              (portRef S1 (instanceRef wcnt_4))
+              (portRef D (instanceRef FF_3))))
+          (net rptr_8
+            (joined
+              (portRef B1 (instanceRef wcnt_4))
+              (portRef ADB12 (instanceRef pdp_ram_0_0_0))
+              (portRef Q (instanceRef FF_14))))
+          (net rptr_7
+            (joined
+              (portRef B0 (instanceRef wcnt_4))
+              (portRef ADB11 (instanceRef pdp_ram_0_0_0))
+              (portRef Q (instanceRef FF_15))))
+          (net wcount_8
+            (joined
+              (portRef A1 (instanceRef wcnt_4))
+              (portRef Q (instanceRef FF_47))
+              (portRef D (instanceRef FF_25))
+              (portRef A0 (instanceRef w_ctr_4))))
+          (net wcount_7
+            (joined
+              (portRef A0 (instanceRef wcnt_4))
+              (portRef Q (instanceRef FF_48))
+              (portRef D (instanceRef FF_26))
+              (portRef A1 (instanceRef w_ctr_3))))
+          (net co3_5
+            (joined
+              (portRef CIN (instanceRef wcnt_4))
+              (portRef COUT (instanceRef wcnt_3))))
+          (net wcnt_sub_9
+            (joined
+              (portRef S0 (instanceRef wcnt_5))
+              (portRef D (instanceRef FF_2))))
+          (net wcnt_sub_10
+            (joined
+              (portRef S1 (instanceRef wcnt_5))
+              (portRef D (instanceRef FF_1))))
+          (net rptr_9
+            (joined
+              (portRef B0 (instanceRef wcnt_5))
+              (portRef ADB13 (instanceRef pdp_ram_0_0_0))
+              (portRef Q (instanceRef FF_13))))
+          (net wcnt_sub_msb
+            (joined
+              (portRef A1 (instanceRef wcnt_5))
+              (portRef Z (instanceRef XOR2_t0))))
+          (net wcount_9
+            (joined
+              (portRef A0 (instanceRef wcnt_5))
+              (portRef Q (instanceRef FF_46))
+              (portRef D (instanceRef FF_24))
+              (portRef A1 (instanceRef w_ctr_4))))
+          (net co4_5
+            (joined
+              (portRef CIN (instanceRef wcnt_5))
+              (portRef COUT (instanceRef wcnt_4))))
+          (net co5_3d
+            (joined
+              (portRef S0 (instanceRef wcntd))))
+          (net co5_3
+            (joined
+              (portRef CIN (instanceRef wcntd))
+              (portRef COUT (instanceRef wcnt_5))))
+          (net wren_i
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_ci_a))
+              (portRef Z (instanceRef AND2_t5))
+              (portRef A (instanceRef AND2_t3))
+              (portRef A (instanceRef XOR2_t2))
+              (portRef A (instanceRef INV_2))
+              (portRef AD1 (instanceRef LUT4_1))
+              (portRef A (instanceRef INV_1))
+              (portRef OCEA (instanceRef pdp_ram_0_0_0))
+              (portRef CEA (instanceRef pdp_ram_0_0_0))
+              (portRef SP (instanceRef FF_55))
+              (portRef SP (instanceRef FF_54))
+              (portRef SP (instanceRef FF_53))
+              (portRef SP (instanceRef FF_52))
+              (portRef SP (instanceRef FF_51))
+              (portRef SP (instanceRef FF_50))
+              (portRef SP (instanceRef FF_49))
+              (portRef SP (instanceRef FF_48))
+              (portRef SP (instanceRef FF_47))
+              (portRef SP (instanceRef FF_46))
+              (portRef SP (instanceRef FF_45))
+              (portRef SP (instanceRef FF_33))
+              (portRef SP (instanceRef FF_32))
+              (portRef SP (instanceRef FF_31))
+              (portRef SP (instanceRef FF_30))
+              (portRef SP (instanceRef FF_29))
+              (portRef SP (instanceRef FF_28))
+              (portRef SP (instanceRef FF_27))
+              (portRef SP (instanceRef FF_26))
+              (portRef SP (instanceRef FF_25))
+              (portRef SP (instanceRef FF_24))
+              (portRef SP (instanceRef FF_23))
+              (portRef B0 (instanceRef g_cmp_0))
+              (portRef B1 (instanceRef g_cmp_0))
+              (portRef B0 (instanceRef g_cmp_1))
+              (portRef B1 (instanceRef g_cmp_1))
+              (portRef B0 (instanceRef g_cmp_2))
+              (portRef B1 (instanceRef g_cmp_2))
+              (portRef B0 (instanceRef g_cmp_3))
+              (portRef B1 (instanceRef g_cmp_3))
+              (portRef B0 (instanceRef g_cmp_4))
+              (portRef B1 (instanceRef g_cmp_4))
+              (portRef B1 (instanceRef af_set_cmp_ci_a))))
+          (net x
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_ci_a))
+              (portRef CIN (instanceRef bdcnt_bctr_cia))
+              (portRef CIN (instanceRef e_cmp_ci_a))
+              (portRef CIN (instanceRef g_cmp_ci_a))
+              (portRef CIN (instanceRef w_ctr_cia))
+              (portRef CIN (instanceRef r_ctr_cia))
+              (portRef CIN (instanceRef precin_inst234))))
+          (net cmp_ci_2
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_0))
+              (portRef COUT (instanceRef af_set_cmp_ci_a))))
+          (net wcnt_reg_0
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_0))
+              (portRef Q (instanceRef FF_11))))
+          (net wcnt_reg_1
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_0))
+              (portRef Q (instanceRef FF_10))))
+          (net co0_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_1))
+              (portRef COUT (instanceRef af_set_cmp_0))))
+          (net wcnt_reg_2
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_1))
+              (portRef Q (instanceRef FF_9))))
+          (net wcnt_reg_3
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_1))
+              (portRef Q (instanceRef FF_8))))
+          (net co1_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_2))
+              (portRef COUT (instanceRef af_set_cmp_1))))
+          (net wcnt_reg_4
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_2))
+              (portRef Q (instanceRef FF_7))))
+          (net wcnt_reg_5
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_2))
+              (portRef Q (instanceRef FF_6))))
+          (net co2_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_3))
+              (portRef COUT (instanceRef af_set_cmp_2))))
+          (net wcnt_reg_6
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_3))
+              (portRef Q (instanceRef FF_5))))
+          (net wcnt_reg_7
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_3))
+              (portRef Q (instanceRef FF_4))))
+          (net co3_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_4))
+              (portRef COUT (instanceRef af_set_cmp_3))))
+          (net wcnt_reg_8
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_4))
+              (portRef Q (instanceRef FF_3))))
+          (net wcnt_reg_9
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_4))
+              (portRef Q (instanceRef FF_2))))
+          (net co4_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_5))
+              (portRef COUT (instanceRef af_set_cmp_4))))
+          (net wcnt_reg_10
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_5))
+              (portRef Q (instanceRef FF_1))))
+          (net af_set
+            (joined
+              (portRef S0 (instanceRef a2))
+              (portRef D (instanceRef FF_0))))
+          (net scuba_vhi
+            (joined
+              (portRef Z (instanceRef scuba_vhi_inst))
+              (portRef OCEB (instanceRef pdp_ram_0_0_0))
+              (portRef WEA (instanceRef pdp_ram_0_0_0))
+              (portRef ADA1 (instanceRef pdp_ram_0_0_0))
+              (portRef ADA0 (instanceRef pdp_ram_0_0_0))
+              (portRef C1 (instanceRef bdcnt_bctr_cia))
+              (portRef C0 (instanceRef bdcnt_bctr_cia))
+              (portRef D1 (instanceRef bdcnt_bctr_cia))
+              (portRef D0 (instanceRef bdcnt_bctr_cia))
+              (portRef D1 (instanceRef bdcnt_bctr_0))
+              (portRef D0 (instanceRef bdcnt_bctr_0))
+              (portRef C1 (instanceRef bdcnt_bctr_0))
+              (portRef C0 (instanceRef bdcnt_bctr_0))
+              (portRef D1 (instanceRef bdcnt_bctr_1))
+              (portRef D0 (instanceRef bdcnt_bctr_1))
+              (portRef C1 (instanceRef bdcnt_bctr_1))
+              (portRef C0 (instanceRef bdcnt_bctr_1))
+              (portRef D1 (instanceRef bdcnt_bctr_2))
+              (portRef D0 (instanceRef bdcnt_bctr_2))
+              (portRef C1 (instanceRef bdcnt_bctr_2))
+              (portRef C0 (instanceRef bdcnt_bctr_2))
+              (portRef D1 (instanceRef bdcnt_bctr_3))
+              (portRef D0 (instanceRef bdcnt_bctr_3))
+              (portRef C1 (instanceRef bdcnt_bctr_3))
+              (portRef C0 (instanceRef bdcnt_bctr_3))
+              (portRef D1 (instanceRef bdcnt_bctr_4))
+              (portRef D0 (instanceRef bdcnt_bctr_4))
+              (portRef C1 (instanceRef bdcnt_bctr_4))
+              (portRef C0 (instanceRef bdcnt_bctr_4))
+              (portRef D1 (instanceRef bdcnt_bctr_5))
+              (portRef D0 (instanceRef bdcnt_bctr_5))
+              (portRef C1 (instanceRef bdcnt_bctr_5))
+              (portRef C0 (instanceRef bdcnt_bctr_5))
+              (portRef C1 (instanceRef e_cmp_ci_a))
+              (portRef C0 (instanceRef e_cmp_ci_a))
+              (portRef D1 (instanceRef e_cmp_ci_a))
+              (portRef D0 (instanceRef e_cmp_ci_a))
+              (portRef B1 (instanceRef e_cmp_ci_a))
+              (portRef B0 (instanceRef e_cmp_ci_a))
+              (portRef A1 (instanceRef e_cmp_ci_a))
+              (portRef A0 (instanceRef e_cmp_ci_a))
+              (portRef D1 (instanceRef e_cmp_0))
+              (portRef D0 (instanceRef e_cmp_0))
+              (portRef C1 (instanceRef e_cmp_0))
+              (portRef C0 (instanceRef e_cmp_0))
+              (portRef D1 (instanceRef e_cmp_1))
+              (portRef D0 (instanceRef e_cmp_1))
+              (portRef C1 (instanceRef e_cmp_1))
+              (portRef C0 (instanceRef e_cmp_1))
+              (portRef D1 (instanceRef e_cmp_2))
+              (portRef D0 (instanceRef e_cmp_2))
+              (portRef C1 (instanceRef e_cmp_2))
+              (portRef C0 (instanceRef e_cmp_2))
+              (portRef D1 (instanceRef e_cmp_3))
+              (portRef D0 (instanceRef e_cmp_3))
+              (portRef C1 (instanceRef e_cmp_3))
+              (portRef C0 (instanceRef e_cmp_3))
+              (portRef D1 (instanceRef e_cmp_4))
+              (portRef D0 (instanceRef e_cmp_4))
+              (portRef C1 (instanceRef e_cmp_4))
+              (portRef C0 (instanceRef e_cmp_4))
+              (portRef D1 (instanceRef e_cmp_5))
+              (portRef D0 (instanceRef e_cmp_5))
+              (portRef C1 (instanceRef e_cmp_5))
+              (portRef C0 (instanceRef e_cmp_5))
+              (portRef C1 (instanceRef a0))
+              (portRef C0 (instanceRef a0))
+              (portRef D1 (instanceRef a0))
+              (portRef D0 (instanceRef a0))
+              (portRef C1 (instanceRef g_cmp_ci_a))
+              (portRef C0 (instanceRef g_cmp_ci_a))
+              (portRef D1 (instanceRef g_cmp_ci_a))
+              (portRef D0 (instanceRef g_cmp_ci_a))
+              (portRef B1 (instanceRef g_cmp_ci_a))
+              (portRef B0 (instanceRef g_cmp_ci_a))
+              (portRef A1 (instanceRef g_cmp_ci_a))
+              (portRef A0 (instanceRef g_cmp_ci_a))
+              (portRef D1 (instanceRef g_cmp_0))
+              (portRef D0 (instanceRef g_cmp_0))
+              (portRef C1 (instanceRef g_cmp_0))
+              (portRef C0 (instanceRef g_cmp_0))
+              (portRef D1 (instanceRef g_cmp_1))
+              (portRef D0 (instanceRef g_cmp_1))
+              (portRef C1 (instanceRef g_cmp_1))
+              (portRef C0 (instanceRef g_cmp_1))
+              (portRef D1 (instanceRef g_cmp_2))
+              (portRef D0 (instanceRef g_cmp_2))
+              (portRef C1 (instanceRef g_cmp_2))
+              (portRef C0 (instanceRef g_cmp_2))
+              (portRef D1 (instanceRef g_cmp_3))
+              (portRef D0 (instanceRef g_cmp_3))
+              (portRef C1 (instanceRef g_cmp_3))
+              (portRef C0 (instanceRef g_cmp_3))
+              (portRef D1 (instanceRef g_cmp_4))
+              (portRef D0 (instanceRef g_cmp_4))
+              (portRef C1 (instanceRef g_cmp_4))
+              (portRef C0 (instanceRef g_cmp_4))
+              (portRef D1 (instanceRef g_cmp_5))
+              (portRef D0 (instanceRef g_cmp_5))
+              (portRef C1 (instanceRef g_cmp_5))
+              (portRef C0 (instanceRef g_cmp_5))
+              (portRef C1 (instanceRef a1))
+              (portRef C0 (instanceRef a1))
+              (portRef D1 (instanceRef a1))
+              (portRef D0 (instanceRef a1))
+              (portRef C1 (instanceRef w_ctr_cia))
+              (portRef C0 (instanceRef w_ctr_cia))
+              (portRef D1 (instanceRef w_ctr_cia))
+              (portRef D0 (instanceRef w_ctr_cia))
+              (portRef B1 (instanceRef w_ctr_cia))
+              (portRef A1 (instanceRef w_ctr_cia))
+              (portRef D1 (instanceRef w_ctr_0))
+              (portRef D0 (instanceRef w_ctr_0))
+              (portRef C1 (instanceRef w_ctr_0))
+              (portRef C0 (instanceRef w_ctr_0))
+              (portRef D1 (instanceRef w_ctr_1))
+              (portRef D0 (instanceRef w_ctr_1))
+              (portRef C1 (instanceRef w_ctr_1))
+              (portRef C0 (instanceRef w_ctr_1))
+              (portRef D1 (instanceRef w_ctr_2))
+              (portRef D0 (instanceRef w_ctr_2))
+              (portRef C1 (instanceRef w_ctr_2))
+              (portRef C0 (instanceRef w_ctr_2))
+              (portRef D1 (instanceRef w_ctr_3))
+              (portRef D0 (instanceRef w_ctr_3))
+              (portRef C1 (instanceRef w_ctr_3))
+              (portRef C0 (instanceRef w_ctr_3))
+              (portRef D1 (instanceRef w_ctr_4))
+              (portRef D0 (instanceRef w_ctr_4))
+              (portRef C1 (instanceRef w_ctr_4))
+              (portRef C0 (instanceRef w_ctr_4))
+              (portRef D1 (instanceRef w_ctr_5))
+              (portRef D0 (instanceRef w_ctr_5))
+              (portRef C1 (instanceRef w_ctr_5))
+              (portRef C0 (instanceRef w_ctr_5))
+              (portRef C1 (instanceRef r_ctr_cia))
+              (portRef C0 (instanceRef r_ctr_cia))
+              (portRef D1 (instanceRef r_ctr_cia))
+              (portRef D0 (instanceRef r_ctr_cia))
+              (portRef B1 (instanceRef r_ctr_cia))
+              (portRef A1 (instanceRef r_ctr_cia))
+              (portRef D1 (instanceRef r_ctr_0))
+              (portRef D0 (instanceRef r_ctr_0))
+              (portRef C1 (instanceRef r_ctr_0))
+              (portRef C0 (instanceRef r_ctr_0))
+              (portRef D1 (instanceRef r_ctr_1))
+              (portRef D0 (instanceRef r_ctr_1))
+              (portRef C1 (instanceRef r_ctr_1))
+              (portRef C0 (instanceRef r_ctr_1))
+              (portRef D1 (instanceRef r_ctr_2))
+              (portRef D0 (instanceRef r_ctr_2))
+              (portRef C1 (instanceRef r_ctr_2))
+              (portRef C0 (instanceRef r_ctr_2))
+              (portRef D1 (instanceRef r_ctr_3))
+              (portRef D0 (instanceRef r_ctr_3))
+              (portRef C1 (instanceRef r_ctr_3))
+              (portRef C0 (instanceRef r_ctr_3))
+              (portRef D1 (instanceRef r_ctr_4))
+              (portRef D0 (instanceRef r_ctr_4))
+              (portRef C1 (instanceRef r_ctr_4))
+              (portRef C0 (instanceRef r_ctr_4))
+              (portRef D1 (instanceRef r_ctr_5))
+              (portRef D0 (instanceRef r_ctr_5))
+              (portRef C1 (instanceRef r_ctr_5))
+              (portRef C0 (instanceRef r_ctr_5))
+              (portRef C1 (instanceRef precin_inst234))
+              (portRef C0 (instanceRef precin_inst234))
+              (portRef D1 (instanceRef precin_inst234))
+              (portRef D0 (instanceRef precin_inst234))
+              (portRef B1 (instanceRef precin_inst234))
+              (portRef B0 (instanceRef precin_inst234))
+              (portRef A1 (instanceRef precin_inst234))
+              (portRef A0 (instanceRef precin_inst234))
+              (portRef C1 (instanceRef wcnt_0))
+              (portRef C0 (instanceRef wcnt_0))
+              (portRef D1 (instanceRef wcnt_0))
+              (portRef D0 (instanceRef wcnt_0))
+              (portRef C1 (instanceRef wcnt_1))
+              (portRef C0 (instanceRef wcnt_1))
+              (portRef D1 (instanceRef wcnt_1))
+              (portRef D0 (instanceRef wcnt_1))
+              (portRef C1 (instanceRef wcnt_2))
+              (portRef C0 (instanceRef wcnt_2))
+              (portRef D1 (instanceRef wcnt_2))
+              (portRef D0 (instanceRef wcnt_2))
+              (portRef C1 (instanceRef wcnt_3))
+              (portRef C0 (instanceRef wcnt_3))
+              (portRef D1 (instanceRef wcnt_3))
+              (portRef D0 (instanceRef wcnt_3))
+              (portRef C1 (instanceRef wcnt_4))
+              (portRef C0 (instanceRef wcnt_4))
+              (portRef D1 (instanceRef wcnt_4))
+              (portRef D0 (instanceRef wcnt_4))
+              (portRef C1 (instanceRef wcnt_5))
+              (portRef C0 (instanceRef wcnt_5))
+              (portRef D1 (instanceRef wcnt_5))
+              (portRef D0 (instanceRef wcnt_5))
+              (portRef C1 (instanceRef wcntd))
+              (portRef C0 (instanceRef wcntd))
+              (portRef D1 (instanceRef wcntd))
+              (portRef D0 (instanceRef wcntd))
+              (portRef C1 (instanceRef af_set_cmp_ci_a))
+              (portRef C0 (instanceRef af_set_cmp_ci_a))
+              (portRef D1 (instanceRef af_set_cmp_ci_a))
+              (portRef D0 (instanceRef af_set_cmp_ci_a))
+              (portRef D1 (instanceRef af_set_cmp_0))
+              (portRef D0 (instanceRef af_set_cmp_0))
+              (portRef C1 (instanceRef af_set_cmp_0))
+              (portRef C0 (instanceRef af_set_cmp_0))
+              (portRef D1 (instanceRef af_set_cmp_1))
+              (portRef D0 (instanceRef af_set_cmp_1))
+              (portRef C1 (instanceRef af_set_cmp_1))
+              (portRef C0 (instanceRef af_set_cmp_1))
+              (portRef D1 (instanceRef af_set_cmp_2))
+              (portRef D0 (instanceRef af_set_cmp_2))
+              (portRef C1 (instanceRef af_set_cmp_2))
+              (portRef C0 (instanceRef af_set_cmp_2))
+              (portRef D1 (instanceRef af_set_cmp_3))
+              (portRef D0 (instanceRef af_set_cmp_3))
+              (portRef C1 (instanceRef af_set_cmp_3))
+              (portRef C0 (instanceRef af_set_cmp_3))
+              (portRef D1 (instanceRef af_set_cmp_4))
+              (portRef D0 (instanceRef af_set_cmp_4))
+              (portRef C1 (instanceRef af_set_cmp_4))
+              (portRef C0 (instanceRef af_set_cmp_4))
+              (portRef D1 (instanceRef af_set_cmp_5))
+              (portRef D0 (instanceRef af_set_cmp_5))
+              (portRef C1 (instanceRef af_set_cmp_5))
+              (portRef C0 (instanceRef af_set_cmp_5))
+              (portRef C1 (instanceRef a2))
+              (portRef C0 (instanceRef a2))
+              (portRef D1 (instanceRef a2))
+              (portRef D0 (instanceRef a2))))
+          (net scuba_vlo
+            (joined
+              (portRef Z (instanceRef scuba_vlo_inst))
+              (portRef AD3 (instanceRef LUT4_1))
+              (portRef AD3 (instanceRef LUT4_0))
+              (portRef CSB2 (instanceRef pdp_ram_0_0_0))
+              (portRef CSA2 (instanceRef pdp_ram_0_0_0))
+              (portRef CSB1 (instanceRef pdp_ram_0_0_0))
+              (portRef CSA1 (instanceRef pdp_ram_0_0_0))
+              (portRef CSB0 (instanceRef pdp_ram_0_0_0))
+              (portRef CSA0 (instanceRef pdp_ram_0_0_0))
+              (portRef WEB (instanceRef pdp_ram_0_0_0))
+              (portRef ADB3 (instanceRef pdp_ram_0_0_0))
+              (portRef ADA3 (instanceRef pdp_ram_0_0_0))
+              (portRef ADB2 (instanceRef pdp_ram_0_0_0))
+              (portRef ADA2 (instanceRef pdp_ram_0_0_0))
+              (portRef ADB1 (instanceRef pdp_ram_0_0_0))
+              (portRef ADB0 (instanceRef pdp_ram_0_0_0))
+              (portRef DIB17 (instanceRef pdp_ram_0_0_0))
+              (portRef DIB16 (instanceRef pdp_ram_0_0_0))
+              (portRef DIB15 (instanceRef pdp_ram_0_0_0))
+              (portRef DIB14 (instanceRef pdp_ram_0_0_0))
+              (portRef DIB13 (instanceRef pdp_ram_0_0_0))
+              (portRef DIB12 (instanceRef pdp_ram_0_0_0))
+              (portRef DIB11 (instanceRef pdp_ram_0_0_0))
+              (portRef DIB10 (instanceRef pdp_ram_0_0_0))
+              (portRef DIB9 (instanceRef pdp_ram_0_0_0))
+              (portRef DIB8 (instanceRef pdp_ram_0_0_0))
+              (portRef DIB7 (instanceRef pdp_ram_0_0_0))
+              (portRef DIB6 (instanceRef pdp_ram_0_0_0))
+              (portRef DIB5 (instanceRef pdp_ram_0_0_0))
+              (portRef DIB4 (instanceRef pdp_ram_0_0_0))
+              (portRef DIB3 (instanceRef pdp_ram_0_0_0))
+              (portRef DIB2 (instanceRef pdp_ram_0_0_0))
+              (portRef DIB1 (instanceRef pdp_ram_0_0_0))
+              (portRef DIB0 (instanceRef pdp_ram_0_0_0))
+              (portRef B0 (instanceRef bdcnt_bctr_cia))
+              (portRef A0 (instanceRef bdcnt_bctr_cia))
+              (portRef A1 (instanceRef bdcnt_bctr_5))
+              (portRef A1 (instanceRef e_cmp_0))
+              (portRef A0 (instanceRef e_cmp_1))
+              (portRef A1 (instanceRef e_cmp_1))
+              (portRef A0 (instanceRef e_cmp_2))
+              (portRef A1 (instanceRef e_cmp_2))
+              (portRef A0 (instanceRef e_cmp_3))
+              (portRef A1 (instanceRef e_cmp_3))
+              (portRef A0 (instanceRef e_cmp_4))
+              (portRef A1 (instanceRef e_cmp_4))
+              (portRef A0 (instanceRef e_cmp_5))
+              (portRef A1 (instanceRef e_cmp_5))
+              (portRef B1 (instanceRef e_cmp_5))
+              (portRef B1 (instanceRef a0))
+              (portRef B0 (instanceRef a0))
+              (portRef A1 (instanceRef a0))
+              (portRef A0 (instanceRef a0))
+              (portRef B1 (instanceRef g_cmp_5))
+              (portRef A1 (instanceRef g_cmp_5))
+              (portRef B1 (instanceRef a1))
+              (portRef B0 (instanceRef a1))
+              (portRef A1 (instanceRef a1))
+              (portRef A0 (instanceRef a1))
+              (portRef B0 (instanceRef w_ctr_cia))
+              (portRef A0 (instanceRef w_ctr_cia))
+              (portRef B1 (instanceRef w_ctr_0))
+              (portRef B0 (instanceRef w_ctr_0))
+              (portRef B1 (instanceRef w_ctr_1))
+              (portRef B0 (instanceRef w_ctr_1))
+              (portRef B1 (instanceRef w_ctr_2))
+              (portRef B0 (instanceRef w_ctr_2))
+              (portRef B1 (instanceRef w_ctr_3))
+              (portRef B0 (instanceRef w_ctr_3))
+              (portRef B1 (instanceRef w_ctr_4))
+              (portRef B0 (instanceRef w_ctr_4))
+              (portRef B1 (instanceRef w_ctr_5))
+              (portRef B0 (instanceRef w_ctr_5))
+              (portRef A1 (instanceRef w_ctr_5))
+              (portRef B0 (instanceRef r_ctr_cia))
+              (portRef A0 (instanceRef r_ctr_cia))
+              (portRef B1 (instanceRef r_ctr_0))
+              (portRef B0 (instanceRef r_ctr_0))
+              (portRef B1 (instanceRef r_ctr_1))
+              (portRef B0 (instanceRef r_ctr_1))
+              (portRef B1 (instanceRef r_ctr_2))
+              (portRef B0 (instanceRef r_ctr_2))
+              (portRef B1 (instanceRef r_ctr_3))
+              (portRef B0 (instanceRef r_ctr_3))
+              (portRef B1 (instanceRef r_ctr_4))
+              (portRef B0 (instanceRef r_ctr_4))
+              (portRef B1 (instanceRef r_ctr_5))
+              (portRef B0 (instanceRef r_ctr_5))
+              (portRef A1 (instanceRef r_ctr_5))
+              (portRef B1 (instanceRef wcnt_5))
+              (portRef B1 (instanceRef wcntd))
+              (portRef B0 (instanceRef wcntd))
+              (portRef A1 (instanceRef wcntd))
+              (portRef A0 (instanceRef wcntd))
+              (portRef B0 (instanceRef af_set_cmp_ci_a))
+              (portRef A0 (instanceRef af_set_cmp_ci_a))
+              (portRef B0 (instanceRef af_set_cmp_5))
+              (portRef B1 (instanceRef af_set_cmp_5))
+              (portRef A1 (instanceRef af_set_cmp_5))
+              (portRef B1 (instanceRef a2))
+              (portRef B0 (instanceRef a2))
+              (portRef A1 (instanceRef a2))
+              (portRef A0 (instanceRef a2))))
+          (net af_set_c
+            (joined
+              (portRef CIN (instanceRef a2))
+              (portRef COUT (instanceRef af_set_cmp_5))))
+          (net partial_full
+            (joined
+              (portRef AlmostFull)
+              (portRef Q (instanceRef FF_0))))
+          (net Full
+            (joined
+              (portRef Full)
+              (portRef Q (instanceRef FF_56))
+              (portRef A (instanceRef INV_5))
+              (portRef AD0 (instanceRef LUT4_0))))
+          (net Empty
+            (joined
+              (portRef Empty)
+              (portRef Q (instanceRef FF_57))
+              (portRef A (instanceRef INV_4))
+              (portRef AD0 (instanceRef LUT4_1))))
+          (net WCNT10
+            (joined
+              (portRef (member WCNT 0))
+              (portRef A0 (instanceRef g_cmp_5))
+              (portRef Q (instanceRef FF_58))
+              (portRef A0 (instanceRef bdcnt_bctr_5))
+              (portRef B0 (instanceRef e_cmp_5))))
+          (net WCNT9
+            (joined
+              (portRef (member WCNT 1))
+              (portRef A1 (instanceRef g_cmp_4))
+              (portRef Q (instanceRef FF_59))
+              (portRef A1 (instanceRef bdcnt_bctr_4))
+              (portRef B1 (instanceRef e_cmp_4))))
+          (net WCNT8
+            (joined
+              (portRef (member WCNT 2))
+              (portRef A0 (instanceRef g_cmp_4))
+              (portRef Q (instanceRef FF_60))
+              (portRef A0 (instanceRef bdcnt_bctr_4))
+              (portRef B0 (instanceRef e_cmp_4))))
+          (net WCNT7
+            (joined
+              (portRef (member WCNT 3))
+              (portRef A1 (instanceRef g_cmp_3))
+              (portRef Q (instanceRef FF_61))
+              (portRef A1 (instanceRef bdcnt_bctr_3))
+              (portRef B1 (instanceRef e_cmp_3))))
+          (net WCNT6
+            (joined
+              (portRef (member WCNT 4))
+              (portRef A0 (instanceRef g_cmp_3))
+              (portRef Q (instanceRef FF_62))
+              (portRef A0 (instanceRef bdcnt_bctr_3))
+              (portRef B0 (instanceRef e_cmp_3))))
+          (net WCNT5
+            (joined
+              (portRef (member WCNT 5))
+              (portRef A1 (instanceRef g_cmp_2))
+              (portRef Q (instanceRef FF_63))
+              (portRef A1 (instanceRef bdcnt_bctr_2))
+              (portRef B1 (instanceRef e_cmp_2))))
+          (net WCNT4
+            (joined
+              (portRef (member WCNT 6))
+              (portRef A0 (instanceRef g_cmp_2))
+              (portRef Q (instanceRef FF_64))
+              (portRef A0 (instanceRef bdcnt_bctr_2))
+              (portRef B0 (instanceRef e_cmp_2))))
+          (net WCNT3
+            (joined
+              (portRef (member WCNT 7))
+              (portRef A1 (instanceRef g_cmp_1))
+              (portRef Q (instanceRef FF_65))
+              (portRef A1 (instanceRef bdcnt_bctr_1))
+              (portRef B1 (instanceRef e_cmp_1))))
+          (net WCNT2
+            (joined
+              (portRef (member WCNT 8))
+              (portRef A0 (instanceRef g_cmp_1))
+              (portRef Q (instanceRef FF_66))
+              (portRef A0 (instanceRef bdcnt_bctr_1))
+              (portRef B0 (instanceRef e_cmp_1))))
+          (net WCNT1
+            (joined
+              (portRef (member WCNT 9))
+              (portRef A1 (instanceRef g_cmp_0))
+              (portRef Q (instanceRef FF_67))
+              (portRef A1 (instanceRef bdcnt_bctr_0))
+              (portRef B1 (instanceRef e_cmp_0))))
+          (net WCNT0
+            (joined
+              (portRef (member WCNT 10))
+              (portRef A0 (instanceRef g_cmp_0))
+              (portRef Q (instanceRef FF_68))
+              (portRef A0 (instanceRef bdcnt_bctr_0))
+              (portRef B0 (instanceRef e_cmp_0))))
+          (net dataout17
+            (joined
+              (portRef (member Q 0))
+              (portRef DOB17 (instanceRef pdp_ram_0_0_0))))
+          (net dataout16
+            (joined
+              (portRef (member Q 1))
+              (portRef DOB16 (instanceRef pdp_ram_0_0_0))))
+          (net dataout15
+            (joined
+              (portRef (member Q 2))
+              (portRef DOB15 (instanceRef pdp_ram_0_0_0))))
+          (net dataout14
+            (joined
+              (portRef (member Q 3))
+              (portRef DOB14 (instanceRef pdp_ram_0_0_0))))
+          (net dataout13
+            (joined
+              (portRef (member Q 4))
+              (portRef DOB13 (instanceRef pdp_ram_0_0_0))))
+          (net dataout12
+            (joined
+              (portRef (member Q 5))
+              (portRef DOB12 (instanceRef pdp_ram_0_0_0))))
+          (net dataout11
+            (joined
+              (portRef (member Q 6))
+              (portRef DOB11 (instanceRef pdp_ram_0_0_0))))
+          (net dataout10
+            (joined
+              (portRef (member Q 7))
+              (portRef DOB10 (instanceRef pdp_ram_0_0_0))))
+          (net dataout9
+            (joined
+              (portRef (member Q 8))
+              (portRef DOB9 (instanceRef pdp_ram_0_0_0))))
+          (net dataout8
+            (joined
+              (portRef (member Q 9))
+              (portRef DOB8 (instanceRef pdp_ram_0_0_0))))
+          (net dataout7
+            (joined
+              (portRef (member Q 10))
+              (portRef DOB7 (instanceRef pdp_ram_0_0_0))))
+          (net dataout6
+            (joined
+              (portRef (member Q 11))
+              (portRef DOB6 (instanceRef pdp_ram_0_0_0))))
+          (net dataout5
+            (joined
+              (portRef (member Q 12))
+              (portRef DOB5 (instanceRef pdp_ram_0_0_0))))
+          (net dataout4
+            (joined
+              (portRef (member Q 13))
+              (portRef DOB4 (instanceRef pdp_ram_0_0_0))))
+          (net dataout3
+            (joined
+              (portRef (member Q 14))
+              (portRef DOB3 (instanceRef pdp_ram_0_0_0))))
+          (net dataout2
+            (joined
+              (portRef (member Q 15))
+              (portRef DOB2 (instanceRef pdp_ram_0_0_0))))
+          (net dataout1
+            (joined
+              (portRef (member Q 16))
+              (portRef DOB1 (instanceRef pdp_ram_0_0_0))))
+          (net dataout0
+            (joined
+              (portRef (member Q 17))
+              (portRef DOB0 (instanceRef pdp_ram_0_0_0))))
+          (net AmFullThresh9
+            (joined
+              (portRef (member AmFullThresh 0))
+              (portRef B1 (instanceRef af_set_cmp_4))))
+          (net AmFullThresh8
+            (joined
+              (portRef (member AmFullThresh 1))
+              (portRef B0 (instanceRef af_set_cmp_4))))
+          (net AmFullThresh7
+            (joined
+              (portRef (member AmFullThresh 2))
+              (portRef B1 (instanceRef af_set_cmp_3))))
+          (net AmFullThresh6
+            (joined
+              (portRef (member AmFullThresh 3))
+              (portRef B0 (instanceRef af_set_cmp_3))))
+          (net AmFullThresh5
+            (joined
+              (portRef (member AmFullThresh 4))
+              (portRef B1 (instanceRef af_set_cmp_2))))
+          (net AmFullThresh4
+            (joined
+              (portRef (member AmFullThresh 5))
+              (portRef B0 (instanceRef af_set_cmp_2))))
+          (net AmFullThresh3
+            (joined
+              (portRef (member AmFullThresh 6))
+              (portRef B1 (instanceRef af_set_cmp_1))))
+          (net AmFullThresh2
+            (joined
+              (portRef (member AmFullThresh 7))
+              (portRef B0 (instanceRef af_set_cmp_1))))
+          (net AmFullThresh1
+            (joined
+              (portRef (member AmFullThresh 8))
+              (portRef B1 (instanceRef af_set_cmp_0))))
+          (net AmFullThresh0
+            (joined
+              (portRef (member AmFullThresh 9))
+              (portRef B0 (instanceRef af_set_cmp_0))))
+          (net reset
+            (joined
+              (portRef Reset)
+              (portRef RSTB (instanceRef pdp_ram_0_0_0))
+              (portRef RSTA (instanceRef pdp_ram_0_0_0))
+              (portRef CD (instanceRef FF_68))
+              (portRef CD (instanceRef FF_67))
+              (portRef CD (instanceRef FF_66))
+              (portRef CD (instanceRef FF_65))
+              (portRef CD (instanceRef FF_64))
+              (portRef CD (instanceRef FF_63))
+              (portRef CD (instanceRef FF_62))
+              (portRef CD (instanceRef FF_61))
+              (portRef CD (instanceRef FF_60))
+              (portRef CD (instanceRef FF_59))
+              (portRef CD (instanceRef FF_58))
+              (portRef PD (instanceRef FF_57))
+              (portRef CD (instanceRef FF_56))
+              (portRef PD (instanceRef FF_55))
+              (portRef CD (instanceRef FF_54))
+              (portRef CD (instanceRef FF_53))
+              (portRef CD (instanceRef FF_52))
+              (portRef CD (instanceRef FF_51))
+              (portRef CD (instanceRef FF_50))
+              (portRef CD (instanceRef FF_49))
+              (portRef CD (instanceRef FF_48))
+              (portRef CD (instanceRef FF_47))
+              (portRef CD (instanceRef FF_46))
+              (portRef CD (instanceRef FF_45))
+              (portRef PD (instanceRef FF_44))
+              (portRef CD (instanceRef FF_43))
+              (portRef CD (instanceRef FF_42))
+              (portRef CD (instanceRef FF_41))
+              (portRef CD (instanceRef FF_40))
+              (portRef CD (instanceRef FF_39))
+              (portRef CD (instanceRef FF_38))
+              (portRef CD (instanceRef FF_37))
+              (portRef CD (instanceRef FF_36))
+              (portRef CD (instanceRef FF_35))
+              (portRef CD (instanceRef FF_34))
+              (portRef CD (instanceRef FF_33))
+              (portRef CD (instanceRef FF_32))
+              (portRef CD (instanceRef FF_31))
+              (portRef CD (instanceRef FF_30))
+              (portRef CD (instanceRef FF_29))
+              (portRef CD (instanceRef FF_28))
+              (portRef CD (instanceRef FF_27))
+              (portRef CD (instanceRef FF_26))
+              (portRef CD (instanceRef FF_25))
+              (portRef CD (instanceRef FF_24))
+              (portRef CD (instanceRef FF_23))
+              (portRef CD (instanceRef FF_22))
+              (portRef CD (instanceRef FF_21))
+              (portRef CD (instanceRef FF_20))
+              (portRef CD (instanceRef FF_19))
+              (portRef CD (instanceRef FF_18))
+              (portRef CD (instanceRef FF_17))
+              (portRef CD (instanceRef FF_16))
+              (portRef CD (instanceRef FF_15))
+              (portRef CD (instanceRef FF_14))
+              (portRef CD (instanceRef FF_13))
+              (portRef CD (instanceRef FF_12))
+              (portRef CD (instanceRef FF_11))
+              (portRef CD (instanceRef FF_10))
+              (portRef CD (instanceRef FF_9))
+              (portRef CD (instanceRef FF_8))
+              (portRef CD (instanceRef FF_7))
+              (portRef CD (instanceRef FF_6))
+              (portRef CD (instanceRef FF_5))
+              (portRef CD (instanceRef FF_4))
+              (portRef CD (instanceRef FF_3))
+              (portRef CD (instanceRef FF_2))
+              (portRef CD (instanceRef FF_1))
+              (portRef CD (instanceRef FF_0))))
+          (net rden
+            (joined
+              (portRef RdEn)
+              (portRef A (instanceRef AND2_t4))))
+          (net wren
+            (joined
+              (portRef WrEn)
+              (portRef A (instanceRef AND2_t5))))
+          (net clk
+            (joined
+              (portRef Clock)
+              (portRef CLKB (instanceRef pdp_ram_0_0_0))
+              (portRef CLKA (instanceRef pdp_ram_0_0_0))
+              (portRef CK (instanceRef FF_68))
+              (portRef CK (instanceRef FF_67))
+              (portRef CK (instanceRef FF_66))
+              (portRef CK (instanceRef FF_65))
+              (portRef CK (instanceRef FF_64))
+              (portRef CK (instanceRef FF_63))
+              (portRef CK (instanceRef FF_62))
+              (portRef CK (instanceRef FF_61))
+              (portRef CK (instanceRef FF_60))
+              (portRef CK (instanceRef FF_59))
+              (portRef CK (instanceRef FF_58))
+              (portRef CK (instanceRef FF_57))
+              (portRef CK (instanceRef FF_56))
+              (portRef CK (instanceRef FF_55))
+              (portRef CK (instanceRef FF_54))
+              (portRef CK (instanceRef FF_53))
+              (portRef CK (instanceRef FF_52))
+              (portRef CK (instanceRef FF_51))
+              (portRef CK (instanceRef FF_50))
+              (portRef CK (instanceRef FF_49))
+              (portRef CK (instanceRef FF_48))
+              (portRef CK (instanceRef FF_47))
+              (portRef CK (instanceRef FF_46))
+              (portRef CK (instanceRef FF_45))
+              (portRef CK (instanceRef FF_44))
+              (portRef CK (instanceRef FF_43))
+              (portRef CK (instanceRef FF_42))
+              (portRef CK (instanceRef FF_41))
+              (portRef CK (instanceRef FF_40))
+              (portRef CK (instanceRef FF_39))
+              (portRef CK (instanceRef FF_38))
+              (portRef CK (instanceRef FF_37))
+              (portRef CK (instanceRef FF_36))
+              (portRef CK (instanceRef FF_35))
+              (portRef CK (instanceRef FF_34))
+              (portRef CK (instanceRef FF_33))
+              (portRef CK (instanceRef FF_32))
+              (portRef CK (instanceRef FF_31))
+              (portRef CK (instanceRef FF_30))
+              (portRef CK (instanceRef FF_29))
+              (portRef CK (instanceRef FF_28))
+              (portRef CK (instanceRef FF_27))
+              (portRef CK (instanceRef FF_26))
+              (portRef CK (instanceRef FF_25))
+              (portRef CK (instanceRef FF_24))
+              (portRef CK (instanceRef FF_23))
+              (portRef CK (instanceRef FF_22))
+              (portRef CK (instanceRef FF_21))
+              (portRef CK (instanceRef FF_20))
+              (portRef CK (instanceRef FF_19))
+              (portRef CK (instanceRef FF_18))
+              (portRef CK (instanceRef FF_17))
+              (portRef CK (instanceRef FF_16))
+              (portRef CK (instanceRef FF_15))
+              (portRef CK (instanceRef FF_14))
+              (portRef CK (instanceRef FF_13))
+              (portRef CK (instanceRef FF_12))
+              (portRef CK (instanceRef FF_11))
+              (portRef CK (instanceRef FF_10))
+              (portRef CK (instanceRef FF_9))
+              (portRef CK (instanceRef FF_8))
+              (portRef CK (instanceRef FF_7))
+              (portRef CK (instanceRef FF_6))
+              (portRef CK (instanceRef FF_5))
+              (portRef CK (instanceRef FF_4))
+              (portRef CK (instanceRef FF_3))
+              (portRef CK (instanceRef FF_2))
+              (portRef CK (instanceRef FF_1))
+              (portRef CK (instanceRef FF_0))))
+          (net datain17
+            (joined
+              (portRef (member Data 0))
+              (portRef DIA17 (instanceRef pdp_ram_0_0_0))))
+          (net datain16
+            (joined
+              (portRef (member Data 1))
+              (portRef DIA16 (instanceRef pdp_ram_0_0_0))))
+          (net datain15
+            (joined
+              (portRef (member Data 2))
+              (portRef DIA15 (instanceRef pdp_ram_0_0_0))))
+          (net datain14
+            (joined
+              (portRef (member Data 3))
+              (portRef DIA14 (instanceRef pdp_ram_0_0_0))))
+          (net datain13
+            (joined
+              (portRef (member Data 4))
+              (portRef DIA13 (instanceRef pdp_ram_0_0_0))))
+          (net datain12
+            (joined
+              (portRef (member Data 5))
+              (portRef DIA12 (instanceRef pdp_ram_0_0_0))))
+          (net datain11
+            (joined
+              (portRef (member Data 6))
+              (portRef DIA11 (instanceRef pdp_ram_0_0_0))))
+          (net datain10
+            (joined
+              (portRef (member Data 7))
+              (portRef DIA10 (instanceRef pdp_ram_0_0_0))))
+          (net datain9
+            (joined
+              (portRef (member Data 8))
+              (portRef DIA9 (instanceRef pdp_ram_0_0_0))))
+          (net datain8
+            (joined
+              (portRef (member Data 9))
+              (portRef DIA8 (instanceRef pdp_ram_0_0_0))))
+          (net datain7
+            (joined
+              (portRef (member Data 10))
+              (portRef DIA7 (instanceRef pdp_ram_0_0_0))))
+          (net datain6
+            (joined
+              (portRef (member Data 11))
+              (portRef DIA6 (instanceRef pdp_ram_0_0_0))))
+          (net datain5
+            (joined
+              (portRef (member Data 12))
+              (portRef DIA5 (instanceRef pdp_ram_0_0_0))))
+          (net datain4
+            (joined
+              (portRef (member Data 13))
+              (portRef DIA4 (instanceRef pdp_ram_0_0_0))))
+          (net datain3
+            (joined
+              (portRef (member Data 14))
+              (portRef DIA3 (instanceRef pdp_ram_0_0_0))))
+          (net datain2
+            (joined
+              (portRef (member Data 15))
+              (portRef DIA2 (instanceRef pdp_ram_0_0_0))))
+          (net datain1
+            (joined
+              (portRef (member Data 16))
+              (portRef DIA1 (instanceRef pdp_ram_0_0_0))))
+          (net datain0
+            (joined
+              (portRef (member Data 17))
+              (portRef DIA0 (instanceRef pdp_ram_0_0_0))))))))
+  (design fifo_18x1k_oreg
+    (cellRef fifo_18x1k_oreg
+      (libraryRef ORCLIB)))
+)

diff --git a/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.fdc b/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.fdc
new file mode 100644 (file)
index 0000000..6fbcac9
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.fdc
@@ -0,0 +1,2 @@
+###==== Start Configuration
+

diff --git a/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.lpc b/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.lpc
new file mode 100644 (file)
index 0000000..aa9cf19
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.lpc
@@ -0,0 +1,50 @@
+[Device]
+Family=ecp5um
+PartType=LFE5UM-85F
+PartName=LFE5UM-85F-8MG285C
+SpeedGrade=8
+Package=CSFBGA285
+OperatingCondition=COM
+Status=C
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO
+CoreRevision=5.0
+ModuleName=fifo_18x1k_oreg
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=03/18/2015
+Time=14:32:07
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=1024
+Width=18
+regout=1
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=1
+PfMode=Dynamic - Single Threshold
+PfAssert=508
+PfDeassert=506
+Reset=Async
+Reset1=Sync
+RDataCount=1
+EnECC=0
+EnFWFT=0
+
+[Command]
+cmd_line= -w -n fifo_18x1k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 1024 -width 18 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill

diff --git a/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.ngd b/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.ngd
new file mode 100644 (file)
index 0000000..739970d
Binary files /dev/null and b/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.ngd differ

diff --git a/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.ngo b/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.ngo
new file mode 100644 (file)
index 0000000..ca80848
Binary files /dev/null and b/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.ngo differ

diff --git a/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.vhd b/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.vhd
new file mode 100644 (file)
index 0000000..51a1398
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.vhd
@@ -0,0 +1,1053 @@
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80
+-- Module  Version: 5.0
+--/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_18x1k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 1024 -width 18 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.fdc 
+
+-- Wed Mar 18 14:32:11 2015
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity fifo_18x1k_oreg is
+    port (
+        Data: in  std_logic_vector(17 downto 0); 
+        Clock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        AmFullThresh: in  std_logic_vector(9 downto 0); 
+        Q: out  std_logic_vector(17 downto 0); 
+        WCNT: out  std_logic_vector(10 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic; 
+        AlmostFull: out  std_logic);
+end fifo_18x1k_oreg;
+
+architecture Structure of fifo_18x1k_oreg is
+
+    -- internal signal declarations
+    signal invout_2: std_logic;
+    signal invout_1: std_logic;
+    signal rden_i_inv: std_logic;
+    signal invout_0: std_logic;
+    signal r_nw: std_logic;
+    signal fcnt_en: std_logic;
+    signal empty_i: std_logic;
+    signal empty_d: std_logic;
+    signal full_i: std_logic;
+    signal full_d: std_logic;
+    signal wptr_0: std_logic;
+    signal wptr_1: std_logic;
+    signal wptr_2: std_logic;
+    signal wptr_3: std_logic;
+    signal wptr_4: std_logic;
+    signal wptr_5: std_logic;
+    signal wptr_6: std_logic;
+    signal wptr_7: std_logic;
+    signal wptr_8: std_logic;
+    signal wptr_9: std_logic;
+    signal wptr_10: std_logic;
+    signal rptr_10: std_logic;
+    signal ifcount_0: std_logic;
+    signal ifcount_1: std_logic;
+    signal bdcnt_bctr_ci: std_logic;
+    signal ifcount_2: std_logic;
+    signal ifcount_3: std_logic;
+    signal co0: std_logic;
+    signal ifcount_4: std_logic;
+    signal ifcount_5: std_logic;
+    signal co1: std_logic;
+    signal ifcount_6: std_logic;
+    signal ifcount_7: std_logic;
+    signal co2: std_logic;
+    signal ifcount_8: std_logic;
+    signal ifcount_9: std_logic;
+    signal co3: std_logic;
+    signal ifcount_10: std_logic;
+    signal co5: std_logic;
+    signal co4: std_logic;
+    signal cmp_ci: std_logic;
+    signal rden_i: std_logic;
+    signal co0_1: std_logic;
+    signal co1_1: std_logic;
+    signal co2_1: std_logic;
+    signal co3_1: std_logic;
+    signal co4_1: std_logic;
+    signal cmp_le_1: std_logic;
+    signal cmp_le_1_c: std_logic;
+    signal cmp_ci_1: std_logic;
+    signal fcount_0: std_logic;
+    signal fcount_1: std_logic;
+    signal co0_2: std_logic;
+    signal fcount_2: std_logic;
+    signal fcount_3: std_logic;
+    signal co1_2: std_logic;
+    signal fcount_4: std_logic;
+    signal fcount_5: std_logic;
+    signal co2_2: std_logic;
+    signal fcount_6: std_logic;
+    signal fcount_7: std_logic;
+    signal co3_2: std_logic;
+    signal fcount_8: std_logic;
+    signal fcount_9: std_logic;
+    signal co4_2: std_logic;
+    signal wren_i_inv: std_logic;
+    signal fcount_10: std_logic;
+    signal cmp_ge_d1: std_logic;
+    signal cmp_ge_d1_c: std_logic;
+    signal iwcount_0: std_logic;
+    signal iwcount_1: std_logic;
+    signal w_ctr_ci: std_logic;
+    signal iwcount_2: std_logic;
+    signal iwcount_3: std_logic;
+    signal co0_3: std_logic;
+    signal iwcount_4: std_logic;
+    signal iwcount_5: std_logic;
+    signal co1_3: std_logic;
+    signal iwcount_6: std_logic;
+    signal iwcount_7: std_logic;
+    signal co2_3: std_logic;
+    signal iwcount_8: std_logic;
+    signal iwcount_9: std_logic;
+    signal co3_3: std_logic;
+    signal iwcount_10: std_logic;
+    signal co5_1: std_logic;
+    signal co4_3: std_logic;
+    signal wcount_10: std_logic;
+    signal ircount_0: std_logic;
+    signal ircount_1: std_logic;
+    signal r_ctr_ci: std_logic;
+    signal rcount_0: std_logic;
+    signal rcount_1: std_logic;
+    signal ircount_2: std_logic;
+    signal ircount_3: std_logic;
+    signal co0_4: std_logic;
+    signal rcount_2: std_logic;
+    signal rcount_3: std_logic;
+    signal ircount_4: std_logic;
+    signal ircount_5: std_logic;
+    signal co1_4: std_logic;
+    signal rcount_4: std_logic;
+    signal rcount_5: std_logic;
+    signal ircount_6: std_logic;
+    signal ircount_7: std_logic;
+    signal co2_4: std_logic;
+    signal rcount_6: std_logic;
+    signal rcount_7: std_logic;
+    signal ircount_8: std_logic;
+    signal ircount_9: std_logic;
+    signal co3_4: std_logic;
+    signal rcount_8: std_logic;
+    signal rcount_9: std_logic;
+    signal ircount_10: std_logic;
+    signal co5_2: std_logic;
+    signal co4_4: std_logic;
+    signal rcount_10: std_logic;
+    signal wcnt_sub_0: std_logic;
+    signal rptr_0: std_logic;
+    signal cnt_con_inv: std_logic;
+    signal wcount_0: std_logic;
+    signal cnt_con: std_logic;
+    signal precin: std_logic;
+    signal wcnt_sub_1: std_logic;
+    signal wcnt_sub_2: std_logic;
+    signal rptr_2: std_logic;
+    signal rptr_1: std_logic;
+    signal wcount_2: std_logic;
+    signal wcount_1: std_logic;
+    signal co0_5: std_logic;
+    signal wcnt_sub_3: std_logic;
+    signal wcnt_sub_4: std_logic;
+    signal rptr_4: std_logic;
+    signal rptr_3: std_logic;
+    signal wcount_4: std_logic;
+    signal wcount_3: std_logic;
+    signal co1_5: std_logic;
+    signal wcnt_sub_5: std_logic;
+    signal wcnt_sub_6: std_logic;
+    signal rptr_6: std_logic;
+    signal rptr_5: std_logic;
+    signal wcount_6: std_logic;
+    signal wcount_5: std_logic;
+    signal co2_5: std_logic;
+    signal wcnt_sub_7: std_logic;
+    signal wcnt_sub_8: std_logic;
+    signal rptr_8: std_logic;
+    signal rptr_7: std_logic;
+    signal wcount_8: std_logic;
+    signal wcount_7: std_logic;
+    signal co3_5: std_logic;
+    signal wcnt_sub_9: std_logic;
+    signal wcnt_sub_10: std_logic;
+    signal rptr_9: std_logic;
+    signal wcnt_sub_msb: std_logic;
+    signal wcount_9: std_logic;
+    signal co4_5: std_logic;
+    signal co5_3d: std_logic;
+    signal co5_3: std_logic;
+    signal wren_i: std_logic;
+    signal cmp_ci_2: std_logic;
+    signal wcnt_reg_0: std_logic;
+    signal wcnt_reg_1: std_logic;
+    signal co0_6: std_logic;
+    signal wcnt_reg_2: std_logic;
+    signal wcnt_reg_3: std_logic;
+    signal co1_6: std_logic;
+    signal wcnt_reg_4: std_logic;
+    signal wcnt_reg_5: std_logic;
+    signal co2_6: std_logic;
+    signal wcnt_reg_6: std_logic;
+    signal wcnt_reg_7: std_logic;
+    signal co3_6: std_logic;
+    signal wcnt_reg_8: std_logic;
+    signal wcnt_reg_9: std_logic;
+    signal co4_6: std_logic;
+    signal wcnt_reg_10: std_logic;
+    signal af_set: std_logic;
+    signal scuba_vhi: std_logic;
+    signal scuba_vlo: std_logic;
+    signal af_set_c: std_logic;
+
+    attribute MEM_LPC_FILE : string; 
+    attribute MEM_INIT_FILE : string; 
+    attribute GSR : string; 
+    attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_18x1k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
+    attribute GSR of FF_68 : label is "ENABLED";
+    attribute GSR of FF_67 : label is "ENABLED";
+    attribute GSR of FF_66 : label is "ENABLED";
+    attribute GSR of FF_65 : label is "ENABLED";
+    attribute GSR of FF_64 : label is "ENABLED";
+    attribute GSR of FF_63 : label is "ENABLED";
+    attribute GSR of FF_62 : label is "ENABLED";
+    attribute GSR of FF_61 : label is "ENABLED";
+    attribute GSR of FF_60 : label is "ENABLED";
+    attribute GSR of FF_59 : label is "ENABLED";
+    attribute GSR of FF_58 : label is "ENABLED";
+    attribute GSR of FF_57 : label is "ENABLED";
+    attribute GSR of FF_56 : label is "ENABLED";
+    attribute GSR of FF_55 : label is "ENABLED";
+    attribute GSR of FF_54 : label is "ENABLED";
+    attribute GSR of FF_53 : label is "ENABLED";
+    attribute GSR of FF_52 : label is "ENABLED";
+    attribute GSR of FF_51 : label is "ENABLED";
+    attribute GSR of FF_50 : label is "ENABLED";
+    attribute GSR of FF_49 : label is "ENABLED";
+    attribute GSR of FF_48 : label is "ENABLED";
+    attribute GSR of FF_47 : label is "ENABLED";
+    attribute GSR of FF_46 : label is "ENABLED";
+    attribute GSR of FF_45 : label is "ENABLED";
+    attribute GSR of FF_44 : label is "ENABLED";
+    attribute GSR of FF_43 : label is "ENABLED";
+    attribute GSR of FF_42 : label is "ENABLED";
+    attribute GSR of FF_41 : label is "ENABLED";
+    attribute GSR of FF_40 : label is "ENABLED";
+    attribute GSR of FF_39 : label is "ENABLED";
+    attribute GSR of FF_38 : label is "ENABLED";
+    attribute GSR of FF_37 : label is "ENABLED";
+    attribute GSR of FF_36 : label is "ENABLED";
+    attribute GSR of FF_35 : label is "ENABLED";
+    attribute GSR of FF_34 : label is "ENABLED";
+    attribute GSR of FF_33 : label is "ENABLED";
+    attribute GSR of FF_32 : label is "ENABLED";
+    attribute GSR of FF_31 : label is "ENABLED";
+    attribute GSR of FF_30 : label is "ENABLED";
+    attribute GSR of FF_29 : label is "ENABLED";
+    attribute GSR of FF_28 : label is "ENABLED";
+    attribute GSR of FF_27 : label is "ENABLED";
+    attribute GSR of FF_26 : label is "ENABLED";
+    attribute GSR of FF_25 : label is "ENABLED";
+    attribute GSR of FF_24 : label is "ENABLED";
+    attribute GSR of FF_23 : label is "ENABLED";
+    attribute GSR of FF_22 : label is "ENABLED";
+    attribute GSR of FF_21 : label is "ENABLED";
+    attribute GSR of FF_20 : label is "ENABLED";
+    attribute GSR of FF_19 : label is "ENABLED";
+    attribute GSR of FF_18 : label is "ENABLED";
+    attribute GSR of FF_17 : label is "ENABLED";
+    attribute GSR of FF_16 : label is "ENABLED";
+    attribute GSR of FF_15 : label is "ENABLED";
+    attribute GSR of FF_14 : label is "ENABLED";
+    attribute GSR of FF_13 : label is "ENABLED";
+    attribute GSR of FF_12 : label is "ENABLED";
+    attribute GSR of FF_11 : label is "ENABLED";
+    attribute GSR of FF_10 : label is "ENABLED";
+    attribute GSR of FF_9 : label is "ENABLED";
+    attribute GSR of FF_8 : label is "ENABLED";
+    attribute GSR of FF_7 : label is "ENABLED";
+    attribute GSR of FF_6 : label is "ENABLED";
+    attribute GSR of FF_5 : label is "ENABLED";
+    attribute GSR of FF_4 : label is "ENABLED";
+    attribute GSR of FF_3 : label is "ENABLED";
+    attribute GSR of FF_2 : label is "ENABLED";
+    attribute GSR of FF_1 : label is "ENABLED";
+    attribute GSR of FF_0 : label is "ENABLED";
+    attribute syn_keep : boolean;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    AND2_t5: AND2
+        port map (A=>WrEn, B=>invout_2, Z=>wren_i);
+
+    INV_5: INV
+        port map (A=>full_i, Z=>invout_2);
+
+    AND2_t4: AND2
+        port map (A=>RdEn, B=>invout_1, Z=>rden_i);
+
+    INV_4: INV
+        port map (A=>empty_i, Z=>invout_1);
+
+    AND2_t3: AND2
+        port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
+
+    XOR2_t2: XOR2
+        port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
+
+    INV_3: INV
+        port map (A=>rden_i, Z=>rden_i_inv);
+
+    INV_2: INV
+        port map (A=>wren_i, Z=>wren_i_inv);
+
+    LUT4_1: ROM16X1A
+        generic map (initval=> X"3232")
+        port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, 
+            AD0=>empty_i, DO0=>empty_d);
+
+    LUT4_0: ROM16X1A
+        generic map (initval=> X"3232")
+        port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, 
+            AD0=>full_i, DO0=>full_d);
+
+    AND2_t1: AND2
+        port map (A=>rden_i, B=>invout_0, Z=>r_nw);
+
+    INV_1: INV
+        port map (A=>wren_i, Z=>invout_0);
+
+    XOR2_t0: XOR2
+        port map (A=>wcount_10, B=>rptr_10, Z=>wcnt_sub_msb);
+
+    INV_0: INV
+        port map (A=>cnt_con, Z=>cnt_con_inv);
+
+    pdp_ram_0_0_0: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  18, 
+        DATA_WIDTH_A=>  18)
+        port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), 
+            DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), 
+            DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), 
+            DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), 
+            DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), 
+            DIA0=>Data(0), ADA13=>wptr_9, ADA12=>wptr_8, ADA11=>wptr_7, 
+            ADA10=>wptr_6, ADA9=>wptr_5, ADA8=>wptr_4, ADA7=>wptr_3, 
+            ADA6=>wptr_2, ADA5=>wptr_1, ADA4=>wptr_0, ADA3=>scuba_vlo, 
+            ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, 
+            CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, 
+            CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>scuba_vlo, 
+            RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, 
+            DIB0=>scuba_vlo, ADB13=>rptr_9, ADB12=>rptr_8, ADB11=>rptr_7, 
+            ADB10=>rptr_6, ADB9=>rptr_5, ADB8=>rptr_4, ADB7=>rptr_3, 
+            ADB6=>rptr_2, ADB5=>rptr_1, ADB4=>rptr_0, ADB3=>scuba_vlo, 
+            ADB2=>scuba_vlo, ADB1=>scuba_vlo, ADB0=>scuba_vlo, 
+            CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>scuba_vlo, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>Q(17), DOB16=>Q(16), DOB15=>Q(15), 
+            DOB14=>Q(14), DOB13=>Q(13), DOB12=>Q(12), DOB11=>Q(11), 
+            DOB10=>Q(10), DOB9=>Q(9), DOB8=>Q(8), DOB7=>Q(7), DOB6=>Q(6), 
+            DOB5=>Q(5), DOB4=>Q(4), DOB3=>Q(3), DOB2=>Q(2), DOB1=>Q(1), 
+            DOB0=>Q(0));
+
+    FF_68: FD1P3DX
+        port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_0);
+
+    FF_67: FD1P3DX
+        port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_1);
+
+    FF_66: FD1P3DX
+        port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_2);
+
+    FF_65: FD1P3DX
+        port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_3);
+
+    FF_64: FD1P3DX
+        port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_4);
+
+    FF_63: FD1P3DX
+        port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_5);
+
+    FF_62: FD1P3DX
+        port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_6);
+
+    FF_61: FD1P3DX
+        port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_7);
+
+    FF_60: FD1P3DX
+        port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_8);
+
+    FF_59: FD1P3DX
+        port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_9);
+
+    FF_58: FD1P3DX
+        port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_10);
+
+    FF_57: FD1S3BX
+        port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
+
+    FF_56: FD1S3DX
+        port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
+
+    FF_55: FD1P3BX
+        port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset, 
+            Q=>wcount_0);
+
+    FF_54: FD1P3DX
+        port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_1);
+
+    FF_53: FD1P3DX
+        port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_2);
+
+    FF_52: FD1P3DX
+        port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_3);
+
+    FF_51: FD1P3DX
+        port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_4);
+
+    FF_50: FD1P3DX
+        port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_5);
+
+    FF_49: FD1P3DX
+        port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_6);
+
+    FF_48: FD1P3DX
+        port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_7);
+
+    FF_47: FD1P3DX
+        port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_8);
+
+    FF_46: FD1P3DX
+        port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_9);
+
+    FF_45: FD1P3DX
+        port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_10);
+
+    FF_44: FD1P3BX
+        port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset, 
+            Q=>rcount_0);
+
+    FF_43: FD1P3DX
+        port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_1);
+
+    FF_42: FD1P3DX
+        port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_2);
+
+    FF_41: FD1P3DX
+        port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_3);
+
+    FF_40: FD1P3DX
+        port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_4);
+
+    FF_39: FD1P3DX
+        port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_5);
+
+    FF_38: FD1P3DX
+        port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_6);
+
+    FF_37: FD1P3DX
+        port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_7);
+
+    FF_36: FD1P3DX
+        port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_8);
+
+    FF_35: FD1P3DX
+        port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_9);
+
+    FF_34: FD1P3DX
+        port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_10);
+
+    FF_33: FD1P3DX
+        port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_0);
+
+    FF_32: FD1P3DX
+        port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_1);
+
+    FF_31: FD1P3DX
+        port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_2);
+
+    FF_30: FD1P3DX
+        port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_3);
+
+    FF_29: FD1P3DX
+        port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_4);
+
+    FF_28: FD1P3DX
+        port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_5);
+
+    FF_27: FD1P3DX
+        port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_6);
+
+    FF_26: FD1P3DX
+        port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_7);
+
+    FF_25: FD1P3DX
+        port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_8);
+
+    FF_24: FD1P3DX
+        port map (D=>wcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_9);
+
+    FF_23: FD1P3DX
+        port map (D=>wcount_10, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_10);
+
+    FF_22: FD1P3DX
+        port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_0);
+
+    FF_21: FD1P3DX
+        port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_1);
+
+    FF_20: FD1P3DX
+        port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_2);
+
+    FF_19: FD1P3DX
+        port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_3);
+
+    FF_18: FD1P3DX
+        port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_4);
+
+    FF_17: FD1P3DX
+        port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_5);
+
+    FF_16: FD1P3DX
+        port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_6);
+
+    FF_15: FD1P3DX
+        port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_7);
+
+    FF_14: FD1P3DX
+        port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_8);
+
+    FF_13: FD1P3DX
+        port map (D=>rcount_9, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_9);
+
+    FF_12: FD1P3DX
+        port map (D=>rcount_10, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_10);
+
+    FF_11: FD1S3DX
+        port map (D=>wcnt_sub_0, CK=>Clock, CD=>Reset, Q=>wcnt_reg_0);
+
+    FF_10: FD1S3DX
+        port map (D=>wcnt_sub_1, CK=>Clock, CD=>Reset, Q=>wcnt_reg_1);
+
+    FF_9: FD1S3DX
+        port map (D=>wcnt_sub_2, CK=>Clock, CD=>Reset, Q=>wcnt_reg_2);
+
+    FF_8: FD1S3DX
+        port map (D=>wcnt_sub_3, CK=>Clock, CD=>Reset, Q=>wcnt_reg_3);
+
+    FF_7: FD1S3DX
+        port map (D=>wcnt_sub_4, CK=>Clock, CD=>Reset, Q=>wcnt_reg_4);
+
+    FF_6: FD1S3DX
+        port map (D=>wcnt_sub_5, CK=>Clock, CD=>Reset, Q=>wcnt_reg_5);
+
+    FF_5: FD1S3DX
+        port map (D=>wcnt_sub_6, CK=>Clock, CD=>Reset, Q=>wcnt_reg_6);
+
+    FF_4: FD1S3DX
+        port map (D=>wcnt_sub_7, CK=>Clock, CD=>Reset, Q=>wcnt_reg_7);
+
+    FF_3: FD1S3DX
+        port map (D=>wcnt_sub_8, CK=>Clock, CD=>Reset, Q=>wcnt_reg_8);
+
+    FF_2: FD1S3DX
+        port map (D=>wcnt_sub_9, CK=>Clock, CD=>Reset, Q=>wcnt_reg_9);
+
+    FF_1: FD1S3DX
+        port map (D=>wcnt_sub_10, CK=>Clock, CD=>Reset, Q=>wcnt_reg_10);
+
+    FF_0: FD1S3DX
+        port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull);
+
+    bdcnt_bctr_cia: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>'X', S0=>open, S1=>open, COUT=>bdcnt_bctr_ci);
+
+    bdcnt_bctr_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_0, A1=>fcount_1, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>bdcnt_bctr_ci, S0=>ifcount_0, S1=>ifcount_1, COUT=>co0);
+
+    bdcnt_bctr_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co0, S0=>ifcount_2, S1=>ifcount_3, COUT=>co1);
+
+    bdcnt_bctr_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_4, A1=>fcount_5, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co1, S0=>ifcount_4, S1=>ifcount_5, COUT=>co2);
+
+    bdcnt_bctr_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_6, A1=>fcount_7, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co2, S0=>ifcount_6, S1=>ifcount_7, COUT=>co3);
+
+    bdcnt_bctr_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_8, A1=>fcount_9, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co3, S0=>ifcount_8, S1=>ifcount_9, COUT=>co4);
+
+    bdcnt_bctr_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_10, A1=>scuba_vlo, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co4, S0=>ifcount_10, S1=>open, COUT=>co5);
+
+    e_cmp_ci_a: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci);
+
+    e_cmp_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>rden_i, A1=>scuba_vlo, B0=>fcount_0, B1=>fcount_1, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>cmp_ci, S0=>open, S1=>open, COUT=>co0_1);
+
+    e_cmp_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_2, 
+            B1=>fcount_3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co0_1, S0=>open, S1=>open, COUT=>co1_1);
+
+    e_cmp_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_4, 
+            B1=>fcount_5, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co1_1, S0=>open, S1=>open, COUT=>co2_1);
+
+    e_cmp_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_6, 
+            B1=>fcount_7, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co2_1, S0=>open, S1=>open, COUT=>co3_1);
+
+    e_cmp_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_8, 
+            B1=>fcount_9, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co3_1, S0=>open, S1=>open, COUT=>co4_1);
+
+    e_cmp_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_10, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co4_1, S0=>open, S1=>open, 
+            COUT=>cmp_le_1_c);
+
+    a0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>cmp_le_1_c, S0=>cmp_le_1, S1=>open, 
+            COUT=>open);
+
+    g_cmp_ci_a: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_1);
+
+    g_cmp_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>cmp_ci_1, S0=>open, S1=>open, COUT=>co0_2);
+
+    g_cmp_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co0_2, S0=>open, S1=>open, COUT=>co1_2);
+
+    g_cmp_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co1_2, S0=>open, S1=>open, COUT=>co2_2);
+
+    g_cmp_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co2_2, S0=>open, S1=>open, COUT=>co3_2);
+
+    g_cmp_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co3_2, S0=>open, S1=>open, COUT=>co4_2);
+
+    g_cmp_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_10, A1=>scuba_vlo, B0=>wren_i_inv, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co4_2, S0=>open, S1=>open, 
+            COUT=>cmp_ge_d1_c);
+
+    a1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>cmp_ge_d1_c, S0=>cmp_ge_d1, S1=>open, 
+            COUT=>open);
+
+    w_ctr_cia: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>w_ctr_ci);
+
+    w_ctr_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>w_ctr_ci, S0=>iwcount_0, S1=>iwcount_1, 
+            COUT=>co0_3);
+
+    w_ctr_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_2, A1=>wcount_3, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co0_3, S0=>iwcount_2, S1=>iwcount_3, 
+            COUT=>co1_3);
+
+    w_ctr_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_4, A1=>wcount_5, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co1_3, S0=>iwcount_4, S1=>iwcount_5, 
+            COUT=>co2_3);
+
+    w_ctr_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_6, A1=>wcount_7, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co2_3, S0=>iwcount_6, S1=>iwcount_7, 
+            COUT=>co3_3);
+
+    w_ctr_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_8, A1=>wcount_9, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co3_3, S0=>iwcount_8, S1=>iwcount_9, 
+            COUT=>co4_3);
+
+    w_ctr_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_10, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co4_3, S0=>iwcount_10, S1=>open, 
+            COUT=>co5_1);
+
+    r_ctr_cia: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>r_ctr_ci);
+
+    r_ctr_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>r_ctr_ci, S0=>ircount_0, S1=>ircount_1, 
+            COUT=>co0_4);
+
+    r_ctr_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_2, A1=>rcount_3, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co0_4, S0=>ircount_2, S1=>ircount_3, 
+            COUT=>co1_4);
+
+    r_ctr_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_4, A1=>rcount_5, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co1_4, S0=>ircount_4, S1=>ircount_5, 
+            COUT=>co2_4);
+
+    r_ctr_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_6, A1=>rcount_7, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co2_4, S0=>ircount_6, S1=>ircount_7, 
+            COUT=>co3_4);
+
+    r_ctr_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_8, A1=>rcount_9, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co3_4, S0=>ircount_8, S1=>ircount_9, 
+            COUT=>co4_4);
+
+    r_ctr_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_10, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co4_4, S0=>ircount_10, S1=>open, 
+            COUT=>co5_2);
+
+    precin_inst234: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"0000", 
+        INIT0=> X"0000")
+        port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>precin);
+
+    wcnt_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>cnt_con, A1=>wcount_0, B0=>cnt_con_inv, B1=>rptr_0, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>precin, S0=>open, S1=>wcnt_sub_0, COUT=>co0_5);
+
+    wcnt_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_1, A1=>wcount_2, B0=>rptr_1, B1=>rptr_2, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co0_5, S0=>wcnt_sub_1, S1=>wcnt_sub_2, COUT=>co1_5);
+
+    wcnt_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_3, A1=>wcount_4, B0=>rptr_3, B1=>rptr_4, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co1_5, S0=>wcnt_sub_3, S1=>wcnt_sub_4, COUT=>co2_5);
+
+    wcnt_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_5, A1=>wcount_6, B0=>rptr_5, B1=>rptr_6, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co2_5, S0=>wcnt_sub_5, S1=>wcnt_sub_6, COUT=>co3_5);
+
+    wcnt_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_7, A1=>wcount_8, B0=>rptr_7, B1=>rptr_8, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co3_5, S0=>wcnt_sub_7, S1=>wcnt_sub_8, COUT=>co4_5);
+
+    wcnt_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_9, A1=>wcnt_sub_msb, B0=>rptr_9, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co4_5, S0=>wcnt_sub_9, S1=>wcnt_sub_10, 
+            COUT=>co5_3);
+
+    wcntd: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co5_3, S0=>co5_3d, S1=>open, COUT=>open);
+
+    af_set_cmp_ci_a: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_2);
+
+    af_set_cmp_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0), 
+            B1=>AmFullThresh(1), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>cmp_ci_2, S0=>open, 
+            S1=>open, COUT=>co0_6);
+
+    af_set_cmp_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2), 
+            B1=>AmFullThresh(3), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co0_6, S0=>open, S1=>open, 
+            COUT=>co1_6);
+
+    af_set_cmp_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4), 
+            B1=>AmFullThresh(5), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co1_6, S0=>open, S1=>open, 
+            COUT=>co2_6);
+
+    af_set_cmp_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6), 
+            B1=>AmFullThresh(7), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co2_6, S0=>open, S1=>open, 
+            COUT=>co3_6);
+
+    af_set_cmp_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8), 
+            B1=>AmFullThresh(9), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co3_6, S0=>open, S1=>open, 
+            COUT=>co4_6);
+
+    af_set_cmp_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_10, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co4_6, S0=>open, S1=>open, 
+            COUT=>af_set_c);
+
+    scuba_vhi_inst: VHI
+        port map (Z=>scuba_vhi);
+
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    a2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>af_set_c, S0=>af_set, S1=>open, 
+            COUT=>open);
+
+    WCNT(0) <= fcount_0;
+    WCNT(1) <= fcount_1;
+    WCNT(2) <= fcount_2;
+    WCNT(3) <= fcount_3;
+    WCNT(4) <= fcount_4;
+    WCNT(5) <= fcount_5;
+    WCNT(6) <= fcount_6;
+    WCNT(7) <= fcount_7;
+    WCNT(8) <= fcount_8;
+    WCNT(9) <= fcount_9;
+    WCNT(10) <= fcount_10;
+    Empty <= empty_i;
+    Full <= full_i;
+end Structure;

diff --git a/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg_ngd.asd b/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg_ngd.asd
new file mode 100644 (file)
index 0000000..c265c78
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg_ngd.asd
@@ -0,0 +1 @@
+[ActiveSupport NGD]

diff --git a/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.cst b/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.cst
new file mode 100644 (file)
index 0000000..4b60fa4
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.cst
@@ -0,0 +1,3 @@
+Date=03/18/2015
+Time=14:42:54
+

diff --git a/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.edn b/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.edn
new file mode 100644 (file)
index 0000000..dbbee06
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.edn
@@ -0,0 +1,2679 @@
+(edif fifo_18x256_oreg
+  (edifVersion 2 0 0)
+  (edifLevel 0)
+  (keywordMap (keywordLevel 0))
+  (status
+    (written
+      (timestamp 2015 3 18 14 42 55)
+      (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80"))))
+      (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_18x256_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 256 -width 18 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.fdc ")
+  (library ORCLIB
+    (edifLevel 0)
+    (technology
+      (numberDefinition))
+    (cell CCU2C
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A0
+            (direction INPUT))
+          (port A1
+            (direction INPUT))
+          (port B0
+            (direction INPUT))
+          (port B1
+            (direction INPUT))
+          (port C0
+            (direction INPUT))
+          (port C1
+            (direction INPUT))
+          (port D0
+            (direction INPUT))
+          (port D1
+            (direction INPUT))
+          (port CIN
+            (direction INPUT))
+          (port S0
+            (direction OUTPUT))
+          (port S1
+            (direction OUTPUT))
+          (port COUT
+            (direction OUTPUT)))))
+    (cell AND2
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A
+            (direction INPUT))
+          (port B
+            (direction INPUT))
+          (port Z
+            (direction OUTPUT)))))
+    (cell FD1P3BX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port SP
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port PD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell FD1P3DX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port SP
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port CD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell FD1S3BX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port PD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell FD1S3DX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port CD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell INV
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A
+            (direction INPUT))
+          (port Z
+            (direction OUTPUT)))))
+    (cell ROM16X1A
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port AD3
+            (direction INPUT))
+          (port AD2
+            (direction INPUT))
+          (port AD1
+            (direction INPUT))
+          (port AD0
+            (direction INPUT))
+          (port DO0
+            (direction OUTPUT)))))
+    (cell VHI
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port Z
+            (direction OUTPUT)))))
+    (cell VLO
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port Z
+            (direction OUTPUT)))))
+    (cell XOR2
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A
+            (direction INPUT))
+          (port B
+            (direction INPUT))
+          (port Z
+            (direction OUTPUT)))))
+    (cell DP16KD
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port DIA17
+            (direction INPUT))
+          (port DIA16
+            (direction INPUT))
+          (port DIA15
+            (direction INPUT))
+          (port DIA14
+            (direction INPUT))
+          (port DIA13
+            (direction INPUT))
+          (port DIA12
+            (direction INPUT))
+          (port DIA11
+            (direction INPUT))
+          (port DIA10
+            (direction INPUT))
+          (port DIA9
+            (direction INPUT))
+          (port DIA8
+            (direction INPUT))
+          (port DIA7
+            (direction INPUT))
+          (port DIA6
+            (direction INPUT))
+          (port DIA5
+            (direction INPUT))
+          (port DIA4
+            (direction INPUT))
+          (port DIA3
+            (direction INPUT))
+          (port DIA2
+            (direction INPUT))
+          (port DIA1
+            (direction INPUT))
+          (port DIA0
+            (direction INPUT))
+          (port ADA13
+            (direction INPUT))
+          (port ADA12
+            (direction INPUT))
+          (port ADA11
+            (direction INPUT))
+          (port ADA10
+            (direction INPUT))
+          (port ADA9
+            (direction INPUT))
+          (port ADA8
+            (direction INPUT))
+          (port ADA7
+            (direction INPUT))
+          (port ADA6
+            (direction INPUT))
+          (port ADA5
+            (direction INPUT))
+          (port ADA4
+            (direction INPUT))
+          (port ADA3
+            (direction INPUT))
+          (port ADA2
+            (direction INPUT))
+          (port ADA1
+            (direction INPUT))
+          (port ADA0
+            (direction INPUT))
+          (port CEA
+            (direction INPUT))
+          (port OCEA
+            (direction INPUT))
+          (port CLKA
+            (direction INPUT))
+          (port WEA
+            (direction INPUT))
+          (port CSA2
+            (direction INPUT))
+          (port CSA1
+            (direction INPUT))
+          (port CSA0
+            (direction INPUT))
+          (port RSTA
+            (direction INPUT))
+          (port DIB17
+            (direction INPUT))
+          (port DIB16
+            (direction INPUT))
+          (port DIB15
+            (direction INPUT))
+          (port DIB14
+            (direction INPUT))
+          (port DIB13
+            (direction INPUT))
+          (port DIB12
+            (direction INPUT))
+          (port DIB11
+            (direction INPUT))
+          (port DIB10
+            (direction INPUT))
+          (port DIB9
+            (direction INPUT))
+          (port DIB8
+            (direction INPUT))
+          (port DIB7
+            (direction INPUT))
+          (port DIB6
+            (direction INPUT))
+          (port DIB5
+            (direction INPUT))
+          (port DIB4
+            (direction INPUT))
+          (port DIB3
+            (direction INPUT))
+          (port DIB2
+            (direction INPUT))
+          (port DIB1
+            (direction INPUT))
+          (port DIB0
+            (direction INPUT))
+          (port ADB13
+            (direction INPUT))
+          (port ADB12
+            (direction INPUT))
+          (port ADB11
+            (direction INPUT))
+          (port ADB10
+            (direction INPUT))
+          (port ADB9
+            (direction INPUT))
+          (port ADB8
+            (direction INPUT))
+          (port ADB7
+            (direction INPUT))
+          (port ADB6
+            (direction INPUT))
+          (port ADB5
+            (direction INPUT))
+          (port ADB4
+            (direction INPUT))
+          (port ADB3
+            (direction INPUT))
+          (port ADB2
+            (direction INPUT))
+          (port ADB1
+            (direction INPUT))
+          (port ADB0
+            (direction INPUT))
+          (port CEB
+            (direction INPUT))
+          (port OCEB
+            (direction INPUT))
+          (port CLKB
+            (direction INPUT))
+          (port WEB
+            (direction INPUT))
+          (port CSB2
+            (direction INPUT))
+          (port CSB1
+            (direction INPUT))
+          (port CSB0
+            (direction INPUT))
+          (port RSTB
+            (direction INPUT))
+          (port DOA17
+            (direction OUTPUT))
+          (port DOA16
+            (direction OUTPUT))
+          (port DOA15
+            (direction OUTPUT))
+          (port DOA14
+            (direction OUTPUT))
+          (port DOA13
+            (direction OUTPUT))
+          (port DOA12
+            (direction OUTPUT))
+          (port DOA11
+            (direction OUTPUT))
+          (port DOA10
+            (direction OUTPUT))
+          (port DOA9
+            (direction OUTPUT))
+          (port DOA8
+            (direction OUTPUT))
+          (port DOA7
+            (direction OUTPUT))
+          (port DOA6
+            (direction OUTPUT))
+          (port DOA5
+            (direction OUTPUT))
+          (port DOA4
+            (direction OUTPUT))
+          (port DOA3
+            (direction OUTPUT))
+          (port DOA2
+            (direction OUTPUT))
+          (port DOA1
+            (direction OUTPUT))
+          (port DOA0
+            (direction OUTPUT))
+          (port DOB17
+            (direction OUTPUT))
+          (port DOB16
+            (direction OUTPUT))
+          (port DOB15
+            (direction OUTPUT))
+          (port DOB14
+            (direction OUTPUT))
+          (port DOB13
+            (direction OUTPUT))
+          (port DOB12
+            (direction OUTPUT))
+          (port DOB11
+            (direction OUTPUT))
+          (port DOB10
+            (direction OUTPUT))
+          (port DOB9
+            (direction OUTPUT))
+          (port DOB8
+            (direction OUTPUT))
+          (port DOB7
+            (direction OUTPUT))
+          (port DOB6
+            (direction OUTPUT))
+          (port DOB5
+            (direction OUTPUT))
+          (port DOB4
+            (direction OUTPUT))
+          (port DOB3
+            (direction OUTPUT))
+          (port DOB2
+            (direction OUTPUT))
+          (port DOB1
+            (direction OUTPUT))
+          (port DOB0
+            (direction OUTPUT)))))
+    (cell fifo_18x256_oreg
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port (array (rename Data "Data(17:0)") 18)
+            (direction INPUT))
+          (port Clock
+            (direction INPUT))
+          (port WrEn
+            (direction INPUT))
+          (port RdEn
+            (direction INPUT))
+          (port Reset
+            (direction INPUT))
+          (port (array (rename AmFullThresh "AmFullThresh(7:0)") 8)
+            (direction INPUT))
+          (port (array (rename Q "Q(17:0)") 18)
+            (direction OUTPUT))
+          (port (array (rename WCNT "WCNT(8:0)") 9)
+            (direction OUTPUT))
+          (port Empty
+            (direction OUTPUT))
+          (port Full
+            (direction OUTPUT))
+          (port AlmostFull
+            (direction OUTPUT)))
+        (property NGD_DRC_MASK (integer 1))
+        (contents
+          (instance AND2_t5
+            (viewRef view1 
+              (cellRef AND2)))
+          (instance INV_5
+            (viewRef view1 
+              (cellRef INV)))
+          (instance AND2_t4
+            (viewRef view1 
+              (cellRef AND2)))
+          (instance INV_4
+            (viewRef view1 
+              (cellRef INV)))
+          (instance AND2_t3
+            (viewRef view1 
+              (cellRef AND2)))
+          (instance XOR2_t2
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance INV_3
+            (viewRef view1 
+              (cellRef INV)))
+          (instance INV_2
+            (viewRef view1 
+              (cellRef INV)))
+          (instance LUT4_1
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x3232")))
+          (instance LUT4_0
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x3232")))
+          (instance AND2_t1
+            (viewRef view1 
+              (cellRef AND2)))
+          (instance INV_1
+            (viewRef view1 
+              (cellRef INV)))
+          (instance XOR2_t0
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance INV_0
+            (viewRef view1 
+              (cellRef INV)))
+          (instance pdp_ram_0_0_0
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_18x256_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b000"))
+            (property CSDECODE_A
+              (string "0b000"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "18"))
+            (property DATA_WIDTH_A
+              (string "18")))
+          (instance FF_56
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_55
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_54
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_53
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_52
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_51
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_50
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_49
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_48
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_47
+            (viewRef view1 
+              (cellRef FD1S3BX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_46
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_45
+            (viewRef view1 
+              (cellRef FD1P3BX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_44
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_43
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_42
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_41
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_40
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_39
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_38
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_37
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_36
+            (viewRef view1 
+              (cellRef FD1P3BX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_35
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_34
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_33
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_32
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_31
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_30
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_29
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_28
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_27
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_26
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_25
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_24
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_23
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_22
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_21
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_20
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_19
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_18
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_17
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_16
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_15
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_14
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_13
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_12
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_11
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_10
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_9
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_8
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_7
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_6
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_5
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_4
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_3
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_2
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_1
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_0
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance bdcnt_bctr_cia
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance bdcnt_bctr_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_ci_a
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance e_cmp_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance a0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance g_cmp_ci_a
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance g_cmp_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance a1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_cia
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_cia
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance precin_inst207
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x0000"))
+            (property INIT0
+              (string "0x0000")))
+          (instance wcnt_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcntd
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance af_set_cmp_ci_a
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance af_set_cmp_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance scuba_vhi_inst
+            (viewRef view1 
+              (cellRef VHI)))
+          (instance scuba_vlo_inst
+            (viewRef view1 
+              (cellRef VLO)))
+          (instance a2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (net invout_2
+            (joined
+              (portRef Z (instanceRef INV_5))
+              (portRef B (instanceRef AND2_t5))))
+          (net invout_1
+            (joined
+              (portRef Z (instanceRef INV_4))
+              (portRef B (instanceRef AND2_t4))))
+          (net rden_i_inv
+            (joined
+              (portRef Z (instanceRef INV_3))
+              (portRef B (instanceRef AND2_t3))))
+          (net invout_0
+            (joined
+              (portRef Z (instanceRef INV_1))
+              (portRef B (instanceRef AND2_t1))))
+          (net r_nw
+            (joined
+              (portRef Z (instanceRef AND2_t1))))
+          (net fcnt_en
+            (joined
+              (portRef SP (instanceRef FF_48))
+              (portRef Z (instanceRef XOR2_t2))
+              (portRef SP (instanceRef FF_56))
+              (portRef SP (instanceRef FF_55))
+              (portRef SP (instanceRef FF_54))
+              (portRef SP (instanceRef FF_53))
+              (portRef SP (instanceRef FF_52))
+              (portRef SP (instanceRef FF_51))
+              (portRef SP (instanceRef FF_50))
+              (portRef SP (instanceRef FF_49))))
+          (net empty_d
+            (joined
+              (portRef D (instanceRef FF_47))
+              (portRef DO0 (instanceRef LUT4_1))))
+          (net full_d
+            (joined
+              (portRef D (instanceRef FF_46))
+              (portRef DO0 (instanceRef LUT4_0))))
+          (net wptr_0
+            (joined
+              (portRef Q (instanceRef FF_27))
+              (portRef ADA4 (instanceRef pdp_ram_0_0_0))))
+          (net wptr_1
+            (joined
+              (portRef Q (instanceRef FF_26))
+              (portRef ADA5 (instanceRef pdp_ram_0_0_0))))
+          (net wptr_2
+            (joined
+              (portRef Q (instanceRef FF_25))
+              (portRef ADA6 (instanceRef pdp_ram_0_0_0))))
+          (net wptr_3
+            (joined
+              (portRef Q (instanceRef FF_24))
+              (portRef ADA7 (instanceRef pdp_ram_0_0_0))))
+          (net wptr_4
+            (joined
+              (portRef Q (instanceRef FF_23))
+              (portRef ADA8 (instanceRef pdp_ram_0_0_0))))
+          (net wptr_5
+            (joined
+              (portRef Q (instanceRef FF_22))
+              (portRef ADA9 (instanceRef pdp_ram_0_0_0))))
+          (net wptr_6
+            (joined
+              (portRef Q (instanceRef FF_21))
+              (portRef ADA10 (instanceRef pdp_ram_0_0_0))))
+          (net wptr_7
+            (joined
+              (portRef Q (instanceRef FF_20))
+              (portRef ADA11 (instanceRef pdp_ram_0_0_0))))
+          (net wptr_8
+            (joined
+              (portRef Q (instanceRef FF_19))))
+          (net rptr_8
+            (joined
+              (portRef Q (instanceRef FF_10))
+              (portRef B (instanceRef XOR2_t0))))
+          (net ifcount_0
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_0))
+              (portRef D (instanceRef FF_56))))
+          (net ifcount_1
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_0))
+              (portRef D (instanceRef FF_55))))
+          (net bdcnt_bctr_ci
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_0))
+              (portRef COUT (instanceRef bdcnt_bctr_cia))))
+          (net ifcount_2
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_1))
+              (portRef D (instanceRef FF_54))))
+          (net ifcount_3
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_1))
+              (portRef D (instanceRef FF_53))))
+          (net co0
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_1))
+              (portRef COUT (instanceRef bdcnt_bctr_0))))
+          (net ifcount_4
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_2))
+              (portRef D (instanceRef FF_52))))
+          (net ifcount_5
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_2))
+              (portRef D (instanceRef FF_51))))
+          (net co1
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_2))
+              (portRef COUT (instanceRef bdcnt_bctr_1))))
+          (net ifcount_6
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_3))
+              (portRef D (instanceRef FF_50))))
+          (net ifcount_7
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_3))
+              (portRef D (instanceRef FF_49))))
+          (net co2
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_3))
+              (portRef COUT (instanceRef bdcnt_bctr_2))))
+          (net ifcount_8
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_4))
+              (portRef D (instanceRef FF_48))))
+          (net co4
+            (joined
+              (portRef COUT (instanceRef bdcnt_bctr_4))))
+          (net co3
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_4))
+              (portRef COUT (instanceRef bdcnt_bctr_3))))
+          (net cmp_ci
+            (joined
+              (portRef CIN (instanceRef e_cmp_0))
+              (portRef COUT (instanceRef e_cmp_ci_a))))
+          (net rden_i
+            (joined
+              (portRef A0 (instanceRef e_cmp_0))
+              (portRef Z (instanceRef AND2_t4))
+              (portRef B (instanceRef XOR2_t2))
+              (portRef A (instanceRef INV_3))
+              (portRef AD1 (instanceRef LUT4_0))
+              (portRef A (instanceRef AND2_t1))
+              (portRef CEB (instanceRef pdp_ram_0_0_0))
+              (portRef SP (instanceRef FF_36))
+              (portRef SP (instanceRef FF_35))
+              (portRef SP (instanceRef FF_34))
+              (portRef SP (instanceRef FF_33))
+              (portRef SP (instanceRef FF_32))
+              (portRef SP (instanceRef FF_31))
+              (portRef SP (instanceRef FF_30))
+              (portRef SP (instanceRef FF_29))
+              (portRef SP (instanceRef FF_28))
+              (portRef SP (instanceRef FF_18))
+              (portRef SP (instanceRef FF_17))
+              (portRef SP (instanceRef FF_16))
+              (portRef SP (instanceRef FF_15))
+              (portRef SP (instanceRef FF_14))
+              (portRef SP (instanceRef FF_13))
+              (portRef SP (instanceRef FF_12))
+              (portRef SP (instanceRef FF_11))
+              (portRef SP (instanceRef FF_10))))
+          (net co0_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_1))
+              (portRef COUT (instanceRef e_cmp_0))))
+          (net co1_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_2))
+              (portRef COUT (instanceRef e_cmp_1))))
+          (net co2_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_3))
+              (portRef COUT (instanceRef e_cmp_2))))
+          (net co3_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_4))
+              (portRef COUT (instanceRef e_cmp_3))))
+          (net cmp_le_1
+            (joined
+              (portRef S0 (instanceRef a0))
+              (portRef AD2 (instanceRef LUT4_1))))
+          (net cmp_le_1_c
+            (joined
+              (portRef CIN (instanceRef a0))
+              (portRef COUT (instanceRef e_cmp_4))))
+          (net cmp_ci_1
+            (joined
+              (portRef CIN (instanceRef g_cmp_0))
+              (portRef COUT (instanceRef g_cmp_ci_a))))
+          (net co0_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_1))
+              (portRef COUT (instanceRef g_cmp_0))))
+          (net co1_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_2))
+              (portRef COUT (instanceRef g_cmp_1))))
+          (net co2_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_3))
+              (portRef COUT (instanceRef g_cmp_2))))
+          (net co3_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_4))
+              (portRef COUT (instanceRef g_cmp_3))))
+          (net wren_i_inv
+            (joined
+              (portRef B0 (instanceRef g_cmp_4))
+              (portRef Z (instanceRef INV_2))))
+          (net cmp_ge_d1
+            (joined
+              (portRef S0 (instanceRef a1))
+              (portRef AD2 (instanceRef LUT4_0))))
+          (net cmp_ge_d1_c
+            (joined
+              (portRef CIN (instanceRef a1))
+              (portRef COUT (instanceRef g_cmp_4))))
+          (net iwcount_0
+            (joined
+              (portRef S0 (instanceRef w_ctr_0))
+              (portRef D (instanceRef FF_45))))
+          (net iwcount_1
+            (joined
+              (portRef S1 (instanceRef w_ctr_0))
+              (portRef D (instanceRef FF_44))))
+          (net w_ctr_ci
+            (joined
+              (portRef CIN (instanceRef w_ctr_0))
+              (portRef COUT (instanceRef w_ctr_cia))))
+          (net iwcount_2
+            (joined
+              (portRef S0 (instanceRef w_ctr_1))
+              (portRef D (instanceRef FF_43))))
+          (net iwcount_3
+            (joined
+              (portRef S1 (instanceRef w_ctr_1))
+              (portRef D (instanceRef FF_42))))
+          (net co0_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_1))
+              (portRef COUT (instanceRef w_ctr_0))))
+          (net iwcount_4
+            (joined
+              (portRef S0 (instanceRef w_ctr_2))
+              (portRef D (instanceRef FF_41))))
+          (net iwcount_5
+            (joined
+              (portRef S1 (instanceRef w_ctr_2))
+              (portRef D (instanceRef FF_40))))
+          (net co1_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_2))
+              (portRef COUT (instanceRef w_ctr_1))))
+          (net iwcount_6
+            (joined
+              (portRef S0 (instanceRef w_ctr_3))
+              (portRef D (instanceRef FF_39))))
+          (net iwcount_7
+            (joined
+              (portRef S1 (instanceRef w_ctr_3))
+              (portRef D (instanceRef FF_38))))
+          (net co2_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_3))
+              (portRef COUT (instanceRef w_ctr_2))))
+          (net iwcount_8
+            (joined
+              (portRef S0 (instanceRef w_ctr_4))
+              (portRef D (instanceRef FF_37))))
+          (net co4_1
+            (joined
+              (portRef COUT (instanceRef w_ctr_4))))
+          (net co3_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_4))
+              (portRef COUT (instanceRef w_ctr_3))))
+          (net wcount_8
+            (joined
+              (portRef A0 (instanceRef w_ctr_4))
+              (portRef A (instanceRef XOR2_t0))
+              (portRef Q (instanceRef FF_37))
+              (portRef D (instanceRef FF_19))))
+          (net ircount_0
+            (joined
+              (portRef S0 (instanceRef r_ctr_0))
+              (portRef D (instanceRef FF_36))))
+          (net ircount_1
+            (joined
+              (portRef S1 (instanceRef r_ctr_0))
+              (portRef D (instanceRef FF_35))))
+          (net r_ctr_ci
+            (joined
+              (portRef CIN (instanceRef r_ctr_0))
+              (portRef COUT (instanceRef r_ctr_cia))))
+          (net rcount_0
+            (joined
+              (portRef A0 (instanceRef r_ctr_0))
+              (portRef Q (instanceRef FF_36))
+              (portRef D (instanceRef FF_18))))
+          (net rcount_1
+            (joined
+              (portRef A1 (instanceRef r_ctr_0))
+              (portRef Q (instanceRef FF_35))
+              (portRef D (instanceRef FF_17))))
+          (net ircount_2
+            (joined
+              (portRef S0 (instanceRef r_ctr_1))
+              (portRef D (instanceRef FF_34))))
+          (net ircount_3
+            (joined
+              (portRef S1 (instanceRef r_ctr_1))
+              (portRef D (instanceRef FF_33))))
+          (net co0_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_1))
+              (portRef COUT (instanceRef r_ctr_0))))
+          (net rcount_2
+            (joined
+              (portRef A0 (instanceRef r_ctr_1))
+              (portRef Q (instanceRef FF_34))
+              (portRef D (instanceRef FF_16))))
+          (net rcount_3
+            (joined
+              (portRef A1 (instanceRef r_ctr_1))
+              (portRef Q (instanceRef FF_33))
+              (portRef D (instanceRef FF_15))))
+          (net ircount_4
+            (joined
+              (portRef S0 (instanceRef r_ctr_2))
+              (portRef D (instanceRef FF_32))))
+          (net ircount_5
+            (joined
+              (portRef S1 (instanceRef r_ctr_2))
+              (portRef D (instanceRef FF_31))))
+          (net co1_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_2))
+              (portRef COUT (instanceRef r_ctr_1))))
+          (net rcount_4
+            (joined
+              (portRef A0 (instanceRef r_ctr_2))
+              (portRef Q (instanceRef FF_32))
+              (portRef D (instanceRef FF_14))))
+          (net rcount_5
+            (joined
+              (portRef A1 (instanceRef r_ctr_2))
+              (portRef Q (instanceRef FF_31))
+              (portRef D (instanceRef FF_13))))
+          (net ircount_6
+            (joined
+              (portRef S0 (instanceRef r_ctr_3))
+              (portRef D (instanceRef FF_30))))
+          (net ircount_7
+            (joined
+              (portRef S1 (instanceRef r_ctr_3))
+              (portRef D (instanceRef FF_29))))
+          (net co2_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_3))
+              (portRef COUT (instanceRef r_ctr_2))))
+          (net rcount_6
+            (joined
+              (portRef A0 (instanceRef r_ctr_3))
+              (portRef Q (instanceRef FF_30))
+              (portRef D (instanceRef FF_12))))
+          (net rcount_7
+            (joined
+              (portRef A1 (instanceRef r_ctr_3))
+              (portRef Q (instanceRef FF_29))
+              (portRef D (instanceRef FF_11))))
+          (net ircount_8
+            (joined
+              (portRef S0 (instanceRef r_ctr_4))
+              (portRef D (instanceRef FF_28))))
+          (net co4_2
+            (joined
+              (portRef COUT (instanceRef r_ctr_4))))
+          (net co3_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_4))
+              (portRef COUT (instanceRef r_ctr_3))))
+          (net rcount_8
+            (joined
+              (portRef A0 (instanceRef r_ctr_4))
+              (portRef Q (instanceRef FF_28))
+              (portRef D (instanceRef FF_10))))
+          (net wcnt_sub_0
+            (joined
+              (portRef S1 (instanceRef wcnt_0))
+              (portRef D (instanceRef FF_9))))
+          (net rptr_0
+            (joined
+              (portRef B1 (instanceRef wcnt_0))
+              (portRef ADB4 (instanceRef pdp_ram_0_0_0))
+              (portRef Q (instanceRef FF_18))))
+          (net cnt_con_inv
+            (joined
+              (portRef B0 (instanceRef wcnt_0))
+              (portRef Z (instanceRef INV_0))))
+          (net wcount_0
+            (joined
+              (portRef A1 (instanceRef wcnt_0))
+              (portRef Q (instanceRef FF_45))
+              (portRef D (instanceRef FF_27))
+              (portRef A0 (instanceRef w_ctr_0))))
+          (net cnt_con
+            (joined
+              (portRef A0 (instanceRef wcnt_0))
+              (portRef Z (instanceRef AND2_t3))
+              (portRef A (instanceRef INV_0))
+              (portRef B1 (instanceRef bdcnt_bctr_cia))
+              (portRef A1 (instanceRef bdcnt_bctr_cia))
+              (portRef B1 (instanceRef bdcnt_bctr_0))
+              (portRef B0 (instanceRef bdcnt_bctr_0))
+              (portRef B1 (instanceRef bdcnt_bctr_1))
+              (portRef B0 (instanceRef bdcnt_bctr_1))
+              (portRef B1 (instanceRef bdcnt_bctr_2))
+              (portRef B0 (instanceRef bdcnt_bctr_2))
+              (portRef B1 (instanceRef bdcnt_bctr_3))
+              (portRef B0 (instanceRef bdcnt_bctr_3))
+              (portRef B1 (instanceRef bdcnt_bctr_4))
+              (portRef B0 (instanceRef bdcnt_bctr_4))))
+          (net precin
+            (joined
+              (portRef CIN (instanceRef wcnt_0))
+              (portRef COUT (instanceRef precin_inst207))))
+          (net wcnt_sub_1
+            (joined
+              (portRef S0 (instanceRef wcnt_1))
+              (portRef D (instanceRef FF_8))))
+          (net wcnt_sub_2
+            (joined
+              (portRef S1 (instanceRef wcnt_1))
+              (portRef D (instanceRef FF_7))))
+          (net rptr_2
+            (joined
+              (portRef B1 (instanceRef wcnt_1))
+              (portRef ADB6 (instanceRef pdp_ram_0_0_0))
+              (portRef Q (instanceRef FF_16))))
+          (net rptr_1
+            (joined
+              (portRef B0 (instanceRef wcnt_1))
+              (portRef ADB5 (instanceRef pdp_ram_0_0_0))
+              (portRef Q (instanceRef FF_17))))
+          (net wcount_2
+            (joined
+              (portRef A1 (instanceRef wcnt_1))
+              (portRef Q (instanceRef FF_43))
+              (portRef D (instanceRef FF_25))
+              (portRef A0 (instanceRef w_ctr_1))))
+          (net wcount_1
+            (joined
+              (portRef A0 (instanceRef wcnt_1))
+              (portRef Q (instanceRef FF_44))
+              (portRef D (instanceRef FF_26))
+              (portRef A1 (instanceRef w_ctr_0))))
+          (net co0_5
+            (joined
+              (portRef CIN (instanceRef wcnt_1))
+              (portRef COUT (instanceRef wcnt_0))))
+          (net wcnt_sub_3
+            (joined
+              (portRef S0 (instanceRef wcnt_2))
+              (portRef D (instanceRef FF_6))))
+          (net wcnt_sub_4
+            (joined
+              (portRef S1 (instanceRef wcnt_2))
+              (portRef D (instanceRef FF_5))))
+          (net rptr_4
+            (joined
+              (portRef B1 (instanceRef wcnt_2))
+              (portRef ADB8 (instanceRef pdp_ram_0_0_0))
+              (portRef Q (instanceRef FF_14))))
+          (net rptr_3
+            (joined
+              (portRef B0 (instanceRef wcnt_2))
+              (portRef ADB7 (instanceRef pdp_ram_0_0_0))
+              (portRef Q (instanceRef FF_15))))
+          (net wcount_4
+            (joined
+              (portRef A1 (instanceRef wcnt_2))
+              (portRef Q (instanceRef FF_41))
+              (portRef D (instanceRef FF_23))
+              (portRef A0 (instanceRef w_ctr_2))))
+          (net wcount_3
+            (joined
+              (portRef A0 (instanceRef wcnt_2))
+              (portRef Q (instanceRef FF_42))
+              (portRef D (instanceRef FF_24))
+              (portRef A1 (instanceRef w_ctr_1))))
+          (net co1_5
+            (joined
+              (portRef CIN (instanceRef wcnt_2))
+              (portRef COUT (instanceRef wcnt_1))))
+          (net wcnt_sub_5
+            (joined
+              (portRef S0 (instanceRef wcnt_3))
+              (portRef D (instanceRef FF_4))))
+          (net wcnt_sub_6
+            (joined
+              (portRef S1 (instanceRef wcnt_3))
+              (portRef D (instanceRef FF_3))))
+          (net rptr_6
+            (joined
+              (portRef B1 (instanceRef wcnt_3))
+              (portRef ADB10 (instanceRef pdp_ram_0_0_0))
+              (portRef Q (instanceRef FF_12))))
+          (net rptr_5
+            (joined
+              (portRef B0 (instanceRef wcnt_3))
+              (portRef ADB9 (instanceRef pdp_ram_0_0_0))
+              (portRef Q (instanceRef FF_13))))
+          (net wcount_6
+            (joined
+              (portRef A1 (instanceRef wcnt_3))
+              (portRef Q (instanceRef FF_39))
+              (portRef D (instanceRef FF_21))
+              (portRef A0 (instanceRef w_ctr_3))))
+          (net wcount_5
+            (joined
+              (portRef A0 (instanceRef wcnt_3))
+              (portRef Q (instanceRef FF_40))
+              (portRef D (instanceRef FF_22))
+              (portRef A1 (instanceRef w_ctr_2))))
+          (net co2_5
+            (joined
+              (portRef CIN (instanceRef wcnt_3))
+              (portRef COUT (instanceRef wcnt_2))))
+          (net wcnt_sub_7
+            (joined
+              (portRef S0 (instanceRef wcnt_4))
+              (portRef D (instanceRef FF_2))))
+          (net wcnt_sub_8
+            (joined
+              (portRef S1 (instanceRef wcnt_4))
+              (portRef D (instanceRef FF_1))))
+          (net rptr_7
+            (joined
+              (portRef B0 (instanceRef wcnt_4))
+              (portRef ADB11 (instanceRef pdp_ram_0_0_0))
+              (portRef Q (instanceRef FF_11))))
+          (net wcnt_sub_msb
+            (joined
+              (portRef A1 (instanceRef wcnt_4))
+              (portRef Z (instanceRef XOR2_t0))))
+          (net wcount_7
+            (joined
+              (portRef A0 (instanceRef wcnt_4))
+              (portRef Q (instanceRef FF_38))
+              (portRef D (instanceRef FF_20))
+              (portRef A1 (instanceRef w_ctr_3))))
+          (net co3_5
+            (joined
+              (portRef CIN (instanceRef wcnt_4))
+              (portRef COUT (instanceRef wcnt_3))))
+          (net co4_3d
+            (joined
+              (portRef S0 (instanceRef wcntd))))
+          (net co4_3
+            (joined
+              (portRef CIN (instanceRef wcntd))
+              (portRef COUT (instanceRef wcnt_4))))
+          (net wren_i
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_ci_a))
+              (portRef Z (instanceRef AND2_t5))
+              (portRef A (instanceRef AND2_t3))
+              (portRef A (instanceRef XOR2_t2))
+              (portRef A (instanceRef INV_2))
+              (portRef AD1 (instanceRef LUT4_1))
+              (portRef A (instanceRef INV_1))
+              (portRef OCEA (instanceRef pdp_ram_0_0_0))
+              (portRef CEA (instanceRef pdp_ram_0_0_0))
+              (portRef SP (instanceRef FF_45))
+              (portRef SP (instanceRef FF_44))
+              (portRef SP (instanceRef FF_43))
+              (portRef SP (instanceRef FF_42))
+              (portRef SP (instanceRef FF_41))
+              (portRef SP (instanceRef FF_40))
+              (portRef SP (instanceRef FF_39))
+              (portRef SP (instanceRef FF_38))
+              (portRef SP (instanceRef FF_37))
+              (portRef SP (instanceRef FF_27))
+              (portRef SP (instanceRef FF_26))
+              (portRef SP (instanceRef FF_25))
+              (portRef SP (instanceRef FF_24))
+              (portRef SP (instanceRef FF_23))
+              (portRef SP (instanceRef FF_22))
+              (portRef SP (instanceRef FF_21))
+              (portRef SP (instanceRef FF_20))
+              (portRef SP (instanceRef FF_19))
+              (portRef B0 (instanceRef g_cmp_0))
+              (portRef B1 (instanceRef g_cmp_0))
+              (portRef B0 (instanceRef g_cmp_1))
+              (portRef B1 (instanceRef g_cmp_1))
+              (portRef B0 (instanceRef g_cmp_2))
+              (portRef B1 (instanceRef g_cmp_2))
+              (portRef B0 (instanceRef g_cmp_3))
+              (portRef B1 (instanceRef g_cmp_3))
+              (portRef B1 (instanceRef af_set_cmp_ci_a))))
+          (net x
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_ci_a))
+              (portRef CIN (instanceRef bdcnt_bctr_cia))
+              (portRef CIN (instanceRef e_cmp_ci_a))
+              (portRef CIN (instanceRef g_cmp_ci_a))
+              (portRef CIN (instanceRef w_ctr_cia))
+              (portRef CIN (instanceRef r_ctr_cia))
+              (portRef CIN (instanceRef precin_inst207))))
+          (net cmp_ci_2
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_0))
+              (portRef COUT (instanceRef af_set_cmp_ci_a))))
+          (net wcnt_reg_0
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_0))
+              (portRef Q (instanceRef FF_9))))
+          (net wcnt_reg_1
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_0))
+              (portRef Q (instanceRef FF_8))))
+          (net co0_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_1))
+              (portRef COUT (instanceRef af_set_cmp_0))))
+          (net wcnt_reg_2
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_1))
+              (portRef Q (instanceRef FF_7))))
+          (net wcnt_reg_3
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_1))
+              (portRef Q (instanceRef FF_6))))
+          (net co1_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_2))
+              (portRef COUT (instanceRef af_set_cmp_1))))
+          (net wcnt_reg_4
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_2))
+              (portRef Q (instanceRef FF_5))))
+          (net wcnt_reg_5
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_2))
+              (portRef Q (instanceRef FF_4))))
+          (net co2_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_3))
+              (portRef COUT (instanceRef af_set_cmp_2))))
+          (net wcnt_reg_6
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_3))
+              (portRef Q (instanceRef FF_3))))
+          (net wcnt_reg_7
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_3))
+              (portRef Q (instanceRef FF_2))))
+          (net co3_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_4))
+              (portRef COUT (instanceRef af_set_cmp_3))))
+          (net wcnt_reg_8
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_4))
+              (portRef Q (instanceRef FF_1))))
+          (net af_set
+            (joined
+              (portRef S0 (instanceRef a2))
+              (portRef D (instanceRef FF_0))))
+          (net scuba_vhi
+            (joined
+              (portRef Z (instanceRef scuba_vhi_inst))
+              (portRef OCEB (instanceRef pdp_ram_0_0_0))
+              (portRef WEA (instanceRef pdp_ram_0_0_0))
+              (portRef ADA1 (instanceRef pdp_ram_0_0_0))
+              (portRef ADA0 (instanceRef pdp_ram_0_0_0))
+              (portRef C1 (instanceRef bdcnt_bctr_cia))
+              (portRef C0 (instanceRef bdcnt_bctr_cia))
+              (portRef D1 (instanceRef bdcnt_bctr_cia))
+              (portRef D0 (instanceRef bdcnt_bctr_cia))
+              (portRef D1 (instanceRef bdcnt_bctr_0))
+              (portRef D0 (instanceRef bdcnt_bctr_0))
+              (portRef C1 (instanceRef bdcnt_bctr_0))
+              (portRef C0 (instanceRef bdcnt_bctr_0))
+              (portRef D1 (instanceRef bdcnt_bctr_1))
+              (portRef D0 (instanceRef bdcnt_bctr_1))
+              (portRef C1 (instanceRef bdcnt_bctr_1))
+              (portRef C0 (instanceRef bdcnt_bctr_1))
+              (portRef D1 (instanceRef bdcnt_bctr_2))
+              (portRef D0 (instanceRef bdcnt_bctr_2))
+              (portRef C1 (instanceRef bdcnt_bctr_2))
+              (portRef C0 (instanceRef bdcnt_bctr_2))
+              (portRef D1 (instanceRef bdcnt_bctr_3))
+              (portRef D0 (instanceRef bdcnt_bctr_3))
+              (portRef C1 (instanceRef bdcnt_bctr_3))
+              (portRef C0 (instanceRef bdcnt_bctr_3))
+              (portRef D1 (instanceRef bdcnt_bctr_4))
+              (portRef D0 (instanceRef bdcnt_bctr_4))
+              (portRef C1 (instanceRef bdcnt_bctr_4))
+              (portRef C0 (instanceRef bdcnt_bctr_4))
+              (portRef C1 (instanceRef e_cmp_ci_a))
+              (portRef C0 (instanceRef e_cmp_ci_a))
+              (portRef D1 (instanceRef e_cmp_ci_a))
+              (portRef D0 (instanceRef e_cmp_ci_a))
+              (portRef B1 (instanceRef e_cmp_ci_a))
+              (portRef B0 (instanceRef e_cmp_ci_a))
+              (portRef A1 (instanceRef e_cmp_ci_a))
+              (portRef A0 (instanceRef e_cmp_ci_a))
+              (portRef D1 (instanceRef e_cmp_0))
+              (portRef D0 (instanceRef e_cmp_0))
+              (portRef C1 (instanceRef e_cmp_0))
+              (portRef C0 (instanceRef e_cmp_0))
+              (portRef D1 (instanceRef e_cmp_1))
+              (portRef D0 (instanceRef e_cmp_1))
+              (portRef C1 (instanceRef e_cmp_1))
+              (portRef C0 (instanceRef e_cmp_1))
+              (portRef D1 (instanceRef e_cmp_2))
+              (portRef D0 (instanceRef e_cmp_2))
+              (portRef C1 (instanceRef e_cmp_2))
+              (portRef C0 (instanceRef e_cmp_2))
+              (portRef D1 (instanceRef e_cmp_3))
+              (portRef D0 (instanceRef e_cmp_3))
+              (portRef C1 (instanceRef e_cmp_3))
+              (portRef C0 (instanceRef e_cmp_3))
+              (portRef D1 (instanceRef e_cmp_4))
+              (portRef D0 (instanceRef e_cmp_4))
+              (portRef C1 (instanceRef e_cmp_4))
+              (portRef C0 (instanceRef e_cmp_4))
+              (portRef C1 (instanceRef a0))
+              (portRef C0 (instanceRef a0))
+              (portRef D1 (instanceRef a0))
+              (portRef D0 (instanceRef a0))
+              (portRef C1 (instanceRef g_cmp_ci_a))
+              (portRef C0 (instanceRef g_cmp_ci_a))
+              (portRef D1 (instanceRef g_cmp_ci_a))
+              (portRef D0 (instanceRef g_cmp_ci_a))
+              (portRef B1 (instanceRef g_cmp_ci_a))
+              (portRef B0 (instanceRef g_cmp_ci_a))
+              (portRef A1 (instanceRef g_cmp_ci_a))
+              (portRef A0 (instanceRef g_cmp_ci_a))
+              (portRef D1 (instanceRef g_cmp_0))
+              (portRef D0 (instanceRef g_cmp_0))
+              (portRef C1 (instanceRef g_cmp_0))
+              (portRef C0 (instanceRef g_cmp_0))
+              (portRef D1 (instanceRef g_cmp_1))
+              (portRef D0 (instanceRef g_cmp_1))
+              (portRef C1 (instanceRef g_cmp_1))
+              (portRef C0 (instanceRef g_cmp_1))
+              (portRef D1 (instanceRef g_cmp_2))
+              (portRef D0 (instanceRef g_cmp_2))
+              (portRef C1 (instanceRef g_cmp_2))
+              (portRef C0 (instanceRef g_cmp_2))
+              (portRef D1 (instanceRef g_cmp_3))
+              (portRef D0 (instanceRef g_cmp_3))
+              (portRef C1 (instanceRef g_cmp_3))
+              (portRef C0 (instanceRef g_cmp_3))
+              (portRef D1 (instanceRef g_cmp_4))
+              (portRef D0 (instanceRef g_cmp_4))
+              (portRef C1 (instanceRef g_cmp_4))
+              (portRef C0 (instanceRef g_cmp_4))
+              (portRef C1 (instanceRef a1))
+              (portRef C0 (instanceRef a1))
+              (portRef D1 (instanceRef a1))
+              (portRef D0 (instanceRef a1))
+              (portRef C1 (instanceRef w_ctr_cia))
+              (portRef C0 (instanceRef w_ctr_cia))
+              (portRef D1 (instanceRef w_ctr_cia))
+              (portRef D0 (instanceRef w_ctr_cia))
+              (portRef B1 (instanceRef w_ctr_cia))
+              (portRef A1 (instanceRef w_ctr_cia))
+              (portRef D1 (instanceRef w_ctr_0))
+              (portRef D0 (instanceRef w_ctr_0))
+              (portRef C1 (instanceRef w_ctr_0))
+              (portRef C0 (instanceRef w_ctr_0))
+              (portRef D1 (instanceRef w_ctr_1))
+              (portRef D0 (instanceRef w_ctr_1))
+              (portRef C1 (instanceRef w_ctr_1))
+              (portRef C0 (instanceRef w_ctr_1))
+              (portRef D1 (instanceRef w_ctr_2))
+              (portRef D0 (instanceRef w_ctr_2))
+              (portRef C1 (instanceRef w_ctr_2))
+              (portRef C0 (instanceRef w_ctr_2))
+              (portRef D1 (instanceRef w_ctr_3))
+              (portRef D0 (instanceRef w_ctr_3))
+              (portRef C1 (instanceRef w_ctr_3))
+              (portRef C0 (instanceRef w_ctr_3))
+              (portRef D1 (instanceRef w_ctr_4))
+              (portRef D0 (instanceRef w_ctr_4))
+              (portRef C1 (instanceRef w_ctr_4))
+              (portRef C0 (instanceRef w_ctr_4))
+              (portRef C1 (instanceRef r_ctr_cia))
+              (portRef C0 (instanceRef r_ctr_cia))
+              (portRef D1 (instanceRef r_ctr_cia))
+              (portRef D0 (instanceRef r_ctr_cia))
+              (portRef B1 (instanceRef r_ctr_cia))
+              (portRef A1 (instanceRef r_ctr_cia))
+              (portRef D1 (instanceRef r_ctr_0))
+              (portRef D0 (instanceRef r_ctr_0))
+              (portRef C1 (instanceRef r_ctr_0))
+              (portRef C0 (instanceRef r_ctr_0))
+              (portRef D1 (instanceRef r_ctr_1))
+              (portRef D0 (instanceRef r_ctr_1))
+              (portRef C1 (instanceRef r_ctr_1))
+              (portRef C0 (instanceRef r_ctr_1))
+              (portRef D1 (instanceRef r_ctr_2))
+              (portRef D0 (instanceRef r_ctr_2))
+              (portRef C1 (instanceRef r_ctr_2))
+              (portRef C0 (instanceRef r_ctr_2))
+              (portRef D1 (instanceRef r_ctr_3))
+              (portRef D0 (instanceRef r_ctr_3))
+              (portRef C1 (instanceRef r_ctr_3))
+              (portRef C0 (instanceRef r_ctr_3))
+              (portRef D1 (instanceRef r_ctr_4))
+              (portRef D0 (instanceRef r_ctr_4))
+              (portRef C1 (instanceRef r_ctr_4))
+              (portRef C0 (instanceRef r_ctr_4))
+              (portRef C1 (instanceRef precin_inst207))
+              (portRef C0 (instanceRef precin_inst207))
+              (portRef D1 (instanceRef precin_inst207))
+              (portRef D0 (instanceRef precin_inst207))
+              (portRef B1 (instanceRef precin_inst207))
+              (portRef B0 (instanceRef precin_inst207))
+              (portRef A1 (instanceRef precin_inst207))
+              (portRef A0 (instanceRef precin_inst207))
+              (portRef C1 (instanceRef wcnt_0))
+              (portRef C0 (instanceRef wcnt_0))
+              (portRef D1 (instanceRef wcnt_0))
+              (portRef D0 (instanceRef wcnt_0))
+              (portRef C1 (instanceRef wcnt_1))
+              (portRef C0 (instanceRef wcnt_1))
+              (portRef D1 (instanceRef wcnt_1))
+              (portRef D0 (instanceRef wcnt_1))
+              (portRef C1 (instanceRef wcnt_2))
+              (portRef C0 (instanceRef wcnt_2))
+              (portRef D1 (instanceRef wcnt_2))
+              (portRef D0 (instanceRef wcnt_2))
+              (portRef C1 (instanceRef wcnt_3))
+              (portRef C0 (instanceRef wcnt_3))
+              (portRef D1 (instanceRef wcnt_3))
+              (portRef D0 (instanceRef wcnt_3))
+              (portRef C1 (instanceRef wcnt_4))
+              (portRef C0 (instanceRef wcnt_4))
+              (portRef D1 (instanceRef wcnt_4))
+              (portRef D0 (instanceRef wcnt_4))
+              (portRef C1 (instanceRef wcntd))
+              (portRef C0 (instanceRef wcntd))
+              (portRef D1 (instanceRef wcntd))
+              (portRef D0 (instanceRef wcntd))
+              (portRef C1 (instanceRef af_set_cmp_ci_a))
+              (portRef C0 (instanceRef af_set_cmp_ci_a))
+              (portRef D1 (instanceRef af_set_cmp_ci_a))
+              (portRef D0 (instanceRef af_set_cmp_ci_a))
+              (portRef D1 (instanceRef af_set_cmp_0))
+              (portRef D0 (instanceRef af_set_cmp_0))
+              (portRef C1 (instanceRef af_set_cmp_0))
+              (portRef C0 (instanceRef af_set_cmp_0))
+              (portRef D1 (instanceRef af_set_cmp_1))
+              (portRef D0 (instanceRef af_set_cmp_1))
+              (portRef C1 (instanceRef af_set_cmp_1))
+              (portRef C0 (instanceRef af_set_cmp_1))
+              (portRef D1 (instanceRef af_set_cmp_2))
+              (portRef D0 (instanceRef af_set_cmp_2))
+              (portRef C1 (instanceRef af_set_cmp_2))
+              (portRef C0 (instanceRef af_set_cmp_2))
+              (portRef D1 (instanceRef af_set_cmp_3))
+              (portRef D0 (instanceRef af_set_cmp_3))
+              (portRef C1 (instanceRef af_set_cmp_3))
+              (portRef C0 (instanceRef af_set_cmp_3))
+              (portRef D1 (instanceRef af_set_cmp_4))
+              (portRef D0 (instanceRef af_set_cmp_4))
+              (portRef C1 (instanceRef af_set_cmp_4))
+              (portRef C0 (instanceRef af_set_cmp_4))
+              (portRef C1 (instanceRef a2))
+              (portRef C0 (instanceRef a2))
+              (portRef D1 (instanceRef a2))
+              (portRef D0 (instanceRef a2))))
+          (net scuba_vlo
+            (joined
+              (portRef Z (instanceRef scuba_vlo_inst))
+              (portRef AD3 (instanceRef LUT4_1))
+              (portRef AD3 (instanceRef LUT4_0))
+              (portRef CSB2 (instanceRef pdp_ram_0_0_0))
+              (portRef CSA2 (instanceRef pdp_ram_0_0_0))
+              (portRef CSB1 (instanceRef pdp_ram_0_0_0))
+              (portRef CSA1 (instanceRef pdp_ram_0_0_0))
+              (portRef CSB0 (instanceRef pdp_ram_0_0_0))
+              (portRef CSA0 (instanceRef pdp_ram_0_0_0))
+              (portRef WEB (instanceRef pdp_ram_0_0_0))
+              (portRef ADB13 (instanceRef pdp_ram_0_0_0))
+              (portRef ADA13 (instanceRef pdp_ram_0_0_0))
+              (portRef ADB12 (instanceRef pdp_ram_0_0_0))
+              (portRef ADA12 (instanceRef pdp_ram_0_0_0))
+              (portRef ADB3 (instanceRef pdp_ram_0_0_0))
+              (portRef ADA3 (instanceRef pdp_ram_0_0_0))
+              (portRef ADB2 (instanceRef pdp_ram_0_0_0))
+              (portRef ADA2 (instanceRef pdp_ram_0_0_0))
+              (portRef ADB1 (instanceRef pdp_ram_0_0_0))
+              (portRef ADB0 (instanceRef pdp_ram_0_0_0))
+              (portRef DIB17 (instanceRef pdp_ram_0_0_0))
+              (portRef DIB16 (instanceRef pdp_ram_0_0_0))
+              (portRef DIB15 (instanceRef pdp_ram_0_0_0))
+              (portRef DIB14 (instanceRef pdp_ram_0_0_0))
+              (portRef DIB13 (instanceRef pdp_ram_0_0_0))
+              (portRef DIB12 (instanceRef pdp_ram_0_0_0))
+              (portRef DIB11 (instanceRef pdp_ram_0_0_0))
+              (portRef DIB10 (instanceRef pdp_ram_0_0_0))
+              (portRef DIB9 (instanceRef pdp_ram_0_0_0))
+              (portRef DIB8 (instanceRef pdp_ram_0_0_0))
+              (portRef DIB7 (instanceRef pdp_ram_0_0_0))
+              (portRef DIB6 (instanceRef pdp_ram_0_0_0))
+              (portRef DIB5 (instanceRef pdp_ram_0_0_0))
+              (portRef DIB4 (instanceRef pdp_ram_0_0_0))
+              (portRef DIB3 (instanceRef pdp_ram_0_0_0))
+              (portRef DIB2 (instanceRef pdp_ram_0_0_0))
+              (portRef DIB1 (instanceRef pdp_ram_0_0_0))
+              (portRef DIB0 (instanceRef pdp_ram_0_0_0))
+              (portRef B0 (instanceRef bdcnt_bctr_cia))
+              (portRef A0 (instanceRef bdcnt_bctr_cia))
+              (portRef A1 (instanceRef bdcnt_bctr_4))
+              (portRef A1 (instanceRef e_cmp_0))
+              (portRef A0 (instanceRef e_cmp_1))
+              (portRef A1 (instanceRef e_cmp_1))
+              (portRef A0 (instanceRef e_cmp_2))
+              (portRef A1 (instanceRef e_cmp_2))
+              (portRef A0 (instanceRef e_cmp_3))
+              (portRef A1 (instanceRef e_cmp_3))
+              (portRef A0 (instanceRef e_cmp_4))
+              (portRef A1 (instanceRef e_cmp_4))
+              (portRef B1 (instanceRef e_cmp_4))
+              (portRef B1 (instanceRef a0))
+              (portRef B0 (instanceRef a0))
+              (portRef A1 (instanceRef a0))
+              (portRef A0 (instanceRef a0))
+              (portRef B1 (instanceRef g_cmp_4))
+              (portRef A1 (instanceRef g_cmp_4))
+              (portRef B1 (instanceRef a1))
+              (portRef B0 (instanceRef a1))
+              (portRef A1 (instanceRef a1))
+              (portRef A0 (instanceRef a1))
+              (portRef B0 (instanceRef w_ctr_cia))
+              (portRef A0 (instanceRef w_ctr_cia))
+              (portRef B1 (instanceRef w_ctr_0))
+              (portRef B0 (instanceRef w_ctr_0))
+              (portRef B1 (instanceRef w_ctr_1))
+              (portRef B0 (instanceRef w_ctr_1))
+              (portRef B1 (instanceRef w_ctr_2))
+              (portRef B0 (instanceRef w_ctr_2))
+              (portRef B1 (instanceRef w_ctr_3))
+              (portRef B0 (instanceRef w_ctr_3))
+              (portRef B1 (instanceRef w_ctr_4))
+              (portRef B0 (instanceRef w_ctr_4))
+              (portRef A1 (instanceRef w_ctr_4))
+              (portRef B0 (instanceRef r_ctr_cia))
+              (portRef A0 (instanceRef r_ctr_cia))
+              (portRef B1 (instanceRef r_ctr_0))
+              (portRef B0 (instanceRef r_ctr_0))
+              (portRef B1 (instanceRef r_ctr_1))
+              (portRef B0 (instanceRef r_ctr_1))
+              (portRef B1 (instanceRef r_ctr_2))
+              (portRef B0 (instanceRef r_ctr_2))
+              (portRef B1 (instanceRef r_ctr_3))
+              (portRef B0 (instanceRef r_ctr_3))
+              (portRef B1 (instanceRef r_ctr_4))
+              (portRef B0 (instanceRef r_ctr_4))
+              (portRef A1 (instanceRef r_ctr_4))
+              (portRef B1 (instanceRef wcnt_4))
+              (portRef B1 (instanceRef wcntd))
+              (portRef B0 (instanceRef wcntd))
+              (portRef A1 (instanceRef wcntd))
+              (portRef A0 (instanceRef wcntd))
+              (portRef B0 (instanceRef af_set_cmp_ci_a))
+              (portRef A0 (instanceRef af_set_cmp_ci_a))
+              (portRef B0 (instanceRef af_set_cmp_4))
+              (portRef B1 (instanceRef af_set_cmp_4))
+              (portRef A1 (instanceRef af_set_cmp_4))
+              (portRef B1 (instanceRef a2))
+              (portRef B0 (instanceRef a2))
+              (portRef A1 (instanceRef a2))
+              (portRef A0 (instanceRef a2))))
+          (net af_set_c
+            (joined
+              (portRef CIN (instanceRef a2))
+              (portRef COUT (instanceRef af_set_cmp_4))))
+          (net partial_full
+            (joined
+              (portRef AlmostFull)
+              (portRef Q (instanceRef FF_0))))
+          (net Full
+            (joined
+              (portRef Full)
+              (portRef Q (instanceRef FF_46))
+              (portRef A (instanceRef INV_5))
+              (portRef AD0 (instanceRef LUT4_0))))
+          (net Empty
+            (joined
+              (portRef Empty)
+              (portRef Q (instanceRef FF_47))
+              (portRef A (instanceRef INV_4))
+              (portRef AD0 (instanceRef LUT4_1))))
+          (net WCNT8
+            (joined
+              (portRef (member WCNT 0))
+              (portRef A0 (instanceRef g_cmp_4))
+              (portRef Q (instanceRef FF_48))
+              (portRef A0 (instanceRef bdcnt_bctr_4))
+              (portRef B0 (instanceRef e_cmp_4))))
+          (net WCNT7
+            (joined
+              (portRef (member WCNT 1))
+              (portRef A1 (instanceRef g_cmp_3))
+              (portRef Q (instanceRef FF_49))
+              (portRef A1 (instanceRef bdcnt_bctr_3))
+              (portRef B1 (instanceRef e_cmp_3))))
+          (net WCNT6
+            (joined
+              (portRef (member WCNT 2))
+              (portRef A0 (instanceRef g_cmp_3))
+              (portRef Q (instanceRef FF_50))
+              (portRef A0 (instanceRef bdcnt_bctr_3))
+              (portRef B0 (instanceRef e_cmp_3))))
+          (net WCNT5
+            (joined
+              (portRef (member WCNT 3))
+              (portRef A1 (instanceRef g_cmp_2))
+              (portRef Q (instanceRef FF_51))
+              (portRef A1 (instanceRef bdcnt_bctr_2))
+              (portRef B1 (instanceRef e_cmp_2))))
+          (net WCNT4
+            (joined
+              (portRef (member WCNT 4))
+              (portRef A0 (instanceRef g_cmp_2))
+              (portRef Q (instanceRef FF_52))
+              (portRef A0 (instanceRef bdcnt_bctr_2))
+              (portRef B0 (instanceRef e_cmp_2))))
+          (net WCNT3
+            (joined
+              (portRef (member WCNT 5))
+              (portRef A1 (instanceRef g_cmp_1))
+              (portRef Q (instanceRef FF_53))
+              (portRef A1 (instanceRef bdcnt_bctr_1))
+              (portRef B1 (instanceRef e_cmp_1))))
+          (net WCNT2
+            (joined
+              (portRef (member WCNT 6))
+              (portRef A0 (instanceRef g_cmp_1))
+              (portRef Q (instanceRef FF_54))
+              (portRef A0 (instanceRef bdcnt_bctr_1))
+              (portRef B0 (instanceRef e_cmp_1))))
+          (net WCNT1
+            (joined
+              (portRef (member WCNT 7))
+              (portRef A1 (instanceRef g_cmp_0))
+              (portRef Q (instanceRef FF_55))
+              (portRef A1 (instanceRef bdcnt_bctr_0))
+              (portRef B1 (instanceRef e_cmp_0))))
+          (net WCNT0
+            (joined
+              (portRef (member WCNT 8))
+              (portRef A0 (instanceRef g_cmp_0))
+              (portRef Q (instanceRef FF_56))
+              (portRef A0 (instanceRef bdcnt_bctr_0))
+              (portRef B0 (instanceRef e_cmp_0))))
+          (net dataout17
+            (joined
+              (portRef (member Q 0))
+              (portRef DOB17 (instanceRef pdp_ram_0_0_0))))
+          (net dataout16
+            (joined
+              (portRef (member Q 1))
+              (portRef DOB16 (instanceRef pdp_ram_0_0_0))))
+          (net dataout15
+            (joined
+              (portRef (member Q 2))
+              (portRef DOB15 (instanceRef pdp_ram_0_0_0))))
+          (net dataout14
+            (joined
+              (portRef (member Q 3))
+              (portRef DOB14 (instanceRef pdp_ram_0_0_0))))
+          (net dataout13
+            (joined
+              (portRef (member Q 4))
+              (portRef DOB13 (instanceRef pdp_ram_0_0_0))))
+          (net dataout12
+            (joined
+              (portRef (member Q 5))
+              (portRef DOB12 (instanceRef pdp_ram_0_0_0))))
+          (net dataout11
+            (joined
+              (portRef (member Q 6))
+              (portRef DOB11 (instanceRef pdp_ram_0_0_0))))
+          (net dataout10
+            (joined
+              (portRef (member Q 7))
+              (portRef DOB10 (instanceRef pdp_ram_0_0_0))))
+          (net dataout9
+            (joined
+              (portRef (member Q 8))
+              (portRef DOB9 (instanceRef pdp_ram_0_0_0))))
+          (net dataout8
+            (joined
+              (portRef (member Q 9))
+              (portRef DOB8 (instanceRef pdp_ram_0_0_0))))
+          (net dataout7
+            (joined
+              (portRef (member Q 10))
+              (portRef DOB7 (instanceRef pdp_ram_0_0_0))))
+          (net dataout6
+            (joined
+              (portRef (member Q 11))
+              (portRef DOB6 (instanceRef pdp_ram_0_0_0))))
+          (net dataout5
+            (joined
+              (portRef (member Q 12))
+              (portRef DOB5 (instanceRef pdp_ram_0_0_0))))
+          (net dataout4
+            (joined
+              (portRef (member Q 13))
+              (portRef DOB4 (instanceRef pdp_ram_0_0_0))))
+          (net dataout3
+            (joined
+              (portRef (member Q 14))
+              (portRef DOB3 (instanceRef pdp_ram_0_0_0))))
+          (net dataout2
+            (joined
+              (portRef (member Q 15))
+              (portRef DOB2 (instanceRef pdp_ram_0_0_0))))
+          (net dataout1
+            (joined
+              (portRef (member Q 16))
+              (portRef DOB1 (instanceRef pdp_ram_0_0_0))))
+          (net dataout0
+            (joined
+              (portRef (member Q 17))
+              (portRef DOB0 (instanceRef pdp_ram_0_0_0))))
+          (net AmFullThresh7
+            (joined
+              (portRef (member AmFullThresh 0))
+              (portRef B1 (instanceRef af_set_cmp_3))))
+          (net AmFullThresh6
+            (joined
+              (portRef (member AmFullThresh 1))
+              (portRef B0 (instanceRef af_set_cmp_3))))
+          (net AmFullThresh5
+            (joined
+              (portRef (member AmFullThresh 2))
+              (portRef B1 (instanceRef af_set_cmp_2))))
+          (net AmFullThresh4
+            (joined
+              (portRef (member AmFullThresh 3))
+              (portRef B0 (instanceRef af_set_cmp_2))))
+          (net AmFullThresh3
+            (joined
+              (portRef (member AmFullThresh 4))
+              (portRef B1 (instanceRef af_set_cmp_1))))
+          (net AmFullThresh2
+            (joined
+              (portRef (member AmFullThresh 5))
+              (portRef B0 (instanceRef af_set_cmp_1))))
+          (net AmFullThresh1
+            (joined
+              (portRef (member AmFullThresh 6))
+              (portRef B1 (instanceRef af_set_cmp_0))))
+          (net AmFullThresh0
+            (joined
+              (portRef (member AmFullThresh 7))
+              (portRef B0 (instanceRef af_set_cmp_0))))
+          (net reset
+            (joined
+              (portRef Reset)
+              (portRef RSTB (instanceRef pdp_ram_0_0_0))
+              (portRef RSTA (instanceRef pdp_ram_0_0_0))
+              (portRef CD (instanceRef FF_56))
+              (portRef CD (instanceRef FF_55))
+              (portRef CD (instanceRef FF_54))
+              (portRef CD (instanceRef FF_53))
+              (portRef CD (instanceRef FF_52))
+              (portRef CD (instanceRef FF_51))
+              (portRef CD (instanceRef FF_50))
+              (portRef CD (instanceRef FF_49))
+              (portRef CD (instanceRef FF_48))
+              (portRef PD (instanceRef FF_47))
+              (portRef CD (instanceRef FF_46))
+              (portRef PD (instanceRef FF_45))
+              (portRef CD (instanceRef FF_44))
+              (portRef CD (instanceRef FF_43))
+              (portRef CD (instanceRef FF_42))
+              (portRef CD (instanceRef FF_41))
+              (portRef CD (instanceRef FF_40))
+              (portRef CD (instanceRef FF_39))
+              (portRef CD (instanceRef FF_38))
+              (portRef CD (instanceRef FF_37))
+              (portRef PD (instanceRef FF_36))
+              (portRef CD (instanceRef FF_35))
+              (portRef CD (instanceRef FF_34))
+              (portRef CD (instanceRef FF_33))
+              (portRef CD (instanceRef FF_32))
+              (portRef CD (instanceRef FF_31))
+              (portRef CD (instanceRef FF_30))
+              (portRef CD (instanceRef FF_29))
+              (portRef CD (instanceRef FF_28))
+              (portRef CD (instanceRef FF_27))
+              (portRef CD (instanceRef FF_26))
+              (portRef CD (instanceRef FF_25))
+              (portRef CD (instanceRef FF_24))
+              (portRef CD (instanceRef FF_23))
+              (portRef CD (instanceRef FF_22))
+              (portRef CD (instanceRef FF_21))
+              (portRef CD (instanceRef FF_20))
+              (portRef CD (instanceRef FF_19))
+              (portRef CD (instanceRef FF_18))
+              (portRef CD (instanceRef FF_17))
+              (portRef CD (instanceRef FF_16))
+              (portRef CD (instanceRef FF_15))
+              (portRef CD (instanceRef FF_14))
+              (portRef CD (instanceRef FF_13))
+              (portRef CD (instanceRef FF_12))
+              (portRef CD (instanceRef FF_11))
+              (portRef CD (instanceRef FF_10))
+              (portRef CD (instanceRef FF_9))
+              (portRef CD (instanceRef FF_8))
+              (portRef CD (instanceRef FF_7))
+              (portRef CD (instanceRef FF_6))
+              (portRef CD (instanceRef FF_5))
+              (portRef CD (instanceRef FF_4))
+              (portRef CD (instanceRef FF_3))
+              (portRef CD (instanceRef FF_2))
+              (portRef CD (instanceRef FF_1))
+              (portRef CD (instanceRef FF_0))))
+          (net rden
+            (joined
+              (portRef RdEn)
+              (portRef A (instanceRef AND2_t4))))
+          (net wren
+            (joined
+              (portRef WrEn)
+              (portRef A (instanceRef AND2_t5))))
+          (net clk
+            (joined
+              (portRef Clock)
+              (portRef CLKB (instanceRef pdp_ram_0_0_0))
+              (portRef CLKA (instanceRef pdp_ram_0_0_0))
+              (portRef CK (instanceRef FF_56))
+              (portRef CK (instanceRef FF_55))
+              (portRef CK (instanceRef FF_54))
+              (portRef CK (instanceRef FF_53))
+              (portRef CK (instanceRef FF_52))
+              (portRef CK (instanceRef FF_51))
+              (portRef CK (instanceRef FF_50))
+              (portRef CK (instanceRef FF_49))
+              (portRef CK (instanceRef FF_48))
+              (portRef CK (instanceRef FF_47))
+              (portRef CK (instanceRef FF_46))
+              (portRef CK (instanceRef FF_45))
+              (portRef CK (instanceRef FF_44))
+              (portRef CK (instanceRef FF_43))
+              (portRef CK (instanceRef FF_42))
+              (portRef CK (instanceRef FF_41))
+              (portRef CK (instanceRef FF_40))
+              (portRef CK (instanceRef FF_39))
+              (portRef CK (instanceRef FF_38))
+              (portRef CK (instanceRef FF_37))
+              (portRef CK (instanceRef FF_36))
+              (portRef CK (instanceRef FF_35))
+              (portRef CK (instanceRef FF_34))
+              (portRef CK (instanceRef FF_33))
+              (portRef CK (instanceRef FF_32))
+              (portRef CK (instanceRef FF_31))
+              (portRef CK (instanceRef FF_30))
+              (portRef CK (instanceRef FF_29))
+              (portRef CK (instanceRef FF_28))
+              (portRef CK (instanceRef FF_27))
+              (portRef CK (instanceRef FF_26))
+              (portRef CK (instanceRef FF_25))
+              (portRef CK (instanceRef FF_24))
+              (portRef CK (instanceRef FF_23))
+              (portRef CK (instanceRef FF_22))
+              (portRef CK (instanceRef FF_21))
+              (portRef CK (instanceRef FF_20))
+              (portRef CK (instanceRef FF_19))
+              (portRef CK (instanceRef FF_18))
+              (portRef CK (instanceRef FF_17))
+              (portRef CK (instanceRef FF_16))
+              (portRef CK (instanceRef FF_15))
+              (portRef CK (instanceRef FF_14))
+              (portRef CK (instanceRef FF_13))
+              (portRef CK (instanceRef FF_12))
+              (portRef CK (instanceRef FF_11))
+              (portRef CK (instanceRef FF_10))
+              (portRef CK (instanceRef FF_9))
+              (portRef CK (instanceRef FF_8))
+              (portRef CK (instanceRef FF_7))
+              (portRef CK (instanceRef FF_6))
+              (portRef CK (instanceRef FF_5))
+              (portRef CK (instanceRef FF_4))
+              (portRef CK (instanceRef FF_3))
+              (portRef CK (instanceRef FF_2))
+              (portRef CK (instanceRef FF_1))
+              (portRef CK (instanceRef FF_0))))
+          (net datain17
+            (joined
+              (portRef (member Data 0))
+              (portRef DIA17 (instanceRef pdp_ram_0_0_0))))
+          (net datain16
+            (joined
+              (portRef (member Data 1))
+              (portRef DIA16 (instanceRef pdp_ram_0_0_0))))
+          (net datain15
+            (joined
+              (portRef (member Data 2))
+              (portRef DIA15 (instanceRef pdp_ram_0_0_0))))
+          (net datain14
+            (joined
+              (portRef (member Data 3))
+              (portRef DIA14 (instanceRef pdp_ram_0_0_0))))
+          (net datain13
+            (joined
+              (portRef (member Data 4))
+              (portRef DIA13 (instanceRef pdp_ram_0_0_0))))
+          (net datain12
+            (joined
+              (portRef (member Data 5))
+              (portRef DIA12 (instanceRef pdp_ram_0_0_0))))
+          (net datain11
+            (joined
+              (portRef (member Data 6))
+              (portRef DIA11 (instanceRef pdp_ram_0_0_0))))
+          (net datain10
+            (joined
+              (portRef (member Data 7))
+              (portRef DIA10 (instanceRef pdp_ram_0_0_0))))
+          (net datain9
+            (joined
+              (portRef (member Data 8))
+              (portRef DIA9 (instanceRef pdp_ram_0_0_0))))
+          (net datain8
+            (joined
+              (portRef (member Data 9))
+              (portRef DIA8 (instanceRef pdp_ram_0_0_0))))
+          (net datain7
+            (joined
+              (portRef (member Data 10))
+              (portRef DIA7 (instanceRef pdp_ram_0_0_0))))
+          (net datain6
+            (joined
+              (portRef (member Data 11))
+              (portRef DIA6 (instanceRef pdp_ram_0_0_0))))
+          (net datain5
+            (joined
+              (portRef (member Data 12))
+              (portRef DIA5 (instanceRef pdp_ram_0_0_0))))
+          (net datain4
+            (joined
+              (portRef (member Data 13))
+              (portRef DIA4 (instanceRef pdp_ram_0_0_0))))
+          (net datain3
+            (joined
+              (portRef (member Data 14))
+              (portRef DIA3 (instanceRef pdp_ram_0_0_0))))
+          (net datain2
+            (joined
+              (portRef (member Data 15))
+              (portRef DIA2 (instanceRef pdp_ram_0_0_0))))
+          (net datain1
+            (joined
+              (portRef (member Data 16))
+              (portRef DIA1 (instanceRef pdp_ram_0_0_0))))
+          (net datain0
+            (joined
+              (portRef (member Data 17))
+              (portRef DIA0 (instanceRef pdp_ram_0_0_0))))))))
+  (design fifo_18x256_oreg
+    (cellRef fifo_18x256_oreg
+      (libraryRef ORCLIB)))
+)

diff --git a/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.fdc b/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.fdc
new file mode 100644 (file)
index 0000000..6fbcac9
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.fdc
@@ -0,0 +1,2 @@
+###==== Start Configuration
+

diff --git a/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.lpc b/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.lpc
new file mode 100644 (file)
index 0000000..a889eae
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.lpc
@@ -0,0 +1,50 @@
+[Device]
+Family=ecp5um
+PartType=LFE5UM-85F
+PartName=LFE5UM-85F-8MG285C
+SpeedGrade=8
+Package=CSFBGA285
+OperatingCondition=COM
+Status=C
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO
+CoreRevision=5.0
+ModuleName=fifo_18x256_oreg
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=03/18/2015
+Time=14:42:54
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=256
+Width=18
+regout=1
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=1
+PfMode=Dynamic - Single Threshold
+PfAssert=508
+PfDeassert=506
+Reset=Async
+Reset1=Sync
+RDataCount=1
+EnECC=0
+EnFWFT=0
+
+[Command]
+cmd_line= -w -n fifo_18x256_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 256 -width 18 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill

diff --git a/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.ngd b/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.ngd
new file mode 100644 (file)
index 0000000..97f9124
Binary files /dev/null and b/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.ngd differ

diff --git a/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.ngo b/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.ngo
new file mode 100644 (file)
index 0000000..f22854e
Binary files /dev/null and b/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.ngo differ

diff --git a/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.vhd b/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.vhd
new file mode 100644 (file)
index 0000000..ba735fc
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.vhd
@@ -0,0 +1,915 @@
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80
+-- Module  Version: 5.0
+--/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_18x256_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 256 -width 18 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.fdc 
+
+-- Wed Mar 18 14:42:55 2015
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity fifo_18x256_oreg is
+    port (
+        Data: in  std_logic_vector(17 downto 0); 
+        Clock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        AmFullThresh: in  std_logic_vector(7 downto 0); 
+        Q: out  std_logic_vector(17 downto 0); 
+        WCNT: out  std_logic_vector(8 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic; 
+        AlmostFull: out  std_logic);
+end fifo_18x256_oreg;
+
+architecture Structure of fifo_18x256_oreg is
+
+    -- internal signal declarations
+    signal invout_2: std_logic;
+    signal invout_1: std_logic;
+    signal rden_i_inv: std_logic;
+    signal invout_0: std_logic;
+    signal r_nw: std_logic;
+    signal fcnt_en: std_logic;
+    signal empty_i: std_logic;
+    signal empty_d: std_logic;
+    signal full_i: std_logic;
+    signal full_d: std_logic;
+    signal wptr_0: std_logic;
+    signal wptr_1: std_logic;
+    signal wptr_2: std_logic;
+    signal wptr_3: std_logic;
+    signal wptr_4: std_logic;
+    signal wptr_5: std_logic;
+    signal wptr_6: std_logic;
+    signal wptr_7: std_logic;
+    signal wptr_8: std_logic;
+    signal rptr_8: std_logic;
+    signal ifcount_0: std_logic;
+    signal ifcount_1: std_logic;
+    signal bdcnt_bctr_ci: std_logic;
+    signal ifcount_2: std_logic;
+    signal ifcount_3: std_logic;
+    signal co0: std_logic;
+    signal ifcount_4: std_logic;
+    signal ifcount_5: std_logic;
+    signal co1: std_logic;
+    signal ifcount_6: std_logic;
+    signal ifcount_7: std_logic;
+    signal co2: std_logic;
+    signal ifcount_8: std_logic;
+    signal co4: std_logic;
+    signal co3: std_logic;
+    signal cmp_ci: std_logic;
+    signal rden_i: std_logic;
+    signal co0_1: std_logic;
+    signal co1_1: std_logic;
+    signal co2_1: std_logic;
+    signal co3_1: std_logic;
+    signal cmp_le_1: std_logic;
+    signal cmp_le_1_c: std_logic;
+    signal cmp_ci_1: std_logic;
+    signal fcount_0: std_logic;
+    signal fcount_1: std_logic;
+    signal co0_2: std_logic;
+    signal fcount_2: std_logic;
+    signal fcount_3: std_logic;
+    signal co1_2: std_logic;
+    signal fcount_4: std_logic;
+    signal fcount_5: std_logic;
+    signal co2_2: std_logic;
+    signal fcount_6: std_logic;
+    signal fcount_7: std_logic;
+    signal co3_2: std_logic;
+    signal wren_i_inv: std_logic;
+    signal fcount_8: std_logic;
+    signal cmp_ge_d1: std_logic;
+    signal cmp_ge_d1_c: std_logic;
+    signal iwcount_0: std_logic;
+    signal iwcount_1: std_logic;
+    signal w_ctr_ci: std_logic;
+    signal iwcount_2: std_logic;
+    signal iwcount_3: std_logic;
+    signal co0_3: std_logic;
+    signal iwcount_4: std_logic;
+    signal iwcount_5: std_logic;
+    signal co1_3: std_logic;
+    signal iwcount_6: std_logic;
+    signal iwcount_7: std_logic;
+    signal co2_3: std_logic;
+    signal iwcount_8: std_logic;
+    signal co4_1: std_logic;
+    signal co3_3: std_logic;
+    signal wcount_8: std_logic;
+    signal ircount_0: std_logic;
+    signal ircount_1: std_logic;
+    signal r_ctr_ci: std_logic;
+    signal rcount_0: std_logic;
+    signal rcount_1: std_logic;
+    signal ircount_2: std_logic;
+    signal ircount_3: std_logic;
+    signal co0_4: std_logic;
+    signal rcount_2: std_logic;
+    signal rcount_3: std_logic;
+    signal ircount_4: std_logic;
+    signal ircount_5: std_logic;
+    signal co1_4: std_logic;
+    signal rcount_4: std_logic;
+    signal rcount_5: std_logic;
+    signal ircount_6: std_logic;
+    signal ircount_7: std_logic;
+    signal co2_4: std_logic;
+    signal rcount_6: std_logic;
+    signal rcount_7: std_logic;
+    signal ircount_8: std_logic;
+    signal co4_2: std_logic;
+    signal co3_4: std_logic;
+    signal rcount_8: std_logic;
+    signal wcnt_sub_0: std_logic;
+    signal rptr_0: std_logic;
+    signal cnt_con_inv: std_logic;
+    signal wcount_0: std_logic;
+    signal cnt_con: std_logic;
+    signal precin: std_logic;
+    signal wcnt_sub_1: std_logic;
+    signal wcnt_sub_2: std_logic;
+    signal rptr_2: std_logic;
+    signal rptr_1: std_logic;
+    signal wcount_2: std_logic;
+    signal wcount_1: std_logic;
+    signal co0_5: std_logic;
+    signal wcnt_sub_3: std_logic;
+    signal wcnt_sub_4: std_logic;
+    signal rptr_4: std_logic;
+    signal rptr_3: std_logic;
+    signal wcount_4: std_logic;
+    signal wcount_3: std_logic;
+    signal co1_5: std_logic;
+    signal wcnt_sub_5: std_logic;
+    signal wcnt_sub_6: std_logic;
+    signal rptr_6: std_logic;
+    signal rptr_5: std_logic;
+    signal wcount_6: std_logic;
+    signal wcount_5: std_logic;
+    signal co2_5: std_logic;
+    signal wcnt_sub_7: std_logic;
+    signal wcnt_sub_8: std_logic;
+    signal rptr_7: std_logic;
+    signal wcnt_sub_msb: std_logic;
+    signal wcount_7: std_logic;
+    signal co3_5: std_logic;
+    signal co4_3d: std_logic;
+    signal co4_3: std_logic;
+    signal wren_i: std_logic;
+    signal cmp_ci_2: std_logic;
+    signal wcnt_reg_0: std_logic;
+    signal wcnt_reg_1: std_logic;
+    signal co0_6: std_logic;
+    signal wcnt_reg_2: std_logic;
+    signal wcnt_reg_3: std_logic;
+    signal co1_6: std_logic;
+    signal wcnt_reg_4: std_logic;
+    signal wcnt_reg_5: std_logic;
+    signal co2_6: std_logic;
+    signal wcnt_reg_6: std_logic;
+    signal wcnt_reg_7: std_logic;
+    signal co3_6: std_logic;
+    signal wcnt_reg_8: std_logic;
+    signal af_set: std_logic;
+    signal scuba_vhi: std_logic;
+    signal scuba_vlo: std_logic;
+    signal af_set_c: std_logic;
+
+    attribute MEM_LPC_FILE : string; 
+    attribute MEM_INIT_FILE : string; 
+    attribute GSR : string; 
+    attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_18x256_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
+    attribute GSR of FF_56 : label is "ENABLED";
+    attribute GSR of FF_55 : label is "ENABLED";
+    attribute GSR of FF_54 : label is "ENABLED";
+    attribute GSR of FF_53 : label is "ENABLED";
+    attribute GSR of FF_52 : label is "ENABLED";
+    attribute GSR of FF_51 : label is "ENABLED";
+    attribute GSR of FF_50 : label is "ENABLED";
+    attribute GSR of FF_49 : label is "ENABLED";
+    attribute GSR of FF_48 : label is "ENABLED";
+    attribute GSR of FF_47 : label is "ENABLED";
+    attribute GSR of FF_46 : label is "ENABLED";
+    attribute GSR of FF_45 : label is "ENABLED";
+    attribute GSR of FF_44 : label is "ENABLED";
+    attribute GSR of FF_43 : label is "ENABLED";
+    attribute GSR of FF_42 : label is "ENABLED";
+    attribute GSR of FF_41 : label is "ENABLED";
+    attribute GSR of FF_40 : label is "ENABLED";
+    attribute GSR of FF_39 : label is "ENABLED";
+    attribute GSR of FF_38 : label is "ENABLED";
+    attribute GSR of FF_37 : label is "ENABLED";
+    attribute GSR of FF_36 : label is "ENABLED";
+    attribute GSR of FF_35 : label is "ENABLED";
+    attribute GSR of FF_34 : label is "ENABLED";
+    attribute GSR of FF_33 : label is "ENABLED";
+    attribute GSR of FF_32 : label is "ENABLED";
+    attribute GSR of FF_31 : label is "ENABLED";
+    attribute GSR of FF_30 : label is "ENABLED";
+    attribute GSR of FF_29 : label is "ENABLED";
+    attribute GSR of FF_28 : label is "ENABLED";
+    attribute GSR of FF_27 : label is "ENABLED";
+    attribute GSR of FF_26 : label is "ENABLED";
+    attribute GSR of FF_25 : label is "ENABLED";
+    attribute GSR of FF_24 : label is "ENABLED";
+    attribute GSR of FF_23 : label is "ENABLED";
+    attribute GSR of FF_22 : label is "ENABLED";
+    attribute GSR of FF_21 : label is "ENABLED";
+    attribute GSR of FF_20 : label is "ENABLED";
+    attribute GSR of FF_19 : label is "ENABLED";
+    attribute GSR of FF_18 : label is "ENABLED";
+    attribute GSR of FF_17 : label is "ENABLED";
+    attribute GSR of FF_16 : label is "ENABLED";
+    attribute GSR of FF_15 : label is "ENABLED";
+    attribute GSR of FF_14 : label is "ENABLED";
+    attribute GSR of FF_13 : label is "ENABLED";
+    attribute GSR of FF_12 : label is "ENABLED";
+    attribute GSR of FF_11 : label is "ENABLED";
+    attribute GSR of FF_10 : label is "ENABLED";
+    attribute GSR of FF_9 : label is "ENABLED";
+    attribute GSR of FF_8 : label is "ENABLED";
+    attribute GSR of FF_7 : label is "ENABLED";
+    attribute GSR of FF_6 : label is "ENABLED";
+    attribute GSR of FF_5 : label is "ENABLED";
+    attribute GSR of FF_4 : label is "ENABLED";
+    attribute GSR of FF_3 : label is "ENABLED";
+    attribute GSR of FF_2 : label is "ENABLED";
+    attribute GSR of FF_1 : label is "ENABLED";
+    attribute GSR of FF_0 : label is "ENABLED";
+    attribute syn_keep : boolean;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    AND2_t5: AND2
+        port map (A=>WrEn, B=>invout_2, Z=>wren_i);
+
+    INV_5: INV
+        port map (A=>full_i, Z=>invout_2);
+
+    AND2_t4: AND2
+        port map (A=>RdEn, B=>invout_1, Z=>rden_i);
+
+    INV_4: INV
+        port map (A=>empty_i, Z=>invout_1);
+
+    AND2_t3: AND2
+        port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
+
+    XOR2_t2: XOR2
+        port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
+
+    INV_3: INV
+        port map (A=>rden_i, Z=>rden_i_inv);
+
+    INV_2: INV
+        port map (A=>wren_i, Z=>wren_i_inv);
+
+    LUT4_1: ROM16X1A
+        generic map (initval=> X"3232")
+        port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, 
+            AD0=>empty_i, DO0=>empty_d);
+
+    LUT4_0: ROM16X1A
+        generic map (initval=> X"3232")
+        port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, 
+            AD0=>full_i, DO0=>full_d);
+
+    AND2_t1: AND2
+        port map (A=>rden_i, B=>invout_0, Z=>r_nw);
+
+    INV_1: INV
+        port map (A=>wren_i, Z=>invout_0);
+
+    XOR2_t0: XOR2
+        port map (A=>wcount_8, B=>rptr_8, Z=>wcnt_sub_msb);
+
+    INV_0: INV
+        port map (A=>cnt_con, Z=>cnt_con_inv);
+
+    pdp_ram_0_0_0: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  18, 
+        DATA_WIDTH_A=>  18)
+        port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), 
+            DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), 
+            DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), 
+            DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), 
+            DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), 
+            DIA0=>Data(0), ADA13=>scuba_vlo, ADA12=>scuba_vlo, 
+            ADA11=>wptr_7, ADA10=>wptr_6, ADA9=>wptr_5, ADA8=>wptr_4, 
+            ADA7=>wptr_3, ADA6=>wptr_2, ADA5=>wptr_1, ADA4=>wptr_0, 
+            ADA3=>scuba_vlo, ADA2=>scuba_vlo, ADA1=>scuba_vhi, 
+            ADA0=>scuba_vhi, CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, 
+            WEA=>scuba_vhi, CSA2=>scuba_vlo, CSA1=>scuba_vlo, 
+            CSA0=>scuba_vlo, RSTA=>Reset, DIB17=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>scuba_vlo, 
+            ADB12=>scuba_vlo, ADB11=>rptr_7, ADB10=>rptr_6, ADB9=>rptr_5, 
+            ADB8=>rptr_4, ADB7=>rptr_3, ADB6=>rptr_2, ADB5=>rptr_1, 
+            ADB4=>rptr_0, ADB3=>scuba_vlo, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>scuba_vlo, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>Q(17), DOB16=>Q(16), DOB15=>Q(15), 
+            DOB14=>Q(14), DOB13=>Q(13), DOB12=>Q(12), DOB11=>Q(11), 
+            DOB10=>Q(10), DOB9=>Q(9), DOB8=>Q(8), DOB7=>Q(7), DOB6=>Q(6), 
+            DOB5=>Q(5), DOB4=>Q(4), DOB3=>Q(3), DOB2=>Q(2), DOB1=>Q(1), 
+            DOB0=>Q(0));
+
+    FF_56: FD1P3DX
+        port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_0);
+
+    FF_55: FD1P3DX
+        port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_1);
+
+    FF_54: FD1P3DX
+        port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_2);
+
+    FF_53: FD1P3DX
+        port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_3);
+
+    FF_52: FD1P3DX
+        port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_4);
+
+    FF_51: FD1P3DX
+        port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_5);
+
+    FF_50: FD1P3DX
+        port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_6);
+
+    FF_49: FD1P3DX
+        port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_7);
+
+    FF_48: FD1P3DX
+        port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_8);
+
+    FF_47: FD1S3BX
+        port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
+
+    FF_46: FD1S3DX
+        port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
+
+    FF_45: FD1P3BX
+        port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset, 
+            Q=>wcount_0);
+
+    FF_44: FD1P3DX
+        port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_1);
+
+    FF_43: FD1P3DX
+        port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_2);
+
+    FF_42: FD1P3DX
+        port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_3);
+
+    FF_41: FD1P3DX
+        port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_4);
+
+    FF_40: FD1P3DX
+        port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_5);
+
+    FF_39: FD1P3DX
+        port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_6);
+
+    FF_38: FD1P3DX
+        port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_7);
+
+    FF_37: FD1P3DX
+        port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_8);
+
+    FF_36: FD1P3BX
+        port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset, 
+            Q=>rcount_0);
+
+    FF_35: FD1P3DX
+        port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_1);
+
+    FF_34: FD1P3DX
+        port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_2);
+
+    FF_33: FD1P3DX
+        port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_3);
+
+    FF_32: FD1P3DX
+        port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_4);
+
+    FF_31: FD1P3DX
+        port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_5);
+
+    FF_30: FD1P3DX
+        port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_6);
+
+    FF_29: FD1P3DX
+        port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_7);
+
+    FF_28: FD1P3DX
+        port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_8);
+
+    FF_27: FD1P3DX
+        port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_0);
+
+    FF_26: FD1P3DX
+        port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_1);
+
+    FF_25: FD1P3DX
+        port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_2);
+
+    FF_24: FD1P3DX
+        port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_3);
+
+    FF_23: FD1P3DX
+        port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_4);
+
+    FF_22: FD1P3DX
+        port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_5);
+
+    FF_21: FD1P3DX
+        port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_6);
+
+    FF_20: FD1P3DX
+        port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_7);
+
+    FF_19: FD1P3DX
+        port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_8);
+
+    FF_18: FD1P3DX
+        port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_0);
+
+    FF_17: FD1P3DX
+        port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_1);
+
+    FF_16: FD1P3DX
+        port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_2);
+
+    FF_15: FD1P3DX
+        port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_3);
+
+    FF_14: FD1P3DX
+        port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_4);
+
+    FF_13: FD1P3DX
+        port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_5);
+
+    FF_12: FD1P3DX
+        port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_6);
+
+    FF_11: FD1P3DX
+        port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_7);
+
+    FF_10: FD1P3DX
+        port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_8);
+
+    FF_9: FD1S3DX
+        port map (D=>wcnt_sub_0, CK=>Clock, CD=>Reset, Q=>wcnt_reg_0);
+
+    FF_8: FD1S3DX
+        port map (D=>wcnt_sub_1, CK=>Clock, CD=>Reset, Q=>wcnt_reg_1);
+
+    FF_7: FD1S3DX
+        port map (D=>wcnt_sub_2, CK=>Clock, CD=>Reset, Q=>wcnt_reg_2);
+
+    FF_6: FD1S3DX
+        port map (D=>wcnt_sub_3, CK=>Clock, CD=>Reset, Q=>wcnt_reg_3);
+
+    FF_5: FD1S3DX
+        port map (D=>wcnt_sub_4, CK=>Clock, CD=>Reset, Q=>wcnt_reg_4);
+
+    FF_4: FD1S3DX
+        port map (D=>wcnt_sub_5, CK=>Clock, CD=>Reset, Q=>wcnt_reg_5);
+
+    FF_3: FD1S3DX
+        port map (D=>wcnt_sub_6, CK=>Clock, CD=>Reset, Q=>wcnt_reg_6);
+
+    FF_2: FD1S3DX
+        port map (D=>wcnt_sub_7, CK=>Clock, CD=>Reset, Q=>wcnt_reg_7);
+
+    FF_1: FD1S3DX
+        port map (D=>wcnt_sub_8, CK=>Clock, CD=>Reset, Q=>wcnt_reg_8);
+
+    FF_0: FD1S3DX
+        port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull);
+
+    bdcnt_bctr_cia: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>'X', S0=>open, S1=>open, COUT=>bdcnt_bctr_ci);
+
+    bdcnt_bctr_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_0, A1=>fcount_1, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>bdcnt_bctr_ci, S0=>ifcount_0, S1=>ifcount_1, COUT=>co0);
+
+    bdcnt_bctr_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co0, S0=>ifcount_2, S1=>ifcount_3, COUT=>co1);
+
+    bdcnt_bctr_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_4, A1=>fcount_5, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co1, S0=>ifcount_4, S1=>ifcount_5, COUT=>co2);
+
+    bdcnt_bctr_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_6, A1=>fcount_7, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co2, S0=>ifcount_6, S1=>ifcount_7, COUT=>co3);
+
+    bdcnt_bctr_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_8, A1=>scuba_vlo, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co3, S0=>ifcount_8, S1=>open, COUT=>co4);
+
+    e_cmp_ci_a: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci);
+
+    e_cmp_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>rden_i, A1=>scuba_vlo, B0=>fcount_0, B1=>fcount_1, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>cmp_ci, S0=>open, S1=>open, COUT=>co0_1);
+
+    e_cmp_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_2, 
+            B1=>fcount_3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co0_1, S0=>open, S1=>open, COUT=>co1_1);
+
+    e_cmp_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_4, 
+            B1=>fcount_5, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co1_1, S0=>open, S1=>open, COUT=>co2_1);
+
+    e_cmp_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_6, 
+            B1=>fcount_7, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co2_1, S0=>open, S1=>open, COUT=>co3_1);
+
+    e_cmp_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_8, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co3_1, S0=>open, S1=>open, 
+            COUT=>cmp_le_1_c);
+
+    a0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>cmp_le_1_c, S0=>cmp_le_1, S1=>open, 
+            COUT=>open);
+
+    g_cmp_ci_a: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_1);
+
+    g_cmp_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>cmp_ci_1, S0=>open, S1=>open, COUT=>co0_2);
+
+    g_cmp_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co0_2, S0=>open, S1=>open, COUT=>co1_2);
+
+    g_cmp_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co1_2, S0=>open, S1=>open, COUT=>co2_2);
+
+    g_cmp_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co2_2, S0=>open, S1=>open, COUT=>co3_2);
+
+    g_cmp_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_8, A1=>scuba_vlo, B0=>wren_i_inv, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co3_2, S0=>open, S1=>open, 
+            COUT=>cmp_ge_d1_c);
+
+    a1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>cmp_ge_d1_c, S0=>cmp_ge_d1, S1=>open, 
+            COUT=>open);
+
+    w_ctr_cia: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>w_ctr_ci);
+
+    w_ctr_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>w_ctr_ci, S0=>iwcount_0, S1=>iwcount_1, 
+            COUT=>co0_3);
+
+    w_ctr_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_2, A1=>wcount_3, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co0_3, S0=>iwcount_2, S1=>iwcount_3, 
+            COUT=>co1_3);
+
+    w_ctr_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_4, A1=>wcount_5, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co1_3, S0=>iwcount_4, S1=>iwcount_5, 
+            COUT=>co2_3);
+
+    w_ctr_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_6, A1=>wcount_7, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co2_3, S0=>iwcount_6, S1=>iwcount_7, 
+            COUT=>co3_3);
+
+    w_ctr_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_8, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co3_3, S0=>iwcount_8, S1=>open, 
+            COUT=>co4_1);
+
+    r_ctr_cia: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>r_ctr_ci);
+
+    r_ctr_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>r_ctr_ci, S0=>ircount_0, S1=>ircount_1, 
+            COUT=>co0_4);
+
+    r_ctr_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_2, A1=>rcount_3, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co0_4, S0=>ircount_2, S1=>ircount_3, 
+            COUT=>co1_4);
+
+    r_ctr_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_4, A1=>rcount_5, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co1_4, S0=>ircount_4, S1=>ircount_5, 
+            COUT=>co2_4);
+
+    r_ctr_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_6, A1=>rcount_7, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co2_4, S0=>ircount_6, S1=>ircount_7, 
+            COUT=>co3_4);
+
+    r_ctr_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_8, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co3_4, S0=>ircount_8, S1=>open, 
+            COUT=>co4_2);
+
+    precin_inst207: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"0000", 
+        INIT0=> X"0000")
+        port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>precin);
+
+    wcnt_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>cnt_con, A1=>wcount_0, B0=>cnt_con_inv, B1=>rptr_0, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>precin, S0=>open, S1=>wcnt_sub_0, COUT=>co0_5);
+
+    wcnt_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_1, A1=>wcount_2, B0=>rptr_1, B1=>rptr_2, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co0_5, S0=>wcnt_sub_1, S1=>wcnt_sub_2, COUT=>co1_5);
+
+    wcnt_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_3, A1=>wcount_4, B0=>rptr_3, B1=>rptr_4, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co1_5, S0=>wcnt_sub_3, S1=>wcnt_sub_4, COUT=>co2_5);
+
+    wcnt_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_5, A1=>wcount_6, B0=>rptr_5, B1=>rptr_6, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co2_5, S0=>wcnt_sub_5, S1=>wcnt_sub_6, COUT=>co3_5);
+
+    wcnt_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_7, A1=>wcnt_sub_msb, B0=>rptr_7, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co3_5, S0=>wcnt_sub_7, S1=>wcnt_sub_8, 
+            COUT=>co4_3);
+
+    wcntd: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co4_3, S0=>co4_3d, S1=>open, COUT=>open);
+
+    af_set_cmp_ci_a: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_2);
+
+    af_set_cmp_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0), 
+            B1=>AmFullThresh(1), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>cmp_ci_2, S0=>open, 
+            S1=>open, COUT=>co0_6);
+
+    af_set_cmp_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2), 
+            B1=>AmFullThresh(3), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co0_6, S0=>open, S1=>open, 
+            COUT=>co1_6);
+
+    af_set_cmp_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4), 
+            B1=>AmFullThresh(5), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co1_6, S0=>open, S1=>open, 
+            COUT=>co2_6);
+
+    af_set_cmp_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6), 
+            B1=>AmFullThresh(7), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co2_6, S0=>open, S1=>open, 
+            COUT=>co3_6);
+
+    af_set_cmp_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_8, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co3_6, S0=>open, S1=>open, 
+            COUT=>af_set_c);
+
+    scuba_vhi_inst: VHI
+        port map (Z=>scuba_vhi);
+
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    a2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>af_set_c, S0=>af_set, S1=>open, 
+            COUT=>open);
+
+    WCNT(0) <= fcount_0;
+    WCNT(1) <= fcount_1;
+    WCNT(2) <= fcount_2;
+    WCNT(3) <= fcount_3;
+    WCNT(4) <= fcount_4;
+    WCNT(5) <= fcount_5;
+    WCNT(6) <= fcount_6;
+    WCNT(7) <= fcount_7;
+    WCNT(8) <= fcount_8;
+    Empty <= empty_i;
+    Full <= full_i;
+end Structure;

diff --git a/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg_ngd.asd b/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg_ngd.asd
new file mode 100644 (file)
index 0000000..c265c78
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg_ngd.asd
@@ -0,0 +1 @@
+[ActiveSupport NGD]

diff --git a/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.cst b/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.cst
new file mode 100644 (file)
index 0000000..d7afd32
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.cst
@@ -0,0 +1,3 @@
+Date=03/18/2015
+Time=14:43:13
+

diff --git a/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.edn b/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.edn
new file mode 100644 (file)
index 0000000..d8b4bab
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.edn
@@ -0,0 +1,2742 @@
+(edif fifo_18x512_oreg
+  (edifVersion 2 0 0)
+  (edifLevel 0)
+  (keywordMap (keywordLevel 0))
+  (status
+    (written
+      (timestamp 2015 3 18 14 43 18)
+      (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80"))))
+      (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_18x512_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 512 -width 18 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.fdc ")
+  (library ORCLIB
+    (edifLevel 0)
+    (technology
+      (numberDefinition))
+    (cell CCU2C
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A0
+            (direction INPUT))
+          (port A1
+            (direction INPUT))
+          (port B0
+            (direction INPUT))
+          (port B1
+            (direction INPUT))
+          (port C0
+            (direction INPUT))
+          (port C1
+            (direction INPUT))
+          (port D0
+            (direction INPUT))
+          (port D1
+            (direction INPUT))
+          (port CIN
+            (direction INPUT))
+          (port S0
+            (direction OUTPUT))
+          (port S1
+            (direction OUTPUT))
+          (port COUT
+            (direction OUTPUT)))))
+    (cell AND2
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A
+            (direction INPUT))
+          (port B
+            (direction INPUT))
+          (port Z
+            (direction OUTPUT)))))
+    (cell FD1P3BX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port SP
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port PD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell FD1P3DX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port SP
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port CD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell FD1S3BX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port PD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell FD1S3DX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port CD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell INV
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A
+            (direction INPUT))
+          (port Z
+            (direction OUTPUT)))))
+    (cell ROM16X1A
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port AD3
+            (direction INPUT))
+          (port AD2
+            (direction INPUT))
+          (port AD1
+            (direction INPUT))
+          (port AD0
+            (direction INPUT))
+          (port DO0
+            (direction OUTPUT)))))
+    (cell VHI
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port Z
+            (direction OUTPUT)))))
+    (cell VLO
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port Z
+            (direction OUTPUT)))))
+    (cell XOR2
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A
+            (direction INPUT))
+          (port B
+            (direction INPUT))
+          (port Z
+            (direction OUTPUT)))))
+    (cell PDPW16KD
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port DI35
+            (direction INPUT))
+          (port DI34
+            (direction INPUT))
+          (port DI33
+            (direction INPUT))
+          (port DI32
+            (direction INPUT))
+          (port DI31
+            (direction INPUT))
+          (port DI30
+            (direction INPUT))
+          (port DI29
+            (direction INPUT))
+          (port DI28
+            (direction INPUT))
+          (port DI27
+            (direction INPUT))
+          (port DI26
+            (direction INPUT))
+          (port DI25
+            (direction INPUT))
+          (port DI24
+            (direction INPUT))
+          (port DI23
+            (direction INPUT))
+          (port DI22
+            (direction INPUT))
+          (port DI21
+            (direction INPUT))
+          (port DI20
+            (direction INPUT))
+          (port DI19
+            (direction INPUT))
+          (port DI18
+            (direction INPUT))
+          (port DI17
+            (direction INPUT))
+          (port DI16
+            (direction INPUT))
+          (port DI15
+            (direction INPUT))
+          (port DI14
+            (direction INPUT))
+          (port DI13
+            (direction INPUT))
+          (port DI12
+            (direction INPUT))
+          (port DI11
+            (direction INPUT))
+          (port DI10
+            (direction INPUT))
+          (port DI9
+            (direction INPUT))
+          (port DI8
+            (direction INPUT))
+          (port DI7
+            (direction INPUT))
+          (port DI6
+            (direction INPUT))
+          (port DI5
+            (direction INPUT))
+          (port DI4
+            (direction INPUT))
+          (port DI3
+            (direction INPUT))
+          (port DI2
+            (direction INPUT))
+          (port DI1
+            (direction INPUT))
+          (port DI0
+            (direction INPUT))
+          (port ADW8
+            (direction INPUT))
+          (port ADW7
+            (direction INPUT))
+          (port ADW6
+            (direction INPUT))
+          (port ADW5
+            (direction INPUT))
+          (port ADW4
+            (direction INPUT))
+          (port ADW3
+            (direction INPUT))
+          (port ADW2
+            (direction INPUT))
+          (port ADW1
+            (direction INPUT))
+          (port ADW0
+            (direction INPUT))
+          (port BE3
+            (direction INPUT))
+          (port BE2
+            (direction INPUT))
+          (port BE1
+            (direction INPUT))
+          (port BE0
+            (direction INPUT))
+          (port CEW
+            (direction INPUT))
+          (port CLKW
+            (direction INPUT))
+          (port CSW2
+            (direction INPUT))
+          (port CSW1
+            (direction INPUT))
+          (port CSW0
+            (direction INPUT))
+          (port ADR13
+            (direction INPUT))
+          (port ADR12
+            (direction INPUT))
+          (port ADR11
+            (direction INPUT))
+          (port ADR10
+            (direction INPUT))
+          (port ADR9
+            (direction INPUT))
+          (port ADR8
+            (direction INPUT))
+          (port ADR7
+            (direction INPUT))
+          (port ADR6
+            (direction INPUT))
+          (port ADR5
+            (direction INPUT))
+          (port ADR4
+            (direction INPUT))
+          (port ADR3
+            (direction INPUT))
+          (port ADR2
+            (direction INPUT))
+          (port ADR1
+            (direction INPUT))
+          (port ADR0
+            (direction INPUT))
+          (port CER
+            (direction INPUT))
+          (port OCER
+            (direction INPUT))
+          (port CLKR
+            (direction INPUT))
+          (port CSR2
+            (direction INPUT))
+          (port CSR1
+            (direction INPUT))
+          (port CSR0
+            (direction INPUT))
+          (port RST
+            (direction INPUT))
+          (port DO35
+            (direction OUTPUT))
+          (port DO34
+            (direction OUTPUT))
+          (port DO33
+            (direction OUTPUT))
+          (port DO32
+            (direction OUTPUT))
+          (port DO31
+            (direction OUTPUT))
+          (port DO30
+            (direction OUTPUT))
+          (port DO29
+            (direction OUTPUT))
+          (port DO28
+            (direction OUTPUT))
+          (port DO27
+            (direction OUTPUT))
+          (port DO26
+            (direction OUTPUT))
+          (port DO25
+            (direction OUTPUT))
+          (port DO24
+            (direction OUTPUT))
+          (port DO23
+            (direction OUTPUT))
+          (port DO22
+            (direction OUTPUT))
+          (port DO21
+            (direction OUTPUT))
+          (port DO20
+            (direction OUTPUT))
+          (port DO19
+            (direction OUTPUT))
+          (port DO18
+            (direction OUTPUT))
+          (port DO17
+            (direction OUTPUT))
+          (port DO16
+            (direction OUTPUT))
+          (port DO15
+            (direction OUTPUT))
+          (port DO14
+            (direction OUTPUT))
+          (port DO13
+            (direction OUTPUT))
+          (port DO12
+            (direction OUTPUT))
+          (port DO11
+            (direction OUTPUT))
+          (port DO10
+            (direction OUTPUT))
+          (port DO9
+            (direction OUTPUT))
+          (port DO8
+            (direction OUTPUT))
+          (port DO7
+            (direction OUTPUT))
+          (port DO6
+            (direction OUTPUT))
+          (port DO5
+            (direction OUTPUT))
+          (port DO4
+            (direction OUTPUT))
+          (port DO3
+            (direction OUTPUT))
+          (port DO2
+            (direction OUTPUT))
+          (port DO1
+            (direction OUTPUT))
+          (port DO0
+            (direction OUTPUT)))))
+    (cell fifo_18x512_oreg
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port (array (rename Data "Data(17:0)") 18)
+            (direction INPUT))
+          (port Clock
+            (direction INPUT))
+          (port WrEn
+            (direction INPUT))
+          (port RdEn
+            (direction INPUT))
+          (port Reset
+            (direction INPUT))
+          (port (array (rename AmFullThresh "AmFullThresh(8:0)") 9)
+            (direction INPUT))
+          (port (array (rename Q "Q(17:0)") 18)
+            (direction OUTPUT))
+          (port (array (rename WCNT "WCNT(9:0)") 10)
+            (direction OUTPUT))
+          (port Empty
+            (direction OUTPUT))
+          (port Full
+            (direction OUTPUT))
+          (port AlmostFull
+            (direction OUTPUT)))
+        (property NGD_DRC_MASK (integer 1))
+        (contents
+          (instance AND2_t5
+            (viewRef view1 
+              (cellRef AND2)))
+          (instance INV_5
+            (viewRef view1 
+              (cellRef INV)))
+          (instance AND2_t4
+            (viewRef view1 
+              (cellRef AND2)))
+          (instance INV_4
+            (viewRef view1 
+              (cellRef INV)))
+          (instance AND2_t3
+            (viewRef view1 
+              (cellRef AND2)))
+          (instance XOR2_t2
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance INV_3
+            (viewRef view1 
+              (cellRef INV)))
+          (instance INV_2
+            (viewRef view1 
+              (cellRef INV)))
+          (instance LUT4_1
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x3232")))
+          (instance LUT4_0
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x3232")))
+          (instance AND2_t1
+            (viewRef view1 
+              (cellRef AND2)))
+          (instance INV_1
+            (viewRef view1 
+              (cellRef INV)))
+          (instance XOR2_t0
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance INV_0
+            (viewRef view1 
+              (cellRef INV)))
+          (instance pdp_ram_0_0_0
+            (viewRef view1 
+              (cellRef PDPW16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_18x512_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_R
+              (string "0b001"))
+            (property CSDECODE_W
+              (string "0b001"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE
+              (string "OUTREG"))
+            (property DATA_WIDTH_R
+              (string "36"))
+            (property DATA_WIDTH_W
+              (string "36")))
+          (instance FF_62
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_61
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_60
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_59
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_58
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_57
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_56
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_55
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_54
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_53
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_52
+            (viewRef view1 
+              (cellRef FD1S3BX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_51
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_50
+            (viewRef view1 
+              (cellRef FD1P3BX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_49
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_48
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_47
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_46
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_45
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_44
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_43
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_42
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_41
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_40
+            (viewRef view1 
+              (cellRef FD1P3BX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_39
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_38
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_37
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_36
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_35
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_34
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_33
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_32
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_31
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_30
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_29
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_28
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_27
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_26
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_25
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_24
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_23
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_22
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_21
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_20
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_19
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_18
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_17
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_16
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_15
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_14
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_13
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_12
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_11
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_10
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_9
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_8
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_7
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_6
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_5
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_4
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_3
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_2
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_1
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_0
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance bdcnt_bctr_cia
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance bdcnt_bctr_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_ci_a
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance e_cmp_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance a0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance g_cmp_ci_a
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance g_cmp_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance a1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_cia
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_cia
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance precin_inst218
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x0000"))
+            (property INIT0
+              (string "0x0000")))
+          (instance wcnt_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_ci_a
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance af_set_cmp_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance scuba_vhi_inst
+            (viewRef view1 
+              (cellRef VHI)))
+          (instance scuba_vlo_inst
+            (viewRef view1 
+              (cellRef VLO)))
+          (instance a2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (net invout_2
+            (joined
+              (portRef Z (instanceRef INV_5))
+              (portRef B (instanceRef AND2_t5))))
+          (net invout_1
+            (joined
+              (portRef Z (instanceRef INV_4))
+              (portRef B (instanceRef AND2_t4))))
+          (net rden_i_inv
+            (joined
+              (portRef Z (instanceRef INV_3))
+              (portRef B (instanceRef AND2_t3))))
+          (net invout_0
+            (joined
+              (portRef Z (instanceRef INV_1))
+              (portRef B (instanceRef AND2_t1))))
+          (net r_nw
+            (joined
+              (portRef Z (instanceRef AND2_t1))))
+          (net fcnt_en
+            (joined
+              (portRef SP (instanceRef FF_53))
+              (portRef Z (instanceRef XOR2_t2))
+              (portRef SP (instanceRef FF_62))
+              (portRef SP (instanceRef FF_61))
+              (portRef SP (instanceRef FF_60))
+              (portRef SP (instanceRef FF_59))
+              (portRef SP (instanceRef FF_58))
+              (portRef SP (instanceRef FF_57))
+              (portRef SP (instanceRef FF_56))
+              (portRef SP (instanceRef FF_55))
+              (portRef SP (instanceRef FF_54))))
+          (net empty_d
+            (joined
+              (portRef D (instanceRef FF_52))
+              (portRef DO0 (instanceRef LUT4_1))))
+          (net full_d
+            (joined
+              (portRef D (instanceRef FF_51))
+              (portRef DO0 (instanceRef LUT4_0))))
+          (net wptr_0
+            (joined
+              (portRef Q (instanceRef FF_30))
+              (portRef ADW0 (instanceRef pdp_ram_0_0_0))))
+          (net wptr_1
+            (joined
+              (portRef Q (instanceRef FF_29))
+              (portRef ADW1 (instanceRef pdp_ram_0_0_0))))
+          (net wptr_2
+            (joined
+              (portRef Q (instanceRef FF_28))
+              (portRef ADW2 (instanceRef pdp_ram_0_0_0))))
+          (net wptr_3
+            (joined
+              (portRef Q (instanceRef FF_27))
+              (portRef ADW3 (instanceRef pdp_ram_0_0_0))))
+          (net wptr_4
+            (joined
+              (portRef Q (instanceRef FF_26))
+              (portRef ADW4 (instanceRef pdp_ram_0_0_0))))
+          (net wptr_5
+            (joined
+              (portRef Q (instanceRef FF_25))
+              (portRef ADW5 (instanceRef pdp_ram_0_0_0))))
+          (net wptr_6
+            (joined
+              (portRef Q (instanceRef FF_24))
+              (portRef ADW6 (instanceRef pdp_ram_0_0_0))))
+          (net wptr_7
+            (joined
+              (portRef Q (instanceRef FF_23))
+              (portRef ADW7 (instanceRef pdp_ram_0_0_0))))
+          (net wptr_8
+            (joined
+              (portRef Q (instanceRef FF_22))
+              (portRef ADW8 (instanceRef pdp_ram_0_0_0))))
+          (net wptr_9
+            (joined
+              (portRef Q (instanceRef FF_21))))
+          (net rptr_9
+            (joined
+              (portRef Q (instanceRef FF_11))
+              (portRef B (instanceRef XOR2_t0))))
+          (net ifcount_0
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_0))
+              (portRef D (instanceRef FF_62))))
+          (net ifcount_1
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_0))
+              (portRef D (instanceRef FF_61))))
+          (net bdcnt_bctr_ci
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_0))
+              (portRef COUT (instanceRef bdcnt_bctr_cia))))
+          (net ifcount_2
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_1))
+              (portRef D (instanceRef FF_60))))
+          (net ifcount_3
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_1))
+              (portRef D (instanceRef FF_59))))
+          (net co0
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_1))
+              (portRef COUT (instanceRef bdcnt_bctr_0))))
+          (net ifcount_4
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_2))
+              (portRef D (instanceRef FF_58))))
+          (net ifcount_5
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_2))
+              (portRef D (instanceRef FF_57))))
+          (net co1
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_2))
+              (portRef COUT (instanceRef bdcnt_bctr_1))))
+          (net ifcount_6
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_3))
+              (portRef D (instanceRef FF_56))))
+          (net ifcount_7
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_3))
+              (portRef D (instanceRef FF_55))))
+          (net co2
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_3))
+              (portRef COUT (instanceRef bdcnt_bctr_2))))
+          (net ifcount_8
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_4))
+              (portRef D (instanceRef FF_54))))
+          (net ifcount_9
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_4))
+              (portRef D (instanceRef FF_53))))
+          (net co4
+            (joined
+              (portRef COUT (instanceRef bdcnt_bctr_4))))
+          (net co3
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_4))
+              (portRef COUT (instanceRef bdcnt_bctr_3))))
+          (net cmp_ci
+            (joined
+              (portRef CIN (instanceRef e_cmp_0))
+              (portRef COUT (instanceRef e_cmp_ci_a))))
+          (net rden_i
+            (joined
+              (portRef A0 (instanceRef e_cmp_0))
+              (portRef Z (instanceRef AND2_t4))
+              (portRef B (instanceRef XOR2_t2))
+              (portRef A (instanceRef INV_3))
+              (portRef AD1 (instanceRef LUT4_0))
+              (portRef A (instanceRef AND2_t1))
+              (portRef CSR0 (instanceRef pdp_ram_0_0_0))
+              (portRef SP (instanceRef FF_40))
+              (portRef SP (instanceRef FF_39))
+              (portRef SP (instanceRef FF_38))
+              (portRef SP (instanceRef FF_37))
+              (portRef SP (instanceRef FF_36))
+              (portRef SP (instanceRef FF_35))
+              (portRef SP (instanceRef FF_34))
+              (portRef SP (instanceRef FF_33))
+              (portRef SP (instanceRef FF_32))
+              (portRef SP (instanceRef FF_31))
+              (portRef SP (instanceRef FF_20))
+              (portRef SP (instanceRef FF_19))
+              (portRef SP (instanceRef FF_18))
+              (portRef SP (instanceRef FF_17))
+              (portRef SP (instanceRef FF_16))
+              (portRef SP (instanceRef FF_15))
+              (portRef SP (instanceRef FF_14))
+              (portRef SP (instanceRef FF_13))
+              (portRef SP (instanceRef FF_12))
+              (portRef SP (instanceRef FF_11))))
+          (net co0_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_1))
+              (portRef COUT (instanceRef e_cmp_0))))
+          (net co1_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_2))
+              (portRef COUT (instanceRef e_cmp_1))))
+          (net co2_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_3))
+              (portRef COUT (instanceRef e_cmp_2))))
+          (net co3_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_4))
+              (portRef COUT (instanceRef e_cmp_3))))
+          (net cmp_le_1
+            (joined
+              (portRef S0 (instanceRef a0))
+              (portRef AD2 (instanceRef LUT4_1))))
+          (net cmp_le_1_c
+            (joined
+              (portRef CIN (instanceRef a0))
+              (portRef COUT (instanceRef e_cmp_4))))
+          (net cmp_ci_1
+            (joined
+              (portRef CIN (instanceRef g_cmp_0))
+              (portRef COUT (instanceRef g_cmp_ci_a))))
+          (net co0_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_1))
+              (portRef COUT (instanceRef g_cmp_0))))
+          (net co1_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_2))
+              (portRef COUT (instanceRef g_cmp_1))))
+          (net co2_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_3))
+              (portRef COUT (instanceRef g_cmp_2))))
+          (net co3_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_4))
+              (portRef COUT (instanceRef g_cmp_3))))
+          (net wren_i_inv
+            (joined
+              (portRef B1 (instanceRef g_cmp_4))
+              (portRef Z (instanceRef INV_2))))
+          (net cmp_ge_d1
+            (joined
+              (portRef S0 (instanceRef a1))
+              (portRef AD2 (instanceRef LUT4_0))))
+          (net cmp_ge_d1_c
+            (joined
+              (portRef CIN (instanceRef a1))
+              (portRef COUT (instanceRef g_cmp_4))))
+          (net iwcount_0
+            (joined
+              (portRef S0 (instanceRef w_ctr_0))
+              (portRef D (instanceRef FF_50))))
+          (net iwcount_1
+            (joined
+              (portRef S1 (instanceRef w_ctr_0))
+              (portRef D (instanceRef FF_49))))
+          (net w_ctr_ci
+            (joined
+              (portRef CIN (instanceRef w_ctr_0))
+              (portRef COUT (instanceRef w_ctr_cia))))
+          (net iwcount_2
+            (joined
+              (portRef S0 (instanceRef w_ctr_1))
+              (portRef D (instanceRef FF_48))))
+          (net iwcount_3
+            (joined
+              (portRef S1 (instanceRef w_ctr_1))
+              (portRef D (instanceRef FF_47))))
+          (net co0_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_1))
+              (portRef COUT (instanceRef w_ctr_0))))
+          (net iwcount_4
+            (joined
+              (portRef S0 (instanceRef w_ctr_2))
+              (portRef D (instanceRef FF_46))))
+          (net iwcount_5
+            (joined
+              (portRef S1 (instanceRef w_ctr_2))
+              (portRef D (instanceRef FF_45))))
+          (net co1_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_2))
+              (portRef COUT (instanceRef w_ctr_1))))
+          (net iwcount_6
+            (joined
+              (portRef S0 (instanceRef w_ctr_3))
+              (portRef D (instanceRef FF_44))))
+          (net iwcount_7
+            (joined
+              (portRef S1 (instanceRef w_ctr_3))
+              (portRef D (instanceRef FF_43))))
+          (net co2_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_3))
+              (portRef COUT (instanceRef w_ctr_2))))
+          (net iwcount_8
+            (joined
+              (portRef S0 (instanceRef w_ctr_4))
+              (portRef D (instanceRef FF_42))))
+          (net iwcount_9
+            (joined
+              (portRef S1 (instanceRef w_ctr_4))
+              (portRef D (instanceRef FF_41))))
+          (net co4_1
+            (joined
+              (portRef COUT (instanceRef w_ctr_4))))
+          (net co3_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_4))
+              (portRef COUT (instanceRef w_ctr_3))))
+          (net wcount_9
+            (joined
+              (portRef A1 (instanceRef w_ctr_4))
+              (portRef A (instanceRef XOR2_t0))
+              (portRef Q (instanceRef FF_41))
+              (portRef D (instanceRef FF_21))))
+          (net ircount_0
+            (joined
+              (portRef S0 (instanceRef r_ctr_0))
+              (portRef D (instanceRef FF_40))))
+          (net ircount_1
+            (joined
+              (portRef S1 (instanceRef r_ctr_0))
+              (portRef D (instanceRef FF_39))))
+          (net r_ctr_ci
+            (joined
+              (portRef CIN (instanceRef r_ctr_0))
+              (portRef COUT (instanceRef r_ctr_cia))))
+          (net rcount_0
+            (joined
+              (portRef A0 (instanceRef r_ctr_0))
+              (portRef Q (instanceRef FF_40))
+              (portRef D (instanceRef FF_20))))
+          (net rcount_1
+            (joined
+              (portRef A1 (instanceRef r_ctr_0))
+              (portRef Q (instanceRef FF_39))
+              (portRef D (instanceRef FF_19))))
+          (net ircount_2
+            (joined
+              (portRef S0 (instanceRef r_ctr_1))
+              (portRef D (instanceRef FF_38))))
+          (net ircount_3
+            (joined
+              (portRef S1 (instanceRef r_ctr_1))
+              (portRef D (instanceRef FF_37))))
+          (net co0_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_1))
+              (portRef COUT (instanceRef r_ctr_0))))
+          (net rcount_2
+            (joined
+              (portRef A0 (instanceRef r_ctr_1))
+              (portRef Q (instanceRef FF_38))
+              (portRef D (instanceRef FF_18))))
+          (net rcount_3
+            (joined
+              (portRef A1 (instanceRef r_ctr_1))
+              (portRef Q (instanceRef FF_37))
+              (portRef D (instanceRef FF_17))))
+          (net ircount_4
+            (joined
+              (portRef S0 (instanceRef r_ctr_2))
+              (portRef D (instanceRef FF_36))))
+          (net ircount_5
+            (joined
+              (portRef S1 (instanceRef r_ctr_2))
+              (portRef D (instanceRef FF_35))))
+          (net co1_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_2))
+              (portRef COUT (instanceRef r_ctr_1))))
+          (net rcount_4
+            (joined
+              (portRef A0 (instanceRef r_ctr_2))
+              (portRef Q (instanceRef FF_36))
+              (portRef D (instanceRef FF_16))))
+          (net rcount_5
+            (joined
+              (portRef A1 (instanceRef r_ctr_2))
+              (portRef Q (instanceRef FF_35))
+              (portRef D (instanceRef FF_15))))
+          (net ircount_6
+            (joined
+              (portRef S0 (instanceRef r_ctr_3))
+              (portRef D (instanceRef FF_34))))
+          (net ircount_7
+            (joined
+              (portRef S1 (instanceRef r_ctr_3))
+              (portRef D (instanceRef FF_33))))
+          (net co2_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_3))
+              (portRef COUT (instanceRef r_ctr_2))))
+          (net rcount_6
+            (joined
+              (portRef A0 (instanceRef r_ctr_3))
+              (portRef Q (instanceRef FF_34))
+              (portRef D (instanceRef FF_14))))
+          (net rcount_7
+            (joined
+              (portRef A1 (instanceRef r_ctr_3))
+              (portRef Q (instanceRef FF_33))
+              (portRef D (instanceRef FF_13))))
+          (net ircount_8
+            (joined
+              (portRef S0 (instanceRef r_ctr_4))
+              (portRef D (instanceRef FF_32))))
+          (net ircount_9
+            (joined
+              (portRef S1 (instanceRef r_ctr_4))
+              (portRef D (instanceRef FF_31))))
+          (net co4_2
+            (joined
+              (portRef COUT (instanceRef r_ctr_4))))
+          (net co3_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_4))
+              (portRef COUT (instanceRef r_ctr_3))))
+          (net rcount_8
+            (joined
+              (portRef A0 (instanceRef r_ctr_4))
+              (portRef Q (instanceRef FF_32))
+              (portRef D (instanceRef FF_12))))
+          (net rcount_9
+            (joined
+              (portRef A1 (instanceRef r_ctr_4))
+              (portRef Q (instanceRef FF_31))
+              (portRef D (instanceRef FF_11))))
+          (net wcnt_sub_0
+            (joined
+              (portRef S1 (instanceRef wcnt_0))
+              (portRef D (instanceRef FF_10))))
+          (net rptr_0
+            (joined
+              (portRef B1 (instanceRef wcnt_0))
+              (portRef ADR5 (instanceRef pdp_ram_0_0_0))
+              (portRef Q (instanceRef FF_20))))
+          (net cnt_con_inv
+            (joined
+              (portRef B0 (instanceRef wcnt_0))
+              (portRef Z (instanceRef INV_0))))
+          (net wcount_0
+            (joined
+              (portRef A1 (instanceRef wcnt_0))
+              (portRef Q (instanceRef FF_50))
+              (portRef D (instanceRef FF_30))
+              (portRef A0 (instanceRef w_ctr_0))))
+          (net cnt_con
+            (joined
+              (portRef A0 (instanceRef wcnt_0))
+              (portRef Z (instanceRef AND2_t3))
+              (portRef A (instanceRef INV_0))
+              (portRef B1 (instanceRef bdcnt_bctr_cia))
+              (portRef A1 (instanceRef bdcnt_bctr_cia))
+              (portRef B1 (instanceRef bdcnt_bctr_0))
+              (portRef B0 (instanceRef bdcnt_bctr_0))
+              (portRef B1 (instanceRef bdcnt_bctr_1))
+              (portRef B0 (instanceRef bdcnt_bctr_1))
+              (portRef B1 (instanceRef bdcnt_bctr_2))
+              (portRef B0 (instanceRef bdcnt_bctr_2))
+              (portRef B1 (instanceRef bdcnt_bctr_3))
+              (portRef B0 (instanceRef bdcnt_bctr_3))
+              (portRef B1 (instanceRef bdcnt_bctr_4))
+              (portRef B0 (instanceRef bdcnt_bctr_4))))
+          (net precin
+            (joined
+              (portRef CIN (instanceRef wcnt_0))
+              (portRef COUT (instanceRef precin_inst218))))
+          (net wcnt_sub_1
+            (joined
+              (portRef S0 (instanceRef wcnt_1))
+              (portRef D (instanceRef FF_9))))
+          (net wcnt_sub_2
+            (joined
+              (portRef S1 (instanceRef wcnt_1))
+              (portRef D (instanceRef FF_8))))
+          (net rptr_2
+            (joined
+              (portRef B1 (instanceRef wcnt_1))
+              (portRef ADR7 (instanceRef pdp_ram_0_0_0))
+              (portRef Q (instanceRef FF_18))))
+          (net rptr_1
+            (joined
+              (portRef B0 (instanceRef wcnt_1))
+              (portRef ADR6 (instanceRef pdp_ram_0_0_0))
+              (portRef Q (instanceRef FF_19))))
+          (net wcount_2
+            (joined
+              (portRef A1 (instanceRef wcnt_1))
+              (portRef Q (instanceRef FF_48))
+              (portRef D (instanceRef FF_28))
+              (portRef A0 (instanceRef w_ctr_1))))
+          (net wcount_1
+            (joined
+              (portRef A0 (instanceRef wcnt_1))
+              (portRef Q (instanceRef FF_49))
+              (portRef D (instanceRef FF_29))
+              (portRef A1 (instanceRef w_ctr_0))))
+          (net co0_5
+            (joined
+              (portRef CIN (instanceRef wcnt_1))
+              (portRef COUT (instanceRef wcnt_0))))
+          (net wcnt_sub_3
+            (joined
+              (portRef S0 (instanceRef wcnt_2))
+              (portRef D (instanceRef FF_7))))
+          (net wcnt_sub_4
+            (joined
+              (portRef S1 (instanceRef wcnt_2))
+              (portRef D (instanceRef FF_6))))
+          (net rptr_4
+            (joined
+              (portRef B1 (instanceRef wcnt_2))
+              (portRef ADR9 (instanceRef pdp_ram_0_0_0))
+              (portRef Q (instanceRef FF_16))))
+          (net rptr_3
+            (joined
+              (portRef B0 (instanceRef wcnt_2))
+              (portRef ADR8 (instanceRef pdp_ram_0_0_0))
+              (portRef Q (instanceRef FF_17))))
+          (net wcount_4
+            (joined
+              (portRef A1 (instanceRef wcnt_2))
+              (portRef Q (instanceRef FF_46))
+              (portRef D (instanceRef FF_26))
+              (portRef A0 (instanceRef w_ctr_2))))
+          (net wcount_3
+            (joined
+              (portRef A0 (instanceRef wcnt_2))
+              (portRef Q (instanceRef FF_47))
+              (portRef D (instanceRef FF_27))
+              (portRef A1 (instanceRef w_ctr_1))))
+          (net co1_5
+            (joined
+              (portRef CIN (instanceRef wcnt_2))
+              (portRef COUT (instanceRef wcnt_1))))
+          (net wcnt_sub_5
+            (joined
+              (portRef S0 (instanceRef wcnt_3))
+              (portRef D (instanceRef FF_5))))
+          (net wcnt_sub_6
+            (joined
+              (portRef S1 (instanceRef wcnt_3))
+              (portRef D (instanceRef FF_4))))
+          (net rptr_6
+            (joined
+              (portRef B1 (instanceRef wcnt_3))
+              (portRef ADR11 (instanceRef pdp_ram_0_0_0))
+              (portRef Q (instanceRef FF_14))))
+          (net rptr_5
+            (joined
+              (portRef B0 (instanceRef wcnt_3))
+              (portRef ADR10 (instanceRef pdp_ram_0_0_0))
+              (portRef Q (instanceRef FF_15))))
+          (net wcount_6
+            (joined
+              (portRef A1 (instanceRef wcnt_3))
+              (portRef Q (instanceRef FF_44))
+              (portRef D (instanceRef FF_24))
+              (portRef A0 (instanceRef w_ctr_3))))
+          (net wcount_5
+            (joined
+              (portRef A0 (instanceRef wcnt_3))
+              (portRef Q (instanceRef FF_45))
+              (portRef D (instanceRef FF_25))
+              (portRef A1 (instanceRef w_ctr_2))))
+          (net co2_5
+            (joined
+              (portRef CIN (instanceRef wcnt_3))
+              (portRef COUT (instanceRef wcnt_2))))
+          (net wcnt_sub_7
+            (joined
+              (portRef S0 (instanceRef wcnt_4))
+              (portRef D (instanceRef FF_3))))
+          (net wcnt_sub_8
+            (joined
+              (portRef S1 (instanceRef wcnt_4))
+              (portRef D (instanceRef FF_2))))
+          (net rptr_8
+            (joined
+              (portRef B1 (instanceRef wcnt_4))
+              (portRef ADR13 (instanceRef pdp_ram_0_0_0))
+              (portRef Q (instanceRef FF_12))))
+          (net rptr_7
+            (joined
+              (portRef B0 (instanceRef wcnt_4))
+              (portRef ADR12 (instanceRef pdp_ram_0_0_0))
+              (portRef Q (instanceRef FF_13))))
+          (net wcount_8
+            (joined
+              (portRef A1 (instanceRef wcnt_4))
+              (portRef Q (instanceRef FF_42))
+              (portRef D (instanceRef FF_22))
+              (portRef A0 (instanceRef w_ctr_4))))
+          (net wcount_7
+            (joined
+              (portRef A0 (instanceRef wcnt_4))
+              (portRef Q (instanceRef FF_43))
+              (portRef D (instanceRef FF_23))
+              (portRef A1 (instanceRef w_ctr_3))))
+          (net co3_5
+            (joined
+              (portRef CIN (instanceRef wcnt_4))
+              (portRef COUT (instanceRef wcnt_3))))
+          (net wcnt_sub_9
+            (joined
+              (portRef S0 (instanceRef wcnt_5))
+              (portRef D (instanceRef FF_1))))
+          (net wcnt_sub_msb
+            (joined
+              (portRef A0 (instanceRef wcnt_5))
+              (portRef Z (instanceRef XOR2_t0))))
+          (net co4_3
+            (joined
+              (portRef CIN (instanceRef wcnt_5))
+              (portRef COUT (instanceRef wcnt_4))))
+          (net wren_i
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_ci_a))
+              (portRef Z (instanceRef AND2_t5))
+              (portRef A (instanceRef AND2_t3))
+              (portRef A (instanceRef XOR2_t2))
+              (portRef A (instanceRef INV_2))
+              (portRef AD1 (instanceRef LUT4_1))
+              (portRef A (instanceRef INV_1))
+              (portRef CEW (instanceRef pdp_ram_0_0_0))
+              (portRef SP (instanceRef FF_50))
+              (portRef SP (instanceRef FF_49))
+              (portRef SP (instanceRef FF_48))
+              (portRef SP (instanceRef FF_47))
+              (portRef SP (instanceRef FF_46))
+              (portRef SP (instanceRef FF_45))
+              (portRef SP (instanceRef FF_44))
+              (portRef SP (instanceRef FF_43))
+              (portRef SP (instanceRef FF_42))
+              (portRef SP (instanceRef FF_41))
+              (portRef SP (instanceRef FF_30))
+              (portRef SP (instanceRef FF_29))
+              (portRef SP (instanceRef FF_28))
+              (portRef SP (instanceRef FF_27))
+              (portRef SP (instanceRef FF_26))
+              (portRef SP (instanceRef FF_25))
+              (portRef SP (instanceRef FF_24))
+              (portRef SP (instanceRef FF_23))
+              (portRef SP (instanceRef FF_22))
+              (portRef SP (instanceRef FF_21))
+              (portRef B0 (instanceRef g_cmp_0))
+              (portRef B1 (instanceRef g_cmp_0))
+              (portRef B0 (instanceRef g_cmp_1))
+              (portRef B1 (instanceRef g_cmp_1))
+              (portRef B0 (instanceRef g_cmp_2))
+              (portRef B1 (instanceRef g_cmp_2))
+              (portRef B0 (instanceRef g_cmp_3))
+              (portRef B1 (instanceRef g_cmp_3))
+              (portRef B0 (instanceRef g_cmp_4))
+              (portRef B1 (instanceRef af_set_cmp_ci_a))))
+          (net x
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_ci_a))
+              (portRef CIN (instanceRef bdcnt_bctr_cia))
+              (portRef CIN (instanceRef e_cmp_ci_a))
+              (portRef CIN (instanceRef g_cmp_ci_a))
+              (portRef CIN (instanceRef w_ctr_cia))
+              (portRef CIN (instanceRef r_ctr_cia))
+              (portRef CIN (instanceRef precin_inst218))))
+          (net cmp_ci_2
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_0))
+              (portRef COUT (instanceRef af_set_cmp_ci_a))))
+          (net wcnt_reg_0
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_0))
+              (portRef Q (instanceRef FF_10))))
+          (net wcnt_reg_1
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_0))
+              (portRef Q (instanceRef FF_9))))
+          (net co0_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_1))
+              (portRef COUT (instanceRef af_set_cmp_0))))
+          (net wcnt_reg_2
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_1))
+              (portRef Q (instanceRef FF_8))))
+          (net wcnt_reg_3
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_1))
+              (portRef Q (instanceRef FF_7))))
+          (net co1_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_2))
+              (portRef COUT (instanceRef af_set_cmp_1))))
+          (net wcnt_reg_4
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_2))
+              (portRef Q (instanceRef FF_6))))
+          (net wcnt_reg_5
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_2))
+              (portRef Q (instanceRef FF_5))))
+          (net co2_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_3))
+              (portRef COUT (instanceRef af_set_cmp_2))))
+          (net wcnt_reg_6
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_3))
+              (portRef Q (instanceRef FF_4))))
+          (net wcnt_reg_7
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_3))
+              (portRef Q (instanceRef FF_3))))
+          (net co3_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_4))
+              (portRef COUT (instanceRef af_set_cmp_3))))
+          (net wcnt_reg_8
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_4))
+              (portRef Q (instanceRef FF_2))))
+          (net wcnt_reg_9
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_4))
+              (portRef Q (instanceRef FF_1))))
+          (net af_set
+            (joined
+              (portRef S0 (instanceRef a2))
+              (portRef D (instanceRef FF_0))))
+          (net scuba_vhi
+            (joined
+              (portRef Z (instanceRef scuba_vhi_inst))
+              (portRef CSW0 (instanceRef pdp_ram_0_0_0))
+              (portRef BE3 (instanceRef pdp_ram_0_0_0))
+              (portRef BE2 (instanceRef pdp_ram_0_0_0))
+              (portRef BE1 (instanceRef pdp_ram_0_0_0))
+              (portRef BE0 (instanceRef pdp_ram_0_0_0))
+              (portRef OCER (instanceRef pdp_ram_0_0_0))
+              (portRef CER (instanceRef pdp_ram_0_0_0))
+              (portRef C1 (instanceRef bdcnt_bctr_cia))
+              (portRef C0 (instanceRef bdcnt_bctr_cia))
+              (portRef D1 (instanceRef bdcnt_bctr_cia))
+              (portRef D0 (instanceRef bdcnt_bctr_cia))
+              (portRef D1 (instanceRef bdcnt_bctr_0))
+              (portRef D0 (instanceRef bdcnt_bctr_0))
+              (portRef C1 (instanceRef bdcnt_bctr_0))
+              (portRef C0 (instanceRef bdcnt_bctr_0))
+              (portRef D1 (instanceRef bdcnt_bctr_1))
+              (portRef D0 (instanceRef bdcnt_bctr_1))
+              (portRef C1 (instanceRef bdcnt_bctr_1))
+              (portRef C0 (instanceRef bdcnt_bctr_1))
+              (portRef D1 (instanceRef bdcnt_bctr_2))
+              (portRef D0 (instanceRef bdcnt_bctr_2))
+              (portRef C1 (instanceRef bdcnt_bctr_2))
+              (portRef C0 (instanceRef bdcnt_bctr_2))
+              (portRef D1 (instanceRef bdcnt_bctr_3))
+              (portRef D0 (instanceRef bdcnt_bctr_3))
+              (portRef C1 (instanceRef bdcnt_bctr_3))
+              (portRef C0 (instanceRef bdcnt_bctr_3))
+              (portRef D1 (instanceRef bdcnt_bctr_4))
+              (portRef D0 (instanceRef bdcnt_bctr_4))
+              (portRef C1 (instanceRef bdcnt_bctr_4))
+              (portRef C0 (instanceRef bdcnt_bctr_4))
+              (portRef C1 (instanceRef e_cmp_ci_a))
+              (portRef C0 (instanceRef e_cmp_ci_a))
+              (portRef D1 (instanceRef e_cmp_ci_a))
+              (portRef D0 (instanceRef e_cmp_ci_a))
+              (portRef B1 (instanceRef e_cmp_ci_a))
+              (portRef B0 (instanceRef e_cmp_ci_a))
+              (portRef A1 (instanceRef e_cmp_ci_a))
+              (portRef A0 (instanceRef e_cmp_ci_a))
+              (portRef D1 (instanceRef e_cmp_0))
+              (portRef D0 (instanceRef e_cmp_0))
+              (portRef C1 (instanceRef e_cmp_0))
+              (portRef C0 (instanceRef e_cmp_0))
+              (portRef D1 (instanceRef e_cmp_1))
+              (portRef D0 (instanceRef e_cmp_1))
+              (portRef C1 (instanceRef e_cmp_1))
+              (portRef C0 (instanceRef e_cmp_1))
+              (portRef D1 (instanceRef e_cmp_2))
+              (portRef D0 (instanceRef e_cmp_2))
+              (portRef C1 (instanceRef e_cmp_2))
+              (portRef C0 (instanceRef e_cmp_2))
+              (portRef D1 (instanceRef e_cmp_3))
+              (portRef D0 (instanceRef e_cmp_3))
+              (portRef C1 (instanceRef e_cmp_3))
+              (portRef C0 (instanceRef e_cmp_3))
+              (portRef D1 (instanceRef e_cmp_4))
+              (portRef D0 (instanceRef e_cmp_4))
+              (portRef C1 (instanceRef e_cmp_4))
+              (portRef C0 (instanceRef e_cmp_4))
+              (portRef C1 (instanceRef a0))
+              (portRef C0 (instanceRef a0))
+              (portRef D1 (instanceRef a0))
+              (portRef D0 (instanceRef a0))
+              (portRef C1 (instanceRef g_cmp_ci_a))
+              (portRef C0 (instanceRef g_cmp_ci_a))
+              (portRef D1 (instanceRef g_cmp_ci_a))
+              (portRef D0 (instanceRef g_cmp_ci_a))
+              (portRef B1 (instanceRef g_cmp_ci_a))
+              (portRef B0 (instanceRef g_cmp_ci_a))
+              (portRef A1 (instanceRef g_cmp_ci_a))
+              (portRef A0 (instanceRef g_cmp_ci_a))
+              (portRef D1 (instanceRef g_cmp_0))
+              (portRef D0 (instanceRef g_cmp_0))
+              (portRef C1 (instanceRef g_cmp_0))
+              (portRef C0 (instanceRef g_cmp_0))
+              (portRef D1 (instanceRef g_cmp_1))
+              (portRef D0 (instanceRef g_cmp_1))
+              (portRef C1 (instanceRef g_cmp_1))
+              (portRef C0 (instanceRef g_cmp_1))
+              (portRef D1 (instanceRef g_cmp_2))
+              (portRef D0 (instanceRef g_cmp_2))
+              (portRef C1 (instanceRef g_cmp_2))
+              (portRef C0 (instanceRef g_cmp_2))
+              (portRef D1 (instanceRef g_cmp_3))
+              (portRef D0 (instanceRef g_cmp_3))
+              (portRef C1 (instanceRef g_cmp_3))
+              (portRef C0 (instanceRef g_cmp_3))
+              (portRef D1 (instanceRef g_cmp_4))
+              (portRef D0 (instanceRef g_cmp_4))
+              (portRef C1 (instanceRef g_cmp_4))
+              (portRef C0 (instanceRef g_cmp_4))
+              (portRef C1 (instanceRef a1))
+              (portRef C0 (instanceRef a1))
+              (portRef D1 (instanceRef a1))
+              (portRef D0 (instanceRef a1))
+              (portRef C1 (instanceRef w_ctr_cia))
+              (portRef C0 (instanceRef w_ctr_cia))
+              (portRef D1 (instanceRef w_ctr_cia))
+              (portRef D0 (instanceRef w_ctr_cia))
+              (portRef B1 (instanceRef w_ctr_cia))
+              (portRef A1 (instanceRef w_ctr_cia))
+              (portRef D1 (instanceRef w_ctr_0))
+              (portRef D0 (instanceRef w_ctr_0))
+              (portRef C1 (instanceRef w_ctr_0))
+              (portRef C0 (instanceRef w_ctr_0))
+              (portRef D1 (instanceRef w_ctr_1))
+              (portRef D0 (instanceRef w_ctr_1))
+              (portRef C1 (instanceRef w_ctr_1))
+              (portRef C0 (instanceRef w_ctr_1))
+              (portRef D1 (instanceRef w_ctr_2))
+              (portRef D0 (instanceRef w_ctr_2))
+              (portRef C1 (instanceRef w_ctr_2))
+              (portRef C0 (instanceRef w_ctr_2))
+              (portRef D1 (instanceRef w_ctr_3))
+              (portRef D0 (instanceRef w_ctr_3))
+              (portRef C1 (instanceRef w_ctr_3))
+              (portRef C0 (instanceRef w_ctr_3))
+              (portRef D1 (instanceRef w_ctr_4))
+              (portRef D0 (instanceRef w_ctr_4))
+              (portRef C1 (instanceRef w_ctr_4))
+              (portRef C0 (instanceRef w_ctr_4))
+              (portRef C1 (instanceRef r_ctr_cia))
+              (portRef C0 (instanceRef r_ctr_cia))
+              (portRef D1 (instanceRef r_ctr_cia))
+              (portRef D0 (instanceRef r_ctr_cia))
+              (portRef B1 (instanceRef r_ctr_cia))
+              (portRef A1 (instanceRef r_ctr_cia))
+              (portRef D1 (instanceRef r_ctr_0))
+              (portRef D0 (instanceRef r_ctr_0))
+              (portRef C1 (instanceRef r_ctr_0))
+              (portRef C0 (instanceRef r_ctr_0))
+              (portRef D1 (instanceRef r_ctr_1))
+              (portRef D0 (instanceRef r_ctr_1))
+              (portRef C1 (instanceRef r_ctr_1))
+              (portRef C0 (instanceRef r_ctr_1))
+              (portRef D1 (instanceRef r_ctr_2))
+              (portRef D0 (instanceRef r_ctr_2))
+              (portRef C1 (instanceRef r_ctr_2))
+              (portRef C0 (instanceRef r_ctr_2))
+              (portRef D1 (instanceRef r_ctr_3))
+              (portRef D0 (instanceRef r_ctr_3))
+              (portRef C1 (instanceRef r_ctr_3))
+              (portRef C0 (instanceRef r_ctr_3))
+              (portRef D1 (instanceRef r_ctr_4))
+              (portRef D0 (instanceRef r_ctr_4))
+              (portRef C1 (instanceRef r_ctr_4))
+              (portRef C0 (instanceRef r_ctr_4))
+              (portRef C1 (instanceRef precin_inst218))
+              (portRef C0 (instanceRef precin_inst218))
+              (portRef D1 (instanceRef precin_inst218))
+              (portRef D0 (instanceRef precin_inst218))
+              (portRef B1 (instanceRef precin_inst218))
+              (portRef B0 (instanceRef precin_inst218))
+              (portRef A1 (instanceRef precin_inst218))
+              (portRef A0 (instanceRef precin_inst218))
+              (portRef C1 (instanceRef wcnt_0))
+              (portRef C0 (instanceRef wcnt_0))
+              (portRef D1 (instanceRef wcnt_0))
+              (portRef D0 (instanceRef wcnt_0))
+              (portRef C1 (instanceRef wcnt_1))
+              (portRef C0 (instanceRef wcnt_1))
+              (portRef D1 (instanceRef wcnt_1))
+              (portRef D0 (instanceRef wcnt_1))
+              (portRef C1 (instanceRef wcnt_2))
+              (portRef C0 (instanceRef wcnt_2))
+              (portRef D1 (instanceRef wcnt_2))
+              (portRef D0 (instanceRef wcnt_2))
+              (portRef C1 (instanceRef wcnt_3))
+              (portRef C0 (instanceRef wcnt_3))
+              (portRef D1 (instanceRef wcnt_3))
+              (portRef D0 (instanceRef wcnt_3))
+              (portRef C1 (instanceRef wcnt_4))
+              (portRef C0 (instanceRef wcnt_4))
+              (portRef D1 (instanceRef wcnt_4))
+              (portRef D0 (instanceRef wcnt_4))
+              (portRef C1 (instanceRef wcnt_5))
+              (portRef C0 (instanceRef wcnt_5))
+              (portRef D1 (instanceRef wcnt_5))
+              (portRef D0 (instanceRef wcnt_5))
+              (portRef C1 (instanceRef af_set_cmp_ci_a))
+              (portRef C0 (instanceRef af_set_cmp_ci_a))
+              (portRef D1 (instanceRef af_set_cmp_ci_a))
+              (portRef D0 (instanceRef af_set_cmp_ci_a))
+              (portRef D1 (instanceRef af_set_cmp_0))
+              (portRef D0 (instanceRef af_set_cmp_0))
+              (portRef C1 (instanceRef af_set_cmp_0))
+              (portRef C0 (instanceRef af_set_cmp_0))
+              (portRef D1 (instanceRef af_set_cmp_1))
+              (portRef D0 (instanceRef af_set_cmp_1))
+              (portRef C1 (instanceRef af_set_cmp_1))
+              (portRef C0 (instanceRef af_set_cmp_1))
+              (portRef D1 (instanceRef af_set_cmp_2))
+              (portRef D0 (instanceRef af_set_cmp_2))
+              (portRef C1 (instanceRef af_set_cmp_2))
+              (portRef C0 (instanceRef af_set_cmp_2))
+              (portRef D1 (instanceRef af_set_cmp_3))
+              (portRef D0 (instanceRef af_set_cmp_3))
+              (portRef C1 (instanceRef af_set_cmp_3))
+              (portRef C0 (instanceRef af_set_cmp_3))
+              (portRef D1 (instanceRef af_set_cmp_4))
+              (portRef D0 (instanceRef af_set_cmp_4))
+              (portRef C1 (instanceRef af_set_cmp_4))
+              (portRef C0 (instanceRef af_set_cmp_4))
+              (portRef C1 (instanceRef a2))
+              (portRef C0 (instanceRef a2))
+              (portRef D1 (instanceRef a2))
+              (portRef D0 (instanceRef a2))))
+          (net scuba_vlo
+            (joined
+              (portRef Z (instanceRef scuba_vlo_inst))
+              (portRef AD3 (instanceRef LUT4_1))
+              (portRef AD3 (instanceRef LUT4_0))
+              (portRef CSR2 (instanceRef pdp_ram_0_0_0))
+              (portRef CSW2 (instanceRef pdp_ram_0_0_0))
+              (portRef CSR1 (instanceRef pdp_ram_0_0_0))
+              (portRef CSW1 (instanceRef pdp_ram_0_0_0))
+              (portRef ADR4 (instanceRef pdp_ram_0_0_0))
+              (portRef ADR3 (instanceRef pdp_ram_0_0_0))
+              (portRef ADR2 (instanceRef pdp_ram_0_0_0))
+              (portRef ADR1 (instanceRef pdp_ram_0_0_0))
+              (portRef ADR0 (instanceRef pdp_ram_0_0_0))
+              (portRef DI35 (instanceRef pdp_ram_0_0_0))
+              (portRef DI34 (instanceRef pdp_ram_0_0_0))
+              (portRef DI33 (instanceRef pdp_ram_0_0_0))
+              (portRef DI32 (instanceRef pdp_ram_0_0_0))
+              (portRef DI31 (instanceRef pdp_ram_0_0_0))
+              (portRef DI30 (instanceRef pdp_ram_0_0_0))
+              (portRef DI29 (instanceRef pdp_ram_0_0_0))
+              (portRef DI28 (instanceRef pdp_ram_0_0_0))
+              (portRef DI27 (instanceRef pdp_ram_0_0_0))
+              (portRef DI26 (instanceRef pdp_ram_0_0_0))
+              (portRef DI25 (instanceRef pdp_ram_0_0_0))
+              (portRef DI24 (instanceRef pdp_ram_0_0_0))
+              (portRef DI23 (instanceRef pdp_ram_0_0_0))
+              (portRef DI22 (instanceRef pdp_ram_0_0_0))
+              (portRef DI21 (instanceRef pdp_ram_0_0_0))
+              (portRef DI20 (instanceRef pdp_ram_0_0_0))
+              (portRef DI19 (instanceRef pdp_ram_0_0_0))
+              (portRef DI18 (instanceRef pdp_ram_0_0_0))
+              (portRef B0 (instanceRef bdcnt_bctr_cia))
+              (portRef A0 (instanceRef bdcnt_bctr_cia))
+              (portRef A1 (instanceRef e_cmp_0))
+              (portRef A0 (instanceRef e_cmp_1))
+              (portRef A1 (instanceRef e_cmp_1))
+              (portRef A0 (instanceRef e_cmp_2))
+              (portRef A1 (instanceRef e_cmp_2))
+              (portRef A0 (instanceRef e_cmp_3))
+              (portRef A1 (instanceRef e_cmp_3))
+              (portRef A0 (instanceRef e_cmp_4))
+              (portRef A1 (instanceRef e_cmp_4))
+              (portRef B1 (instanceRef a0))
+              (portRef B0 (instanceRef a0))
+              (portRef A1 (instanceRef a0))
+              (portRef A0 (instanceRef a0))
+              (portRef B1 (instanceRef a1))
+              (portRef B0 (instanceRef a1))
+              (portRef A1 (instanceRef a1))
+              (portRef A0 (instanceRef a1))
+              (portRef B0 (instanceRef w_ctr_cia))
+              (portRef A0 (instanceRef w_ctr_cia))
+              (portRef B1 (instanceRef w_ctr_0))
+              (portRef B0 (instanceRef w_ctr_0))
+              (portRef B1 (instanceRef w_ctr_1))
+              (portRef B0 (instanceRef w_ctr_1))
+              (portRef B1 (instanceRef w_ctr_2))
+              (portRef B0 (instanceRef w_ctr_2))
+              (portRef B1 (instanceRef w_ctr_3))
+              (portRef B0 (instanceRef w_ctr_3))
+              (portRef B1 (instanceRef w_ctr_4))
+              (portRef B0 (instanceRef w_ctr_4))
+              (portRef B0 (instanceRef r_ctr_cia))
+              (portRef A0 (instanceRef r_ctr_cia))
+              (portRef B1 (instanceRef r_ctr_0))
+              (portRef B0 (instanceRef r_ctr_0))
+              (portRef B1 (instanceRef r_ctr_1))
+              (portRef B0 (instanceRef r_ctr_1))
+              (portRef B1 (instanceRef r_ctr_2))
+              (portRef B0 (instanceRef r_ctr_2))
+              (portRef B1 (instanceRef r_ctr_3))
+              (portRef B0 (instanceRef r_ctr_3))
+              (portRef B1 (instanceRef r_ctr_4))
+              (portRef B0 (instanceRef r_ctr_4))
+              (portRef B1 (instanceRef wcnt_5))
+              (portRef B0 (instanceRef wcnt_5))
+              (portRef A1 (instanceRef wcnt_5))
+              (portRef B0 (instanceRef af_set_cmp_ci_a))
+              (portRef A0 (instanceRef af_set_cmp_ci_a))
+              (portRef B1 (instanceRef af_set_cmp_4))
+              (portRef B1 (instanceRef a2))
+              (portRef B0 (instanceRef a2))
+              (portRef A1 (instanceRef a2))
+              (portRef A0 (instanceRef a2))))
+          (net af_set_c
+            (joined
+              (portRef CIN (instanceRef a2))
+              (portRef COUT (instanceRef af_set_cmp_4))))
+          (net partial_full
+            (joined
+              (portRef AlmostFull)
+              (portRef Q (instanceRef FF_0))))
+          (net Full
+            (joined
+              (portRef Full)
+              (portRef Q (instanceRef FF_51))
+              (portRef A (instanceRef INV_5))
+              (portRef AD0 (instanceRef LUT4_0))))
+          (net Empty
+            (joined
+              (portRef Empty)
+              (portRef Q (instanceRef FF_52))
+              (portRef A (instanceRef INV_4))
+              (portRef AD0 (instanceRef LUT4_1))))
+          (net WCNT9
+            (joined
+              (portRef (member WCNT 0))
+              (portRef A1 (instanceRef g_cmp_4))
+              (portRef Q (instanceRef FF_53))
+              (portRef A1 (instanceRef bdcnt_bctr_4))
+              (portRef B1 (instanceRef e_cmp_4))))
+          (net WCNT8
+            (joined
+              (portRef (member WCNT 1))
+              (portRef A0 (instanceRef g_cmp_4))
+              (portRef Q (instanceRef FF_54))
+              (portRef A0 (instanceRef bdcnt_bctr_4))
+              (portRef B0 (instanceRef e_cmp_4))))
+          (net WCNT7
+            (joined
+              (portRef (member WCNT 2))
+              (portRef A1 (instanceRef g_cmp_3))
+              (portRef Q (instanceRef FF_55))
+              (portRef A1 (instanceRef bdcnt_bctr_3))
+              (portRef B1 (instanceRef e_cmp_3))))
+          (net WCNT6
+            (joined
+              (portRef (member WCNT 3))
+              (portRef A0 (instanceRef g_cmp_3))
+              (portRef Q (instanceRef FF_56))
+              (portRef A0 (instanceRef bdcnt_bctr_3))
+              (portRef B0 (instanceRef e_cmp_3))))
+          (net WCNT5
+            (joined
+              (portRef (member WCNT 4))
+              (portRef A1 (instanceRef g_cmp_2))
+              (portRef Q (instanceRef FF_57))
+              (portRef A1 (instanceRef bdcnt_bctr_2))
+              (portRef B1 (instanceRef e_cmp_2))))
+          (net WCNT4
+            (joined
+              (portRef (member WCNT 5))
+              (portRef A0 (instanceRef g_cmp_2))
+              (portRef Q (instanceRef FF_58))
+              (portRef A0 (instanceRef bdcnt_bctr_2))
+              (portRef B0 (instanceRef e_cmp_2))))
+          (net WCNT3
+            (joined
+              (portRef (member WCNT 6))
+              (portRef A1 (instanceRef g_cmp_1))
+              (portRef Q (instanceRef FF_59))
+              (portRef A1 (instanceRef bdcnt_bctr_1))
+              (portRef B1 (instanceRef e_cmp_1))))
+          (net WCNT2
+            (joined
+              (portRef (member WCNT 7))
+              (portRef A0 (instanceRef g_cmp_1))
+              (portRef Q (instanceRef FF_60))
+              (portRef A0 (instanceRef bdcnt_bctr_1))
+              (portRef B0 (instanceRef e_cmp_1))))
+          (net WCNT1
+            (joined
+              (portRef (member WCNT 8))
+              (portRef A1 (instanceRef g_cmp_0))
+              (portRef Q (instanceRef FF_61))
+              (portRef A1 (instanceRef bdcnt_bctr_0))
+              (portRef B1 (instanceRef e_cmp_0))))
+          (net WCNT0
+            (joined
+              (portRef (member WCNT 9))
+              (portRef A0 (instanceRef g_cmp_0))
+              (portRef Q (instanceRef FF_62))
+              (portRef A0 (instanceRef bdcnt_bctr_0))
+              (portRef B0 (instanceRef e_cmp_0))))
+          (net dataout17
+            (joined
+              (portRef (member Q 0))
+              (portRef DO35 (instanceRef pdp_ram_0_0_0))))
+          (net dataout16
+            (joined
+              (portRef (member Q 1))
+              (portRef DO34 (instanceRef pdp_ram_0_0_0))))
+          (net dataout15
+            (joined
+              (portRef (member Q 2))
+              (portRef DO33 (instanceRef pdp_ram_0_0_0))))
+          (net dataout14
+            (joined
+              (portRef (member Q 3))
+              (portRef DO32 (instanceRef pdp_ram_0_0_0))))
+          (net dataout13
+            (joined
+              (portRef (member Q 4))
+              (portRef DO31 (instanceRef pdp_ram_0_0_0))))
+          (net dataout12
+            (joined
+              (portRef (member Q 5))
+              (portRef DO30 (instanceRef pdp_ram_0_0_0))))
+          (net dataout11
+            (joined
+              (portRef (member Q 6))
+              (portRef DO29 (instanceRef pdp_ram_0_0_0))))
+          (net dataout10
+            (joined
+              (portRef (member Q 7))
+              (portRef DO28 (instanceRef pdp_ram_0_0_0))))
+          (net dataout9
+            (joined
+              (portRef (member Q 8))
+              (portRef DO27 (instanceRef pdp_ram_0_0_0))))
+          (net dataout8
+            (joined
+              (portRef (member Q 9))
+              (portRef DO26 (instanceRef pdp_ram_0_0_0))))
+          (net dataout7
+            (joined
+              (portRef (member Q 10))
+              (portRef DO25 (instanceRef pdp_ram_0_0_0))))
+          (net dataout6
+            (joined
+              (portRef (member Q 11))
+              (portRef DO24 (instanceRef pdp_ram_0_0_0))))
+          (net dataout5
+            (joined
+              (portRef (member Q 12))
+              (portRef DO23 (instanceRef pdp_ram_0_0_0))))
+          (net dataout4
+            (joined
+              (portRef (member Q 13))
+              (portRef DO22 (instanceRef pdp_ram_0_0_0))))
+          (net dataout3
+            (joined
+              (portRef (member Q 14))
+              (portRef DO21 (instanceRef pdp_ram_0_0_0))))
+          (net dataout2
+            (joined
+              (portRef (member Q 15))
+              (portRef DO20 (instanceRef pdp_ram_0_0_0))))
+          (net dataout1
+            (joined
+              (portRef (member Q 16))
+              (portRef DO19 (instanceRef pdp_ram_0_0_0))))
+          (net dataout0
+            (joined
+              (portRef (member Q 17))
+              (portRef DO18 (instanceRef pdp_ram_0_0_0))))
+          (net AmFullThresh8
+            (joined
+              (portRef (member AmFullThresh 0))
+              (portRef B0 (instanceRef af_set_cmp_4))))
+          (net AmFullThresh7
+            (joined
+              (portRef (member AmFullThresh 1))
+              (portRef B1 (instanceRef af_set_cmp_3))))
+          (net AmFullThresh6
+            (joined
+              (portRef (member AmFullThresh 2))
+              (portRef B0 (instanceRef af_set_cmp_3))))
+          (net AmFullThresh5
+            (joined
+              (portRef (member AmFullThresh 3))
+              (portRef B1 (instanceRef af_set_cmp_2))))
+          (net AmFullThresh4
+            (joined
+              (portRef (member AmFullThresh 4))
+              (portRef B0 (instanceRef af_set_cmp_2))))
+          (net AmFullThresh3
+            (joined
+              (portRef (member AmFullThresh 5))
+              (portRef B1 (instanceRef af_set_cmp_1))))
+          (net AmFullThresh2
+            (joined
+              (portRef (member AmFullThresh 6))
+              (portRef B0 (instanceRef af_set_cmp_1))))
+          (net AmFullThresh1
+            (joined
+              (portRef (member AmFullThresh 7))
+              (portRef B1 (instanceRef af_set_cmp_0))))
+          (net AmFullThresh0
+            (joined
+              (portRef (member AmFullThresh 8))
+              (portRef B0 (instanceRef af_set_cmp_0))))
+          (net reset
+            (joined
+              (portRef Reset)
+              (portRef RST (instanceRef pdp_ram_0_0_0))
+              (portRef CD (instanceRef FF_62))
+              (portRef CD (instanceRef FF_61))
+              (portRef CD (instanceRef FF_60))
+              (portRef CD (instanceRef FF_59))
+              (portRef CD (instanceRef FF_58))
+              (portRef CD (instanceRef FF_57))
+              (portRef CD (instanceRef FF_56))
+              (portRef CD (instanceRef FF_55))
+              (portRef CD (instanceRef FF_54))
+              (portRef CD (instanceRef FF_53))
+              (portRef PD (instanceRef FF_52))
+              (portRef CD (instanceRef FF_51))
+              (portRef PD (instanceRef FF_50))
+              (portRef CD (instanceRef FF_49))
+              (portRef CD (instanceRef FF_48))
+              (portRef CD (instanceRef FF_47))
+              (portRef CD (instanceRef FF_46))
+              (portRef CD (instanceRef FF_45))
+              (portRef CD (instanceRef FF_44))
+              (portRef CD (instanceRef FF_43))
+              (portRef CD (instanceRef FF_42))
+              (portRef CD (instanceRef FF_41))
+              (portRef PD (instanceRef FF_40))
+              (portRef CD (instanceRef FF_39))
+              (portRef CD (instanceRef FF_38))
+              (portRef CD (instanceRef FF_37))
+              (portRef CD (instanceRef FF_36))
+              (portRef CD (instanceRef FF_35))
+              (portRef CD (instanceRef FF_34))
+              (portRef CD (instanceRef FF_33))
+              (portRef CD (instanceRef FF_32))
+              (portRef CD (instanceRef FF_31))
+              (portRef CD (instanceRef FF_30))
+              (portRef CD (instanceRef FF_29))
+              (portRef CD (instanceRef FF_28))
+              (portRef CD (instanceRef FF_27))
+              (portRef CD (instanceRef FF_26))
+              (portRef CD (instanceRef FF_25))
+              (portRef CD (instanceRef FF_24))
+              (portRef CD (instanceRef FF_23))
+              (portRef CD (instanceRef FF_22))
+              (portRef CD (instanceRef FF_21))
+              (portRef CD (instanceRef FF_20))
+              (portRef CD (instanceRef FF_19))
+              (portRef CD (instanceRef FF_18))
+              (portRef CD (instanceRef FF_17))
+              (portRef CD (instanceRef FF_16))
+              (portRef CD (instanceRef FF_15))
+              (portRef CD (instanceRef FF_14))
+              (portRef CD (instanceRef FF_13))
+              (portRef CD (instanceRef FF_12))
+              (portRef CD (instanceRef FF_11))
+              (portRef CD (instanceRef FF_10))
+              (portRef CD (instanceRef FF_9))
+              (portRef CD (instanceRef FF_8))
+              (portRef CD (instanceRef FF_7))
+              (portRef CD (instanceRef FF_6))
+              (portRef CD (instanceRef FF_5))
+              (portRef CD (instanceRef FF_4))
+              (portRef CD (instanceRef FF_3))
+              (portRef CD (instanceRef FF_2))
+              (portRef CD (instanceRef FF_1))
+              (portRef CD (instanceRef FF_0))))
+          (net rden
+            (joined
+              (portRef RdEn)
+              (portRef A (instanceRef AND2_t4))))
+          (net wren
+            (joined
+              (portRef WrEn)
+              (portRef A (instanceRef AND2_t5))))
+          (net clk
+            (joined
+              (portRef Clock)
+              (portRef CLKR (instanceRef pdp_ram_0_0_0))
+              (portRef CLKW (instanceRef pdp_ram_0_0_0))
+              (portRef CK (instanceRef FF_62))
+              (portRef CK (instanceRef FF_61))
+              (portRef CK (instanceRef FF_60))
+              (portRef CK (instanceRef FF_59))
+              (portRef CK (instanceRef FF_58))
+              (portRef CK (instanceRef FF_57))
+              (portRef CK (instanceRef FF_56))
+              (portRef CK (instanceRef FF_55))
+              (portRef CK (instanceRef FF_54))
+              (portRef CK (instanceRef FF_53))
+              (portRef CK (instanceRef FF_52))
+              (portRef CK (instanceRef FF_51))
+              (portRef CK (instanceRef FF_50))
+              (portRef CK (instanceRef FF_49))
+              (portRef CK (instanceRef FF_48))
+              (portRef CK (instanceRef FF_47))
+              (portRef CK (instanceRef FF_46))
+              (portRef CK (instanceRef FF_45))
+              (portRef CK (instanceRef FF_44))
+              (portRef CK (instanceRef FF_43))
+              (portRef CK (instanceRef FF_42))
+              (portRef CK (instanceRef FF_41))
+              (portRef CK (instanceRef FF_40))
+              (portRef CK (instanceRef FF_39))
+              (portRef CK (instanceRef FF_38))
+              (portRef CK (instanceRef FF_37))
+              (portRef CK (instanceRef FF_36))
+              (portRef CK (instanceRef FF_35))
+              (portRef CK (instanceRef FF_34))
+              (portRef CK (instanceRef FF_33))
+              (portRef CK (instanceRef FF_32))
+              (portRef CK (instanceRef FF_31))
+              (portRef CK (instanceRef FF_30))
+              (portRef CK (instanceRef FF_29))
+              (portRef CK (instanceRef FF_28))
+              (portRef CK (instanceRef FF_27))
+              (portRef CK (instanceRef FF_26))
+              (portRef CK (instanceRef FF_25))
+              (portRef CK (instanceRef FF_24))
+              (portRef CK (instanceRef FF_23))
+              (portRef CK (instanceRef FF_22))
+              (portRef CK (instanceRef FF_21))
+              (portRef CK (instanceRef FF_20))
+              (portRef CK (instanceRef FF_19))
+              (portRef CK (instanceRef FF_18))
+              (portRef CK (instanceRef FF_17))
+              (portRef CK (instanceRef FF_16))
+              (portRef CK (instanceRef FF_15))
+              (portRef CK (instanceRef FF_14))
+              (portRef CK (instanceRef FF_13))
+              (portRef CK (instanceRef FF_12))
+              (portRef CK (instanceRef FF_11))
+              (portRef CK (instanceRef FF_10))
+              (portRef CK (instanceRef FF_9))
+              (portRef CK (instanceRef FF_8))
+              (portRef CK (instanceRef FF_7))
+              (portRef CK (instanceRef FF_6))
+              (portRef CK (instanceRef FF_5))
+              (portRef CK (instanceRef FF_4))
+              (portRef CK (instanceRef FF_3))
+              (portRef CK (instanceRef FF_2))
+              (portRef CK (instanceRef FF_1))
+              (portRef CK (instanceRef FF_0))))
+          (net datain17
+            (joined
+              (portRef (member Data 0))
+              (portRef DI17 (instanceRef pdp_ram_0_0_0))))
+          (net datain16
+            (joined
+              (portRef (member Data 1))
+              (portRef DI16 (instanceRef pdp_ram_0_0_0))))
+          (net datain15
+            (joined
+              (portRef (member Data 2))
+              (portRef DI15 (instanceRef pdp_ram_0_0_0))))
+          (net datain14
+            (joined
+              (portRef (member Data 3))
+              (portRef DI14 (instanceRef pdp_ram_0_0_0))))
+          (net datain13
+            (joined
+              (portRef (member Data 4))
+              (portRef DI13 (instanceRef pdp_ram_0_0_0))))
+          (net datain12
+            (joined
+              (portRef (member Data 5))
+              (portRef DI12 (instanceRef pdp_ram_0_0_0))))
+          (net datain11
+            (joined
+              (portRef (member Data 6))
+              (portRef DI11 (instanceRef pdp_ram_0_0_0))))
+          (net datain10
+            (joined
+              (portRef (member Data 7))
+              (portRef DI10 (instanceRef pdp_ram_0_0_0))))
+          (net datain9
+            (joined
+              (portRef (member Data 8))
+              (portRef DI9 (instanceRef pdp_ram_0_0_0))))
+          (net datain8
+            (joined
+              (portRef (member Data 9))
+              (portRef DI8 (instanceRef pdp_ram_0_0_0))))
+          (net datain7
+            (joined
+              (portRef (member Data 10))
+              (portRef DI7 (instanceRef pdp_ram_0_0_0))))
+          (net datain6
+            (joined
+              (portRef (member Data 11))
+              (portRef DI6 (instanceRef pdp_ram_0_0_0))))
+          (net datain5
+            (joined
+              (portRef (member Data 12))
+              (portRef DI5 (instanceRef pdp_ram_0_0_0))))
+          (net datain4
+            (joined
+              (portRef (member Data 13))
+              (portRef DI4 (instanceRef pdp_ram_0_0_0))))
+          (net datain3
+            (joined
+              (portRef (member Data 14))
+              (portRef DI3 (instanceRef pdp_ram_0_0_0))))
+          (net datain2
+            (joined
+              (portRef (member Data 15))
+              (portRef DI2 (instanceRef pdp_ram_0_0_0))))
+          (net datain1
+            (joined
+              (portRef (member Data 16))
+              (portRef DI1 (instanceRef pdp_ram_0_0_0))))
+          (net datain0
+            (joined
+              (portRef (member Data 17))
+              (portRef DI0 (instanceRef pdp_ram_0_0_0))))))))
+  (design fifo_18x512_oreg
+    (cellRef fifo_18x512_oreg
+      (libraryRef ORCLIB)))
+)

diff --git a/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.fdc b/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.fdc
new file mode 100644 (file)
index 0000000..6fbcac9
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.fdc
@@ -0,0 +1,2 @@
+###==== Start Configuration
+

diff --git a/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.lpc b/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.lpc
new file mode 100644 (file)
index 0000000..a92d8d4
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.lpc
@@ -0,0 +1,50 @@
+[Device]
+Family=ecp5um
+PartType=LFE5UM-85F
+PartName=LFE5UM-85F-8MG285C
+SpeedGrade=8
+Package=CSFBGA285
+OperatingCondition=COM
+Status=C
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO
+CoreRevision=5.0
+ModuleName=fifo_18x512_oreg
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=03/18/2015
+Time=14:43:13
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=512
+Width=18
+regout=1
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=1
+PfMode=Dynamic - Single Threshold
+PfAssert=508
+PfDeassert=506
+Reset=Async
+Reset1=Sync
+RDataCount=1
+EnECC=0
+EnFWFT=0
+
+[Command]
+cmd_line= -w -n fifo_18x512_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 512 -width 18 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill

diff --git a/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.ngd b/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.ngd
new file mode 100644 (file)
index 0000000..ecd1e9a
Binary files /dev/null and b/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.ngd differ

diff --git a/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.ngo b/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.ngo
new file mode 100644 (file)
index 0000000..25f8b97
Binary files /dev/null and b/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.ngo differ

diff --git a/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.vhd b/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.vhd
new file mode 100644 (file)
index 0000000..0e3a077
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.vhd
@@ -0,0 +1,949 @@
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80
+-- Module  Version: 5.0
+--/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_18x512_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 512 -width 18 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.fdc 
+
+-- Wed Mar 18 14:43:18 2015
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity fifo_18x512_oreg is
+    port (
+        Data: in  std_logic_vector(17 downto 0); 
+        Clock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        AmFullThresh: in  std_logic_vector(8 downto 0); 
+        Q: out  std_logic_vector(17 downto 0); 
+        WCNT: out  std_logic_vector(9 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic; 
+        AlmostFull: out  std_logic);
+end fifo_18x512_oreg;
+
+architecture Structure of fifo_18x512_oreg is
+
+    -- internal signal declarations
+    signal invout_2: std_logic;
+    signal invout_1: std_logic;
+    signal rden_i_inv: std_logic;
+    signal invout_0: std_logic;
+    signal r_nw: std_logic;
+    signal fcnt_en: std_logic;
+    signal empty_i: std_logic;
+    signal empty_d: std_logic;
+    signal full_i: std_logic;
+    signal full_d: std_logic;
+    signal wptr_0: std_logic;
+    signal wptr_1: std_logic;
+    signal wptr_2: std_logic;
+    signal wptr_3: std_logic;
+    signal wptr_4: std_logic;
+    signal wptr_5: std_logic;
+    signal wptr_6: std_logic;
+    signal wptr_7: std_logic;
+    signal wptr_8: std_logic;
+    signal wptr_9: std_logic;
+    signal rptr_9: std_logic;
+    signal ifcount_0: std_logic;
+    signal ifcount_1: std_logic;
+    signal bdcnt_bctr_ci: std_logic;
+    signal ifcount_2: std_logic;
+    signal ifcount_3: std_logic;
+    signal co0: std_logic;
+    signal ifcount_4: std_logic;
+    signal ifcount_5: std_logic;
+    signal co1: std_logic;
+    signal ifcount_6: std_logic;
+    signal ifcount_7: std_logic;
+    signal co2: std_logic;
+    signal ifcount_8: std_logic;
+    signal ifcount_9: std_logic;
+    signal co4: std_logic;
+    signal co3: std_logic;
+    signal cmp_ci: std_logic;
+    signal rden_i: std_logic;
+    signal co0_1: std_logic;
+    signal co1_1: std_logic;
+    signal co2_1: std_logic;
+    signal co3_1: std_logic;
+    signal cmp_le_1: std_logic;
+    signal cmp_le_1_c: std_logic;
+    signal cmp_ci_1: std_logic;
+    signal fcount_0: std_logic;
+    signal fcount_1: std_logic;
+    signal co0_2: std_logic;
+    signal fcount_2: std_logic;
+    signal fcount_3: std_logic;
+    signal co1_2: std_logic;
+    signal fcount_4: std_logic;
+    signal fcount_5: std_logic;
+    signal co2_2: std_logic;
+    signal fcount_6: std_logic;
+    signal fcount_7: std_logic;
+    signal co3_2: std_logic;
+    signal wren_i_inv: std_logic;
+    signal fcount_8: std_logic;
+    signal fcount_9: std_logic;
+    signal cmp_ge_d1: std_logic;
+    signal cmp_ge_d1_c: std_logic;
+    signal iwcount_0: std_logic;
+    signal iwcount_1: std_logic;
+    signal w_ctr_ci: std_logic;
+    signal iwcount_2: std_logic;
+    signal iwcount_3: std_logic;
+    signal co0_3: std_logic;
+    signal iwcount_4: std_logic;
+    signal iwcount_5: std_logic;
+    signal co1_3: std_logic;
+    signal iwcount_6: std_logic;
+    signal iwcount_7: std_logic;
+    signal co2_3: std_logic;
+    signal iwcount_8: std_logic;
+    signal iwcount_9: std_logic;
+    signal co4_1: std_logic;
+    signal co3_3: std_logic;
+    signal wcount_9: std_logic;
+    signal ircount_0: std_logic;
+    signal ircount_1: std_logic;
+    signal r_ctr_ci: std_logic;
+    signal rcount_0: std_logic;
+    signal rcount_1: std_logic;
+    signal ircount_2: std_logic;
+    signal ircount_3: std_logic;
+    signal co0_4: std_logic;
+    signal rcount_2: std_logic;
+    signal rcount_3: std_logic;
+    signal ircount_4: std_logic;
+    signal ircount_5: std_logic;
+    signal co1_4: std_logic;
+    signal rcount_4: std_logic;
+    signal rcount_5: std_logic;
+    signal ircount_6: std_logic;
+    signal ircount_7: std_logic;
+    signal co2_4: std_logic;
+    signal rcount_6: std_logic;
+    signal rcount_7: std_logic;
+    signal ircount_8: std_logic;
+    signal ircount_9: std_logic;
+    signal co4_2: std_logic;
+    signal co3_4: std_logic;
+    signal rcount_8: std_logic;
+    signal rcount_9: std_logic;
+    signal wcnt_sub_0: std_logic;
+    signal rptr_0: std_logic;
+    signal cnt_con_inv: std_logic;
+    signal wcount_0: std_logic;
+    signal cnt_con: std_logic;
+    signal precin: std_logic;
+    signal wcnt_sub_1: std_logic;
+    signal wcnt_sub_2: std_logic;
+    signal rptr_2: std_logic;
+    signal rptr_1: std_logic;
+    signal wcount_2: std_logic;
+    signal wcount_1: std_logic;
+    signal co0_5: std_logic;
+    signal wcnt_sub_3: std_logic;
+    signal wcnt_sub_4: std_logic;
+    signal rptr_4: std_logic;
+    signal rptr_3: std_logic;
+    signal wcount_4: std_logic;
+    signal wcount_3: std_logic;
+    signal co1_5: std_logic;
+    signal wcnt_sub_5: std_logic;
+    signal wcnt_sub_6: std_logic;
+    signal rptr_6: std_logic;
+    signal rptr_5: std_logic;
+    signal wcount_6: std_logic;
+    signal wcount_5: std_logic;
+    signal co2_5: std_logic;
+    signal wcnt_sub_7: std_logic;
+    signal wcnt_sub_8: std_logic;
+    signal rptr_8: std_logic;
+    signal rptr_7: std_logic;
+    signal wcount_8: std_logic;
+    signal wcount_7: std_logic;
+    signal co3_5: std_logic;
+    signal wcnt_sub_9: std_logic;
+    signal wcnt_sub_msb: std_logic;
+    signal co4_3: std_logic;
+    signal wren_i: std_logic;
+    signal cmp_ci_2: std_logic;
+    signal wcnt_reg_0: std_logic;
+    signal wcnt_reg_1: std_logic;
+    signal co0_6: std_logic;
+    signal wcnt_reg_2: std_logic;
+    signal wcnt_reg_3: std_logic;
+    signal co1_6: std_logic;
+    signal wcnt_reg_4: std_logic;
+    signal wcnt_reg_5: std_logic;
+    signal co2_6: std_logic;
+    signal wcnt_reg_6: std_logic;
+    signal wcnt_reg_7: std_logic;
+    signal co3_6: std_logic;
+    signal wcnt_reg_8: std_logic;
+    signal wcnt_reg_9: std_logic;
+    signal af_set: std_logic;
+    signal scuba_vhi: std_logic;
+    signal scuba_vlo: std_logic;
+    signal af_set_c: std_logic;
+
+    attribute MEM_LPC_FILE : string; 
+    attribute MEM_INIT_FILE : string; 
+    attribute GSR : string; 
+    attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_18x512_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
+    attribute GSR of FF_62 : label is "ENABLED";
+    attribute GSR of FF_61 : label is "ENABLED";
+    attribute GSR of FF_60 : label is "ENABLED";
+    attribute GSR of FF_59 : label is "ENABLED";
+    attribute GSR of FF_58 : label is "ENABLED";
+    attribute GSR of FF_57 : label is "ENABLED";
+    attribute GSR of FF_56 : label is "ENABLED";
+    attribute GSR of FF_55 : label is "ENABLED";
+    attribute GSR of FF_54 : label is "ENABLED";
+    attribute GSR of FF_53 : label is "ENABLED";
+    attribute GSR of FF_52 : label is "ENABLED";
+    attribute GSR of FF_51 : label is "ENABLED";
+    attribute GSR of FF_50 : label is "ENABLED";
+    attribute GSR of FF_49 : label is "ENABLED";
+    attribute GSR of FF_48 : label is "ENABLED";
+    attribute GSR of FF_47 : label is "ENABLED";
+    attribute GSR of FF_46 : label is "ENABLED";
+    attribute GSR of FF_45 : label is "ENABLED";
+    attribute GSR of FF_44 : label is "ENABLED";
+    attribute GSR of FF_43 : label is "ENABLED";
+    attribute GSR of FF_42 : label is "ENABLED";
+    attribute GSR of FF_41 : label is "ENABLED";
+    attribute GSR of FF_40 : label is "ENABLED";
+    attribute GSR of FF_39 : label is "ENABLED";
+    attribute GSR of FF_38 : label is "ENABLED";
+    attribute GSR of FF_37 : label is "ENABLED";
+    attribute GSR of FF_36 : label is "ENABLED";
+    attribute GSR of FF_35 : label is "ENABLED";
+    attribute GSR of FF_34 : label is "ENABLED";
+    attribute GSR of FF_33 : label is "ENABLED";
+    attribute GSR of FF_32 : label is "ENABLED";
+    attribute GSR of FF_31 : label is "ENABLED";
+    attribute GSR of FF_30 : label is "ENABLED";
+    attribute GSR of FF_29 : label is "ENABLED";
+    attribute GSR of FF_28 : label is "ENABLED";
+    attribute GSR of FF_27 : label is "ENABLED";
+    attribute GSR of FF_26 : label is "ENABLED";
+    attribute GSR of FF_25 : label is "ENABLED";
+    attribute GSR of FF_24 : label is "ENABLED";
+    attribute GSR of FF_23 : label is "ENABLED";
+    attribute GSR of FF_22 : label is "ENABLED";
+    attribute GSR of FF_21 : label is "ENABLED";
+    attribute GSR of FF_20 : label is "ENABLED";
+    attribute GSR of FF_19 : label is "ENABLED";
+    attribute GSR of FF_18 : label is "ENABLED";
+    attribute GSR of FF_17 : label is "ENABLED";
+    attribute GSR of FF_16 : label is "ENABLED";
+    attribute GSR of FF_15 : label is "ENABLED";
+    attribute GSR of FF_14 : label is "ENABLED";
+    attribute GSR of FF_13 : label is "ENABLED";
+    attribute GSR of FF_12 : label is "ENABLED";
+    attribute GSR of FF_11 : label is "ENABLED";
+    attribute GSR of FF_10 : label is "ENABLED";
+    attribute GSR of FF_9 : label is "ENABLED";
+    attribute GSR of FF_8 : label is "ENABLED";
+    attribute GSR of FF_7 : label is "ENABLED";
+    attribute GSR of FF_6 : label is "ENABLED";
+    attribute GSR of FF_5 : label is "ENABLED";
+    attribute GSR of FF_4 : label is "ENABLED";
+    attribute GSR of FF_3 : label is "ENABLED";
+    attribute GSR of FF_2 : label is "ENABLED";
+    attribute GSR of FF_1 : label is "ENABLED";
+    attribute GSR of FF_0 : label is "ENABLED";
+    attribute syn_keep : boolean;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    AND2_t5: AND2
+        port map (A=>WrEn, B=>invout_2, Z=>wren_i);
+
+    INV_5: INV
+        port map (A=>full_i, Z=>invout_2);
+
+    AND2_t4: AND2
+        port map (A=>RdEn, B=>invout_1, Z=>rden_i);
+
+    INV_4: INV
+        port map (A=>empty_i, Z=>invout_1);
+
+    AND2_t3: AND2
+        port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
+
+    XOR2_t2: XOR2
+        port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
+
+    INV_3: INV
+        port map (A=>rden_i, Z=>rden_i_inv);
+
+    INV_2: INV
+        port map (A=>wren_i, Z=>wren_i_inv);
+
+    LUT4_1: ROM16X1A
+        generic map (initval=> X"3232")
+        port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, 
+            AD0=>empty_i, DO0=>empty_d);
+
+    LUT4_0: ROM16X1A
+        generic map (initval=> X"3232")
+        port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, 
+            AD0=>full_i, DO0=>full_d);
+
+    AND2_t1: AND2
+        port map (A=>rden_i, B=>invout_0, Z=>r_nw);
+
+    INV_1: INV
+        port map (A=>wren_i, Z=>invout_0);
+
+    XOR2_t0: XOR2
+        port map (A=>wcount_9, B=>rptr_9, Z=>wcnt_sub_msb);
+
+    INV_0: INV
+        port map (A=>cnt_con, Z=>cnt_con_inv);
+
+    pdp_ram_0_0_0: PDPW16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "ENABLED", 
+        RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=>  36, 
+        DATA_WIDTH_W=>  36)
+        port map (DI35=>scuba_vlo, DI34=>scuba_vlo, DI33=>scuba_vlo, 
+            DI32=>scuba_vlo, DI31=>scuba_vlo, DI30=>scuba_vlo, 
+            DI29=>scuba_vlo, DI28=>scuba_vlo, DI27=>scuba_vlo, 
+            DI26=>scuba_vlo, DI25=>scuba_vlo, DI24=>scuba_vlo, 
+            DI23=>scuba_vlo, DI22=>scuba_vlo, DI21=>scuba_vlo, 
+            DI20=>scuba_vlo, DI19=>scuba_vlo, DI18=>scuba_vlo, 
+            DI17=>Data(17), DI16=>Data(16), DI15=>Data(15), 
+            DI14=>Data(14), DI13=>Data(13), DI12=>Data(12), 
+            DI11=>Data(11), DI10=>Data(10), DI9=>Data(9), DI8=>Data(8), 
+            DI7=>Data(7), DI6=>Data(6), DI5=>Data(5), DI4=>Data(4), 
+            DI3=>Data(3), DI2=>Data(2), DI1=>Data(1), DI0=>Data(0), 
+            ADW8=>wptr_8, ADW7=>wptr_7, ADW6=>wptr_6, ADW5=>wptr_5, 
+            ADW4=>wptr_4, ADW3=>wptr_3, ADW2=>wptr_2, ADW1=>wptr_1, 
+            ADW0=>wptr_0, BE3=>scuba_vhi, BE2=>scuba_vhi, BE1=>scuba_vhi, 
+            BE0=>scuba_vhi, CEW=>wren_i, CLKW=>Clock, CSW2=>scuba_vlo, 
+            CSW1=>scuba_vlo, CSW0=>scuba_vhi, ADR13=>rptr_8, 
+            ADR12=>rptr_7, ADR11=>rptr_6, ADR10=>rptr_5, ADR9=>rptr_4, 
+            ADR8=>rptr_3, ADR7=>rptr_2, ADR6=>rptr_1, ADR5=>rptr_0, 
+            ADR4=>scuba_vlo, ADR3=>scuba_vlo, ADR2=>scuba_vlo, 
+            ADR1=>scuba_vlo, ADR0=>scuba_vlo, CER=>scuba_vhi, 
+            OCER=>scuba_vhi, CLKR=>Clock, CSR2=>scuba_vlo, 
+            CSR1=>scuba_vlo, CSR0=>rden_i, RST=>Reset, DO35=>Q(17), 
+            DO34=>Q(16), DO33=>Q(15), DO32=>Q(14), DO31=>Q(13), 
+            DO30=>Q(12), DO29=>Q(11), DO28=>Q(10), DO27=>Q(9), 
+            DO26=>Q(8), DO25=>Q(7), DO24=>Q(6), DO23=>Q(5), DO22=>Q(4), 
+            DO21=>Q(3), DO20=>Q(2), DO19=>Q(1), DO18=>Q(0), DO17=>open, 
+            DO16=>open, DO15=>open, DO14=>open, DO13=>open, DO12=>open, 
+            DO11=>open, DO10=>open, DO9=>open, DO8=>open, DO7=>open, 
+            DO6=>open, DO5=>open, DO4=>open, DO3=>open, DO2=>open, 
+            DO1=>open, DO0=>open);
+
+    FF_62: FD1P3DX
+        port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_0);
+
+    FF_61: FD1P3DX
+        port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_1);
+
+    FF_60: FD1P3DX
+        port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_2);
+
+    FF_59: FD1P3DX
+        port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_3);
+
+    FF_58: FD1P3DX
+        port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_4);
+
+    FF_57: FD1P3DX
+        port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_5);
+
+    FF_56: FD1P3DX
+        port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_6);
+
+    FF_55: FD1P3DX
+        port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_7);
+
+    FF_54: FD1P3DX
+        port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_8);
+
+    FF_53: FD1P3DX
+        port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_9);
+
+    FF_52: FD1S3BX
+        port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
+
+    FF_51: FD1S3DX
+        port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
+
+    FF_50: FD1P3BX
+        port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset, 
+            Q=>wcount_0);
+
+    FF_49: FD1P3DX
+        port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_1);
+
+    FF_48: FD1P3DX
+        port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_2);
+
+    FF_47: FD1P3DX
+        port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_3);
+
+    FF_46: FD1P3DX
+        port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_4);
+
+    FF_45: FD1P3DX
+        port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_5);
+
+    FF_44: FD1P3DX
+        port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_6);
+
+    FF_43: FD1P3DX
+        port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_7);
+
+    FF_42: FD1P3DX
+        port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_8);
+
+    FF_41: FD1P3DX
+        port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_9);
+
+    FF_40: FD1P3BX
+        port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset, 
+            Q=>rcount_0);
+
+    FF_39: FD1P3DX
+        port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_1);
+
+    FF_38: FD1P3DX
+        port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_2);
+
+    FF_37: FD1P3DX
+        port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_3);
+
+    FF_36: FD1P3DX
+        port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_4);
+
+    FF_35: FD1P3DX
+        port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_5);
+
+    FF_34: FD1P3DX
+        port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_6);
+
+    FF_33: FD1P3DX
+        port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_7);
+
+    FF_32: FD1P3DX
+        port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_8);
+
+    FF_31: FD1P3DX
+        port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_9);
+
+    FF_30: FD1P3DX
+        port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_0);
+
+    FF_29: FD1P3DX
+        port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_1);
+
+    FF_28: FD1P3DX
+        port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_2);
+
+    FF_27: FD1P3DX
+        port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_3);
+
+    FF_26: FD1P3DX
+        port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_4);
+
+    FF_25: FD1P3DX
+        port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_5);
+
+    FF_24: FD1P3DX
+        port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_6);
+
+    FF_23: FD1P3DX
+        port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_7);
+
+    FF_22: FD1P3DX
+        port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_8);
+
+    FF_21: FD1P3DX
+        port map (D=>wcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_9);
+
+    FF_20: FD1P3DX
+        port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_0);
+
+    FF_19: FD1P3DX
+        port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_1);
+
+    FF_18: FD1P3DX
+        port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_2);
+
+    FF_17: FD1P3DX
+        port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_3);
+
+    FF_16: FD1P3DX
+        port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_4);
+
+    FF_15: FD1P3DX
+        port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_5);
+
+    FF_14: FD1P3DX
+        port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_6);
+
+    FF_13: FD1P3DX
+        port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_7);
+
+    FF_12: FD1P3DX
+        port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_8);
+
+    FF_11: FD1P3DX
+        port map (D=>rcount_9, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_9);
+
+    FF_10: FD1S3DX
+        port map (D=>wcnt_sub_0, CK=>Clock, CD=>Reset, Q=>wcnt_reg_0);
+
+    FF_9: FD1S3DX
+        port map (D=>wcnt_sub_1, CK=>Clock, CD=>Reset, Q=>wcnt_reg_1);
+
+    FF_8: FD1S3DX
+        port map (D=>wcnt_sub_2, CK=>Clock, CD=>Reset, Q=>wcnt_reg_2);
+
+    FF_7: FD1S3DX
+        port map (D=>wcnt_sub_3, CK=>Clock, CD=>Reset, Q=>wcnt_reg_3);
+
+    FF_6: FD1S3DX
+        port map (D=>wcnt_sub_4, CK=>Clock, CD=>Reset, Q=>wcnt_reg_4);
+
+    FF_5: FD1S3DX
+        port map (D=>wcnt_sub_5, CK=>Clock, CD=>Reset, Q=>wcnt_reg_5);
+
+    FF_4: FD1S3DX
+        port map (D=>wcnt_sub_6, CK=>Clock, CD=>Reset, Q=>wcnt_reg_6);
+
+    FF_3: FD1S3DX
+        port map (D=>wcnt_sub_7, CK=>Clock, CD=>Reset, Q=>wcnt_reg_7);
+
+    FF_2: FD1S3DX
+        port map (D=>wcnt_sub_8, CK=>Clock, CD=>Reset, Q=>wcnt_reg_8);
+
+    FF_1: FD1S3DX
+        port map (D=>wcnt_sub_9, CK=>Clock, CD=>Reset, Q=>wcnt_reg_9);
+
+    FF_0: FD1S3DX
+        port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull);
+
+    bdcnt_bctr_cia: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>'X', S0=>open, S1=>open, COUT=>bdcnt_bctr_ci);
+
+    bdcnt_bctr_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_0, A1=>fcount_1, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>bdcnt_bctr_ci, S0=>ifcount_0, S1=>ifcount_1, COUT=>co0);
+
+    bdcnt_bctr_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co0, S0=>ifcount_2, S1=>ifcount_3, COUT=>co1);
+
+    bdcnt_bctr_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_4, A1=>fcount_5, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co1, S0=>ifcount_4, S1=>ifcount_5, COUT=>co2);
+
+    bdcnt_bctr_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_6, A1=>fcount_7, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co2, S0=>ifcount_6, S1=>ifcount_7, COUT=>co3);
+
+    bdcnt_bctr_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_8, A1=>fcount_9, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co3, S0=>ifcount_8, S1=>ifcount_9, COUT=>co4);
+
+    e_cmp_ci_a: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci);
+
+    e_cmp_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>rden_i, A1=>scuba_vlo, B0=>fcount_0, B1=>fcount_1, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>cmp_ci, S0=>open, S1=>open, COUT=>co0_1);
+
+    e_cmp_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_2, 
+            B1=>fcount_3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co0_1, S0=>open, S1=>open, COUT=>co1_1);
+
+    e_cmp_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_4, 
+            B1=>fcount_5, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co1_1, S0=>open, S1=>open, COUT=>co2_1);
+
+    e_cmp_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_6, 
+            B1=>fcount_7, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co2_1, S0=>open, S1=>open, COUT=>co3_1);
+
+    e_cmp_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_8, 
+            B1=>fcount_9, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co3_1, S0=>open, S1=>open, 
+            COUT=>cmp_le_1_c);
+
+    a0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>cmp_le_1_c, S0=>cmp_le_1, S1=>open, 
+            COUT=>open);
+
+    g_cmp_ci_a: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_1);
+
+    g_cmp_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>cmp_ci_1, S0=>open, S1=>open, COUT=>co0_2);
+
+    g_cmp_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co0_2, S0=>open, S1=>open, COUT=>co1_2);
+
+    g_cmp_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co1_2, S0=>open, S1=>open, COUT=>co2_2);
+
+    g_cmp_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co2_2, S0=>open, S1=>open, COUT=>co3_2);
+
+    g_cmp_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i_inv, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co3_2, S0=>open, S1=>open, COUT=>cmp_ge_d1_c);
+
+    a1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>cmp_ge_d1_c, S0=>cmp_ge_d1, S1=>open, 
+            COUT=>open);
+
+    w_ctr_cia: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>w_ctr_ci);
+
+    w_ctr_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>w_ctr_ci, S0=>iwcount_0, S1=>iwcount_1, 
+            COUT=>co0_3);
+
+    w_ctr_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_2, A1=>wcount_3, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co0_3, S0=>iwcount_2, S1=>iwcount_3, 
+            COUT=>co1_3);
+
+    w_ctr_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_4, A1=>wcount_5, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co1_3, S0=>iwcount_4, S1=>iwcount_5, 
+            COUT=>co2_3);
+
+    w_ctr_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_6, A1=>wcount_7, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co2_3, S0=>iwcount_6, S1=>iwcount_7, 
+            COUT=>co3_3);
+
+    w_ctr_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_8, A1=>wcount_9, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co3_3, S0=>iwcount_8, S1=>iwcount_9, 
+            COUT=>co4_1);
+
+    r_ctr_cia: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>r_ctr_ci);
+
+    r_ctr_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>r_ctr_ci, S0=>ircount_0, S1=>ircount_1, 
+            COUT=>co0_4);
+
+    r_ctr_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_2, A1=>rcount_3, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co0_4, S0=>ircount_2, S1=>ircount_3, 
+            COUT=>co1_4);
+
+    r_ctr_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_4, A1=>rcount_5, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co1_4, S0=>ircount_4, S1=>ircount_5, 
+            COUT=>co2_4);
+
+    r_ctr_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_6, A1=>rcount_7, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co2_4, S0=>ircount_6, S1=>ircount_7, 
+            COUT=>co3_4);
+
+    r_ctr_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_8, A1=>rcount_9, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co3_4, S0=>ircount_8, S1=>ircount_9, 
+            COUT=>co4_2);
+
+    precin_inst218: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"0000", 
+        INIT0=> X"0000")
+        port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>precin);
+
+    wcnt_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>cnt_con, A1=>wcount_0, B0=>cnt_con_inv, B1=>rptr_0, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>precin, S0=>open, S1=>wcnt_sub_0, COUT=>co0_5);
+
+    wcnt_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_1, A1=>wcount_2, B0=>rptr_1, B1=>rptr_2, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co0_5, S0=>wcnt_sub_1, S1=>wcnt_sub_2, COUT=>co1_5);
+
+    wcnt_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_3, A1=>wcount_4, B0=>rptr_3, B1=>rptr_4, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co1_5, S0=>wcnt_sub_3, S1=>wcnt_sub_4, COUT=>co2_5);
+
+    wcnt_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_5, A1=>wcount_6, B0=>rptr_5, B1=>rptr_6, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co2_5, S0=>wcnt_sub_5, S1=>wcnt_sub_6, COUT=>co3_5);
+
+    wcnt_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_7, A1=>wcount_8, B0=>rptr_7, B1=>rptr_8, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co3_5, S0=>wcnt_sub_7, S1=>wcnt_sub_8, COUT=>co4_3);
+
+    wcnt_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co4_3, S0=>wcnt_sub_9, S1=>open, 
+            COUT=>open);
+
+    af_set_cmp_ci_a: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_2);
+
+    af_set_cmp_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0), 
+            B1=>AmFullThresh(1), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>cmp_ci_2, S0=>open, 
+            S1=>open, COUT=>co0_6);
+
+    af_set_cmp_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2), 
+            B1=>AmFullThresh(3), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co0_6, S0=>open, S1=>open, 
+            COUT=>co1_6);
+
+    af_set_cmp_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4), 
+            B1=>AmFullThresh(5), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co1_6, S0=>open, S1=>open, 
+            COUT=>co2_6);
+
+    af_set_cmp_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6), 
+            B1=>AmFullThresh(7), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co2_6, S0=>open, S1=>open, 
+            COUT=>co3_6);
+
+    af_set_cmp_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8), 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co3_6, S0=>open, S1=>open, 
+            COUT=>af_set_c);
+
+    scuba_vhi_inst: VHI
+        port map (Z=>scuba_vhi);
+
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    a2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>af_set_c, S0=>af_set, S1=>open, 
+            COUT=>open);
+
+    WCNT(0) <= fcount_0;
+    WCNT(1) <= fcount_1;
+    WCNT(2) <= fcount_2;
+    WCNT(3) <= fcount_3;
+    WCNT(4) <= fcount_4;
+    WCNT(5) <= fcount_5;
+    WCNT(6) <= fcount_6;
+    WCNT(7) <= fcount_7;
+    WCNT(8) <= fcount_8;
+    WCNT(9) <= fcount_9;
+    Empty <= empty_i;
+    Full <= full_i;
+end Structure;

diff --git a/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg_ngd.asd b/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg_ngd.asd
new file mode 100644 (file)
index 0000000..c265c78
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg_ngd.asd
@@ -0,0 +1 @@
+[ActiveSupport NGD]

diff --git a/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.cst b/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.cst
new file mode 100644 (file)
index 0000000..0fafcfe
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.cst
@@ -0,0 +1,3 @@
+Date=03/18/2015
+Time=14:42:06
+

diff --git a/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.edn b/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.edn
new file mode 100644 (file)
index 0000000..f9adae0
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.edn
@@ -0,0 +1,8720 @@
+(edif fifo_36x16k_oreg
+  (edifVersion 2 0 0)
+  (edifLevel 0)
+  (keywordMap (keywordLevel 0))
+  (status
+    (written
+      (timestamp 2015 3 18 14 42 8)
+      (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80"))))
+      (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x16k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 16384 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.fdc ")
+  (library ORCLIB
+    (edifLevel 0)
+    (technology
+      (numberDefinition))
+    (cell CCU2C
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A0
+            (direction INPUT))
+          (port A1
+            (direction INPUT))
+          (port B0
+            (direction INPUT))
+          (port B1
+            (direction INPUT))
+          (port C0
+            (direction INPUT))
+          (port C1
+            (direction INPUT))
+          (port D0
+            (direction INPUT))
+          (port D1
+            (direction INPUT))
+          (port CIN
+            (direction INPUT))
+          (port S0
+            (direction OUTPUT))
+          (port S1
+            (direction OUTPUT))
+          (port COUT
+            (direction OUTPUT)))))
+    (cell AND2
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A
+            (direction INPUT))
+          (port B
+            (direction INPUT))
+          (port Z
+            (direction OUTPUT)))))
+    (cell FD1P3BX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port SP
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port PD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell FD1P3DX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port SP
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port CD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell FD1S3BX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port PD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell FD1S3DX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port CD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell INV
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A
+            (direction INPUT))
+          (port Z
+            (direction OUTPUT)))))
+    (cell MUX81
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D0
+            (direction INPUT))
+          (port D1
+            (direction INPUT))
+          (port D2
+            (direction INPUT))
+          (port D3
+            (direction INPUT))
+          (port D4
+            (direction INPUT))
+          (port D5
+            (direction INPUT))
+          (port D6
+            (direction INPUT))
+          (port D7
+            (direction INPUT))
+          (port SD1
+            (direction INPUT))
+          (port SD2
+            (direction INPUT))
+          (port SD3
+            (direction INPUT))
+          (port Z
+            (direction OUTPUT)))))
+    (cell ROM16X1A
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port AD3
+            (direction INPUT))
+          (port AD2
+            (direction INPUT))
+          (port AD1
+            (direction INPUT))
+          (port AD0
+            (direction INPUT))
+          (port DO0
+            (direction OUTPUT)))))
+    (cell VHI
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port Z
+            (direction OUTPUT)))))
+    (cell VLO
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port Z
+            (direction OUTPUT)))))
+    (cell XOR2
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A
+            (direction INPUT))
+          (port B
+            (direction INPUT))
+          (port Z
+            (direction OUTPUT)))))
+    (cell DP16KD
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port DIA17
+            (direction INPUT))
+          (port DIA16
+            (direction INPUT))
+          (port DIA15
+            (direction INPUT))
+          (port DIA14
+            (direction INPUT))
+          (port DIA13
+            (direction INPUT))
+          (port DIA12
+            (direction INPUT))
+          (port DIA11
+            (direction INPUT))
+          (port DIA10
+            (direction INPUT))
+          (port DIA9
+            (direction INPUT))
+          (port DIA8
+            (direction INPUT))
+          (port DIA7
+            (direction INPUT))
+          (port DIA6
+            (direction INPUT))
+          (port DIA5
+            (direction INPUT))
+          (port DIA4
+            (direction INPUT))
+          (port DIA3
+            (direction INPUT))
+          (port DIA2
+            (direction INPUT))
+          (port DIA1
+            (direction INPUT))
+          (port DIA0
+            (direction INPUT))
+          (port ADA13
+            (direction INPUT))
+          (port ADA12
+            (direction INPUT))
+          (port ADA11
+            (direction INPUT))
+          (port ADA10
+            (direction INPUT))
+          (port ADA9
+            (direction INPUT))
+          (port ADA8
+            (direction INPUT))
+          (port ADA7
+            (direction INPUT))
+          (port ADA6
+            (direction INPUT))
+          (port ADA5
+            (direction INPUT))
+          (port ADA4
+            (direction INPUT))
+          (port ADA3
+            (direction INPUT))
+          (port ADA2
+            (direction INPUT))
+          (port ADA1
+            (direction INPUT))
+          (port ADA0
+            (direction INPUT))
+          (port CEA
+            (direction INPUT))
+          (port OCEA
+            (direction INPUT))
+          (port CLKA
+            (direction INPUT))
+          (port WEA
+            (direction INPUT))
+          (port CSA2
+            (direction INPUT))
+          (port CSA1
+            (direction INPUT))
+          (port CSA0
+            (direction INPUT))
+          (port RSTA
+            (direction INPUT))
+          (port DIB17
+            (direction INPUT))
+          (port DIB16
+            (direction INPUT))
+          (port DIB15
+            (direction INPUT))
+          (port DIB14
+            (direction INPUT))
+          (port DIB13
+            (direction INPUT))
+          (port DIB12
+            (direction INPUT))
+          (port DIB11
+            (direction INPUT))
+          (port DIB10
+            (direction INPUT))
+          (port DIB9
+            (direction INPUT))
+          (port DIB8
+            (direction INPUT))
+          (port DIB7
+            (direction INPUT))
+          (port DIB6
+            (direction INPUT))
+          (port DIB5
+            (direction INPUT))
+          (port DIB4
+            (direction INPUT))
+          (port DIB3
+            (direction INPUT))
+          (port DIB2
+            (direction INPUT))
+          (port DIB1
+            (direction INPUT))
+          (port DIB0
+            (direction INPUT))
+          (port ADB13
+            (direction INPUT))
+          (port ADB12
+            (direction INPUT))
+          (port ADB11
+            (direction INPUT))
+          (port ADB10
+            (direction INPUT))
+          (port ADB9
+            (direction INPUT))
+          (port ADB8
+            (direction INPUT))
+          (port ADB7
+            (direction INPUT))
+          (port ADB6
+            (direction INPUT))
+          (port ADB5
+            (direction INPUT))
+          (port ADB4
+            (direction INPUT))
+          (port ADB3
+            (direction INPUT))
+          (port ADB2
+            (direction INPUT))
+          (port ADB1
+            (direction INPUT))
+          (port ADB0
+            (direction INPUT))
+          (port CEB
+            (direction INPUT))
+          (port OCEB
+            (direction INPUT))
+          (port CLKB
+            (direction INPUT))
+          (port WEB
+            (direction INPUT))
+          (port CSB2
+            (direction INPUT))
+          (port CSB1
+            (direction INPUT))
+          (port CSB0
+            (direction INPUT))
+          (port RSTB
+            (direction INPUT))
+          (port DOA17
+            (direction OUTPUT))
+          (port DOA16
+            (direction OUTPUT))
+          (port DOA15
+            (direction OUTPUT))
+          (port DOA14
+            (direction OUTPUT))
+          (port DOA13
+            (direction OUTPUT))
+          (port DOA12
+            (direction OUTPUT))
+          (port DOA11
+            (direction OUTPUT))
+          (port DOA10
+            (direction OUTPUT))
+          (port DOA9
+            (direction OUTPUT))
+          (port DOA8
+            (direction OUTPUT))
+          (port DOA7
+            (direction OUTPUT))
+          (port DOA6
+            (direction OUTPUT))
+          (port DOA5
+            (direction OUTPUT))
+          (port DOA4
+            (direction OUTPUT))
+          (port DOA3
+            (direction OUTPUT))
+          (port DOA2
+            (direction OUTPUT))
+          (port DOA1
+            (direction OUTPUT))
+          (port DOA0
+            (direction OUTPUT))
+          (port DOB17
+            (direction OUTPUT))
+          (port DOB16
+            (direction OUTPUT))
+          (port DOB15
+            (direction OUTPUT))
+          (port DOB14
+            (direction OUTPUT))
+          (port DOB13
+            (direction OUTPUT))
+          (port DOB12
+            (direction OUTPUT))
+          (port DOB11
+            (direction OUTPUT))
+          (port DOB10
+            (direction OUTPUT))
+          (port DOB9
+            (direction OUTPUT))
+          (port DOB8
+            (direction OUTPUT))
+          (port DOB7
+            (direction OUTPUT))
+          (port DOB6
+            (direction OUTPUT))
+          (port DOB5
+            (direction OUTPUT))
+          (port DOB4
+            (direction OUTPUT))
+          (port DOB3
+            (direction OUTPUT))
+          (port DOB2
+            (direction OUTPUT))
+          (port DOB1
+            (direction OUTPUT))
+          (port DOB0
+            (direction OUTPUT)))))
+    (cell fifo_36x16k_oreg
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port (array (rename Data "Data(35:0)") 36)
+            (direction INPUT))
+          (port Clock
+            (direction INPUT))
+          (port WrEn
+            (direction INPUT))
+          (port RdEn
+            (direction INPUT))
+          (port Reset
+            (direction INPUT))
+          (port (array (rename AmFullThresh "AmFullThresh(13:0)") 14)
+            (direction INPUT))
+          (port (array (rename Q "Q(35:0)") 36)
+            (direction OUTPUT))
+          (port (array (rename WCNT "WCNT(14:0)") 15)
+            (direction OUTPUT))
+          (port Empty
+            (direction OUTPUT))
+          (port Full
+            (direction OUTPUT))
+          (port AlmostFull
+            (direction OUTPUT)))
+        (property NGD_DRC_MASK (integer 1))
+        (contents
+          (instance AND2_t5
+            (viewRef view1 
+              (cellRef AND2)))
+          (instance INV_5
+            (viewRef view1 
+              (cellRef INV)))
+          (instance AND2_t4
+            (viewRef view1 
+              (cellRef AND2)))
+          (instance INV_4
+            (viewRef view1 
+              (cellRef INV)))
+          (instance AND2_t3
+            (viewRef view1 
+              (cellRef AND2)))
+          (instance XOR2_t2
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance INV_3
+            (viewRef view1 
+              (cellRef INV)))
+          (instance INV_2
+            (viewRef view1 
+              (cellRef INV)))
+          (instance LUT4_1
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x3232")))
+          (instance LUT4_0
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x3232")))
+          (instance AND2_t1
+            (viewRef view1 
+              (cellRef AND2)))
+          (instance INV_1
+            (viewRef view1 
+              (cellRef INV)))
+          (instance XOR2_t0
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance INV_0
+            (viewRef view1 
+              (cellRef INV)))
+          (instance pdp_ram_0_0_31
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x16k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b000"))
+            (property CSDECODE_A
+              (string "0b000"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_0_1_30
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x16k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b000"))
+            (property CSDECODE_A
+              (string "0b000"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_0_2_29
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x16k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b000"))
+            (property CSDECODE_A
+              (string "0b000"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_0_3_28
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x16k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b000"))
+            (property CSDECODE_A
+              (string "0b000"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_1_0_27
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x16k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_1_1_26
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x16k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_1_2_25
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x16k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_1_3_24
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x16k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_2_0_23
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x16k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b010"))
+            (property CSDECODE_A
+              (string "0b010"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_2_1_22
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x16k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b010"))
+            (property CSDECODE_A
+              (string "0b010"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_2_2_21
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x16k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b010"))
+            (property CSDECODE_A
+              (string "0b010"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_2_3_20
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x16k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b010"))
+            (property CSDECODE_A
+              (string "0b010"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_3_0_19
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x16k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b011"))
+            (property CSDECODE_A
+              (string "0b011"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_3_1_18
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x16k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b011"))
+            (property CSDECODE_A
+              (string "0b011"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_3_2_17
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x16k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b011"))
+            (property CSDECODE_A
+              (string "0b011"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_3_3_16
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x16k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b011"))
+            (property CSDECODE_A
+              (string "0b011"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_4_0_15
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x16k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b100"))
+            (property CSDECODE_A
+              (string "0b100"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_4_1_14
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x16k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b100"))
+            (property CSDECODE_A
+              (string "0b100"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_4_2_13
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x16k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b100"))
+            (property CSDECODE_A
+              (string "0b100"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_4_3_12
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x16k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b100"))
+            (property CSDECODE_A
+              (string "0b100"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_5_0_11
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x16k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b101"))
+            (property CSDECODE_A
+              (string "0b101"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_5_1_10
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x16k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b101"))
+            (property CSDECODE_A
+              (string "0b101"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_5_2_9
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x16k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b101"))
+            (property CSDECODE_A
+              (string "0b101"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_5_3_8
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x16k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b101"))
+            (property CSDECODE_A
+              (string "0b101"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_6_0_7
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x16k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b110"))
+            (property CSDECODE_A
+              (string "0b110"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_6_1_6
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x16k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b110"))
+            (property CSDECODE_A
+              (string "0b110"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_6_2_5
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x16k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b110"))
+            (property CSDECODE_A
+              (string "0b110"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_6_3_4
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x16k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b110"))
+            (property CSDECODE_A
+              (string "0b110"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_7_0_3
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x16k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b111"))
+            (property CSDECODE_A
+              (string "0b111"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_7_1_2
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x16k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b111"))
+            (property CSDECODE_A
+              (string "0b111"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_7_2_1
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x16k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b111"))
+            (property CSDECODE_A
+              (string "0b111"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_7_3_0
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x16k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b111"))
+            (property CSDECODE_A
+              (string "0b111"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance FF_98
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_97
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_96
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_95
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_94
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_93
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_92
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_91
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_90
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_89
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_88
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_87
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_86
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_85
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_84
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_83
+            (viewRef view1 
+              (cellRef FD1S3BX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_82
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_81
+            (viewRef view1 
+              (cellRef FD1P3BX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_80
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_79
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_78
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_77
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_76
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_75
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_74
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_73
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_72
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_71
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_70
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_69
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_68
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_67
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_66
+            (viewRef view1 
+              (cellRef FD1P3BX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_65
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_64
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_63
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_62
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_61
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_60
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_59
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_58
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_57
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_56
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_55
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_54
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_53
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_52
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_51
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_50
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_49
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_48
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_47
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_46
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_45
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_44
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_43
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_42
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_41
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_40
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_39
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_38
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_37
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_36
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_35
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_34
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_33
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_32
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_31
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_30
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_29
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_28
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_27
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_26
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_25
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_24
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_23
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_22
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_21
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_20
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_19
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_18
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_17
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_16
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_15
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_14
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_13
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_12
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_11
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_10
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_9
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_8
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_7
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_6
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_5
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_4
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_3
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_2
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_1
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_0
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance bdcnt_bctr_cia
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance bdcnt_bctr_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_6
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_7
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_ci_a
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance e_cmp_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_6
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_7
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance a0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance g_cmp_ci_a
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance g_cmp_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_6
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_7
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance a1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_cia
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_6
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_7
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_cia
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_6
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_7
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance mux_35
+            (viewRef view1 
+              (cellRef MUX81)))
+          (instance mux_34
+            (viewRef view1 
+              (cellRef MUX81)))
+          (instance mux_33
+            (viewRef view1 
+              (cellRef MUX81)))
+          (instance mux_32
+            (viewRef view1 
+              (cellRef MUX81)))
+          (instance mux_31
+            (viewRef view1 
+              (cellRef MUX81)))
+          (instance mux_30
+            (viewRef view1 
+              (cellRef MUX81)))
+          (instance mux_29
+            (viewRef view1 
+              (cellRef MUX81)))
+          (instance mux_28
+            (viewRef view1 
+              (cellRef MUX81)))
+          (instance mux_27
+            (viewRef view1 
+              (cellRef MUX81)))
+          (instance mux_26
+            (viewRef view1 
+              (cellRef MUX81)))
+          (instance mux_25
+            (viewRef view1 
+              (cellRef MUX81)))
+          (instance mux_24
+            (viewRef view1 
+              (cellRef MUX81)))
+          (instance mux_23
+            (viewRef view1 
+              (cellRef MUX81)))
+          (instance mux_22
+            (viewRef view1 
+              (cellRef MUX81)))
+          (instance mux_21
+            (viewRef view1 
+              (cellRef MUX81)))
+          (instance mux_20
+            (viewRef view1 
+              (cellRef MUX81)))
+          (instance mux_19
+            (viewRef view1 
+              (cellRef MUX81)))
+          (instance mux_18
+            (viewRef view1 
+              (cellRef MUX81)))
+          (instance mux_17
+            (viewRef view1 
+              (cellRef MUX81)))
+          (instance mux_16
+            (viewRef view1 
+              (cellRef MUX81)))
+          (instance mux_15
+            (viewRef view1 
+              (cellRef MUX81)))
+          (instance mux_14
+            (viewRef view1 
+              (cellRef MUX81)))
+          (instance mux_13
+            (viewRef view1 
+              (cellRef MUX81)))
+          (instance mux_12
+            (viewRef view1 
+              (cellRef MUX81)))
+          (instance mux_11
+            (viewRef view1 
+              (cellRef MUX81)))
+          (instance mux_10
+            (viewRef view1 
+              (cellRef MUX81)))
+          (instance mux_9
+            (viewRef view1 
+              (cellRef MUX81)))
+          (instance mux_8
+            (viewRef view1 
+              (cellRef MUX81)))
+          (instance mux_7
+            (viewRef view1 
+              (cellRef MUX81)))
+          (instance mux_6
+            (viewRef view1 
+              (cellRef MUX81)))
+          (instance mux_5
+            (viewRef view1 
+              (cellRef MUX81)))
+          (instance mux_4
+            (viewRef view1 
+              (cellRef MUX81)))
+          (instance mux_3
+            (viewRef view1 
+              (cellRef MUX81)))
+          (instance mux_2
+            (viewRef view1 
+              (cellRef MUX81)))
+          (instance mux_1
+            (viewRef view1 
+              (cellRef MUX81)))
+          (instance mux_0
+            (viewRef view1 
+              (cellRef MUX81)))
+          (instance precin_inst636
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x0000"))
+            (property INIT0
+              (string "0x0000")))
+          (instance wcnt_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_6
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_7
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcntd
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance af_set_cmp_ci_a
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance af_set_cmp_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_6
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_7
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance scuba_vhi_inst
+            (viewRef view1 
+              (cellRef VHI)))
+          (instance scuba_vlo_inst
+            (viewRef view1 
+              (cellRef VLO)))
+          (instance a2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (net invout_2
+            (joined
+              (portRef Z (instanceRef INV_5))
+              (portRef B (instanceRef AND2_t5))))
+          (net invout_1
+            (joined
+              (portRef Z (instanceRef INV_4))
+              (portRef B (instanceRef AND2_t4))))
+          (net rden_i_inv
+            (joined
+              (portRef Z (instanceRef INV_3))
+              (portRef B (instanceRef AND2_t3))))
+          (net invout_0
+            (joined
+              (portRef Z (instanceRef INV_1))
+              (portRef B (instanceRef AND2_t1))))
+          (net r_nw
+            (joined
+              (portRef Z (instanceRef AND2_t1))))
+          (net fcnt_en
+            (joined
+              (portRef SP (instanceRef FF_84))
+              (portRef Z (instanceRef XOR2_t2))
+              (portRef SP (instanceRef FF_98))
+              (portRef SP (instanceRef FF_97))
+              (portRef SP (instanceRef FF_96))
+              (portRef SP (instanceRef FF_95))
+              (portRef SP (instanceRef FF_94))
+              (portRef SP (instanceRef FF_93))
+              (portRef SP (instanceRef FF_92))
+              (portRef SP (instanceRef FF_91))
+              (portRef SP (instanceRef FF_90))
+              (portRef SP (instanceRef FF_89))
+              (portRef SP (instanceRef FF_88))
+              (portRef SP (instanceRef FF_87))
+              (portRef SP (instanceRef FF_86))
+              (portRef SP (instanceRef FF_85))))
+          (net empty_d
+            (joined
+              (portRef D (instanceRef FF_83))
+              (portRef DO0 (instanceRef LUT4_1))))
+          (net full_d
+            (joined
+              (portRef D (instanceRef FF_82))
+              (portRef DO0 (instanceRef LUT4_0))))
+          (net wptr_0
+            (joined
+              (portRef Q (instanceRef FF_51))
+              (portRef ADA3 (instanceRef pdp_ram_0_0_31))
+              (portRef ADA3 (instanceRef pdp_ram_0_1_30))
+              (portRef ADA3 (instanceRef pdp_ram_0_2_29))
+              (portRef ADA3 (instanceRef pdp_ram_0_3_28))
+              (portRef ADA3 (instanceRef pdp_ram_1_0_27))
+              (portRef ADA3 (instanceRef pdp_ram_1_1_26))
+              (portRef ADA3 (instanceRef pdp_ram_1_2_25))
+              (portRef ADA3 (instanceRef pdp_ram_1_3_24))
+              (portRef ADA3 (instanceRef pdp_ram_2_0_23))
+              (portRef ADA3 (instanceRef pdp_ram_2_1_22))
+              (portRef ADA3 (instanceRef pdp_ram_2_2_21))
+              (portRef ADA3 (instanceRef pdp_ram_2_3_20))
+              (portRef ADA3 (instanceRef pdp_ram_3_0_19))
+              (portRef ADA3 (instanceRef pdp_ram_3_1_18))
+              (portRef ADA3 (instanceRef pdp_ram_3_2_17))
+              (portRef ADA3 (instanceRef pdp_ram_3_3_16))
+              (portRef ADA3 (instanceRef pdp_ram_4_0_15))
+              (portRef ADA3 (instanceRef pdp_ram_4_1_14))
+              (portRef ADA3 (instanceRef pdp_ram_4_2_13))
+              (portRef ADA3 (instanceRef pdp_ram_4_3_12))
+              (portRef ADA3 (instanceRef pdp_ram_5_0_11))
+              (portRef ADA3 (instanceRef pdp_ram_5_1_10))
+              (portRef ADA3 (instanceRef pdp_ram_5_2_9))
+              (portRef ADA3 (instanceRef pdp_ram_5_3_8))
+              (portRef ADA3 (instanceRef pdp_ram_6_0_7))
+              (portRef ADA3 (instanceRef pdp_ram_6_1_6))
+              (portRef ADA3 (instanceRef pdp_ram_6_2_5))
+              (portRef ADA3 (instanceRef pdp_ram_6_3_4))
+              (portRef ADA3 (instanceRef pdp_ram_7_0_3))
+              (portRef ADA3 (instanceRef pdp_ram_7_1_2))
+              (portRef ADA3 (instanceRef pdp_ram_7_2_1))
+              (portRef ADA3 (instanceRef pdp_ram_7_3_0))))
+          (net wptr_1
+            (joined
+              (portRef Q (instanceRef FF_50))
+              (portRef ADA4 (instanceRef pdp_ram_0_0_31))
+              (portRef ADA4 (instanceRef pdp_ram_0_1_30))
+              (portRef ADA4 (instanceRef pdp_ram_0_2_29))
+              (portRef ADA4 (instanceRef pdp_ram_0_3_28))
+              (portRef ADA4 (instanceRef pdp_ram_1_0_27))
+              (portRef ADA4 (instanceRef pdp_ram_1_1_26))
+              (portRef ADA4 (instanceRef pdp_ram_1_2_25))
+              (portRef ADA4 (instanceRef pdp_ram_1_3_24))
+              (portRef ADA4 (instanceRef pdp_ram_2_0_23))
+              (portRef ADA4 (instanceRef pdp_ram_2_1_22))
+              (portRef ADA4 (instanceRef pdp_ram_2_2_21))
+              (portRef ADA4 (instanceRef pdp_ram_2_3_20))
+              (portRef ADA4 (instanceRef pdp_ram_3_0_19))
+              (portRef ADA4 (instanceRef pdp_ram_3_1_18))
+              (portRef ADA4 (instanceRef pdp_ram_3_2_17))
+              (portRef ADA4 (instanceRef pdp_ram_3_3_16))
+              (portRef ADA4 (instanceRef pdp_ram_4_0_15))
+              (portRef ADA4 (instanceRef pdp_ram_4_1_14))
+              (portRef ADA4 (instanceRef pdp_ram_4_2_13))
+              (portRef ADA4 (instanceRef pdp_ram_4_3_12))
+              (portRef ADA4 (instanceRef pdp_ram_5_0_11))
+              (portRef ADA4 (instanceRef pdp_ram_5_1_10))
+              (portRef ADA4 (instanceRef pdp_ram_5_2_9))
+              (portRef ADA4 (instanceRef pdp_ram_5_3_8))
+              (portRef ADA4 (instanceRef pdp_ram_6_0_7))
+              (portRef ADA4 (instanceRef pdp_ram_6_1_6))
+              (portRef ADA4 (instanceRef pdp_ram_6_2_5))
+              (portRef ADA4 (instanceRef pdp_ram_6_3_4))
+              (portRef ADA4 (instanceRef pdp_ram_7_0_3))
+              (portRef ADA4 (instanceRef pdp_ram_7_1_2))
+              (portRef ADA4 (instanceRef pdp_ram_7_2_1))
+              (portRef ADA4 (instanceRef pdp_ram_7_3_0))))
+          (net wptr_2
+            (joined
+              (portRef Q (instanceRef FF_49))
+              (portRef ADA5 (instanceRef pdp_ram_0_0_31))
+              (portRef ADA5 (instanceRef pdp_ram_0_1_30))
+              (portRef ADA5 (instanceRef pdp_ram_0_2_29))
+              (portRef ADA5 (instanceRef pdp_ram_0_3_28))
+              (portRef ADA5 (instanceRef pdp_ram_1_0_27))
+              (portRef ADA5 (instanceRef pdp_ram_1_1_26))
+              (portRef ADA5 (instanceRef pdp_ram_1_2_25))
+              (portRef ADA5 (instanceRef pdp_ram_1_3_24))
+              (portRef ADA5 (instanceRef pdp_ram_2_0_23))
+              (portRef ADA5 (instanceRef pdp_ram_2_1_22))
+              (portRef ADA5 (instanceRef pdp_ram_2_2_21))
+              (portRef ADA5 (instanceRef pdp_ram_2_3_20))
+              (portRef ADA5 (instanceRef pdp_ram_3_0_19))
+              (portRef ADA5 (instanceRef pdp_ram_3_1_18))
+              (portRef ADA5 (instanceRef pdp_ram_3_2_17))
+              (portRef ADA5 (instanceRef pdp_ram_3_3_16))
+              (portRef ADA5 (instanceRef pdp_ram_4_0_15))
+              (portRef ADA5 (instanceRef pdp_ram_4_1_14))
+              (portRef ADA5 (instanceRef pdp_ram_4_2_13))
+              (portRef ADA5 (instanceRef pdp_ram_4_3_12))
+              (portRef ADA5 (instanceRef pdp_ram_5_0_11))
+              (portRef ADA5 (instanceRef pdp_ram_5_1_10))
+              (portRef ADA5 (instanceRef pdp_ram_5_2_9))
+              (portRef ADA5 (instanceRef pdp_ram_5_3_8))
+              (portRef ADA5 (instanceRef pdp_ram_6_0_7))
+              (portRef ADA5 (instanceRef pdp_ram_6_1_6))
+              (portRef ADA5 (instanceRef pdp_ram_6_2_5))
+              (portRef ADA5 (instanceRef pdp_ram_6_3_4))
+              (portRef ADA5 (instanceRef pdp_ram_7_0_3))
+              (portRef ADA5 (instanceRef pdp_ram_7_1_2))
+              (portRef ADA5 (instanceRef pdp_ram_7_2_1))
+              (portRef ADA5 (instanceRef pdp_ram_7_3_0))))
+          (net wptr_3
+            (joined
+              (portRef Q (instanceRef FF_48))
+              (portRef ADA6 (instanceRef pdp_ram_0_0_31))
+              (portRef ADA6 (instanceRef pdp_ram_0_1_30))
+              (portRef ADA6 (instanceRef pdp_ram_0_2_29))
+              (portRef ADA6 (instanceRef pdp_ram_0_3_28))
+              (portRef ADA6 (instanceRef pdp_ram_1_0_27))
+              (portRef ADA6 (instanceRef pdp_ram_1_1_26))
+              (portRef ADA6 (instanceRef pdp_ram_1_2_25))
+              (portRef ADA6 (instanceRef pdp_ram_1_3_24))
+              (portRef ADA6 (instanceRef pdp_ram_2_0_23))
+              (portRef ADA6 (instanceRef pdp_ram_2_1_22))
+              (portRef ADA6 (instanceRef pdp_ram_2_2_21))
+              (portRef ADA6 (instanceRef pdp_ram_2_3_20))
+              (portRef ADA6 (instanceRef pdp_ram_3_0_19))
+              (portRef ADA6 (instanceRef pdp_ram_3_1_18))
+              (portRef ADA6 (instanceRef pdp_ram_3_2_17))
+              (portRef ADA6 (instanceRef pdp_ram_3_3_16))
+              (portRef ADA6 (instanceRef pdp_ram_4_0_15))
+              (portRef ADA6 (instanceRef pdp_ram_4_1_14))
+              (portRef ADA6 (instanceRef pdp_ram_4_2_13))
+              (portRef ADA6 (instanceRef pdp_ram_4_3_12))
+              (portRef ADA6 (instanceRef pdp_ram_5_0_11))
+              (portRef ADA6 (instanceRef pdp_ram_5_1_10))
+              (portRef ADA6 (instanceRef pdp_ram_5_2_9))
+              (portRef ADA6 (instanceRef pdp_ram_5_3_8))
+              (portRef ADA6 (instanceRef pdp_ram_6_0_7))
+              (portRef ADA6 (instanceRef pdp_ram_6_1_6))
+              (portRef ADA6 (instanceRef pdp_ram_6_2_5))
+              (portRef ADA6 (instanceRef pdp_ram_6_3_4))
+              (portRef ADA6 (instanceRef pdp_ram_7_0_3))
+              (portRef ADA6 (instanceRef pdp_ram_7_1_2))
+              (portRef ADA6 (instanceRef pdp_ram_7_2_1))
+              (portRef ADA6 (instanceRef pdp_ram_7_3_0))))
+          (net wptr_4
+            (joined
+              (portRef Q (instanceRef FF_47))
+              (portRef ADA7 (instanceRef pdp_ram_0_0_31))
+              (portRef ADA7 (instanceRef pdp_ram_0_1_30))
+              (portRef ADA7 (instanceRef pdp_ram_0_2_29))
+              (portRef ADA7 (instanceRef pdp_ram_0_3_28))
+              (portRef ADA7 (instanceRef pdp_ram_1_0_27))
+              (portRef ADA7 (instanceRef pdp_ram_1_1_26))
+              (portRef ADA7 (instanceRef pdp_ram_1_2_25))
+              (portRef ADA7 (instanceRef pdp_ram_1_3_24))
+              (portRef ADA7 (instanceRef pdp_ram_2_0_23))
+              (portRef ADA7 (instanceRef pdp_ram_2_1_22))
+              (portRef ADA7 (instanceRef pdp_ram_2_2_21))
+              (portRef ADA7 (instanceRef pdp_ram_2_3_20))
+              (portRef ADA7 (instanceRef pdp_ram_3_0_19))
+              (portRef ADA7 (instanceRef pdp_ram_3_1_18))
+              (portRef ADA7 (instanceRef pdp_ram_3_2_17))
+              (portRef ADA7 (instanceRef pdp_ram_3_3_16))
+              (portRef ADA7 (instanceRef pdp_ram_4_0_15))
+              (portRef ADA7 (instanceRef pdp_ram_4_1_14))
+              (portRef ADA7 (instanceRef pdp_ram_4_2_13))
+              (portRef ADA7 (instanceRef pdp_ram_4_3_12))
+              (portRef ADA7 (instanceRef pdp_ram_5_0_11))
+              (portRef ADA7 (instanceRef pdp_ram_5_1_10))
+              (portRef ADA7 (instanceRef pdp_ram_5_2_9))
+              (portRef ADA7 (instanceRef pdp_ram_5_3_8))
+              (portRef ADA7 (instanceRef pdp_ram_6_0_7))
+              (portRef ADA7 (instanceRef pdp_ram_6_1_6))
+              (portRef ADA7 (instanceRef pdp_ram_6_2_5))
+              (portRef ADA7 (instanceRef pdp_ram_6_3_4))
+              (portRef ADA7 (instanceRef pdp_ram_7_0_3))
+              (portRef ADA7 (instanceRef pdp_ram_7_1_2))
+              (portRef ADA7 (instanceRef pdp_ram_7_2_1))
+              (portRef ADA7 (instanceRef pdp_ram_7_3_0))))
+          (net wptr_5
+            (joined
+              (portRef Q (instanceRef FF_46))
+              (portRef ADA8 (instanceRef pdp_ram_0_0_31))
+              (portRef ADA8 (instanceRef pdp_ram_0_1_30))
+              (portRef ADA8 (instanceRef pdp_ram_0_2_29))
+              (portRef ADA8 (instanceRef pdp_ram_0_3_28))
+              (portRef ADA8 (instanceRef pdp_ram_1_0_27))
+              (portRef ADA8 (instanceRef pdp_ram_1_1_26))
+              (portRef ADA8 (instanceRef pdp_ram_1_2_25))
+              (portRef ADA8 (instanceRef pdp_ram_1_3_24))
+              (portRef ADA8 (instanceRef pdp_ram_2_0_23))
+              (portRef ADA8 (instanceRef pdp_ram_2_1_22))
+              (portRef ADA8 (instanceRef pdp_ram_2_2_21))
+              (portRef ADA8 (instanceRef pdp_ram_2_3_20))
+              (portRef ADA8 (instanceRef pdp_ram_3_0_19))
+              (portRef ADA8 (instanceRef pdp_ram_3_1_18))
+              (portRef ADA8 (instanceRef pdp_ram_3_2_17))
+              (portRef ADA8 (instanceRef pdp_ram_3_3_16))
+              (portRef ADA8 (instanceRef pdp_ram_4_0_15))
+              (portRef ADA8 (instanceRef pdp_ram_4_1_14))
+              (portRef ADA8 (instanceRef pdp_ram_4_2_13))
+              (portRef ADA8 (instanceRef pdp_ram_4_3_12))
+              (portRef ADA8 (instanceRef pdp_ram_5_0_11))
+              (portRef ADA8 (instanceRef pdp_ram_5_1_10))
+              (portRef ADA8 (instanceRef pdp_ram_5_2_9))
+              (portRef ADA8 (instanceRef pdp_ram_5_3_8))
+              (portRef ADA8 (instanceRef pdp_ram_6_0_7))
+              (portRef ADA8 (instanceRef pdp_ram_6_1_6))
+              (portRef ADA8 (instanceRef pdp_ram_6_2_5))
+              (portRef ADA8 (instanceRef pdp_ram_6_3_4))
+              (portRef ADA8 (instanceRef pdp_ram_7_0_3))
+              (portRef ADA8 (instanceRef pdp_ram_7_1_2))
+              (portRef ADA8 (instanceRef pdp_ram_7_2_1))
+              (portRef ADA8 (instanceRef pdp_ram_7_3_0))))
+          (net wptr_6
+            (joined
+              (portRef Q (instanceRef FF_45))
+              (portRef ADA9 (instanceRef pdp_ram_0_0_31))
+              (portRef ADA9 (instanceRef pdp_ram_0_1_30))
+              (portRef ADA9 (instanceRef pdp_ram_0_2_29))
+              (portRef ADA9 (instanceRef pdp_ram_0_3_28))
+              (portRef ADA9 (instanceRef pdp_ram_1_0_27))
+              (portRef ADA9 (instanceRef pdp_ram_1_1_26))
+              (portRef ADA9 (instanceRef pdp_ram_1_2_25))
+              (portRef ADA9 (instanceRef pdp_ram_1_3_24))
+              (portRef ADA9 (instanceRef pdp_ram_2_0_23))
+              (portRef ADA9 (instanceRef pdp_ram_2_1_22))
+              (portRef ADA9 (instanceRef pdp_ram_2_2_21))
+              (portRef ADA9 (instanceRef pdp_ram_2_3_20))
+              (portRef ADA9 (instanceRef pdp_ram_3_0_19))
+              (portRef ADA9 (instanceRef pdp_ram_3_1_18))
+              (portRef ADA9 (instanceRef pdp_ram_3_2_17))
+              (portRef ADA9 (instanceRef pdp_ram_3_3_16))
+              (portRef ADA9 (instanceRef pdp_ram_4_0_15))
+              (portRef ADA9 (instanceRef pdp_ram_4_1_14))
+              (portRef ADA9 (instanceRef pdp_ram_4_2_13))
+              (portRef ADA9 (instanceRef pdp_ram_4_3_12))
+              (portRef ADA9 (instanceRef pdp_ram_5_0_11))
+              (portRef ADA9 (instanceRef pdp_ram_5_1_10))
+              (portRef ADA9 (instanceRef pdp_ram_5_2_9))
+              (portRef ADA9 (instanceRef pdp_ram_5_3_8))
+              (portRef ADA9 (instanceRef pdp_ram_6_0_7))
+              (portRef ADA9 (instanceRef pdp_ram_6_1_6))
+              (portRef ADA9 (instanceRef pdp_ram_6_2_5))
+              (portRef ADA9 (instanceRef pdp_ram_6_3_4))
+              (portRef ADA9 (instanceRef pdp_ram_7_0_3))
+              (portRef ADA9 (instanceRef pdp_ram_7_1_2))
+              (portRef ADA9 (instanceRef pdp_ram_7_2_1))
+              (portRef ADA9 (instanceRef pdp_ram_7_3_0))))
+          (net wptr_7
+            (joined
+              (portRef Q (instanceRef FF_44))
+              (portRef ADA10 (instanceRef pdp_ram_0_0_31))
+              (portRef ADA10 (instanceRef pdp_ram_0_1_30))
+              (portRef ADA10 (instanceRef pdp_ram_0_2_29))
+              (portRef ADA10 (instanceRef pdp_ram_0_3_28))
+              (portRef ADA10 (instanceRef pdp_ram_1_0_27))
+              (portRef ADA10 (instanceRef pdp_ram_1_1_26))
+              (portRef ADA10 (instanceRef pdp_ram_1_2_25))
+              (portRef ADA10 (instanceRef pdp_ram_1_3_24))
+              (portRef ADA10 (instanceRef pdp_ram_2_0_23))
+              (portRef ADA10 (instanceRef pdp_ram_2_1_22))
+              (portRef ADA10 (instanceRef pdp_ram_2_2_21))
+              (portRef ADA10 (instanceRef pdp_ram_2_3_20))
+              (portRef ADA10 (instanceRef pdp_ram_3_0_19))
+              (portRef ADA10 (instanceRef pdp_ram_3_1_18))
+              (portRef ADA10 (instanceRef pdp_ram_3_2_17))
+              (portRef ADA10 (instanceRef pdp_ram_3_3_16))
+              (portRef ADA10 (instanceRef pdp_ram_4_0_15))
+              (portRef ADA10 (instanceRef pdp_ram_4_1_14))
+              (portRef ADA10 (instanceRef pdp_ram_4_2_13))
+              (portRef ADA10 (instanceRef pdp_ram_4_3_12))
+              (portRef ADA10 (instanceRef pdp_ram_5_0_11))
+              (portRef ADA10 (instanceRef pdp_ram_5_1_10))
+              (portRef ADA10 (instanceRef pdp_ram_5_2_9))
+              (portRef ADA10 (instanceRef pdp_ram_5_3_8))
+              (portRef ADA10 (instanceRef pdp_ram_6_0_7))
+              (portRef ADA10 (instanceRef pdp_ram_6_1_6))
+              (portRef ADA10 (instanceRef pdp_ram_6_2_5))
+              (portRef ADA10 (instanceRef pdp_ram_6_3_4))
+              (portRef ADA10 (instanceRef pdp_ram_7_0_3))
+              (portRef ADA10 (instanceRef pdp_ram_7_1_2))
+              (portRef ADA10 (instanceRef pdp_ram_7_2_1))
+              (portRef ADA10 (instanceRef pdp_ram_7_3_0))))
+          (net wptr_8
+            (joined
+              (portRef Q (instanceRef FF_43))
+              (portRef ADA11 (instanceRef pdp_ram_0_0_31))
+              (portRef ADA11 (instanceRef pdp_ram_0_1_30))
+              (portRef ADA11 (instanceRef pdp_ram_0_2_29))
+              (portRef ADA11 (instanceRef pdp_ram_0_3_28))
+              (portRef ADA11 (instanceRef pdp_ram_1_0_27))
+              (portRef ADA11 (instanceRef pdp_ram_1_1_26))
+              (portRef ADA11 (instanceRef pdp_ram_1_2_25))
+              (portRef ADA11 (instanceRef pdp_ram_1_3_24))
+              (portRef ADA11 (instanceRef pdp_ram_2_0_23))
+              (portRef ADA11 (instanceRef pdp_ram_2_1_22))
+              (portRef ADA11 (instanceRef pdp_ram_2_2_21))
+              (portRef ADA11 (instanceRef pdp_ram_2_3_20))
+              (portRef ADA11 (instanceRef pdp_ram_3_0_19))
+              (portRef ADA11 (instanceRef pdp_ram_3_1_18))
+              (portRef ADA11 (instanceRef pdp_ram_3_2_17))
+              (portRef ADA11 (instanceRef pdp_ram_3_3_16))
+              (portRef ADA11 (instanceRef pdp_ram_4_0_15))
+              (portRef ADA11 (instanceRef pdp_ram_4_1_14))
+              (portRef ADA11 (instanceRef pdp_ram_4_2_13))
+              (portRef ADA11 (instanceRef pdp_ram_4_3_12))
+              (portRef ADA11 (instanceRef pdp_ram_5_0_11))
+              (portRef ADA11 (instanceRef pdp_ram_5_1_10))
+              (portRef ADA11 (instanceRef pdp_ram_5_2_9))
+              (portRef ADA11 (instanceRef pdp_ram_5_3_8))
+              (portRef ADA11 (instanceRef pdp_ram_6_0_7))
+              (portRef ADA11 (instanceRef pdp_ram_6_1_6))
+              (portRef ADA11 (instanceRef pdp_ram_6_2_5))
+              (portRef ADA11 (instanceRef pdp_ram_6_3_4))
+              (portRef ADA11 (instanceRef pdp_ram_7_0_3))
+              (portRef ADA11 (instanceRef pdp_ram_7_1_2))
+              (portRef ADA11 (instanceRef pdp_ram_7_2_1))
+              (portRef ADA11 (instanceRef pdp_ram_7_3_0))))
+          (net wptr_9
+            (joined
+              (portRef Q (instanceRef FF_42))
+              (portRef ADA12 (instanceRef pdp_ram_0_0_31))
+              (portRef ADA12 (instanceRef pdp_ram_0_1_30))
+              (portRef ADA12 (instanceRef pdp_ram_0_2_29))
+              (portRef ADA12 (instanceRef pdp_ram_0_3_28))
+              (portRef ADA12 (instanceRef pdp_ram_1_0_27))
+              (portRef ADA12 (instanceRef pdp_ram_1_1_26))
+              (portRef ADA12 (instanceRef pdp_ram_1_2_25))
+              (portRef ADA12 (instanceRef pdp_ram_1_3_24))
+              (portRef ADA12 (instanceRef pdp_ram_2_0_23))
+              (portRef ADA12 (instanceRef pdp_ram_2_1_22))
+              (portRef ADA12 (instanceRef pdp_ram_2_2_21))
+              (portRef ADA12 (instanceRef pdp_ram_2_3_20))
+              (portRef ADA12 (instanceRef pdp_ram_3_0_19))
+              (portRef ADA12 (instanceRef pdp_ram_3_1_18))
+              (portRef ADA12 (instanceRef pdp_ram_3_2_17))
+              (portRef ADA12 (instanceRef pdp_ram_3_3_16))
+              (portRef ADA12 (instanceRef pdp_ram_4_0_15))
+              (portRef ADA12 (instanceRef pdp_ram_4_1_14))
+              (portRef ADA12 (instanceRef pdp_ram_4_2_13))
+              (portRef ADA12 (instanceRef pdp_ram_4_3_12))
+              (portRef ADA12 (instanceRef pdp_ram_5_0_11))
+              (portRef ADA12 (instanceRef pdp_ram_5_1_10))
+              (portRef ADA12 (instanceRef pdp_ram_5_2_9))
+              (portRef ADA12 (instanceRef pdp_ram_5_3_8))
+              (portRef ADA12 (instanceRef pdp_ram_6_0_7))
+              (portRef ADA12 (instanceRef pdp_ram_6_1_6))
+              (portRef ADA12 (instanceRef pdp_ram_6_2_5))
+              (portRef ADA12 (instanceRef pdp_ram_6_3_4))
+              (portRef ADA12 (instanceRef pdp_ram_7_0_3))
+              (portRef ADA12 (instanceRef pdp_ram_7_1_2))
+              (portRef ADA12 (instanceRef pdp_ram_7_2_1))
+              (portRef ADA12 (instanceRef pdp_ram_7_3_0))))
+          (net wptr_10
+            (joined
+              (portRef Q (instanceRef FF_41))
+              (portRef ADA13 (instanceRef pdp_ram_0_0_31))
+              (portRef ADA13 (instanceRef pdp_ram_0_1_30))
+              (portRef ADA13 (instanceRef pdp_ram_0_2_29))
+              (portRef ADA13 (instanceRef pdp_ram_0_3_28))
+              (portRef ADA13 (instanceRef pdp_ram_1_0_27))
+              (portRef ADA13 (instanceRef pdp_ram_1_1_26))
+              (portRef ADA13 (instanceRef pdp_ram_1_2_25))
+              (portRef ADA13 (instanceRef pdp_ram_1_3_24))
+              (portRef ADA13 (instanceRef pdp_ram_2_0_23))
+              (portRef ADA13 (instanceRef pdp_ram_2_1_22))
+              (portRef ADA13 (instanceRef pdp_ram_2_2_21))
+              (portRef ADA13 (instanceRef pdp_ram_2_3_20))
+              (portRef ADA13 (instanceRef pdp_ram_3_0_19))
+              (portRef ADA13 (instanceRef pdp_ram_3_1_18))
+              (portRef ADA13 (instanceRef pdp_ram_3_2_17))
+              (portRef ADA13 (instanceRef pdp_ram_3_3_16))
+              (portRef ADA13 (instanceRef pdp_ram_4_0_15))
+              (portRef ADA13 (instanceRef pdp_ram_4_1_14))
+              (portRef ADA13 (instanceRef pdp_ram_4_2_13))
+              (portRef ADA13 (instanceRef pdp_ram_4_3_12))
+              (portRef ADA13 (instanceRef pdp_ram_5_0_11))
+              (portRef ADA13 (instanceRef pdp_ram_5_1_10))
+              (portRef ADA13 (instanceRef pdp_ram_5_2_9))
+              (portRef ADA13 (instanceRef pdp_ram_5_3_8))
+              (portRef ADA13 (instanceRef pdp_ram_6_0_7))
+              (portRef ADA13 (instanceRef pdp_ram_6_1_6))
+              (portRef ADA13 (instanceRef pdp_ram_6_2_5))
+              (portRef ADA13 (instanceRef pdp_ram_6_3_4))
+              (portRef ADA13 (instanceRef pdp_ram_7_0_3))
+              (portRef ADA13 (instanceRef pdp_ram_7_1_2))
+              (portRef ADA13 (instanceRef pdp_ram_7_2_1))
+              (portRef ADA13 (instanceRef pdp_ram_7_3_0))))
+          (net wptr_11
+            (joined
+              (portRef Q (instanceRef FF_40))
+              (portRef CSA0 (instanceRef pdp_ram_0_0_31))
+              (portRef CSA0 (instanceRef pdp_ram_0_1_30))
+              (portRef CSA0 (instanceRef pdp_ram_0_2_29))
+              (portRef CSA0 (instanceRef pdp_ram_0_3_28))
+              (portRef CSA0 (instanceRef pdp_ram_1_0_27))
+              (portRef CSA0 (instanceRef pdp_ram_1_1_26))
+              (portRef CSA0 (instanceRef pdp_ram_1_2_25))
+              (portRef CSA0 (instanceRef pdp_ram_1_3_24))
+              (portRef CSA0 (instanceRef pdp_ram_2_0_23))
+              (portRef CSA0 (instanceRef pdp_ram_2_1_22))
+              (portRef CSA0 (instanceRef pdp_ram_2_2_21))
+              (portRef CSA0 (instanceRef pdp_ram_2_3_20))
+              (portRef CSA0 (instanceRef pdp_ram_3_0_19))
+              (portRef CSA0 (instanceRef pdp_ram_3_1_18))
+              (portRef CSA0 (instanceRef pdp_ram_3_2_17))
+              (portRef CSA0 (instanceRef pdp_ram_3_3_16))
+              (portRef CSA0 (instanceRef pdp_ram_4_0_15))
+              (portRef CSA0 (instanceRef pdp_ram_4_1_14))
+              (portRef CSA0 (instanceRef pdp_ram_4_2_13))
+              (portRef CSA0 (instanceRef pdp_ram_4_3_12))
+              (portRef CSA0 (instanceRef pdp_ram_5_0_11))
+              (portRef CSA0 (instanceRef pdp_ram_5_1_10))
+              (portRef CSA0 (instanceRef pdp_ram_5_2_9))
+              (portRef CSA0 (instanceRef pdp_ram_5_3_8))
+              (portRef CSA0 (instanceRef pdp_ram_6_0_7))
+              (portRef CSA0 (instanceRef pdp_ram_6_1_6))
+              (portRef CSA0 (instanceRef pdp_ram_6_2_5))
+              (portRef CSA0 (instanceRef pdp_ram_6_3_4))
+              (portRef CSA0 (instanceRef pdp_ram_7_0_3))
+              (portRef CSA0 (instanceRef pdp_ram_7_1_2))
+              (portRef CSA0 (instanceRef pdp_ram_7_2_1))
+              (portRef CSA0 (instanceRef pdp_ram_7_3_0))))
+          (net wptr_12
+            (joined
+              (portRef Q (instanceRef FF_39))
+              (portRef CSA1 (instanceRef pdp_ram_0_0_31))
+              (portRef CSA1 (instanceRef pdp_ram_0_1_30))
+              (portRef CSA1 (instanceRef pdp_ram_0_2_29))
+              (portRef CSA1 (instanceRef pdp_ram_0_3_28))
+              (portRef CSA1 (instanceRef pdp_ram_1_0_27))
+              (portRef CSA1 (instanceRef pdp_ram_1_1_26))
+              (portRef CSA1 (instanceRef pdp_ram_1_2_25))
+              (portRef CSA1 (instanceRef pdp_ram_1_3_24))
+              (portRef CSA1 (instanceRef pdp_ram_2_0_23))
+              (portRef CSA1 (instanceRef pdp_ram_2_1_22))
+              (portRef CSA1 (instanceRef pdp_ram_2_2_21))
+              (portRef CSA1 (instanceRef pdp_ram_2_3_20))
+              (portRef CSA1 (instanceRef pdp_ram_3_0_19))
+              (portRef CSA1 (instanceRef pdp_ram_3_1_18))
+              (portRef CSA1 (instanceRef pdp_ram_3_2_17))
+              (portRef CSA1 (instanceRef pdp_ram_3_3_16))
+              (portRef CSA1 (instanceRef pdp_ram_4_0_15))
+              (portRef CSA1 (instanceRef pdp_ram_4_1_14))
+              (portRef CSA1 (instanceRef pdp_ram_4_2_13))
+              (portRef CSA1 (instanceRef pdp_ram_4_3_12))
+              (portRef CSA1 (instanceRef pdp_ram_5_0_11))
+              (portRef CSA1 (instanceRef pdp_ram_5_1_10))
+              (portRef CSA1 (instanceRef pdp_ram_5_2_9))
+              (portRef CSA1 (instanceRef pdp_ram_5_3_8))
+              (portRef CSA1 (instanceRef pdp_ram_6_0_7))
+              (portRef CSA1 (instanceRef pdp_ram_6_1_6))
+              (portRef CSA1 (instanceRef pdp_ram_6_2_5))
+              (portRef CSA1 (instanceRef pdp_ram_6_3_4))
+              (portRef CSA1 (instanceRef pdp_ram_7_0_3))
+              (portRef CSA1 (instanceRef pdp_ram_7_1_2))
+              (portRef CSA1 (instanceRef pdp_ram_7_2_1))
+              (portRef CSA1 (instanceRef pdp_ram_7_3_0))))
+          (net wptr_13
+            (joined
+              (portRef Q (instanceRef FF_38))
+              (portRef CSA2 (instanceRef pdp_ram_0_0_31))
+              (portRef CSA2 (instanceRef pdp_ram_0_1_30))
+              (portRef CSA2 (instanceRef pdp_ram_0_2_29))
+              (portRef CSA2 (instanceRef pdp_ram_0_3_28))
+              (portRef CSA2 (instanceRef pdp_ram_1_0_27))
+              (portRef CSA2 (instanceRef pdp_ram_1_1_26))
+              (portRef CSA2 (instanceRef pdp_ram_1_2_25))
+              (portRef CSA2 (instanceRef pdp_ram_1_3_24))
+              (portRef CSA2 (instanceRef pdp_ram_2_0_23))
+              (portRef CSA2 (instanceRef pdp_ram_2_1_22))
+              (portRef CSA2 (instanceRef pdp_ram_2_2_21))
+              (portRef CSA2 (instanceRef pdp_ram_2_3_20))
+              (portRef CSA2 (instanceRef pdp_ram_3_0_19))
+              (portRef CSA2 (instanceRef pdp_ram_3_1_18))
+              (portRef CSA2 (instanceRef pdp_ram_3_2_17))
+              (portRef CSA2 (instanceRef pdp_ram_3_3_16))
+              (portRef CSA2 (instanceRef pdp_ram_4_0_15))
+              (portRef CSA2 (instanceRef pdp_ram_4_1_14))
+              (portRef CSA2 (instanceRef pdp_ram_4_2_13))
+              (portRef CSA2 (instanceRef pdp_ram_4_3_12))
+              (portRef CSA2 (instanceRef pdp_ram_5_0_11))
+              (portRef CSA2 (instanceRef pdp_ram_5_1_10))
+              (portRef CSA2 (instanceRef pdp_ram_5_2_9))
+              (portRef CSA2 (instanceRef pdp_ram_5_3_8))
+              (portRef CSA2 (instanceRef pdp_ram_6_0_7))
+              (portRef CSA2 (instanceRef pdp_ram_6_1_6))
+              (portRef CSA2 (instanceRef pdp_ram_6_2_5))
+              (portRef CSA2 (instanceRef pdp_ram_6_3_4))
+              (portRef CSA2 (instanceRef pdp_ram_7_0_3))
+              (portRef CSA2 (instanceRef pdp_ram_7_1_2))
+              (portRef CSA2 (instanceRef pdp_ram_7_2_1))
+              (portRef CSA2 (instanceRef pdp_ram_7_3_0))))
+          (net wptr_14
+            (joined
+              (portRef Q (instanceRef FF_37))))
+          (net rptr_14
+            (joined
+              (portRef Q (instanceRef FF_22))
+              (portRef B (instanceRef XOR2_t0))))
+          (net rptr_11_ff
+            (joined
+              (portRef D (instanceRef FF_18))
+              (portRef Q (instanceRef FF_21))))
+          (net rptr_12_ff
+            (joined
+              (portRef D (instanceRef FF_17))
+              (portRef Q (instanceRef FF_20))))
+          (net rptr_13_ff
+            (joined
+              (portRef D (instanceRef FF_16))
+              (portRef Q (instanceRef FF_19))))
+          (net ifcount_0
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_0))
+              (portRef D (instanceRef FF_98))))
+          (net ifcount_1
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_0))
+              (portRef D (instanceRef FF_97))))
+          (net bdcnt_bctr_ci
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_0))
+              (portRef COUT (instanceRef bdcnt_bctr_cia))))
+          (net ifcount_2
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_1))
+              (portRef D (instanceRef FF_96))))
+          (net ifcount_3
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_1))
+              (portRef D (instanceRef FF_95))))
+          (net co0
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_1))
+              (portRef COUT (instanceRef bdcnt_bctr_0))))
+          (net ifcount_4
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_2))
+              (portRef D (instanceRef FF_94))))
+          (net ifcount_5
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_2))
+              (portRef D (instanceRef FF_93))))
+          (net co1
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_2))
+              (portRef COUT (instanceRef bdcnt_bctr_1))))
+          (net ifcount_6
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_3))
+              (portRef D (instanceRef FF_92))))
+          (net ifcount_7
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_3))
+              (portRef D (instanceRef FF_91))))
+          (net co2
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_3))
+              (portRef COUT (instanceRef bdcnt_bctr_2))))
+          (net ifcount_8
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_4))
+              (portRef D (instanceRef FF_90))))
+          (net ifcount_9
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_4))
+              (portRef D (instanceRef FF_89))))
+          (net co3
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_4))
+              (portRef COUT (instanceRef bdcnt_bctr_3))))
+          (net ifcount_10
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_5))
+              (portRef D (instanceRef FF_88))))
+          (net ifcount_11
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_5))
+              (portRef D (instanceRef FF_87))))
+          (net co4
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_5))
+              (portRef COUT (instanceRef bdcnt_bctr_4))))
+          (net ifcount_12
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_6))
+              (portRef D (instanceRef FF_86))))
+          (net ifcount_13
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_6))
+              (portRef D (instanceRef FF_85))))
+          (net co5
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_6))
+              (portRef COUT (instanceRef bdcnt_bctr_5))))
+          (net ifcount_14
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_7))
+              (portRef D (instanceRef FF_84))))
+          (net co7
+            (joined
+              (portRef COUT (instanceRef bdcnt_bctr_7))))
+          (net co6
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_7))
+              (portRef COUT (instanceRef bdcnt_bctr_6))))
+          (net cmp_ci
+            (joined
+              (portRef CIN (instanceRef e_cmp_0))
+              (portRef COUT (instanceRef e_cmp_ci_a))))
+          (net rden_i
+            (joined
+              (portRef A0 (instanceRef e_cmp_0))
+              (portRef Z (instanceRef AND2_t4))
+              (portRef B (instanceRef XOR2_t2))
+              (portRef A (instanceRef INV_3))
+              (portRef AD1 (instanceRef LUT4_0))
+              (portRef A (instanceRef AND2_t1))
+              (portRef CEB (instanceRef pdp_ram_0_0_31))
+              (portRef CEB (instanceRef pdp_ram_0_1_30))
+              (portRef CEB (instanceRef pdp_ram_0_2_29))
+              (portRef CEB (instanceRef pdp_ram_0_3_28))
+              (portRef CEB (instanceRef pdp_ram_1_0_27))
+              (portRef CEB (instanceRef pdp_ram_1_1_26))
+              (portRef CEB (instanceRef pdp_ram_1_2_25))
+              (portRef CEB (instanceRef pdp_ram_1_3_24))
+              (portRef CEB (instanceRef pdp_ram_2_0_23))
+              (portRef CEB (instanceRef pdp_ram_2_1_22))
+              (portRef CEB (instanceRef pdp_ram_2_2_21))
+              (portRef CEB (instanceRef pdp_ram_2_3_20))
+              (portRef CEB (instanceRef pdp_ram_3_0_19))
+              (portRef CEB (instanceRef pdp_ram_3_1_18))
+              (portRef CEB (instanceRef pdp_ram_3_2_17))
+              (portRef CEB (instanceRef pdp_ram_3_3_16))
+              (portRef CEB (instanceRef pdp_ram_4_0_15))
+              (portRef CEB (instanceRef pdp_ram_4_1_14))
+              (portRef CEB (instanceRef pdp_ram_4_2_13))
+              (portRef CEB (instanceRef pdp_ram_4_3_12))
+              (portRef CEB (instanceRef pdp_ram_5_0_11))
+              (portRef CEB (instanceRef pdp_ram_5_1_10))
+              (portRef CEB (instanceRef pdp_ram_5_2_9))
+              (portRef CEB (instanceRef pdp_ram_5_3_8))
+              (portRef CEB (instanceRef pdp_ram_6_0_7))
+              (portRef CEB (instanceRef pdp_ram_6_1_6))
+              (portRef CEB (instanceRef pdp_ram_6_2_5))
+              (portRef CEB (instanceRef pdp_ram_6_3_4))
+              (portRef CEB (instanceRef pdp_ram_7_0_3))
+              (portRef CEB (instanceRef pdp_ram_7_1_2))
+              (portRef CEB (instanceRef pdp_ram_7_2_1))
+              (portRef CEB (instanceRef pdp_ram_7_3_0))
+              (portRef SP (instanceRef FF_66))
+              (portRef SP (instanceRef FF_65))
+              (portRef SP (instanceRef FF_64))
+              (portRef SP (instanceRef FF_63))
+              (portRef SP (instanceRef FF_62))
+              (portRef SP (instanceRef FF_61))
+              (portRef SP (instanceRef FF_60))
+              (portRef SP (instanceRef FF_59))
+              (portRef SP (instanceRef FF_58))
+              (portRef SP (instanceRef FF_57))
+              (portRef SP (instanceRef FF_56))
+              (portRef SP (instanceRef FF_55))
+              (portRef SP (instanceRef FF_54))
+              (portRef SP (instanceRef FF_53))
+              (portRef SP (instanceRef FF_52))
+              (portRef SP (instanceRef FF_36))
+              (portRef SP (instanceRef FF_35))
+              (portRef SP (instanceRef FF_34))
+              (portRef SP (instanceRef FF_33))
+              (portRef SP (instanceRef FF_32))
+              (portRef SP (instanceRef FF_31))
+              (portRef SP (instanceRef FF_30))
+              (portRef SP (instanceRef FF_29))
+              (portRef SP (instanceRef FF_28))
+              (portRef SP (instanceRef FF_27))
+              (portRef SP (instanceRef FF_26))
+              (portRef SP (instanceRef FF_25))
+              (portRef SP (instanceRef FF_24))
+              (portRef SP (instanceRef FF_23))
+              (portRef SP (instanceRef FF_22))
+              (portRef SP (instanceRef FF_21))
+              (portRef SP (instanceRef FF_20))
+              (portRef SP (instanceRef FF_19))
+              (portRef SP (instanceRef FF_18))
+              (portRef SP (instanceRef FF_17))
+              (portRef SP (instanceRef FF_16))))
+          (net co0_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_1))
+              (portRef COUT (instanceRef e_cmp_0))))
+          (net co1_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_2))
+              (portRef COUT (instanceRef e_cmp_1))))
+          (net co2_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_3))
+              (portRef COUT (instanceRef e_cmp_2))))
+          (net co3_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_4))
+              (portRef COUT (instanceRef e_cmp_3))))
+          (net co4_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_5))
+              (portRef COUT (instanceRef e_cmp_4))))
+          (net co5_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_6))
+              (portRef COUT (instanceRef e_cmp_5))))
+          (net co6_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_7))
+              (portRef COUT (instanceRef e_cmp_6))))
+          (net cmp_le_1
+            (joined
+              (portRef S0 (instanceRef a0))
+              (portRef AD2 (instanceRef LUT4_1))))
+          (net cmp_le_1_c
+            (joined
+              (portRef CIN (instanceRef a0))
+              (portRef COUT (instanceRef e_cmp_7))))
+          (net cmp_ci_1
+            (joined
+              (portRef CIN (instanceRef g_cmp_0))
+              (portRef COUT (instanceRef g_cmp_ci_a))))
+          (net co0_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_1))
+              (portRef COUT (instanceRef g_cmp_0))))
+          (net co1_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_2))
+              (portRef COUT (instanceRef g_cmp_1))))
+          (net co2_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_3))
+              (portRef COUT (instanceRef g_cmp_2))))
+          (net co3_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_4))
+              (portRef COUT (instanceRef g_cmp_3))))
+          (net co4_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_5))
+              (portRef COUT (instanceRef g_cmp_4))))
+          (net co5_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_6))
+              (portRef COUT (instanceRef g_cmp_5))))
+          (net co6_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_7))
+              (portRef COUT (instanceRef g_cmp_6))))
+          (net wren_i_inv
+            (joined
+              (portRef B0 (instanceRef g_cmp_7))
+              (portRef Z (instanceRef INV_2))))
+          (net cmp_ge_d1
+            (joined
+              (portRef S0 (instanceRef a1))
+              (portRef AD2 (instanceRef LUT4_0))))
+          (net cmp_ge_d1_c
+            (joined
+              (portRef CIN (instanceRef a1))
+              (portRef COUT (instanceRef g_cmp_7))))
+          (net iwcount_0
+            (joined
+              (portRef S0 (instanceRef w_ctr_0))
+              (portRef D (instanceRef FF_81))))
+          (net iwcount_1
+            (joined
+              (portRef S1 (instanceRef w_ctr_0))
+              (portRef D (instanceRef FF_80))))
+          (net w_ctr_ci
+            (joined
+              (portRef CIN (instanceRef w_ctr_0))
+              (portRef COUT (instanceRef w_ctr_cia))))
+          (net iwcount_2
+            (joined
+              (portRef S0 (instanceRef w_ctr_1))
+              (portRef D (instanceRef FF_79))))
+          (net iwcount_3
+            (joined
+              (portRef S1 (instanceRef w_ctr_1))
+              (portRef D (instanceRef FF_78))))
+          (net co0_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_1))
+              (portRef COUT (instanceRef w_ctr_0))))
+          (net iwcount_4
+            (joined
+              (portRef S0 (instanceRef w_ctr_2))
+              (portRef D (instanceRef FF_77))))
+          (net iwcount_5
+            (joined
+              (portRef S1 (instanceRef w_ctr_2))
+              (portRef D (instanceRef FF_76))))
+          (net co1_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_2))
+              (portRef COUT (instanceRef w_ctr_1))))
+          (net iwcount_6
+            (joined
+              (portRef S0 (instanceRef w_ctr_3))
+              (portRef D (instanceRef FF_75))))
+          (net iwcount_7
+            (joined
+              (portRef S1 (instanceRef w_ctr_3))
+              (portRef D (instanceRef FF_74))))
+          (net co2_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_3))
+              (portRef COUT (instanceRef w_ctr_2))))
+          (net iwcount_8
+            (joined
+              (portRef S0 (instanceRef w_ctr_4))
+              (portRef D (instanceRef FF_73))))
+          (net iwcount_9
+            (joined
+              (portRef S1 (instanceRef w_ctr_4))
+              (portRef D (instanceRef FF_72))))
+          (net co3_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_4))
+              (portRef COUT (instanceRef w_ctr_3))))
+          (net iwcount_10
+            (joined
+              (portRef S0 (instanceRef w_ctr_5))
+              (portRef D (instanceRef FF_71))))
+          (net iwcount_11
+            (joined
+              (portRef S1 (instanceRef w_ctr_5))
+              (portRef D (instanceRef FF_70))))
+          (net co4_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_5))
+              (portRef COUT (instanceRef w_ctr_4))))
+          (net iwcount_12
+            (joined
+              (portRef S0 (instanceRef w_ctr_6))
+              (portRef D (instanceRef FF_69))))
+          (net iwcount_13
+            (joined
+              (portRef S1 (instanceRef w_ctr_6))
+              (portRef D (instanceRef FF_68))))
+          (net co5_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_6))
+              (portRef COUT (instanceRef w_ctr_5))))
+          (net iwcount_14
+            (joined
+              (portRef S0 (instanceRef w_ctr_7))
+              (portRef D (instanceRef FF_67))))
+          (net co7_1
+            (joined
+              (portRef COUT (instanceRef w_ctr_7))))
+          (net co6_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_7))
+              (portRef COUT (instanceRef w_ctr_6))))
+          (net wcount_14
+            (joined
+              (portRef A0 (instanceRef w_ctr_7))
+              (portRef A (instanceRef XOR2_t0))
+              (portRef Q (instanceRef FF_67))
+              (portRef D (instanceRef FF_37))))
+          (net ircount_0
+            (joined
+              (portRef S0 (instanceRef r_ctr_0))
+              (portRef D (instanceRef FF_66))))
+          (net ircount_1
+            (joined
+              (portRef S1 (instanceRef r_ctr_0))
+              (portRef D (instanceRef FF_65))))
+          (net r_ctr_ci
+            (joined
+              (portRef CIN (instanceRef r_ctr_0))
+              (portRef COUT (instanceRef r_ctr_cia))))
+          (net rcount_0
+            (joined
+              (portRef A0 (instanceRef r_ctr_0))
+              (portRef Q (instanceRef FF_66))
+              (portRef D (instanceRef FF_36))))
+          (net rcount_1
+            (joined
+              (portRef A1 (instanceRef r_ctr_0))
+              (portRef Q (instanceRef FF_65))
+              (portRef D (instanceRef FF_35))))
+          (net ircount_2
+            (joined
+              (portRef S0 (instanceRef r_ctr_1))
+              (portRef D (instanceRef FF_64))))
+          (net ircount_3
+            (joined
+              (portRef S1 (instanceRef r_ctr_1))
+              (portRef D (instanceRef FF_63))))
+          (net co0_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_1))
+              (portRef COUT (instanceRef r_ctr_0))))
+          (net rcount_2
+            (joined
+              (portRef A0 (instanceRef r_ctr_1))
+              (portRef Q (instanceRef FF_64))
+              (portRef D (instanceRef FF_34))))
+          (net rcount_3
+            (joined
+              (portRef A1 (instanceRef r_ctr_1))
+              (portRef Q (instanceRef FF_63))
+              (portRef D (instanceRef FF_33))))
+          (net ircount_4
+            (joined
+              (portRef S0 (instanceRef r_ctr_2))
+              (portRef D (instanceRef FF_62))))
+          (net ircount_5
+            (joined
+              (portRef S1 (instanceRef r_ctr_2))
+              (portRef D (instanceRef FF_61))))
+          (net co1_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_2))
+              (portRef COUT (instanceRef r_ctr_1))))
+          (net rcount_4
+            (joined
+              (portRef A0 (instanceRef r_ctr_2))
+              (portRef Q (instanceRef FF_62))
+              (portRef D (instanceRef FF_32))))
+          (net rcount_5
+            (joined
+              (portRef A1 (instanceRef r_ctr_2))
+              (portRef Q (instanceRef FF_61))
+              (portRef D (instanceRef FF_31))))
+          (net ircount_6
+            (joined
+              (portRef S0 (instanceRef r_ctr_3))
+              (portRef D (instanceRef FF_60))))
+          (net ircount_7
+            (joined
+              (portRef S1 (instanceRef r_ctr_3))
+              (portRef D (instanceRef FF_59))))
+          (net co2_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_3))
+              (portRef COUT (instanceRef r_ctr_2))))
+          (net rcount_6
+            (joined
+              (portRef A0 (instanceRef r_ctr_3))
+              (portRef Q (instanceRef FF_60))
+              (portRef D (instanceRef FF_30))))
+          (net rcount_7
+            (joined
+              (portRef A1 (instanceRef r_ctr_3))
+              (portRef Q (instanceRef FF_59))
+              (portRef D (instanceRef FF_29))))
+          (net ircount_8
+            (joined
+              (portRef S0 (instanceRef r_ctr_4))
+              (portRef D (instanceRef FF_58))))
+          (net ircount_9
+            (joined
+              (portRef S1 (instanceRef r_ctr_4))
+              (portRef D (instanceRef FF_57))))
+          (net co3_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_4))
+              (portRef COUT (instanceRef r_ctr_3))))
+          (net rcount_8
+            (joined
+              (portRef A0 (instanceRef r_ctr_4))
+              (portRef Q (instanceRef FF_58))
+              (portRef D (instanceRef FF_28))))
+          (net rcount_9
+            (joined
+              (portRef A1 (instanceRef r_ctr_4))
+              (portRef Q (instanceRef FF_57))
+              (portRef D (instanceRef FF_27))))
+          (net ircount_10
+            (joined
+              (portRef S0 (instanceRef r_ctr_5))
+              (portRef D (instanceRef FF_56))))
+          (net ircount_11
+            (joined
+              (portRef S1 (instanceRef r_ctr_5))
+              (portRef D (instanceRef FF_55))))
+          (net co4_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_5))
+              (portRef COUT (instanceRef r_ctr_4))))
+          (net rcount_10
+            (joined
+              (portRef A0 (instanceRef r_ctr_5))
+              (portRef Q (instanceRef FF_56))
+              (portRef D (instanceRef FF_26))))
+          (net rcount_11
+            (joined
+              (portRef A1 (instanceRef r_ctr_5))
+              (portRef Q (instanceRef FF_55))
+              (portRef D (instanceRef FF_25))))
+          (net ircount_12
+            (joined
+              (portRef S0 (instanceRef r_ctr_6))
+              (portRef D (instanceRef FF_54))))
+          (net ircount_13
+            (joined
+              (portRef S1 (instanceRef r_ctr_6))
+              (portRef D (instanceRef FF_53))))
+          (net co5_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_6))
+              (portRef COUT (instanceRef r_ctr_5))))
+          (net rcount_12
+            (joined
+              (portRef A0 (instanceRef r_ctr_6))
+              (portRef Q (instanceRef FF_54))
+              (portRef D (instanceRef FF_24))))
+          (net rcount_13
+            (joined
+              (portRef A1 (instanceRef r_ctr_6))
+              (portRef Q (instanceRef FF_53))
+              (portRef D (instanceRef FF_23))))
+          (net ircount_14
+            (joined
+              (portRef S0 (instanceRef r_ctr_7))
+              (portRef D (instanceRef FF_52))))
+          (net co7_2
+            (joined
+              (portRef COUT (instanceRef r_ctr_7))))
+          (net co6_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_7))
+              (portRef COUT (instanceRef r_ctr_6))))
+          (net rcount_14
+            (joined
+              (portRef A0 (instanceRef r_ctr_7))
+              (portRef Q (instanceRef FF_52))
+              (portRef D (instanceRef FF_22))))
+          (net mdout1_7_0
+            (joined
+              (portRef D7 (instanceRef mux_35))
+              (portRef DOB0 (instanceRef pdp_ram_7_0_3))))
+          (net mdout1_6_0
+            (joined
+              (portRef D6 (instanceRef mux_35))
+              (portRef DOB0 (instanceRef pdp_ram_6_0_7))))
+          (net mdout1_5_0
+            (joined
+              (portRef D5 (instanceRef mux_35))
+              (portRef DOB0 (instanceRef pdp_ram_5_0_11))))
+          (net mdout1_4_0
+            (joined
+              (portRef D4 (instanceRef mux_35))
+              (portRef DOB0 (instanceRef pdp_ram_4_0_15))))
+          (net mdout1_3_0
+            (joined
+              (portRef D3 (instanceRef mux_35))
+              (portRef DOB0 (instanceRef pdp_ram_3_0_19))))
+          (net mdout1_2_0
+            (joined
+              (portRef D2 (instanceRef mux_35))
+              (portRef DOB0 (instanceRef pdp_ram_2_0_23))))
+          (net mdout1_1_0
+            (joined
+              (portRef D1 (instanceRef mux_35))
+              (portRef DOB0 (instanceRef pdp_ram_1_0_27))))
+          (net mdout1_0_0
+            (joined
+              (portRef D0 (instanceRef mux_35))
+              (portRef DOB0 (instanceRef pdp_ram_0_0_31))))
+          (net mdout1_7_1
+            (joined
+              (portRef D7 (instanceRef mux_34))
+              (portRef DOB1 (instanceRef pdp_ram_7_0_3))))
+          (net mdout1_6_1
+            (joined
+              (portRef D6 (instanceRef mux_34))
+              (portRef DOB1 (instanceRef pdp_ram_6_0_7))))
+          (net mdout1_5_1
+            (joined
+              (portRef D5 (instanceRef mux_34))
+              (portRef DOB1 (instanceRef pdp_ram_5_0_11))))
+          (net mdout1_4_1
+            (joined
+              (portRef D4 (instanceRef mux_34))
+              (portRef DOB1 (instanceRef pdp_ram_4_0_15))))
+          (net mdout1_3_1
+            (joined
+              (portRef D3 (instanceRef mux_34))
+              (portRef DOB1 (instanceRef pdp_ram_3_0_19))))
+          (net mdout1_2_1
+            (joined
+              (portRef D2 (instanceRef mux_34))
+              (portRef DOB1 (instanceRef pdp_ram_2_0_23))))
+          (net mdout1_1_1
+            (joined
+              (portRef D1 (instanceRef mux_34))
+              (portRef DOB1 (instanceRef pdp_ram_1_0_27))))
+          (net mdout1_0_1
+            (joined
+              (portRef D0 (instanceRef mux_34))
+              (portRef DOB1 (instanceRef pdp_ram_0_0_31))))
+          (net mdout1_7_2
+            (joined
+              (portRef D7 (instanceRef mux_33))
+              (portRef DOB2 (instanceRef pdp_ram_7_0_3))))
+          (net mdout1_6_2
+            (joined
+              (portRef D6 (instanceRef mux_33))
+              (portRef DOB2 (instanceRef pdp_ram_6_0_7))))
+          (net mdout1_5_2
+            (joined
+              (portRef D5 (instanceRef mux_33))
+              (portRef DOB2 (instanceRef pdp_ram_5_0_11))))
+          (net mdout1_4_2
+            (joined
+              (portRef D4 (instanceRef mux_33))
+              (portRef DOB2 (instanceRef pdp_ram_4_0_15))))
+          (net mdout1_3_2
+            (joined
+              (portRef D3 (instanceRef mux_33))
+              (portRef DOB2 (instanceRef pdp_ram_3_0_19))))
+          (net mdout1_2_2
+            (joined
+              (portRef D2 (instanceRef mux_33))
+              (portRef DOB2 (instanceRef pdp_ram_2_0_23))))
+          (net mdout1_1_2
+            (joined
+              (portRef D1 (instanceRef mux_33))
+              (portRef DOB2 (instanceRef pdp_ram_1_0_27))))
+          (net mdout1_0_2
+            (joined
+              (portRef D0 (instanceRef mux_33))
+              (portRef DOB2 (instanceRef pdp_ram_0_0_31))))
+          (net mdout1_7_3
+            (joined
+              (portRef D7 (instanceRef mux_32))
+              (portRef DOB3 (instanceRef pdp_ram_7_0_3))))
+          (net mdout1_6_3
+            (joined
+              (portRef D6 (instanceRef mux_32))
+              (portRef DOB3 (instanceRef pdp_ram_6_0_7))))
+          (net mdout1_5_3
+            (joined
+              (portRef D5 (instanceRef mux_32))
+              (portRef DOB3 (instanceRef pdp_ram_5_0_11))))
+          (net mdout1_4_3
+            (joined
+              (portRef D4 (instanceRef mux_32))
+              (portRef DOB3 (instanceRef pdp_ram_4_0_15))))
+          (net mdout1_3_3
+            (joined
+              (portRef D3 (instanceRef mux_32))
+              (portRef DOB3 (instanceRef pdp_ram_3_0_19))))
+          (net mdout1_2_3
+            (joined
+              (portRef D2 (instanceRef mux_32))
+              (portRef DOB3 (instanceRef pdp_ram_2_0_23))))
+          (net mdout1_1_3
+            (joined
+              (portRef D1 (instanceRef mux_32))
+              (portRef DOB3 (instanceRef pdp_ram_1_0_27))))
+          (net mdout1_0_3
+            (joined
+              (portRef D0 (instanceRef mux_32))
+              (portRef DOB3 (instanceRef pdp_ram_0_0_31))))
+          (net mdout1_7_4
+            (joined
+              (portRef D7 (instanceRef mux_31))
+              (portRef DOB4 (instanceRef pdp_ram_7_0_3))))
+          (net mdout1_6_4
+            (joined
+              (portRef D6 (instanceRef mux_31))
+              (portRef DOB4 (instanceRef pdp_ram_6_0_7))))
+          (net mdout1_5_4
+            (joined
+              (portRef D5 (instanceRef mux_31))
+              (portRef DOB4 (instanceRef pdp_ram_5_0_11))))
+          (net mdout1_4_4
+            (joined
+              (portRef D4 (instanceRef mux_31))
+              (portRef DOB4 (instanceRef pdp_ram_4_0_15))))
+          (net mdout1_3_4
+            (joined
+              (portRef D3 (instanceRef mux_31))
+              (portRef DOB4 (instanceRef pdp_ram_3_0_19))))
+          (net mdout1_2_4
+            (joined
+              (portRef D2 (instanceRef mux_31))
+              (portRef DOB4 (instanceRef pdp_ram_2_0_23))))
+          (net mdout1_1_4
+            (joined
+              (portRef D1 (instanceRef mux_31))
+              (portRef DOB4 (instanceRef pdp_ram_1_0_27))))
+          (net mdout1_0_4
+            (joined
+              (portRef D0 (instanceRef mux_31))
+              (portRef DOB4 (instanceRef pdp_ram_0_0_31))))
+          (net mdout1_7_5
+            (joined
+              (portRef D7 (instanceRef mux_30))
+              (portRef DOB5 (instanceRef pdp_ram_7_0_3))))
+          (net mdout1_6_5
+            (joined
+              (portRef D6 (instanceRef mux_30))
+              (portRef DOB5 (instanceRef pdp_ram_6_0_7))))
+          (net mdout1_5_5
+            (joined
+              (portRef D5 (instanceRef mux_30))
+              (portRef DOB5 (instanceRef pdp_ram_5_0_11))))
+          (net mdout1_4_5
+            (joined
+              (portRef D4 (instanceRef mux_30))
+              (portRef DOB5 (instanceRef pdp_ram_4_0_15))))
+          (net mdout1_3_5
+            (joined
+              (portRef D3 (instanceRef mux_30))
+              (portRef DOB5 (instanceRef pdp_ram_3_0_19))))
+          (net mdout1_2_5
+            (joined
+              (portRef D2 (instanceRef mux_30))
+              (portRef DOB5 (instanceRef pdp_ram_2_0_23))))
+          (net mdout1_1_5
+            (joined
+              (portRef D1 (instanceRef mux_30))
+              (portRef DOB5 (instanceRef pdp_ram_1_0_27))))
+          (net mdout1_0_5
+            (joined
+              (portRef D0 (instanceRef mux_30))
+              (portRef DOB5 (instanceRef pdp_ram_0_0_31))))
+          (net mdout1_7_6
+            (joined
+              (portRef D7 (instanceRef mux_29))
+              (portRef DOB6 (instanceRef pdp_ram_7_0_3))))
+          (net mdout1_6_6
+            (joined
+              (portRef D6 (instanceRef mux_29))
+              (portRef DOB6 (instanceRef pdp_ram_6_0_7))))
+          (net mdout1_5_6
+            (joined
+              (portRef D5 (instanceRef mux_29))
+              (portRef DOB6 (instanceRef pdp_ram_5_0_11))))
+          (net mdout1_4_6
+            (joined
+              (portRef D4 (instanceRef mux_29))
+              (portRef DOB6 (instanceRef pdp_ram_4_0_15))))
+          (net mdout1_3_6
+            (joined
+              (portRef D3 (instanceRef mux_29))
+              (portRef DOB6 (instanceRef pdp_ram_3_0_19))))
+          (net mdout1_2_6
+            (joined
+              (portRef D2 (instanceRef mux_29))
+              (portRef DOB6 (instanceRef pdp_ram_2_0_23))))
+          (net mdout1_1_6
+            (joined
+              (portRef D1 (instanceRef mux_29))
+              (portRef DOB6 (instanceRef pdp_ram_1_0_27))))
+          (net mdout1_0_6
+            (joined
+              (portRef D0 (instanceRef mux_29))
+              (portRef DOB6 (instanceRef pdp_ram_0_0_31))))
+          (net mdout1_7_7
+            (joined
+              (portRef D7 (instanceRef mux_28))
+              (portRef DOB7 (instanceRef pdp_ram_7_0_3))))
+          (net mdout1_6_7
+            (joined
+              (portRef D6 (instanceRef mux_28))
+              (portRef DOB7 (instanceRef pdp_ram_6_0_7))))
+          (net mdout1_5_7
+            (joined
+              (portRef D5 (instanceRef mux_28))
+              (portRef DOB7 (instanceRef pdp_ram_5_0_11))))
+          (net mdout1_4_7
+            (joined
+              (portRef D4 (instanceRef mux_28))
+              (portRef DOB7 (instanceRef pdp_ram_4_0_15))))
+          (net mdout1_3_7
+            (joined
+              (portRef D3 (instanceRef mux_28))
+              (portRef DOB7 (instanceRef pdp_ram_3_0_19))))
+          (net mdout1_2_7
+            (joined
+              (portRef D2 (instanceRef mux_28))
+              (portRef DOB7 (instanceRef pdp_ram_2_0_23))))
+          (net mdout1_1_7
+            (joined
+              (portRef D1 (instanceRef mux_28))
+              (portRef DOB7 (instanceRef pdp_ram_1_0_27))))
+          (net mdout1_0_7
+            (joined
+              (portRef D0 (instanceRef mux_28))
+              (portRef DOB7 (instanceRef pdp_ram_0_0_31))))
+          (net mdout1_7_8
+            (joined
+              (portRef D7 (instanceRef mux_27))
+              (portRef DOB8 (instanceRef pdp_ram_7_0_3))))
+          (net mdout1_6_8
+            (joined
+              (portRef D6 (instanceRef mux_27))
+              (portRef DOB8 (instanceRef pdp_ram_6_0_7))))
+          (net mdout1_5_8
+            (joined
+              (portRef D5 (instanceRef mux_27))
+              (portRef DOB8 (instanceRef pdp_ram_5_0_11))))
+          (net mdout1_4_8
+            (joined
+              (portRef D4 (instanceRef mux_27))
+              (portRef DOB8 (instanceRef pdp_ram_4_0_15))))
+          (net mdout1_3_8
+            (joined
+              (portRef D3 (instanceRef mux_27))
+              (portRef DOB8 (instanceRef pdp_ram_3_0_19))))
+          (net mdout1_2_8
+            (joined
+              (portRef D2 (instanceRef mux_27))
+              (portRef DOB8 (instanceRef pdp_ram_2_0_23))))
+          (net mdout1_1_8
+            (joined
+              (portRef D1 (instanceRef mux_27))
+              (portRef DOB8 (instanceRef pdp_ram_1_0_27))))
+          (net mdout1_0_8
+            (joined
+              (portRef D0 (instanceRef mux_27))
+              (portRef DOB8 (instanceRef pdp_ram_0_0_31))))
+          (net mdout1_7_9
+            (joined
+              (portRef D7 (instanceRef mux_26))
+              (portRef DOB0 (instanceRef pdp_ram_7_1_2))))
+          (net mdout1_6_9
+            (joined
+              (portRef D6 (instanceRef mux_26))
+              (portRef DOB0 (instanceRef pdp_ram_6_1_6))))
+          (net mdout1_5_9
+            (joined
+              (portRef D5 (instanceRef mux_26))
+              (portRef DOB0 (instanceRef pdp_ram_5_1_10))))
+          (net mdout1_4_9
+            (joined
+              (portRef D4 (instanceRef mux_26))
+              (portRef DOB0 (instanceRef pdp_ram_4_1_14))))
+          (net mdout1_3_9
+            (joined
+              (portRef D3 (instanceRef mux_26))
+              (portRef DOB0 (instanceRef pdp_ram_3_1_18))))
+          (net mdout1_2_9
+            (joined
+              (portRef D2 (instanceRef mux_26))
+              (portRef DOB0 (instanceRef pdp_ram_2_1_22))))
+          (net mdout1_1_9
+            (joined
+              (portRef D1 (instanceRef mux_26))
+              (portRef DOB0 (instanceRef pdp_ram_1_1_26))))
+          (net mdout1_0_9
+            (joined
+              (portRef D0 (instanceRef mux_26))
+              (portRef DOB0 (instanceRef pdp_ram_0_1_30))))
+          (net mdout1_7_10
+            (joined
+              (portRef D7 (instanceRef mux_25))
+              (portRef DOB1 (instanceRef pdp_ram_7_1_2))))
+          (net mdout1_6_10
+            (joined
+              (portRef D6 (instanceRef mux_25))
+              (portRef DOB1 (instanceRef pdp_ram_6_1_6))))
+          (net mdout1_5_10
+            (joined
+              (portRef D5 (instanceRef mux_25))
+              (portRef DOB1 (instanceRef pdp_ram_5_1_10))))
+          (net mdout1_4_10
+            (joined
+              (portRef D4 (instanceRef mux_25))
+              (portRef DOB1 (instanceRef pdp_ram_4_1_14))))
+          (net mdout1_3_10
+            (joined
+              (portRef D3 (instanceRef mux_25))
+              (portRef DOB1 (instanceRef pdp_ram_3_1_18))))
+          (net mdout1_2_10
+            (joined
+              (portRef D2 (instanceRef mux_25))
+              (portRef DOB1 (instanceRef pdp_ram_2_1_22))))
+          (net mdout1_1_10
+            (joined
+              (portRef D1 (instanceRef mux_25))
+              (portRef DOB1 (instanceRef pdp_ram_1_1_26))))
+          (net mdout1_0_10
+            (joined
+              (portRef D0 (instanceRef mux_25))
+              (portRef DOB1 (instanceRef pdp_ram_0_1_30))))
+          (net mdout1_7_11
+            (joined
+              (portRef D7 (instanceRef mux_24))
+              (portRef DOB2 (instanceRef pdp_ram_7_1_2))))
+          (net mdout1_6_11
+            (joined
+              (portRef D6 (instanceRef mux_24))
+              (portRef DOB2 (instanceRef pdp_ram_6_1_6))))
+          (net mdout1_5_11
+            (joined
+              (portRef D5 (instanceRef mux_24))
+              (portRef DOB2 (instanceRef pdp_ram_5_1_10))))
+          (net mdout1_4_11
+            (joined
+              (portRef D4 (instanceRef mux_24))
+              (portRef DOB2 (instanceRef pdp_ram_4_1_14))))
+          (net mdout1_3_11
+            (joined
+              (portRef D3 (instanceRef mux_24))
+              (portRef DOB2 (instanceRef pdp_ram_3_1_18))))
+          (net mdout1_2_11
+            (joined
+              (portRef D2 (instanceRef mux_24))
+              (portRef DOB2 (instanceRef pdp_ram_2_1_22))))
+          (net mdout1_1_11
+            (joined
+              (portRef D1 (instanceRef mux_24))
+              (portRef DOB2 (instanceRef pdp_ram_1_1_26))))
+          (net mdout1_0_11
+            (joined
+              (portRef D0 (instanceRef mux_24))
+              (portRef DOB2 (instanceRef pdp_ram_0_1_30))))
+          (net mdout1_7_12
+            (joined
+              (portRef D7 (instanceRef mux_23))
+              (portRef DOB3 (instanceRef pdp_ram_7_1_2))))
+          (net mdout1_6_12
+            (joined
+              (portRef D6 (instanceRef mux_23))
+              (portRef DOB3 (instanceRef pdp_ram_6_1_6))))
+          (net mdout1_5_12
+            (joined
+              (portRef D5 (instanceRef mux_23))
+              (portRef DOB3 (instanceRef pdp_ram_5_1_10))))
+          (net mdout1_4_12
+            (joined
+              (portRef D4 (instanceRef mux_23))
+              (portRef DOB3 (instanceRef pdp_ram_4_1_14))))
+          (net mdout1_3_12
+            (joined
+              (portRef D3 (instanceRef mux_23))
+              (portRef DOB3 (instanceRef pdp_ram_3_1_18))))
+          (net mdout1_2_12
+            (joined
+              (portRef D2 (instanceRef mux_23))
+              (portRef DOB3 (instanceRef pdp_ram_2_1_22))))
+          (net mdout1_1_12
+            (joined
+              (portRef D1 (instanceRef mux_23))
+              (portRef DOB3 (instanceRef pdp_ram_1_1_26))))
+          (net mdout1_0_12
+            (joined
+              (portRef D0 (instanceRef mux_23))
+              (portRef DOB3 (instanceRef pdp_ram_0_1_30))))
+          (net mdout1_7_13
+            (joined
+              (portRef D7 (instanceRef mux_22))
+              (portRef DOB4 (instanceRef pdp_ram_7_1_2))))
+          (net mdout1_6_13
+            (joined
+              (portRef D6 (instanceRef mux_22))
+              (portRef DOB4 (instanceRef pdp_ram_6_1_6))))
+          (net mdout1_5_13
+            (joined
+              (portRef D5 (instanceRef mux_22))
+              (portRef DOB4 (instanceRef pdp_ram_5_1_10))))
+          (net mdout1_4_13
+            (joined
+              (portRef D4 (instanceRef mux_22))
+              (portRef DOB4 (instanceRef pdp_ram_4_1_14))))
+          (net mdout1_3_13
+            (joined
+              (portRef D3 (instanceRef mux_22))
+              (portRef DOB4 (instanceRef pdp_ram_3_1_18))))
+          (net mdout1_2_13
+            (joined
+              (portRef D2 (instanceRef mux_22))
+              (portRef DOB4 (instanceRef pdp_ram_2_1_22))))
+          (net mdout1_1_13
+            (joined
+              (portRef D1 (instanceRef mux_22))
+              (portRef DOB4 (instanceRef pdp_ram_1_1_26))))
+          (net mdout1_0_13
+            (joined
+              (portRef D0 (instanceRef mux_22))
+              (portRef DOB4 (instanceRef pdp_ram_0_1_30))))
+          (net mdout1_7_14
+            (joined
+              (portRef D7 (instanceRef mux_21))
+              (portRef DOB5 (instanceRef pdp_ram_7_1_2))))
+          (net mdout1_6_14
+            (joined
+              (portRef D6 (instanceRef mux_21))
+              (portRef DOB5 (instanceRef pdp_ram_6_1_6))))
+          (net mdout1_5_14
+            (joined
+              (portRef D5 (instanceRef mux_21))
+              (portRef DOB5 (instanceRef pdp_ram_5_1_10))))
+          (net mdout1_4_14
+            (joined
+              (portRef D4 (instanceRef mux_21))
+              (portRef DOB5 (instanceRef pdp_ram_4_1_14))))
+          (net mdout1_3_14
+            (joined
+              (portRef D3 (instanceRef mux_21))
+              (portRef DOB5 (instanceRef pdp_ram_3_1_18))))
+          (net mdout1_2_14
+            (joined
+              (portRef D2 (instanceRef mux_21))
+              (portRef DOB5 (instanceRef pdp_ram_2_1_22))))
+          (net mdout1_1_14
+            (joined
+              (portRef D1 (instanceRef mux_21))
+              (portRef DOB5 (instanceRef pdp_ram_1_1_26))))
+          (net mdout1_0_14
+            (joined
+              (portRef D0 (instanceRef mux_21))
+              (portRef DOB5 (instanceRef pdp_ram_0_1_30))))
+          (net mdout1_7_15
+            (joined
+              (portRef D7 (instanceRef mux_20))
+              (portRef DOB6 (instanceRef pdp_ram_7_1_2))))
+          (net mdout1_6_15
+            (joined
+              (portRef D6 (instanceRef mux_20))
+              (portRef DOB6 (instanceRef pdp_ram_6_1_6))))
+          (net mdout1_5_15
+            (joined
+              (portRef D5 (instanceRef mux_20))
+              (portRef DOB6 (instanceRef pdp_ram_5_1_10))))
+          (net mdout1_4_15
+            (joined
+              (portRef D4 (instanceRef mux_20))
+              (portRef DOB6 (instanceRef pdp_ram_4_1_14))))
+          (net mdout1_3_15
+            (joined
+              (portRef D3 (instanceRef mux_20))
+              (portRef DOB6 (instanceRef pdp_ram_3_1_18))))
+          (net mdout1_2_15
+            (joined
+              (portRef D2 (instanceRef mux_20))
+              (portRef DOB6 (instanceRef pdp_ram_2_1_22))))
+          (net mdout1_1_15
+            (joined
+              (portRef D1 (instanceRef mux_20))
+              (portRef DOB6 (instanceRef pdp_ram_1_1_26))))
+          (net mdout1_0_15
+            (joined
+              (portRef D0 (instanceRef mux_20))
+              (portRef DOB6 (instanceRef pdp_ram_0_1_30))))
+          (net mdout1_7_16
+            (joined
+              (portRef D7 (instanceRef mux_19))
+              (portRef DOB7 (instanceRef pdp_ram_7_1_2))))
+          (net mdout1_6_16
+            (joined
+              (portRef D6 (instanceRef mux_19))
+              (portRef DOB7 (instanceRef pdp_ram_6_1_6))))
+          (net mdout1_5_16
+            (joined
+              (portRef D5 (instanceRef mux_19))
+              (portRef DOB7 (instanceRef pdp_ram_5_1_10))))
+          (net mdout1_4_16
+            (joined
+              (portRef D4 (instanceRef mux_19))
+              (portRef DOB7 (instanceRef pdp_ram_4_1_14))))
+          (net mdout1_3_16
+            (joined
+              (portRef D3 (instanceRef mux_19))
+              (portRef DOB7 (instanceRef pdp_ram_3_1_18))))
+          (net mdout1_2_16
+            (joined
+              (portRef D2 (instanceRef mux_19))
+              (portRef DOB7 (instanceRef pdp_ram_2_1_22))))
+          (net mdout1_1_16
+            (joined
+              (portRef D1 (instanceRef mux_19))
+              (portRef DOB7 (instanceRef pdp_ram_1_1_26))))
+          (net mdout1_0_16
+            (joined
+              (portRef D0 (instanceRef mux_19))
+              (portRef DOB7 (instanceRef pdp_ram_0_1_30))))
+          (net mdout1_7_17
+            (joined
+              (portRef D7 (instanceRef mux_18))
+              (portRef DOB8 (instanceRef pdp_ram_7_1_2))))
+          (net mdout1_6_17
+            (joined
+              (portRef D6 (instanceRef mux_18))
+              (portRef DOB8 (instanceRef pdp_ram_6_1_6))))
+          (net mdout1_5_17
+            (joined
+              (portRef D5 (instanceRef mux_18))
+              (portRef DOB8 (instanceRef pdp_ram_5_1_10))))
+          (net mdout1_4_17
+            (joined
+              (portRef D4 (instanceRef mux_18))
+              (portRef DOB8 (instanceRef pdp_ram_4_1_14))))
+          (net mdout1_3_17
+            (joined
+              (portRef D3 (instanceRef mux_18))
+              (portRef DOB8 (instanceRef pdp_ram_3_1_18))))
+          (net mdout1_2_17
+            (joined
+              (portRef D2 (instanceRef mux_18))
+              (portRef DOB8 (instanceRef pdp_ram_2_1_22))))
+          (net mdout1_1_17
+            (joined
+              (portRef D1 (instanceRef mux_18))
+              (portRef DOB8 (instanceRef pdp_ram_1_1_26))))
+          (net mdout1_0_17
+            (joined
+              (portRef D0 (instanceRef mux_18))
+              (portRef DOB8 (instanceRef pdp_ram_0_1_30))))
+          (net mdout1_7_18
+            (joined
+              (portRef D7 (instanceRef mux_17))
+              (portRef DOB0 (instanceRef pdp_ram_7_2_1))))
+          (net mdout1_6_18
+            (joined
+              (portRef D6 (instanceRef mux_17))
+              (portRef DOB0 (instanceRef pdp_ram_6_2_5))))
+          (net mdout1_5_18
+            (joined
+              (portRef D5 (instanceRef mux_17))
+              (portRef DOB0 (instanceRef pdp_ram_5_2_9))))
+          (net mdout1_4_18
+            (joined
+              (portRef D4 (instanceRef mux_17))
+              (portRef DOB0 (instanceRef pdp_ram_4_2_13))))
+          (net mdout1_3_18
+            (joined
+              (portRef D3 (instanceRef mux_17))
+              (portRef DOB0 (instanceRef pdp_ram_3_2_17))))
+          (net mdout1_2_18
+            (joined
+              (portRef D2 (instanceRef mux_17))
+              (portRef DOB0 (instanceRef pdp_ram_2_2_21))))
+          (net mdout1_1_18
+            (joined
+              (portRef D1 (instanceRef mux_17))
+              (portRef DOB0 (instanceRef pdp_ram_1_2_25))))
+          (net mdout1_0_18
+            (joined
+              (portRef D0 (instanceRef mux_17))
+              (portRef DOB0 (instanceRef pdp_ram_0_2_29))))
+          (net mdout1_7_19
+            (joined
+              (portRef D7 (instanceRef mux_16))
+              (portRef DOB1 (instanceRef pdp_ram_7_2_1))))
+          (net mdout1_6_19
+            (joined
+              (portRef D6 (instanceRef mux_16))
+              (portRef DOB1 (instanceRef pdp_ram_6_2_5))))
+          (net mdout1_5_19
+            (joined
+              (portRef D5 (instanceRef mux_16))
+              (portRef DOB1 (instanceRef pdp_ram_5_2_9))))
+          (net mdout1_4_19
+            (joined
+              (portRef D4 (instanceRef mux_16))
+              (portRef DOB1 (instanceRef pdp_ram_4_2_13))))
+          (net mdout1_3_19
+            (joined
+              (portRef D3 (instanceRef mux_16))
+              (portRef DOB1 (instanceRef pdp_ram_3_2_17))))
+          (net mdout1_2_19
+            (joined
+              (portRef D2 (instanceRef mux_16))
+              (portRef DOB1 (instanceRef pdp_ram_2_2_21))))
+          (net mdout1_1_19
+            (joined
+              (portRef D1 (instanceRef mux_16))
+              (portRef DOB1 (instanceRef pdp_ram_1_2_25))))
+          (net mdout1_0_19
+            (joined
+              (portRef D0 (instanceRef mux_16))
+              (portRef DOB1 (instanceRef pdp_ram_0_2_29))))
+          (net mdout1_7_20
+            (joined
+              (portRef D7 (instanceRef mux_15))
+              (portRef DOB2 (instanceRef pdp_ram_7_2_1))))
+          (net mdout1_6_20
+            (joined
+              (portRef D6 (instanceRef mux_15))
+              (portRef DOB2 (instanceRef pdp_ram_6_2_5))))
+          (net mdout1_5_20
+            (joined
+              (portRef D5 (instanceRef mux_15))
+              (portRef DOB2 (instanceRef pdp_ram_5_2_9))))
+          (net mdout1_4_20
+            (joined
+              (portRef D4 (instanceRef mux_15))
+              (portRef DOB2 (instanceRef pdp_ram_4_2_13))))
+          (net mdout1_3_20
+            (joined
+              (portRef D3 (instanceRef mux_15))
+              (portRef DOB2 (instanceRef pdp_ram_3_2_17))))
+          (net mdout1_2_20
+            (joined
+              (portRef D2 (instanceRef mux_15))
+              (portRef DOB2 (instanceRef pdp_ram_2_2_21))))
+          (net mdout1_1_20
+            (joined
+              (portRef D1 (instanceRef mux_15))
+              (portRef DOB2 (instanceRef pdp_ram_1_2_25))))
+          (net mdout1_0_20
+            (joined
+              (portRef D0 (instanceRef mux_15))
+              (portRef DOB2 (instanceRef pdp_ram_0_2_29))))
+          (net mdout1_7_21
+            (joined
+              (portRef D7 (instanceRef mux_14))
+              (portRef DOB3 (instanceRef pdp_ram_7_2_1))))
+          (net mdout1_6_21
+            (joined
+              (portRef D6 (instanceRef mux_14))
+              (portRef DOB3 (instanceRef pdp_ram_6_2_5))))
+          (net mdout1_5_21
+            (joined
+              (portRef D5 (instanceRef mux_14))
+              (portRef DOB3 (instanceRef pdp_ram_5_2_9))))
+          (net mdout1_4_21
+            (joined
+              (portRef D4 (instanceRef mux_14))
+              (portRef DOB3 (instanceRef pdp_ram_4_2_13))))
+          (net mdout1_3_21
+            (joined
+              (portRef D3 (instanceRef mux_14))
+              (portRef DOB3 (instanceRef pdp_ram_3_2_17))))
+          (net mdout1_2_21
+            (joined
+              (portRef D2 (instanceRef mux_14))
+              (portRef DOB3 (instanceRef pdp_ram_2_2_21))))
+          (net mdout1_1_21
+            (joined
+              (portRef D1 (instanceRef mux_14))
+              (portRef DOB3 (instanceRef pdp_ram_1_2_25))))
+          (net mdout1_0_21
+            (joined
+              (portRef D0 (instanceRef mux_14))
+              (portRef DOB3 (instanceRef pdp_ram_0_2_29))))
+          (net mdout1_7_22
+            (joined
+              (portRef D7 (instanceRef mux_13))
+              (portRef DOB4 (instanceRef pdp_ram_7_2_1))))
+          (net mdout1_6_22
+            (joined
+              (portRef D6 (instanceRef mux_13))
+              (portRef DOB4 (instanceRef pdp_ram_6_2_5))))
+          (net mdout1_5_22
+            (joined
+              (portRef D5 (instanceRef mux_13))
+              (portRef DOB4 (instanceRef pdp_ram_5_2_9))))
+          (net mdout1_4_22
+            (joined
+              (portRef D4 (instanceRef mux_13))
+              (portRef DOB4 (instanceRef pdp_ram_4_2_13))))
+          (net mdout1_3_22
+            (joined
+              (portRef D3 (instanceRef mux_13))
+              (portRef DOB4 (instanceRef pdp_ram_3_2_17))))
+          (net mdout1_2_22
+            (joined
+              (portRef D2 (instanceRef mux_13))
+              (portRef DOB4 (instanceRef pdp_ram_2_2_21))))
+          (net mdout1_1_22
+            (joined
+              (portRef D1 (instanceRef mux_13))
+              (portRef DOB4 (instanceRef pdp_ram_1_2_25))))
+          (net mdout1_0_22
+            (joined
+              (portRef D0 (instanceRef mux_13))
+              (portRef DOB4 (instanceRef pdp_ram_0_2_29))))
+          (net mdout1_7_23
+            (joined
+              (portRef D7 (instanceRef mux_12))
+              (portRef DOB5 (instanceRef pdp_ram_7_2_1))))
+          (net mdout1_6_23
+            (joined
+              (portRef D6 (instanceRef mux_12))
+              (portRef DOB5 (instanceRef pdp_ram_6_2_5))))
+          (net mdout1_5_23
+            (joined
+              (portRef D5 (instanceRef mux_12))
+              (portRef DOB5 (instanceRef pdp_ram_5_2_9))))
+          (net mdout1_4_23
+            (joined
+              (portRef D4 (instanceRef mux_12))
+              (portRef DOB5 (instanceRef pdp_ram_4_2_13))))
+          (net mdout1_3_23
+            (joined
+              (portRef D3 (instanceRef mux_12))
+              (portRef DOB5 (instanceRef pdp_ram_3_2_17))))
+          (net mdout1_2_23
+            (joined
+              (portRef D2 (instanceRef mux_12))
+              (portRef DOB5 (instanceRef pdp_ram_2_2_21))))
+          (net mdout1_1_23
+            (joined
+              (portRef D1 (instanceRef mux_12))
+              (portRef DOB5 (instanceRef pdp_ram_1_2_25))))
+          (net mdout1_0_23
+            (joined
+              (portRef D0 (instanceRef mux_12))
+              (portRef DOB5 (instanceRef pdp_ram_0_2_29))))
+          (net mdout1_7_24
+            (joined
+              (portRef D7 (instanceRef mux_11))
+              (portRef DOB6 (instanceRef pdp_ram_7_2_1))))
+          (net mdout1_6_24
+            (joined
+              (portRef D6 (instanceRef mux_11))
+              (portRef DOB6 (instanceRef pdp_ram_6_2_5))))
+          (net mdout1_5_24
+            (joined
+              (portRef D5 (instanceRef mux_11))
+              (portRef DOB6 (instanceRef pdp_ram_5_2_9))))
+          (net mdout1_4_24
+            (joined
+              (portRef D4 (instanceRef mux_11))
+              (portRef DOB6 (instanceRef pdp_ram_4_2_13))))
+          (net mdout1_3_24
+            (joined
+              (portRef D3 (instanceRef mux_11))
+              (portRef DOB6 (instanceRef pdp_ram_3_2_17))))
+          (net mdout1_2_24
+            (joined
+              (portRef D2 (instanceRef mux_11))
+              (portRef DOB6 (instanceRef pdp_ram_2_2_21))))
+          (net mdout1_1_24
+            (joined
+              (portRef D1 (instanceRef mux_11))
+              (portRef DOB6 (instanceRef pdp_ram_1_2_25))))
+          (net mdout1_0_24
+            (joined
+              (portRef D0 (instanceRef mux_11))
+              (portRef DOB6 (instanceRef pdp_ram_0_2_29))))
+          (net mdout1_7_25
+            (joined
+              (portRef D7 (instanceRef mux_10))
+              (portRef DOB7 (instanceRef pdp_ram_7_2_1))))
+          (net mdout1_6_25
+            (joined
+              (portRef D6 (instanceRef mux_10))
+              (portRef DOB7 (instanceRef pdp_ram_6_2_5))))
+          (net mdout1_5_25
+            (joined
+              (portRef D5 (instanceRef mux_10))
+              (portRef DOB7 (instanceRef pdp_ram_5_2_9))))
+          (net mdout1_4_25
+            (joined
+              (portRef D4 (instanceRef mux_10))
+              (portRef DOB7 (instanceRef pdp_ram_4_2_13))))
+          (net mdout1_3_25
+            (joined
+              (portRef D3 (instanceRef mux_10))
+              (portRef DOB7 (instanceRef pdp_ram_3_2_17))))
+          (net mdout1_2_25
+            (joined
+              (portRef D2 (instanceRef mux_10))
+              (portRef DOB7 (instanceRef pdp_ram_2_2_21))))
+          (net mdout1_1_25
+            (joined
+              (portRef D1 (instanceRef mux_10))
+              (portRef DOB7 (instanceRef pdp_ram_1_2_25))))
+          (net mdout1_0_25
+            (joined
+              (portRef D0 (instanceRef mux_10))
+              (portRef DOB7 (instanceRef pdp_ram_0_2_29))))
+          (net mdout1_7_26
+            (joined
+              (portRef D7 (instanceRef mux_9))
+              (portRef DOB8 (instanceRef pdp_ram_7_2_1))))
+          (net mdout1_6_26
+            (joined
+              (portRef D6 (instanceRef mux_9))
+              (portRef DOB8 (instanceRef pdp_ram_6_2_5))))
+          (net mdout1_5_26
+            (joined
+              (portRef D5 (instanceRef mux_9))
+              (portRef DOB8 (instanceRef pdp_ram_5_2_9))))
+          (net mdout1_4_26
+            (joined
+              (portRef D4 (instanceRef mux_9))
+              (portRef DOB8 (instanceRef pdp_ram_4_2_13))))
+          (net mdout1_3_26
+            (joined
+              (portRef D3 (instanceRef mux_9))
+              (portRef DOB8 (instanceRef pdp_ram_3_2_17))))
+          (net mdout1_2_26
+            (joined
+              (portRef D2 (instanceRef mux_9))
+              (portRef DOB8 (instanceRef pdp_ram_2_2_21))))
+          (net mdout1_1_26
+            (joined
+              (portRef D1 (instanceRef mux_9))
+              (portRef DOB8 (instanceRef pdp_ram_1_2_25))))
+          (net mdout1_0_26
+            (joined
+              (portRef D0 (instanceRef mux_9))
+              (portRef DOB8 (instanceRef pdp_ram_0_2_29))))
+          (net mdout1_7_27
+            (joined
+              (portRef D7 (instanceRef mux_8))
+              (portRef DOB0 (instanceRef pdp_ram_7_3_0))))
+          (net mdout1_6_27
+            (joined
+              (portRef D6 (instanceRef mux_8))
+              (portRef DOB0 (instanceRef pdp_ram_6_3_4))))
+          (net mdout1_5_27
+            (joined
+              (portRef D5 (instanceRef mux_8))
+              (portRef DOB0 (instanceRef pdp_ram_5_3_8))))
+          (net mdout1_4_27
+            (joined
+              (portRef D4 (instanceRef mux_8))
+              (portRef DOB0 (instanceRef pdp_ram_4_3_12))))
+          (net mdout1_3_27
+            (joined
+              (portRef D3 (instanceRef mux_8))
+              (portRef DOB0 (instanceRef pdp_ram_3_3_16))))
+          (net mdout1_2_27
+            (joined
+              (portRef D2 (instanceRef mux_8))
+              (portRef DOB0 (instanceRef pdp_ram_2_3_20))))
+          (net mdout1_1_27
+            (joined
+              (portRef D1 (instanceRef mux_8))
+              (portRef DOB0 (instanceRef pdp_ram_1_3_24))))
+          (net mdout1_0_27
+            (joined
+              (portRef D0 (instanceRef mux_8))
+              (portRef DOB0 (instanceRef pdp_ram_0_3_28))))
+          (net mdout1_7_28
+            (joined
+              (portRef D7 (instanceRef mux_7))
+              (portRef DOB1 (instanceRef pdp_ram_7_3_0))))
+          (net mdout1_6_28
+            (joined
+              (portRef D6 (instanceRef mux_7))
+              (portRef DOB1 (instanceRef pdp_ram_6_3_4))))
+          (net mdout1_5_28
+            (joined
+              (portRef D5 (instanceRef mux_7))
+              (portRef DOB1 (instanceRef pdp_ram_5_3_8))))
+          (net mdout1_4_28
+            (joined
+              (portRef D4 (instanceRef mux_7))
+              (portRef DOB1 (instanceRef pdp_ram_4_3_12))))
+          (net mdout1_3_28
+            (joined
+              (portRef D3 (instanceRef mux_7))
+              (portRef DOB1 (instanceRef pdp_ram_3_3_16))))
+          (net mdout1_2_28
+            (joined
+              (portRef D2 (instanceRef mux_7))
+              (portRef DOB1 (instanceRef pdp_ram_2_3_20))))
+          (net mdout1_1_28
+            (joined
+              (portRef D1 (instanceRef mux_7))
+              (portRef DOB1 (instanceRef pdp_ram_1_3_24))))
+          (net mdout1_0_28
+            (joined
+              (portRef D0 (instanceRef mux_7))
+              (portRef DOB1 (instanceRef pdp_ram_0_3_28))))
+          (net mdout1_7_29
+            (joined
+              (portRef D7 (instanceRef mux_6))
+              (portRef DOB2 (instanceRef pdp_ram_7_3_0))))
+          (net mdout1_6_29
+            (joined
+              (portRef D6 (instanceRef mux_6))
+              (portRef DOB2 (instanceRef pdp_ram_6_3_4))))
+          (net mdout1_5_29
+            (joined
+              (portRef D5 (instanceRef mux_6))
+              (portRef DOB2 (instanceRef pdp_ram_5_3_8))))
+          (net mdout1_4_29
+            (joined
+              (portRef D4 (instanceRef mux_6))
+              (portRef DOB2 (instanceRef pdp_ram_4_3_12))))
+          (net mdout1_3_29
+            (joined
+              (portRef D3 (instanceRef mux_6))
+              (portRef DOB2 (instanceRef pdp_ram_3_3_16))))
+          (net mdout1_2_29
+            (joined
+              (portRef D2 (instanceRef mux_6))
+              (portRef DOB2 (instanceRef pdp_ram_2_3_20))))
+          (net mdout1_1_29
+            (joined
+              (portRef D1 (instanceRef mux_6))
+              (portRef DOB2 (instanceRef pdp_ram_1_3_24))))
+          (net mdout1_0_29
+            (joined
+              (portRef D0 (instanceRef mux_6))
+              (portRef DOB2 (instanceRef pdp_ram_0_3_28))))
+          (net mdout1_7_30
+            (joined
+              (portRef D7 (instanceRef mux_5))
+              (portRef DOB3 (instanceRef pdp_ram_7_3_0))))
+          (net mdout1_6_30
+            (joined
+              (portRef D6 (instanceRef mux_5))
+              (portRef DOB3 (instanceRef pdp_ram_6_3_4))))
+          (net mdout1_5_30
+            (joined
+              (portRef D5 (instanceRef mux_5))
+              (portRef DOB3 (instanceRef pdp_ram_5_3_8))))
+          (net mdout1_4_30
+            (joined
+              (portRef D4 (instanceRef mux_5))
+              (portRef DOB3 (instanceRef pdp_ram_4_3_12))))
+          (net mdout1_3_30
+            (joined
+              (portRef D3 (instanceRef mux_5))
+              (portRef DOB3 (instanceRef pdp_ram_3_3_16))))
+          (net mdout1_2_30
+            (joined
+              (portRef D2 (instanceRef mux_5))
+              (portRef DOB3 (instanceRef pdp_ram_2_3_20))))
+          (net mdout1_1_30
+            (joined
+              (portRef D1 (instanceRef mux_5))
+              (portRef DOB3 (instanceRef pdp_ram_1_3_24))))
+          (net mdout1_0_30
+            (joined
+              (portRef D0 (instanceRef mux_5))
+              (portRef DOB3 (instanceRef pdp_ram_0_3_28))))
+          (net mdout1_7_31
+            (joined
+              (portRef D7 (instanceRef mux_4))
+              (portRef DOB4 (instanceRef pdp_ram_7_3_0))))
+          (net mdout1_6_31
+            (joined
+              (portRef D6 (instanceRef mux_4))
+              (portRef DOB4 (instanceRef pdp_ram_6_3_4))))
+          (net mdout1_5_31
+            (joined
+              (portRef D5 (instanceRef mux_4))
+              (portRef DOB4 (instanceRef pdp_ram_5_3_8))))
+          (net mdout1_4_31
+            (joined
+              (portRef D4 (instanceRef mux_4))
+              (portRef DOB4 (instanceRef pdp_ram_4_3_12))))
+          (net mdout1_3_31
+            (joined
+              (portRef D3 (instanceRef mux_4))
+              (portRef DOB4 (instanceRef pdp_ram_3_3_16))))
+          (net mdout1_2_31
+            (joined
+              (portRef D2 (instanceRef mux_4))
+              (portRef DOB4 (instanceRef pdp_ram_2_3_20))))
+          (net mdout1_1_31
+            (joined
+              (portRef D1 (instanceRef mux_4))
+              (portRef DOB4 (instanceRef pdp_ram_1_3_24))))
+          (net mdout1_0_31
+            (joined
+              (portRef D0 (instanceRef mux_4))
+              (portRef DOB4 (instanceRef pdp_ram_0_3_28))))
+          (net mdout1_7_32
+            (joined
+              (portRef D7 (instanceRef mux_3))
+              (portRef DOB5 (instanceRef pdp_ram_7_3_0))))
+          (net mdout1_6_32
+            (joined
+              (portRef D6 (instanceRef mux_3))
+              (portRef DOB5 (instanceRef pdp_ram_6_3_4))))
+          (net mdout1_5_32
+            (joined
+              (portRef D5 (instanceRef mux_3))
+              (portRef DOB5 (instanceRef pdp_ram_5_3_8))))
+          (net mdout1_4_32
+            (joined
+              (portRef D4 (instanceRef mux_3))
+              (portRef DOB5 (instanceRef pdp_ram_4_3_12))))
+          (net mdout1_3_32
+            (joined
+              (portRef D3 (instanceRef mux_3))
+              (portRef DOB5 (instanceRef pdp_ram_3_3_16))))
+          (net mdout1_2_32
+            (joined
+              (portRef D2 (instanceRef mux_3))
+              (portRef DOB5 (instanceRef pdp_ram_2_3_20))))
+          (net mdout1_1_32
+            (joined
+              (portRef D1 (instanceRef mux_3))
+              (portRef DOB5 (instanceRef pdp_ram_1_3_24))))
+          (net mdout1_0_32
+            (joined
+              (portRef D0 (instanceRef mux_3))
+              (portRef DOB5 (instanceRef pdp_ram_0_3_28))))
+          (net mdout1_7_33
+            (joined
+              (portRef D7 (instanceRef mux_2))
+              (portRef DOB6 (instanceRef pdp_ram_7_3_0))))
+          (net mdout1_6_33
+            (joined
+              (portRef D6 (instanceRef mux_2))
+              (portRef DOB6 (instanceRef pdp_ram_6_3_4))))
+          (net mdout1_5_33
+            (joined
+              (portRef D5 (instanceRef mux_2))
+              (portRef DOB6 (instanceRef pdp_ram_5_3_8))))
+          (net mdout1_4_33
+            (joined
+              (portRef D4 (instanceRef mux_2))
+              (portRef DOB6 (instanceRef pdp_ram_4_3_12))))
+          (net mdout1_3_33
+            (joined
+              (portRef D3 (instanceRef mux_2))
+              (portRef DOB6 (instanceRef pdp_ram_3_3_16))))
+          (net mdout1_2_33
+            (joined
+              (portRef D2 (instanceRef mux_2))
+              (portRef DOB6 (instanceRef pdp_ram_2_3_20))))
+          (net mdout1_1_33
+            (joined
+              (portRef D1 (instanceRef mux_2))
+              (portRef DOB6 (instanceRef pdp_ram_1_3_24))))
+          (net mdout1_0_33
+            (joined
+              (portRef D0 (instanceRef mux_2))
+              (portRef DOB6 (instanceRef pdp_ram_0_3_28))))
+          (net mdout1_7_34
+            (joined
+              (portRef D7 (instanceRef mux_1))
+              (portRef DOB7 (instanceRef pdp_ram_7_3_0))))
+          (net mdout1_6_34
+            (joined
+              (portRef D6 (instanceRef mux_1))
+              (portRef DOB7 (instanceRef pdp_ram_6_3_4))))
+          (net mdout1_5_34
+            (joined
+              (portRef D5 (instanceRef mux_1))
+              (portRef DOB7 (instanceRef pdp_ram_5_3_8))))
+          (net mdout1_4_34
+            (joined
+              (portRef D4 (instanceRef mux_1))
+              (portRef DOB7 (instanceRef pdp_ram_4_3_12))))
+          (net mdout1_3_34
+            (joined
+              (portRef D3 (instanceRef mux_1))
+              (portRef DOB7 (instanceRef pdp_ram_3_3_16))))
+          (net mdout1_2_34
+            (joined
+              (portRef D2 (instanceRef mux_1))
+              (portRef DOB7 (instanceRef pdp_ram_2_3_20))))
+          (net mdout1_1_34
+            (joined
+              (portRef D1 (instanceRef mux_1))
+              (portRef DOB7 (instanceRef pdp_ram_1_3_24))))
+          (net mdout1_0_34
+            (joined
+              (portRef D0 (instanceRef mux_1))
+              (portRef DOB7 (instanceRef pdp_ram_0_3_28))))
+          (net rptr_13_ff2
+            (joined
+              (portRef SD3 (instanceRef mux_0))
+              (portRef Q (instanceRef FF_16))
+              (portRef SD3 (instanceRef mux_35))
+              (portRef SD3 (instanceRef mux_34))
+              (portRef SD3 (instanceRef mux_33))
+              (portRef SD3 (instanceRef mux_32))
+              (portRef SD3 (instanceRef mux_31))
+              (portRef SD3 (instanceRef mux_30))
+              (portRef SD3 (instanceRef mux_29))
+              (portRef SD3 (instanceRef mux_28))
+              (portRef SD3 (instanceRef mux_27))
+              (portRef SD3 (instanceRef mux_26))
+              (portRef SD3 (instanceRef mux_25))
+              (portRef SD3 (instanceRef mux_24))
+              (portRef SD3 (instanceRef mux_23))
+              (portRef SD3 (instanceRef mux_22))
+              (portRef SD3 (instanceRef mux_21))
+              (portRef SD3 (instanceRef mux_20))
+              (portRef SD3 (instanceRef mux_19))
+              (portRef SD3 (instanceRef mux_18))
+              (portRef SD3 (instanceRef mux_17))
+              (portRef SD3 (instanceRef mux_16))
+              (portRef SD3 (instanceRef mux_15))
+              (portRef SD3 (instanceRef mux_14))
+              (portRef SD3 (instanceRef mux_13))
+              (portRef SD3 (instanceRef mux_12))
+              (portRef SD3 (instanceRef mux_11))
+              (portRef SD3 (instanceRef mux_10))
+              (portRef SD3 (instanceRef mux_9))
+              (portRef SD3 (instanceRef mux_8))
+              (portRef SD3 (instanceRef mux_7))
+              (portRef SD3 (instanceRef mux_6))
+              (portRef SD3 (instanceRef mux_5))
+              (portRef SD3 (instanceRef mux_4))
+              (portRef SD3 (instanceRef mux_3))
+              (portRef SD3 (instanceRef mux_2))
+              (portRef SD3 (instanceRef mux_1))))
+          (net rptr_12_ff2
+            (joined
+              (portRef SD2 (instanceRef mux_0))
+              (portRef Q (instanceRef FF_17))
+              (portRef SD2 (instanceRef mux_35))
+              (portRef SD2 (instanceRef mux_34))
+              (portRef SD2 (instanceRef mux_33))
+              (portRef SD2 (instanceRef mux_32))
+              (portRef SD2 (instanceRef mux_31))
+              (portRef SD2 (instanceRef mux_30))
+              (portRef SD2 (instanceRef mux_29))
+              (portRef SD2 (instanceRef mux_28))
+              (portRef SD2 (instanceRef mux_27))
+              (portRef SD2 (instanceRef mux_26))
+              (portRef SD2 (instanceRef mux_25))
+              (portRef SD2 (instanceRef mux_24))
+              (portRef SD2 (instanceRef mux_23))
+              (portRef SD2 (instanceRef mux_22))
+              (portRef SD2 (instanceRef mux_21))
+              (portRef SD2 (instanceRef mux_20))
+              (portRef SD2 (instanceRef mux_19))
+              (portRef SD2 (instanceRef mux_18))
+              (portRef SD2 (instanceRef mux_17))
+              (portRef SD2 (instanceRef mux_16))
+              (portRef SD2 (instanceRef mux_15))
+              (portRef SD2 (instanceRef mux_14))
+              (portRef SD2 (instanceRef mux_13))
+              (portRef SD2 (instanceRef mux_12))
+              (portRef SD2 (instanceRef mux_11))
+              (portRef SD2 (instanceRef mux_10))
+              (portRef SD2 (instanceRef mux_9))
+              (portRef SD2 (instanceRef mux_8))
+              (portRef SD2 (instanceRef mux_7))
+              (portRef SD2 (instanceRef mux_6))
+              (portRef SD2 (instanceRef mux_5))
+              (portRef SD2 (instanceRef mux_4))
+              (portRef SD2 (instanceRef mux_3))
+              (portRef SD2 (instanceRef mux_2))
+              (portRef SD2 (instanceRef mux_1))))
+          (net rptr_11_ff2
+            (joined
+              (portRef SD1 (instanceRef mux_0))
+              (portRef Q (instanceRef FF_18))
+              (portRef SD1 (instanceRef mux_35))
+              (portRef SD1 (instanceRef mux_34))
+              (portRef SD1 (instanceRef mux_33))
+              (portRef SD1 (instanceRef mux_32))
+              (portRef SD1 (instanceRef mux_31))
+              (portRef SD1 (instanceRef mux_30))
+              (portRef SD1 (instanceRef mux_29))
+              (portRef SD1 (instanceRef mux_28))
+              (portRef SD1 (instanceRef mux_27))
+              (portRef SD1 (instanceRef mux_26))
+              (portRef SD1 (instanceRef mux_25))
+              (portRef SD1 (instanceRef mux_24))
+              (portRef SD1 (instanceRef mux_23))
+              (portRef SD1 (instanceRef mux_22))
+              (portRef SD1 (instanceRef mux_21))
+              (portRef SD1 (instanceRef mux_20))
+              (portRef SD1 (instanceRef mux_19))
+              (portRef SD1 (instanceRef mux_18))
+              (portRef SD1 (instanceRef mux_17))
+              (portRef SD1 (instanceRef mux_16))
+              (portRef SD1 (instanceRef mux_15))
+              (portRef SD1 (instanceRef mux_14))
+              (portRef SD1 (instanceRef mux_13))
+              (portRef SD1 (instanceRef mux_12))
+              (portRef SD1 (instanceRef mux_11))
+              (portRef SD1 (instanceRef mux_10))
+              (portRef SD1 (instanceRef mux_9))
+              (portRef SD1 (instanceRef mux_8))
+              (portRef SD1 (instanceRef mux_7))
+              (portRef SD1 (instanceRef mux_6))
+              (portRef SD1 (instanceRef mux_5))
+              (portRef SD1 (instanceRef mux_4))
+              (portRef SD1 (instanceRef mux_3))
+              (portRef SD1 (instanceRef mux_2))
+              (portRef SD1 (instanceRef mux_1))))
+          (net mdout1_7_35
+            (joined
+              (portRef D7 (instanceRef mux_0))
+              (portRef DOB8 (instanceRef pdp_ram_7_3_0))))
+          (net mdout1_6_35
+            (joined
+              (portRef D6 (instanceRef mux_0))
+              (portRef DOB8 (instanceRef pdp_ram_6_3_4))))
+          (net mdout1_5_35
+            (joined
+              (portRef D5 (instanceRef mux_0))
+              (portRef DOB8 (instanceRef pdp_ram_5_3_8))))
+          (net mdout1_4_35
+            (joined
+              (portRef D4 (instanceRef mux_0))
+              (portRef DOB8 (instanceRef pdp_ram_4_3_12))))
+          (net mdout1_3_35
+            (joined
+              (portRef D3 (instanceRef mux_0))
+              (portRef DOB8 (instanceRef pdp_ram_3_3_16))))
+          (net mdout1_2_35
+            (joined
+              (portRef D2 (instanceRef mux_0))
+              (portRef DOB8 (instanceRef pdp_ram_2_3_20))))
+          (net mdout1_1_35
+            (joined
+              (portRef D1 (instanceRef mux_0))
+              (portRef DOB8 (instanceRef pdp_ram_1_3_24))))
+          (net mdout1_0_35
+            (joined
+              (portRef D0 (instanceRef mux_0))
+              (portRef DOB8 (instanceRef pdp_ram_0_3_28))))
+          (net wcnt_sub_0
+            (joined
+              (portRef S1 (instanceRef wcnt_0))
+              (portRef D (instanceRef FF_15))))
+          (net rptr_0
+            (joined
+              (portRef B1 (instanceRef wcnt_0))
+              (portRef ADB3 (instanceRef pdp_ram_0_0_31))
+              (portRef ADB3 (instanceRef pdp_ram_0_1_30))
+              (portRef ADB3 (instanceRef pdp_ram_0_2_29))
+              (portRef ADB3 (instanceRef pdp_ram_0_3_28))
+              (portRef ADB3 (instanceRef pdp_ram_1_0_27))
+              (portRef ADB3 (instanceRef pdp_ram_1_1_26))
+              (portRef ADB3 (instanceRef pdp_ram_1_2_25))
+              (portRef ADB3 (instanceRef pdp_ram_1_3_24))
+              (portRef ADB3 (instanceRef pdp_ram_2_0_23))
+              (portRef ADB3 (instanceRef pdp_ram_2_1_22))
+              (portRef ADB3 (instanceRef pdp_ram_2_2_21))
+              (portRef ADB3 (instanceRef pdp_ram_2_3_20))
+              (portRef ADB3 (instanceRef pdp_ram_3_0_19))
+              (portRef ADB3 (instanceRef pdp_ram_3_1_18))
+              (portRef ADB3 (instanceRef pdp_ram_3_2_17))
+              (portRef ADB3 (instanceRef pdp_ram_3_3_16))
+              (portRef ADB3 (instanceRef pdp_ram_4_0_15))
+              (portRef ADB3 (instanceRef pdp_ram_4_1_14))
+              (portRef ADB3 (instanceRef pdp_ram_4_2_13))
+              (portRef ADB3 (instanceRef pdp_ram_4_3_12))
+              (portRef ADB3 (instanceRef pdp_ram_5_0_11))
+              (portRef ADB3 (instanceRef pdp_ram_5_1_10))
+              (portRef ADB3 (instanceRef pdp_ram_5_2_9))
+              (portRef ADB3 (instanceRef pdp_ram_5_3_8))
+              (portRef ADB3 (instanceRef pdp_ram_6_0_7))
+              (portRef ADB3 (instanceRef pdp_ram_6_1_6))
+              (portRef ADB3 (instanceRef pdp_ram_6_2_5))
+              (portRef ADB3 (instanceRef pdp_ram_6_3_4))
+              (portRef ADB3 (instanceRef pdp_ram_7_0_3))
+              (portRef ADB3 (instanceRef pdp_ram_7_1_2))
+              (portRef ADB3 (instanceRef pdp_ram_7_2_1))
+              (portRef ADB3 (instanceRef pdp_ram_7_3_0))
+              (portRef Q (instanceRef FF_36))))
+          (net cnt_con_inv
+            (joined
+              (portRef B0 (instanceRef wcnt_0))
+              (portRef Z (instanceRef INV_0))))
+          (net wcount_0
+            (joined
+              (portRef A1 (instanceRef wcnt_0))
+              (portRef Q (instanceRef FF_81))
+              (portRef D (instanceRef FF_51))
+              (portRef A0 (instanceRef w_ctr_0))))
+          (net cnt_con
+            (joined
+              (portRef A0 (instanceRef wcnt_0))
+              (portRef Z (instanceRef AND2_t3))
+              (portRef A (instanceRef INV_0))
+              (portRef B1 (instanceRef bdcnt_bctr_cia))
+              (portRef A1 (instanceRef bdcnt_bctr_cia))
+              (portRef B1 (instanceRef bdcnt_bctr_0))
+              (portRef B0 (instanceRef bdcnt_bctr_0))
+              (portRef B1 (instanceRef bdcnt_bctr_1))
+              (portRef B0 (instanceRef bdcnt_bctr_1))
+              (portRef B1 (instanceRef bdcnt_bctr_2))
+              (portRef B0 (instanceRef bdcnt_bctr_2))
+              (portRef B1 (instanceRef bdcnt_bctr_3))
+              (portRef B0 (instanceRef bdcnt_bctr_3))
+              (portRef B1 (instanceRef bdcnt_bctr_4))
+              (portRef B0 (instanceRef bdcnt_bctr_4))
+              (portRef B1 (instanceRef bdcnt_bctr_5))
+              (portRef B0 (instanceRef bdcnt_bctr_5))
+              (portRef B1 (instanceRef bdcnt_bctr_6))
+              (portRef B0 (instanceRef bdcnt_bctr_6))
+              (portRef B1 (instanceRef bdcnt_bctr_7))
+              (portRef B0 (instanceRef bdcnt_bctr_7))))
+          (net precin
+            (joined
+              (portRef CIN (instanceRef wcnt_0))
+              (portRef COUT (instanceRef precin_inst636))))
+          (net wcnt_sub_1
+            (joined
+              (portRef S0 (instanceRef wcnt_1))
+              (portRef D (instanceRef FF_14))))
+          (net wcnt_sub_2
+            (joined
+              (portRef S1 (instanceRef wcnt_1))
+              (portRef D (instanceRef FF_13))))
+          (net rptr_2
+            (joined
+              (portRef B1 (instanceRef wcnt_1))
+              (portRef ADB5 (instanceRef pdp_ram_0_0_31))
+              (portRef ADB5 (instanceRef pdp_ram_0_1_30))
+              (portRef ADB5 (instanceRef pdp_ram_0_2_29))
+              (portRef ADB5 (instanceRef pdp_ram_0_3_28))
+              (portRef ADB5 (instanceRef pdp_ram_1_0_27))
+              (portRef ADB5 (instanceRef pdp_ram_1_1_26))
+              (portRef ADB5 (instanceRef pdp_ram_1_2_25))
+              (portRef ADB5 (instanceRef pdp_ram_1_3_24))
+              (portRef ADB5 (instanceRef pdp_ram_2_0_23))
+              (portRef ADB5 (instanceRef pdp_ram_2_1_22))
+              (portRef ADB5 (instanceRef pdp_ram_2_2_21))
+              (portRef ADB5 (instanceRef pdp_ram_2_3_20))
+              (portRef ADB5 (instanceRef pdp_ram_3_0_19))
+              (portRef ADB5 (instanceRef pdp_ram_3_1_18))
+              (portRef ADB5 (instanceRef pdp_ram_3_2_17))
+              (portRef ADB5 (instanceRef pdp_ram_3_3_16))
+              (portRef ADB5 (instanceRef pdp_ram_4_0_15))
+              (portRef ADB5 (instanceRef pdp_ram_4_1_14))
+              (portRef ADB5 (instanceRef pdp_ram_4_2_13))
+              (portRef ADB5 (instanceRef pdp_ram_4_3_12))
+              (portRef ADB5 (instanceRef pdp_ram_5_0_11))
+              (portRef ADB5 (instanceRef pdp_ram_5_1_10))
+              (portRef ADB5 (instanceRef pdp_ram_5_2_9))
+              (portRef ADB5 (instanceRef pdp_ram_5_3_8))
+              (portRef ADB5 (instanceRef pdp_ram_6_0_7))
+              (portRef ADB5 (instanceRef pdp_ram_6_1_6))
+              (portRef ADB5 (instanceRef pdp_ram_6_2_5))
+              (portRef ADB5 (instanceRef pdp_ram_6_3_4))
+              (portRef ADB5 (instanceRef pdp_ram_7_0_3))
+              (portRef ADB5 (instanceRef pdp_ram_7_1_2))
+              (portRef ADB5 (instanceRef pdp_ram_7_2_1))
+              (portRef ADB5 (instanceRef pdp_ram_7_3_0))
+              (portRef Q (instanceRef FF_34))))
+          (net rptr_1
+            (joined
+              (portRef B0 (instanceRef wcnt_1))
+              (portRef ADB4 (instanceRef pdp_ram_0_0_31))
+              (portRef ADB4 (instanceRef pdp_ram_0_1_30))
+              (portRef ADB4 (instanceRef pdp_ram_0_2_29))
+              (portRef ADB4 (instanceRef pdp_ram_0_3_28))
+              (portRef ADB4 (instanceRef pdp_ram_1_0_27))
+              (portRef ADB4 (instanceRef pdp_ram_1_1_26))
+              (portRef ADB4 (instanceRef pdp_ram_1_2_25))
+              (portRef ADB4 (instanceRef pdp_ram_1_3_24))
+              (portRef ADB4 (instanceRef pdp_ram_2_0_23))
+              (portRef ADB4 (instanceRef pdp_ram_2_1_22))
+              (portRef ADB4 (instanceRef pdp_ram_2_2_21))
+              (portRef ADB4 (instanceRef pdp_ram_2_3_20))
+              (portRef ADB4 (instanceRef pdp_ram_3_0_19))
+              (portRef ADB4 (instanceRef pdp_ram_3_1_18))
+              (portRef ADB4 (instanceRef pdp_ram_3_2_17))
+              (portRef ADB4 (instanceRef pdp_ram_3_3_16))
+              (portRef ADB4 (instanceRef pdp_ram_4_0_15))
+              (portRef ADB4 (instanceRef pdp_ram_4_1_14))
+              (portRef ADB4 (instanceRef pdp_ram_4_2_13))
+              (portRef ADB4 (instanceRef pdp_ram_4_3_12))
+              (portRef ADB4 (instanceRef pdp_ram_5_0_11))
+              (portRef ADB4 (instanceRef pdp_ram_5_1_10))
+              (portRef ADB4 (instanceRef pdp_ram_5_2_9))
+              (portRef ADB4 (instanceRef pdp_ram_5_3_8))
+              (portRef ADB4 (instanceRef pdp_ram_6_0_7))
+              (portRef ADB4 (instanceRef pdp_ram_6_1_6))
+              (portRef ADB4 (instanceRef pdp_ram_6_2_5))
+              (portRef ADB4 (instanceRef pdp_ram_6_3_4))
+              (portRef ADB4 (instanceRef pdp_ram_7_0_3))
+              (portRef ADB4 (instanceRef pdp_ram_7_1_2))
+              (portRef ADB4 (instanceRef pdp_ram_7_2_1))
+              (portRef ADB4 (instanceRef pdp_ram_7_3_0))
+              (portRef Q (instanceRef FF_35))))
+          (net wcount_2
+            (joined
+              (portRef A1 (instanceRef wcnt_1))
+              (portRef Q (instanceRef FF_79))
+              (portRef D (instanceRef FF_49))
+              (portRef A0 (instanceRef w_ctr_1))))
+          (net wcount_1
+            (joined
+              (portRef A0 (instanceRef wcnt_1))
+              (portRef Q (instanceRef FF_80))
+              (portRef D (instanceRef FF_50))
+              (portRef A1 (instanceRef w_ctr_0))))
+          (net co0_5
+            (joined
+              (portRef CIN (instanceRef wcnt_1))
+              (portRef COUT (instanceRef wcnt_0))))
+          (net wcnt_sub_3
+            (joined
+              (portRef S0 (instanceRef wcnt_2))
+              (portRef D (instanceRef FF_12))))
+          (net wcnt_sub_4
+            (joined
+              (portRef S1 (instanceRef wcnt_2))
+              (portRef D (instanceRef FF_11))))
+          (net rptr_4
+            (joined
+              (portRef B1 (instanceRef wcnt_2))
+              (portRef ADB7 (instanceRef pdp_ram_0_0_31))
+              (portRef ADB7 (instanceRef pdp_ram_0_1_30))
+              (portRef ADB7 (instanceRef pdp_ram_0_2_29))
+              (portRef ADB7 (instanceRef pdp_ram_0_3_28))
+              (portRef ADB7 (instanceRef pdp_ram_1_0_27))
+              (portRef ADB7 (instanceRef pdp_ram_1_1_26))
+              (portRef ADB7 (instanceRef pdp_ram_1_2_25))
+              (portRef ADB7 (instanceRef pdp_ram_1_3_24))
+              (portRef ADB7 (instanceRef pdp_ram_2_0_23))
+              (portRef ADB7 (instanceRef pdp_ram_2_1_22))
+              (portRef ADB7 (instanceRef pdp_ram_2_2_21))
+              (portRef ADB7 (instanceRef pdp_ram_2_3_20))
+              (portRef ADB7 (instanceRef pdp_ram_3_0_19))
+              (portRef ADB7 (instanceRef pdp_ram_3_1_18))
+              (portRef ADB7 (instanceRef pdp_ram_3_2_17))
+              (portRef ADB7 (instanceRef pdp_ram_3_3_16))
+              (portRef ADB7 (instanceRef pdp_ram_4_0_15))
+              (portRef ADB7 (instanceRef pdp_ram_4_1_14))
+              (portRef ADB7 (instanceRef pdp_ram_4_2_13))
+              (portRef ADB7 (instanceRef pdp_ram_4_3_12))
+              (portRef ADB7 (instanceRef pdp_ram_5_0_11))
+              (portRef ADB7 (instanceRef pdp_ram_5_1_10))
+              (portRef ADB7 (instanceRef pdp_ram_5_2_9))
+              (portRef ADB7 (instanceRef pdp_ram_5_3_8))
+              (portRef ADB7 (instanceRef pdp_ram_6_0_7))
+              (portRef ADB7 (instanceRef pdp_ram_6_1_6))
+              (portRef ADB7 (instanceRef pdp_ram_6_2_5))
+              (portRef ADB7 (instanceRef pdp_ram_6_3_4))
+              (portRef ADB7 (instanceRef pdp_ram_7_0_3))
+              (portRef ADB7 (instanceRef pdp_ram_7_1_2))
+              (portRef ADB7 (instanceRef pdp_ram_7_2_1))
+              (portRef ADB7 (instanceRef pdp_ram_7_3_0))
+              (portRef Q (instanceRef FF_32))))
+          (net rptr_3
+            (joined
+              (portRef B0 (instanceRef wcnt_2))
+              (portRef ADB6 (instanceRef pdp_ram_0_0_31))
+              (portRef ADB6 (instanceRef pdp_ram_0_1_30))
+              (portRef ADB6 (instanceRef pdp_ram_0_2_29))
+              (portRef ADB6 (instanceRef pdp_ram_0_3_28))
+              (portRef ADB6 (instanceRef pdp_ram_1_0_27))
+              (portRef ADB6 (instanceRef pdp_ram_1_1_26))
+              (portRef ADB6 (instanceRef pdp_ram_1_2_25))
+              (portRef ADB6 (instanceRef pdp_ram_1_3_24))
+              (portRef ADB6 (instanceRef pdp_ram_2_0_23))
+              (portRef ADB6 (instanceRef pdp_ram_2_1_22))
+              (portRef ADB6 (instanceRef pdp_ram_2_2_21))
+              (portRef ADB6 (instanceRef pdp_ram_2_3_20))
+              (portRef ADB6 (instanceRef pdp_ram_3_0_19))
+              (portRef ADB6 (instanceRef pdp_ram_3_1_18))
+              (portRef ADB6 (instanceRef pdp_ram_3_2_17))
+              (portRef ADB6 (instanceRef pdp_ram_3_3_16))
+              (portRef ADB6 (instanceRef pdp_ram_4_0_15))
+              (portRef ADB6 (instanceRef pdp_ram_4_1_14))
+              (portRef ADB6 (instanceRef pdp_ram_4_2_13))
+              (portRef ADB6 (instanceRef pdp_ram_4_3_12))
+              (portRef ADB6 (instanceRef pdp_ram_5_0_11))
+              (portRef ADB6 (instanceRef pdp_ram_5_1_10))
+              (portRef ADB6 (instanceRef pdp_ram_5_2_9))
+              (portRef ADB6 (instanceRef pdp_ram_5_3_8))
+              (portRef ADB6 (instanceRef pdp_ram_6_0_7))
+              (portRef ADB6 (instanceRef pdp_ram_6_1_6))
+              (portRef ADB6 (instanceRef pdp_ram_6_2_5))
+              (portRef ADB6 (instanceRef pdp_ram_6_3_4))
+              (portRef ADB6 (instanceRef pdp_ram_7_0_3))
+              (portRef ADB6 (instanceRef pdp_ram_7_1_2))
+              (portRef ADB6 (instanceRef pdp_ram_7_2_1))
+              (portRef ADB6 (instanceRef pdp_ram_7_3_0))
+              (portRef Q (instanceRef FF_33))))
+          (net wcount_4
+            (joined
+              (portRef A1 (instanceRef wcnt_2))
+              (portRef Q (instanceRef FF_77))
+              (portRef D (instanceRef FF_47))
+              (portRef A0 (instanceRef w_ctr_2))))
+          (net wcount_3
+            (joined
+              (portRef A0 (instanceRef wcnt_2))
+              (portRef Q (instanceRef FF_78))
+              (portRef D (instanceRef FF_48))
+              (portRef A1 (instanceRef w_ctr_1))))
+          (net co1_5
+            (joined
+              (portRef CIN (instanceRef wcnt_2))
+              (portRef COUT (instanceRef wcnt_1))))
+          (net wcnt_sub_5
+            (joined
+              (portRef S0 (instanceRef wcnt_3))
+              (portRef D (instanceRef FF_10))))
+          (net wcnt_sub_6
+            (joined
+              (portRef S1 (instanceRef wcnt_3))
+              (portRef D (instanceRef FF_9))))
+          (net rptr_6
+            (joined
+              (portRef B1 (instanceRef wcnt_3))
+              (portRef ADB9 (instanceRef pdp_ram_0_0_31))
+              (portRef ADB9 (instanceRef pdp_ram_0_1_30))
+              (portRef ADB9 (instanceRef pdp_ram_0_2_29))
+              (portRef ADB9 (instanceRef pdp_ram_0_3_28))
+              (portRef ADB9 (instanceRef pdp_ram_1_0_27))
+              (portRef ADB9 (instanceRef pdp_ram_1_1_26))
+              (portRef ADB9 (instanceRef pdp_ram_1_2_25))
+              (portRef ADB9 (instanceRef pdp_ram_1_3_24))
+              (portRef ADB9 (instanceRef pdp_ram_2_0_23))
+              (portRef ADB9 (instanceRef pdp_ram_2_1_22))
+              (portRef ADB9 (instanceRef pdp_ram_2_2_21))
+              (portRef ADB9 (instanceRef pdp_ram_2_3_20))
+              (portRef ADB9 (instanceRef pdp_ram_3_0_19))
+              (portRef ADB9 (instanceRef pdp_ram_3_1_18))
+              (portRef ADB9 (instanceRef pdp_ram_3_2_17))
+              (portRef ADB9 (instanceRef pdp_ram_3_3_16))
+              (portRef ADB9 (instanceRef pdp_ram_4_0_15))
+              (portRef ADB9 (instanceRef pdp_ram_4_1_14))
+              (portRef ADB9 (instanceRef pdp_ram_4_2_13))
+              (portRef ADB9 (instanceRef pdp_ram_4_3_12))
+              (portRef ADB9 (instanceRef pdp_ram_5_0_11))
+              (portRef ADB9 (instanceRef pdp_ram_5_1_10))
+              (portRef ADB9 (instanceRef pdp_ram_5_2_9))
+              (portRef ADB9 (instanceRef pdp_ram_5_3_8))
+              (portRef ADB9 (instanceRef pdp_ram_6_0_7))
+              (portRef ADB9 (instanceRef pdp_ram_6_1_6))
+              (portRef ADB9 (instanceRef pdp_ram_6_2_5))
+              (portRef ADB9 (instanceRef pdp_ram_6_3_4))
+              (portRef ADB9 (instanceRef pdp_ram_7_0_3))
+              (portRef ADB9 (instanceRef pdp_ram_7_1_2))
+              (portRef ADB9 (instanceRef pdp_ram_7_2_1))
+              (portRef ADB9 (instanceRef pdp_ram_7_3_0))
+              (portRef Q (instanceRef FF_30))))
+          (net rptr_5
+            (joined
+              (portRef B0 (instanceRef wcnt_3))
+              (portRef ADB8 (instanceRef pdp_ram_0_0_31))
+              (portRef ADB8 (instanceRef pdp_ram_0_1_30))
+              (portRef ADB8 (instanceRef pdp_ram_0_2_29))
+              (portRef ADB8 (instanceRef pdp_ram_0_3_28))
+              (portRef ADB8 (instanceRef pdp_ram_1_0_27))
+              (portRef ADB8 (instanceRef pdp_ram_1_1_26))
+              (portRef ADB8 (instanceRef pdp_ram_1_2_25))
+              (portRef ADB8 (instanceRef pdp_ram_1_3_24))
+              (portRef ADB8 (instanceRef pdp_ram_2_0_23))
+              (portRef ADB8 (instanceRef pdp_ram_2_1_22))
+              (portRef ADB8 (instanceRef pdp_ram_2_2_21))
+              (portRef ADB8 (instanceRef pdp_ram_2_3_20))
+              (portRef ADB8 (instanceRef pdp_ram_3_0_19))
+              (portRef ADB8 (instanceRef pdp_ram_3_1_18))
+              (portRef ADB8 (instanceRef pdp_ram_3_2_17))
+              (portRef ADB8 (instanceRef pdp_ram_3_3_16))
+              (portRef ADB8 (instanceRef pdp_ram_4_0_15))
+              (portRef ADB8 (instanceRef pdp_ram_4_1_14))
+              (portRef ADB8 (instanceRef pdp_ram_4_2_13))
+              (portRef ADB8 (instanceRef pdp_ram_4_3_12))
+              (portRef ADB8 (instanceRef pdp_ram_5_0_11))
+              (portRef ADB8 (instanceRef pdp_ram_5_1_10))
+              (portRef ADB8 (instanceRef pdp_ram_5_2_9))
+              (portRef ADB8 (instanceRef pdp_ram_5_3_8))
+              (portRef ADB8 (instanceRef pdp_ram_6_0_7))
+              (portRef ADB8 (instanceRef pdp_ram_6_1_6))
+              (portRef ADB8 (instanceRef pdp_ram_6_2_5))
+              (portRef ADB8 (instanceRef pdp_ram_6_3_4))
+              (portRef ADB8 (instanceRef pdp_ram_7_0_3))
+              (portRef ADB8 (instanceRef pdp_ram_7_1_2))
+              (portRef ADB8 (instanceRef pdp_ram_7_2_1))
+              (portRef ADB8 (instanceRef pdp_ram_7_3_0))
+              (portRef Q (instanceRef FF_31))))
+          (net wcount_6
+            (joined
+              (portRef A1 (instanceRef wcnt_3))
+              (portRef Q (instanceRef FF_75))
+              (portRef D (instanceRef FF_45))
+              (portRef A0 (instanceRef w_ctr_3))))
+          (net wcount_5
+            (joined
+              (portRef A0 (instanceRef wcnt_3))
+              (portRef Q (instanceRef FF_76))
+              (portRef D (instanceRef FF_46))
+              (portRef A1 (instanceRef w_ctr_2))))
+          (net co2_5
+            (joined
+              (portRef CIN (instanceRef wcnt_3))
+              (portRef COUT (instanceRef wcnt_2))))
+          (net wcnt_sub_7
+            (joined
+              (portRef S0 (instanceRef wcnt_4))
+              (portRef D (instanceRef FF_8))))
+          (net wcnt_sub_8
+            (joined
+              (portRef S1 (instanceRef wcnt_4))
+              (portRef D (instanceRef FF_7))))
+          (net rptr_8
+            (joined
+              (portRef B1 (instanceRef wcnt_4))
+              (portRef ADB11 (instanceRef pdp_ram_0_0_31))
+              (portRef ADB11 (instanceRef pdp_ram_0_1_30))
+              (portRef ADB11 (instanceRef pdp_ram_0_2_29))
+              (portRef ADB11 (instanceRef pdp_ram_0_3_28))
+              (portRef ADB11 (instanceRef pdp_ram_1_0_27))
+              (portRef ADB11 (instanceRef pdp_ram_1_1_26))
+              (portRef ADB11 (instanceRef pdp_ram_1_2_25))
+              (portRef ADB11 (instanceRef pdp_ram_1_3_24))
+              (portRef ADB11 (instanceRef pdp_ram_2_0_23))
+              (portRef ADB11 (instanceRef pdp_ram_2_1_22))
+              (portRef ADB11 (instanceRef pdp_ram_2_2_21))
+              (portRef ADB11 (instanceRef pdp_ram_2_3_20))
+              (portRef ADB11 (instanceRef pdp_ram_3_0_19))
+              (portRef ADB11 (instanceRef pdp_ram_3_1_18))
+              (portRef ADB11 (instanceRef pdp_ram_3_2_17))
+              (portRef ADB11 (instanceRef pdp_ram_3_3_16))
+              (portRef ADB11 (instanceRef pdp_ram_4_0_15))
+              (portRef ADB11 (instanceRef pdp_ram_4_1_14))
+              (portRef ADB11 (instanceRef pdp_ram_4_2_13))
+              (portRef ADB11 (instanceRef pdp_ram_4_3_12))
+              (portRef ADB11 (instanceRef pdp_ram_5_0_11))
+              (portRef ADB11 (instanceRef pdp_ram_5_1_10))
+              (portRef ADB11 (instanceRef pdp_ram_5_2_9))
+              (portRef ADB11 (instanceRef pdp_ram_5_3_8))
+              (portRef ADB11 (instanceRef pdp_ram_6_0_7))
+              (portRef ADB11 (instanceRef pdp_ram_6_1_6))
+              (portRef ADB11 (instanceRef pdp_ram_6_2_5))
+              (portRef ADB11 (instanceRef pdp_ram_6_3_4))
+              (portRef ADB11 (instanceRef pdp_ram_7_0_3))
+              (portRef ADB11 (instanceRef pdp_ram_7_1_2))
+              (portRef ADB11 (instanceRef pdp_ram_7_2_1))
+              (portRef ADB11 (instanceRef pdp_ram_7_3_0))
+              (portRef Q (instanceRef FF_28))))
+          (net rptr_7
+            (joined
+              (portRef B0 (instanceRef wcnt_4))
+              (portRef ADB10 (instanceRef pdp_ram_0_0_31))
+              (portRef ADB10 (instanceRef pdp_ram_0_1_30))
+              (portRef ADB10 (instanceRef pdp_ram_0_2_29))
+              (portRef ADB10 (instanceRef pdp_ram_0_3_28))
+              (portRef ADB10 (instanceRef pdp_ram_1_0_27))
+              (portRef ADB10 (instanceRef pdp_ram_1_1_26))
+              (portRef ADB10 (instanceRef pdp_ram_1_2_25))
+              (portRef ADB10 (instanceRef pdp_ram_1_3_24))
+              (portRef ADB10 (instanceRef pdp_ram_2_0_23))
+              (portRef ADB10 (instanceRef pdp_ram_2_1_22))
+              (portRef ADB10 (instanceRef pdp_ram_2_2_21))
+              (portRef ADB10 (instanceRef pdp_ram_2_3_20))
+              (portRef ADB10 (instanceRef pdp_ram_3_0_19))
+              (portRef ADB10 (instanceRef pdp_ram_3_1_18))
+              (portRef ADB10 (instanceRef pdp_ram_3_2_17))
+              (portRef ADB10 (instanceRef pdp_ram_3_3_16))
+              (portRef ADB10 (instanceRef pdp_ram_4_0_15))
+              (portRef ADB10 (instanceRef pdp_ram_4_1_14))
+              (portRef ADB10 (instanceRef pdp_ram_4_2_13))
+              (portRef ADB10 (instanceRef pdp_ram_4_3_12))
+              (portRef ADB10 (instanceRef pdp_ram_5_0_11))
+              (portRef ADB10 (instanceRef pdp_ram_5_1_10))
+              (portRef ADB10 (instanceRef pdp_ram_5_2_9))
+              (portRef ADB10 (instanceRef pdp_ram_5_3_8))
+              (portRef ADB10 (instanceRef pdp_ram_6_0_7))
+              (portRef ADB10 (instanceRef pdp_ram_6_1_6))
+              (portRef ADB10 (instanceRef pdp_ram_6_2_5))
+              (portRef ADB10 (instanceRef pdp_ram_6_3_4))
+              (portRef ADB10 (instanceRef pdp_ram_7_0_3))
+              (portRef ADB10 (instanceRef pdp_ram_7_1_2))
+              (portRef ADB10 (instanceRef pdp_ram_7_2_1))
+              (portRef ADB10 (instanceRef pdp_ram_7_3_0))
+              (portRef Q (instanceRef FF_29))))
+          (net wcount_8
+            (joined
+              (portRef A1 (instanceRef wcnt_4))
+              (portRef Q (instanceRef FF_73))
+              (portRef D (instanceRef FF_43))
+              (portRef A0 (instanceRef w_ctr_4))))
+          (net wcount_7
+            (joined
+              (portRef A0 (instanceRef wcnt_4))
+              (portRef Q (instanceRef FF_74))
+              (portRef D (instanceRef FF_44))
+              (portRef A1 (instanceRef w_ctr_3))))
+          (net co3_5
+            (joined
+              (portRef CIN (instanceRef wcnt_4))
+              (portRef COUT (instanceRef wcnt_3))))
+          (net wcnt_sub_9
+            (joined
+              (portRef S0 (instanceRef wcnt_5))
+              (portRef D (instanceRef FF_6))))
+          (net wcnt_sub_10
+            (joined
+              (portRef S1 (instanceRef wcnt_5))
+              (portRef D (instanceRef FF_5))))
+          (net rptr_10
+            (joined
+              (portRef B1 (instanceRef wcnt_5))
+              (portRef ADB13 (instanceRef pdp_ram_0_0_31))
+              (portRef ADB13 (instanceRef pdp_ram_0_1_30))
+              (portRef ADB13 (instanceRef pdp_ram_0_2_29))
+              (portRef ADB13 (instanceRef pdp_ram_0_3_28))
+              (portRef ADB13 (instanceRef pdp_ram_1_0_27))
+              (portRef ADB13 (instanceRef pdp_ram_1_1_26))
+              (portRef ADB13 (instanceRef pdp_ram_1_2_25))
+              (portRef ADB13 (instanceRef pdp_ram_1_3_24))
+              (portRef ADB13 (instanceRef pdp_ram_2_0_23))
+              (portRef ADB13 (instanceRef pdp_ram_2_1_22))
+              (portRef ADB13 (instanceRef pdp_ram_2_2_21))
+              (portRef ADB13 (instanceRef pdp_ram_2_3_20))
+              (portRef ADB13 (instanceRef pdp_ram_3_0_19))
+              (portRef ADB13 (instanceRef pdp_ram_3_1_18))
+              (portRef ADB13 (instanceRef pdp_ram_3_2_17))
+              (portRef ADB13 (instanceRef pdp_ram_3_3_16))
+              (portRef ADB13 (instanceRef pdp_ram_4_0_15))
+              (portRef ADB13 (instanceRef pdp_ram_4_1_14))
+              (portRef ADB13 (instanceRef pdp_ram_4_2_13))
+              (portRef ADB13 (instanceRef pdp_ram_4_3_12))
+              (portRef ADB13 (instanceRef pdp_ram_5_0_11))
+              (portRef ADB13 (instanceRef pdp_ram_5_1_10))
+              (portRef ADB13 (instanceRef pdp_ram_5_2_9))
+              (portRef ADB13 (instanceRef pdp_ram_5_3_8))
+              (portRef ADB13 (instanceRef pdp_ram_6_0_7))
+              (portRef ADB13 (instanceRef pdp_ram_6_1_6))
+              (portRef ADB13 (instanceRef pdp_ram_6_2_5))
+              (portRef ADB13 (instanceRef pdp_ram_6_3_4))
+              (portRef ADB13 (instanceRef pdp_ram_7_0_3))
+              (portRef ADB13 (instanceRef pdp_ram_7_1_2))
+              (portRef ADB13 (instanceRef pdp_ram_7_2_1))
+              (portRef ADB13 (instanceRef pdp_ram_7_3_0))
+              (portRef Q (instanceRef FF_26))))
+          (net rptr_9
+            (joined
+              (portRef B0 (instanceRef wcnt_5))
+              (portRef ADB12 (instanceRef pdp_ram_0_0_31))
+              (portRef ADB12 (instanceRef pdp_ram_0_1_30))
+              (portRef ADB12 (instanceRef pdp_ram_0_2_29))
+              (portRef ADB12 (instanceRef pdp_ram_0_3_28))
+              (portRef ADB12 (instanceRef pdp_ram_1_0_27))
+              (portRef ADB12 (instanceRef pdp_ram_1_1_26))
+              (portRef ADB12 (instanceRef pdp_ram_1_2_25))
+              (portRef ADB12 (instanceRef pdp_ram_1_3_24))
+              (portRef ADB12 (instanceRef pdp_ram_2_0_23))
+              (portRef ADB12 (instanceRef pdp_ram_2_1_22))
+              (portRef ADB12 (instanceRef pdp_ram_2_2_21))
+              (portRef ADB12 (instanceRef pdp_ram_2_3_20))
+              (portRef ADB12 (instanceRef pdp_ram_3_0_19))
+              (portRef ADB12 (instanceRef pdp_ram_3_1_18))
+              (portRef ADB12 (instanceRef pdp_ram_3_2_17))
+              (portRef ADB12 (instanceRef pdp_ram_3_3_16))
+              (portRef ADB12 (instanceRef pdp_ram_4_0_15))
+              (portRef ADB12 (instanceRef pdp_ram_4_1_14))
+              (portRef ADB12 (instanceRef pdp_ram_4_2_13))
+              (portRef ADB12 (instanceRef pdp_ram_4_3_12))
+              (portRef ADB12 (instanceRef pdp_ram_5_0_11))
+              (portRef ADB12 (instanceRef pdp_ram_5_1_10))
+              (portRef ADB12 (instanceRef pdp_ram_5_2_9))
+              (portRef ADB12 (instanceRef pdp_ram_5_3_8))
+              (portRef ADB12 (instanceRef pdp_ram_6_0_7))
+              (portRef ADB12 (instanceRef pdp_ram_6_1_6))
+              (portRef ADB12 (instanceRef pdp_ram_6_2_5))
+              (portRef ADB12 (instanceRef pdp_ram_6_3_4))
+              (portRef ADB12 (instanceRef pdp_ram_7_0_3))
+              (portRef ADB12 (instanceRef pdp_ram_7_1_2))
+              (portRef ADB12 (instanceRef pdp_ram_7_2_1))
+              (portRef ADB12 (instanceRef pdp_ram_7_3_0))
+              (portRef Q (instanceRef FF_27))))
+          (net wcount_10
+            (joined
+              (portRef A1 (instanceRef wcnt_5))
+              (portRef Q (instanceRef FF_71))
+              (portRef D (instanceRef FF_41))
+              (portRef A0 (instanceRef w_ctr_5))))
+          (net wcount_9
+            (joined
+              (portRef A0 (instanceRef wcnt_5))
+              (portRef Q (instanceRef FF_72))
+              (portRef D (instanceRef FF_42))
+              (portRef A1 (instanceRef w_ctr_4))))
+          (net co4_5
+            (joined
+              (portRef CIN (instanceRef wcnt_5))
+              (portRef COUT (instanceRef wcnt_4))))
+          (net wcnt_sub_11
+            (joined
+              (portRef S0 (instanceRef wcnt_6))
+              (portRef D (instanceRef FF_4))))
+          (net wcnt_sub_12
+            (joined
+              (portRef S1 (instanceRef wcnt_6))
+              (portRef D (instanceRef FF_3))))
+          (net rptr_12
+            (joined
+              (portRef B1 (instanceRef wcnt_6))
+              (portRef CSB1 (instanceRef pdp_ram_0_0_31))
+              (portRef CSB1 (instanceRef pdp_ram_0_1_30))
+              (portRef CSB1 (instanceRef pdp_ram_0_2_29))
+              (portRef CSB1 (instanceRef pdp_ram_0_3_28))
+              (portRef CSB1 (instanceRef pdp_ram_1_0_27))
+              (portRef CSB1 (instanceRef pdp_ram_1_1_26))
+              (portRef CSB1 (instanceRef pdp_ram_1_2_25))
+              (portRef CSB1 (instanceRef pdp_ram_1_3_24))
+              (portRef CSB1 (instanceRef pdp_ram_2_0_23))
+              (portRef CSB1 (instanceRef pdp_ram_2_1_22))
+              (portRef CSB1 (instanceRef pdp_ram_2_2_21))
+              (portRef CSB1 (instanceRef pdp_ram_2_3_20))
+              (portRef CSB1 (instanceRef pdp_ram_3_0_19))
+              (portRef CSB1 (instanceRef pdp_ram_3_1_18))
+              (portRef CSB1 (instanceRef pdp_ram_3_2_17))
+              (portRef CSB1 (instanceRef pdp_ram_3_3_16))
+              (portRef CSB1 (instanceRef pdp_ram_4_0_15))
+              (portRef CSB1 (instanceRef pdp_ram_4_1_14))
+              (portRef CSB1 (instanceRef pdp_ram_4_2_13))
+              (portRef CSB1 (instanceRef pdp_ram_4_3_12))
+              (portRef CSB1 (instanceRef pdp_ram_5_0_11))
+              (portRef CSB1 (instanceRef pdp_ram_5_1_10))
+              (portRef CSB1 (instanceRef pdp_ram_5_2_9))
+              (portRef CSB1 (instanceRef pdp_ram_5_3_8))
+              (portRef CSB1 (instanceRef pdp_ram_6_0_7))
+              (portRef CSB1 (instanceRef pdp_ram_6_1_6))
+              (portRef CSB1 (instanceRef pdp_ram_6_2_5))
+              (portRef CSB1 (instanceRef pdp_ram_6_3_4))
+              (portRef CSB1 (instanceRef pdp_ram_7_0_3))
+              (portRef CSB1 (instanceRef pdp_ram_7_1_2))
+              (portRef CSB1 (instanceRef pdp_ram_7_2_1))
+              (portRef CSB1 (instanceRef pdp_ram_7_3_0))
+              (portRef Q (instanceRef FF_24))
+              (portRef D (instanceRef FF_20))))
+          (net rptr_11
+            (joined
+              (portRef B0 (instanceRef wcnt_6))
+              (portRef CSB0 (instanceRef pdp_ram_0_0_31))
+              (portRef CSB0 (instanceRef pdp_ram_0_1_30))
+              (portRef CSB0 (instanceRef pdp_ram_0_2_29))
+              (portRef CSB0 (instanceRef pdp_ram_0_3_28))
+              (portRef CSB0 (instanceRef pdp_ram_1_0_27))
+              (portRef CSB0 (instanceRef pdp_ram_1_1_26))
+              (portRef CSB0 (instanceRef pdp_ram_1_2_25))
+              (portRef CSB0 (instanceRef pdp_ram_1_3_24))
+              (portRef CSB0 (instanceRef pdp_ram_2_0_23))
+              (portRef CSB0 (instanceRef pdp_ram_2_1_22))
+              (portRef CSB0 (instanceRef pdp_ram_2_2_21))
+              (portRef CSB0 (instanceRef pdp_ram_2_3_20))
+              (portRef CSB0 (instanceRef pdp_ram_3_0_19))
+              (portRef CSB0 (instanceRef pdp_ram_3_1_18))
+              (portRef CSB0 (instanceRef pdp_ram_3_2_17))
+              (portRef CSB0 (instanceRef pdp_ram_3_3_16))
+              (portRef CSB0 (instanceRef pdp_ram_4_0_15))
+              (portRef CSB0 (instanceRef pdp_ram_4_1_14))
+              (portRef CSB0 (instanceRef pdp_ram_4_2_13))
+              (portRef CSB0 (instanceRef pdp_ram_4_3_12))
+              (portRef CSB0 (instanceRef pdp_ram_5_0_11))
+              (portRef CSB0 (instanceRef pdp_ram_5_1_10))
+              (portRef CSB0 (instanceRef pdp_ram_5_2_9))
+              (portRef CSB0 (instanceRef pdp_ram_5_3_8))
+              (portRef CSB0 (instanceRef pdp_ram_6_0_7))
+              (portRef CSB0 (instanceRef pdp_ram_6_1_6))
+              (portRef CSB0 (instanceRef pdp_ram_6_2_5))
+              (portRef CSB0 (instanceRef pdp_ram_6_3_4))
+              (portRef CSB0 (instanceRef pdp_ram_7_0_3))
+              (portRef CSB0 (instanceRef pdp_ram_7_1_2))
+              (portRef CSB0 (instanceRef pdp_ram_7_2_1))
+              (portRef CSB0 (instanceRef pdp_ram_7_3_0))
+              (portRef Q (instanceRef FF_25))
+              (portRef D (instanceRef FF_21))))
+          (net wcount_12
+            (joined
+              (portRef A1 (instanceRef wcnt_6))
+              (portRef Q (instanceRef FF_69))
+              (portRef D (instanceRef FF_39))
+              (portRef A0 (instanceRef w_ctr_6))))
+          (net wcount_11
+            (joined
+              (portRef A0 (instanceRef wcnt_6))
+              (portRef Q (instanceRef FF_70))
+              (portRef D (instanceRef FF_40))
+              (portRef A1 (instanceRef w_ctr_5))))
+          (net co5_5
+            (joined
+              (portRef CIN (instanceRef wcnt_6))
+              (portRef COUT (instanceRef wcnt_5))))
+          (net wcnt_sub_13
+            (joined
+              (portRef S0 (instanceRef wcnt_7))
+              (portRef D (instanceRef FF_2))))
+          (net wcnt_sub_14
+            (joined
+              (portRef S1 (instanceRef wcnt_7))
+              (portRef D (instanceRef FF_1))))
+          (net rptr_13
+            (joined
+              (portRef B0 (instanceRef wcnt_7))
+              (portRef CSB2 (instanceRef pdp_ram_0_0_31))
+              (portRef CSB2 (instanceRef pdp_ram_0_1_30))
+              (portRef CSB2 (instanceRef pdp_ram_0_2_29))
+              (portRef CSB2 (instanceRef pdp_ram_0_3_28))
+              (portRef CSB2 (instanceRef pdp_ram_1_0_27))
+              (portRef CSB2 (instanceRef pdp_ram_1_1_26))
+              (portRef CSB2 (instanceRef pdp_ram_1_2_25))
+              (portRef CSB2 (instanceRef pdp_ram_1_3_24))
+              (portRef CSB2 (instanceRef pdp_ram_2_0_23))
+              (portRef CSB2 (instanceRef pdp_ram_2_1_22))
+              (portRef CSB2 (instanceRef pdp_ram_2_2_21))
+              (portRef CSB2 (instanceRef pdp_ram_2_3_20))
+              (portRef CSB2 (instanceRef pdp_ram_3_0_19))
+              (portRef CSB2 (instanceRef pdp_ram_3_1_18))
+              (portRef CSB2 (instanceRef pdp_ram_3_2_17))
+              (portRef CSB2 (instanceRef pdp_ram_3_3_16))
+              (portRef CSB2 (instanceRef pdp_ram_4_0_15))
+              (portRef CSB2 (instanceRef pdp_ram_4_1_14))
+              (portRef CSB2 (instanceRef pdp_ram_4_2_13))
+              (portRef CSB2 (instanceRef pdp_ram_4_3_12))
+              (portRef CSB2 (instanceRef pdp_ram_5_0_11))
+              (portRef CSB2 (instanceRef pdp_ram_5_1_10))
+              (portRef CSB2 (instanceRef pdp_ram_5_2_9))
+              (portRef CSB2 (instanceRef pdp_ram_5_3_8))
+              (portRef CSB2 (instanceRef pdp_ram_6_0_7))
+              (portRef CSB2 (instanceRef pdp_ram_6_1_6))
+              (portRef CSB2 (instanceRef pdp_ram_6_2_5))
+              (portRef CSB2 (instanceRef pdp_ram_6_3_4))
+              (portRef CSB2 (instanceRef pdp_ram_7_0_3))
+              (portRef CSB2 (instanceRef pdp_ram_7_1_2))
+              (portRef CSB2 (instanceRef pdp_ram_7_2_1))
+              (portRef CSB2 (instanceRef pdp_ram_7_3_0))
+              (portRef Q (instanceRef FF_23))
+              (portRef D (instanceRef FF_19))))
+          (net wcnt_sub_msb
+            (joined
+              (portRef A1 (instanceRef wcnt_7))
+              (portRef Z (instanceRef XOR2_t0))))
+          (net wcount_13
+            (joined
+              (portRef A0 (instanceRef wcnt_7))
+              (portRef Q (instanceRef FF_68))
+              (portRef D (instanceRef FF_38))
+              (portRef A1 (instanceRef w_ctr_6))))
+          (net co6_5
+            (joined
+              (portRef CIN (instanceRef wcnt_7))
+              (portRef COUT (instanceRef wcnt_6))))
+          (net co7_3d
+            (joined
+              (portRef S0 (instanceRef wcntd))))
+          (net co7_3
+            (joined
+              (portRef CIN (instanceRef wcntd))
+              (portRef COUT (instanceRef wcnt_7))))
+          (net wren_i
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_ci_a))
+              (portRef Z (instanceRef AND2_t5))
+              (portRef A (instanceRef AND2_t3))
+              (portRef A (instanceRef XOR2_t2))
+              (portRef A (instanceRef INV_2))
+              (portRef AD1 (instanceRef LUT4_1))
+              (portRef A (instanceRef INV_1))
+              (portRef OCEA (instanceRef pdp_ram_0_0_31))
+              (portRef CEA (instanceRef pdp_ram_0_0_31))
+              (portRef OCEA (instanceRef pdp_ram_0_1_30))
+              (portRef CEA (instanceRef pdp_ram_0_1_30))
+              (portRef OCEA (instanceRef pdp_ram_0_2_29))
+              (portRef CEA (instanceRef pdp_ram_0_2_29))
+              (portRef OCEA (instanceRef pdp_ram_0_3_28))
+              (portRef CEA (instanceRef pdp_ram_0_3_28))
+              (portRef OCEA (instanceRef pdp_ram_1_0_27))
+              (portRef CEA (instanceRef pdp_ram_1_0_27))
+              (portRef OCEA (instanceRef pdp_ram_1_1_26))
+              (portRef CEA (instanceRef pdp_ram_1_1_26))
+              (portRef OCEA (instanceRef pdp_ram_1_2_25))
+              (portRef CEA (instanceRef pdp_ram_1_2_25))
+              (portRef OCEA (instanceRef pdp_ram_1_3_24))
+              (portRef CEA (instanceRef pdp_ram_1_3_24))
+              (portRef OCEA (instanceRef pdp_ram_2_0_23))
+              (portRef CEA (instanceRef pdp_ram_2_0_23))
+              (portRef OCEA (instanceRef pdp_ram_2_1_22))
+              (portRef CEA (instanceRef pdp_ram_2_1_22))
+              (portRef OCEA (instanceRef pdp_ram_2_2_21))
+              (portRef CEA (instanceRef pdp_ram_2_2_21))
+              (portRef OCEA (instanceRef pdp_ram_2_3_20))
+              (portRef CEA (instanceRef pdp_ram_2_3_20))
+              (portRef OCEA (instanceRef pdp_ram_3_0_19))
+              (portRef CEA (instanceRef pdp_ram_3_0_19))
+              (portRef OCEA (instanceRef pdp_ram_3_1_18))
+              (portRef CEA (instanceRef pdp_ram_3_1_18))
+              (portRef OCEA (instanceRef pdp_ram_3_2_17))
+              (portRef CEA (instanceRef pdp_ram_3_2_17))
+              (portRef OCEA (instanceRef pdp_ram_3_3_16))
+              (portRef CEA (instanceRef pdp_ram_3_3_16))
+              (portRef OCEA (instanceRef pdp_ram_4_0_15))
+              (portRef CEA (instanceRef pdp_ram_4_0_15))
+              (portRef OCEA (instanceRef pdp_ram_4_1_14))
+              (portRef CEA (instanceRef pdp_ram_4_1_14))
+              (portRef OCEA (instanceRef pdp_ram_4_2_13))
+              (portRef CEA (instanceRef pdp_ram_4_2_13))
+              (portRef OCEA (instanceRef pdp_ram_4_3_12))
+              (portRef CEA (instanceRef pdp_ram_4_3_12))
+              (portRef OCEA (instanceRef pdp_ram_5_0_11))
+              (portRef CEA (instanceRef pdp_ram_5_0_11))
+              (portRef OCEA (instanceRef pdp_ram_5_1_10))
+              (portRef CEA (instanceRef pdp_ram_5_1_10))
+              (portRef OCEA (instanceRef pdp_ram_5_2_9))
+              (portRef CEA (instanceRef pdp_ram_5_2_9))
+              (portRef OCEA (instanceRef pdp_ram_5_3_8))
+              (portRef CEA (instanceRef pdp_ram_5_3_8))
+              (portRef OCEA (instanceRef pdp_ram_6_0_7))
+              (portRef CEA (instanceRef pdp_ram_6_0_7))
+              (portRef OCEA (instanceRef pdp_ram_6_1_6))
+              (portRef CEA (instanceRef pdp_ram_6_1_6))
+              (portRef OCEA (instanceRef pdp_ram_6_2_5))
+              (portRef CEA (instanceRef pdp_ram_6_2_5))
+              (portRef OCEA (instanceRef pdp_ram_6_3_4))
+              (portRef CEA (instanceRef pdp_ram_6_3_4))
+              (portRef OCEA (instanceRef pdp_ram_7_0_3))
+              (portRef CEA (instanceRef pdp_ram_7_0_3))
+              (portRef OCEA (instanceRef pdp_ram_7_1_2))
+              (portRef CEA (instanceRef pdp_ram_7_1_2))
+              (portRef OCEA (instanceRef pdp_ram_7_2_1))
+              (portRef CEA (instanceRef pdp_ram_7_2_1))
+              (portRef OCEA (instanceRef pdp_ram_7_3_0))
+              (portRef CEA (instanceRef pdp_ram_7_3_0))
+              (portRef SP (instanceRef FF_81))
+              (portRef SP (instanceRef FF_80))
+              (portRef SP (instanceRef FF_79))
+              (portRef SP (instanceRef FF_78))
+              (portRef SP (instanceRef FF_77))
+              (portRef SP (instanceRef FF_76))
+              (portRef SP (instanceRef FF_75))
+              (portRef SP (instanceRef FF_74))
+              (portRef SP (instanceRef FF_73))
+              (portRef SP (instanceRef FF_72))
+              (portRef SP (instanceRef FF_71))
+              (portRef SP (instanceRef FF_70))
+              (portRef SP (instanceRef FF_69))
+              (portRef SP (instanceRef FF_68))
+              (portRef SP (instanceRef FF_67))
+              (portRef SP (instanceRef FF_51))
+              (portRef SP (instanceRef FF_50))
+              (portRef SP (instanceRef FF_49))
+              (portRef SP (instanceRef FF_48))
+              (portRef SP (instanceRef FF_47))
+              (portRef SP (instanceRef FF_46))
+              (portRef SP (instanceRef FF_45))
+              (portRef SP (instanceRef FF_44))
+              (portRef SP (instanceRef FF_43))
+              (portRef SP (instanceRef FF_42))
+              (portRef SP (instanceRef FF_41))
+              (portRef SP (instanceRef FF_40))
+              (portRef SP (instanceRef FF_39))
+              (portRef SP (instanceRef FF_38))
+              (portRef SP (instanceRef FF_37))
+              (portRef B0 (instanceRef g_cmp_0))
+              (portRef B1 (instanceRef g_cmp_0))
+              (portRef B0 (instanceRef g_cmp_1))
+              (portRef B1 (instanceRef g_cmp_1))
+              (portRef B0 (instanceRef g_cmp_2))
+              (portRef B1 (instanceRef g_cmp_2))
+              (portRef B0 (instanceRef g_cmp_3))
+              (portRef B1 (instanceRef g_cmp_3))
+              (portRef B0 (instanceRef g_cmp_4))
+              (portRef B1 (instanceRef g_cmp_4))
+              (portRef B0 (instanceRef g_cmp_5))
+              (portRef B1 (instanceRef g_cmp_5))
+              (portRef B0 (instanceRef g_cmp_6))
+              (portRef B1 (instanceRef g_cmp_6))
+              (portRef B1 (instanceRef af_set_cmp_ci_a))))
+          (net x
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_ci_a))
+              (portRef CIN (instanceRef bdcnt_bctr_cia))
+              (portRef CIN (instanceRef e_cmp_ci_a))
+              (portRef CIN (instanceRef g_cmp_ci_a))
+              (portRef CIN (instanceRef w_ctr_cia))
+              (portRef CIN (instanceRef r_ctr_cia))
+              (portRef CIN (instanceRef precin_inst636))))
+          (net cmp_ci_2
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_0))
+              (portRef COUT (instanceRef af_set_cmp_ci_a))))
+          (net wcnt_reg_0
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_0))
+              (portRef Q (instanceRef FF_15))))
+          (net wcnt_reg_1
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_0))
+              (portRef Q (instanceRef FF_14))))
+          (net co0_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_1))
+              (portRef COUT (instanceRef af_set_cmp_0))))
+          (net wcnt_reg_2
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_1))
+              (portRef Q (instanceRef FF_13))))
+          (net wcnt_reg_3
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_1))
+              (portRef Q (instanceRef FF_12))))
+          (net co1_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_2))
+              (portRef COUT (instanceRef af_set_cmp_1))))
+          (net wcnt_reg_4
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_2))
+              (portRef Q (instanceRef FF_11))))
+          (net wcnt_reg_5
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_2))
+              (portRef Q (instanceRef FF_10))))
+          (net co2_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_3))
+              (portRef COUT (instanceRef af_set_cmp_2))))
+          (net wcnt_reg_6
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_3))
+              (portRef Q (instanceRef FF_9))))
+          (net wcnt_reg_7
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_3))
+              (portRef Q (instanceRef FF_8))))
+          (net co3_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_4))
+              (portRef COUT (instanceRef af_set_cmp_3))))
+          (net wcnt_reg_8
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_4))
+              (portRef Q (instanceRef FF_7))))
+          (net wcnt_reg_9
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_4))
+              (portRef Q (instanceRef FF_6))))
+          (net co4_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_5))
+              (portRef COUT (instanceRef af_set_cmp_4))))
+          (net wcnt_reg_10
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_5))
+              (portRef Q (instanceRef FF_5))))
+          (net wcnt_reg_11
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_5))
+              (portRef Q (instanceRef FF_4))))
+          (net co5_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_6))
+              (portRef COUT (instanceRef af_set_cmp_5))))
+          (net wcnt_reg_12
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_6))
+              (portRef Q (instanceRef FF_3))))
+          (net wcnt_reg_13
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_6))
+              (portRef Q (instanceRef FF_2))))
+          (net co6_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_7))
+              (portRef COUT (instanceRef af_set_cmp_6))))
+          (net wcnt_reg_14
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_7))
+              (portRef Q (instanceRef FF_1))))
+          (net af_set
+            (joined
+              (portRef S0 (instanceRef a2))
+              (portRef D (instanceRef FF_0))))
+          (net scuba_vhi
+            (joined
+              (portRef Z (instanceRef scuba_vhi_inst))
+              (portRef OCEB (instanceRef pdp_ram_0_0_31))
+              (portRef WEA (instanceRef pdp_ram_0_0_31))
+              (portRef OCEB (instanceRef pdp_ram_0_1_30))
+              (portRef WEA (instanceRef pdp_ram_0_1_30))
+              (portRef OCEB (instanceRef pdp_ram_0_2_29))
+              (portRef WEA (instanceRef pdp_ram_0_2_29))
+              (portRef OCEB (instanceRef pdp_ram_0_3_28))
+              (portRef WEA (instanceRef pdp_ram_0_3_28))
+              (portRef OCEB (instanceRef pdp_ram_1_0_27))
+              (portRef WEA (instanceRef pdp_ram_1_0_27))
+              (portRef OCEB (instanceRef pdp_ram_1_1_26))
+              (portRef WEA (instanceRef pdp_ram_1_1_26))
+              (portRef OCEB (instanceRef pdp_ram_1_2_25))
+              (portRef WEA (instanceRef pdp_ram_1_2_25))
+              (portRef OCEB (instanceRef pdp_ram_1_3_24))
+              (portRef WEA (instanceRef pdp_ram_1_3_24))
+              (portRef OCEB (instanceRef pdp_ram_2_0_23))
+              (portRef WEA (instanceRef pdp_ram_2_0_23))
+              (portRef OCEB (instanceRef pdp_ram_2_1_22))
+              (portRef WEA (instanceRef pdp_ram_2_1_22))
+              (portRef OCEB (instanceRef pdp_ram_2_2_21))
+              (portRef WEA (instanceRef pdp_ram_2_2_21))
+              (portRef OCEB (instanceRef pdp_ram_2_3_20))
+              (portRef WEA (instanceRef pdp_ram_2_3_20))
+              (portRef OCEB (instanceRef pdp_ram_3_0_19))
+              (portRef WEA (instanceRef pdp_ram_3_0_19))
+              (portRef OCEB (instanceRef pdp_ram_3_1_18))
+              (portRef WEA (instanceRef pdp_ram_3_1_18))
+              (portRef OCEB (instanceRef pdp_ram_3_2_17))
+              (portRef WEA (instanceRef pdp_ram_3_2_17))
+              (portRef OCEB (instanceRef pdp_ram_3_3_16))
+              (portRef WEA (instanceRef pdp_ram_3_3_16))
+              (portRef OCEB (instanceRef pdp_ram_4_0_15))
+              (portRef WEA (instanceRef pdp_ram_4_0_15))
+              (portRef OCEB (instanceRef pdp_ram_4_1_14))
+              (portRef WEA (instanceRef pdp_ram_4_1_14))
+              (portRef OCEB (instanceRef pdp_ram_4_2_13))
+              (portRef WEA (instanceRef pdp_ram_4_2_13))
+              (portRef OCEB (instanceRef pdp_ram_4_3_12))
+              (portRef WEA (instanceRef pdp_ram_4_3_12))
+              (portRef OCEB (instanceRef pdp_ram_5_0_11))
+              (portRef WEA (instanceRef pdp_ram_5_0_11))
+              (portRef OCEB (instanceRef pdp_ram_5_1_10))
+              (portRef WEA (instanceRef pdp_ram_5_1_10))
+              (portRef OCEB (instanceRef pdp_ram_5_2_9))
+              (portRef WEA (instanceRef pdp_ram_5_2_9))
+              (portRef OCEB (instanceRef pdp_ram_5_3_8))
+              (portRef WEA (instanceRef pdp_ram_5_3_8))
+              (portRef OCEB (instanceRef pdp_ram_6_0_7))
+              (portRef WEA (instanceRef pdp_ram_6_0_7))
+              (portRef OCEB (instanceRef pdp_ram_6_1_6))
+              (portRef WEA (instanceRef pdp_ram_6_1_6))
+              (portRef OCEB (instanceRef pdp_ram_6_2_5))
+              (portRef WEA (instanceRef pdp_ram_6_2_5))
+              (portRef OCEB (instanceRef pdp_ram_6_3_4))
+              (portRef WEA (instanceRef pdp_ram_6_3_4))
+              (portRef OCEB (instanceRef pdp_ram_7_0_3))
+              (portRef WEA (instanceRef pdp_ram_7_0_3))
+              (portRef OCEB (instanceRef pdp_ram_7_1_2))
+              (portRef WEA (instanceRef pdp_ram_7_1_2))
+              (portRef OCEB (instanceRef pdp_ram_7_2_1))
+              (portRef WEA (instanceRef pdp_ram_7_2_1))
+              (portRef OCEB (instanceRef pdp_ram_7_3_0))
+              (portRef WEA (instanceRef pdp_ram_7_3_0))
+              (portRef C1 (instanceRef bdcnt_bctr_cia))
+              (portRef C0 (instanceRef bdcnt_bctr_cia))
+              (portRef D1 (instanceRef bdcnt_bctr_cia))
+              (portRef D0 (instanceRef bdcnt_bctr_cia))
+              (portRef D1 (instanceRef bdcnt_bctr_0))
+              (portRef D0 (instanceRef bdcnt_bctr_0))
+              (portRef C1 (instanceRef bdcnt_bctr_0))
+              (portRef C0 (instanceRef bdcnt_bctr_0))
+              (portRef D1 (instanceRef bdcnt_bctr_1))
+              (portRef D0 (instanceRef bdcnt_bctr_1))
+              (portRef C1 (instanceRef bdcnt_bctr_1))
+              (portRef C0 (instanceRef bdcnt_bctr_1))
+              (portRef D1 (instanceRef bdcnt_bctr_2))
+              (portRef D0 (instanceRef bdcnt_bctr_2))
+              (portRef C1 (instanceRef bdcnt_bctr_2))
+              (portRef C0 (instanceRef bdcnt_bctr_2))
+              (portRef D1 (instanceRef bdcnt_bctr_3))
+              (portRef D0 (instanceRef bdcnt_bctr_3))
+              (portRef C1 (instanceRef bdcnt_bctr_3))
+              (portRef C0 (instanceRef bdcnt_bctr_3))
+              (portRef D1 (instanceRef bdcnt_bctr_4))
+              (portRef D0 (instanceRef bdcnt_bctr_4))
+              (portRef C1 (instanceRef bdcnt_bctr_4))
+              (portRef C0 (instanceRef bdcnt_bctr_4))
+              (portRef D1 (instanceRef bdcnt_bctr_5))
+              (portRef D0 (instanceRef bdcnt_bctr_5))
+              (portRef C1 (instanceRef bdcnt_bctr_5))
+              (portRef C0 (instanceRef bdcnt_bctr_5))
+              (portRef D1 (instanceRef bdcnt_bctr_6))
+              (portRef D0 (instanceRef bdcnt_bctr_6))
+              (portRef C1 (instanceRef bdcnt_bctr_6))
+              (portRef C0 (instanceRef bdcnt_bctr_6))
+              (portRef D1 (instanceRef bdcnt_bctr_7))
+              (portRef D0 (instanceRef bdcnt_bctr_7))
+              (portRef C1 (instanceRef bdcnt_bctr_7))
+              (portRef C0 (instanceRef bdcnt_bctr_7))
+              (portRef C1 (instanceRef e_cmp_ci_a))
+              (portRef C0 (instanceRef e_cmp_ci_a))
+              (portRef D1 (instanceRef e_cmp_ci_a))
+              (portRef D0 (instanceRef e_cmp_ci_a))
+              (portRef B1 (instanceRef e_cmp_ci_a))
+              (portRef B0 (instanceRef e_cmp_ci_a))
+              (portRef A1 (instanceRef e_cmp_ci_a))
+              (portRef A0 (instanceRef e_cmp_ci_a))
+              (portRef D1 (instanceRef e_cmp_0))
+              (portRef D0 (instanceRef e_cmp_0))
+              (portRef C1 (instanceRef e_cmp_0))
+              (portRef C0 (instanceRef e_cmp_0))
+              (portRef D1 (instanceRef e_cmp_1))
+              (portRef D0 (instanceRef e_cmp_1))
+              (portRef C1 (instanceRef e_cmp_1))
+              (portRef C0 (instanceRef e_cmp_1))
+              (portRef D1 (instanceRef e_cmp_2))
+              (portRef D0 (instanceRef e_cmp_2))
+              (portRef C1 (instanceRef e_cmp_2))
+              (portRef C0 (instanceRef e_cmp_2))
+              (portRef D1 (instanceRef e_cmp_3))
+              (portRef D0 (instanceRef e_cmp_3))
+              (portRef C1 (instanceRef e_cmp_3))
+              (portRef C0 (instanceRef e_cmp_3))
+              (portRef D1 (instanceRef e_cmp_4))
+              (portRef D0 (instanceRef e_cmp_4))
+              (portRef C1 (instanceRef e_cmp_4))
+              (portRef C0 (instanceRef e_cmp_4))
+              (portRef D1 (instanceRef e_cmp_5))
+              (portRef D0 (instanceRef e_cmp_5))
+              (portRef C1 (instanceRef e_cmp_5))
+              (portRef C0 (instanceRef e_cmp_5))
+              (portRef D1 (instanceRef e_cmp_6))
+              (portRef D0 (instanceRef e_cmp_6))
+              (portRef C1 (instanceRef e_cmp_6))
+              (portRef C0 (instanceRef e_cmp_6))
+              (portRef D1 (instanceRef e_cmp_7))
+              (portRef D0 (instanceRef e_cmp_7))
+              (portRef C1 (instanceRef e_cmp_7))
+              (portRef C0 (instanceRef e_cmp_7))
+              (portRef C1 (instanceRef a0))
+              (portRef C0 (instanceRef a0))
+              (portRef D1 (instanceRef a0))
+              (portRef D0 (instanceRef a0))
+              (portRef C1 (instanceRef g_cmp_ci_a))
+              (portRef C0 (instanceRef g_cmp_ci_a))
+              (portRef D1 (instanceRef g_cmp_ci_a))
+              (portRef D0 (instanceRef g_cmp_ci_a))
+              (portRef B1 (instanceRef g_cmp_ci_a))
+              (portRef B0 (instanceRef g_cmp_ci_a))
+              (portRef A1 (instanceRef g_cmp_ci_a))
+              (portRef A0 (instanceRef g_cmp_ci_a))
+              (portRef D1 (instanceRef g_cmp_0))
+              (portRef D0 (instanceRef g_cmp_0))
+              (portRef C1 (instanceRef g_cmp_0))
+              (portRef C0 (instanceRef g_cmp_0))
+              (portRef D1 (instanceRef g_cmp_1))
+              (portRef D0 (instanceRef g_cmp_1))
+              (portRef C1 (instanceRef g_cmp_1))
+              (portRef C0 (instanceRef g_cmp_1))
+              (portRef D1 (instanceRef g_cmp_2))
+              (portRef D0 (instanceRef g_cmp_2))
+              (portRef C1 (instanceRef g_cmp_2))
+              (portRef C0 (instanceRef g_cmp_2))
+              (portRef D1 (instanceRef g_cmp_3))
+              (portRef D0 (instanceRef g_cmp_3))
+              (portRef C1 (instanceRef g_cmp_3))
+              (portRef C0 (instanceRef g_cmp_3))
+              (portRef D1 (instanceRef g_cmp_4))
+              (portRef D0 (instanceRef g_cmp_4))
+              (portRef C1 (instanceRef g_cmp_4))
+              (portRef C0 (instanceRef g_cmp_4))
+              (portRef D1 (instanceRef g_cmp_5))
+              (portRef D0 (instanceRef g_cmp_5))
+              (portRef C1 (instanceRef g_cmp_5))
+              (portRef C0 (instanceRef g_cmp_5))
+              (portRef D1 (instanceRef g_cmp_6))
+              (portRef D0 (instanceRef g_cmp_6))
+              (portRef C1 (instanceRef g_cmp_6))
+              (portRef C0 (instanceRef g_cmp_6))
+              (portRef D1 (instanceRef g_cmp_7))
+              (portRef D0 (instanceRef g_cmp_7))
+              (portRef C1 (instanceRef g_cmp_7))
+              (portRef C0 (instanceRef g_cmp_7))
+              (portRef C1 (instanceRef a1))
+              (portRef C0 (instanceRef a1))
+              (portRef D1 (instanceRef a1))
+              (portRef D0 (instanceRef a1))
+              (portRef C1 (instanceRef w_ctr_cia))
+              (portRef C0 (instanceRef w_ctr_cia))
+              (portRef D1 (instanceRef w_ctr_cia))
+              (portRef D0 (instanceRef w_ctr_cia))
+              (portRef B1 (instanceRef w_ctr_cia))
+              (portRef A1 (instanceRef w_ctr_cia))
+              (portRef D1 (instanceRef w_ctr_0))
+              (portRef D0 (instanceRef w_ctr_0))
+              (portRef C1 (instanceRef w_ctr_0))
+              (portRef C0 (instanceRef w_ctr_0))
+              (portRef D1 (instanceRef w_ctr_1))
+              (portRef D0 (instanceRef w_ctr_1))
+              (portRef C1 (instanceRef w_ctr_1))
+              (portRef C0 (instanceRef w_ctr_1))
+              (portRef D1 (instanceRef w_ctr_2))
+              (portRef D0 (instanceRef w_ctr_2))
+              (portRef C1 (instanceRef w_ctr_2))
+              (portRef C0 (instanceRef w_ctr_2))
+              (portRef D1 (instanceRef w_ctr_3))
+              (portRef D0 (instanceRef w_ctr_3))
+              (portRef C1 (instanceRef w_ctr_3))
+              (portRef C0 (instanceRef w_ctr_3))
+              (portRef D1 (instanceRef w_ctr_4))
+              (portRef D0 (instanceRef w_ctr_4))
+              (portRef C1 (instanceRef w_ctr_4))
+              (portRef C0 (instanceRef w_ctr_4))
+              (portRef D1 (instanceRef w_ctr_5))
+              (portRef D0 (instanceRef w_ctr_5))
+              (portRef C1 (instanceRef w_ctr_5))
+              (portRef C0 (instanceRef w_ctr_5))
+              (portRef D1 (instanceRef w_ctr_6))
+              (portRef D0 (instanceRef w_ctr_6))
+              (portRef C1 (instanceRef w_ctr_6))
+              (portRef C0 (instanceRef w_ctr_6))
+              (portRef D1 (instanceRef w_ctr_7))
+              (portRef D0 (instanceRef w_ctr_7))
+              (portRef C1 (instanceRef w_ctr_7))
+              (portRef C0 (instanceRef w_ctr_7))
+              (portRef C1 (instanceRef r_ctr_cia))
+              (portRef C0 (instanceRef r_ctr_cia))
+              (portRef D1 (instanceRef r_ctr_cia))
+              (portRef D0 (instanceRef r_ctr_cia))
+              (portRef B1 (instanceRef r_ctr_cia))
+              (portRef A1 (instanceRef r_ctr_cia))
+              (portRef D1 (instanceRef r_ctr_0))
+              (portRef D0 (instanceRef r_ctr_0))
+              (portRef C1 (instanceRef r_ctr_0))
+              (portRef C0 (instanceRef r_ctr_0))
+              (portRef D1 (instanceRef r_ctr_1))
+              (portRef D0 (instanceRef r_ctr_1))
+              (portRef C1 (instanceRef r_ctr_1))
+              (portRef C0 (instanceRef r_ctr_1))
+              (portRef D1 (instanceRef r_ctr_2))
+              (portRef D0 (instanceRef r_ctr_2))
+              (portRef C1 (instanceRef r_ctr_2))
+              (portRef C0 (instanceRef r_ctr_2))
+              (portRef D1 (instanceRef r_ctr_3))
+              (portRef D0 (instanceRef r_ctr_3))
+              (portRef C1 (instanceRef r_ctr_3))
+              (portRef C0 (instanceRef r_ctr_3))
+              (portRef D1 (instanceRef r_ctr_4))
+              (portRef D0 (instanceRef r_ctr_4))
+              (portRef C1 (instanceRef r_ctr_4))
+              (portRef C0 (instanceRef r_ctr_4))
+              (portRef D1 (instanceRef r_ctr_5))
+              (portRef D0 (instanceRef r_ctr_5))
+              (portRef C1 (instanceRef r_ctr_5))
+              (portRef C0 (instanceRef r_ctr_5))
+              (portRef D1 (instanceRef r_ctr_6))
+              (portRef D0 (instanceRef r_ctr_6))
+              (portRef C1 (instanceRef r_ctr_6))
+              (portRef C0 (instanceRef r_ctr_6))
+              (portRef D1 (instanceRef r_ctr_7))
+              (portRef D0 (instanceRef r_ctr_7))
+              (portRef C1 (instanceRef r_ctr_7))
+              (portRef C0 (instanceRef r_ctr_7))
+              (portRef C1 (instanceRef precin_inst636))
+              (portRef C0 (instanceRef precin_inst636))
+              (portRef D1 (instanceRef precin_inst636))
+              (portRef D0 (instanceRef precin_inst636))
+              (portRef B1 (instanceRef precin_inst636))
+              (portRef B0 (instanceRef precin_inst636))
+              (portRef A1 (instanceRef precin_inst636))
+              (portRef A0 (instanceRef precin_inst636))
+              (portRef C1 (instanceRef wcnt_0))
+              (portRef C0 (instanceRef wcnt_0))
+              (portRef D1 (instanceRef wcnt_0))
+              (portRef D0 (instanceRef wcnt_0))
+              (portRef C1 (instanceRef wcnt_1))
+              (portRef C0 (instanceRef wcnt_1))
+              (portRef D1 (instanceRef wcnt_1))
+              (portRef D0 (instanceRef wcnt_1))
+              (portRef C1 (instanceRef wcnt_2))
+              (portRef C0 (instanceRef wcnt_2))
+              (portRef D1 (instanceRef wcnt_2))
+              (portRef D0 (instanceRef wcnt_2))
+              (portRef C1 (instanceRef wcnt_3))
+              (portRef C0 (instanceRef wcnt_3))
+              (portRef D1 (instanceRef wcnt_3))
+              (portRef D0 (instanceRef wcnt_3))
+              (portRef C1 (instanceRef wcnt_4))
+              (portRef C0 (instanceRef wcnt_4))
+              (portRef D1 (instanceRef wcnt_4))
+              (portRef D0 (instanceRef wcnt_4))
+              (portRef C1 (instanceRef wcnt_5))
+              (portRef C0 (instanceRef wcnt_5))
+              (portRef D1 (instanceRef wcnt_5))
+              (portRef D0 (instanceRef wcnt_5))
+              (portRef C1 (instanceRef wcnt_6))
+              (portRef C0 (instanceRef wcnt_6))
+              (portRef D1 (instanceRef wcnt_6))
+              (portRef D0 (instanceRef wcnt_6))
+              (portRef C1 (instanceRef wcnt_7))
+              (portRef C0 (instanceRef wcnt_7))
+              (portRef D1 (instanceRef wcnt_7))
+              (portRef D0 (instanceRef wcnt_7))
+              (portRef C1 (instanceRef wcntd))
+              (portRef C0 (instanceRef wcntd))
+              (portRef D1 (instanceRef wcntd))
+              (portRef D0 (instanceRef wcntd))
+              (portRef C1 (instanceRef af_set_cmp_ci_a))
+              (portRef C0 (instanceRef af_set_cmp_ci_a))
+              (portRef D1 (instanceRef af_set_cmp_ci_a))
+              (portRef D0 (instanceRef af_set_cmp_ci_a))
+              (portRef D1 (instanceRef af_set_cmp_0))
+              (portRef D0 (instanceRef af_set_cmp_0))
+              (portRef C1 (instanceRef af_set_cmp_0))
+              (portRef C0 (instanceRef af_set_cmp_0))
+              (portRef D1 (instanceRef af_set_cmp_1))
+              (portRef D0 (instanceRef af_set_cmp_1))
+              (portRef C1 (instanceRef af_set_cmp_1))
+              (portRef C0 (instanceRef af_set_cmp_1))
+              (portRef D1 (instanceRef af_set_cmp_2))
+              (portRef D0 (instanceRef af_set_cmp_2))
+              (portRef C1 (instanceRef af_set_cmp_2))
+              (portRef C0 (instanceRef af_set_cmp_2))
+              (portRef D1 (instanceRef af_set_cmp_3))
+              (portRef D0 (instanceRef af_set_cmp_3))
+              (portRef C1 (instanceRef af_set_cmp_3))
+              (portRef C0 (instanceRef af_set_cmp_3))
+              (portRef D1 (instanceRef af_set_cmp_4))
+              (portRef D0 (instanceRef af_set_cmp_4))
+              (portRef C1 (instanceRef af_set_cmp_4))
+              (portRef C0 (instanceRef af_set_cmp_4))
+              (portRef D1 (instanceRef af_set_cmp_5))
+              (portRef D0 (instanceRef af_set_cmp_5))
+              (portRef C1 (instanceRef af_set_cmp_5))
+              (portRef C0 (instanceRef af_set_cmp_5))
+              (portRef D1 (instanceRef af_set_cmp_6))
+              (portRef D0 (instanceRef af_set_cmp_6))
+              (portRef C1 (instanceRef af_set_cmp_6))
+              (portRef C0 (instanceRef af_set_cmp_6))
+              (portRef D1 (instanceRef af_set_cmp_7))
+              (portRef D0 (instanceRef af_set_cmp_7))
+              (portRef C1 (instanceRef af_set_cmp_7))
+              (portRef C0 (instanceRef af_set_cmp_7))
+              (portRef C1 (instanceRef a2))
+              (portRef C0 (instanceRef a2))
+              (portRef D1 (instanceRef a2))
+              (portRef D0 (instanceRef a2))))
+          (net scuba_vlo
+            (joined
+              (portRef Z (instanceRef scuba_vlo_inst))
+              (portRef AD3 (instanceRef LUT4_1))
+              (portRef AD3 (instanceRef LUT4_0))
+              (portRef WEB (instanceRef pdp_ram_0_0_31))
+              (portRef ADB2 (instanceRef pdp_ram_0_0_31))
+              (portRef ADA2 (instanceRef pdp_ram_0_0_31))
+              (portRef ADB1 (instanceRef pdp_ram_0_0_31))
+              (portRef ADA1 (instanceRef pdp_ram_0_0_31))
+              (portRef ADB0 (instanceRef pdp_ram_0_0_31))
+              (portRef ADA0 (instanceRef pdp_ram_0_0_31))
+              (portRef DIB17 (instanceRef pdp_ram_0_0_31))
+              (portRef DIA17 (instanceRef pdp_ram_0_0_31))
+              (portRef DIB16 (instanceRef pdp_ram_0_0_31))
+              (portRef DIA16 (instanceRef pdp_ram_0_0_31))
+              (portRef DIB15 (instanceRef pdp_ram_0_0_31))
+              (portRef DIA15 (instanceRef pdp_ram_0_0_31))
+              (portRef DIB14 (instanceRef pdp_ram_0_0_31))
+              (portRef DIA14 (instanceRef pdp_ram_0_0_31))
+              (portRef DIB13 (instanceRef pdp_ram_0_0_31))
+              (portRef DIA13 (instanceRef pdp_ram_0_0_31))
+              (portRef DIB12 (instanceRef pdp_ram_0_0_31))
+              (portRef DIA12 (instanceRef pdp_ram_0_0_31))
+              (portRef DIB11 (instanceRef pdp_ram_0_0_31))
+              (portRef DIA11 (instanceRef pdp_ram_0_0_31))
+              (portRef DIB10 (instanceRef pdp_ram_0_0_31))
+              (portRef DIA10 (instanceRef pdp_ram_0_0_31))
+              (portRef DIB9 (instanceRef pdp_ram_0_0_31))
+              (portRef DIA9 (instanceRef pdp_ram_0_0_31))
+              (portRef DIB8 (instanceRef pdp_ram_0_0_31))
+              (portRef DIB7 (instanceRef pdp_ram_0_0_31))
+              (portRef DIB6 (instanceRef pdp_ram_0_0_31))
+              (portRef DIB5 (instanceRef pdp_ram_0_0_31))
+              (portRef DIB4 (instanceRef pdp_ram_0_0_31))
+              (portRef DIB3 (instanceRef pdp_ram_0_0_31))
+              (portRef DIB2 (instanceRef pdp_ram_0_0_31))
+              (portRef DIB1 (instanceRef pdp_ram_0_0_31))
+              (portRef DIB0 (instanceRef pdp_ram_0_0_31))
+              (portRef WEB (instanceRef pdp_ram_0_1_30))
+              (portRef ADB2 (instanceRef pdp_ram_0_1_30))
+              (portRef ADA2 (instanceRef pdp_ram_0_1_30))
+              (portRef ADB1 (instanceRef pdp_ram_0_1_30))
+              (portRef ADA1 (instanceRef pdp_ram_0_1_30))
+              (portRef ADB0 (instanceRef pdp_ram_0_1_30))
+              (portRef ADA0 (instanceRef pdp_ram_0_1_30))
+              (portRef DIB17 (instanceRef pdp_ram_0_1_30))
+              (portRef DIA17 (instanceRef pdp_ram_0_1_30))
+              (portRef DIB16 (instanceRef pdp_ram_0_1_30))
+              (portRef DIA16 (instanceRef pdp_ram_0_1_30))
+              (portRef DIB15 (instanceRef pdp_ram_0_1_30))
+              (portRef DIA15 (instanceRef pdp_ram_0_1_30))
+              (portRef DIB14 (instanceRef pdp_ram_0_1_30))
+              (portRef DIA14 (instanceRef pdp_ram_0_1_30))
+              (portRef DIB13 (instanceRef pdp_ram_0_1_30))
+              (portRef DIA13 (instanceRef pdp_ram_0_1_30))
+              (portRef DIB12 (instanceRef pdp_ram_0_1_30))
+              (portRef DIA12 (instanceRef pdp_ram_0_1_30))
+              (portRef DIB11 (instanceRef pdp_ram_0_1_30))
+              (portRef DIA11 (instanceRef pdp_ram_0_1_30))
+              (portRef DIB10 (instanceRef pdp_ram_0_1_30))
+              (portRef DIA10 (instanceRef pdp_ram_0_1_30))
+              (portRef DIB9 (instanceRef pdp_ram_0_1_30))
+              (portRef DIA9 (instanceRef pdp_ram_0_1_30))
+              (portRef DIB8 (instanceRef pdp_ram_0_1_30))
+              (portRef DIB7 (instanceRef pdp_ram_0_1_30))
+              (portRef DIB6 (instanceRef pdp_ram_0_1_30))
+              (portRef DIB5 (instanceRef pdp_ram_0_1_30))
+              (portRef DIB4 (instanceRef pdp_ram_0_1_30))
+              (portRef DIB3 (instanceRef pdp_ram_0_1_30))
+              (portRef DIB2 (instanceRef pdp_ram_0_1_30))
+              (portRef DIB1 (instanceRef pdp_ram_0_1_30))
+              (portRef DIB0 (instanceRef pdp_ram_0_1_30))
+              (portRef WEB (instanceRef pdp_ram_0_2_29))
+              (portRef ADB2 (instanceRef pdp_ram_0_2_29))
+              (portRef ADA2 (instanceRef pdp_ram_0_2_29))
+              (portRef ADB1 (instanceRef pdp_ram_0_2_29))
+              (portRef ADA1 (instanceRef pdp_ram_0_2_29))
+              (portRef ADB0 (instanceRef pdp_ram_0_2_29))
+              (portRef ADA0 (instanceRef pdp_ram_0_2_29))
+              (portRef DIB17 (instanceRef pdp_ram_0_2_29))
+              (portRef DIA17 (instanceRef pdp_ram_0_2_29))
+              (portRef DIB16 (instanceRef pdp_ram_0_2_29))
+              (portRef DIA16 (instanceRef pdp_ram_0_2_29))
+              (portRef DIB15 (instanceRef pdp_ram_0_2_29))
+              (portRef DIA15 (instanceRef pdp_ram_0_2_29))
+              (portRef DIB14 (instanceRef pdp_ram_0_2_29))
+              (portRef DIA14 (instanceRef pdp_ram_0_2_29))
+              (portRef DIB13 (instanceRef pdp_ram_0_2_29))
+              (portRef DIA13 (instanceRef pdp_ram_0_2_29))
+              (portRef DIB12 (instanceRef pdp_ram_0_2_29))
+              (portRef DIA12 (instanceRef pdp_ram_0_2_29))
+              (portRef DIB11 (instanceRef pdp_ram_0_2_29))
+              (portRef DIA11 (instanceRef pdp_ram_0_2_29))
+              (portRef DIB10 (instanceRef pdp_ram_0_2_29))
+              (portRef DIA10 (instanceRef pdp_ram_0_2_29))
+              (portRef DIB9 (instanceRef pdp_ram_0_2_29))
+              (portRef DIA9 (instanceRef pdp_ram_0_2_29))
+              (portRef DIB8 (instanceRef pdp_ram_0_2_29))
+              (portRef DIB7 (instanceRef pdp_ram_0_2_29))
+              (portRef DIB6 (instanceRef pdp_ram_0_2_29))
+              (portRef DIB5 (instanceRef pdp_ram_0_2_29))
+              (portRef DIB4 (instanceRef pdp_ram_0_2_29))
+              (portRef DIB3 (instanceRef pdp_ram_0_2_29))
+              (portRef DIB2 (instanceRef pdp_ram_0_2_29))
+              (portRef DIB1 (instanceRef pdp_ram_0_2_29))
+              (portRef DIB0 (instanceRef pdp_ram_0_2_29))
+              (portRef WEB (instanceRef pdp_ram_0_3_28))
+              (portRef ADB2 (instanceRef pdp_ram_0_3_28))
+              (portRef ADA2 (instanceRef pdp_ram_0_3_28))
+              (portRef ADB1 (instanceRef pdp_ram_0_3_28))
+              (portRef ADA1 (instanceRef pdp_ram_0_3_28))
+              (portRef ADB0 (instanceRef pdp_ram_0_3_28))
+              (portRef ADA0 (instanceRef pdp_ram_0_3_28))
+              (portRef DIB17 (instanceRef pdp_ram_0_3_28))
+              (portRef DIA17 (instanceRef pdp_ram_0_3_28))
+              (portRef DIB16 (instanceRef pdp_ram_0_3_28))
+              (portRef DIA16 (instanceRef pdp_ram_0_3_28))
+              (portRef DIB15 (instanceRef pdp_ram_0_3_28))
+              (portRef DIA15 (instanceRef pdp_ram_0_3_28))
+              (portRef DIB14 (instanceRef pdp_ram_0_3_28))
+              (portRef DIA14 (instanceRef pdp_ram_0_3_28))
+              (portRef DIB13 (instanceRef pdp_ram_0_3_28))
+              (portRef DIA13 (instanceRef pdp_ram_0_3_28))
+              (portRef DIB12 (instanceRef pdp_ram_0_3_28))
+              (portRef DIA12 (instanceRef pdp_ram_0_3_28))
+              (portRef DIB11 (instanceRef pdp_ram_0_3_28))
+              (portRef DIA11 (instanceRef pdp_ram_0_3_28))
+              (portRef DIB10 (instanceRef pdp_ram_0_3_28))
+              (portRef DIA10 (instanceRef pdp_ram_0_3_28))
+              (portRef DIB9 (instanceRef pdp_ram_0_3_28))
+              (portRef DIA9 (instanceRef pdp_ram_0_3_28))
+              (portRef DIB8 (instanceRef pdp_ram_0_3_28))
+              (portRef DIB7 (instanceRef pdp_ram_0_3_28))
+              (portRef DIB6 (instanceRef pdp_ram_0_3_28))
+              (portRef DIB5 (instanceRef pdp_ram_0_3_28))
+              (portRef DIB4 (instanceRef pdp_ram_0_3_28))
+              (portRef DIB3 (instanceRef pdp_ram_0_3_28))
+              (portRef DIB2 (instanceRef pdp_ram_0_3_28))
+              (portRef DIB1 (instanceRef pdp_ram_0_3_28))
+              (portRef DIB0 (instanceRef pdp_ram_0_3_28))
+              (portRef WEB (instanceRef pdp_ram_1_0_27))
+              (portRef ADB2 (instanceRef pdp_ram_1_0_27))
+              (portRef ADA2 (instanceRef pdp_ram_1_0_27))
+              (portRef ADB1 (instanceRef pdp_ram_1_0_27))
+              (portRef ADA1 (instanceRef pdp_ram_1_0_27))
+              (portRef ADB0 (instanceRef pdp_ram_1_0_27))
+              (portRef ADA0 (instanceRef pdp_ram_1_0_27))
+              (portRef DIB17 (instanceRef pdp_ram_1_0_27))
+              (portRef DIA17 (instanceRef pdp_ram_1_0_27))
+              (portRef DIB16 (instanceRef pdp_ram_1_0_27))
+              (portRef DIA16 (instanceRef pdp_ram_1_0_27))
+              (portRef DIB15 (instanceRef pdp_ram_1_0_27))
+              (portRef DIA15 (instanceRef pdp_ram_1_0_27))
+              (portRef DIB14 (instanceRef pdp_ram_1_0_27))
+              (portRef DIA14 (instanceRef pdp_ram_1_0_27))
+              (portRef DIB13 (instanceRef pdp_ram_1_0_27))
+              (portRef DIA13 (instanceRef pdp_ram_1_0_27))
+              (portRef DIB12 (instanceRef pdp_ram_1_0_27))
+              (portRef DIA12 (instanceRef pdp_ram_1_0_27))
+              (portRef DIB11 (instanceRef pdp_ram_1_0_27))
+              (portRef DIA11 (instanceRef pdp_ram_1_0_27))
+              (portRef DIB10 (instanceRef pdp_ram_1_0_27))
+              (portRef DIA10 (instanceRef pdp_ram_1_0_27))
+              (portRef DIB9 (instanceRef pdp_ram_1_0_27))
+              (portRef DIA9 (instanceRef pdp_ram_1_0_27))
+              (portRef DIB8 (instanceRef pdp_ram_1_0_27))
+              (portRef DIB7 (instanceRef pdp_ram_1_0_27))
+              (portRef DIB6 (instanceRef pdp_ram_1_0_27))
+              (portRef DIB5 (instanceRef pdp_ram_1_0_27))
+              (portRef DIB4 (instanceRef pdp_ram_1_0_27))
+              (portRef DIB3 (instanceRef pdp_ram_1_0_27))
+              (portRef DIB2 (instanceRef pdp_ram_1_0_27))
+              (portRef DIB1 (instanceRef pdp_ram_1_0_27))
+              (portRef DIB0 (instanceRef pdp_ram_1_0_27))
+              (portRef WEB (instanceRef pdp_ram_1_1_26))
+              (portRef ADB2 (instanceRef pdp_ram_1_1_26))
+              (portRef ADA2 (instanceRef pdp_ram_1_1_26))
+              (portRef ADB1 (instanceRef pdp_ram_1_1_26))
+              (portRef ADA1 (instanceRef pdp_ram_1_1_26))
+              (portRef ADB0 (instanceRef pdp_ram_1_1_26))
+              (portRef ADA0 (instanceRef pdp_ram_1_1_26))
+              (portRef DIB17 (instanceRef pdp_ram_1_1_26))
+              (portRef DIA17 (instanceRef pdp_ram_1_1_26))
+              (portRef DIB16 (instanceRef pdp_ram_1_1_26))
+              (portRef DIA16 (instanceRef pdp_ram_1_1_26))
+              (portRef DIB15 (instanceRef pdp_ram_1_1_26))
+              (portRef DIA15 (instanceRef pdp_ram_1_1_26))
+              (portRef DIB14 (instanceRef pdp_ram_1_1_26))
+              (portRef DIA14 (instanceRef pdp_ram_1_1_26))
+              (portRef DIB13 (instanceRef pdp_ram_1_1_26))
+              (portRef DIA13 (instanceRef pdp_ram_1_1_26))
+              (portRef DIB12 (instanceRef pdp_ram_1_1_26))
+              (portRef DIA12 (instanceRef pdp_ram_1_1_26))
+              (portRef DIB11 (instanceRef pdp_ram_1_1_26))
+              (portRef DIA11 (instanceRef pdp_ram_1_1_26))
+              (portRef DIB10 (instanceRef pdp_ram_1_1_26))
+              (portRef DIA10 (instanceRef pdp_ram_1_1_26))
+              (portRef DIB9 (instanceRef pdp_ram_1_1_26))
+              (portRef DIA9 (instanceRef pdp_ram_1_1_26))
+              (portRef DIB8 (instanceRef pdp_ram_1_1_26))
+              (portRef DIB7 (instanceRef pdp_ram_1_1_26))
+              (portRef DIB6 (instanceRef pdp_ram_1_1_26))
+              (portRef DIB5 (instanceRef pdp_ram_1_1_26))
+              (portRef DIB4 (instanceRef pdp_ram_1_1_26))
+              (portRef DIB3 (instanceRef pdp_ram_1_1_26))
+              (portRef DIB2 (instanceRef pdp_ram_1_1_26))
+              (portRef DIB1 (instanceRef pdp_ram_1_1_26))
+              (portRef DIB0 (instanceRef pdp_ram_1_1_26))
+              (portRef WEB (instanceRef pdp_ram_1_2_25))
+              (portRef ADB2 (instanceRef pdp_ram_1_2_25))
+              (portRef ADA2 (instanceRef pdp_ram_1_2_25))
+              (portRef ADB1 (instanceRef pdp_ram_1_2_25))
+              (portRef ADA1 (instanceRef pdp_ram_1_2_25))
+              (portRef ADB0 (instanceRef pdp_ram_1_2_25))
+              (portRef ADA0 (instanceRef pdp_ram_1_2_25))
+              (portRef DIB17 (instanceRef pdp_ram_1_2_25))
+              (portRef DIA17 (instanceRef pdp_ram_1_2_25))
+              (portRef DIB16 (instanceRef pdp_ram_1_2_25))
+              (portRef DIA16 (instanceRef pdp_ram_1_2_25))
+              (portRef DIB15 (instanceRef pdp_ram_1_2_25))
+              (portRef DIA15 (instanceRef pdp_ram_1_2_25))
+              (portRef DIB14 (instanceRef pdp_ram_1_2_25))
+              (portRef DIA14 (instanceRef pdp_ram_1_2_25))
+              (portRef DIB13 (instanceRef pdp_ram_1_2_25))
+              (portRef DIA13 (instanceRef pdp_ram_1_2_25))
+              (portRef DIB12 (instanceRef pdp_ram_1_2_25))
+              (portRef DIA12 (instanceRef pdp_ram_1_2_25))
+              (portRef DIB11 (instanceRef pdp_ram_1_2_25))
+              (portRef DIA11 (instanceRef pdp_ram_1_2_25))
+              (portRef DIB10 (instanceRef pdp_ram_1_2_25))
+              (portRef DIA10 (instanceRef pdp_ram_1_2_25))
+              (portRef DIB9 (instanceRef pdp_ram_1_2_25))
+              (portRef DIA9 (instanceRef pdp_ram_1_2_25))
+              (portRef DIB8 (instanceRef pdp_ram_1_2_25))
+              (portRef DIB7 (instanceRef pdp_ram_1_2_25))
+              (portRef DIB6 (instanceRef pdp_ram_1_2_25))
+              (portRef DIB5 (instanceRef pdp_ram_1_2_25))
+              (portRef DIB4 (instanceRef pdp_ram_1_2_25))
+              (portRef DIB3 (instanceRef pdp_ram_1_2_25))
+              (portRef DIB2 (instanceRef pdp_ram_1_2_25))
+              (portRef DIB1 (instanceRef pdp_ram_1_2_25))
+              (portRef DIB0 (instanceRef pdp_ram_1_2_25))
+              (portRef WEB (instanceRef pdp_ram_1_3_24))
+              (portRef ADB2 (instanceRef pdp_ram_1_3_24))
+              (portRef ADA2 (instanceRef pdp_ram_1_3_24))
+              (portRef ADB1 (instanceRef pdp_ram_1_3_24))
+              (portRef ADA1 (instanceRef pdp_ram_1_3_24))
+              (portRef ADB0 (instanceRef pdp_ram_1_3_24))
+              (portRef ADA0 (instanceRef pdp_ram_1_3_24))
+              (portRef DIB17 (instanceRef pdp_ram_1_3_24))
+              (portRef DIA17 (instanceRef pdp_ram_1_3_24))
+              (portRef DIB16 (instanceRef pdp_ram_1_3_24))
+              (portRef DIA16 (instanceRef pdp_ram_1_3_24))
+              (portRef DIB15 (instanceRef pdp_ram_1_3_24))
+              (portRef DIA15 (instanceRef pdp_ram_1_3_24))
+              (portRef DIB14 (instanceRef pdp_ram_1_3_24))
+              (portRef DIA14 (instanceRef pdp_ram_1_3_24))
+              (portRef DIB13 (instanceRef pdp_ram_1_3_24))
+              (portRef DIA13 (instanceRef pdp_ram_1_3_24))
+              (portRef DIB12 (instanceRef pdp_ram_1_3_24))
+              (portRef DIA12 (instanceRef pdp_ram_1_3_24))
+              (portRef DIB11 (instanceRef pdp_ram_1_3_24))
+              (portRef DIA11 (instanceRef pdp_ram_1_3_24))
+              (portRef DIB10 (instanceRef pdp_ram_1_3_24))
+              (portRef DIA10 (instanceRef pdp_ram_1_3_24))
+              (portRef DIB9 (instanceRef pdp_ram_1_3_24))
+              (portRef DIA9 (instanceRef pdp_ram_1_3_24))
+              (portRef DIB8 (instanceRef pdp_ram_1_3_24))
+              (portRef DIB7 (instanceRef pdp_ram_1_3_24))
+              (portRef DIB6 (instanceRef pdp_ram_1_3_24))
+              (portRef DIB5 (instanceRef pdp_ram_1_3_24))
+              (portRef DIB4 (instanceRef pdp_ram_1_3_24))
+              (portRef DIB3 (instanceRef pdp_ram_1_3_24))
+              (portRef DIB2 (instanceRef pdp_ram_1_3_24))
+              (portRef DIB1 (instanceRef pdp_ram_1_3_24))
+              (portRef DIB0 (instanceRef pdp_ram_1_3_24))
+              (portRef WEB (instanceRef pdp_ram_2_0_23))
+              (portRef ADB2 (instanceRef pdp_ram_2_0_23))
+              (portRef ADA2 (instanceRef pdp_ram_2_0_23))
+              (portRef ADB1 (instanceRef pdp_ram_2_0_23))
+              (portRef ADA1 (instanceRef pdp_ram_2_0_23))
+              (portRef ADB0 (instanceRef pdp_ram_2_0_23))
+              (portRef ADA0 (instanceRef pdp_ram_2_0_23))
+              (portRef DIB17 (instanceRef pdp_ram_2_0_23))
+              (portRef DIA17 (instanceRef pdp_ram_2_0_23))
+              (portRef DIB16 (instanceRef pdp_ram_2_0_23))
+              (portRef DIA16 (instanceRef pdp_ram_2_0_23))
+              (portRef DIB15 (instanceRef pdp_ram_2_0_23))
+              (portRef DIA15 (instanceRef pdp_ram_2_0_23))
+              (portRef DIB14 (instanceRef pdp_ram_2_0_23))
+              (portRef DIA14 (instanceRef pdp_ram_2_0_23))
+              (portRef DIB13 (instanceRef pdp_ram_2_0_23))
+              (portRef DIA13 (instanceRef pdp_ram_2_0_23))
+              (portRef DIB12 (instanceRef pdp_ram_2_0_23))
+              (portRef DIA12 (instanceRef pdp_ram_2_0_23))
+              (portRef DIB11 (instanceRef pdp_ram_2_0_23))
+              (portRef DIA11 (instanceRef pdp_ram_2_0_23))
+              (portRef DIB10 (instanceRef pdp_ram_2_0_23))
+              (portRef DIA10 (instanceRef pdp_ram_2_0_23))
+              (portRef DIB9 (instanceRef pdp_ram_2_0_23))
+              (portRef DIA9 (instanceRef pdp_ram_2_0_23))
+              (portRef DIB8 (instanceRef pdp_ram_2_0_23))
+              (portRef DIB7 (instanceRef pdp_ram_2_0_23))
+              (portRef DIB6 (instanceRef pdp_ram_2_0_23))
+              (portRef DIB5 (instanceRef pdp_ram_2_0_23))
+              (portRef DIB4 (instanceRef pdp_ram_2_0_23))
+              (portRef DIB3 (instanceRef pdp_ram_2_0_23))
+              (portRef DIB2 (instanceRef pdp_ram_2_0_23))
+              (portRef DIB1 (instanceRef pdp_ram_2_0_23))
+              (portRef DIB0 (instanceRef pdp_ram_2_0_23))
+              (portRef WEB (instanceRef pdp_ram_2_1_22))
+              (portRef ADB2 (instanceRef pdp_ram_2_1_22))
+              (portRef ADA2 (instanceRef pdp_ram_2_1_22))
+              (portRef ADB1 (instanceRef pdp_ram_2_1_22))
+              (portRef ADA1 (instanceRef pdp_ram_2_1_22))
+              (portRef ADB0 (instanceRef pdp_ram_2_1_22))
+              (portRef ADA0 (instanceRef pdp_ram_2_1_22))
+              (portRef DIB17 (instanceRef pdp_ram_2_1_22))
+              (portRef DIA17 (instanceRef pdp_ram_2_1_22))
+              (portRef DIB16 (instanceRef pdp_ram_2_1_22))
+              (portRef DIA16 (instanceRef pdp_ram_2_1_22))
+              (portRef DIB15 (instanceRef pdp_ram_2_1_22))
+              (portRef DIA15 (instanceRef pdp_ram_2_1_22))
+              (portRef DIB14 (instanceRef pdp_ram_2_1_22))
+              (portRef DIA14 (instanceRef pdp_ram_2_1_22))
+              (portRef DIB13 (instanceRef pdp_ram_2_1_22))
+              (portRef DIA13 (instanceRef pdp_ram_2_1_22))
+              (portRef DIB12 (instanceRef pdp_ram_2_1_22))
+              (portRef DIA12 (instanceRef pdp_ram_2_1_22))
+              (portRef DIB11 (instanceRef pdp_ram_2_1_22))
+              (portRef DIA11 (instanceRef pdp_ram_2_1_22))
+              (portRef DIB10 (instanceRef pdp_ram_2_1_22))
+              (portRef DIA10 (instanceRef pdp_ram_2_1_22))
+              (portRef DIB9 (instanceRef pdp_ram_2_1_22))
+              (portRef DIA9 (instanceRef pdp_ram_2_1_22))
+              (portRef DIB8 (instanceRef pdp_ram_2_1_22))
+              (portRef DIB7 (instanceRef pdp_ram_2_1_22))
+              (portRef DIB6 (instanceRef pdp_ram_2_1_22))
+              (portRef DIB5 (instanceRef pdp_ram_2_1_22))
+              (portRef DIB4 (instanceRef pdp_ram_2_1_22))
+              (portRef DIB3 (instanceRef pdp_ram_2_1_22))
+              (portRef DIB2 (instanceRef pdp_ram_2_1_22))
+              (portRef DIB1 (instanceRef pdp_ram_2_1_22))
+              (portRef DIB0 (instanceRef pdp_ram_2_1_22))
+              (portRef WEB (instanceRef pdp_ram_2_2_21))
+              (portRef ADB2 (instanceRef pdp_ram_2_2_21))
+              (portRef ADA2 (instanceRef pdp_ram_2_2_21))
+              (portRef ADB1 (instanceRef pdp_ram_2_2_21))
+              (portRef ADA1 (instanceRef pdp_ram_2_2_21))
+              (portRef ADB0 (instanceRef pdp_ram_2_2_21))
+              (portRef ADA0 (instanceRef pdp_ram_2_2_21))
+              (portRef DIB17 (instanceRef pdp_ram_2_2_21))
+              (portRef DIA17 (instanceRef pdp_ram_2_2_21))
+              (portRef DIB16 (instanceRef pdp_ram_2_2_21))
+              (portRef DIA16 (instanceRef pdp_ram_2_2_21))
+              (portRef DIB15 (instanceRef pdp_ram_2_2_21))
+              (portRef DIA15 (instanceRef pdp_ram_2_2_21))
+              (portRef DIB14 (instanceRef pdp_ram_2_2_21))
+              (portRef DIA14 (instanceRef pdp_ram_2_2_21))
+              (portRef DIB13 (instanceRef pdp_ram_2_2_21))
+              (portRef DIA13 (instanceRef pdp_ram_2_2_21))
+              (portRef DIB12 (instanceRef pdp_ram_2_2_21))
+              (portRef DIA12 (instanceRef pdp_ram_2_2_21))
+              (portRef DIB11 (instanceRef pdp_ram_2_2_21))
+              (portRef DIA11 (instanceRef pdp_ram_2_2_21))
+              (portRef DIB10 (instanceRef pdp_ram_2_2_21))
+              (portRef DIA10 (instanceRef pdp_ram_2_2_21))
+              (portRef DIB9 (instanceRef pdp_ram_2_2_21))
+              (portRef DIA9 (instanceRef pdp_ram_2_2_21))
+              (portRef DIB8 (instanceRef pdp_ram_2_2_21))
+              (portRef DIB7 (instanceRef pdp_ram_2_2_21))
+              (portRef DIB6 (instanceRef pdp_ram_2_2_21))
+              (portRef DIB5 (instanceRef pdp_ram_2_2_21))
+              (portRef DIB4 (instanceRef pdp_ram_2_2_21))
+              (portRef DIB3 (instanceRef pdp_ram_2_2_21))
+              (portRef DIB2 (instanceRef pdp_ram_2_2_21))
+              (portRef DIB1 (instanceRef pdp_ram_2_2_21))
+              (portRef DIB0 (instanceRef pdp_ram_2_2_21))
+              (portRef WEB (instanceRef pdp_ram_2_3_20))
+              (portRef ADB2 (instanceRef pdp_ram_2_3_20))
+              (portRef ADA2 (instanceRef pdp_ram_2_3_20))
+              (portRef ADB1 (instanceRef pdp_ram_2_3_20))
+              (portRef ADA1 (instanceRef pdp_ram_2_3_20))
+              (portRef ADB0 (instanceRef pdp_ram_2_3_20))
+              (portRef ADA0 (instanceRef pdp_ram_2_3_20))
+              (portRef DIB17 (instanceRef pdp_ram_2_3_20))
+              (portRef DIA17 (instanceRef pdp_ram_2_3_20))
+              (portRef DIB16 (instanceRef pdp_ram_2_3_20))
+              (portRef DIA16 (instanceRef pdp_ram_2_3_20))
+              (portRef DIB15 (instanceRef pdp_ram_2_3_20))
+              (portRef DIA15 (instanceRef pdp_ram_2_3_20))
+              (portRef DIB14 (instanceRef pdp_ram_2_3_20))
+              (portRef DIA14 (instanceRef pdp_ram_2_3_20))
+              (portRef DIB13 (instanceRef pdp_ram_2_3_20))
+              (portRef DIA13 (instanceRef pdp_ram_2_3_20))
+              (portRef DIB12 (instanceRef pdp_ram_2_3_20))
+              (portRef DIA12 (instanceRef pdp_ram_2_3_20))
+              (portRef DIB11 (instanceRef pdp_ram_2_3_20))
+              (portRef DIA11 (instanceRef pdp_ram_2_3_20))
+              (portRef DIB10 (instanceRef pdp_ram_2_3_20))
+              (portRef DIA10 (instanceRef pdp_ram_2_3_20))
+              (portRef DIB9 (instanceRef pdp_ram_2_3_20))
+              (portRef DIA9 (instanceRef pdp_ram_2_3_20))
+              (portRef DIB8 (instanceRef pdp_ram_2_3_20))
+              (portRef DIB7 (instanceRef pdp_ram_2_3_20))
+              (portRef DIB6 (instanceRef pdp_ram_2_3_20))
+              (portRef DIB5 (instanceRef pdp_ram_2_3_20))
+              (portRef DIB4 (instanceRef pdp_ram_2_3_20))
+              (portRef DIB3 (instanceRef pdp_ram_2_3_20))
+              (portRef DIB2 (instanceRef pdp_ram_2_3_20))
+              (portRef DIB1 (instanceRef pdp_ram_2_3_20))
+              (portRef DIB0 (instanceRef pdp_ram_2_3_20))
+              (portRef WEB (instanceRef pdp_ram_3_0_19))
+              (portRef ADB2 (instanceRef pdp_ram_3_0_19))
+              (portRef ADA2 (instanceRef pdp_ram_3_0_19))
+              (portRef ADB1 (instanceRef pdp_ram_3_0_19))
+              (portRef ADA1 (instanceRef pdp_ram_3_0_19))
+              (portRef ADB0 (instanceRef pdp_ram_3_0_19))
+              (portRef ADA0 (instanceRef pdp_ram_3_0_19))
+              (portRef DIB17 (instanceRef pdp_ram_3_0_19))
+              (portRef DIA17 (instanceRef pdp_ram_3_0_19))
+              (portRef DIB16 (instanceRef pdp_ram_3_0_19))
+              (portRef DIA16 (instanceRef pdp_ram_3_0_19))
+              (portRef DIB15 (instanceRef pdp_ram_3_0_19))
+              (portRef DIA15 (instanceRef pdp_ram_3_0_19))
+              (portRef DIB14 (instanceRef pdp_ram_3_0_19))
+              (portRef DIA14 (instanceRef pdp_ram_3_0_19))
+              (portRef DIB13 (instanceRef pdp_ram_3_0_19))
+              (portRef DIA13 (instanceRef pdp_ram_3_0_19))
+              (portRef DIB12 (instanceRef pdp_ram_3_0_19))
+              (portRef DIA12 (instanceRef pdp_ram_3_0_19))
+              (portRef DIB11 (instanceRef pdp_ram_3_0_19))
+              (portRef DIA11 (instanceRef pdp_ram_3_0_19))
+              (portRef DIB10 (instanceRef pdp_ram_3_0_19))
+              (portRef DIA10 (instanceRef pdp_ram_3_0_19))
+              (portRef DIB9 (instanceRef pdp_ram_3_0_19))
+              (portRef DIA9 (instanceRef pdp_ram_3_0_19))
+              (portRef DIB8 (instanceRef pdp_ram_3_0_19))
+              (portRef DIB7 (instanceRef pdp_ram_3_0_19))
+              (portRef DIB6 (instanceRef pdp_ram_3_0_19))
+              (portRef DIB5 (instanceRef pdp_ram_3_0_19))
+              (portRef DIB4 (instanceRef pdp_ram_3_0_19))
+              (portRef DIB3 (instanceRef pdp_ram_3_0_19))
+              (portRef DIB2 (instanceRef pdp_ram_3_0_19))
+              (portRef DIB1 (instanceRef pdp_ram_3_0_19))
+              (portRef DIB0 (instanceRef pdp_ram_3_0_19))
+              (portRef WEB (instanceRef pdp_ram_3_1_18))
+              (portRef ADB2 (instanceRef pdp_ram_3_1_18))
+              (portRef ADA2 (instanceRef pdp_ram_3_1_18))
+              (portRef ADB1 (instanceRef pdp_ram_3_1_18))
+              (portRef ADA1 (instanceRef pdp_ram_3_1_18))
+              (portRef ADB0 (instanceRef pdp_ram_3_1_18))
+              (portRef ADA0 (instanceRef pdp_ram_3_1_18))
+              (portRef DIB17 (instanceRef pdp_ram_3_1_18))
+              (portRef DIA17 (instanceRef pdp_ram_3_1_18))
+              (portRef DIB16 (instanceRef pdp_ram_3_1_18))
+              (portRef DIA16 (instanceRef pdp_ram_3_1_18))
+              (portRef DIB15 (instanceRef pdp_ram_3_1_18))
+              (portRef DIA15 (instanceRef pdp_ram_3_1_18))
+              (portRef DIB14 (instanceRef pdp_ram_3_1_18))
+              (portRef DIA14 (instanceRef pdp_ram_3_1_18))
+              (portRef DIB13 (instanceRef pdp_ram_3_1_18))
+              (portRef DIA13 (instanceRef pdp_ram_3_1_18))
+              (portRef DIB12 (instanceRef pdp_ram_3_1_18))
+              (portRef DIA12 (instanceRef pdp_ram_3_1_18))
+              (portRef DIB11 (instanceRef pdp_ram_3_1_18))
+              (portRef DIA11 (instanceRef pdp_ram_3_1_18))
+              (portRef DIB10 (instanceRef pdp_ram_3_1_18))
+              (portRef DIA10 (instanceRef pdp_ram_3_1_18))
+              (portRef DIB9 (instanceRef pdp_ram_3_1_18))
+              (portRef DIA9 (instanceRef pdp_ram_3_1_18))
+              (portRef DIB8 (instanceRef pdp_ram_3_1_18))
+              (portRef DIB7 (instanceRef pdp_ram_3_1_18))
+              (portRef DIB6 (instanceRef pdp_ram_3_1_18))
+              (portRef DIB5 (instanceRef pdp_ram_3_1_18))
+              (portRef DIB4 (instanceRef pdp_ram_3_1_18))
+              (portRef DIB3 (instanceRef pdp_ram_3_1_18))
+              (portRef DIB2 (instanceRef pdp_ram_3_1_18))
+              (portRef DIB1 (instanceRef pdp_ram_3_1_18))
+              (portRef DIB0 (instanceRef pdp_ram_3_1_18))
+              (portRef WEB (instanceRef pdp_ram_3_2_17))
+              (portRef ADB2 (instanceRef pdp_ram_3_2_17))
+              (portRef ADA2 (instanceRef pdp_ram_3_2_17))
+              (portRef ADB1 (instanceRef pdp_ram_3_2_17))
+              (portRef ADA1 (instanceRef pdp_ram_3_2_17))
+              (portRef ADB0 (instanceRef pdp_ram_3_2_17))
+              (portRef ADA0 (instanceRef pdp_ram_3_2_17))
+              (portRef DIB17 (instanceRef pdp_ram_3_2_17))
+              (portRef DIA17 (instanceRef pdp_ram_3_2_17))
+              (portRef DIB16 (instanceRef pdp_ram_3_2_17))
+              (portRef DIA16 (instanceRef pdp_ram_3_2_17))
+              (portRef DIB15 (instanceRef pdp_ram_3_2_17))
+              (portRef DIA15 (instanceRef pdp_ram_3_2_17))
+              (portRef DIB14 (instanceRef pdp_ram_3_2_17))
+              (portRef DIA14 (instanceRef pdp_ram_3_2_17))
+              (portRef DIB13 (instanceRef pdp_ram_3_2_17))
+              (portRef DIA13 (instanceRef pdp_ram_3_2_17))
+              (portRef DIB12 (instanceRef pdp_ram_3_2_17))
+              (portRef DIA12 (instanceRef pdp_ram_3_2_17))
+              (portRef DIB11 (instanceRef pdp_ram_3_2_17))
+              (portRef DIA11 (instanceRef pdp_ram_3_2_17))
+              (portRef DIB10 (instanceRef pdp_ram_3_2_17))
+              (portRef DIA10 (instanceRef pdp_ram_3_2_17))
+              (portRef DIB9 (instanceRef pdp_ram_3_2_17))
+              (portRef DIA9 (instanceRef pdp_ram_3_2_17))
+              (portRef DIB8 (instanceRef pdp_ram_3_2_17))
+              (portRef DIB7 (instanceRef pdp_ram_3_2_17))
+              (portRef DIB6 (instanceRef pdp_ram_3_2_17))
+              (portRef DIB5 (instanceRef pdp_ram_3_2_17))
+              (portRef DIB4 (instanceRef pdp_ram_3_2_17))
+              (portRef DIB3 (instanceRef pdp_ram_3_2_17))
+              (portRef DIB2 (instanceRef pdp_ram_3_2_17))
+              (portRef DIB1 (instanceRef pdp_ram_3_2_17))
+              (portRef DIB0 (instanceRef pdp_ram_3_2_17))
+              (portRef WEB (instanceRef pdp_ram_3_3_16))
+              (portRef ADB2 (instanceRef pdp_ram_3_3_16))
+              (portRef ADA2 (instanceRef pdp_ram_3_3_16))
+              (portRef ADB1 (instanceRef pdp_ram_3_3_16))
+              (portRef ADA1 (instanceRef pdp_ram_3_3_16))
+              (portRef ADB0 (instanceRef pdp_ram_3_3_16))
+              (portRef ADA0 (instanceRef pdp_ram_3_3_16))
+              (portRef DIB17 (instanceRef pdp_ram_3_3_16))
+              (portRef DIA17 (instanceRef pdp_ram_3_3_16))
+              (portRef DIB16 (instanceRef pdp_ram_3_3_16))
+              (portRef DIA16 (instanceRef pdp_ram_3_3_16))
+              (portRef DIB15 (instanceRef pdp_ram_3_3_16))
+              (portRef DIA15 (instanceRef pdp_ram_3_3_16))
+              (portRef DIB14 (instanceRef pdp_ram_3_3_16))
+              (portRef DIA14 (instanceRef pdp_ram_3_3_16))
+              (portRef DIB13 (instanceRef pdp_ram_3_3_16))
+              (portRef DIA13 (instanceRef pdp_ram_3_3_16))
+              (portRef DIB12 (instanceRef pdp_ram_3_3_16))
+              (portRef DIA12 (instanceRef pdp_ram_3_3_16))
+              (portRef DIB11 (instanceRef pdp_ram_3_3_16))
+              (portRef DIA11 (instanceRef pdp_ram_3_3_16))
+              (portRef DIB10 (instanceRef pdp_ram_3_3_16))
+              (portRef DIA10 (instanceRef pdp_ram_3_3_16))
+              (portRef DIB9 (instanceRef pdp_ram_3_3_16))
+              (portRef DIA9 (instanceRef pdp_ram_3_3_16))
+              (portRef DIB8 (instanceRef pdp_ram_3_3_16))
+              (portRef DIB7 (instanceRef pdp_ram_3_3_16))
+              (portRef DIB6 (instanceRef pdp_ram_3_3_16))
+              (portRef DIB5 (instanceRef pdp_ram_3_3_16))
+              (portRef DIB4 (instanceRef pdp_ram_3_3_16))
+              (portRef DIB3 (instanceRef pdp_ram_3_3_16))
+              (portRef DIB2 (instanceRef pdp_ram_3_3_16))
+              (portRef DIB1 (instanceRef pdp_ram_3_3_16))
+              (portRef DIB0 (instanceRef pdp_ram_3_3_16))
+              (portRef WEB (instanceRef pdp_ram_4_0_15))
+              (portRef ADB2 (instanceRef pdp_ram_4_0_15))
+              (portRef ADA2 (instanceRef pdp_ram_4_0_15))
+              (portRef ADB1 (instanceRef pdp_ram_4_0_15))
+              (portRef ADA1 (instanceRef pdp_ram_4_0_15))
+              (portRef ADB0 (instanceRef pdp_ram_4_0_15))
+              (portRef ADA0 (instanceRef pdp_ram_4_0_15))
+              (portRef DIB17 (instanceRef pdp_ram_4_0_15))
+              (portRef DIA17 (instanceRef pdp_ram_4_0_15))
+              (portRef DIB16 (instanceRef pdp_ram_4_0_15))
+              (portRef DIA16 (instanceRef pdp_ram_4_0_15))
+              (portRef DIB15 (instanceRef pdp_ram_4_0_15))
+              (portRef DIA15 (instanceRef pdp_ram_4_0_15))
+              (portRef DIB14 (instanceRef pdp_ram_4_0_15))
+              (portRef DIA14 (instanceRef pdp_ram_4_0_15))
+              (portRef DIB13 (instanceRef pdp_ram_4_0_15))
+              (portRef DIA13 (instanceRef pdp_ram_4_0_15))
+              (portRef DIB12 (instanceRef pdp_ram_4_0_15))
+              (portRef DIA12 (instanceRef pdp_ram_4_0_15))
+              (portRef DIB11 (instanceRef pdp_ram_4_0_15))
+              (portRef DIA11 (instanceRef pdp_ram_4_0_15))
+              (portRef DIB10 (instanceRef pdp_ram_4_0_15))
+              (portRef DIA10 (instanceRef pdp_ram_4_0_15))
+              (portRef DIB9 (instanceRef pdp_ram_4_0_15))
+              (portRef DIA9 (instanceRef pdp_ram_4_0_15))
+              (portRef DIB8 (instanceRef pdp_ram_4_0_15))
+              (portRef DIB7 (instanceRef pdp_ram_4_0_15))
+              (portRef DIB6 (instanceRef pdp_ram_4_0_15))
+              (portRef DIB5 (instanceRef pdp_ram_4_0_15))
+              (portRef DIB4 (instanceRef pdp_ram_4_0_15))
+              (portRef DIB3 (instanceRef pdp_ram_4_0_15))
+              (portRef DIB2 (instanceRef pdp_ram_4_0_15))
+              (portRef DIB1 (instanceRef pdp_ram_4_0_15))
+              (portRef DIB0 (instanceRef pdp_ram_4_0_15))
+              (portRef WEB (instanceRef pdp_ram_4_1_14))
+              (portRef ADB2 (instanceRef pdp_ram_4_1_14))
+              (portRef ADA2 (instanceRef pdp_ram_4_1_14))
+              (portRef ADB1 (instanceRef pdp_ram_4_1_14))
+              (portRef ADA1 (instanceRef pdp_ram_4_1_14))
+              (portRef ADB0 (instanceRef pdp_ram_4_1_14))
+              (portRef ADA0 (instanceRef pdp_ram_4_1_14))
+              (portRef DIB17 (instanceRef pdp_ram_4_1_14))
+              (portRef DIA17 (instanceRef pdp_ram_4_1_14))
+              (portRef DIB16 (instanceRef pdp_ram_4_1_14))
+              (portRef DIA16 (instanceRef pdp_ram_4_1_14))
+              (portRef DIB15 (instanceRef pdp_ram_4_1_14))
+              (portRef DIA15 (instanceRef pdp_ram_4_1_14))
+              (portRef DIB14 (instanceRef pdp_ram_4_1_14))
+              (portRef DIA14 (instanceRef pdp_ram_4_1_14))
+              (portRef DIB13 (instanceRef pdp_ram_4_1_14))
+              (portRef DIA13 (instanceRef pdp_ram_4_1_14))
+              (portRef DIB12 (instanceRef pdp_ram_4_1_14))
+              (portRef DIA12 (instanceRef pdp_ram_4_1_14))
+              (portRef DIB11 (instanceRef pdp_ram_4_1_14))
+              (portRef DIA11 (instanceRef pdp_ram_4_1_14))
+              (portRef DIB10 (instanceRef pdp_ram_4_1_14))
+              (portRef DIA10 (instanceRef pdp_ram_4_1_14))
+              (portRef DIB9 (instanceRef pdp_ram_4_1_14))
+              (portRef DIA9 (instanceRef pdp_ram_4_1_14))
+              (portRef DIB8 (instanceRef pdp_ram_4_1_14))
+              (portRef DIB7 (instanceRef pdp_ram_4_1_14))
+              (portRef DIB6 (instanceRef pdp_ram_4_1_14))
+              (portRef DIB5 (instanceRef pdp_ram_4_1_14))
+              (portRef DIB4 (instanceRef pdp_ram_4_1_14))
+              (portRef DIB3 (instanceRef pdp_ram_4_1_14))
+              (portRef DIB2 (instanceRef pdp_ram_4_1_14))
+              (portRef DIB1 (instanceRef pdp_ram_4_1_14))
+              (portRef DIB0 (instanceRef pdp_ram_4_1_14))
+              (portRef WEB (instanceRef pdp_ram_4_2_13))
+              (portRef ADB2 (instanceRef pdp_ram_4_2_13))
+              (portRef ADA2 (instanceRef pdp_ram_4_2_13))
+              (portRef ADB1 (instanceRef pdp_ram_4_2_13))
+              (portRef ADA1 (instanceRef pdp_ram_4_2_13))
+              (portRef ADB0 (instanceRef pdp_ram_4_2_13))
+              (portRef ADA0 (instanceRef pdp_ram_4_2_13))
+              (portRef DIB17 (instanceRef pdp_ram_4_2_13))
+              (portRef DIA17 (instanceRef pdp_ram_4_2_13))
+              (portRef DIB16 (instanceRef pdp_ram_4_2_13))
+              (portRef DIA16 (instanceRef pdp_ram_4_2_13))
+              (portRef DIB15 (instanceRef pdp_ram_4_2_13))
+              (portRef DIA15 (instanceRef pdp_ram_4_2_13))
+              (portRef DIB14 (instanceRef pdp_ram_4_2_13))
+              (portRef DIA14 (instanceRef pdp_ram_4_2_13))
+              (portRef DIB13 (instanceRef pdp_ram_4_2_13))
+              (portRef DIA13 (instanceRef pdp_ram_4_2_13))
+              (portRef DIB12 (instanceRef pdp_ram_4_2_13))
+              (portRef DIA12 (instanceRef pdp_ram_4_2_13))
+              (portRef DIB11 (instanceRef pdp_ram_4_2_13))
+              (portRef DIA11 (instanceRef pdp_ram_4_2_13))
+              (portRef DIB10 (instanceRef pdp_ram_4_2_13))
+              (portRef DIA10 (instanceRef pdp_ram_4_2_13))
+              (portRef DIB9 (instanceRef pdp_ram_4_2_13))
+              (portRef DIA9 (instanceRef pdp_ram_4_2_13))
+              (portRef DIB8 (instanceRef pdp_ram_4_2_13))
+              (portRef DIB7 (instanceRef pdp_ram_4_2_13))
+              (portRef DIB6 (instanceRef pdp_ram_4_2_13))
+              (portRef DIB5 (instanceRef pdp_ram_4_2_13))
+              (portRef DIB4 (instanceRef pdp_ram_4_2_13))
+              (portRef DIB3 (instanceRef pdp_ram_4_2_13))
+              (portRef DIB2 (instanceRef pdp_ram_4_2_13))
+              (portRef DIB1 (instanceRef pdp_ram_4_2_13))
+              (portRef DIB0 (instanceRef pdp_ram_4_2_13))
+              (portRef WEB (instanceRef pdp_ram_4_3_12))
+              (portRef ADB2 (instanceRef pdp_ram_4_3_12))
+              (portRef ADA2 (instanceRef pdp_ram_4_3_12))
+              (portRef ADB1 (instanceRef pdp_ram_4_3_12))
+              (portRef ADA1 (instanceRef pdp_ram_4_3_12))
+              (portRef ADB0 (instanceRef pdp_ram_4_3_12))
+              (portRef ADA0 (instanceRef pdp_ram_4_3_12))
+              (portRef DIB17 (instanceRef pdp_ram_4_3_12))
+              (portRef DIA17 (instanceRef pdp_ram_4_3_12))
+              (portRef DIB16 (instanceRef pdp_ram_4_3_12))
+              (portRef DIA16 (instanceRef pdp_ram_4_3_12))
+              (portRef DIB15 (instanceRef pdp_ram_4_3_12))
+              (portRef DIA15 (instanceRef pdp_ram_4_3_12))
+              (portRef DIB14 (instanceRef pdp_ram_4_3_12))
+              (portRef DIA14 (instanceRef pdp_ram_4_3_12))
+              (portRef DIB13 (instanceRef pdp_ram_4_3_12))
+              (portRef DIA13 (instanceRef pdp_ram_4_3_12))
+              (portRef DIB12 (instanceRef pdp_ram_4_3_12))
+              (portRef DIA12 (instanceRef pdp_ram_4_3_12))
+              (portRef DIB11 (instanceRef pdp_ram_4_3_12))
+              (portRef DIA11 (instanceRef pdp_ram_4_3_12))
+              (portRef DIB10 (instanceRef pdp_ram_4_3_12))
+              (portRef DIA10 (instanceRef pdp_ram_4_3_12))
+              (portRef DIB9 (instanceRef pdp_ram_4_3_12))
+              (portRef DIA9 (instanceRef pdp_ram_4_3_12))
+              (portRef DIB8 (instanceRef pdp_ram_4_3_12))
+              (portRef DIB7 (instanceRef pdp_ram_4_3_12))
+              (portRef DIB6 (instanceRef pdp_ram_4_3_12))
+              (portRef DIB5 (instanceRef pdp_ram_4_3_12))
+              (portRef DIB4 (instanceRef pdp_ram_4_3_12))
+              (portRef DIB3 (instanceRef pdp_ram_4_3_12))
+              (portRef DIB2 (instanceRef pdp_ram_4_3_12))
+              (portRef DIB1 (instanceRef pdp_ram_4_3_12))
+              (portRef DIB0 (instanceRef pdp_ram_4_3_12))
+              (portRef WEB (instanceRef pdp_ram_5_0_11))
+              (portRef ADB2 (instanceRef pdp_ram_5_0_11))
+              (portRef ADA2 (instanceRef pdp_ram_5_0_11))
+              (portRef ADB1 (instanceRef pdp_ram_5_0_11))
+              (portRef ADA1 (instanceRef pdp_ram_5_0_11))
+              (portRef ADB0 (instanceRef pdp_ram_5_0_11))
+              (portRef ADA0 (instanceRef pdp_ram_5_0_11))
+              (portRef DIB17 (instanceRef pdp_ram_5_0_11))
+              (portRef DIA17 (instanceRef pdp_ram_5_0_11))
+              (portRef DIB16 (instanceRef pdp_ram_5_0_11))
+              (portRef DIA16 (instanceRef pdp_ram_5_0_11))
+              (portRef DIB15 (instanceRef pdp_ram_5_0_11))
+              (portRef DIA15 (instanceRef pdp_ram_5_0_11))
+              (portRef DIB14 (instanceRef pdp_ram_5_0_11))
+              (portRef DIA14 (instanceRef pdp_ram_5_0_11))
+              (portRef DIB13 (instanceRef pdp_ram_5_0_11))
+              (portRef DIA13 (instanceRef pdp_ram_5_0_11))
+              (portRef DIB12 (instanceRef pdp_ram_5_0_11))
+              (portRef DIA12 (instanceRef pdp_ram_5_0_11))
+              (portRef DIB11 (instanceRef pdp_ram_5_0_11))
+              (portRef DIA11 (instanceRef pdp_ram_5_0_11))
+              (portRef DIB10 (instanceRef pdp_ram_5_0_11))
+              (portRef DIA10 (instanceRef pdp_ram_5_0_11))
+              (portRef DIB9 (instanceRef pdp_ram_5_0_11))
+              (portRef DIA9 (instanceRef pdp_ram_5_0_11))
+              (portRef DIB8 (instanceRef pdp_ram_5_0_11))
+              (portRef DIB7 (instanceRef pdp_ram_5_0_11))
+              (portRef DIB6 (instanceRef pdp_ram_5_0_11))
+              (portRef DIB5 (instanceRef pdp_ram_5_0_11))
+              (portRef DIB4 (instanceRef pdp_ram_5_0_11))
+              (portRef DIB3 (instanceRef pdp_ram_5_0_11))
+              (portRef DIB2 (instanceRef pdp_ram_5_0_11))
+              (portRef DIB1 (instanceRef pdp_ram_5_0_11))
+              (portRef DIB0 (instanceRef pdp_ram_5_0_11))
+              (portRef WEB (instanceRef pdp_ram_5_1_10))
+              (portRef ADB2 (instanceRef pdp_ram_5_1_10))
+              (portRef ADA2 (instanceRef pdp_ram_5_1_10))
+              (portRef ADB1 (instanceRef pdp_ram_5_1_10))
+              (portRef ADA1 (instanceRef pdp_ram_5_1_10))
+              (portRef ADB0 (instanceRef pdp_ram_5_1_10))
+              (portRef ADA0 (instanceRef pdp_ram_5_1_10))
+              (portRef DIB17 (instanceRef pdp_ram_5_1_10))
+              (portRef DIA17 (instanceRef pdp_ram_5_1_10))
+              (portRef DIB16 (instanceRef pdp_ram_5_1_10))
+              (portRef DIA16 (instanceRef pdp_ram_5_1_10))
+              (portRef DIB15 (instanceRef pdp_ram_5_1_10))
+              (portRef DIA15 (instanceRef pdp_ram_5_1_10))
+              (portRef DIB14 (instanceRef pdp_ram_5_1_10))
+              (portRef DIA14 (instanceRef pdp_ram_5_1_10))
+              (portRef DIB13 (instanceRef pdp_ram_5_1_10))
+              (portRef DIA13 (instanceRef pdp_ram_5_1_10))
+              (portRef DIB12 (instanceRef pdp_ram_5_1_10))
+              (portRef DIA12 (instanceRef pdp_ram_5_1_10))
+              (portRef DIB11 (instanceRef pdp_ram_5_1_10))
+              (portRef DIA11 (instanceRef pdp_ram_5_1_10))
+              (portRef DIB10 (instanceRef pdp_ram_5_1_10))
+              (portRef DIA10 (instanceRef pdp_ram_5_1_10))
+              (portRef DIB9 (instanceRef pdp_ram_5_1_10))
+              (portRef DIA9 (instanceRef pdp_ram_5_1_10))
+              (portRef DIB8 (instanceRef pdp_ram_5_1_10))
+              (portRef DIB7 (instanceRef pdp_ram_5_1_10))
+              (portRef DIB6 (instanceRef pdp_ram_5_1_10))
+              (portRef DIB5 (instanceRef pdp_ram_5_1_10))
+              (portRef DIB4 (instanceRef pdp_ram_5_1_10))
+              (portRef DIB3 (instanceRef pdp_ram_5_1_10))
+              (portRef DIB2 (instanceRef pdp_ram_5_1_10))
+              (portRef DIB1 (instanceRef pdp_ram_5_1_10))
+              (portRef DIB0 (instanceRef pdp_ram_5_1_10))
+              (portRef WEB (instanceRef pdp_ram_5_2_9))
+              (portRef ADB2 (instanceRef pdp_ram_5_2_9))
+              (portRef ADA2 (instanceRef pdp_ram_5_2_9))
+              (portRef ADB1 (instanceRef pdp_ram_5_2_9))
+              (portRef ADA1 (instanceRef pdp_ram_5_2_9))
+              (portRef ADB0 (instanceRef pdp_ram_5_2_9))
+              (portRef ADA0 (instanceRef pdp_ram_5_2_9))
+              (portRef DIB17 (instanceRef pdp_ram_5_2_9))
+              (portRef DIA17 (instanceRef pdp_ram_5_2_9))
+              (portRef DIB16 (instanceRef pdp_ram_5_2_9))
+              (portRef DIA16 (instanceRef pdp_ram_5_2_9))
+              (portRef DIB15 (instanceRef pdp_ram_5_2_9))
+              (portRef DIA15 (instanceRef pdp_ram_5_2_9))
+              (portRef DIB14 (instanceRef pdp_ram_5_2_9))
+              (portRef DIA14 (instanceRef pdp_ram_5_2_9))
+              (portRef DIB13 (instanceRef pdp_ram_5_2_9))
+              (portRef DIA13 (instanceRef pdp_ram_5_2_9))
+              (portRef DIB12 (instanceRef pdp_ram_5_2_9))
+              (portRef DIA12 (instanceRef pdp_ram_5_2_9))
+              (portRef DIB11 (instanceRef pdp_ram_5_2_9))
+              (portRef DIA11 (instanceRef pdp_ram_5_2_9))
+              (portRef DIB10 (instanceRef pdp_ram_5_2_9))
+              (portRef DIA10 (instanceRef pdp_ram_5_2_9))
+              (portRef DIB9 (instanceRef pdp_ram_5_2_9))
+              (portRef DIA9 (instanceRef pdp_ram_5_2_9))
+              (portRef DIB8 (instanceRef pdp_ram_5_2_9))
+              (portRef DIB7 (instanceRef pdp_ram_5_2_9))
+              (portRef DIB6 (instanceRef pdp_ram_5_2_9))
+              (portRef DIB5 (instanceRef pdp_ram_5_2_9))
+              (portRef DIB4 (instanceRef pdp_ram_5_2_9))
+              (portRef DIB3 (instanceRef pdp_ram_5_2_9))
+              (portRef DIB2 (instanceRef pdp_ram_5_2_9))
+              (portRef DIB1 (instanceRef pdp_ram_5_2_9))
+              (portRef DIB0 (instanceRef pdp_ram_5_2_9))
+              (portRef WEB (instanceRef pdp_ram_5_3_8))
+              (portRef ADB2 (instanceRef pdp_ram_5_3_8))
+              (portRef ADA2 (instanceRef pdp_ram_5_3_8))
+              (portRef ADB1 (instanceRef pdp_ram_5_3_8))
+              (portRef ADA1 (instanceRef pdp_ram_5_3_8))
+              (portRef ADB0 (instanceRef pdp_ram_5_3_8))
+              (portRef ADA0 (instanceRef pdp_ram_5_3_8))
+              (portRef DIB17 (instanceRef pdp_ram_5_3_8))
+              (portRef DIA17 (instanceRef pdp_ram_5_3_8))
+              (portRef DIB16 (instanceRef pdp_ram_5_3_8))
+              (portRef DIA16 (instanceRef pdp_ram_5_3_8))
+              (portRef DIB15 (instanceRef pdp_ram_5_3_8))
+              (portRef DIA15 (instanceRef pdp_ram_5_3_8))
+              (portRef DIB14 (instanceRef pdp_ram_5_3_8))
+              (portRef DIA14 (instanceRef pdp_ram_5_3_8))
+              (portRef DIB13 (instanceRef pdp_ram_5_3_8))
+              (portRef DIA13 (instanceRef pdp_ram_5_3_8))
+              (portRef DIB12 (instanceRef pdp_ram_5_3_8))
+              (portRef DIA12 (instanceRef pdp_ram_5_3_8))
+              (portRef DIB11 (instanceRef pdp_ram_5_3_8))
+              (portRef DIA11 (instanceRef pdp_ram_5_3_8))
+              (portRef DIB10 (instanceRef pdp_ram_5_3_8))
+              (portRef DIA10 (instanceRef pdp_ram_5_3_8))
+              (portRef DIB9 (instanceRef pdp_ram_5_3_8))
+              (portRef DIA9 (instanceRef pdp_ram_5_3_8))
+              (portRef DIB8 (instanceRef pdp_ram_5_3_8))
+              (portRef DIB7 (instanceRef pdp_ram_5_3_8))
+              (portRef DIB6 (instanceRef pdp_ram_5_3_8))
+              (portRef DIB5 (instanceRef pdp_ram_5_3_8))
+              (portRef DIB4 (instanceRef pdp_ram_5_3_8))
+              (portRef DIB3 (instanceRef pdp_ram_5_3_8))
+              (portRef DIB2 (instanceRef pdp_ram_5_3_8))
+              (portRef DIB1 (instanceRef pdp_ram_5_3_8))
+              (portRef DIB0 (instanceRef pdp_ram_5_3_8))
+              (portRef WEB (instanceRef pdp_ram_6_0_7))
+              (portRef ADB2 (instanceRef pdp_ram_6_0_7))
+              (portRef ADA2 (instanceRef pdp_ram_6_0_7))
+              (portRef ADB1 (instanceRef pdp_ram_6_0_7))
+              (portRef ADA1 (instanceRef pdp_ram_6_0_7))
+              (portRef ADB0 (instanceRef pdp_ram_6_0_7))
+              (portRef ADA0 (instanceRef pdp_ram_6_0_7))
+              (portRef DIB17 (instanceRef pdp_ram_6_0_7))
+              (portRef DIA17 (instanceRef pdp_ram_6_0_7))
+              (portRef DIB16 (instanceRef pdp_ram_6_0_7))
+              (portRef DIA16 (instanceRef pdp_ram_6_0_7))
+              (portRef DIB15 (instanceRef pdp_ram_6_0_7))
+              (portRef DIA15 (instanceRef pdp_ram_6_0_7))
+              (portRef DIB14 (instanceRef pdp_ram_6_0_7))
+              (portRef DIA14 (instanceRef pdp_ram_6_0_7))
+              (portRef DIB13 (instanceRef pdp_ram_6_0_7))
+              (portRef DIA13 (instanceRef pdp_ram_6_0_7))
+              (portRef DIB12 (instanceRef pdp_ram_6_0_7))
+              (portRef DIA12 (instanceRef pdp_ram_6_0_7))
+              (portRef DIB11 (instanceRef pdp_ram_6_0_7))
+              (portRef DIA11 (instanceRef pdp_ram_6_0_7))
+              (portRef DIB10 (instanceRef pdp_ram_6_0_7))
+              (portRef DIA10 (instanceRef pdp_ram_6_0_7))
+              (portRef DIB9 (instanceRef pdp_ram_6_0_7))
+              (portRef DIA9 (instanceRef pdp_ram_6_0_7))
+              (portRef DIB8 (instanceRef pdp_ram_6_0_7))
+              (portRef DIB7 (instanceRef pdp_ram_6_0_7))
+              (portRef DIB6 (instanceRef pdp_ram_6_0_7))
+              (portRef DIB5 (instanceRef pdp_ram_6_0_7))
+              (portRef DIB4 (instanceRef pdp_ram_6_0_7))
+              (portRef DIB3 (instanceRef pdp_ram_6_0_7))
+              (portRef DIB2 (instanceRef pdp_ram_6_0_7))
+              (portRef DIB1 (instanceRef pdp_ram_6_0_7))
+              (portRef DIB0 (instanceRef pdp_ram_6_0_7))
+              (portRef WEB (instanceRef pdp_ram_6_1_6))
+              (portRef ADB2 (instanceRef pdp_ram_6_1_6))
+              (portRef ADA2 (instanceRef pdp_ram_6_1_6))
+              (portRef ADB1 (instanceRef pdp_ram_6_1_6))
+              (portRef ADA1 (instanceRef pdp_ram_6_1_6))
+              (portRef ADB0 (instanceRef pdp_ram_6_1_6))
+              (portRef ADA0 (instanceRef pdp_ram_6_1_6))
+              (portRef DIB17 (instanceRef pdp_ram_6_1_6))
+              (portRef DIA17 (instanceRef pdp_ram_6_1_6))
+              (portRef DIB16 (instanceRef pdp_ram_6_1_6))
+              (portRef DIA16 (instanceRef pdp_ram_6_1_6))
+              (portRef DIB15 (instanceRef pdp_ram_6_1_6))
+              (portRef DIA15 (instanceRef pdp_ram_6_1_6))
+              (portRef DIB14 (instanceRef pdp_ram_6_1_6))
+              (portRef DIA14 (instanceRef pdp_ram_6_1_6))
+              (portRef DIB13 (instanceRef pdp_ram_6_1_6))
+              (portRef DIA13 (instanceRef pdp_ram_6_1_6))
+              (portRef DIB12 (instanceRef pdp_ram_6_1_6))
+              (portRef DIA12 (instanceRef pdp_ram_6_1_6))
+              (portRef DIB11 (instanceRef pdp_ram_6_1_6))
+              (portRef DIA11 (instanceRef pdp_ram_6_1_6))
+              (portRef DIB10 (instanceRef pdp_ram_6_1_6))
+              (portRef DIA10 (instanceRef pdp_ram_6_1_6))
+              (portRef DIB9 (instanceRef pdp_ram_6_1_6))
+              (portRef DIA9 (instanceRef pdp_ram_6_1_6))
+              (portRef DIB8 (instanceRef pdp_ram_6_1_6))
+              (portRef DIB7 (instanceRef pdp_ram_6_1_6))
+              (portRef DIB6 (instanceRef pdp_ram_6_1_6))
+              (portRef DIB5 (instanceRef pdp_ram_6_1_6))
+              (portRef DIB4 (instanceRef pdp_ram_6_1_6))
+              (portRef DIB3 (instanceRef pdp_ram_6_1_6))
+              (portRef DIB2 (instanceRef pdp_ram_6_1_6))
+              (portRef DIB1 (instanceRef pdp_ram_6_1_6))
+              (portRef DIB0 (instanceRef pdp_ram_6_1_6))
+              (portRef WEB (instanceRef pdp_ram_6_2_5))
+              (portRef ADB2 (instanceRef pdp_ram_6_2_5))
+              (portRef ADA2 (instanceRef pdp_ram_6_2_5))
+              (portRef ADB1 (instanceRef pdp_ram_6_2_5))
+              (portRef ADA1 (instanceRef pdp_ram_6_2_5))
+              (portRef ADB0 (instanceRef pdp_ram_6_2_5))
+              (portRef ADA0 (instanceRef pdp_ram_6_2_5))
+              (portRef DIB17 (instanceRef pdp_ram_6_2_5))
+              (portRef DIA17 (instanceRef pdp_ram_6_2_5))
+              (portRef DIB16 (instanceRef pdp_ram_6_2_5))
+              (portRef DIA16 (instanceRef pdp_ram_6_2_5))
+              (portRef DIB15 (instanceRef pdp_ram_6_2_5))
+              (portRef DIA15 (instanceRef pdp_ram_6_2_5))
+              (portRef DIB14 (instanceRef pdp_ram_6_2_5))
+              (portRef DIA14 (instanceRef pdp_ram_6_2_5))
+              (portRef DIB13 (instanceRef pdp_ram_6_2_5))
+              (portRef DIA13 (instanceRef pdp_ram_6_2_5))
+              (portRef DIB12 (instanceRef pdp_ram_6_2_5))
+              (portRef DIA12 (instanceRef pdp_ram_6_2_5))
+              (portRef DIB11 (instanceRef pdp_ram_6_2_5))
+              (portRef DIA11 (instanceRef pdp_ram_6_2_5))
+              (portRef DIB10 (instanceRef pdp_ram_6_2_5))
+              (portRef DIA10 (instanceRef pdp_ram_6_2_5))
+              (portRef DIB9 (instanceRef pdp_ram_6_2_5))
+              (portRef DIA9 (instanceRef pdp_ram_6_2_5))
+              (portRef DIB8 (instanceRef pdp_ram_6_2_5))
+              (portRef DIB7 (instanceRef pdp_ram_6_2_5))
+              (portRef DIB6 (instanceRef pdp_ram_6_2_5))
+              (portRef DIB5 (instanceRef pdp_ram_6_2_5))
+              (portRef DIB4 (instanceRef pdp_ram_6_2_5))
+              (portRef DIB3 (instanceRef pdp_ram_6_2_5))
+              (portRef DIB2 (instanceRef pdp_ram_6_2_5))
+              (portRef DIB1 (instanceRef pdp_ram_6_2_5))
+              (portRef DIB0 (instanceRef pdp_ram_6_2_5))
+              (portRef WEB (instanceRef pdp_ram_6_3_4))
+              (portRef ADB2 (instanceRef pdp_ram_6_3_4))
+              (portRef ADA2 (instanceRef pdp_ram_6_3_4))
+              (portRef ADB1 (instanceRef pdp_ram_6_3_4))
+              (portRef ADA1 (instanceRef pdp_ram_6_3_4))
+              (portRef ADB0 (instanceRef pdp_ram_6_3_4))
+              (portRef ADA0 (instanceRef pdp_ram_6_3_4))
+              (portRef DIB17 (instanceRef pdp_ram_6_3_4))
+              (portRef DIA17 (instanceRef pdp_ram_6_3_4))
+              (portRef DIB16 (instanceRef pdp_ram_6_3_4))
+              (portRef DIA16 (instanceRef pdp_ram_6_3_4))
+              (portRef DIB15 (instanceRef pdp_ram_6_3_4))
+              (portRef DIA15 (instanceRef pdp_ram_6_3_4))
+              (portRef DIB14 (instanceRef pdp_ram_6_3_4))
+              (portRef DIA14 (instanceRef pdp_ram_6_3_4))
+              (portRef DIB13 (instanceRef pdp_ram_6_3_4))
+              (portRef DIA13 (instanceRef pdp_ram_6_3_4))
+              (portRef DIB12 (instanceRef pdp_ram_6_3_4))
+              (portRef DIA12 (instanceRef pdp_ram_6_3_4))
+              (portRef DIB11 (instanceRef pdp_ram_6_3_4))
+              (portRef DIA11 (instanceRef pdp_ram_6_3_4))
+              (portRef DIB10 (instanceRef pdp_ram_6_3_4))
+              (portRef DIA10 (instanceRef pdp_ram_6_3_4))
+              (portRef DIB9 (instanceRef pdp_ram_6_3_4))
+              (portRef DIA9 (instanceRef pdp_ram_6_3_4))
+              (portRef DIB8 (instanceRef pdp_ram_6_3_4))
+              (portRef DIB7 (instanceRef pdp_ram_6_3_4))
+              (portRef DIB6 (instanceRef pdp_ram_6_3_4))
+              (portRef DIB5 (instanceRef pdp_ram_6_3_4))
+              (portRef DIB4 (instanceRef pdp_ram_6_3_4))
+              (portRef DIB3 (instanceRef pdp_ram_6_3_4))
+              (portRef DIB2 (instanceRef pdp_ram_6_3_4))
+              (portRef DIB1 (instanceRef pdp_ram_6_3_4))
+              (portRef DIB0 (instanceRef pdp_ram_6_3_4))
+              (portRef WEB (instanceRef pdp_ram_7_0_3))
+              (portRef ADB2 (instanceRef pdp_ram_7_0_3))
+              (portRef ADA2 (instanceRef pdp_ram_7_0_3))
+              (portRef ADB1 (instanceRef pdp_ram_7_0_3))
+              (portRef ADA1 (instanceRef pdp_ram_7_0_3))
+              (portRef ADB0 (instanceRef pdp_ram_7_0_3))
+              (portRef ADA0 (instanceRef pdp_ram_7_0_3))
+              (portRef DIB17 (instanceRef pdp_ram_7_0_3))
+              (portRef DIA17 (instanceRef pdp_ram_7_0_3))
+              (portRef DIB16 (instanceRef pdp_ram_7_0_3))
+              (portRef DIA16 (instanceRef pdp_ram_7_0_3))
+              (portRef DIB15 (instanceRef pdp_ram_7_0_3))
+              (portRef DIA15 (instanceRef pdp_ram_7_0_3))
+              (portRef DIB14 (instanceRef pdp_ram_7_0_3))
+              (portRef DIA14 (instanceRef pdp_ram_7_0_3))
+              (portRef DIB13 (instanceRef pdp_ram_7_0_3))
+              (portRef DIA13 (instanceRef pdp_ram_7_0_3))
+              (portRef DIB12 (instanceRef pdp_ram_7_0_3))
+              (portRef DIA12 (instanceRef pdp_ram_7_0_3))
+              (portRef DIB11 (instanceRef pdp_ram_7_0_3))
+              (portRef DIA11 (instanceRef pdp_ram_7_0_3))
+              (portRef DIB10 (instanceRef pdp_ram_7_0_3))
+              (portRef DIA10 (instanceRef pdp_ram_7_0_3))
+              (portRef DIB9 (instanceRef pdp_ram_7_0_3))
+              (portRef DIA9 (instanceRef pdp_ram_7_0_3))
+              (portRef DIB8 (instanceRef pdp_ram_7_0_3))
+              (portRef DIB7 (instanceRef pdp_ram_7_0_3))
+              (portRef DIB6 (instanceRef pdp_ram_7_0_3))
+              (portRef DIB5 (instanceRef pdp_ram_7_0_3))
+              (portRef DIB4 (instanceRef pdp_ram_7_0_3))
+              (portRef DIB3 (instanceRef pdp_ram_7_0_3))
+              (portRef DIB2 (instanceRef pdp_ram_7_0_3))
+              (portRef DIB1 (instanceRef pdp_ram_7_0_3))
+              (portRef DIB0 (instanceRef pdp_ram_7_0_3))
+              (portRef WEB (instanceRef pdp_ram_7_1_2))
+              (portRef ADB2 (instanceRef pdp_ram_7_1_2))
+              (portRef ADA2 (instanceRef pdp_ram_7_1_2))
+              (portRef ADB1 (instanceRef pdp_ram_7_1_2))
+              (portRef ADA1 (instanceRef pdp_ram_7_1_2))
+              (portRef ADB0 (instanceRef pdp_ram_7_1_2))
+              (portRef ADA0 (instanceRef pdp_ram_7_1_2))
+              (portRef DIB17 (instanceRef pdp_ram_7_1_2))
+              (portRef DIA17 (instanceRef pdp_ram_7_1_2))
+              (portRef DIB16 (instanceRef pdp_ram_7_1_2))
+              (portRef DIA16 (instanceRef pdp_ram_7_1_2))
+              (portRef DIB15 (instanceRef pdp_ram_7_1_2))
+              (portRef DIA15 (instanceRef pdp_ram_7_1_2))
+              (portRef DIB14 (instanceRef pdp_ram_7_1_2))
+              (portRef DIA14 (instanceRef pdp_ram_7_1_2))
+              (portRef DIB13 (instanceRef pdp_ram_7_1_2))
+              (portRef DIA13 (instanceRef pdp_ram_7_1_2))
+              (portRef DIB12 (instanceRef pdp_ram_7_1_2))
+              (portRef DIA12 (instanceRef pdp_ram_7_1_2))
+              (portRef DIB11 (instanceRef pdp_ram_7_1_2))
+              (portRef DIA11 (instanceRef pdp_ram_7_1_2))
+              (portRef DIB10 (instanceRef pdp_ram_7_1_2))
+              (portRef DIA10 (instanceRef pdp_ram_7_1_2))
+              (portRef DIB9 (instanceRef pdp_ram_7_1_2))
+              (portRef DIA9 (instanceRef pdp_ram_7_1_2))
+              (portRef DIB8 (instanceRef pdp_ram_7_1_2))
+              (portRef DIB7 (instanceRef pdp_ram_7_1_2))
+              (portRef DIB6 (instanceRef pdp_ram_7_1_2))
+              (portRef DIB5 (instanceRef pdp_ram_7_1_2))
+              (portRef DIB4 (instanceRef pdp_ram_7_1_2))
+              (portRef DIB3 (instanceRef pdp_ram_7_1_2))
+              (portRef DIB2 (instanceRef pdp_ram_7_1_2))
+              (portRef DIB1 (instanceRef pdp_ram_7_1_2))
+              (portRef DIB0 (instanceRef pdp_ram_7_1_2))
+              (portRef WEB (instanceRef pdp_ram_7_2_1))
+              (portRef ADB2 (instanceRef pdp_ram_7_2_1))
+              (portRef ADA2 (instanceRef pdp_ram_7_2_1))
+              (portRef ADB1 (instanceRef pdp_ram_7_2_1))
+              (portRef ADA1 (instanceRef pdp_ram_7_2_1))
+              (portRef ADB0 (instanceRef pdp_ram_7_2_1))
+              (portRef ADA0 (instanceRef pdp_ram_7_2_1))
+              (portRef DIB17 (instanceRef pdp_ram_7_2_1))
+              (portRef DIA17 (instanceRef pdp_ram_7_2_1))
+              (portRef DIB16 (instanceRef pdp_ram_7_2_1))
+              (portRef DIA16 (instanceRef pdp_ram_7_2_1))
+              (portRef DIB15 (instanceRef pdp_ram_7_2_1))
+              (portRef DIA15 (instanceRef pdp_ram_7_2_1))
+              (portRef DIB14 (instanceRef pdp_ram_7_2_1))
+              (portRef DIA14 (instanceRef pdp_ram_7_2_1))
+              (portRef DIB13 (instanceRef pdp_ram_7_2_1))
+              (portRef DIA13 (instanceRef pdp_ram_7_2_1))
+              (portRef DIB12 (instanceRef pdp_ram_7_2_1))
+              (portRef DIA12 (instanceRef pdp_ram_7_2_1))
+              (portRef DIB11 (instanceRef pdp_ram_7_2_1))
+              (portRef DIA11 (instanceRef pdp_ram_7_2_1))
+              (portRef DIB10 (instanceRef pdp_ram_7_2_1))
+              (portRef DIA10 (instanceRef pdp_ram_7_2_1))
+              (portRef DIB9 (instanceRef pdp_ram_7_2_1))
+              (portRef DIA9 (instanceRef pdp_ram_7_2_1))
+              (portRef DIB8 (instanceRef pdp_ram_7_2_1))
+              (portRef DIB7 (instanceRef pdp_ram_7_2_1))
+              (portRef DIB6 (instanceRef pdp_ram_7_2_1))
+              (portRef DIB5 (instanceRef pdp_ram_7_2_1))
+              (portRef DIB4 (instanceRef pdp_ram_7_2_1))
+              (portRef DIB3 (instanceRef pdp_ram_7_2_1))
+              (portRef DIB2 (instanceRef pdp_ram_7_2_1))
+              (portRef DIB1 (instanceRef pdp_ram_7_2_1))
+              (portRef DIB0 (instanceRef pdp_ram_7_2_1))
+              (portRef WEB (instanceRef pdp_ram_7_3_0))
+              (portRef ADB2 (instanceRef pdp_ram_7_3_0))
+              (portRef ADA2 (instanceRef pdp_ram_7_3_0))
+              (portRef ADB1 (instanceRef pdp_ram_7_3_0))
+              (portRef ADA1 (instanceRef pdp_ram_7_3_0))
+              (portRef ADB0 (instanceRef pdp_ram_7_3_0))
+              (portRef ADA0 (instanceRef pdp_ram_7_3_0))
+              (portRef DIB17 (instanceRef pdp_ram_7_3_0))
+              (portRef DIA17 (instanceRef pdp_ram_7_3_0))
+              (portRef DIB16 (instanceRef pdp_ram_7_3_0))
+              (portRef DIA16 (instanceRef pdp_ram_7_3_0))
+              (portRef DIB15 (instanceRef pdp_ram_7_3_0))
+              (portRef DIA15 (instanceRef pdp_ram_7_3_0))
+              (portRef DIB14 (instanceRef pdp_ram_7_3_0))
+              (portRef DIA14 (instanceRef pdp_ram_7_3_0))
+              (portRef DIB13 (instanceRef pdp_ram_7_3_0))
+              (portRef DIA13 (instanceRef pdp_ram_7_3_0))
+              (portRef DIB12 (instanceRef pdp_ram_7_3_0))
+              (portRef DIA12 (instanceRef pdp_ram_7_3_0))
+              (portRef DIB11 (instanceRef pdp_ram_7_3_0))
+              (portRef DIA11 (instanceRef pdp_ram_7_3_0))
+              (portRef DIB10 (instanceRef pdp_ram_7_3_0))
+              (portRef DIA10 (instanceRef pdp_ram_7_3_0))
+              (portRef DIB9 (instanceRef pdp_ram_7_3_0))
+              (portRef DIA9 (instanceRef pdp_ram_7_3_0))
+              (portRef DIB8 (instanceRef pdp_ram_7_3_0))
+              (portRef DIB7 (instanceRef pdp_ram_7_3_0))
+              (portRef DIB6 (instanceRef pdp_ram_7_3_0))
+              (portRef DIB5 (instanceRef pdp_ram_7_3_0))
+              (portRef DIB4 (instanceRef pdp_ram_7_3_0))
+              (portRef DIB3 (instanceRef pdp_ram_7_3_0))
+              (portRef DIB2 (instanceRef pdp_ram_7_3_0))
+              (portRef DIB1 (instanceRef pdp_ram_7_3_0))
+              (portRef DIB0 (instanceRef pdp_ram_7_3_0))
+              (portRef CD (instanceRef FF_21))
+              (portRef CD (instanceRef FF_20))
+              (portRef CD (instanceRef FF_19))
+              (portRef CD (instanceRef FF_18))
+              (portRef CD (instanceRef FF_17))
+              (portRef CD (instanceRef FF_16))
+              (portRef B0 (instanceRef bdcnt_bctr_cia))
+              (portRef A0 (instanceRef bdcnt_bctr_cia))
+              (portRef A1 (instanceRef bdcnt_bctr_7))
+              (portRef A1 (instanceRef e_cmp_0))
+              (portRef A0 (instanceRef e_cmp_1))
+              (portRef A1 (instanceRef e_cmp_1))
+              (portRef A0 (instanceRef e_cmp_2))
+              (portRef A1 (instanceRef e_cmp_2))
+              (portRef A0 (instanceRef e_cmp_3))
+              (portRef A1 (instanceRef e_cmp_3))
+              (portRef A0 (instanceRef e_cmp_4))
+              (portRef A1 (instanceRef e_cmp_4))
+              (portRef A0 (instanceRef e_cmp_5))
+              (portRef A1 (instanceRef e_cmp_5))
+              (portRef A0 (instanceRef e_cmp_6))
+              (portRef A1 (instanceRef e_cmp_6))
+              (portRef A0 (instanceRef e_cmp_7))
+              (portRef A1 (instanceRef e_cmp_7))
+              (portRef B1 (instanceRef e_cmp_7))
+              (portRef B1 (instanceRef a0))
+              (portRef B0 (instanceRef a0))
+              (portRef A1 (instanceRef a0))
+              (portRef A0 (instanceRef a0))
+              (portRef B1 (instanceRef g_cmp_7))
+              (portRef A1 (instanceRef g_cmp_7))
+              (portRef B1 (instanceRef a1))
+              (portRef B0 (instanceRef a1))
+              (portRef A1 (instanceRef a1))
+              (portRef A0 (instanceRef a1))
+              (portRef B0 (instanceRef w_ctr_cia))
+              (portRef A0 (instanceRef w_ctr_cia))
+              (portRef B1 (instanceRef w_ctr_0))
+              (portRef B0 (instanceRef w_ctr_0))
+              (portRef B1 (instanceRef w_ctr_1))
+              (portRef B0 (instanceRef w_ctr_1))
+              (portRef B1 (instanceRef w_ctr_2))
+              (portRef B0 (instanceRef w_ctr_2))
+              (portRef B1 (instanceRef w_ctr_3))
+              (portRef B0 (instanceRef w_ctr_3))
+              (portRef B1 (instanceRef w_ctr_4))
+              (portRef B0 (instanceRef w_ctr_4))
+              (portRef B1 (instanceRef w_ctr_5))
+              (portRef B0 (instanceRef w_ctr_5))
+              (portRef B1 (instanceRef w_ctr_6))
+              (portRef B0 (instanceRef w_ctr_6))
+              (portRef B1 (instanceRef w_ctr_7))
+              (portRef B0 (instanceRef w_ctr_7))
+              (portRef A1 (instanceRef w_ctr_7))
+              (portRef B0 (instanceRef r_ctr_cia))
+              (portRef A0 (instanceRef r_ctr_cia))
+              (portRef B1 (instanceRef r_ctr_0))
+              (portRef B0 (instanceRef r_ctr_0))
+              (portRef B1 (instanceRef r_ctr_1))
+              (portRef B0 (instanceRef r_ctr_1))
+              (portRef B1 (instanceRef r_ctr_2))
+              (portRef B0 (instanceRef r_ctr_2))
+              (portRef B1 (instanceRef r_ctr_3))
+              (portRef B0 (instanceRef r_ctr_3))
+              (portRef B1 (instanceRef r_ctr_4))
+              (portRef B0 (instanceRef r_ctr_4))
+              (portRef B1 (instanceRef r_ctr_5))
+              (portRef B0 (instanceRef r_ctr_5))
+              (portRef B1 (instanceRef r_ctr_6))
+              (portRef B0 (instanceRef r_ctr_6))
+              (portRef B1 (instanceRef r_ctr_7))
+              (portRef B0 (instanceRef r_ctr_7))
+              (portRef A1 (instanceRef r_ctr_7))
+              (portRef B1 (instanceRef wcnt_7))
+              (portRef B1 (instanceRef wcntd))
+              (portRef B0 (instanceRef wcntd))
+              (portRef A1 (instanceRef wcntd))
+              (portRef A0 (instanceRef wcntd))
+              (portRef B0 (instanceRef af_set_cmp_ci_a))
+              (portRef A0 (instanceRef af_set_cmp_ci_a))
+              (portRef B0 (instanceRef af_set_cmp_7))
+              (portRef B1 (instanceRef af_set_cmp_7))
+              (portRef A1 (instanceRef af_set_cmp_7))
+              (portRef B1 (instanceRef a2))
+              (portRef B0 (instanceRef a2))
+              (portRef A1 (instanceRef a2))
+              (portRef A0 (instanceRef a2))))
+          (net af_set_c
+            (joined
+              (portRef CIN (instanceRef a2))
+              (portRef COUT (instanceRef af_set_cmp_7))))
+          (net partial_full
+            (joined
+              (portRef AlmostFull)
+              (portRef Q (instanceRef FF_0))))
+          (net Full
+            (joined
+              (portRef Full)
+              (portRef Q (instanceRef FF_82))
+              (portRef A (instanceRef INV_5))
+              (portRef AD0 (instanceRef LUT4_0))))
+          (net Empty
+            (joined
+              (portRef Empty)
+              (portRef Q (instanceRef FF_83))
+              (portRef A (instanceRef INV_4))
+              (portRef AD0 (instanceRef LUT4_1))))
+          (net WCNT14
+            (joined
+              (portRef (member WCNT 0))
+              (portRef A0 (instanceRef g_cmp_7))
+              (portRef Q (instanceRef FF_84))
+              (portRef A0 (instanceRef bdcnt_bctr_7))
+              (portRef B0 (instanceRef e_cmp_7))))
+          (net WCNT13
+            (joined
+              (portRef (member WCNT 1))
+              (portRef A1 (instanceRef g_cmp_6))
+              (portRef Q (instanceRef FF_85))
+              (portRef A1 (instanceRef bdcnt_bctr_6))
+              (portRef B1 (instanceRef e_cmp_6))))
+          (net WCNT12
+            (joined
+              (portRef (member WCNT 2))
+              (portRef A0 (instanceRef g_cmp_6))
+              (portRef Q (instanceRef FF_86))
+              (portRef A0 (instanceRef bdcnt_bctr_6))
+              (portRef B0 (instanceRef e_cmp_6))))
+          (net WCNT11
+            (joined
+              (portRef (member WCNT 3))
+              (portRef A1 (instanceRef g_cmp_5))
+              (portRef Q (instanceRef FF_87))
+              (portRef A1 (instanceRef bdcnt_bctr_5))
+              (portRef B1 (instanceRef e_cmp_5))))
+          (net WCNT10
+            (joined
+              (portRef (member WCNT 4))
+              (portRef A0 (instanceRef g_cmp_5))
+              (portRef Q (instanceRef FF_88))
+              (portRef A0 (instanceRef bdcnt_bctr_5))
+              (portRef B0 (instanceRef e_cmp_5))))
+          (net WCNT9
+            (joined
+              (portRef (member WCNT 5))
+              (portRef A1 (instanceRef g_cmp_4))
+              (portRef Q (instanceRef FF_89))
+              (portRef A1 (instanceRef bdcnt_bctr_4))
+              (portRef B1 (instanceRef e_cmp_4))))
+          (net WCNT8
+            (joined
+              (portRef (member WCNT 6))
+              (portRef A0 (instanceRef g_cmp_4))
+              (portRef Q (instanceRef FF_90))
+              (portRef A0 (instanceRef bdcnt_bctr_4))
+              (portRef B0 (instanceRef e_cmp_4))))
+          (net WCNT7
+            (joined
+              (portRef (member WCNT 7))
+              (portRef A1 (instanceRef g_cmp_3))
+              (portRef Q (instanceRef FF_91))
+              (portRef A1 (instanceRef bdcnt_bctr_3))
+              (portRef B1 (instanceRef e_cmp_3))))
+          (net WCNT6
+            (joined
+              (portRef (member WCNT 8))
+              (portRef A0 (instanceRef g_cmp_3))
+              (portRef Q (instanceRef FF_92))
+              (portRef A0 (instanceRef bdcnt_bctr_3))
+              (portRef B0 (instanceRef e_cmp_3))))
+          (net WCNT5
+            (joined
+              (portRef (member WCNT 9))
+              (portRef A1 (instanceRef g_cmp_2))
+              (portRef Q (instanceRef FF_93))
+              (portRef A1 (instanceRef bdcnt_bctr_2))
+              (portRef B1 (instanceRef e_cmp_2))))
+          (net WCNT4
+            (joined
+              (portRef (member WCNT 10))
+              (portRef A0 (instanceRef g_cmp_2))
+              (portRef Q (instanceRef FF_94))
+              (portRef A0 (instanceRef bdcnt_bctr_2))
+              (portRef B0 (instanceRef e_cmp_2))))
+          (net WCNT3
+            (joined
+              (portRef (member WCNT 11))
+              (portRef A1 (instanceRef g_cmp_1))
+              (portRef Q (instanceRef FF_95))
+              (portRef A1 (instanceRef bdcnt_bctr_1))
+              (portRef B1 (instanceRef e_cmp_1))))
+          (net WCNT2
+            (joined
+              (portRef (member WCNT 12))
+              (portRef A0 (instanceRef g_cmp_1))
+              (portRef Q (instanceRef FF_96))
+              (portRef A0 (instanceRef bdcnt_bctr_1))
+              (portRef B0 (instanceRef e_cmp_1))))
+          (net WCNT1
+            (joined
+              (portRef (member WCNT 13))
+              (portRef A1 (instanceRef g_cmp_0))
+              (portRef Q (instanceRef FF_97))
+              (portRef A1 (instanceRef bdcnt_bctr_0))
+              (portRef B1 (instanceRef e_cmp_0))))
+          (net WCNT0
+            (joined
+              (portRef (member WCNT 14))
+              (portRef A0 (instanceRef g_cmp_0))
+              (portRef Q (instanceRef FF_98))
+              (portRef A0 (instanceRef bdcnt_bctr_0))
+              (portRef B0 (instanceRef e_cmp_0))))
+          (net dataout35
+            (joined
+              (portRef (member Q 0))
+              (portRef Z (instanceRef mux_0))))
+          (net dataout34
+            (joined
+              (portRef (member Q 1))
+              (portRef Z (instanceRef mux_1))))
+          (net dataout33
+            (joined
+              (portRef (member Q 2))
+              (portRef Z (instanceRef mux_2))))
+          (net dataout32
+            (joined
+              (portRef (member Q 3))
+              (portRef Z (instanceRef mux_3))))
+          (net dataout31
+            (joined
+              (portRef (member Q 4))
+              (portRef Z (instanceRef mux_4))))
+          (net dataout30
+            (joined
+              (portRef (member Q 5))
+              (portRef Z (instanceRef mux_5))))
+          (net dataout29
+            (joined
+              (portRef (member Q 6))
+              (portRef Z (instanceRef mux_6))))
+          (net dataout28
+            (joined
+              (portRef (member Q 7))
+              (portRef Z (instanceRef mux_7))))
+          (net dataout27
+            (joined
+              (portRef (member Q 8))
+              (portRef Z (instanceRef mux_8))))
+          (net dataout26
+            (joined
+              (portRef (member Q 9))
+              (portRef Z (instanceRef mux_9))))
+          (net dataout25
+            (joined
+              (portRef (member Q 10))
+              (portRef Z (instanceRef mux_10))))
+          (net dataout24
+            (joined
+              (portRef (member Q 11))
+              (portRef Z (instanceRef mux_11))))
+          (net dataout23
+            (joined
+              (portRef (member Q 12))
+              (portRef Z (instanceRef mux_12))))
+          (net dataout22
+            (joined
+              (portRef (member Q 13))
+              (portRef Z (instanceRef mux_13))))
+          (net dataout21
+            (joined
+              (portRef (member Q 14))
+              (portRef Z (instanceRef mux_14))))
+          (net dataout20
+            (joined
+              (portRef (member Q 15))
+              (portRef Z (instanceRef mux_15))))
+          (net dataout19
+            (joined
+              (portRef (member Q 16))
+              (portRef Z (instanceRef mux_16))))
+          (net dataout18
+            (joined
+              (portRef (member Q 17))
+              (portRef Z (instanceRef mux_17))))
+          (net dataout17
+            (joined
+              (portRef (member Q 18))
+              (portRef Z (instanceRef mux_18))))
+          (net dataout16
+            (joined
+              (portRef (member Q 19))
+              (portRef Z (instanceRef mux_19))))
+          (net dataout15
+            (joined
+              (portRef (member Q 20))
+              (portRef Z (instanceRef mux_20))))
+          (net dataout14
+            (joined
+              (portRef (member Q 21))
+              (portRef Z (instanceRef mux_21))))
+          (net dataout13
+            (joined
+              (portRef (member Q 22))
+              (portRef Z (instanceRef mux_22))))
+          (net dataout12
+            (joined
+              (portRef (member Q 23))
+              (portRef Z (instanceRef mux_23))))
+          (net dataout11
+            (joined
+              (portRef (member Q 24))
+              (portRef Z (instanceRef mux_24))))
+          (net dataout10
+            (joined
+              (portRef (member Q 25))
+              (portRef Z (instanceRef mux_25))))
+          (net dataout9
+            (joined
+              (portRef (member Q 26))
+              (portRef Z (instanceRef mux_26))))
+          (net dataout8
+            (joined
+              (portRef (member Q 27))
+              (portRef Z (instanceRef mux_27))))
+          (net dataout7
+            (joined
+              (portRef (member Q 28))
+              (portRef Z (instanceRef mux_28))))
+          (net dataout6
+            (joined
+              (portRef (member Q 29))
+              (portRef Z (instanceRef mux_29))))
+          (net dataout5
+            (joined
+              (portRef (member Q 30))
+              (portRef Z (instanceRef mux_30))))
+          (net dataout4
+            (joined
+              (portRef (member Q 31))
+              (portRef Z (instanceRef mux_31))))
+          (net dataout3
+            (joined
+              (portRef (member Q 32))
+              (portRef Z (instanceRef mux_32))))
+          (net dataout2
+            (joined
+              (portRef (member Q 33))
+              (portRef Z (instanceRef mux_33))))
+          (net dataout1
+            (joined
+              (portRef (member Q 34))
+              (portRef Z (instanceRef mux_34))))
+          (net dataout0
+            (joined
+              (portRef (member Q 35))
+              (portRef Z (instanceRef mux_35))))
+          (net AmFullThresh13
+            (joined
+              (portRef (member AmFullThresh 0))
+              (portRef B1 (instanceRef af_set_cmp_6))))
+          (net AmFullThresh12
+            (joined
+              (portRef (member AmFullThresh 1))
+              (portRef B0 (instanceRef af_set_cmp_6))))
+          (net AmFullThresh11
+            (joined
+              (portRef (member AmFullThresh 2))
+              (portRef B1 (instanceRef af_set_cmp_5))))
+          (net AmFullThresh10
+            (joined
+              (portRef (member AmFullThresh 3))
+              (portRef B0 (instanceRef af_set_cmp_5))))
+          (net AmFullThresh9
+            (joined
+              (portRef (member AmFullThresh 4))
+              (portRef B1 (instanceRef af_set_cmp_4))))
+          (net AmFullThresh8
+            (joined
+              (portRef (member AmFullThresh 5))
+              (portRef B0 (instanceRef af_set_cmp_4))))
+          (net AmFullThresh7
+            (joined
+              (portRef (member AmFullThresh 6))
+              (portRef B1 (instanceRef af_set_cmp_3))))
+          (net AmFullThresh6
+            (joined
+              (portRef (member AmFullThresh 7))
+              (portRef B0 (instanceRef af_set_cmp_3))))
+          (net AmFullThresh5
+            (joined
+              (portRef (member AmFullThresh 8))
+              (portRef B1 (instanceRef af_set_cmp_2))))
+          (net AmFullThresh4
+            (joined
+              (portRef (member AmFullThresh 9))
+              (portRef B0 (instanceRef af_set_cmp_2))))
+          (net AmFullThresh3
+            (joined
+              (portRef (member AmFullThresh 10))
+              (portRef B1 (instanceRef af_set_cmp_1))))
+          (net AmFullThresh2
+            (joined
+              (portRef (member AmFullThresh 11))
+              (portRef B0 (instanceRef af_set_cmp_1))))
+          (net AmFullThresh1
+            (joined
+              (portRef (member AmFullThresh 12))
+              (portRef B1 (instanceRef af_set_cmp_0))))
+          (net AmFullThresh0
+            (joined
+              (portRef (member AmFullThresh 13))
+              (portRef B0 (instanceRef af_set_cmp_0))))
+          (net reset
+            (joined
+              (portRef Reset)
+              (portRef RSTB (instanceRef pdp_ram_0_0_31))
+              (portRef RSTA (instanceRef pdp_ram_0_0_31))
+              (portRef RSTB (instanceRef pdp_ram_0_1_30))
+              (portRef RSTA (instanceRef pdp_ram_0_1_30))
+              (portRef RSTB (instanceRef pdp_ram_0_2_29))
+              (portRef RSTA (instanceRef pdp_ram_0_2_29))
+              (portRef RSTB (instanceRef pdp_ram_0_3_28))
+              (portRef RSTA (instanceRef pdp_ram_0_3_28))
+              (portRef RSTB (instanceRef pdp_ram_1_0_27))
+              (portRef RSTA (instanceRef pdp_ram_1_0_27))
+              (portRef RSTB (instanceRef pdp_ram_1_1_26))
+              (portRef RSTA (instanceRef pdp_ram_1_1_26))
+              (portRef RSTB (instanceRef pdp_ram_1_2_25))
+              (portRef RSTA (instanceRef pdp_ram_1_2_25))
+              (portRef RSTB (instanceRef pdp_ram_1_3_24))
+              (portRef RSTA (instanceRef pdp_ram_1_3_24))
+              (portRef RSTB (instanceRef pdp_ram_2_0_23))
+              (portRef RSTA (instanceRef pdp_ram_2_0_23))
+              (portRef RSTB (instanceRef pdp_ram_2_1_22))
+              (portRef RSTA (instanceRef pdp_ram_2_1_22))
+              (portRef RSTB (instanceRef pdp_ram_2_2_21))
+              (portRef RSTA (instanceRef pdp_ram_2_2_21))
+              (portRef RSTB (instanceRef pdp_ram_2_3_20))
+              (portRef RSTA (instanceRef pdp_ram_2_3_20))
+              (portRef RSTB (instanceRef pdp_ram_3_0_19))
+              (portRef RSTA (instanceRef pdp_ram_3_0_19))
+              (portRef RSTB (instanceRef pdp_ram_3_1_18))
+              (portRef RSTA (instanceRef pdp_ram_3_1_18))
+              (portRef RSTB (instanceRef pdp_ram_3_2_17))
+              (portRef RSTA (instanceRef pdp_ram_3_2_17))
+              (portRef RSTB (instanceRef pdp_ram_3_3_16))
+              (portRef RSTA (instanceRef pdp_ram_3_3_16))
+              (portRef RSTB (instanceRef pdp_ram_4_0_15))
+              (portRef RSTA (instanceRef pdp_ram_4_0_15))
+              (portRef RSTB (instanceRef pdp_ram_4_1_14))
+              (portRef RSTA (instanceRef pdp_ram_4_1_14))
+              (portRef RSTB (instanceRef pdp_ram_4_2_13))
+              (portRef RSTA (instanceRef pdp_ram_4_2_13))
+              (portRef RSTB (instanceRef pdp_ram_4_3_12))
+              (portRef RSTA (instanceRef pdp_ram_4_3_12))
+              (portRef RSTB (instanceRef pdp_ram_5_0_11))
+              (portRef RSTA (instanceRef pdp_ram_5_0_11))
+              (portRef RSTB (instanceRef pdp_ram_5_1_10))
+              (portRef RSTA (instanceRef pdp_ram_5_1_10))
+              (portRef RSTB (instanceRef pdp_ram_5_2_9))
+              (portRef RSTA (instanceRef pdp_ram_5_2_9))
+              (portRef RSTB (instanceRef pdp_ram_5_3_8))
+              (portRef RSTA (instanceRef pdp_ram_5_3_8))
+              (portRef RSTB (instanceRef pdp_ram_6_0_7))
+              (portRef RSTA (instanceRef pdp_ram_6_0_7))
+              (portRef RSTB (instanceRef pdp_ram_6_1_6))
+              (portRef RSTA (instanceRef pdp_ram_6_1_6))
+              (portRef RSTB (instanceRef pdp_ram_6_2_5))
+              (portRef RSTA (instanceRef pdp_ram_6_2_5))
+              (portRef RSTB (instanceRef pdp_ram_6_3_4))
+              (portRef RSTA (instanceRef pdp_ram_6_3_4))
+              (portRef RSTB (instanceRef pdp_ram_7_0_3))
+              (portRef RSTA (instanceRef pdp_ram_7_0_3))
+              (portRef RSTB (instanceRef pdp_ram_7_1_2))
+              (portRef RSTA (instanceRef pdp_ram_7_1_2))
+              (portRef RSTB (instanceRef pdp_ram_7_2_1))
+              (portRef RSTA (instanceRef pdp_ram_7_2_1))
+              (portRef RSTB (instanceRef pdp_ram_7_3_0))
+              (portRef RSTA (instanceRef pdp_ram_7_3_0))
+              (portRef CD (instanceRef FF_98))
+              (portRef CD (instanceRef FF_97))
+              (portRef CD (instanceRef FF_96))
+              (portRef CD (instanceRef FF_95))
+              (portRef CD (instanceRef FF_94))
+              (portRef CD (instanceRef FF_93))
+              (portRef CD (instanceRef FF_92))
+              (portRef CD (instanceRef FF_91))
+              (portRef CD (instanceRef FF_90))
+              (portRef CD (instanceRef FF_89))
+              (portRef CD (instanceRef FF_88))
+              (portRef CD (instanceRef FF_87))
+              (portRef CD (instanceRef FF_86))
+              (portRef CD (instanceRef FF_85))
+              (portRef CD (instanceRef FF_84))
+              (portRef PD (instanceRef FF_83))
+              (portRef CD (instanceRef FF_82))
+              (portRef PD (instanceRef FF_81))
+              (portRef CD (instanceRef FF_80))
+              (portRef CD (instanceRef FF_79))
+              (portRef CD (instanceRef FF_78))
+              (portRef CD (instanceRef FF_77))
+              (portRef CD (instanceRef FF_76))
+              (portRef CD (instanceRef FF_75))
+              (portRef CD (instanceRef FF_74))
+              (portRef CD (instanceRef FF_73))
+              (portRef CD (instanceRef FF_72))
+              (portRef CD (instanceRef FF_71))
+              (portRef CD (instanceRef FF_70))
+              (portRef CD (instanceRef FF_69))
+              (portRef CD (instanceRef FF_68))
+              (portRef CD (instanceRef FF_67))
+              (portRef PD (instanceRef FF_66))
+              (portRef CD (instanceRef FF_65))
+              (portRef CD (instanceRef FF_64))
+              (portRef CD (instanceRef FF_63))
+              (portRef CD (instanceRef FF_62))
+              (portRef CD (instanceRef FF_61))
+              (portRef CD (instanceRef FF_60))
+              (portRef CD (instanceRef FF_59))
+              (portRef CD (instanceRef FF_58))
+              (portRef CD (instanceRef FF_57))
+              (portRef CD (instanceRef FF_56))
+              (portRef CD (instanceRef FF_55))
+              (portRef CD (instanceRef FF_54))
+              (portRef CD (instanceRef FF_53))
+              (portRef CD (instanceRef FF_52))
+              (portRef CD (instanceRef FF_51))
+              (portRef CD (instanceRef FF_50))
+              (portRef CD (instanceRef FF_49))
+              (portRef CD (instanceRef FF_48))
+              (portRef CD (instanceRef FF_47))
+              (portRef CD (instanceRef FF_46))
+              (portRef CD (instanceRef FF_45))
+              (portRef CD (instanceRef FF_44))
+              (portRef CD (instanceRef FF_43))
+              (portRef CD (instanceRef FF_42))
+              (portRef CD (instanceRef FF_41))
+              (portRef CD (instanceRef FF_40))
+              (portRef CD (instanceRef FF_39))
+              (portRef CD (instanceRef FF_38))
+              (portRef CD (instanceRef FF_37))
+              (portRef CD (instanceRef FF_36))
+              (portRef CD (instanceRef FF_35))
+              (portRef CD (instanceRef FF_34))
+              (portRef CD (instanceRef FF_33))
+              (portRef CD (instanceRef FF_32))
+              (portRef CD (instanceRef FF_31))
+              (portRef CD (instanceRef FF_30))
+              (portRef CD (instanceRef FF_29))
+              (portRef CD (instanceRef FF_28))
+              (portRef CD (instanceRef FF_27))
+              (portRef CD (instanceRef FF_26))
+              (portRef CD (instanceRef FF_25))
+              (portRef CD (instanceRef FF_24))
+              (portRef CD (instanceRef FF_23))
+              (portRef CD (instanceRef FF_22))
+              (portRef CD (instanceRef FF_15))
+              (portRef CD (instanceRef FF_14))
+              (portRef CD (instanceRef FF_13))
+              (portRef CD (instanceRef FF_12))
+              (portRef CD (instanceRef FF_11))
+              (portRef CD (instanceRef FF_10))
+              (portRef CD (instanceRef FF_9))
+              (portRef CD (instanceRef FF_8))
+              (portRef CD (instanceRef FF_7))
+              (portRef CD (instanceRef FF_6))
+              (portRef CD (instanceRef FF_5))
+              (portRef CD (instanceRef FF_4))
+              (portRef CD (instanceRef FF_3))
+              (portRef CD (instanceRef FF_2))
+              (portRef CD (instanceRef FF_1))
+              (portRef CD (instanceRef FF_0))))
+          (net rden
+            (joined
+              (portRef RdEn)
+              (portRef A (instanceRef AND2_t4))))
+          (net wren
+            (joined
+              (portRef WrEn)
+              (portRef A (instanceRef AND2_t5))))
+          (net clk
+            (joined
+              (portRef Clock)
+              (portRef CLKB (instanceRef pdp_ram_0_0_31))
+              (portRef CLKA (instanceRef pdp_ram_0_0_31))
+              (portRef CLKB (instanceRef pdp_ram_0_1_30))
+              (portRef CLKA (instanceRef pdp_ram_0_1_30))
+              (portRef CLKB (instanceRef pdp_ram_0_2_29))
+              (portRef CLKA (instanceRef pdp_ram_0_2_29))
+              (portRef CLKB (instanceRef pdp_ram_0_3_28))
+              (portRef CLKA (instanceRef pdp_ram_0_3_28))
+              (portRef CLKB (instanceRef pdp_ram_1_0_27))
+              (portRef CLKA (instanceRef pdp_ram_1_0_27))
+              (portRef CLKB (instanceRef pdp_ram_1_1_26))
+              (portRef CLKA (instanceRef pdp_ram_1_1_26))
+              (portRef CLKB (instanceRef pdp_ram_1_2_25))
+              (portRef CLKA (instanceRef pdp_ram_1_2_25))
+              (portRef CLKB (instanceRef pdp_ram_1_3_24))
+              (portRef CLKA (instanceRef pdp_ram_1_3_24))
+              (portRef CLKB (instanceRef pdp_ram_2_0_23))
+              (portRef CLKA (instanceRef pdp_ram_2_0_23))
+              (portRef CLKB (instanceRef pdp_ram_2_1_22))
+              (portRef CLKA (instanceRef pdp_ram_2_1_22))
+              (portRef CLKB (instanceRef pdp_ram_2_2_21))
+              (portRef CLKA (instanceRef pdp_ram_2_2_21))
+              (portRef CLKB (instanceRef pdp_ram_2_3_20))
+              (portRef CLKA (instanceRef pdp_ram_2_3_20))
+              (portRef CLKB (instanceRef pdp_ram_3_0_19))
+              (portRef CLKA (instanceRef pdp_ram_3_0_19))
+              (portRef CLKB (instanceRef pdp_ram_3_1_18))
+              (portRef CLKA (instanceRef pdp_ram_3_1_18))
+              (portRef CLKB (instanceRef pdp_ram_3_2_17))
+              (portRef CLKA (instanceRef pdp_ram_3_2_17))
+              (portRef CLKB (instanceRef pdp_ram_3_3_16))
+              (portRef CLKA (instanceRef pdp_ram_3_3_16))
+              (portRef CLKB (instanceRef pdp_ram_4_0_15))
+              (portRef CLKA (instanceRef pdp_ram_4_0_15))
+              (portRef CLKB (instanceRef pdp_ram_4_1_14))
+              (portRef CLKA (instanceRef pdp_ram_4_1_14))
+              (portRef CLKB (instanceRef pdp_ram_4_2_13))
+              (portRef CLKA (instanceRef pdp_ram_4_2_13))
+              (portRef CLKB (instanceRef pdp_ram_4_3_12))
+              (portRef CLKA (instanceRef pdp_ram_4_3_12))
+              (portRef CLKB (instanceRef pdp_ram_5_0_11))
+              (portRef CLKA (instanceRef pdp_ram_5_0_11))
+              (portRef CLKB (instanceRef pdp_ram_5_1_10))
+              (portRef CLKA (instanceRef pdp_ram_5_1_10))
+              (portRef CLKB (instanceRef pdp_ram_5_2_9))
+              (portRef CLKA (instanceRef pdp_ram_5_2_9))
+              (portRef CLKB (instanceRef pdp_ram_5_3_8))
+              (portRef CLKA (instanceRef pdp_ram_5_3_8))
+              (portRef CLKB (instanceRef pdp_ram_6_0_7))
+              (portRef CLKA (instanceRef pdp_ram_6_0_7))
+              (portRef CLKB (instanceRef pdp_ram_6_1_6))
+              (portRef CLKA (instanceRef pdp_ram_6_1_6))
+              (portRef CLKB (instanceRef pdp_ram_6_2_5))
+              (portRef CLKA (instanceRef pdp_ram_6_2_5))
+              (portRef CLKB (instanceRef pdp_ram_6_3_4))
+              (portRef CLKA (instanceRef pdp_ram_6_3_4))
+              (portRef CLKB (instanceRef pdp_ram_7_0_3))
+              (portRef CLKA (instanceRef pdp_ram_7_0_3))
+              (portRef CLKB (instanceRef pdp_ram_7_1_2))
+              (portRef CLKA (instanceRef pdp_ram_7_1_2))
+              (portRef CLKB (instanceRef pdp_ram_7_2_1))
+              (portRef CLKA (instanceRef pdp_ram_7_2_1))
+              (portRef CLKB (instanceRef pdp_ram_7_3_0))
+              (portRef CLKA (instanceRef pdp_ram_7_3_0))
+              (portRef CK (instanceRef FF_98))
+              (portRef CK (instanceRef FF_97))
+              (portRef CK (instanceRef FF_96))
+              (portRef CK (instanceRef FF_95))
+              (portRef CK (instanceRef FF_94))
+              (portRef CK (instanceRef FF_93))
+              (portRef CK (instanceRef FF_92))
+              (portRef CK (instanceRef FF_91))
+              (portRef CK (instanceRef FF_90))
+              (portRef CK (instanceRef FF_89))
+              (portRef CK (instanceRef FF_88))
+              (portRef CK (instanceRef FF_87))
+              (portRef CK (instanceRef FF_86))
+              (portRef CK (instanceRef FF_85))
+              (portRef CK (instanceRef FF_84))
+              (portRef CK (instanceRef FF_83))
+              (portRef CK (instanceRef FF_82))
+              (portRef CK (instanceRef FF_81))
+              (portRef CK (instanceRef FF_80))
+              (portRef CK (instanceRef FF_79))
+              (portRef CK (instanceRef FF_78))
+              (portRef CK (instanceRef FF_77))
+              (portRef CK (instanceRef FF_76))
+              (portRef CK (instanceRef FF_75))
+              (portRef CK (instanceRef FF_74))
+              (portRef CK (instanceRef FF_73))
+              (portRef CK (instanceRef FF_72))
+              (portRef CK (instanceRef FF_71))
+              (portRef CK (instanceRef FF_70))
+              (portRef CK (instanceRef FF_69))
+              (portRef CK (instanceRef FF_68))
+              (portRef CK (instanceRef FF_67))
+              (portRef CK (instanceRef FF_66))
+              (portRef CK (instanceRef FF_65))
+              (portRef CK (instanceRef FF_64))
+              (portRef CK (instanceRef FF_63))
+              (portRef CK (instanceRef FF_62))
+              (portRef CK (instanceRef FF_61))
+              (portRef CK (instanceRef FF_60))
+              (portRef CK (instanceRef FF_59))
+              (portRef CK (instanceRef FF_58))
+              (portRef CK (instanceRef FF_57))
+              (portRef CK (instanceRef FF_56))
+              (portRef CK (instanceRef FF_55))
+              (portRef CK (instanceRef FF_54))
+              (portRef CK (instanceRef FF_53))
+              (portRef CK (instanceRef FF_52))
+              (portRef CK (instanceRef FF_51))
+              (portRef CK (instanceRef FF_50))
+              (portRef CK (instanceRef FF_49))
+              (portRef CK (instanceRef FF_48))
+              (portRef CK (instanceRef FF_47))
+              (portRef CK (instanceRef FF_46))
+              (portRef CK (instanceRef FF_45))
+              (portRef CK (instanceRef FF_44))
+              (portRef CK (instanceRef FF_43))
+              (portRef CK (instanceRef FF_42))
+              (portRef CK (instanceRef FF_41))
+              (portRef CK (instanceRef FF_40))
+              (portRef CK (instanceRef FF_39))
+              (portRef CK (instanceRef FF_38))
+              (portRef CK (instanceRef FF_37))
+              (portRef CK (instanceRef FF_36))
+              (portRef CK (instanceRef FF_35))
+              (portRef CK (instanceRef FF_34))
+              (portRef CK (instanceRef FF_33))
+              (portRef CK (instanceRef FF_32))
+              (portRef CK (instanceRef FF_31))
+              (portRef CK (instanceRef FF_30))
+              (portRef CK (instanceRef FF_29))
+              (portRef CK (instanceRef FF_28))
+              (portRef CK (instanceRef FF_27))
+              (portRef CK (instanceRef FF_26))
+              (portRef CK (instanceRef FF_25))
+              (portRef CK (instanceRef FF_24))
+              (portRef CK (instanceRef FF_23))
+              (portRef CK (instanceRef FF_22))
+              (portRef CK (instanceRef FF_21))
+              (portRef CK (instanceRef FF_20))
+              (portRef CK (instanceRef FF_19))
+              (portRef CK (instanceRef FF_18))
+              (portRef CK (instanceRef FF_17))
+              (portRef CK (instanceRef FF_16))
+              (portRef CK (instanceRef FF_15))
+              (portRef CK (instanceRef FF_14))
+              (portRef CK (instanceRef FF_13))
+              (portRef CK (instanceRef FF_12))
+              (portRef CK (instanceRef FF_11))
+              (portRef CK (instanceRef FF_10))
+              (portRef CK (instanceRef FF_9))
+              (portRef CK (instanceRef FF_8))
+              (portRef CK (instanceRef FF_7))
+              (portRef CK (instanceRef FF_6))
+              (portRef CK (instanceRef FF_5))
+              (portRef CK (instanceRef FF_4))
+              (portRef CK (instanceRef FF_3))
+              (portRef CK (instanceRef FF_2))
+              (portRef CK (instanceRef FF_1))
+              (portRef CK (instanceRef FF_0))))
+          (net datain35
+            (joined
+              (portRef (member Data 0))
+              (portRef DIA8 (instanceRef pdp_ram_0_3_28))
+              (portRef DIA8 (instanceRef pdp_ram_1_3_24))
+              (portRef DIA8 (instanceRef pdp_ram_2_3_20))
+              (portRef DIA8 (instanceRef pdp_ram_3_3_16))
+              (portRef DIA8 (instanceRef pdp_ram_4_3_12))
+              (portRef DIA8 (instanceRef pdp_ram_5_3_8))
+              (portRef DIA8 (instanceRef pdp_ram_6_3_4))
+              (portRef DIA8 (instanceRef pdp_ram_7_3_0))))
+          (net datain34
+            (joined
+              (portRef (member Data 1))
+              (portRef DIA7 (instanceRef pdp_ram_0_3_28))
+              (portRef DIA7 (instanceRef pdp_ram_1_3_24))
+              (portRef DIA7 (instanceRef pdp_ram_2_3_20))
+              (portRef DIA7 (instanceRef pdp_ram_3_3_16))
+              (portRef DIA7 (instanceRef pdp_ram_4_3_12))
+              (portRef DIA7 (instanceRef pdp_ram_5_3_8))
+              (portRef DIA7 (instanceRef pdp_ram_6_3_4))
+              (portRef DIA7 (instanceRef pdp_ram_7_3_0))))
+          (net datain33
+            (joined
+              (portRef (member Data 2))
+              (portRef DIA6 (instanceRef pdp_ram_0_3_28))
+              (portRef DIA6 (instanceRef pdp_ram_1_3_24))
+              (portRef DIA6 (instanceRef pdp_ram_2_3_20))
+              (portRef DIA6 (instanceRef pdp_ram_3_3_16))
+              (portRef DIA6 (instanceRef pdp_ram_4_3_12))
+              (portRef DIA6 (instanceRef pdp_ram_5_3_8))
+              (portRef DIA6 (instanceRef pdp_ram_6_3_4))
+              (portRef DIA6 (instanceRef pdp_ram_7_3_0))))
+          (net datain32
+            (joined
+              (portRef (member Data 3))
+              (portRef DIA5 (instanceRef pdp_ram_0_3_28))
+              (portRef DIA5 (instanceRef pdp_ram_1_3_24))
+              (portRef DIA5 (instanceRef pdp_ram_2_3_20))
+              (portRef DIA5 (instanceRef pdp_ram_3_3_16))
+              (portRef DIA5 (instanceRef pdp_ram_4_3_12))
+              (portRef DIA5 (instanceRef pdp_ram_5_3_8))
+              (portRef DIA5 (instanceRef pdp_ram_6_3_4))
+              (portRef DIA5 (instanceRef pdp_ram_7_3_0))))
+          (net datain31
+            (joined
+              (portRef (member Data 4))
+              (portRef DIA4 (instanceRef pdp_ram_0_3_28))
+              (portRef DIA4 (instanceRef pdp_ram_1_3_24))
+              (portRef DIA4 (instanceRef pdp_ram_2_3_20))
+              (portRef DIA4 (instanceRef pdp_ram_3_3_16))
+              (portRef DIA4 (instanceRef pdp_ram_4_3_12))
+              (portRef DIA4 (instanceRef pdp_ram_5_3_8))
+              (portRef DIA4 (instanceRef pdp_ram_6_3_4))
+              (portRef DIA4 (instanceRef pdp_ram_7_3_0))))
+          (net datain30
+            (joined
+              (portRef (member Data 5))
+              (portRef DIA3 (instanceRef pdp_ram_0_3_28))
+              (portRef DIA3 (instanceRef pdp_ram_1_3_24))
+              (portRef DIA3 (instanceRef pdp_ram_2_3_20))
+              (portRef DIA3 (instanceRef pdp_ram_3_3_16))
+              (portRef DIA3 (instanceRef pdp_ram_4_3_12))
+              (portRef DIA3 (instanceRef pdp_ram_5_3_8))
+              (portRef DIA3 (instanceRef pdp_ram_6_3_4))
+              (portRef DIA3 (instanceRef pdp_ram_7_3_0))))
+          (net datain29
+            (joined
+              (portRef (member Data 6))
+              (portRef DIA2 (instanceRef pdp_ram_0_3_28))
+              (portRef DIA2 (instanceRef pdp_ram_1_3_24))
+              (portRef DIA2 (instanceRef pdp_ram_2_3_20))
+              (portRef DIA2 (instanceRef pdp_ram_3_3_16))
+              (portRef DIA2 (instanceRef pdp_ram_4_3_12))
+              (portRef DIA2 (instanceRef pdp_ram_5_3_8))
+              (portRef DIA2 (instanceRef pdp_ram_6_3_4))
+              (portRef DIA2 (instanceRef pdp_ram_7_3_0))))
+          (net datain28
+            (joined
+              (portRef (member Data 7))
+              (portRef DIA1 (instanceRef pdp_ram_0_3_28))
+              (portRef DIA1 (instanceRef pdp_ram_1_3_24))
+              (portRef DIA1 (instanceRef pdp_ram_2_3_20))
+              (portRef DIA1 (instanceRef pdp_ram_3_3_16))
+              (portRef DIA1 (instanceRef pdp_ram_4_3_12))
+              (portRef DIA1 (instanceRef pdp_ram_5_3_8))
+              (portRef DIA1 (instanceRef pdp_ram_6_3_4))
+              (portRef DIA1 (instanceRef pdp_ram_7_3_0))))
+          (net datain27
+            (joined
+              (portRef (member Data 8))
+              (portRef DIA0 (instanceRef pdp_ram_0_3_28))
+              (portRef DIA0 (instanceRef pdp_ram_1_3_24))
+              (portRef DIA0 (instanceRef pdp_ram_2_3_20))
+              (portRef DIA0 (instanceRef pdp_ram_3_3_16))
+              (portRef DIA0 (instanceRef pdp_ram_4_3_12))
+              (portRef DIA0 (instanceRef pdp_ram_5_3_8))
+              (portRef DIA0 (instanceRef pdp_ram_6_3_4))
+              (portRef DIA0 (instanceRef pdp_ram_7_3_0))))
+          (net datain26
+            (joined
+              (portRef (member Data 9))
+              (portRef DIA8 (instanceRef pdp_ram_0_2_29))
+              (portRef DIA8 (instanceRef pdp_ram_1_2_25))
+              (portRef DIA8 (instanceRef pdp_ram_2_2_21))
+              (portRef DIA8 (instanceRef pdp_ram_3_2_17))
+              (portRef DIA8 (instanceRef pdp_ram_4_2_13))
+              (portRef DIA8 (instanceRef pdp_ram_5_2_9))
+              (portRef DIA8 (instanceRef pdp_ram_6_2_5))
+              (portRef DIA8 (instanceRef pdp_ram_7_2_1))))
+          (net datain25
+            (joined
+              (portRef (member Data 10))
+              (portRef DIA7 (instanceRef pdp_ram_0_2_29))
+              (portRef DIA7 (instanceRef pdp_ram_1_2_25))
+              (portRef DIA7 (instanceRef pdp_ram_2_2_21))
+              (portRef DIA7 (instanceRef pdp_ram_3_2_17))
+              (portRef DIA7 (instanceRef pdp_ram_4_2_13))
+              (portRef DIA7 (instanceRef pdp_ram_5_2_9))
+              (portRef DIA7 (instanceRef pdp_ram_6_2_5))
+              (portRef DIA7 (instanceRef pdp_ram_7_2_1))))
+          (net datain24
+            (joined
+              (portRef (member Data 11))
+              (portRef DIA6 (instanceRef pdp_ram_0_2_29))
+              (portRef DIA6 (instanceRef pdp_ram_1_2_25))
+              (portRef DIA6 (instanceRef pdp_ram_2_2_21))
+              (portRef DIA6 (instanceRef pdp_ram_3_2_17))
+              (portRef DIA6 (instanceRef pdp_ram_4_2_13))
+              (portRef DIA6 (instanceRef pdp_ram_5_2_9))
+              (portRef DIA6 (instanceRef pdp_ram_6_2_5))
+              (portRef DIA6 (instanceRef pdp_ram_7_2_1))))
+          (net datain23
+            (joined
+              (portRef (member Data 12))
+              (portRef DIA5 (instanceRef pdp_ram_0_2_29))
+              (portRef DIA5 (instanceRef pdp_ram_1_2_25))
+              (portRef DIA5 (instanceRef pdp_ram_2_2_21))
+              (portRef DIA5 (instanceRef pdp_ram_3_2_17))
+              (portRef DIA5 (instanceRef pdp_ram_4_2_13))
+              (portRef DIA5 (instanceRef pdp_ram_5_2_9))
+              (portRef DIA5 (instanceRef pdp_ram_6_2_5))
+              (portRef DIA5 (instanceRef pdp_ram_7_2_1))))
+          (net datain22
+            (joined
+              (portRef (member Data 13))
+              (portRef DIA4 (instanceRef pdp_ram_0_2_29))
+              (portRef DIA4 (instanceRef pdp_ram_1_2_25))
+              (portRef DIA4 (instanceRef pdp_ram_2_2_21))
+              (portRef DIA4 (instanceRef pdp_ram_3_2_17))
+              (portRef DIA4 (instanceRef pdp_ram_4_2_13))
+              (portRef DIA4 (instanceRef pdp_ram_5_2_9))
+              (portRef DIA4 (instanceRef pdp_ram_6_2_5))
+              (portRef DIA4 (instanceRef pdp_ram_7_2_1))))
+          (net datain21
+            (joined
+              (portRef (member Data 14))
+              (portRef DIA3 (instanceRef pdp_ram_0_2_29))
+              (portRef DIA3 (instanceRef pdp_ram_1_2_25))
+              (portRef DIA3 (instanceRef pdp_ram_2_2_21))
+              (portRef DIA3 (instanceRef pdp_ram_3_2_17))
+              (portRef DIA3 (instanceRef pdp_ram_4_2_13))
+              (portRef DIA3 (instanceRef pdp_ram_5_2_9))
+              (portRef DIA3 (instanceRef pdp_ram_6_2_5))
+              (portRef DIA3 (instanceRef pdp_ram_7_2_1))))
+          (net datain20
+            (joined
+              (portRef (member Data 15))
+              (portRef DIA2 (instanceRef pdp_ram_0_2_29))
+              (portRef DIA2 (instanceRef pdp_ram_1_2_25))
+              (portRef DIA2 (instanceRef pdp_ram_2_2_21))
+              (portRef DIA2 (instanceRef pdp_ram_3_2_17))
+              (portRef DIA2 (instanceRef pdp_ram_4_2_13))
+              (portRef DIA2 (instanceRef pdp_ram_5_2_9))
+              (portRef DIA2 (instanceRef pdp_ram_6_2_5))
+              (portRef DIA2 (instanceRef pdp_ram_7_2_1))))
+          (net datain19
+            (joined
+              (portRef (member Data 16))
+              (portRef DIA1 (instanceRef pdp_ram_0_2_29))
+              (portRef DIA1 (instanceRef pdp_ram_1_2_25))
+              (portRef DIA1 (instanceRef pdp_ram_2_2_21))
+              (portRef DIA1 (instanceRef pdp_ram_3_2_17))
+              (portRef DIA1 (instanceRef pdp_ram_4_2_13))
+              (portRef DIA1 (instanceRef pdp_ram_5_2_9))
+              (portRef DIA1 (instanceRef pdp_ram_6_2_5))
+              (portRef DIA1 (instanceRef pdp_ram_7_2_1))))
+          (net datain18
+            (joined
+              (portRef (member Data 17))
+              (portRef DIA0 (instanceRef pdp_ram_0_2_29))
+              (portRef DIA0 (instanceRef pdp_ram_1_2_25))
+              (portRef DIA0 (instanceRef pdp_ram_2_2_21))
+              (portRef DIA0 (instanceRef pdp_ram_3_2_17))
+              (portRef DIA0 (instanceRef pdp_ram_4_2_13))
+              (portRef DIA0 (instanceRef pdp_ram_5_2_9))
+              (portRef DIA0 (instanceRef pdp_ram_6_2_5))
+              (portRef DIA0 (instanceRef pdp_ram_7_2_1))))
+          (net datain17
+            (joined
+              (portRef (member Data 18))
+              (portRef DIA8 (instanceRef pdp_ram_0_1_30))
+              (portRef DIA8 (instanceRef pdp_ram_1_1_26))
+              (portRef DIA8 (instanceRef pdp_ram_2_1_22))
+              (portRef DIA8 (instanceRef pdp_ram_3_1_18))
+              (portRef DIA8 (instanceRef pdp_ram_4_1_14))
+              (portRef DIA8 (instanceRef pdp_ram_5_1_10))
+              (portRef DIA8 (instanceRef pdp_ram_6_1_6))
+              (portRef DIA8 (instanceRef pdp_ram_7_1_2))))
+          (net datain16
+            (joined
+              (portRef (member Data 19))
+              (portRef DIA7 (instanceRef pdp_ram_0_1_30))
+              (portRef DIA7 (instanceRef pdp_ram_1_1_26))
+              (portRef DIA7 (instanceRef pdp_ram_2_1_22))
+              (portRef DIA7 (instanceRef pdp_ram_3_1_18))
+              (portRef DIA7 (instanceRef pdp_ram_4_1_14))
+              (portRef DIA7 (instanceRef pdp_ram_5_1_10))
+              (portRef DIA7 (instanceRef pdp_ram_6_1_6))
+              (portRef DIA7 (instanceRef pdp_ram_7_1_2))))
+          (net datain15
+            (joined
+              (portRef (member Data 20))
+              (portRef DIA6 (instanceRef pdp_ram_0_1_30))
+              (portRef DIA6 (instanceRef pdp_ram_1_1_26))
+              (portRef DIA6 (instanceRef pdp_ram_2_1_22))
+              (portRef DIA6 (instanceRef pdp_ram_3_1_18))
+              (portRef DIA6 (instanceRef pdp_ram_4_1_14))
+              (portRef DIA6 (instanceRef pdp_ram_5_1_10))
+              (portRef DIA6 (instanceRef pdp_ram_6_1_6))
+              (portRef DIA6 (instanceRef pdp_ram_7_1_2))))
+          (net datain14
+            (joined
+              (portRef (member Data 21))
+              (portRef DIA5 (instanceRef pdp_ram_0_1_30))
+              (portRef DIA5 (instanceRef pdp_ram_1_1_26))
+              (portRef DIA5 (instanceRef pdp_ram_2_1_22))
+              (portRef DIA5 (instanceRef pdp_ram_3_1_18))
+              (portRef DIA5 (instanceRef pdp_ram_4_1_14))
+              (portRef DIA5 (instanceRef pdp_ram_5_1_10))
+              (portRef DIA5 (instanceRef pdp_ram_6_1_6))
+              (portRef DIA5 (instanceRef pdp_ram_7_1_2))))
+          (net datain13
+            (joined
+              (portRef (member Data 22))
+              (portRef DIA4 (instanceRef pdp_ram_0_1_30))
+              (portRef DIA4 (instanceRef pdp_ram_1_1_26))
+              (portRef DIA4 (instanceRef pdp_ram_2_1_22))
+              (portRef DIA4 (instanceRef pdp_ram_3_1_18))
+              (portRef DIA4 (instanceRef pdp_ram_4_1_14))
+              (portRef DIA4 (instanceRef pdp_ram_5_1_10))
+              (portRef DIA4 (instanceRef pdp_ram_6_1_6))
+              (portRef DIA4 (instanceRef pdp_ram_7_1_2))))
+          (net datain12
+            (joined
+              (portRef (member Data 23))
+              (portRef DIA3 (instanceRef pdp_ram_0_1_30))
+              (portRef DIA3 (instanceRef pdp_ram_1_1_26))
+              (portRef DIA3 (instanceRef pdp_ram_2_1_22))
+              (portRef DIA3 (instanceRef pdp_ram_3_1_18))
+              (portRef DIA3 (instanceRef pdp_ram_4_1_14))
+              (portRef DIA3 (instanceRef pdp_ram_5_1_10))
+              (portRef DIA3 (instanceRef pdp_ram_6_1_6))
+              (portRef DIA3 (instanceRef pdp_ram_7_1_2))))
+          (net datain11
+            (joined
+              (portRef (member Data 24))
+              (portRef DIA2 (instanceRef pdp_ram_0_1_30))
+              (portRef DIA2 (instanceRef pdp_ram_1_1_26))
+              (portRef DIA2 (instanceRef pdp_ram_2_1_22))
+              (portRef DIA2 (instanceRef pdp_ram_3_1_18))
+              (portRef DIA2 (instanceRef pdp_ram_4_1_14))
+              (portRef DIA2 (instanceRef pdp_ram_5_1_10))
+              (portRef DIA2 (instanceRef pdp_ram_6_1_6))
+              (portRef DIA2 (instanceRef pdp_ram_7_1_2))))
+          (net datain10
+            (joined
+              (portRef (member Data 25))
+              (portRef DIA1 (instanceRef pdp_ram_0_1_30))
+              (portRef DIA1 (instanceRef pdp_ram_1_1_26))
+              (portRef DIA1 (instanceRef pdp_ram_2_1_22))
+              (portRef DIA1 (instanceRef pdp_ram_3_1_18))
+              (portRef DIA1 (instanceRef pdp_ram_4_1_14))
+              (portRef DIA1 (instanceRef pdp_ram_5_1_10))
+              (portRef DIA1 (instanceRef pdp_ram_6_1_6))
+              (portRef DIA1 (instanceRef pdp_ram_7_1_2))))
+          (net datain9
+            (joined
+              (portRef (member Data 26))
+              (portRef DIA0 (instanceRef pdp_ram_0_1_30))
+              (portRef DIA0 (instanceRef pdp_ram_1_1_26))
+              (portRef DIA0 (instanceRef pdp_ram_2_1_22))
+              (portRef DIA0 (instanceRef pdp_ram_3_1_18))
+              (portRef DIA0 (instanceRef pdp_ram_4_1_14))
+              (portRef DIA0 (instanceRef pdp_ram_5_1_10))
+              (portRef DIA0 (instanceRef pdp_ram_6_1_6))
+              (portRef DIA0 (instanceRef pdp_ram_7_1_2))))
+          (net datain8
+            (joined
+              (portRef (member Data 27))
+              (portRef DIA8 (instanceRef pdp_ram_0_0_31))
+              (portRef DIA8 (instanceRef pdp_ram_1_0_27))
+              (portRef DIA8 (instanceRef pdp_ram_2_0_23))
+              (portRef DIA8 (instanceRef pdp_ram_3_0_19))
+              (portRef DIA8 (instanceRef pdp_ram_4_0_15))
+              (portRef DIA8 (instanceRef pdp_ram_5_0_11))
+              (portRef DIA8 (instanceRef pdp_ram_6_0_7))
+              (portRef DIA8 (instanceRef pdp_ram_7_0_3))))
+          (net datain7
+            (joined
+              (portRef (member Data 28))
+              (portRef DIA7 (instanceRef pdp_ram_0_0_31))
+              (portRef DIA7 (instanceRef pdp_ram_1_0_27))
+              (portRef DIA7 (instanceRef pdp_ram_2_0_23))
+              (portRef DIA7 (instanceRef pdp_ram_3_0_19))
+              (portRef DIA7 (instanceRef pdp_ram_4_0_15))
+              (portRef DIA7 (instanceRef pdp_ram_5_0_11))
+              (portRef DIA7 (instanceRef pdp_ram_6_0_7))
+              (portRef DIA7 (instanceRef pdp_ram_7_0_3))))
+          (net datain6
+            (joined
+              (portRef (member Data 29))
+              (portRef DIA6 (instanceRef pdp_ram_0_0_31))
+              (portRef DIA6 (instanceRef pdp_ram_1_0_27))
+              (portRef DIA6 (instanceRef pdp_ram_2_0_23))
+              (portRef DIA6 (instanceRef pdp_ram_3_0_19))
+              (portRef DIA6 (instanceRef pdp_ram_4_0_15))
+              (portRef DIA6 (instanceRef pdp_ram_5_0_11))
+              (portRef DIA6 (instanceRef pdp_ram_6_0_7))
+              (portRef DIA6 (instanceRef pdp_ram_7_0_3))))
+          (net datain5
+            (joined
+              (portRef (member Data 30))
+              (portRef DIA5 (instanceRef pdp_ram_0_0_31))
+              (portRef DIA5 (instanceRef pdp_ram_1_0_27))
+              (portRef DIA5 (instanceRef pdp_ram_2_0_23))
+              (portRef DIA5 (instanceRef pdp_ram_3_0_19))
+              (portRef DIA5 (instanceRef pdp_ram_4_0_15))
+              (portRef DIA5 (instanceRef pdp_ram_5_0_11))
+              (portRef DIA5 (instanceRef pdp_ram_6_0_7))
+              (portRef DIA5 (instanceRef pdp_ram_7_0_3))))
+          (net datain4
+            (joined
+              (portRef (member Data 31))
+              (portRef DIA4 (instanceRef pdp_ram_0_0_31))
+              (portRef DIA4 (instanceRef pdp_ram_1_0_27))
+              (portRef DIA4 (instanceRef pdp_ram_2_0_23))
+              (portRef DIA4 (instanceRef pdp_ram_3_0_19))
+              (portRef DIA4 (instanceRef pdp_ram_4_0_15))
+              (portRef DIA4 (instanceRef pdp_ram_5_0_11))
+              (portRef DIA4 (instanceRef pdp_ram_6_0_7))
+              (portRef DIA4 (instanceRef pdp_ram_7_0_3))))
+          (net datain3
+            (joined
+              (portRef (member Data 32))
+              (portRef DIA3 (instanceRef pdp_ram_0_0_31))
+              (portRef DIA3 (instanceRef pdp_ram_1_0_27))
+              (portRef DIA3 (instanceRef pdp_ram_2_0_23))
+              (portRef DIA3 (instanceRef pdp_ram_3_0_19))
+              (portRef DIA3 (instanceRef pdp_ram_4_0_15))
+              (portRef DIA3 (instanceRef pdp_ram_5_0_11))
+              (portRef DIA3 (instanceRef pdp_ram_6_0_7))
+              (portRef DIA3 (instanceRef pdp_ram_7_0_3))))
+          (net datain2
+            (joined
+              (portRef (member Data 33))
+              (portRef DIA2 (instanceRef pdp_ram_0_0_31))
+              (portRef DIA2 (instanceRef pdp_ram_1_0_27))
+              (portRef DIA2 (instanceRef pdp_ram_2_0_23))
+              (portRef DIA2 (instanceRef pdp_ram_3_0_19))
+              (portRef DIA2 (instanceRef pdp_ram_4_0_15))
+              (portRef DIA2 (instanceRef pdp_ram_5_0_11))
+              (portRef DIA2 (instanceRef pdp_ram_6_0_7))
+              (portRef DIA2 (instanceRef pdp_ram_7_0_3))))
+          (net datain1
+            (joined
+              (portRef (member Data 34))
+              (portRef DIA1 (instanceRef pdp_ram_0_0_31))
+              (portRef DIA1 (instanceRef pdp_ram_1_0_27))
+              (portRef DIA1 (instanceRef pdp_ram_2_0_23))
+              (portRef DIA1 (instanceRef pdp_ram_3_0_19))
+              (portRef DIA1 (instanceRef pdp_ram_4_0_15))
+              (portRef DIA1 (instanceRef pdp_ram_5_0_11))
+              (portRef DIA1 (instanceRef pdp_ram_6_0_7))
+              (portRef DIA1 (instanceRef pdp_ram_7_0_3))))
+          (net datain0
+            (joined
+              (portRef (member Data 35))
+              (portRef DIA0 (instanceRef pdp_ram_0_0_31))
+              (portRef DIA0 (instanceRef pdp_ram_1_0_27))
+              (portRef DIA0 (instanceRef pdp_ram_2_0_23))
+              (portRef DIA0 (instanceRef pdp_ram_3_0_19))
+              (portRef DIA0 (instanceRef pdp_ram_4_0_15))
+              (portRef DIA0 (instanceRef pdp_ram_5_0_11))
+              (portRef DIA0 (instanceRef pdp_ram_6_0_7))
+              (portRef DIA0 (instanceRef pdp_ram_7_0_3))))))))
+  (design fifo_36x16k_oreg
+    (cellRef fifo_36x16k_oreg
+      (libraryRef ORCLIB)))
+)

diff --git a/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.fdc b/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.fdc
new file mode 100644 (file)
index 0000000..6fbcac9
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.fdc
@@ -0,0 +1,2 @@
+###==== Start Configuration
+

diff --git a/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.lpc b/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.lpc
new file mode 100644 (file)
index 0000000..0b5cbed
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.lpc
@@ -0,0 +1,50 @@
+[Device]
+Family=ecp5um
+PartType=LFE5UM-85F
+PartName=LFE5UM-85F-8MG285C
+SpeedGrade=8
+Package=CSFBGA285
+OperatingCondition=COM
+Status=C
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO
+CoreRevision=5.0
+ModuleName=fifo_36x16k_oreg
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=03/18/2015
+Time=14:42:06
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=16384
+Width=36
+regout=1
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=1
+PfMode=Dynamic - Single Threshold
+PfAssert=508
+PfDeassert=506
+Reset=Async
+Reset1=Sync
+RDataCount=1
+EnECC=0
+EnFWFT=0
+
+[Command]
+cmd_line= -w -n fifo_36x16k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 16384 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill

diff --git a/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.ngd b/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.ngd
new file mode 100644 (file)
index 0000000..46e0192
Binary files /dev/null and b/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.ngd differ

diff --git a/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.ngo b/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.ngo
new file mode 100644 (file)
index 0000000..cbb3015
Binary files /dev/null and b/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.ngo differ

diff --git a/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.vhd b/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.vhd
new file mode 100644 (file)
index 0000000..ab8fb13
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.vhd
@@ -0,0 +1,3166 @@
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80
+-- Module  Version: 5.0
+--/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x16k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 16384 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.fdc 
+
+-- Wed Mar 18 14:42:08 2015
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity fifo_36x16k_oreg is
+    port (
+        Data: in  std_logic_vector(35 downto 0); 
+        Clock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        AmFullThresh: in  std_logic_vector(13 downto 0); 
+        Q: out  std_logic_vector(35 downto 0); 
+        WCNT: out  std_logic_vector(14 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic; 
+        AlmostFull: out  std_logic);
+end fifo_36x16k_oreg;
+
+architecture Structure of fifo_36x16k_oreg is
+
+    -- internal signal declarations
+    signal invout_2: std_logic;
+    signal invout_1: std_logic;
+    signal rden_i_inv: std_logic;
+    signal invout_0: std_logic;
+    signal r_nw: std_logic;
+    signal fcnt_en: std_logic;
+    signal empty_i: std_logic;
+    signal empty_d: std_logic;
+    signal full_i: std_logic;
+    signal full_d: std_logic;
+    signal wptr_0: std_logic;
+    signal wptr_1: std_logic;
+    signal wptr_2: std_logic;
+    signal wptr_3: std_logic;
+    signal wptr_4: std_logic;
+    signal wptr_5: std_logic;
+    signal wptr_6: std_logic;
+    signal wptr_7: std_logic;
+    signal wptr_8: std_logic;
+    signal wptr_9: std_logic;
+    signal wptr_10: std_logic;
+    signal wptr_11: std_logic;
+    signal wptr_12: std_logic;
+    signal wptr_13: std_logic;
+    signal wptr_14: std_logic;
+    signal rptr_14: std_logic;
+    signal rptr_11_ff: std_logic;
+    signal rptr_12_ff: std_logic;
+    signal rptr_13_ff: std_logic;
+    signal ifcount_0: std_logic;
+    signal ifcount_1: std_logic;
+    signal bdcnt_bctr_ci: std_logic;
+    signal ifcount_2: std_logic;
+    signal ifcount_3: std_logic;
+    signal co0: std_logic;
+    signal ifcount_4: std_logic;
+    signal ifcount_5: std_logic;
+    signal co1: std_logic;
+    signal ifcount_6: std_logic;
+    signal ifcount_7: std_logic;
+    signal co2: std_logic;
+    signal ifcount_8: std_logic;
+    signal ifcount_9: std_logic;
+    signal co3: std_logic;
+    signal ifcount_10: std_logic;
+    signal ifcount_11: std_logic;
+    signal co4: std_logic;
+    signal ifcount_12: std_logic;
+    signal ifcount_13: std_logic;
+    signal co5: std_logic;
+    signal ifcount_14: std_logic;
+    signal co7: std_logic;
+    signal co6: std_logic;
+    signal cmp_ci: std_logic;
+    signal rden_i: std_logic;
+    signal co0_1: std_logic;
+    signal co1_1: std_logic;
+    signal co2_1: std_logic;
+    signal co3_1: std_logic;
+    signal co4_1: std_logic;
+    signal co5_1: std_logic;
+    signal co6_1: std_logic;
+    signal cmp_le_1: std_logic;
+    signal cmp_le_1_c: std_logic;
+    signal cmp_ci_1: std_logic;
+    signal fcount_0: std_logic;
+    signal fcount_1: std_logic;
+    signal co0_2: std_logic;
+    signal fcount_2: std_logic;
+    signal fcount_3: std_logic;
+    signal co1_2: std_logic;
+    signal fcount_4: std_logic;
+    signal fcount_5: std_logic;
+    signal co2_2: std_logic;
+    signal fcount_6: std_logic;
+    signal fcount_7: std_logic;
+    signal co3_2: std_logic;
+    signal fcount_8: std_logic;
+    signal fcount_9: std_logic;
+    signal co4_2: std_logic;
+    signal fcount_10: std_logic;
+    signal fcount_11: std_logic;
+    signal co5_2: std_logic;
+    signal fcount_12: std_logic;
+    signal fcount_13: std_logic;
+    signal co6_2: std_logic;
+    signal wren_i_inv: std_logic;
+    signal fcount_14: std_logic;
+    signal cmp_ge_d1: std_logic;
+    signal cmp_ge_d1_c: std_logic;
+    signal iwcount_0: std_logic;
+    signal iwcount_1: std_logic;
+    signal w_ctr_ci: std_logic;
+    signal iwcount_2: std_logic;
+    signal iwcount_3: std_logic;
+    signal co0_3: std_logic;
+    signal iwcount_4: std_logic;
+    signal iwcount_5: std_logic;
+    signal co1_3: std_logic;
+    signal iwcount_6: std_logic;
+    signal iwcount_7: std_logic;
+    signal co2_3: std_logic;
+    signal iwcount_8: std_logic;
+    signal iwcount_9: std_logic;
+    signal co3_3: std_logic;
+    signal iwcount_10: std_logic;
+    signal iwcount_11: std_logic;
+    signal co4_3: std_logic;
+    signal iwcount_12: std_logic;
+    signal iwcount_13: std_logic;
+    signal co5_3: std_logic;
+    signal iwcount_14: std_logic;
+    signal co7_1: std_logic;
+    signal co6_3: std_logic;
+    signal wcount_14: std_logic;
+    signal ircount_0: std_logic;
+    signal ircount_1: std_logic;
+    signal r_ctr_ci: std_logic;
+    signal rcount_0: std_logic;
+    signal rcount_1: std_logic;
+    signal ircount_2: std_logic;
+    signal ircount_3: std_logic;
+    signal co0_4: std_logic;
+    signal rcount_2: std_logic;
+    signal rcount_3: std_logic;
+    signal ircount_4: std_logic;
+    signal ircount_5: std_logic;
+    signal co1_4: std_logic;
+    signal rcount_4: std_logic;
+    signal rcount_5: std_logic;
+    signal ircount_6: std_logic;
+    signal ircount_7: std_logic;
+    signal co2_4: std_logic;
+    signal rcount_6: std_logic;
+    signal rcount_7: std_logic;
+    signal ircount_8: std_logic;
+    signal ircount_9: std_logic;
+    signal co3_4: std_logic;
+    signal rcount_8: std_logic;
+    signal rcount_9: std_logic;
+    signal ircount_10: std_logic;
+    signal ircount_11: std_logic;
+    signal co4_4: std_logic;
+    signal rcount_10: std_logic;
+    signal rcount_11: std_logic;
+    signal ircount_12: std_logic;
+    signal ircount_13: std_logic;
+    signal co5_4: std_logic;
+    signal rcount_12: std_logic;
+    signal rcount_13: std_logic;
+    signal ircount_14: std_logic;
+    signal co7_2: std_logic;
+    signal co6_4: std_logic;
+    signal rcount_14: std_logic;
+    signal mdout1_7_0: std_logic;
+    signal mdout1_6_0: std_logic;
+    signal mdout1_5_0: std_logic;
+    signal mdout1_4_0: std_logic;
+    signal mdout1_3_0: std_logic;
+    signal mdout1_2_0: std_logic;
+    signal mdout1_1_0: std_logic;
+    signal mdout1_0_0: std_logic;
+    signal mdout1_7_1: std_logic;
+    signal mdout1_6_1: std_logic;
+    signal mdout1_5_1: std_logic;
+    signal mdout1_4_1: std_logic;
+    signal mdout1_3_1: std_logic;
+    signal mdout1_2_1: std_logic;
+    signal mdout1_1_1: std_logic;
+    signal mdout1_0_1: std_logic;
+    signal mdout1_7_2: std_logic;
+    signal mdout1_6_2: std_logic;
+    signal mdout1_5_2: std_logic;
+    signal mdout1_4_2: std_logic;
+    signal mdout1_3_2: std_logic;
+    signal mdout1_2_2: std_logic;
+    signal mdout1_1_2: std_logic;
+    signal mdout1_0_2: std_logic;
+    signal mdout1_7_3: std_logic;
+    signal mdout1_6_3: std_logic;
+    signal mdout1_5_3: std_logic;
+    signal mdout1_4_3: std_logic;
+    signal mdout1_3_3: std_logic;
+    signal mdout1_2_3: std_logic;
+    signal mdout1_1_3: std_logic;
+    signal mdout1_0_3: std_logic;
+    signal mdout1_7_4: std_logic;
+    signal mdout1_6_4: std_logic;
+    signal mdout1_5_4: std_logic;
+    signal mdout1_4_4: std_logic;
+    signal mdout1_3_4: std_logic;
+    signal mdout1_2_4: std_logic;
+    signal mdout1_1_4: std_logic;
+    signal mdout1_0_4: std_logic;
+    signal mdout1_7_5: std_logic;
+    signal mdout1_6_5: std_logic;
+    signal mdout1_5_5: std_logic;
+    signal mdout1_4_5: std_logic;
+    signal mdout1_3_5: std_logic;
+    signal mdout1_2_5: std_logic;
+    signal mdout1_1_5: std_logic;
+    signal mdout1_0_5: std_logic;
+    signal mdout1_7_6: std_logic;
+    signal mdout1_6_6: std_logic;
+    signal mdout1_5_6: std_logic;
+    signal mdout1_4_6: std_logic;
+    signal mdout1_3_6: std_logic;
+    signal mdout1_2_6: std_logic;
+    signal mdout1_1_6: std_logic;
+    signal mdout1_0_6: std_logic;
+    signal mdout1_7_7: std_logic;
+    signal mdout1_6_7: std_logic;
+    signal mdout1_5_7: std_logic;
+    signal mdout1_4_7: std_logic;
+    signal mdout1_3_7: std_logic;
+    signal mdout1_2_7: std_logic;
+    signal mdout1_1_7: std_logic;
+    signal mdout1_0_7: std_logic;
+    signal mdout1_7_8: std_logic;
+    signal mdout1_6_8: std_logic;
+    signal mdout1_5_8: std_logic;
+    signal mdout1_4_8: std_logic;
+    signal mdout1_3_8: std_logic;
+    signal mdout1_2_8: std_logic;
+    signal mdout1_1_8: std_logic;
+    signal mdout1_0_8: std_logic;
+    signal mdout1_7_9: std_logic;
+    signal mdout1_6_9: std_logic;
+    signal mdout1_5_9: std_logic;
+    signal mdout1_4_9: std_logic;
+    signal mdout1_3_9: std_logic;
+    signal mdout1_2_9: std_logic;
+    signal mdout1_1_9: std_logic;
+    signal mdout1_0_9: std_logic;
+    signal mdout1_7_10: std_logic;
+    signal mdout1_6_10: std_logic;
+    signal mdout1_5_10: std_logic;
+    signal mdout1_4_10: std_logic;
+    signal mdout1_3_10: std_logic;
+    signal mdout1_2_10: std_logic;
+    signal mdout1_1_10: std_logic;
+    signal mdout1_0_10: std_logic;
+    signal mdout1_7_11: std_logic;
+    signal mdout1_6_11: std_logic;
+    signal mdout1_5_11: std_logic;
+    signal mdout1_4_11: std_logic;
+    signal mdout1_3_11: std_logic;
+    signal mdout1_2_11: std_logic;
+    signal mdout1_1_11: std_logic;
+    signal mdout1_0_11: std_logic;
+    signal mdout1_7_12: std_logic;
+    signal mdout1_6_12: std_logic;
+    signal mdout1_5_12: std_logic;
+    signal mdout1_4_12: std_logic;
+    signal mdout1_3_12: std_logic;
+    signal mdout1_2_12: std_logic;
+    signal mdout1_1_12: std_logic;
+    signal mdout1_0_12: std_logic;
+    signal mdout1_7_13: std_logic;
+    signal mdout1_6_13: std_logic;
+    signal mdout1_5_13: std_logic;
+    signal mdout1_4_13: std_logic;
+    signal mdout1_3_13: std_logic;
+    signal mdout1_2_13: std_logic;
+    signal mdout1_1_13: std_logic;
+    signal mdout1_0_13: std_logic;
+    signal mdout1_7_14: std_logic;
+    signal mdout1_6_14: std_logic;
+    signal mdout1_5_14: std_logic;
+    signal mdout1_4_14: std_logic;
+    signal mdout1_3_14: std_logic;
+    signal mdout1_2_14: std_logic;
+    signal mdout1_1_14: std_logic;
+    signal mdout1_0_14: std_logic;
+    signal mdout1_7_15: std_logic;
+    signal mdout1_6_15: std_logic;
+    signal mdout1_5_15: std_logic;
+    signal mdout1_4_15: std_logic;
+    signal mdout1_3_15: std_logic;
+    signal mdout1_2_15: std_logic;
+    signal mdout1_1_15: std_logic;
+    signal mdout1_0_15: std_logic;
+    signal mdout1_7_16: std_logic;
+    signal mdout1_6_16: std_logic;
+    signal mdout1_5_16: std_logic;
+    signal mdout1_4_16: std_logic;
+    signal mdout1_3_16: std_logic;
+    signal mdout1_2_16: std_logic;
+    signal mdout1_1_16: std_logic;
+    signal mdout1_0_16: std_logic;
+    signal mdout1_7_17: std_logic;
+    signal mdout1_6_17: std_logic;
+    signal mdout1_5_17: std_logic;
+    signal mdout1_4_17: std_logic;
+    signal mdout1_3_17: std_logic;
+    signal mdout1_2_17: std_logic;
+    signal mdout1_1_17: std_logic;
+    signal mdout1_0_17: std_logic;
+    signal mdout1_7_18: std_logic;
+    signal mdout1_6_18: std_logic;
+    signal mdout1_5_18: std_logic;
+    signal mdout1_4_18: std_logic;
+    signal mdout1_3_18: std_logic;
+    signal mdout1_2_18: std_logic;
+    signal mdout1_1_18: std_logic;
+    signal mdout1_0_18: std_logic;
+    signal mdout1_7_19: std_logic;
+    signal mdout1_6_19: std_logic;
+    signal mdout1_5_19: std_logic;
+    signal mdout1_4_19: std_logic;
+    signal mdout1_3_19: std_logic;
+    signal mdout1_2_19: std_logic;
+    signal mdout1_1_19: std_logic;
+    signal mdout1_0_19: std_logic;
+    signal mdout1_7_20: std_logic;
+    signal mdout1_6_20: std_logic;
+    signal mdout1_5_20: std_logic;
+    signal mdout1_4_20: std_logic;
+    signal mdout1_3_20: std_logic;
+    signal mdout1_2_20: std_logic;
+    signal mdout1_1_20: std_logic;
+    signal mdout1_0_20: std_logic;
+    signal mdout1_7_21: std_logic;
+    signal mdout1_6_21: std_logic;
+    signal mdout1_5_21: std_logic;
+    signal mdout1_4_21: std_logic;
+    signal mdout1_3_21: std_logic;
+    signal mdout1_2_21: std_logic;
+    signal mdout1_1_21: std_logic;
+    signal mdout1_0_21: std_logic;
+    signal mdout1_7_22: std_logic;
+    signal mdout1_6_22: std_logic;
+    signal mdout1_5_22: std_logic;
+    signal mdout1_4_22: std_logic;
+    signal mdout1_3_22: std_logic;
+    signal mdout1_2_22: std_logic;
+    signal mdout1_1_22: std_logic;
+    signal mdout1_0_22: std_logic;
+    signal mdout1_7_23: std_logic;
+    signal mdout1_6_23: std_logic;
+    signal mdout1_5_23: std_logic;
+    signal mdout1_4_23: std_logic;
+    signal mdout1_3_23: std_logic;
+    signal mdout1_2_23: std_logic;
+    signal mdout1_1_23: std_logic;
+    signal mdout1_0_23: std_logic;
+    signal mdout1_7_24: std_logic;
+    signal mdout1_6_24: std_logic;
+    signal mdout1_5_24: std_logic;
+    signal mdout1_4_24: std_logic;
+    signal mdout1_3_24: std_logic;
+    signal mdout1_2_24: std_logic;
+    signal mdout1_1_24: std_logic;
+    signal mdout1_0_24: std_logic;
+    signal mdout1_7_25: std_logic;
+    signal mdout1_6_25: std_logic;
+    signal mdout1_5_25: std_logic;
+    signal mdout1_4_25: std_logic;
+    signal mdout1_3_25: std_logic;
+    signal mdout1_2_25: std_logic;
+    signal mdout1_1_25: std_logic;
+    signal mdout1_0_25: std_logic;
+    signal mdout1_7_26: std_logic;
+    signal mdout1_6_26: std_logic;
+    signal mdout1_5_26: std_logic;
+    signal mdout1_4_26: std_logic;
+    signal mdout1_3_26: std_logic;
+    signal mdout1_2_26: std_logic;
+    signal mdout1_1_26: std_logic;
+    signal mdout1_0_26: std_logic;
+    signal mdout1_7_27: std_logic;
+    signal mdout1_6_27: std_logic;
+    signal mdout1_5_27: std_logic;
+    signal mdout1_4_27: std_logic;
+    signal mdout1_3_27: std_logic;
+    signal mdout1_2_27: std_logic;
+    signal mdout1_1_27: std_logic;
+    signal mdout1_0_27: std_logic;
+    signal mdout1_7_28: std_logic;
+    signal mdout1_6_28: std_logic;
+    signal mdout1_5_28: std_logic;
+    signal mdout1_4_28: std_logic;
+    signal mdout1_3_28: std_logic;
+    signal mdout1_2_28: std_logic;
+    signal mdout1_1_28: std_logic;
+    signal mdout1_0_28: std_logic;
+    signal mdout1_7_29: std_logic;
+    signal mdout1_6_29: std_logic;
+    signal mdout1_5_29: std_logic;
+    signal mdout1_4_29: std_logic;
+    signal mdout1_3_29: std_logic;
+    signal mdout1_2_29: std_logic;
+    signal mdout1_1_29: std_logic;
+    signal mdout1_0_29: std_logic;
+    signal mdout1_7_30: std_logic;
+    signal mdout1_6_30: std_logic;
+    signal mdout1_5_30: std_logic;
+    signal mdout1_4_30: std_logic;
+    signal mdout1_3_30: std_logic;
+    signal mdout1_2_30: std_logic;
+    signal mdout1_1_30: std_logic;
+    signal mdout1_0_30: std_logic;
+    signal mdout1_7_31: std_logic;
+    signal mdout1_6_31: std_logic;
+    signal mdout1_5_31: std_logic;
+    signal mdout1_4_31: std_logic;
+    signal mdout1_3_31: std_logic;
+    signal mdout1_2_31: std_logic;
+    signal mdout1_1_31: std_logic;
+    signal mdout1_0_31: std_logic;
+    signal mdout1_7_32: std_logic;
+    signal mdout1_6_32: std_logic;
+    signal mdout1_5_32: std_logic;
+    signal mdout1_4_32: std_logic;
+    signal mdout1_3_32: std_logic;
+    signal mdout1_2_32: std_logic;
+    signal mdout1_1_32: std_logic;
+    signal mdout1_0_32: std_logic;
+    signal mdout1_7_33: std_logic;
+    signal mdout1_6_33: std_logic;
+    signal mdout1_5_33: std_logic;
+    signal mdout1_4_33: std_logic;
+    signal mdout1_3_33: std_logic;
+    signal mdout1_2_33: std_logic;
+    signal mdout1_1_33: std_logic;
+    signal mdout1_0_33: std_logic;
+    signal mdout1_7_34: std_logic;
+    signal mdout1_6_34: std_logic;
+    signal mdout1_5_34: std_logic;
+    signal mdout1_4_34: std_logic;
+    signal mdout1_3_34: std_logic;
+    signal mdout1_2_34: std_logic;
+    signal mdout1_1_34: std_logic;
+    signal mdout1_0_34: std_logic;
+    signal rptr_13_ff2: std_logic;
+    signal rptr_12_ff2: std_logic;
+    signal rptr_11_ff2: std_logic;
+    signal mdout1_7_35: std_logic;
+    signal mdout1_6_35: std_logic;
+    signal mdout1_5_35: std_logic;
+    signal mdout1_4_35: std_logic;
+    signal mdout1_3_35: std_logic;
+    signal mdout1_2_35: std_logic;
+    signal mdout1_1_35: std_logic;
+    signal mdout1_0_35: std_logic;
+    signal wcnt_sub_0: std_logic;
+    signal rptr_0: std_logic;
+    signal cnt_con_inv: std_logic;
+    signal wcount_0: std_logic;
+    signal cnt_con: std_logic;
+    signal precin: std_logic;
+    signal wcnt_sub_1: std_logic;
+    signal wcnt_sub_2: std_logic;
+    signal rptr_2: std_logic;
+    signal rptr_1: std_logic;
+    signal wcount_2: std_logic;
+    signal wcount_1: std_logic;
+    signal co0_5: std_logic;
+    signal wcnt_sub_3: std_logic;
+    signal wcnt_sub_4: std_logic;
+    signal rptr_4: std_logic;
+    signal rptr_3: std_logic;
+    signal wcount_4: std_logic;
+    signal wcount_3: std_logic;
+    signal co1_5: std_logic;
+    signal wcnt_sub_5: std_logic;
+    signal wcnt_sub_6: std_logic;
+    signal rptr_6: std_logic;
+    signal rptr_5: std_logic;
+    signal wcount_6: std_logic;
+    signal wcount_5: std_logic;
+    signal co2_5: std_logic;
+    signal wcnt_sub_7: std_logic;
+    signal wcnt_sub_8: std_logic;
+    signal rptr_8: std_logic;
+    signal rptr_7: std_logic;
+    signal wcount_8: std_logic;
+    signal wcount_7: std_logic;
+    signal co3_5: std_logic;
+    signal wcnt_sub_9: std_logic;
+    signal wcnt_sub_10: std_logic;
+    signal rptr_10: std_logic;
+    signal rptr_9: std_logic;
+    signal wcount_10: std_logic;
+    signal wcount_9: std_logic;
+    signal co4_5: std_logic;
+    signal wcnt_sub_11: std_logic;
+    signal wcnt_sub_12: std_logic;
+    signal rptr_12: std_logic;
+    signal rptr_11: std_logic;
+    signal wcount_12: std_logic;
+    signal wcount_11: std_logic;
+    signal co5_5: std_logic;
+    signal wcnt_sub_13: std_logic;
+    signal wcnt_sub_14: std_logic;
+    signal rptr_13: std_logic;
+    signal wcnt_sub_msb: std_logic;
+    signal wcount_13: std_logic;
+    signal co6_5: std_logic;
+    signal co7_3d: std_logic;
+    signal co7_3: std_logic;
+    signal wren_i: std_logic;
+    signal cmp_ci_2: std_logic;
+    signal wcnt_reg_0: std_logic;
+    signal wcnt_reg_1: std_logic;
+    signal co0_6: std_logic;
+    signal wcnt_reg_2: std_logic;
+    signal wcnt_reg_3: std_logic;
+    signal co1_6: std_logic;
+    signal wcnt_reg_4: std_logic;
+    signal wcnt_reg_5: std_logic;
+    signal co2_6: std_logic;
+    signal wcnt_reg_6: std_logic;
+    signal wcnt_reg_7: std_logic;
+    signal co3_6: std_logic;
+    signal wcnt_reg_8: std_logic;
+    signal wcnt_reg_9: std_logic;
+    signal co4_6: std_logic;
+    signal wcnt_reg_10: std_logic;
+    signal wcnt_reg_11: std_logic;
+    signal co5_6: std_logic;
+    signal wcnt_reg_12: std_logic;
+    signal wcnt_reg_13: std_logic;
+    signal co6_6: std_logic;
+    signal wcnt_reg_14: std_logic;
+    signal af_set: std_logic;
+    signal scuba_vhi: std_logic;
+    signal scuba_vlo: std_logic;
+    signal af_set_c: std_logic;
+
+    attribute MEM_LPC_FILE : string; 
+    attribute MEM_INIT_FILE : string; 
+    attribute GSR : string; 
+    attribute MEM_LPC_FILE of pdp_ram_0_0_31 : label is "fifo_36x16k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_0_31 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_0_1_30 : label is "fifo_36x16k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_1_30 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_0_2_29 : label is "fifo_36x16k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_2_29 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_0_3_28 : label is "fifo_36x16k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_3_28 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_1_0_27 : label is "fifo_36x16k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_1_0_27 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_1_1_26 : label is "fifo_36x16k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_1_1_26 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_1_2_25 : label is "fifo_36x16k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_1_2_25 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_1_3_24 : label is "fifo_36x16k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_1_3_24 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_2_0_23 : label is "fifo_36x16k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_2_0_23 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_2_1_22 : label is "fifo_36x16k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_2_1_22 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_2_2_21 : label is "fifo_36x16k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_2_2_21 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_2_3_20 : label is "fifo_36x16k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_2_3_20 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_3_0_19 : label is "fifo_36x16k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_3_0_19 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_3_1_18 : label is "fifo_36x16k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_3_1_18 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_3_2_17 : label is "fifo_36x16k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_3_2_17 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_3_3_16 : label is "fifo_36x16k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_3_3_16 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_4_0_15 : label is "fifo_36x16k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_4_0_15 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_4_1_14 : label is "fifo_36x16k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_4_1_14 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_4_2_13 : label is "fifo_36x16k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_4_2_13 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_4_3_12 : label is "fifo_36x16k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_4_3_12 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_5_0_11 : label is "fifo_36x16k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_5_0_11 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_5_1_10 : label is "fifo_36x16k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_5_1_10 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_5_2_9 : label is "fifo_36x16k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_5_2_9 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_5_3_8 : label is "fifo_36x16k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_5_3_8 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_6_0_7 : label is "fifo_36x16k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_6_0_7 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_6_1_6 : label is "fifo_36x16k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_6_1_6 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_6_2_5 : label is "fifo_36x16k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_6_2_5 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_6_3_4 : label is "fifo_36x16k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_6_3_4 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_7_0_3 : label is "fifo_36x16k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_7_0_3 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_7_1_2 : label is "fifo_36x16k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_7_1_2 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_7_2_1 : label is "fifo_36x16k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_7_2_1 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_7_3_0 : label is "fifo_36x16k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_7_3_0 : label is "";
+    attribute GSR of FF_98 : label is "ENABLED";
+    attribute GSR of FF_97 : label is "ENABLED";
+    attribute GSR of FF_96 : label is "ENABLED";
+    attribute GSR of FF_95 : label is "ENABLED";
+    attribute GSR of FF_94 : label is "ENABLED";
+    attribute GSR of FF_93 : label is "ENABLED";
+    attribute GSR of FF_92 : label is "ENABLED";
+    attribute GSR of FF_91 : label is "ENABLED";
+    attribute GSR of FF_90 : label is "ENABLED";
+    attribute GSR of FF_89 : label is "ENABLED";
+    attribute GSR of FF_88 : label is "ENABLED";
+    attribute GSR of FF_87 : label is "ENABLED";
+    attribute GSR of FF_86 : label is "ENABLED";
+    attribute GSR of FF_85 : label is "ENABLED";
+    attribute GSR of FF_84 : label is "ENABLED";
+    attribute GSR of FF_83 : label is "ENABLED";
+    attribute GSR of FF_82 : label is "ENABLED";
+    attribute GSR of FF_81 : label is "ENABLED";
+    attribute GSR of FF_80 : label is "ENABLED";
+    attribute GSR of FF_79 : label is "ENABLED";
+    attribute GSR of FF_78 : label is "ENABLED";
+    attribute GSR of FF_77 : label is "ENABLED";
+    attribute GSR of FF_76 : label is "ENABLED";
+    attribute GSR of FF_75 : label is "ENABLED";
+    attribute GSR of FF_74 : label is "ENABLED";
+    attribute GSR of FF_73 : label is "ENABLED";
+    attribute GSR of FF_72 : label is "ENABLED";
+    attribute GSR of FF_71 : label is "ENABLED";
+    attribute GSR of FF_70 : label is "ENABLED";
+    attribute GSR of FF_69 : label is "ENABLED";
+    attribute GSR of FF_68 : label is "ENABLED";
+    attribute GSR of FF_67 : label is "ENABLED";
+    attribute GSR of FF_66 : label is "ENABLED";
+    attribute GSR of FF_65 : label is "ENABLED";
+    attribute GSR of FF_64 : label is "ENABLED";
+    attribute GSR of FF_63 : label is "ENABLED";
+    attribute GSR of FF_62 : label is "ENABLED";
+    attribute GSR of FF_61 : label is "ENABLED";
+    attribute GSR of FF_60 : label is "ENABLED";
+    attribute GSR of FF_59 : label is "ENABLED";
+    attribute GSR of FF_58 : label is "ENABLED";
+    attribute GSR of FF_57 : label is "ENABLED";
+    attribute GSR of FF_56 : label is "ENABLED";
+    attribute GSR of FF_55 : label is "ENABLED";
+    attribute GSR of FF_54 : label is "ENABLED";
+    attribute GSR of FF_53 : label is "ENABLED";
+    attribute GSR of FF_52 : label is "ENABLED";
+    attribute GSR of FF_51 : label is "ENABLED";
+    attribute GSR of FF_50 : label is "ENABLED";
+    attribute GSR of FF_49 : label is "ENABLED";
+    attribute GSR of FF_48 : label is "ENABLED";
+    attribute GSR of FF_47 : label is "ENABLED";
+    attribute GSR of FF_46 : label is "ENABLED";
+    attribute GSR of FF_45 : label is "ENABLED";
+    attribute GSR of FF_44 : label is "ENABLED";
+    attribute GSR of FF_43 : label is "ENABLED";
+    attribute GSR of FF_42 : label is "ENABLED";
+    attribute GSR of FF_41 : label is "ENABLED";
+    attribute GSR of FF_40 : label is "ENABLED";
+    attribute GSR of FF_39 : label is "ENABLED";
+    attribute GSR of FF_38 : label is "ENABLED";
+    attribute GSR of FF_37 : label is "ENABLED";
+    attribute GSR of FF_36 : label is "ENABLED";
+    attribute GSR of FF_35 : label is "ENABLED";
+    attribute GSR of FF_34 : label is "ENABLED";
+    attribute GSR of FF_33 : label is "ENABLED";
+    attribute GSR of FF_32 : label is "ENABLED";
+    attribute GSR of FF_31 : label is "ENABLED";
+    attribute GSR of FF_30 : label is "ENABLED";
+    attribute GSR of FF_29 : label is "ENABLED";
+    attribute GSR of FF_28 : label is "ENABLED";
+    attribute GSR of FF_27 : label is "ENABLED";
+    attribute GSR of FF_26 : label is "ENABLED";
+    attribute GSR of FF_25 : label is "ENABLED";
+    attribute GSR of FF_24 : label is "ENABLED";
+    attribute GSR of FF_23 : label is "ENABLED";
+    attribute GSR of FF_22 : label is "ENABLED";
+    attribute GSR of FF_21 : label is "ENABLED";
+    attribute GSR of FF_20 : label is "ENABLED";
+    attribute GSR of FF_19 : label is "ENABLED";
+    attribute GSR of FF_18 : label is "ENABLED";
+    attribute GSR of FF_17 : label is "ENABLED";
+    attribute GSR of FF_16 : label is "ENABLED";
+    attribute GSR of FF_15 : label is "ENABLED";
+    attribute GSR of FF_14 : label is "ENABLED";
+    attribute GSR of FF_13 : label is "ENABLED";
+    attribute GSR of FF_12 : label is "ENABLED";
+    attribute GSR of FF_11 : label is "ENABLED";
+    attribute GSR of FF_10 : label is "ENABLED";
+    attribute GSR of FF_9 : label is "ENABLED";
+    attribute GSR of FF_8 : label is "ENABLED";
+    attribute GSR of FF_7 : label is "ENABLED";
+    attribute GSR of FF_6 : label is "ENABLED";
+    attribute GSR of FF_5 : label is "ENABLED";
+    attribute GSR of FF_4 : label is "ENABLED";
+    attribute GSR of FF_3 : label is "ENABLED";
+    attribute GSR of FF_2 : label is "ENABLED";
+    attribute GSR of FF_1 : label is "ENABLED";
+    attribute GSR of FF_0 : label is "ENABLED";
+    attribute syn_keep : boolean;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    AND2_t5: AND2
+        port map (A=>WrEn, B=>invout_2, Z=>wren_i);
+
+    INV_5: INV
+        port map (A=>full_i, Z=>invout_2);
+
+    AND2_t4: AND2
+        port map (A=>RdEn, B=>invout_1, Z=>rden_i);
+
+    INV_4: INV
+        port map (A=>empty_i, Z=>invout_1);
+
+    AND2_t3: AND2
+        port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
+
+    XOR2_t2: XOR2
+        port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
+
+    INV_3: INV
+        port map (A=>rden_i, Z=>rden_i_inv);
+
+    INV_2: INV
+        port map (A=>wren_i, Z=>wren_i_inv);
+
+    LUT4_1: ROM16X1A
+        generic map (initval=> X"3232")
+        port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, 
+            AD0=>empty_i, DO0=>empty_d);
+
+    LUT4_0: ROM16X1A
+        generic map (initval=> X"3232")
+        port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, 
+            AD0=>full_i, DO0=>full_d);
+
+    AND2_t1: AND2
+        port map (A=>rden_i, B=>invout_0, Z=>r_nw);
+
+    INV_1: INV
+        port map (A=>wren_i, Z=>invout_0);
+
+    XOR2_t0: XOR2
+        port map (A=>wcount_14, B=>rptr_14, Z=>wcnt_sub_msb);
+
+    INV_0: INV
+        port map (A=>cnt_con, Z=>cnt_con_inv);
+
+    pdp_ram_0_0_31: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), 
+            DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), 
+            DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, 
+            ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, 
+            ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, 
+            ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, 
+            CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, 
+            CSA2=>wptr_13, CSA1=>wptr_12, CSA0=>wptr_11, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, CSB2=>rptr_13, 
+            CSB1=>rptr_12, CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, 
+            DOA16=>open, DOA15=>open, DOA14=>open, DOA13=>open, 
+            DOA12=>open, DOA11=>open, DOA10=>open, DOA9=>open, 
+            DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open, DOA4=>open, 
+            DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open, DOB17=>open, 
+            DOB16=>open, DOB15=>open, DOB14=>open, DOB13=>open, 
+            DOB12=>open, DOB11=>open, DOB10=>open, DOB9=>open, 
+            DOB8=>mdout1_0_8, DOB7=>mdout1_0_7, DOB6=>mdout1_0_6, 
+            DOB5=>mdout1_0_5, DOB4=>mdout1_0_4, DOB3=>mdout1_0_3, 
+            DOB2=>mdout1_0_2, DOB1=>mdout1_0_1, DOB0=>mdout1_0_0);
+
+    pdp_ram_0_1_30: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), 
+            DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), 
+            DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, 
+            CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, 
+            ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, 
+            ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, 
+            ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_0_17, 
+            DOB7=>mdout1_0_16, DOB6=>mdout1_0_15, DOB5=>mdout1_0_14, 
+            DOB4=>mdout1_0_13, DOB3=>mdout1_0_12, DOB2=>mdout1_0_11, 
+            DOB1=>mdout1_0_10, DOB0=>mdout1_0_9);
+
+    pdp_ram_0_2_29: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), 
+            DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), 
+            DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, 
+            CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, 
+            ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, 
+            ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, 
+            ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_0_26, 
+            DOB7=>mdout1_0_25, DOB6=>mdout1_0_24, DOB5=>mdout1_0_23, 
+            DOB4=>mdout1_0_22, DOB3=>mdout1_0_21, DOB2=>mdout1_0_20, 
+            DOB1=>mdout1_0_19, DOB0=>mdout1_0_18);
+
+    pdp_ram_0_3_28: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), 
+            DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), 
+            DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, 
+            CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, 
+            ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, 
+            ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, 
+            ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_0_35, 
+            DOB7=>mdout1_0_34, DOB6=>mdout1_0_33, DOB5=>mdout1_0_32, 
+            DOB4=>mdout1_0_31, DOB3=>mdout1_0_30, DOB2=>mdout1_0_29, 
+            DOB1=>mdout1_0_28, DOB0=>mdout1_0_27);
+
+    pdp_ram_1_0_27: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), 
+            DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), 
+            DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, 
+            ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, 
+            ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, 
+            ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, 
+            CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, 
+            CSA2=>wptr_13, CSA1=>wptr_12, CSA0=>wptr_11, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, CSB2=>rptr_13, 
+            CSB1=>rptr_12, CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, 
+            DOA16=>open, DOA15=>open, DOA14=>open, DOA13=>open, 
+            DOA12=>open, DOA11=>open, DOA10=>open, DOA9=>open, 
+            DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open, DOA4=>open, 
+            DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open, DOB17=>open, 
+            DOB16=>open, DOB15=>open, DOB14=>open, DOB13=>open, 
+            DOB12=>open, DOB11=>open, DOB10=>open, DOB9=>open, 
+            DOB8=>mdout1_1_8, DOB7=>mdout1_1_7, DOB6=>mdout1_1_6, 
+            DOB5=>mdout1_1_5, DOB4=>mdout1_1_4, DOB3=>mdout1_1_3, 
+            DOB2=>mdout1_1_2, DOB1=>mdout1_1_1, DOB0=>mdout1_1_0);
+
+    pdp_ram_1_1_26: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), 
+            DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), 
+            DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, 
+            CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, 
+            ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, 
+            ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, 
+            ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_1_17, 
+            DOB7=>mdout1_1_16, DOB6=>mdout1_1_15, DOB5=>mdout1_1_14, 
+            DOB4=>mdout1_1_13, DOB3=>mdout1_1_12, DOB2=>mdout1_1_11, 
+            DOB1=>mdout1_1_10, DOB0=>mdout1_1_9);
+
+    pdp_ram_1_2_25: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), 
+            DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), 
+            DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, 
+            CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, 
+            ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, 
+            ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, 
+            ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_1_26, 
+            DOB7=>mdout1_1_25, DOB6=>mdout1_1_24, DOB5=>mdout1_1_23, 
+            DOB4=>mdout1_1_22, DOB3=>mdout1_1_21, DOB2=>mdout1_1_20, 
+            DOB1=>mdout1_1_19, DOB0=>mdout1_1_18);
+
+    pdp_ram_1_3_24: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), 
+            DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), 
+            DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, 
+            CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, 
+            ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, 
+            ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, 
+            ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_1_35, 
+            DOB7=>mdout1_1_34, DOB6=>mdout1_1_33, DOB5=>mdout1_1_32, 
+            DOB4=>mdout1_1_31, DOB3=>mdout1_1_30, DOB2=>mdout1_1_29, 
+            DOB1=>mdout1_1_28, DOB0=>mdout1_1_27);
+
+    pdp_ram_2_0_23: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), 
+            DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), 
+            DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, 
+            ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, 
+            ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, 
+            ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, 
+            CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, 
+            CSA2=>wptr_13, CSA1=>wptr_12, CSA0=>wptr_11, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, CSB2=>rptr_13, 
+            CSB1=>rptr_12, CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, 
+            DOA16=>open, DOA15=>open, DOA14=>open, DOA13=>open, 
+            DOA12=>open, DOA11=>open, DOA10=>open, DOA9=>open, 
+            DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open, DOA4=>open, 
+            DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open, DOB17=>open, 
+            DOB16=>open, DOB15=>open, DOB14=>open, DOB13=>open, 
+            DOB12=>open, DOB11=>open, DOB10=>open, DOB9=>open, 
+            DOB8=>mdout1_2_8, DOB7=>mdout1_2_7, DOB6=>mdout1_2_6, 
+            DOB5=>mdout1_2_5, DOB4=>mdout1_2_4, DOB3=>mdout1_2_3, 
+            DOB2=>mdout1_2_2, DOB1=>mdout1_2_1, DOB0=>mdout1_2_0);
+
+    pdp_ram_2_1_22: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), 
+            DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), 
+            DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, 
+            CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, 
+            ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, 
+            ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, 
+            ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_2_17, 
+            DOB7=>mdout1_2_16, DOB6=>mdout1_2_15, DOB5=>mdout1_2_14, 
+            DOB4=>mdout1_2_13, DOB3=>mdout1_2_12, DOB2=>mdout1_2_11, 
+            DOB1=>mdout1_2_10, DOB0=>mdout1_2_9);
+
+    pdp_ram_2_2_21: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), 
+            DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), 
+            DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, 
+            CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, 
+            ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, 
+            ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, 
+            ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_2_26, 
+            DOB7=>mdout1_2_25, DOB6=>mdout1_2_24, DOB5=>mdout1_2_23, 
+            DOB4=>mdout1_2_22, DOB3=>mdout1_2_21, DOB2=>mdout1_2_20, 
+            DOB1=>mdout1_2_19, DOB0=>mdout1_2_18);
+
+    pdp_ram_2_3_20: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), 
+            DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), 
+            DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, 
+            CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, 
+            ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, 
+            ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, 
+            ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_2_35, 
+            DOB7=>mdout1_2_34, DOB6=>mdout1_2_33, DOB5=>mdout1_2_32, 
+            DOB4=>mdout1_2_31, DOB3=>mdout1_2_30, DOB2=>mdout1_2_29, 
+            DOB1=>mdout1_2_28, DOB0=>mdout1_2_27);
+
+    pdp_ram_3_0_19: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), 
+            DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), 
+            DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, 
+            ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, 
+            ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, 
+            ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, 
+            CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, 
+            CSA2=>wptr_13, CSA1=>wptr_12, CSA0=>wptr_11, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, CSB2=>rptr_13, 
+            CSB1=>rptr_12, CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, 
+            DOA16=>open, DOA15=>open, DOA14=>open, DOA13=>open, 
+            DOA12=>open, DOA11=>open, DOA10=>open, DOA9=>open, 
+            DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open, DOA4=>open, 
+            DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open, DOB17=>open, 
+            DOB16=>open, DOB15=>open, DOB14=>open, DOB13=>open, 
+            DOB12=>open, DOB11=>open, DOB10=>open, DOB9=>open, 
+            DOB8=>mdout1_3_8, DOB7=>mdout1_3_7, DOB6=>mdout1_3_6, 
+            DOB5=>mdout1_3_5, DOB4=>mdout1_3_4, DOB3=>mdout1_3_3, 
+            DOB2=>mdout1_3_2, DOB1=>mdout1_3_1, DOB0=>mdout1_3_0);
+
+    pdp_ram_3_1_18: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), 
+            DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), 
+            DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, 
+            CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, 
+            ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, 
+            ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, 
+            ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_3_17, 
+            DOB7=>mdout1_3_16, DOB6=>mdout1_3_15, DOB5=>mdout1_3_14, 
+            DOB4=>mdout1_3_13, DOB3=>mdout1_3_12, DOB2=>mdout1_3_11, 
+            DOB1=>mdout1_3_10, DOB0=>mdout1_3_9);
+
+    pdp_ram_3_2_17: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), 
+            DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), 
+            DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, 
+            CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, 
+            ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, 
+            ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, 
+            ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_3_26, 
+            DOB7=>mdout1_3_25, DOB6=>mdout1_3_24, DOB5=>mdout1_3_23, 
+            DOB4=>mdout1_3_22, DOB3=>mdout1_3_21, DOB2=>mdout1_3_20, 
+            DOB1=>mdout1_3_19, DOB0=>mdout1_3_18);
+
+    pdp_ram_3_3_16: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), 
+            DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), 
+            DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, 
+            CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, 
+            ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, 
+            ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, 
+            ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_3_35, 
+            DOB7=>mdout1_3_34, DOB6=>mdout1_3_33, DOB5=>mdout1_3_32, 
+            DOB4=>mdout1_3_31, DOB3=>mdout1_3_30, DOB2=>mdout1_3_29, 
+            DOB1=>mdout1_3_28, DOB0=>mdout1_3_27);
+
+    pdp_ram_4_0_15: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b100", CSDECODE_A=> "0b100", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), 
+            DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), 
+            DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, 
+            ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, 
+            ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, 
+            ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, 
+            CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, 
+            CSA2=>wptr_13, CSA1=>wptr_12, CSA0=>wptr_11, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, CSB2=>rptr_13, 
+            CSB1=>rptr_12, CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, 
+            DOA16=>open, DOA15=>open, DOA14=>open, DOA13=>open, 
+            DOA12=>open, DOA11=>open, DOA10=>open, DOA9=>open, 
+            DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open, DOA4=>open, 
+            DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open, DOB17=>open, 
+            DOB16=>open, DOB15=>open, DOB14=>open, DOB13=>open, 
+            DOB12=>open, DOB11=>open, DOB10=>open, DOB9=>open, 
+            DOB8=>mdout1_4_8, DOB7=>mdout1_4_7, DOB6=>mdout1_4_6, 
+            DOB5=>mdout1_4_5, DOB4=>mdout1_4_4, DOB3=>mdout1_4_3, 
+            DOB2=>mdout1_4_2, DOB1=>mdout1_4_1, DOB0=>mdout1_4_0);
+
+    pdp_ram_4_1_14: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b100", CSDECODE_A=> "0b100", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), 
+            DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), 
+            DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, 
+            CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, 
+            ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, 
+            ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, 
+            ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_4_17, 
+            DOB7=>mdout1_4_16, DOB6=>mdout1_4_15, DOB5=>mdout1_4_14, 
+            DOB4=>mdout1_4_13, DOB3=>mdout1_4_12, DOB2=>mdout1_4_11, 
+            DOB1=>mdout1_4_10, DOB0=>mdout1_4_9);
+
+    pdp_ram_4_2_13: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b100", CSDECODE_A=> "0b100", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), 
+            DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), 
+            DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, 
+            CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, 
+            ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, 
+            ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, 
+            ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_4_26, 
+            DOB7=>mdout1_4_25, DOB6=>mdout1_4_24, DOB5=>mdout1_4_23, 
+            DOB4=>mdout1_4_22, DOB3=>mdout1_4_21, DOB2=>mdout1_4_20, 
+            DOB1=>mdout1_4_19, DOB0=>mdout1_4_18);
+
+    pdp_ram_4_3_12: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b100", CSDECODE_A=> "0b100", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), 
+            DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), 
+            DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, 
+            CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, 
+            ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, 
+            ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, 
+            ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_4_35, 
+            DOB7=>mdout1_4_34, DOB6=>mdout1_4_33, DOB5=>mdout1_4_32, 
+            DOB4=>mdout1_4_31, DOB3=>mdout1_4_30, DOB2=>mdout1_4_29, 
+            DOB1=>mdout1_4_28, DOB0=>mdout1_4_27);
+
+    pdp_ram_5_0_11: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b101", CSDECODE_A=> "0b101", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), 
+            DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), 
+            DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, 
+            ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, 
+            ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, 
+            ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, 
+            CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, 
+            CSA2=>wptr_13, CSA1=>wptr_12, CSA0=>wptr_11, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, CSB2=>rptr_13, 
+            CSB1=>rptr_12, CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, 
+            DOA16=>open, DOA15=>open, DOA14=>open, DOA13=>open, 
+            DOA12=>open, DOA11=>open, DOA10=>open, DOA9=>open, 
+            DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open, DOA4=>open, 
+            DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open, DOB17=>open, 
+            DOB16=>open, DOB15=>open, DOB14=>open, DOB13=>open, 
+            DOB12=>open, DOB11=>open, DOB10=>open, DOB9=>open, 
+            DOB8=>mdout1_5_8, DOB7=>mdout1_5_7, DOB6=>mdout1_5_6, 
+            DOB5=>mdout1_5_5, DOB4=>mdout1_5_4, DOB3=>mdout1_5_3, 
+            DOB2=>mdout1_5_2, DOB1=>mdout1_5_1, DOB0=>mdout1_5_0);
+
+    pdp_ram_5_1_10: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b101", CSDECODE_A=> "0b101", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), 
+            DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), 
+            DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, 
+            CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, 
+            ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, 
+            ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, 
+            ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_5_17, 
+            DOB7=>mdout1_5_16, DOB6=>mdout1_5_15, DOB5=>mdout1_5_14, 
+            DOB4=>mdout1_5_13, DOB3=>mdout1_5_12, DOB2=>mdout1_5_11, 
+            DOB1=>mdout1_5_10, DOB0=>mdout1_5_9);
+
+    pdp_ram_5_2_9: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b101", CSDECODE_A=> "0b101", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), 
+            DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), 
+            DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, 
+            CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, 
+            ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, 
+            ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, 
+            ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_5_26, 
+            DOB7=>mdout1_5_25, DOB6=>mdout1_5_24, DOB5=>mdout1_5_23, 
+            DOB4=>mdout1_5_22, DOB3=>mdout1_5_21, DOB2=>mdout1_5_20, 
+            DOB1=>mdout1_5_19, DOB0=>mdout1_5_18);
+
+    pdp_ram_5_3_8: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b101", CSDECODE_A=> "0b101", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), 
+            DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), 
+            DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, 
+            CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, 
+            ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, 
+            ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, 
+            ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_5_35, 
+            DOB7=>mdout1_5_34, DOB6=>mdout1_5_33, DOB5=>mdout1_5_32, 
+            DOB4=>mdout1_5_31, DOB3=>mdout1_5_30, DOB2=>mdout1_5_29, 
+            DOB1=>mdout1_5_28, DOB0=>mdout1_5_27);
+
+    pdp_ram_6_0_7: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b110", CSDECODE_A=> "0b110", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), 
+            DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), 
+            DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, 
+            ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, 
+            ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, 
+            ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, 
+            CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, 
+            CSA2=>wptr_13, CSA1=>wptr_12, CSA0=>wptr_11, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, CSB2=>rptr_13, 
+            CSB1=>rptr_12, CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, 
+            DOA16=>open, DOA15=>open, DOA14=>open, DOA13=>open, 
+            DOA12=>open, DOA11=>open, DOA10=>open, DOA9=>open, 
+            DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open, DOA4=>open, 
+            DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open, DOB17=>open, 
+            DOB16=>open, DOB15=>open, DOB14=>open, DOB13=>open, 
+            DOB12=>open, DOB11=>open, DOB10=>open, DOB9=>open, 
+            DOB8=>mdout1_6_8, DOB7=>mdout1_6_7, DOB6=>mdout1_6_6, 
+            DOB5=>mdout1_6_5, DOB4=>mdout1_6_4, DOB3=>mdout1_6_3, 
+            DOB2=>mdout1_6_2, DOB1=>mdout1_6_1, DOB0=>mdout1_6_0);
+
+    pdp_ram_6_1_6: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b110", CSDECODE_A=> "0b110", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), 
+            DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), 
+            DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, 
+            CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, 
+            ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, 
+            ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, 
+            ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_6_17, 
+            DOB7=>mdout1_6_16, DOB6=>mdout1_6_15, DOB5=>mdout1_6_14, 
+            DOB4=>mdout1_6_13, DOB3=>mdout1_6_12, DOB2=>mdout1_6_11, 
+            DOB1=>mdout1_6_10, DOB0=>mdout1_6_9);
+
+    pdp_ram_6_2_5: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b110", CSDECODE_A=> "0b110", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), 
+            DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), 
+            DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, 
+            CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, 
+            ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, 
+            ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, 
+            ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_6_26, 
+            DOB7=>mdout1_6_25, DOB6=>mdout1_6_24, DOB5=>mdout1_6_23, 
+            DOB4=>mdout1_6_22, DOB3=>mdout1_6_21, DOB2=>mdout1_6_20, 
+            DOB1=>mdout1_6_19, DOB0=>mdout1_6_18);
+
+    pdp_ram_6_3_4: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b110", CSDECODE_A=> "0b110", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), 
+            DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), 
+            DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, 
+            CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, 
+            ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, 
+            ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, 
+            ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_6_35, 
+            DOB7=>mdout1_6_34, DOB6=>mdout1_6_33, DOB5=>mdout1_6_32, 
+            DOB4=>mdout1_6_31, DOB3=>mdout1_6_30, DOB2=>mdout1_6_29, 
+            DOB1=>mdout1_6_28, DOB0=>mdout1_6_27);
+
+    pdp_ram_7_0_3: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b111", CSDECODE_A=> "0b111", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), 
+            DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), 
+            DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, 
+            ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, 
+            ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, 
+            ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, 
+            CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, 
+            CSA2=>wptr_13, CSA1=>wptr_12, CSA0=>wptr_11, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, CSB2=>rptr_13, 
+            CSB1=>rptr_12, CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, 
+            DOA16=>open, DOA15=>open, DOA14=>open, DOA13=>open, 
+            DOA12=>open, DOA11=>open, DOA10=>open, DOA9=>open, 
+            DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open, DOA4=>open, 
+            DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open, DOB17=>open, 
+            DOB16=>open, DOB15=>open, DOB14=>open, DOB13=>open, 
+            DOB12=>open, DOB11=>open, DOB10=>open, DOB9=>open, 
+            DOB8=>mdout1_7_8, DOB7=>mdout1_7_7, DOB6=>mdout1_7_6, 
+            DOB5=>mdout1_7_5, DOB4=>mdout1_7_4, DOB3=>mdout1_7_3, 
+            DOB2=>mdout1_7_2, DOB1=>mdout1_7_1, DOB0=>mdout1_7_0);
+
+    pdp_ram_7_1_2: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b111", CSDECODE_A=> "0b111", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), 
+            DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), 
+            DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, 
+            CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, 
+            ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, 
+            ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, 
+            ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_7_17, 
+            DOB7=>mdout1_7_16, DOB6=>mdout1_7_15, DOB5=>mdout1_7_14, 
+            DOB4=>mdout1_7_13, DOB3=>mdout1_7_12, DOB2=>mdout1_7_11, 
+            DOB1=>mdout1_7_10, DOB0=>mdout1_7_9);
+
+    pdp_ram_7_2_1: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b111", CSDECODE_A=> "0b111", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), 
+            DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), 
+            DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, 
+            CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, 
+            ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, 
+            ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, 
+            ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_7_26, 
+            DOB7=>mdout1_7_25, DOB6=>mdout1_7_24, DOB5=>mdout1_7_23, 
+            DOB4=>mdout1_7_22, DOB3=>mdout1_7_21, DOB2=>mdout1_7_20, 
+            DOB1=>mdout1_7_19, DOB0=>mdout1_7_18);
+
+    pdp_ram_7_3_0: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b111", CSDECODE_A=> "0b111", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), 
+            DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), 
+            DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, 
+            CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, 
+            ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, 
+            ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, 
+            ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_7_35, 
+            DOB7=>mdout1_7_34, DOB6=>mdout1_7_33, DOB5=>mdout1_7_32, 
+            DOB4=>mdout1_7_31, DOB3=>mdout1_7_30, DOB2=>mdout1_7_29, 
+            DOB1=>mdout1_7_28, DOB0=>mdout1_7_27);
+
+    FF_98: FD1P3DX
+        port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_0);
+
+    FF_97: FD1P3DX
+        port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_1);
+
+    FF_96: FD1P3DX
+        port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_2);
+
+    FF_95: FD1P3DX
+        port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_3);
+
+    FF_94: FD1P3DX
+        port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_4);
+
+    FF_93: FD1P3DX
+        port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_5);
+
+    FF_92: FD1P3DX
+        port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_6);
+
+    FF_91: FD1P3DX
+        port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_7);
+
+    FF_90: FD1P3DX
+        port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_8);
+
+    FF_89: FD1P3DX
+        port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_9);
+
+    FF_88: FD1P3DX
+        port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_10);
+
+    FF_87: FD1P3DX
+        port map (D=>ifcount_11, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_11);
+
+    FF_86: FD1P3DX
+        port map (D=>ifcount_12, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_12);
+
+    FF_85: FD1P3DX
+        port map (D=>ifcount_13, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_13);
+
+    FF_84: FD1P3DX
+        port map (D=>ifcount_14, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_14);
+
+    FF_83: FD1S3BX
+        port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
+
+    FF_82: FD1S3DX
+        port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
+
+    FF_81: FD1P3BX
+        port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset, 
+            Q=>wcount_0);
+
+    FF_80: FD1P3DX
+        port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_1);
+
+    FF_79: FD1P3DX
+        port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_2);
+
+    FF_78: FD1P3DX
+        port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_3);
+
+    FF_77: FD1P3DX
+        port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_4);
+
+    FF_76: FD1P3DX
+        port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_5);
+
+    FF_75: FD1P3DX
+        port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_6);
+
+    FF_74: FD1P3DX
+        port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_7);
+
+    FF_73: FD1P3DX
+        port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_8);
+
+    FF_72: FD1P3DX
+        port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_9);
+
+    FF_71: FD1P3DX
+        port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_10);
+
+    FF_70: FD1P3DX
+        port map (D=>iwcount_11, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_11);
+
+    FF_69: FD1P3DX
+        port map (D=>iwcount_12, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_12);
+
+    FF_68: FD1P3DX
+        port map (D=>iwcount_13, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_13);
+
+    FF_67: FD1P3DX
+        port map (D=>iwcount_14, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_14);
+
+    FF_66: FD1P3BX
+        port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset, 
+            Q=>rcount_0);
+
+    FF_65: FD1P3DX
+        port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_1);
+
+    FF_64: FD1P3DX
+        port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_2);
+
+    FF_63: FD1P3DX
+        port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_3);
+
+    FF_62: FD1P3DX
+        port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_4);
+
+    FF_61: FD1P3DX
+        port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_5);
+
+    FF_60: FD1P3DX
+        port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_6);
+
+    FF_59: FD1P3DX
+        port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_7);
+
+    FF_58: FD1P3DX
+        port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_8);
+
+    FF_57: FD1P3DX
+        port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_9);
+
+    FF_56: FD1P3DX
+        port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_10);
+
+    FF_55: FD1P3DX
+        port map (D=>ircount_11, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_11);
+
+    FF_54: FD1P3DX
+        port map (D=>ircount_12, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_12);
+
+    FF_53: FD1P3DX
+        port map (D=>ircount_13, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_13);
+
+    FF_52: FD1P3DX
+        port map (D=>ircount_14, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_14);
+
+    FF_51: FD1P3DX
+        port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_0);
+
+    FF_50: FD1P3DX
+        port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_1);
+
+    FF_49: FD1P3DX
+        port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_2);
+
+    FF_48: FD1P3DX
+        port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_3);
+
+    FF_47: FD1P3DX
+        port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_4);
+
+    FF_46: FD1P3DX
+        port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_5);
+
+    FF_45: FD1P3DX
+        port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_6);
+
+    FF_44: FD1P3DX
+        port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_7);
+
+    FF_43: FD1P3DX
+        port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_8);
+
+    FF_42: FD1P3DX
+        port map (D=>wcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_9);
+
+    FF_41: FD1P3DX
+        port map (D=>wcount_10, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_10);
+
+    FF_40: FD1P3DX
+        port map (D=>wcount_11, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_11);
+
+    FF_39: FD1P3DX
+        port map (D=>wcount_12, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_12);
+
+    FF_38: FD1P3DX
+        port map (D=>wcount_13, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_13);
+
+    FF_37: FD1P3DX
+        port map (D=>wcount_14, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_14);
+
+    FF_36: FD1P3DX
+        port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_0);
+
+    FF_35: FD1P3DX
+        port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_1);
+
+    FF_34: FD1P3DX
+        port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_2);
+
+    FF_33: FD1P3DX
+        port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_3);
+
+    FF_32: FD1P3DX
+        port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_4);
+
+    FF_31: FD1P3DX
+        port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_5);
+
+    FF_30: FD1P3DX
+        port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_6);
+
+    FF_29: FD1P3DX
+        port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_7);
+
+    FF_28: FD1P3DX
+        port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_8);
+
+    FF_27: FD1P3DX
+        port map (D=>rcount_9, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_9);
+
+    FF_26: FD1P3DX
+        port map (D=>rcount_10, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_10);
+
+    FF_25: FD1P3DX
+        port map (D=>rcount_11, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_11);
+
+    FF_24: FD1P3DX
+        port map (D=>rcount_12, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_12);
+
+    FF_23: FD1P3DX
+        port map (D=>rcount_13, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_13);
+
+    FF_22: FD1P3DX
+        port map (D=>rcount_14, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_14);
+
+    FF_21: FD1P3DX
+        port map (D=>rptr_11, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, 
+            Q=>rptr_11_ff);
+
+    FF_20: FD1P3DX
+        port map (D=>rptr_12, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, 
+            Q=>rptr_12_ff);
+
+    FF_19: FD1P3DX
+        port map (D=>rptr_13, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, 
+            Q=>rptr_13_ff);
+
+    FF_18: FD1P3DX
+        port map (D=>rptr_11_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, 
+            Q=>rptr_11_ff2);
+
+    FF_17: FD1P3DX
+        port map (D=>rptr_12_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, 
+            Q=>rptr_12_ff2);
+
+    FF_16: FD1P3DX
+        port map (D=>rptr_13_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, 
+            Q=>rptr_13_ff2);
+
+    FF_15: FD1S3DX
+        port map (D=>wcnt_sub_0, CK=>Clock, CD=>Reset, Q=>wcnt_reg_0);
+
+    FF_14: FD1S3DX
+        port map (D=>wcnt_sub_1, CK=>Clock, CD=>Reset, Q=>wcnt_reg_1);
+
+    FF_13: FD1S3DX
+        port map (D=>wcnt_sub_2, CK=>Clock, CD=>Reset, Q=>wcnt_reg_2);
+
+    FF_12: FD1S3DX
+        port map (D=>wcnt_sub_3, CK=>Clock, CD=>Reset, Q=>wcnt_reg_3);
+
+    FF_11: FD1S3DX
+        port map (D=>wcnt_sub_4, CK=>Clock, CD=>Reset, Q=>wcnt_reg_4);
+
+    FF_10: FD1S3DX
+        port map (D=>wcnt_sub_5, CK=>Clock, CD=>Reset, Q=>wcnt_reg_5);
+
+    FF_9: FD1S3DX
+        port map (D=>wcnt_sub_6, CK=>Clock, CD=>Reset, Q=>wcnt_reg_6);
+
+    FF_8: FD1S3DX
+        port map (D=>wcnt_sub_7, CK=>Clock, CD=>Reset, Q=>wcnt_reg_7);
+
+    FF_7: FD1S3DX
+        port map (D=>wcnt_sub_8, CK=>Clock, CD=>Reset, Q=>wcnt_reg_8);
+
+    FF_6: FD1S3DX
+        port map (D=>wcnt_sub_9, CK=>Clock, CD=>Reset, Q=>wcnt_reg_9);
+
+    FF_5: FD1S3DX
+        port map (D=>wcnt_sub_10, CK=>Clock, CD=>Reset, Q=>wcnt_reg_10);
+
+    FF_4: FD1S3DX
+        port map (D=>wcnt_sub_11, CK=>Clock, CD=>Reset, Q=>wcnt_reg_11);
+
+    FF_3: FD1S3DX
+        port map (D=>wcnt_sub_12, CK=>Clock, CD=>Reset, Q=>wcnt_reg_12);
+
+    FF_2: FD1S3DX
+        port map (D=>wcnt_sub_13, CK=>Clock, CD=>Reset, Q=>wcnt_reg_13);
+
+    FF_1: FD1S3DX
+        port map (D=>wcnt_sub_14, CK=>Clock, CD=>Reset, Q=>wcnt_reg_14);
+
+    FF_0: FD1S3DX
+        port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull);
+
+    bdcnt_bctr_cia: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>'X', S0=>open, S1=>open, COUT=>bdcnt_bctr_ci);
+
+    bdcnt_bctr_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_0, A1=>fcount_1, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>bdcnt_bctr_ci, S0=>ifcount_0, S1=>ifcount_1, COUT=>co0);
+
+    bdcnt_bctr_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co0, S0=>ifcount_2, S1=>ifcount_3, COUT=>co1);
+
+    bdcnt_bctr_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_4, A1=>fcount_5, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co1, S0=>ifcount_4, S1=>ifcount_5, COUT=>co2);
+
+    bdcnt_bctr_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_6, A1=>fcount_7, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co2, S0=>ifcount_6, S1=>ifcount_7, COUT=>co3);
+
+    bdcnt_bctr_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_8, A1=>fcount_9, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co3, S0=>ifcount_8, S1=>ifcount_9, COUT=>co4);
+
+    bdcnt_bctr_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_10, A1=>fcount_11, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co4, S0=>ifcount_10, S1=>ifcount_11, COUT=>co5);
+
+    bdcnt_bctr_6: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_12, A1=>fcount_13, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co5, S0=>ifcount_12, S1=>ifcount_13, COUT=>co6);
+
+    bdcnt_bctr_7: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_14, A1=>scuba_vlo, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co6, S0=>ifcount_14, S1=>open, COUT=>co7);
+
+    e_cmp_ci_a: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci);
+
+    e_cmp_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>rden_i, A1=>scuba_vlo, B0=>fcount_0, B1=>fcount_1, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>cmp_ci, S0=>open, S1=>open, COUT=>co0_1);
+
+    e_cmp_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_2, 
+            B1=>fcount_3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co0_1, S0=>open, S1=>open, COUT=>co1_1);
+
+    e_cmp_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_4, 
+            B1=>fcount_5, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co1_1, S0=>open, S1=>open, COUT=>co2_1);
+
+    e_cmp_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_6, 
+            B1=>fcount_7, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co2_1, S0=>open, S1=>open, COUT=>co3_1);
+
+    e_cmp_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_8, 
+            B1=>fcount_9, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co3_1, S0=>open, S1=>open, COUT=>co4_1);
+
+    e_cmp_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_10, 
+            B1=>fcount_11, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co4_1, S0=>open, S1=>open, COUT=>co5_1);
+
+    e_cmp_6: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_12, 
+            B1=>fcount_13, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co5_1, S0=>open, S1=>open, COUT=>co6_1);
+
+    e_cmp_7: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_14, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co6_1, S0=>open, S1=>open, 
+            COUT=>cmp_le_1_c);
+
+    a0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>cmp_le_1_c, S0=>cmp_le_1, S1=>open, 
+            COUT=>open);
+
+    g_cmp_ci_a: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_1);
+
+    g_cmp_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>cmp_ci_1, S0=>open, S1=>open, COUT=>co0_2);
+
+    g_cmp_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co0_2, S0=>open, S1=>open, COUT=>co1_2);
+
+    g_cmp_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co1_2, S0=>open, S1=>open, COUT=>co2_2);
+
+    g_cmp_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co2_2, S0=>open, S1=>open, COUT=>co3_2);
+
+    g_cmp_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co3_2, S0=>open, S1=>open, COUT=>co4_2);
+
+    g_cmp_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_10, A1=>fcount_11, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co4_2, S0=>open, S1=>open, COUT=>co5_2);
+
+    g_cmp_6: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_12, A1=>fcount_13, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co5_2, S0=>open, S1=>open, COUT=>co6_2);
+
+    g_cmp_7: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_14, A1=>scuba_vlo, B0=>wren_i_inv, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co6_2, S0=>open, S1=>open, 
+            COUT=>cmp_ge_d1_c);
+
+    a1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>cmp_ge_d1_c, S0=>cmp_ge_d1, S1=>open, 
+            COUT=>open);
+
+    w_ctr_cia: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>w_ctr_ci);
+
+    w_ctr_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>w_ctr_ci, S0=>iwcount_0, S1=>iwcount_1, 
+            COUT=>co0_3);
+
+    w_ctr_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_2, A1=>wcount_3, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co0_3, S0=>iwcount_2, S1=>iwcount_3, 
+            COUT=>co1_3);
+
+    w_ctr_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_4, A1=>wcount_5, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co1_3, S0=>iwcount_4, S1=>iwcount_5, 
+            COUT=>co2_3);
+
+    w_ctr_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_6, A1=>wcount_7, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co2_3, S0=>iwcount_6, S1=>iwcount_7, 
+            COUT=>co3_3);
+
+    w_ctr_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_8, A1=>wcount_9, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co3_3, S0=>iwcount_8, S1=>iwcount_9, 
+            COUT=>co4_3);
+
+    w_ctr_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_10, A1=>wcount_11, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co4_3, S0=>iwcount_10, S1=>iwcount_11, 
+            COUT=>co5_3);
+
+    w_ctr_6: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_12, A1=>wcount_13, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co5_3, S0=>iwcount_12, S1=>iwcount_13, 
+            COUT=>co6_3);
+
+    w_ctr_7: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_14, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co6_3, S0=>iwcount_14, S1=>open, 
+            COUT=>co7_1);
+
+    r_ctr_cia: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>r_ctr_ci);
+
+    r_ctr_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>r_ctr_ci, S0=>ircount_0, S1=>ircount_1, 
+            COUT=>co0_4);
+
+    r_ctr_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_2, A1=>rcount_3, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co0_4, S0=>ircount_2, S1=>ircount_3, 
+            COUT=>co1_4);
+
+    r_ctr_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_4, A1=>rcount_5, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co1_4, S0=>ircount_4, S1=>ircount_5, 
+            COUT=>co2_4);
+
+    r_ctr_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_6, A1=>rcount_7, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co2_4, S0=>ircount_6, S1=>ircount_7, 
+            COUT=>co3_4);
+
+    r_ctr_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_8, A1=>rcount_9, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co3_4, S0=>ircount_8, S1=>ircount_9, 
+            COUT=>co4_4);
+
+    r_ctr_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_10, A1=>rcount_11, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co4_4, S0=>ircount_10, S1=>ircount_11, 
+            COUT=>co5_4);
+
+    r_ctr_6: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_12, A1=>rcount_13, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co5_4, S0=>ircount_12, S1=>ircount_13, 
+            COUT=>co6_4);
+
+    r_ctr_7: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_14, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co6_4, S0=>ircount_14, S1=>open, 
+            COUT=>co7_2);
+
+    mux_35: MUX81
+        port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0, 
+            D3=>mdout1_3_0, D4=>mdout1_4_0, D5=>mdout1_5_0, 
+            D6=>mdout1_6_0, D7=>mdout1_7_0, SD1=>rptr_11_ff2, 
+            SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(0));
+
+    mux_34: MUX81
+        port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1, 
+            D3=>mdout1_3_1, D4=>mdout1_4_1, D5=>mdout1_5_1, 
+            D6=>mdout1_6_1, D7=>mdout1_7_1, SD1=>rptr_11_ff2, 
+            SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(1));
+
+    mux_33: MUX81
+        port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2, 
+            D3=>mdout1_3_2, D4=>mdout1_4_2, D5=>mdout1_5_2, 
+            D6=>mdout1_6_2, D7=>mdout1_7_2, SD1=>rptr_11_ff2, 
+            SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(2));
+
+    mux_32: MUX81
+        port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3, 
+            D3=>mdout1_3_3, D4=>mdout1_4_3, D5=>mdout1_5_3, 
+            D6=>mdout1_6_3, D7=>mdout1_7_3, SD1=>rptr_11_ff2, 
+            SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(3));
+
+    mux_31: MUX81
+        port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4, 
+            D3=>mdout1_3_4, D4=>mdout1_4_4, D5=>mdout1_5_4, 
+            D6=>mdout1_6_4, D7=>mdout1_7_4, SD1=>rptr_11_ff2, 
+            SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(4));
+
+    mux_30: MUX81
+        port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5, 
+            D3=>mdout1_3_5, D4=>mdout1_4_5, D5=>mdout1_5_5, 
+            D6=>mdout1_6_5, D7=>mdout1_7_5, SD1=>rptr_11_ff2, 
+            SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(5));
+
+    mux_29: MUX81
+        port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6, 
+            D3=>mdout1_3_6, D4=>mdout1_4_6, D5=>mdout1_5_6, 
+            D6=>mdout1_6_6, D7=>mdout1_7_6, SD1=>rptr_11_ff2, 
+            SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(6));
+
+    mux_28: MUX81
+        port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7, 
+            D3=>mdout1_3_7, D4=>mdout1_4_7, D5=>mdout1_5_7, 
+            D6=>mdout1_6_7, D7=>mdout1_7_7, SD1=>rptr_11_ff2, 
+            SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(7));
+
+    mux_27: MUX81
+        port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8, 
+            D3=>mdout1_3_8, D4=>mdout1_4_8, D5=>mdout1_5_8, 
+            D6=>mdout1_6_8, D7=>mdout1_7_8, SD1=>rptr_11_ff2, 
+            SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(8));
+
+    mux_26: MUX81
+        port map (D0=>mdout1_0_9, D1=>mdout1_1_9, D2=>mdout1_2_9, 
+            D3=>mdout1_3_9, D4=>mdout1_4_9, D5=>mdout1_5_9, 
+            D6=>mdout1_6_9, D7=>mdout1_7_9, SD1=>rptr_11_ff2, 
+            SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(9));
+
+    mux_25: MUX81
+        port map (D0=>mdout1_0_10, D1=>mdout1_1_10, D2=>mdout1_2_10, 
+            D3=>mdout1_3_10, D4=>mdout1_4_10, D5=>mdout1_5_10, 
+            D6=>mdout1_6_10, D7=>mdout1_7_10, SD1=>rptr_11_ff2, 
+            SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(10));
+
+    mux_24: MUX81
+        port map (D0=>mdout1_0_11, D1=>mdout1_1_11, D2=>mdout1_2_11, 
+            D3=>mdout1_3_11, D4=>mdout1_4_11, D5=>mdout1_5_11, 
+            D6=>mdout1_6_11, D7=>mdout1_7_11, SD1=>rptr_11_ff2, 
+            SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(11));
+
+    mux_23: MUX81
+        port map (D0=>mdout1_0_12, D1=>mdout1_1_12, D2=>mdout1_2_12, 
+            D3=>mdout1_3_12, D4=>mdout1_4_12, D5=>mdout1_5_12, 
+            D6=>mdout1_6_12, D7=>mdout1_7_12, SD1=>rptr_11_ff2, 
+            SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(12));
+
+    mux_22: MUX81
+        port map (D0=>mdout1_0_13, D1=>mdout1_1_13, D2=>mdout1_2_13, 
+            D3=>mdout1_3_13, D4=>mdout1_4_13, D5=>mdout1_5_13, 
+            D6=>mdout1_6_13, D7=>mdout1_7_13, SD1=>rptr_11_ff2, 
+            SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(13));
+
+    mux_21: MUX81
+        port map (D0=>mdout1_0_14, D1=>mdout1_1_14, D2=>mdout1_2_14, 
+            D3=>mdout1_3_14, D4=>mdout1_4_14, D5=>mdout1_5_14, 
+            D6=>mdout1_6_14, D7=>mdout1_7_14, SD1=>rptr_11_ff2, 
+            SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(14));
+
+    mux_20: MUX81
+        port map (D0=>mdout1_0_15, D1=>mdout1_1_15, D2=>mdout1_2_15, 
+            D3=>mdout1_3_15, D4=>mdout1_4_15, D5=>mdout1_5_15, 
+            D6=>mdout1_6_15, D7=>mdout1_7_15, SD1=>rptr_11_ff2, 
+            SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(15));
+
+    mux_19: MUX81
+        port map (D0=>mdout1_0_16, D1=>mdout1_1_16, D2=>mdout1_2_16, 
+            D3=>mdout1_3_16, D4=>mdout1_4_16, D5=>mdout1_5_16, 
+            D6=>mdout1_6_16, D7=>mdout1_7_16, SD1=>rptr_11_ff2, 
+            SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(16));
+
+    mux_18: MUX81
+        port map (D0=>mdout1_0_17, D1=>mdout1_1_17, D2=>mdout1_2_17, 
+            D3=>mdout1_3_17, D4=>mdout1_4_17, D5=>mdout1_5_17, 
+            D6=>mdout1_6_17, D7=>mdout1_7_17, SD1=>rptr_11_ff2, 
+            SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(17));
+
+    mux_17: MUX81
+        port map (D0=>mdout1_0_18, D1=>mdout1_1_18, D2=>mdout1_2_18, 
+            D3=>mdout1_3_18, D4=>mdout1_4_18, D5=>mdout1_5_18, 
+            D6=>mdout1_6_18, D7=>mdout1_7_18, SD1=>rptr_11_ff2, 
+            SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(18));
+
+    mux_16: MUX81
+        port map (D0=>mdout1_0_19, D1=>mdout1_1_19, D2=>mdout1_2_19, 
+            D3=>mdout1_3_19, D4=>mdout1_4_19, D5=>mdout1_5_19, 
+            D6=>mdout1_6_19, D7=>mdout1_7_19, SD1=>rptr_11_ff2, 
+            SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(19));
+
+    mux_15: MUX81
+        port map (D0=>mdout1_0_20, D1=>mdout1_1_20, D2=>mdout1_2_20, 
+            D3=>mdout1_3_20, D4=>mdout1_4_20, D5=>mdout1_5_20, 
+            D6=>mdout1_6_20, D7=>mdout1_7_20, SD1=>rptr_11_ff2, 
+            SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(20));
+
+    mux_14: MUX81
+        port map (D0=>mdout1_0_21, D1=>mdout1_1_21, D2=>mdout1_2_21, 
+            D3=>mdout1_3_21, D4=>mdout1_4_21, D5=>mdout1_5_21, 
+            D6=>mdout1_6_21, D7=>mdout1_7_21, SD1=>rptr_11_ff2, 
+            SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(21));
+
+    mux_13: MUX81
+        port map (D0=>mdout1_0_22, D1=>mdout1_1_22, D2=>mdout1_2_22, 
+            D3=>mdout1_3_22, D4=>mdout1_4_22, D5=>mdout1_5_22, 
+            D6=>mdout1_6_22, D7=>mdout1_7_22, SD1=>rptr_11_ff2, 
+            SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(22));
+
+    mux_12: MUX81
+        port map (D0=>mdout1_0_23, D1=>mdout1_1_23, D2=>mdout1_2_23, 
+            D3=>mdout1_3_23, D4=>mdout1_4_23, D5=>mdout1_5_23, 
+            D6=>mdout1_6_23, D7=>mdout1_7_23, SD1=>rptr_11_ff2, 
+            SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(23));
+
+    mux_11: MUX81
+        port map (D0=>mdout1_0_24, D1=>mdout1_1_24, D2=>mdout1_2_24, 
+            D3=>mdout1_3_24, D4=>mdout1_4_24, D5=>mdout1_5_24, 
+            D6=>mdout1_6_24, D7=>mdout1_7_24, SD1=>rptr_11_ff2, 
+            SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(24));
+
+    mux_10: MUX81
+        port map (D0=>mdout1_0_25, D1=>mdout1_1_25, D2=>mdout1_2_25, 
+            D3=>mdout1_3_25, D4=>mdout1_4_25, D5=>mdout1_5_25, 
+            D6=>mdout1_6_25, D7=>mdout1_7_25, SD1=>rptr_11_ff2, 
+            SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(25));
+
+    mux_9: MUX81
+        port map (D0=>mdout1_0_26, D1=>mdout1_1_26, D2=>mdout1_2_26, 
+            D3=>mdout1_3_26, D4=>mdout1_4_26, D5=>mdout1_5_26, 
+            D6=>mdout1_6_26, D7=>mdout1_7_26, SD1=>rptr_11_ff2, 
+            SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(26));
+
+    mux_8: MUX81
+        port map (D0=>mdout1_0_27, D1=>mdout1_1_27, D2=>mdout1_2_27, 
+            D3=>mdout1_3_27, D4=>mdout1_4_27, D5=>mdout1_5_27, 
+            D6=>mdout1_6_27, D7=>mdout1_7_27, SD1=>rptr_11_ff2, 
+            SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(27));
+
+    mux_7: MUX81
+        port map (D0=>mdout1_0_28, D1=>mdout1_1_28, D2=>mdout1_2_28, 
+            D3=>mdout1_3_28, D4=>mdout1_4_28, D5=>mdout1_5_28, 
+            D6=>mdout1_6_28, D7=>mdout1_7_28, SD1=>rptr_11_ff2, 
+            SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(28));
+
+    mux_6: MUX81
+        port map (D0=>mdout1_0_29, D1=>mdout1_1_29, D2=>mdout1_2_29, 
+            D3=>mdout1_3_29, D4=>mdout1_4_29, D5=>mdout1_5_29, 
+            D6=>mdout1_6_29, D7=>mdout1_7_29, SD1=>rptr_11_ff2, 
+            SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(29));
+
+    mux_5: MUX81
+        port map (D0=>mdout1_0_30, D1=>mdout1_1_30, D2=>mdout1_2_30, 
+            D3=>mdout1_3_30, D4=>mdout1_4_30, D5=>mdout1_5_30, 
+            D6=>mdout1_6_30, D7=>mdout1_7_30, SD1=>rptr_11_ff2, 
+            SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(30));
+
+    mux_4: MUX81
+        port map (D0=>mdout1_0_31, D1=>mdout1_1_31, D2=>mdout1_2_31, 
+            D3=>mdout1_3_31, D4=>mdout1_4_31, D5=>mdout1_5_31, 
+            D6=>mdout1_6_31, D7=>mdout1_7_31, SD1=>rptr_11_ff2, 
+            SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(31));
+
+    mux_3: MUX81
+        port map (D0=>mdout1_0_32, D1=>mdout1_1_32, D2=>mdout1_2_32, 
+            D3=>mdout1_3_32, D4=>mdout1_4_32, D5=>mdout1_5_32, 
+            D6=>mdout1_6_32, D7=>mdout1_7_32, SD1=>rptr_11_ff2, 
+            SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(32));
+
+    mux_2: MUX81
+        port map (D0=>mdout1_0_33, D1=>mdout1_1_33, D2=>mdout1_2_33, 
+            D3=>mdout1_3_33, D4=>mdout1_4_33, D5=>mdout1_5_33, 
+            D6=>mdout1_6_33, D7=>mdout1_7_33, SD1=>rptr_11_ff2, 
+            SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(33));
+
+    mux_1: MUX81
+        port map (D0=>mdout1_0_34, D1=>mdout1_1_34, D2=>mdout1_2_34, 
+            D3=>mdout1_3_34, D4=>mdout1_4_34, D5=>mdout1_5_34, 
+            D6=>mdout1_6_34, D7=>mdout1_7_34, SD1=>rptr_11_ff2, 
+            SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(34));
+
+    mux_0: MUX81
+        port map (D0=>mdout1_0_35, D1=>mdout1_1_35, D2=>mdout1_2_35, 
+            D3=>mdout1_3_35, D4=>mdout1_4_35, D5=>mdout1_5_35, 
+            D6=>mdout1_6_35, D7=>mdout1_7_35, SD1=>rptr_11_ff2, 
+            SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(35));
+
+    precin_inst636: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"0000", 
+        INIT0=> X"0000")
+        port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>precin);
+
+    wcnt_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>cnt_con, A1=>wcount_0, B0=>cnt_con_inv, B1=>rptr_0, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>precin, S0=>open, S1=>wcnt_sub_0, COUT=>co0_5);
+
+    wcnt_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_1, A1=>wcount_2, B0=>rptr_1, B1=>rptr_2, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co0_5, S0=>wcnt_sub_1, S1=>wcnt_sub_2, COUT=>co1_5);
+
+    wcnt_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_3, A1=>wcount_4, B0=>rptr_3, B1=>rptr_4, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co1_5, S0=>wcnt_sub_3, S1=>wcnt_sub_4, COUT=>co2_5);
+
+    wcnt_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_5, A1=>wcount_6, B0=>rptr_5, B1=>rptr_6, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co2_5, S0=>wcnt_sub_5, S1=>wcnt_sub_6, COUT=>co3_5);
+
+    wcnt_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_7, A1=>wcount_8, B0=>rptr_7, B1=>rptr_8, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co3_5, S0=>wcnt_sub_7, S1=>wcnt_sub_8, COUT=>co4_5);
+
+    wcnt_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_9, A1=>wcount_10, B0=>rptr_9, B1=>rptr_10, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co4_5, S0=>wcnt_sub_9, S1=>wcnt_sub_10, COUT=>co5_5);
+
+    wcnt_6: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_11, A1=>wcount_12, B0=>rptr_11, B1=>rptr_12, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co5_5, S0=>wcnt_sub_11, S1=>wcnt_sub_12, COUT=>co6_5);
+
+    wcnt_7: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_13, A1=>wcnt_sub_msb, B0=>rptr_13, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co6_5, S0=>wcnt_sub_13, S1=>wcnt_sub_14, 
+            COUT=>co7_3);
+
+    wcntd: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co7_3, S0=>co7_3d, S1=>open, COUT=>open);
+
+    af_set_cmp_ci_a: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_2);
+
+    af_set_cmp_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0), 
+            B1=>AmFullThresh(1), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>cmp_ci_2, S0=>open, 
+            S1=>open, COUT=>co0_6);
+
+    af_set_cmp_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2), 
+            B1=>AmFullThresh(3), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co0_6, S0=>open, S1=>open, 
+            COUT=>co1_6);
+
+    af_set_cmp_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4), 
+            B1=>AmFullThresh(5), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co1_6, S0=>open, S1=>open, 
+            COUT=>co2_6);
+
+    af_set_cmp_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6), 
+            B1=>AmFullThresh(7), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co2_6, S0=>open, S1=>open, 
+            COUT=>co3_6);
+
+    af_set_cmp_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8), 
+            B1=>AmFullThresh(9), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co3_6, S0=>open, S1=>open, 
+            COUT=>co4_6);
+
+    af_set_cmp_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_10, A1=>wcnt_reg_11, B0=>AmFullThresh(10), 
+            B1=>AmFullThresh(11), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co4_6, S0=>open, S1=>open, 
+            COUT=>co5_6);
+
+    af_set_cmp_6: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_12, A1=>wcnt_reg_13, B0=>AmFullThresh(12), 
+            B1=>AmFullThresh(13), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co5_6, S0=>open, S1=>open, 
+            COUT=>co6_6);
+
+    af_set_cmp_7: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_14, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co6_6, S0=>open, S1=>open, 
+            COUT=>af_set_c);
+
+    scuba_vhi_inst: VHI
+        port map (Z=>scuba_vhi);
+
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    a2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>af_set_c, S0=>af_set, S1=>open, 
+            COUT=>open);
+
+    WCNT(0) <= fcount_0;
+    WCNT(1) <= fcount_1;
+    WCNT(2) <= fcount_2;
+    WCNT(3) <= fcount_3;
+    WCNT(4) <= fcount_4;
+    WCNT(5) <= fcount_5;
+    WCNT(6) <= fcount_6;
+    WCNT(7) <= fcount_7;
+    WCNT(8) <= fcount_8;
+    WCNT(9) <= fcount_9;
+    WCNT(10) <= fcount_10;
+    WCNT(11) <= fcount_11;
+    WCNT(12) <= fcount_12;
+    WCNT(13) <= fcount_13;
+    WCNT(14) <= fcount_14;
+    Empty <= empty_i;
+    Full <= full_i;
+end Structure;

diff --git a/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg_ngd.asd b/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg_ngd.asd
new file mode 100644 (file)
index 0000000..c265c78
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg_ngd.asd
@@ -0,0 +1 @@
+[ActiveSupport NGD]

diff --git a/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.cst b/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.cst
new file mode 100644 (file)
index 0000000..e2ce71a
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.cst
@@ -0,0 +1,3 @@
+Date=03/18/2015
+Time=14:40:46
+

diff --git a/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.edn b/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.edn
new file mode 100644 (file)
index 0000000..a1e46fb
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.edn
@@ -0,0 +1,3251 @@
+(edif fifo_36x1k_oreg
+  (edifVersion 2 0 0)
+  (edifLevel 0)
+  (keywordMap (keywordLevel 0))
+  (status
+    (written
+      (timestamp 2015 3 18 14 40 48)
+      (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80"))))
+      (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x1k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 1024 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.fdc ")
+  (library ORCLIB
+    (edifLevel 0)
+    (technology
+      (numberDefinition))
+    (cell CCU2C
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A0
+            (direction INPUT))
+          (port A1
+            (direction INPUT))
+          (port B0
+            (direction INPUT))
+          (port B1
+            (direction INPUT))
+          (port C0
+            (direction INPUT))
+          (port C1
+            (direction INPUT))
+          (port D0
+            (direction INPUT))
+          (port D1
+            (direction INPUT))
+          (port CIN
+            (direction INPUT))
+          (port S0
+            (direction OUTPUT))
+          (port S1
+            (direction OUTPUT))
+          (port COUT
+            (direction OUTPUT)))))
+    (cell AND2
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A
+            (direction INPUT))
+          (port B
+            (direction INPUT))
+          (port Z
+            (direction OUTPUT)))))
+    (cell FD1P3BX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port SP
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port PD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell FD1P3DX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port SP
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port CD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell FD1S3BX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port PD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell FD1S3DX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port CD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell INV
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A
+            (direction INPUT))
+          (port Z
+            (direction OUTPUT)))))
+    (cell ROM16X1A
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port AD3
+            (direction INPUT))
+          (port AD2
+            (direction INPUT))
+          (port AD1
+            (direction INPUT))
+          (port AD0
+            (direction INPUT))
+          (port DO0
+            (direction OUTPUT)))))
+    (cell VHI
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port Z
+            (direction OUTPUT)))))
+    (cell VLO
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port Z
+            (direction OUTPUT)))))
+    (cell XOR2
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A
+            (direction INPUT))
+          (port B
+            (direction INPUT))
+          (port Z
+            (direction OUTPUT)))))
+    (cell DP16KD
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port DIA17
+            (direction INPUT))
+          (port DIA16
+            (direction INPUT))
+          (port DIA15
+            (direction INPUT))
+          (port DIA14
+            (direction INPUT))
+          (port DIA13
+            (direction INPUT))
+          (port DIA12
+            (direction INPUT))
+          (port DIA11
+            (direction INPUT))
+          (port DIA10
+            (direction INPUT))
+          (port DIA9
+            (direction INPUT))
+          (port DIA8
+            (direction INPUT))
+          (port DIA7
+            (direction INPUT))
+          (port DIA6
+            (direction INPUT))
+          (port DIA5
+            (direction INPUT))
+          (port DIA4
+            (direction INPUT))
+          (port DIA3
+            (direction INPUT))
+          (port DIA2
+            (direction INPUT))
+          (port DIA1
+            (direction INPUT))
+          (port DIA0
+            (direction INPUT))
+          (port ADA13
+            (direction INPUT))
+          (port ADA12
+            (direction INPUT))
+          (port ADA11
+            (direction INPUT))
+          (port ADA10
+            (direction INPUT))
+          (port ADA9
+            (direction INPUT))
+          (port ADA8
+            (direction INPUT))
+          (port ADA7
+            (direction INPUT))
+          (port ADA6
+            (direction INPUT))
+          (port ADA5
+            (direction INPUT))
+          (port ADA4
+            (direction INPUT))
+          (port ADA3
+            (direction INPUT))
+          (port ADA2
+            (direction INPUT))
+          (port ADA1
+            (direction INPUT))
+          (port ADA0
+            (direction INPUT))
+          (port CEA
+            (direction INPUT))
+          (port OCEA
+            (direction INPUT))
+          (port CLKA
+            (direction INPUT))
+          (port WEA
+            (direction INPUT))
+          (port CSA2
+            (direction INPUT))
+          (port CSA1
+            (direction INPUT))
+          (port CSA0
+            (direction INPUT))
+          (port RSTA
+            (direction INPUT))
+          (port DIB17
+            (direction INPUT))
+          (port DIB16
+            (direction INPUT))
+          (port DIB15
+            (direction INPUT))
+          (port DIB14
+            (direction INPUT))
+          (port DIB13
+            (direction INPUT))
+          (port DIB12
+            (direction INPUT))
+          (port DIB11
+            (direction INPUT))
+          (port DIB10
+            (direction INPUT))
+          (port DIB9
+            (direction INPUT))
+          (port DIB8
+            (direction INPUT))
+          (port DIB7
+            (direction INPUT))
+          (port DIB6
+            (direction INPUT))
+          (port DIB5
+            (direction INPUT))
+          (port DIB4
+            (direction INPUT))
+          (port DIB3
+            (direction INPUT))
+          (port DIB2
+            (direction INPUT))
+          (port DIB1
+            (direction INPUT))
+          (port DIB0
+            (direction INPUT))
+          (port ADB13
+            (direction INPUT))
+          (port ADB12
+            (direction INPUT))
+          (port ADB11
+            (direction INPUT))
+          (port ADB10
+            (direction INPUT))
+          (port ADB9
+            (direction INPUT))
+          (port ADB8
+            (direction INPUT))
+          (port ADB7
+            (direction INPUT))
+          (port ADB6
+            (direction INPUT))
+          (port ADB5
+            (direction INPUT))
+          (port ADB4
+            (direction INPUT))
+          (port ADB3
+            (direction INPUT))
+          (port ADB2
+            (direction INPUT))
+          (port ADB1
+            (direction INPUT))
+          (port ADB0
+            (direction INPUT))
+          (port CEB
+            (direction INPUT))
+          (port OCEB
+            (direction INPUT))
+          (port CLKB
+            (direction INPUT))
+          (port WEB
+            (direction INPUT))
+          (port CSB2
+            (direction INPUT))
+          (port CSB1
+            (direction INPUT))
+          (port CSB0
+            (direction INPUT))
+          (port RSTB
+            (direction INPUT))
+          (port DOA17
+            (direction OUTPUT))
+          (port DOA16
+            (direction OUTPUT))
+          (port DOA15
+            (direction OUTPUT))
+          (port DOA14
+            (direction OUTPUT))
+          (port DOA13
+            (direction OUTPUT))
+          (port DOA12
+            (direction OUTPUT))
+          (port DOA11
+            (direction OUTPUT))
+          (port DOA10
+            (direction OUTPUT))
+          (port DOA9
+            (direction OUTPUT))
+          (port DOA8
+            (direction OUTPUT))
+          (port DOA7
+            (direction OUTPUT))
+          (port DOA6
+            (direction OUTPUT))
+          (port DOA5
+            (direction OUTPUT))
+          (port DOA4
+            (direction OUTPUT))
+          (port DOA3
+            (direction OUTPUT))
+          (port DOA2
+            (direction OUTPUT))
+          (port DOA1
+            (direction OUTPUT))
+          (port DOA0
+            (direction OUTPUT))
+          (port DOB17
+            (direction OUTPUT))
+          (port DOB16
+            (direction OUTPUT))
+          (port DOB15
+            (direction OUTPUT))
+          (port DOB14
+            (direction OUTPUT))
+          (port DOB13
+            (direction OUTPUT))
+          (port DOB12
+            (direction OUTPUT))
+          (port DOB11
+            (direction OUTPUT))
+          (port DOB10
+            (direction OUTPUT))
+          (port DOB9
+            (direction OUTPUT))
+          (port DOB8
+            (direction OUTPUT))
+          (port DOB7
+            (direction OUTPUT))
+          (port DOB6
+            (direction OUTPUT))
+          (port DOB5
+            (direction OUTPUT))
+          (port DOB4
+            (direction OUTPUT))
+          (port DOB3
+            (direction OUTPUT))
+          (port DOB2
+            (direction OUTPUT))
+          (port DOB1
+            (direction OUTPUT))
+          (port DOB0
+            (direction OUTPUT)))))
+    (cell fifo_36x1k_oreg
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port (array (rename Data "Data(35:0)") 36)
+            (direction INPUT))
+          (port Clock
+            (direction INPUT))
+          (port WrEn
+            (direction INPUT))
+          (port RdEn
+            (direction INPUT))
+          (port Reset
+            (direction INPUT))
+          (port (array (rename AmFullThresh "AmFullThresh(9:0)") 10)
+            (direction INPUT))
+          (port (array (rename Q "Q(35:0)") 36)
+            (direction OUTPUT))
+          (port (array (rename WCNT "WCNT(10:0)") 11)
+            (direction OUTPUT))
+          (port Empty
+            (direction OUTPUT))
+          (port Full
+            (direction OUTPUT))
+          (port AlmostFull
+            (direction OUTPUT)))
+        (property NGD_DRC_MASK (integer 1))
+        (contents
+          (instance AND2_t5
+            (viewRef view1 
+              (cellRef AND2)))
+          (instance INV_5
+            (viewRef view1 
+              (cellRef INV)))
+          (instance AND2_t4
+            (viewRef view1 
+              (cellRef AND2)))
+          (instance INV_4
+            (viewRef view1 
+              (cellRef INV)))
+          (instance AND2_t3
+            (viewRef view1 
+              (cellRef AND2)))
+          (instance XOR2_t2
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance INV_3
+            (viewRef view1 
+              (cellRef INV)))
+          (instance INV_2
+            (viewRef view1 
+              (cellRef INV)))
+          (instance LUT4_1
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x3232")))
+          (instance LUT4_0
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x3232")))
+          (instance AND2_t1
+            (viewRef view1 
+              (cellRef AND2)))
+          (instance INV_1
+            (viewRef view1 
+              (cellRef INV)))
+          (instance XOR2_t0
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance INV_0
+            (viewRef view1 
+              (cellRef INV)))
+          (instance pdp_ram_0_0_1
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x1k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b000"))
+            (property CSDECODE_A
+              (string "0b000"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "18"))
+            (property DATA_WIDTH_A
+              (string "18")))
+          (instance pdp_ram_0_1_0
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x1k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b000"))
+            (property CSDECODE_A
+              (string "0b000"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "18"))
+            (property DATA_WIDTH_A
+              (string "18")))
+          (instance FF_68
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_67
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_66
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_65
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_64
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_63
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_62
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_61
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_60
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_59
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_58
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_57
+            (viewRef view1 
+              (cellRef FD1S3BX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_56
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_55
+            (viewRef view1 
+              (cellRef FD1P3BX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_54
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_53
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_52
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_51
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_50
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_49
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_48
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_47
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_46
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_45
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_44
+            (viewRef view1 
+              (cellRef FD1P3BX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_43
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_42
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_41
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_40
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_39
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_38
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_37
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_36
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_35
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_34
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_33
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_32
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_31
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_30
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_29
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_28
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_27
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_26
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_25
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_24
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_23
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_22
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_21
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_20
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_19
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_18
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_17
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_16
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_15
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_14
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_13
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_12
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_11
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_10
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_9
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_8
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_7
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_6
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_5
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_4
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_3
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_2
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_1
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_0
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance bdcnt_bctr_cia
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance bdcnt_bctr_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_ci_a
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance e_cmp_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance a0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance g_cmp_ci_a
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance g_cmp_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance a1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_cia
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_cia
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance precin_inst288
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x0000"))
+            (property INIT0
+              (string "0x0000")))
+          (instance wcnt_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcntd
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance af_set_cmp_ci_a
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance af_set_cmp_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance scuba_vhi_inst
+            (viewRef view1 
+              (cellRef VHI)))
+          (instance scuba_vlo_inst
+            (viewRef view1 
+              (cellRef VLO)))
+          (instance a2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (net invout_2
+            (joined
+              (portRef Z (instanceRef INV_5))
+              (portRef B (instanceRef AND2_t5))))
+          (net invout_1
+            (joined
+              (portRef Z (instanceRef INV_4))
+              (portRef B (instanceRef AND2_t4))))
+          (net rden_i_inv
+            (joined
+              (portRef Z (instanceRef INV_3))
+              (portRef B (instanceRef AND2_t3))))
+          (net invout_0
+            (joined
+              (portRef Z (instanceRef INV_1))
+              (portRef B (instanceRef AND2_t1))))
+          (net r_nw
+            (joined
+              (portRef Z (instanceRef AND2_t1))))
+          (net fcnt_en
+            (joined
+              (portRef SP (instanceRef FF_58))
+              (portRef Z (instanceRef XOR2_t2))
+              (portRef SP (instanceRef FF_68))
+              (portRef SP (instanceRef FF_67))
+              (portRef SP (instanceRef FF_66))
+              (portRef SP (instanceRef FF_65))
+              (portRef SP (instanceRef FF_64))
+              (portRef SP (instanceRef FF_63))
+              (portRef SP (instanceRef FF_62))
+              (portRef SP (instanceRef FF_61))
+              (portRef SP (instanceRef FF_60))
+              (portRef SP (instanceRef FF_59))))
+          (net empty_d
+            (joined
+              (portRef D (instanceRef FF_57))
+              (portRef DO0 (instanceRef LUT4_1))))
+          (net full_d
+            (joined
+              (portRef D (instanceRef FF_56))
+              (portRef DO0 (instanceRef LUT4_0))))
+          (net wptr_0
+            (joined
+              (portRef Q (instanceRef FF_33))
+              (portRef ADA4 (instanceRef pdp_ram_0_0_1))
+              (portRef ADA4 (instanceRef pdp_ram_0_1_0))))
+          (net wptr_1
+            (joined
+              (portRef Q (instanceRef FF_32))
+              (portRef ADA5 (instanceRef pdp_ram_0_0_1))
+              (portRef ADA5 (instanceRef pdp_ram_0_1_0))))
+          (net wptr_2
+            (joined
+              (portRef Q (instanceRef FF_31))
+              (portRef ADA6 (instanceRef pdp_ram_0_0_1))
+              (portRef ADA6 (instanceRef pdp_ram_0_1_0))))
+          (net wptr_3
+            (joined
+              (portRef Q (instanceRef FF_30))
+              (portRef ADA7 (instanceRef pdp_ram_0_0_1))
+              (portRef ADA7 (instanceRef pdp_ram_0_1_0))))
+          (net wptr_4
+            (joined
+              (portRef Q (instanceRef FF_29))
+              (portRef ADA8 (instanceRef pdp_ram_0_0_1))
+              (portRef ADA8 (instanceRef pdp_ram_0_1_0))))
+          (net wptr_5
+            (joined
+              (portRef Q (instanceRef FF_28))
+              (portRef ADA9 (instanceRef pdp_ram_0_0_1))
+              (portRef ADA9 (instanceRef pdp_ram_0_1_0))))
+          (net wptr_6
+            (joined
+              (portRef Q (instanceRef FF_27))
+              (portRef ADA10 (instanceRef pdp_ram_0_0_1))
+              (portRef ADA10 (instanceRef pdp_ram_0_1_0))))
+          (net wptr_7
+            (joined
+              (portRef Q (instanceRef FF_26))
+              (portRef ADA11 (instanceRef pdp_ram_0_0_1))
+              (portRef ADA11 (instanceRef pdp_ram_0_1_0))))
+          (net wptr_8
+            (joined
+              (portRef Q (instanceRef FF_25))
+              (portRef ADA12 (instanceRef pdp_ram_0_0_1))
+              (portRef ADA12 (instanceRef pdp_ram_0_1_0))))
+          (net wptr_9
+            (joined
+              (portRef Q (instanceRef FF_24))
+              (portRef ADA13 (instanceRef pdp_ram_0_0_1))
+              (portRef ADA13 (instanceRef pdp_ram_0_1_0))))
+          (net wptr_10
+            (joined
+              (portRef Q (instanceRef FF_23))))
+          (net rptr_10
+            (joined
+              (portRef Q (instanceRef FF_12))
+              (portRef B (instanceRef XOR2_t0))))
+          (net ifcount_0
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_0))
+              (portRef D (instanceRef FF_68))))
+          (net ifcount_1
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_0))
+              (portRef D (instanceRef FF_67))))
+          (net bdcnt_bctr_ci
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_0))
+              (portRef COUT (instanceRef bdcnt_bctr_cia))))
+          (net ifcount_2
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_1))
+              (portRef D (instanceRef FF_66))))
+          (net ifcount_3
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_1))
+              (portRef D (instanceRef FF_65))))
+          (net co0
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_1))
+              (portRef COUT (instanceRef bdcnt_bctr_0))))
+          (net ifcount_4
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_2))
+              (portRef D (instanceRef FF_64))))
+          (net ifcount_5
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_2))
+              (portRef D (instanceRef FF_63))))
+          (net co1
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_2))
+              (portRef COUT (instanceRef bdcnt_bctr_1))))
+          (net ifcount_6
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_3))
+              (portRef D (instanceRef FF_62))))
+          (net ifcount_7
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_3))
+              (portRef D (instanceRef FF_61))))
+          (net co2
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_3))
+              (portRef COUT (instanceRef bdcnt_bctr_2))))
+          (net ifcount_8
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_4))
+              (portRef D (instanceRef FF_60))))
+          (net ifcount_9
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_4))
+              (portRef D (instanceRef FF_59))))
+          (net co3
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_4))
+              (portRef COUT (instanceRef bdcnt_bctr_3))))
+          (net ifcount_10
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_5))
+              (portRef D (instanceRef FF_58))))
+          (net co5
+            (joined
+              (portRef COUT (instanceRef bdcnt_bctr_5))))
+          (net co4
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_5))
+              (portRef COUT (instanceRef bdcnt_bctr_4))))
+          (net cmp_ci
+            (joined
+              (portRef CIN (instanceRef e_cmp_0))
+              (portRef COUT (instanceRef e_cmp_ci_a))))
+          (net rden_i
+            (joined
+              (portRef A0 (instanceRef e_cmp_0))
+              (portRef Z (instanceRef AND2_t4))
+              (portRef B (instanceRef XOR2_t2))
+              (portRef A (instanceRef INV_3))
+              (portRef AD1 (instanceRef LUT4_0))
+              (portRef A (instanceRef AND2_t1))
+              (portRef CEB (instanceRef pdp_ram_0_0_1))
+              (portRef CEB (instanceRef pdp_ram_0_1_0))
+              (portRef SP (instanceRef FF_44))
+              (portRef SP (instanceRef FF_43))
+              (portRef SP (instanceRef FF_42))
+              (portRef SP (instanceRef FF_41))
+              (portRef SP (instanceRef FF_40))
+              (portRef SP (instanceRef FF_39))
+              (portRef SP (instanceRef FF_38))
+              (portRef SP (instanceRef FF_37))
+              (portRef SP (instanceRef FF_36))
+              (portRef SP (instanceRef FF_35))
+              (portRef SP (instanceRef FF_34))
+              (portRef SP (instanceRef FF_22))
+              (portRef SP (instanceRef FF_21))
+              (portRef SP (instanceRef FF_20))
+              (portRef SP (instanceRef FF_19))
+              (portRef SP (instanceRef FF_18))
+              (portRef SP (instanceRef FF_17))
+              (portRef SP (instanceRef FF_16))
+              (portRef SP (instanceRef FF_15))
+              (portRef SP (instanceRef FF_14))
+              (portRef SP (instanceRef FF_13))
+              (portRef SP (instanceRef FF_12))))
+          (net co0_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_1))
+              (portRef COUT (instanceRef e_cmp_0))))
+          (net co1_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_2))
+              (portRef COUT (instanceRef e_cmp_1))))
+          (net co2_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_3))
+              (portRef COUT (instanceRef e_cmp_2))))
+          (net co3_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_4))
+              (portRef COUT (instanceRef e_cmp_3))))
+          (net co4_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_5))
+              (portRef COUT (instanceRef e_cmp_4))))
+          (net cmp_le_1
+            (joined
+              (portRef S0 (instanceRef a0))
+              (portRef AD2 (instanceRef LUT4_1))))
+          (net cmp_le_1_c
+            (joined
+              (portRef CIN (instanceRef a0))
+              (portRef COUT (instanceRef e_cmp_5))))
+          (net cmp_ci_1
+            (joined
+              (portRef CIN (instanceRef g_cmp_0))
+              (portRef COUT (instanceRef g_cmp_ci_a))))
+          (net co0_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_1))
+              (portRef COUT (instanceRef g_cmp_0))))
+          (net co1_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_2))
+              (portRef COUT (instanceRef g_cmp_1))))
+          (net co2_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_3))
+              (portRef COUT (instanceRef g_cmp_2))))
+          (net co3_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_4))
+              (portRef COUT (instanceRef g_cmp_3))))
+          (net co4_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_5))
+              (portRef COUT (instanceRef g_cmp_4))))
+          (net wren_i_inv
+            (joined
+              (portRef B0 (instanceRef g_cmp_5))
+              (portRef Z (instanceRef INV_2))))
+          (net cmp_ge_d1
+            (joined
+              (portRef S0 (instanceRef a1))
+              (portRef AD2 (instanceRef LUT4_0))))
+          (net cmp_ge_d1_c
+            (joined
+              (portRef CIN (instanceRef a1))
+              (portRef COUT (instanceRef g_cmp_5))))
+          (net iwcount_0
+            (joined
+              (portRef S0 (instanceRef w_ctr_0))
+              (portRef D (instanceRef FF_55))))
+          (net iwcount_1
+            (joined
+              (portRef S1 (instanceRef w_ctr_0))
+              (portRef D (instanceRef FF_54))))
+          (net w_ctr_ci
+            (joined
+              (portRef CIN (instanceRef w_ctr_0))
+              (portRef COUT (instanceRef w_ctr_cia))))
+          (net iwcount_2
+            (joined
+              (portRef S0 (instanceRef w_ctr_1))
+              (portRef D (instanceRef FF_53))))
+          (net iwcount_3
+            (joined
+              (portRef S1 (instanceRef w_ctr_1))
+              (portRef D (instanceRef FF_52))))
+          (net co0_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_1))
+              (portRef COUT (instanceRef w_ctr_0))))
+          (net iwcount_4
+            (joined
+              (portRef S0 (instanceRef w_ctr_2))
+              (portRef D (instanceRef FF_51))))
+          (net iwcount_5
+            (joined
+              (portRef S1 (instanceRef w_ctr_2))
+              (portRef D (instanceRef FF_50))))
+          (net co1_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_2))
+              (portRef COUT (instanceRef w_ctr_1))))
+          (net iwcount_6
+            (joined
+              (portRef S0 (instanceRef w_ctr_3))
+              (portRef D (instanceRef FF_49))))
+          (net iwcount_7
+            (joined
+              (portRef S1 (instanceRef w_ctr_3))
+              (portRef D (instanceRef FF_48))))
+          (net co2_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_3))
+              (portRef COUT (instanceRef w_ctr_2))))
+          (net iwcount_8
+            (joined
+              (portRef S0 (instanceRef w_ctr_4))
+              (portRef D (instanceRef FF_47))))
+          (net iwcount_9
+            (joined
+              (portRef S1 (instanceRef w_ctr_4))
+              (portRef D (instanceRef FF_46))))
+          (net co3_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_4))
+              (portRef COUT (instanceRef w_ctr_3))))
+          (net iwcount_10
+            (joined
+              (portRef S0 (instanceRef w_ctr_5))
+              (portRef D (instanceRef FF_45))))
+          (net co5_1
+            (joined
+              (portRef COUT (instanceRef w_ctr_5))))
+          (net co4_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_5))
+              (portRef COUT (instanceRef w_ctr_4))))
+          (net wcount_10
+            (joined
+              (portRef A0 (instanceRef w_ctr_5))
+              (portRef A (instanceRef XOR2_t0))
+              (portRef Q (instanceRef FF_45))
+              (portRef D (instanceRef FF_23))))
+          (net ircount_0
+            (joined
+              (portRef S0 (instanceRef r_ctr_0))
+              (portRef D (instanceRef FF_44))))
+          (net ircount_1
+            (joined
+              (portRef S1 (instanceRef r_ctr_0))
+              (portRef D (instanceRef FF_43))))
+          (net r_ctr_ci
+            (joined
+              (portRef CIN (instanceRef r_ctr_0))
+              (portRef COUT (instanceRef r_ctr_cia))))
+          (net rcount_0
+            (joined
+              (portRef A0 (instanceRef r_ctr_0))
+              (portRef Q (instanceRef FF_44))
+              (portRef D (instanceRef FF_22))))
+          (net rcount_1
+            (joined
+              (portRef A1 (instanceRef r_ctr_0))
+              (portRef Q (instanceRef FF_43))
+              (portRef D (instanceRef FF_21))))
+          (net ircount_2
+            (joined
+              (portRef S0 (instanceRef r_ctr_1))
+              (portRef D (instanceRef FF_42))))
+          (net ircount_3
+            (joined
+              (portRef S1 (instanceRef r_ctr_1))
+              (portRef D (instanceRef FF_41))))
+          (net co0_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_1))
+              (portRef COUT (instanceRef r_ctr_0))))
+          (net rcount_2
+            (joined
+              (portRef A0 (instanceRef r_ctr_1))
+              (portRef Q (instanceRef FF_42))
+              (portRef D (instanceRef FF_20))))
+          (net rcount_3
+            (joined
+              (portRef A1 (instanceRef r_ctr_1))
+              (portRef Q (instanceRef FF_41))
+              (portRef D (instanceRef FF_19))))
+          (net ircount_4
+            (joined
+              (portRef S0 (instanceRef r_ctr_2))
+              (portRef D (instanceRef FF_40))))
+          (net ircount_5
+            (joined
+              (portRef S1 (instanceRef r_ctr_2))
+              (portRef D (instanceRef FF_39))))
+          (net co1_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_2))
+              (portRef COUT (instanceRef r_ctr_1))))
+          (net rcount_4
+            (joined
+              (portRef A0 (instanceRef r_ctr_2))
+              (portRef Q (instanceRef FF_40))
+              (portRef D (instanceRef FF_18))))
+          (net rcount_5
+            (joined
+              (portRef A1 (instanceRef r_ctr_2))
+              (portRef Q (instanceRef FF_39))
+              (portRef D (instanceRef FF_17))))
+          (net ircount_6
+            (joined
+              (portRef S0 (instanceRef r_ctr_3))
+              (portRef D (instanceRef FF_38))))
+          (net ircount_7
+            (joined
+              (portRef S1 (instanceRef r_ctr_3))
+              (portRef D (instanceRef FF_37))))
+          (net co2_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_3))
+              (portRef COUT (instanceRef r_ctr_2))))
+          (net rcount_6
+            (joined
+              (portRef A0 (instanceRef r_ctr_3))
+              (portRef Q (instanceRef FF_38))
+              (portRef D (instanceRef FF_16))))
+          (net rcount_7
+            (joined
+              (portRef A1 (instanceRef r_ctr_3))
+              (portRef Q (instanceRef FF_37))
+              (portRef D (instanceRef FF_15))))
+          (net ircount_8
+            (joined
+              (portRef S0 (instanceRef r_ctr_4))
+              (portRef D (instanceRef FF_36))))
+          (net ircount_9
+            (joined
+              (portRef S1 (instanceRef r_ctr_4))
+              (portRef D (instanceRef FF_35))))
+          (net co3_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_4))
+              (portRef COUT (instanceRef r_ctr_3))))
+          (net rcount_8
+            (joined
+              (portRef A0 (instanceRef r_ctr_4))
+              (portRef Q (instanceRef FF_36))
+              (portRef D (instanceRef FF_14))))
+          (net rcount_9
+            (joined
+              (portRef A1 (instanceRef r_ctr_4))
+              (portRef Q (instanceRef FF_35))
+              (portRef D (instanceRef FF_13))))
+          (net ircount_10
+            (joined
+              (portRef S0 (instanceRef r_ctr_5))
+              (portRef D (instanceRef FF_34))))
+          (net co5_2
+            (joined
+              (portRef COUT (instanceRef r_ctr_5))))
+          (net co4_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_5))
+              (portRef COUT (instanceRef r_ctr_4))))
+          (net rcount_10
+            (joined
+              (portRef A0 (instanceRef r_ctr_5))
+              (portRef Q (instanceRef FF_34))
+              (portRef D (instanceRef FF_12))))
+          (net wcnt_sub_0
+            (joined
+              (portRef S1 (instanceRef wcnt_0))
+              (portRef D (instanceRef FF_11))))
+          (net rptr_0
+            (joined
+              (portRef B1 (instanceRef wcnt_0))
+              (portRef ADB4 (instanceRef pdp_ram_0_0_1))
+              (portRef ADB4 (instanceRef pdp_ram_0_1_0))
+              (portRef Q (instanceRef FF_22))))
+          (net cnt_con_inv
+            (joined
+              (portRef B0 (instanceRef wcnt_0))
+              (portRef Z (instanceRef INV_0))))
+          (net wcount_0
+            (joined
+              (portRef A1 (instanceRef wcnt_0))
+              (portRef Q (instanceRef FF_55))
+              (portRef D (instanceRef FF_33))
+              (portRef A0 (instanceRef w_ctr_0))))
+          (net cnt_con
+            (joined
+              (portRef A0 (instanceRef wcnt_0))
+              (portRef Z (instanceRef AND2_t3))
+              (portRef A (instanceRef INV_0))
+              (portRef B1 (instanceRef bdcnt_bctr_cia))
+              (portRef A1 (instanceRef bdcnt_bctr_cia))
+              (portRef B1 (instanceRef bdcnt_bctr_0))
+              (portRef B0 (instanceRef bdcnt_bctr_0))
+              (portRef B1 (instanceRef bdcnt_bctr_1))
+              (portRef B0 (instanceRef bdcnt_bctr_1))
+              (portRef B1 (instanceRef bdcnt_bctr_2))
+              (portRef B0 (instanceRef bdcnt_bctr_2))
+              (portRef B1 (instanceRef bdcnt_bctr_3))
+              (portRef B0 (instanceRef bdcnt_bctr_3))
+              (portRef B1 (instanceRef bdcnt_bctr_4))
+              (portRef B0 (instanceRef bdcnt_bctr_4))
+              (portRef B1 (instanceRef bdcnt_bctr_5))
+              (portRef B0 (instanceRef bdcnt_bctr_5))))
+          (net precin
+            (joined
+              (portRef CIN (instanceRef wcnt_0))
+              (portRef COUT (instanceRef precin_inst288))))
+          (net wcnt_sub_1
+            (joined
+              (portRef S0 (instanceRef wcnt_1))
+              (portRef D (instanceRef FF_10))))
+          (net wcnt_sub_2
+            (joined
+              (portRef S1 (instanceRef wcnt_1))
+              (portRef D (instanceRef FF_9))))
+          (net rptr_2
+            (joined
+              (portRef B1 (instanceRef wcnt_1))
+              (portRef ADB6 (instanceRef pdp_ram_0_0_1))
+              (portRef ADB6 (instanceRef pdp_ram_0_1_0))
+              (portRef Q (instanceRef FF_20))))
+          (net rptr_1
+            (joined
+              (portRef B0 (instanceRef wcnt_1))
+              (portRef ADB5 (instanceRef pdp_ram_0_0_1))
+              (portRef ADB5 (instanceRef pdp_ram_0_1_0))
+              (portRef Q (instanceRef FF_21))))
+          (net wcount_2
+            (joined
+              (portRef A1 (instanceRef wcnt_1))
+              (portRef Q (instanceRef FF_53))
+              (portRef D (instanceRef FF_31))
+              (portRef A0 (instanceRef w_ctr_1))))
+          (net wcount_1
+            (joined
+              (portRef A0 (instanceRef wcnt_1))
+              (portRef Q (instanceRef FF_54))
+              (portRef D (instanceRef FF_32))
+              (portRef A1 (instanceRef w_ctr_0))))
+          (net co0_5
+            (joined
+              (portRef CIN (instanceRef wcnt_1))
+              (portRef COUT (instanceRef wcnt_0))))
+          (net wcnt_sub_3
+            (joined
+              (portRef S0 (instanceRef wcnt_2))
+              (portRef D (instanceRef FF_8))))
+          (net wcnt_sub_4
+            (joined
+              (portRef S1 (instanceRef wcnt_2))
+              (portRef D (instanceRef FF_7))))
+          (net rptr_4
+            (joined
+              (portRef B1 (instanceRef wcnt_2))
+              (portRef ADB8 (instanceRef pdp_ram_0_0_1))
+              (portRef ADB8 (instanceRef pdp_ram_0_1_0))
+              (portRef Q (instanceRef FF_18))))
+          (net rptr_3
+            (joined
+              (portRef B0 (instanceRef wcnt_2))
+              (portRef ADB7 (instanceRef pdp_ram_0_0_1))
+              (portRef ADB7 (instanceRef pdp_ram_0_1_0))
+              (portRef Q (instanceRef FF_19))))
+          (net wcount_4
+            (joined
+              (portRef A1 (instanceRef wcnt_2))
+              (portRef Q (instanceRef FF_51))
+              (portRef D (instanceRef FF_29))
+              (portRef A0 (instanceRef w_ctr_2))))
+          (net wcount_3
+            (joined
+              (portRef A0 (instanceRef wcnt_2))
+              (portRef Q (instanceRef FF_52))
+              (portRef D (instanceRef FF_30))
+              (portRef A1 (instanceRef w_ctr_1))))
+          (net co1_5
+            (joined
+              (portRef CIN (instanceRef wcnt_2))
+              (portRef COUT (instanceRef wcnt_1))))
+          (net wcnt_sub_5
+            (joined
+              (portRef S0 (instanceRef wcnt_3))
+              (portRef D (instanceRef FF_6))))
+          (net wcnt_sub_6
+            (joined
+              (portRef S1 (instanceRef wcnt_3))
+              (portRef D (instanceRef FF_5))))
+          (net rptr_6
+            (joined
+              (portRef B1 (instanceRef wcnt_3))
+              (portRef ADB10 (instanceRef pdp_ram_0_0_1))
+              (portRef ADB10 (instanceRef pdp_ram_0_1_0))
+              (portRef Q (instanceRef FF_16))))
+          (net rptr_5
+            (joined
+              (portRef B0 (instanceRef wcnt_3))
+              (portRef ADB9 (instanceRef pdp_ram_0_0_1))
+              (portRef ADB9 (instanceRef pdp_ram_0_1_0))
+              (portRef Q (instanceRef FF_17))))
+          (net wcount_6
+            (joined
+              (portRef A1 (instanceRef wcnt_3))
+              (portRef Q (instanceRef FF_49))
+              (portRef D (instanceRef FF_27))
+              (portRef A0 (instanceRef w_ctr_3))))
+          (net wcount_5
+            (joined
+              (portRef A0 (instanceRef wcnt_3))
+              (portRef Q (instanceRef FF_50))
+              (portRef D (instanceRef FF_28))
+              (portRef A1 (instanceRef w_ctr_2))))
+          (net co2_5
+            (joined
+              (portRef CIN (instanceRef wcnt_3))
+              (portRef COUT (instanceRef wcnt_2))))
+          (net wcnt_sub_7
+            (joined
+              (portRef S0 (instanceRef wcnt_4))
+              (portRef D (instanceRef FF_4))))
+          (net wcnt_sub_8
+            (joined
+              (portRef S1 (instanceRef wcnt_4))
+              (portRef D (instanceRef FF_3))))
+          (net rptr_8
+            (joined
+              (portRef B1 (instanceRef wcnt_4))
+              (portRef ADB12 (instanceRef pdp_ram_0_0_1))
+              (portRef ADB12 (instanceRef pdp_ram_0_1_0))
+              (portRef Q (instanceRef FF_14))))
+          (net rptr_7
+            (joined
+              (portRef B0 (instanceRef wcnt_4))
+              (portRef ADB11 (instanceRef pdp_ram_0_0_1))
+              (portRef ADB11 (instanceRef pdp_ram_0_1_0))
+              (portRef Q (instanceRef FF_15))))
+          (net wcount_8
+            (joined
+              (portRef A1 (instanceRef wcnt_4))
+              (portRef Q (instanceRef FF_47))
+              (portRef D (instanceRef FF_25))
+              (portRef A0 (instanceRef w_ctr_4))))
+          (net wcount_7
+            (joined
+              (portRef A0 (instanceRef wcnt_4))
+              (portRef Q (instanceRef FF_48))
+              (portRef D (instanceRef FF_26))
+              (portRef A1 (instanceRef w_ctr_3))))
+          (net co3_5
+            (joined
+              (portRef CIN (instanceRef wcnt_4))
+              (portRef COUT (instanceRef wcnt_3))))
+          (net wcnt_sub_9
+            (joined
+              (portRef S0 (instanceRef wcnt_5))
+              (portRef D (instanceRef FF_2))))
+          (net wcnt_sub_10
+            (joined
+              (portRef S1 (instanceRef wcnt_5))
+              (portRef D (instanceRef FF_1))))
+          (net rptr_9
+            (joined
+              (portRef B0 (instanceRef wcnt_5))
+              (portRef ADB13 (instanceRef pdp_ram_0_0_1))
+              (portRef ADB13 (instanceRef pdp_ram_0_1_0))
+              (portRef Q (instanceRef FF_13))))
+          (net wcnt_sub_msb
+            (joined
+              (portRef A1 (instanceRef wcnt_5))
+              (portRef Z (instanceRef XOR2_t0))))
+          (net wcount_9
+            (joined
+              (portRef A0 (instanceRef wcnt_5))
+              (portRef Q (instanceRef FF_46))
+              (portRef D (instanceRef FF_24))
+              (portRef A1 (instanceRef w_ctr_4))))
+          (net co4_5
+            (joined
+              (portRef CIN (instanceRef wcnt_5))
+              (portRef COUT (instanceRef wcnt_4))))
+          (net co5_3d
+            (joined
+              (portRef S0 (instanceRef wcntd))))
+          (net co5_3
+            (joined
+              (portRef CIN (instanceRef wcntd))
+              (portRef COUT (instanceRef wcnt_5))))
+          (net wren_i
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_ci_a))
+              (portRef Z (instanceRef AND2_t5))
+              (portRef A (instanceRef AND2_t3))
+              (portRef A (instanceRef XOR2_t2))
+              (portRef A (instanceRef INV_2))
+              (portRef AD1 (instanceRef LUT4_1))
+              (portRef A (instanceRef INV_1))
+              (portRef OCEA (instanceRef pdp_ram_0_0_1))
+              (portRef CEA (instanceRef pdp_ram_0_0_1))
+              (portRef OCEA (instanceRef pdp_ram_0_1_0))
+              (portRef CEA (instanceRef pdp_ram_0_1_0))
+              (portRef SP (instanceRef FF_55))
+              (portRef SP (instanceRef FF_54))
+              (portRef SP (instanceRef FF_53))
+              (portRef SP (instanceRef FF_52))
+              (portRef SP (instanceRef FF_51))
+              (portRef SP (instanceRef FF_50))
+              (portRef SP (instanceRef FF_49))
+              (portRef SP (instanceRef FF_48))
+              (portRef SP (instanceRef FF_47))
+              (portRef SP (instanceRef FF_46))
+              (portRef SP (instanceRef FF_45))
+              (portRef SP (instanceRef FF_33))
+              (portRef SP (instanceRef FF_32))
+              (portRef SP (instanceRef FF_31))
+              (portRef SP (instanceRef FF_30))
+              (portRef SP (instanceRef FF_29))
+              (portRef SP (instanceRef FF_28))
+              (portRef SP (instanceRef FF_27))
+              (portRef SP (instanceRef FF_26))
+              (portRef SP (instanceRef FF_25))
+              (portRef SP (instanceRef FF_24))
+              (portRef SP (instanceRef FF_23))
+              (portRef B0 (instanceRef g_cmp_0))
+              (portRef B1 (instanceRef g_cmp_0))
+              (portRef B0 (instanceRef g_cmp_1))
+              (portRef B1 (instanceRef g_cmp_1))
+              (portRef B0 (instanceRef g_cmp_2))
+              (portRef B1 (instanceRef g_cmp_2))
+              (portRef B0 (instanceRef g_cmp_3))
+              (portRef B1 (instanceRef g_cmp_3))
+              (portRef B0 (instanceRef g_cmp_4))
+              (portRef B1 (instanceRef g_cmp_4))
+              (portRef B1 (instanceRef af_set_cmp_ci_a))))
+          (net x
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_ci_a))
+              (portRef CIN (instanceRef bdcnt_bctr_cia))
+              (portRef CIN (instanceRef e_cmp_ci_a))
+              (portRef CIN (instanceRef g_cmp_ci_a))
+              (portRef CIN (instanceRef w_ctr_cia))
+              (portRef CIN (instanceRef r_ctr_cia))
+              (portRef CIN (instanceRef precin_inst288))))
+          (net cmp_ci_2
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_0))
+              (portRef COUT (instanceRef af_set_cmp_ci_a))))
+          (net wcnt_reg_0
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_0))
+              (portRef Q (instanceRef FF_11))))
+          (net wcnt_reg_1
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_0))
+              (portRef Q (instanceRef FF_10))))
+          (net co0_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_1))
+              (portRef COUT (instanceRef af_set_cmp_0))))
+          (net wcnt_reg_2
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_1))
+              (portRef Q (instanceRef FF_9))))
+          (net wcnt_reg_3
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_1))
+              (portRef Q (instanceRef FF_8))))
+          (net co1_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_2))
+              (portRef COUT (instanceRef af_set_cmp_1))))
+          (net wcnt_reg_4
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_2))
+              (portRef Q (instanceRef FF_7))))
+          (net wcnt_reg_5
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_2))
+              (portRef Q (instanceRef FF_6))))
+          (net co2_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_3))
+              (portRef COUT (instanceRef af_set_cmp_2))))
+          (net wcnt_reg_6
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_3))
+              (portRef Q (instanceRef FF_5))))
+          (net wcnt_reg_7
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_3))
+              (portRef Q (instanceRef FF_4))))
+          (net co3_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_4))
+              (portRef COUT (instanceRef af_set_cmp_3))))
+          (net wcnt_reg_8
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_4))
+              (portRef Q (instanceRef FF_3))))
+          (net wcnt_reg_9
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_4))
+              (portRef Q (instanceRef FF_2))))
+          (net co4_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_5))
+              (portRef COUT (instanceRef af_set_cmp_4))))
+          (net wcnt_reg_10
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_5))
+              (portRef Q (instanceRef FF_1))))
+          (net af_set
+            (joined
+              (portRef S0 (instanceRef a2))
+              (portRef D (instanceRef FF_0))))
+          (net scuba_vhi
+            (joined
+              (portRef Z (instanceRef scuba_vhi_inst))
+              (portRef OCEB (instanceRef pdp_ram_0_0_1))
+              (portRef WEA (instanceRef pdp_ram_0_0_1))
+              (portRef ADA1 (instanceRef pdp_ram_0_0_1))
+              (portRef ADA0 (instanceRef pdp_ram_0_0_1))
+              (portRef OCEB (instanceRef pdp_ram_0_1_0))
+              (portRef WEA (instanceRef pdp_ram_0_1_0))
+              (portRef ADA1 (instanceRef pdp_ram_0_1_0))
+              (portRef ADA0 (instanceRef pdp_ram_0_1_0))
+              (portRef C1 (instanceRef bdcnt_bctr_cia))
+              (portRef C0 (instanceRef bdcnt_bctr_cia))
+              (portRef D1 (instanceRef bdcnt_bctr_cia))
+              (portRef D0 (instanceRef bdcnt_bctr_cia))
+              (portRef D1 (instanceRef bdcnt_bctr_0))
+              (portRef D0 (instanceRef bdcnt_bctr_0))
+              (portRef C1 (instanceRef bdcnt_bctr_0))
+              (portRef C0 (instanceRef bdcnt_bctr_0))
+              (portRef D1 (instanceRef bdcnt_bctr_1))
+              (portRef D0 (instanceRef bdcnt_bctr_1))
+              (portRef C1 (instanceRef bdcnt_bctr_1))
+              (portRef C0 (instanceRef bdcnt_bctr_1))
+              (portRef D1 (instanceRef bdcnt_bctr_2))
+              (portRef D0 (instanceRef bdcnt_bctr_2))
+              (portRef C1 (instanceRef bdcnt_bctr_2))
+              (portRef C0 (instanceRef bdcnt_bctr_2))
+              (portRef D1 (instanceRef bdcnt_bctr_3))
+              (portRef D0 (instanceRef bdcnt_bctr_3))
+              (portRef C1 (instanceRef bdcnt_bctr_3))
+              (portRef C0 (instanceRef bdcnt_bctr_3))
+              (portRef D1 (instanceRef bdcnt_bctr_4))
+              (portRef D0 (instanceRef bdcnt_bctr_4))
+              (portRef C1 (instanceRef bdcnt_bctr_4))
+              (portRef C0 (instanceRef bdcnt_bctr_4))
+              (portRef D1 (instanceRef bdcnt_bctr_5))
+              (portRef D0 (instanceRef bdcnt_bctr_5))
+              (portRef C1 (instanceRef bdcnt_bctr_5))
+              (portRef C0 (instanceRef bdcnt_bctr_5))
+              (portRef C1 (instanceRef e_cmp_ci_a))
+              (portRef C0 (instanceRef e_cmp_ci_a))
+              (portRef D1 (instanceRef e_cmp_ci_a))
+              (portRef D0 (instanceRef e_cmp_ci_a))
+              (portRef B1 (instanceRef e_cmp_ci_a))
+              (portRef B0 (instanceRef e_cmp_ci_a))
+              (portRef A1 (instanceRef e_cmp_ci_a))
+              (portRef A0 (instanceRef e_cmp_ci_a))
+              (portRef D1 (instanceRef e_cmp_0))
+              (portRef D0 (instanceRef e_cmp_0))
+              (portRef C1 (instanceRef e_cmp_0))
+              (portRef C0 (instanceRef e_cmp_0))
+              (portRef D1 (instanceRef e_cmp_1))
+              (portRef D0 (instanceRef e_cmp_1))
+              (portRef C1 (instanceRef e_cmp_1))
+              (portRef C0 (instanceRef e_cmp_1))
+              (portRef D1 (instanceRef e_cmp_2))
+              (portRef D0 (instanceRef e_cmp_2))
+              (portRef C1 (instanceRef e_cmp_2))
+              (portRef C0 (instanceRef e_cmp_2))
+              (portRef D1 (instanceRef e_cmp_3))
+              (portRef D0 (instanceRef e_cmp_3))
+              (portRef C1 (instanceRef e_cmp_3))
+              (portRef C0 (instanceRef e_cmp_3))
+              (portRef D1 (instanceRef e_cmp_4))
+              (portRef D0 (instanceRef e_cmp_4))
+              (portRef C1 (instanceRef e_cmp_4))
+              (portRef C0 (instanceRef e_cmp_4))
+              (portRef D1 (instanceRef e_cmp_5))
+              (portRef D0 (instanceRef e_cmp_5))
+              (portRef C1 (instanceRef e_cmp_5))
+              (portRef C0 (instanceRef e_cmp_5))
+              (portRef C1 (instanceRef a0))
+              (portRef C0 (instanceRef a0))
+              (portRef D1 (instanceRef a0))
+              (portRef D0 (instanceRef a0))
+              (portRef C1 (instanceRef g_cmp_ci_a))
+              (portRef C0 (instanceRef g_cmp_ci_a))
+              (portRef D1 (instanceRef g_cmp_ci_a))
+              (portRef D0 (instanceRef g_cmp_ci_a))
+              (portRef B1 (instanceRef g_cmp_ci_a))
+              (portRef B0 (instanceRef g_cmp_ci_a))
+              (portRef A1 (instanceRef g_cmp_ci_a))
+              (portRef A0 (instanceRef g_cmp_ci_a))
+              (portRef D1 (instanceRef g_cmp_0))
+              (portRef D0 (instanceRef g_cmp_0))
+              (portRef C1 (instanceRef g_cmp_0))
+              (portRef C0 (instanceRef g_cmp_0))
+              (portRef D1 (instanceRef g_cmp_1))
+              (portRef D0 (instanceRef g_cmp_1))
+              (portRef C1 (instanceRef g_cmp_1))
+              (portRef C0 (instanceRef g_cmp_1))
+              (portRef D1 (instanceRef g_cmp_2))
+              (portRef D0 (instanceRef g_cmp_2))
+              (portRef C1 (instanceRef g_cmp_2))
+              (portRef C0 (instanceRef g_cmp_2))
+              (portRef D1 (instanceRef g_cmp_3))
+              (portRef D0 (instanceRef g_cmp_3))
+              (portRef C1 (instanceRef g_cmp_3))
+              (portRef C0 (instanceRef g_cmp_3))
+              (portRef D1 (instanceRef g_cmp_4))
+              (portRef D0 (instanceRef g_cmp_4))
+              (portRef C1 (instanceRef g_cmp_4))
+              (portRef C0 (instanceRef g_cmp_4))
+              (portRef D1 (instanceRef g_cmp_5))
+              (portRef D0 (instanceRef g_cmp_5))
+              (portRef C1 (instanceRef g_cmp_5))
+              (portRef C0 (instanceRef g_cmp_5))
+              (portRef C1 (instanceRef a1))
+              (portRef C0 (instanceRef a1))
+              (portRef D1 (instanceRef a1))
+              (portRef D0 (instanceRef a1))
+              (portRef C1 (instanceRef w_ctr_cia))
+              (portRef C0 (instanceRef w_ctr_cia))
+              (portRef D1 (instanceRef w_ctr_cia))
+              (portRef D0 (instanceRef w_ctr_cia))
+              (portRef B1 (instanceRef w_ctr_cia))
+              (portRef A1 (instanceRef w_ctr_cia))
+              (portRef D1 (instanceRef w_ctr_0))
+              (portRef D0 (instanceRef w_ctr_0))
+              (portRef C1 (instanceRef w_ctr_0))
+              (portRef C0 (instanceRef w_ctr_0))
+              (portRef D1 (instanceRef w_ctr_1))
+              (portRef D0 (instanceRef w_ctr_1))
+              (portRef C1 (instanceRef w_ctr_1))
+              (portRef C0 (instanceRef w_ctr_1))
+              (portRef D1 (instanceRef w_ctr_2))
+              (portRef D0 (instanceRef w_ctr_2))
+              (portRef C1 (instanceRef w_ctr_2))
+              (portRef C0 (instanceRef w_ctr_2))
+              (portRef D1 (instanceRef w_ctr_3))
+              (portRef D0 (instanceRef w_ctr_3))
+              (portRef C1 (instanceRef w_ctr_3))
+              (portRef C0 (instanceRef w_ctr_3))
+              (portRef D1 (instanceRef w_ctr_4))
+              (portRef D0 (instanceRef w_ctr_4))
+              (portRef C1 (instanceRef w_ctr_4))
+              (portRef C0 (instanceRef w_ctr_4))
+              (portRef D1 (instanceRef w_ctr_5))
+              (portRef D0 (instanceRef w_ctr_5))
+              (portRef C1 (instanceRef w_ctr_5))
+              (portRef C0 (instanceRef w_ctr_5))
+              (portRef C1 (instanceRef r_ctr_cia))
+              (portRef C0 (instanceRef r_ctr_cia))
+              (portRef D1 (instanceRef r_ctr_cia))
+              (portRef D0 (instanceRef r_ctr_cia))
+              (portRef B1 (instanceRef r_ctr_cia))
+              (portRef A1 (instanceRef r_ctr_cia))
+              (portRef D1 (instanceRef r_ctr_0))
+              (portRef D0 (instanceRef r_ctr_0))
+              (portRef C1 (instanceRef r_ctr_0))
+              (portRef C0 (instanceRef r_ctr_0))
+              (portRef D1 (instanceRef r_ctr_1))
+              (portRef D0 (instanceRef r_ctr_1))
+              (portRef C1 (instanceRef r_ctr_1))
+              (portRef C0 (instanceRef r_ctr_1))
+              (portRef D1 (instanceRef r_ctr_2))
+              (portRef D0 (instanceRef r_ctr_2))
+              (portRef C1 (instanceRef r_ctr_2))
+              (portRef C0 (instanceRef r_ctr_2))
+              (portRef D1 (instanceRef r_ctr_3))
+              (portRef D0 (instanceRef r_ctr_3))
+              (portRef C1 (instanceRef r_ctr_3))
+              (portRef C0 (instanceRef r_ctr_3))
+              (portRef D1 (instanceRef r_ctr_4))
+              (portRef D0 (instanceRef r_ctr_4))
+              (portRef C1 (instanceRef r_ctr_4))
+              (portRef C0 (instanceRef r_ctr_4))
+              (portRef D1 (instanceRef r_ctr_5))
+              (portRef D0 (instanceRef r_ctr_5))
+              (portRef C1 (instanceRef r_ctr_5))
+              (portRef C0 (instanceRef r_ctr_5))
+              (portRef C1 (instanceRef precin_inst288))
+              (portRef C0 (instanceRef precin_inst288))
+              (portRef D1 (instanceRef precin_inst288))
+              (portRef D0 (instanceRef precin_inst288))
+              (portRef B1 (instanceRef precin_inst288))
+              (portRef B0 (instanceRef precin_inst288))
+              (portRef A1 (instanceRef precin_inst288))
+              (portRef A0 (instanceRef precin_inst288))
+              (portRef C1 (instanceRef wcnt_0))
+              (portRef C0 (instanceRef wcnt_0))
+              (portRef D1 (instanceRef wcnt_0))
+              (portRef D0 (instanceRef wcnt_0))
+              (portRef C1 (instanceRef wcnt_1))
+              (portRef C0 (instanceRef wcnt_1))
+              (portRef D1 (instanceRef wcnt_1))
+              (portRef D0 (instanceRef wcnt_1))
+              (portRef C1 (instanceRef wcnt_2))
+              (portRef C0 (instanceRef wcnt_2))
+              (portRef D1 (instanceRef wcnt_2))
+              (portRef D0 (instanceRef wcnt_2))
+              (portRef C1 (instanceRef wcnt_3))
+              (portRef C0 (instanceRef wcnt_3))
+              (portRef D1 (instanceRef wcnt_3))
+              (portRef D0 (instanceRef wcnt_3))
+              (portRef C1 (instanceRef wcnt_4))
+              (portRef C0 (instanceRef wcnt_4))
+              (portRef D1 (instanceRef wcnt_4))
+              (portRef D0 (instanceRef wcnt_4))
+              (portRef C1 (instanceRef wcnt_5))
+              (portRef C0 (instanceRef wcnt_5))
+              (portRef D1 (instanceRef wcnt_5))
+              (portRef D0 (instanceRef wcnt_5))
+              (portRef C1 (instanceRef wcntd))
+              (portRef C0 (instanceRef wcntd))
+              (portRef D1 (instanceRef wcntd))
+              (portRef D0 (instanceRef wcntd))
+              (portRef C1 (instanceRef af_set_cmp_ci_a))
+              (portRef C0 (instanceRef af_set_cmp_ci_a))
+              (portRef D1 (instanceRef af_set_cmp_ci_a))
+              (portRef D0 (instanceRef af_set_cmp_ci_a))
+              (portRef D1 (instanceRef af_set_cmp_0))
+              (portRef D0 (instanceRef af_set_cmp_0))
+              (portRef C1 (instanceRef af_set_cmp_0))
+              (portRef C0 (instanceRef af_set_cmp_0))
+              (portRef D1 (instanceRef af_set_cmp_1))
+              (portRef D0 (instanceRef af_set_cmp_1))
+              (portRef C1 (instanceRef af_set_cmp_1))
+              (portRef C0 (instanceRef af_set_cmp_1))
+              (portRef D1 (instanceRef af_set_cmp_2))
+              (portRef D0 (instanceRef af_set_cmp_2))
+              (portRef C1 (instanceRef af_set_cmp_2))
+              (portRef C0 (instanceRef af_set_cmp_2))
+              (portRef D1 (instanceRef af_set_cmp_3))
+              (portRef D0 (instanceRef af_set_cmp_3))
+              (portRef C1 (instanceRef af_set_cmp_3))
+              (portRef C0 (instanceRef af_set_cmp_3))
+              (portRef D1 (instanceRef af_set_cmp_4))
+              (portRef D0 (instanceRef af_set_cmp_4))
+              (portRef C1 (instanceRef af_set_cmp_4))
+              (portRef C0 (instanceRef af_set_cmp_4))
+              (portRef D1 (instanceRef af_set_cmp_5))
+              (portRef D0 (instanceRef af_set_cmp_5))
+              (portRef C1 (instanceRef af_set_cmp_5))
+              (portRef C0 (instanceRef af_set_cmp_5))
+              (portRef C1 (instanceRef a2))
+              (portRef C0 (instanceRef a2))
+              (portRef D1 (instanceRef a2))
+              (portRef D0 (instanceRef a2))))
+          (net scuba_vlo
+            (joined
+              (portRef Z (instanceRef scuba_vlo_inst))
+              (portRef AD3 (instanceRef LUT4_1))
+              (portRef AD3 (instanceRef LUT4_0))
+              (portRef CSB2 (instanceRef pdp_ram_0_0_1))
+              (portRef CSA2 (instanceRef pdp_ram_0_0_1))
+              (portRef CSB1 (instanceRef pdp_ram_0_0_1))
+              (portRef CSA1 (instanceRef pdp_ram_0_0_1))
+              (portRef CSB0 (instanceRef pdp_ram_0_0_1))
+              (portRef CSA0 (instanceRef pdp_ram_0_0_1))
+              (portRef WEB (instanceRef pdp_ram_0_0_1))
+              (portRef ADB3 (instanceRef pdp_ram_0_0_1))
+              (portRef ADA3 (instanceRef pdp_ram_0_0_1))
+              (portRef ADB2 (instanceRef pdp_ram_0_0_1))
+              (portRef ADA2 (instanceRef pdp_ram_0_0_1))
+              (portRef ADB1 (instanceRef pdp_ram_0_0_1))
+              (portRef ADB0 (instanceRef pdp_ram_0_0_1))
+              (portRef DIB17 (instanceRef pdp_ram_0_0_1))
+              (portRef DIB16 (instanceRef pdp_ram_0_0_1))
+              (portRef DIB15 (instanceRef pdp_ram_0_0_1))
+              (portRef DIB14 (instanceRef pdp_ram_0_0_1))
+              (portRef DIB13 (instanceRef pdp_ram_0_0_1))
+              (portRef DIB12 (instanceRef pdp_ram_0_0_1))
+              (portRef DIB11 (instanceRef pdp_ram_0_0_1))
+              (portRef DIB10 (instanceRef pdp_ram_0_0_1))
+              (portRef DIB9 (instanceRef pdp_ram_0_0_1))
+              (portRef DIB8 (instanceRef pdp_ram_0_0_1))
+              (portRef DIB7 (instanceRef pdp_ram_0_0_1))
+              (portRef DIB6 (instanceRef pdp_ram_0_0_1))
+              (portRef DIB5 (instanceRef pdp_ram_0_0_1))
+              (portRef DIB4 (instanceRef pdp_ram_0_0_1))
+              (portRef DIB3 (instanceRef pdp_ram_0_0_1))
+              (portRef DIB2 (instanceRef pdp_ram_0_0_1))
+              (portRef DIB1 (instanceRef pdp_ram_0_0_1))
+              (portRef DIB0 (instanceRef pdp_ram_0_0_1))
+              (portRef CSB2 (instanceRef pdp_ram_0_1_0))
+              (portRef CSA2 (instanceRef pdp_ram_0_1_0))
+              (portRef CSB1 (instanceRef pdp_ram_0_1_0))
+              (portRef CSA1 (instanceRef pdp_ram_0_1_0))
+              (portRef CSB0 (instanceRef pdp_ram_0_1_0))
+              (portRef CSA0 (instanceRef pdp_ram_0_1_0))
+              (portRef WEB (instanceRef pdp_ram_0_1_0))
+              (portRef ADB3 (instanceRef pdp_ram_0_1_0))
+              (portRef ADA3 (instanceRef pdp_ram_0_1_0))
+              (portRef ADB2 (instanceRef pdp_ram_0_1_0))
+              (portRef ADA2 (instanceRef pdp_ram_0_1_0))
+              (portRef ADB1 (instanceRef pdp_ram_0_1_0))
+              (portRef ADB0 (instanceRef pdp_ram_0_1_0))
+              (portRef DIB17 (instanceRef pdp_ram_0_1_0))
+              (portRef DIB16 (instanceRef pdp_ram_0_1_0))
+              (portRef DIB15 (instanceRef pdp_ram_0_1_0))
+              (portRef DIB14 (instanceRef pdp_ram_0_1_0))
+              (portRef DIB13 (instanceRef pdp_ram_0_1_0))
+              (portRef DIB12 (instanceRef pdp_ram_0_1_0))
+              (portRef DIB11 (instanceRef pdp_ram_0_1_0))
+              (portRef DIB10 (instanceRef pdp_ram_0_1_0))
+              (portRef DIB9 (instanceRef pdp_ram_0_1_0))
+              (portRef DIB8 (instanceRef pdp_ram_0_1_0))
+              (portRef DIB7 (instanceRef pdp_ram_0_1_0))
+              (portRef DIB6 (instanceRef pdp_ram_0_1_0))
+              (portRef DIB5 (instanceRef pdp_ram_0_1_0))
+              (portRef DIB4 (instanceRef pdp_ram_0_1_0))
+              (portRef DIB3 (instanceRef pdp_ram_0_1_0))
+              (portRef DIB2 (instanceRef pdp_ram_0_1_0))
+              (portRef DIB1 (instanceRef pdp_ram_0_1_0))
+              (portRef DIB0 (instanceRef pdp_ram_0_1_0))
+              (portRef B0 (instanceRef bdcnt_bctr_cia))
+              (portRef A0 (instanceRef bdcnt_bctr_cia))
+              (portRef A1 (instanceRef bdcnt_bctr_5))
+              (portRef A1 (instanceRef e_cmp_0))
+              (portRef A0 (instanceRef e_cmp_1))
+              (portRef A1 (instanceRef e_cmp_1))
+              (portRef A0 (instanceRef e_cmp_2))
+              (portRef A1 (instanceRef e_cmp_2))
+              (portRef A0 (instanceRef e_cmp_3))
+              (portRef A1 (instanceRef e_cmp_3))
+              (portRef A0 (instanceRef e_cmp_4))
+              (portRef A1 (instanceRef e_cmp_4))
+              (portRef A0 (instanceRef e_cmp_5))
+              (portRef A1 (instanceRef e_cmp_5))
+              (portRef B1 (instanceRef e_cmp_5))
+              (portRef B1 (instanceRef a0))
+              (portRef B0 (instanceRef a0))
+              (portRef A1 (instanceRef a0))
+              (portRef A0 (instanceRef a0))
+              (portRef B1 (instanceRef g_cmp_5))
+              (portRef A1 (instanceRef g_cmp_5))
+              (portRef B1 (instanceRef a1))
+              (portRef B0 (instanceRef a1))
+              (portRef A1 (instanceRef a1))
+              (portRef A0 (instanceRef a1))
+              (portRef B0 (instanceRef w_ctr_cia))
+              (portRef A0 (instanceRef w_ctr_cia))
+              (portRef B1 (instanceRef w_ctr_0))
+              (portRef B0 (instanceRef w_ctr_0))
+              (portRef B1 (instanceRef w_ctr_1))
+              (portRef B0 (instanceRef w_ctr_1))
+              (portRef B1 (instanceRef w_ctr_2))
+              (portRef B0 (instanceRef w_ctr_2))
+              (portRef B1 (instanceRef w_ctr_3))
+              (portRef B0 (instanceRef w_ctr_3))
+              (portRef B1 (instanceRef w_ctr_4))
+              (portRef B0 (instanceRef w_ctr_4))
+              (portRef B1 (instanceRef w_ctr_5))
+              (portRef B0 (instanceRef w_ctr_5))
+              (portRef A1 (instanceRef w_ctr_5))
+              (portRef B0 (instanceRef r_ctr_cia))
+              (portRef A0 (instanceRef r_ctr_cia))
+              (portRef B1 (instanceRef r_ctr_0))
+              (portRef B0 (instanceRef r_ctr_0))
+              (portRef B1 (instanceRef r_ctr_1))
+              (portRef B0 (instanceRef r_ctr_1))
+              (portRef B1 (instanceRef r_ctr_2))
+              (portRef B0 (instanceRef r_ctr_2))
+              (portRef B1 (instanceRef r_ctr_3))
+              (portRef B0 (instanceRef r_ctr_3))
+              (portRef B1 (instanceRef r_ctr_4))
+              (portRef B0 (instanceRef r_ctr_4))
+              (portRef B1 (instanceRef r_ctr_5))
+              (portRef B0 (instanceRef r_ctr_5))
+              (portRef A1 (instanceRef r_ctr_5))
+              (portRef B1 (instanceRef wcnt_5))
+              (portRef B1 (instanceRef wcntd))
+              (portRef B0 (instanceRef wcntd))
+              (portRef A1 (instanceRef wcntd))
+              (portRef A0 (instanceRef wcntd))
+              (portRef B0 (instanceRef af_set_cmp_ci_a))
+              (portRef A0 (instanceRef af_set_cmp_ci_a))
+              (portRef B0 (instanceRef af_set_cmp_5))
+              (portRef B1 (instanceRef af_set_cmp_5))
+              (portRef A1 (instanceRef af_set_cmp_5))
+              (portRef B1 (instanceRef a2))
+              (portRef B0 (instanceRef a2))
+              (portRef A1 (instanceRef a2))
+              (portRef A0 (instanceRef a2))))
+          (net af_set_c
+            (joined
+              (portRef CIN (instanceRef a2))
+              (portRef COUT (instanceRef af_set_cmp_5))))
+          (net partial_full
+            (joined
+              (portRef AlmostFull)
+              (portRef Q (instanceRef FF_0))))
+          (net Full
+            (joined
+              (portRef Full)
+              (portRef Q (instanceRef FF_56))
+              (portRef A (instanceRef INV_5))
+              (portRef AD0 (instanceRef LUT4_0))))
+          (net Empty
+            (joined
+              (portRef Empty)
+              (portRef Q (instanceRef FF_57))
+              (portRef A (instanceRef INV_4))
+              (portRef AD0 (instanceRef LUT4_1))))
+          (net WCNT10
+            (joined
+              (portRef (member WCNT 0))
+              (portRef A0 (instanceRef g_cmp_5))
+              (portRef Q (instanceRef FF_58))
+              (portRef A0 (instanceRef bdcnt_bctr_5))
+              (portRef B0 (instanceRef e_cmp_5))))
+          (net WCNT9
+            (joined
+              (portRef (member WCNT 1))
+              (portRef A1 (instanceRef g_cmp_4))
+              (portRef Q (instanceRef FF_59))
+              (portRef A1 (instanceRef bdcnt_bctr_4))
+              (portRef B1 (instanceRef e_cmp_4))))
+          (net WCNT8
+            (joined
+              (portRef (member WCNT 2))
+              (portRef A0 (instanceRef g_cmp_4))
+              (portRef Q (instanceRef FF_60))
+              (portRef A0 (instanceRef bdcnt_bctr_4))
+              (portRef B0 (instanceRef e_cmp_4))))
+          (net WCNT7
+            (joined
+              (portRef (member WCNT 3))
+              (portRef A1 (instanceRef g_cmp_3))
+              (portRef Q (instanceRef FF_61))
+              (portRef A1 (instanceRef bdcnt_bctr_3))
+              (portRef B1 (instanceRef e_cmp_3))))
+          (net WCNT6
+            (joined
+              (portRef (member WCNT 4))
+              (portRef A0 (instanceRef g_cmp_3))
+              (portRef Q (instanceRef FF_62))
+              (portRef A0 (instanceRef bdcnt_bctr_3))
+              (portRef B0 (instanceRef e_cmp_3))))
+          (net WCNT5
+            (joined
+              (portRef (member WCNT 5))
+              (portRef A1 (instanceRef g_cmp_2))
+              (portRef Q (instanceRef FF_63))
+              (portRef A1 (instanceRef bdcnt_bctr_2))
+              (portRef B1 (instanceRef e_cmp_2))))
+          (net WCNT4
+            (joined
+              (portRef (member WCNT 6))
+              (portRef A0 (instanceRef g_cmp_2))
+              (portRef Q (instanceRef FF_64))
+              (portRef A0 (instanceRef bdcnt_bctr_2))
+              (portRef B0 (instanceRef e_cmp_2))))
+          (net WCNT3
+            (joined
+              (portRef (member WCNT 7))
+              (portRef A1 (instanceRef g_cmp_1))
+              (portRef Q (instanceRef FF_65))
+              (portRef A1 (instanceRef bdcnt_bctr_1))
+              (portRef B1 (instanceRef e_cmp_1))))
+          (net WCNT2
+            (joined
+              (portRef (member WCNT 8))
+              (portRef A0 (instanceRef g_cmp_1))
+              (portRef Q (instanceRef FF_66))
+              (portRef A0 (instanceRef bdcnt_bctr_1))
+              (portRef B0 (instanceRef e_cmp_1))))
+          (net WCNT1
+            (joined
+              (portRef (member WCNT 9))
+              (portRef A1 (instanceRef g_cmp_0))
+              (portRef Q (instanceRef FF_67))
+              (portRef A1 (instanceRef bdcnt_bctr_0))
+              (portRef B1 (instanceRef e_cmp_0))))
+          (net WCNT0
+            (joined
+              (portRef (member WCNT 10))
+              (portRef A0 (instanceRef g_cmp_0))
+              (portRef Q (instanceRef FF_68))
+              (portRef A0 (instanceRef bdcnt_bctr_0))
+              (portRef B0 (instanceRef e_cmp_0))))
+          (net dataout35
+            (joined
+              (portRef (member Q 0))
+              (portRef DOB17 (instanceRef pdp_ram_0_1_0))))
+          (net dataout34
+            (joined
+              (portRef (member Q 1))
+              (portRef DOB16 (instanceRef pdp_ram_0_1_0))))
+          (net dataout33
+            (joined
+              (portRef (member Q 2))
+              (portRef DOB15 (instanceRef pdp_ram_0_1_0))))
+          (net dataout32
+            (joined
+              (portRef (member Q 3))
+              (portRef DOB14 (instanceRef pdp_ram_0_1_0))))
+          (net dataout31
+            (joined
+              (portRef (member Q 4))
+              (portRef DOB13 (instanceRef pdp_ram_0_1_0))))
+          (net dataout30
+            (joined
+              (portRef (member Q 5))
+              (portRef DOB12 (instanceRef pdp_ram_0_1_0))))
+          (net dataout29
+            (joined
+              (portRef (member Q 6))
+              (portRef DOB11 (instanceRef pdp_ram_0_1_0))))
+          (net dataout28
+            (joined
+              (portRef (member Q 7))
+              (portRef DOB10 (instanceRef pdp_ram_0_1_0))))
+          (net dataout27
+            (joined
+              (portRef (member Q 8))
+              (portRef DOB9 (instanceRef pdp_ram_0_1_0))))
+          (net dataout26
+            (joined
+              (portRef (member Q 9))
+              (portRef DOB8 (instanceRef pdp_ram_0_1_0))))
+          (net dataout25
+            (joined
+              (portRef (member Q 10))
+              (portRef DOB7 (instanceRef pdp_ram_0_1_0))))
+          (net dataout24
+            (joined
+              (portRef (member Q 11))
+              (portRef DOB6 (instanceRef pdp_ram_0_1_0))))
+          (net dataout23
+            (joined
+              (portRef (member Q 12))
+              (portRef DOB5 (instanceRef pdp_ram_0_1_0))))
+          (net dataout22
+            (joined
+              (portRef (member Q 13))
+              (portRef DOB4 (instanceRef pdp_ram_0_1_0))))
+          (net dataout21
+            (joined
+              (portRef (member Q 14))
+              (portRef DOB3 (instanceRef pdp_ram_0_1_0))))
+          (net dataout20
+            (joined
+              (portRef (member Q 15))
+              (portRef DOB2 (instanceRef pdp_ram_0_1_0))))
+          (net dataout19
+            (joined
+              (portRef (member Q 16))
+              (portRef DOB1 (instanceRef pdp_ram_0_1_0))))
+          (net dataout18
+            (joined
+              (portRef (member Q 17))
+              (portRef DOB0 (instanceRef pdp_ram_0_1_0))))
+          (net dataout17
+            (joined
+              (portRef (member Q 18))
+              (portRef DOB17 (instanceRef pdp_ram_0_0_1))))
+          (net dataout16
+            (joined
+              (portRef (member Q 19))
+              (portRef DOB16 (instanceRef pdp_ram_0_0_1))))
+          (net dataout15
+            (joined
+              (portRef (member Q 20))
+              (portRef DOB15 (instanceRef pdp_ram_0_0_1))))
+          (net dataout14
+            (joined
+              (portRef (member Q 21))
+              (portRef DOB14 (instanceRef pdp_ram_0_0_1))))
+          (net dataout13
+            (joined
+              (portRef (member Q 22))
+              (portRef DOB13 (instanceRef pdp_ram_0_0_1))))
+          (net dataout12
+            (joined
+              (portRef (member Q 23))
+              (portRef DOB12 (instanceRef pdp_ram_0_0_1))))
+          (net dataout11
+            (joined
+              (portRef (member Q 24))
+              (portRef DOB11 (instanceRef pdp_ram_0_0_1))))
+          (net dataout10
+            (joined
+              (portRef (member Q 25))
+              (portRef DOB10 (instanceRef pdp_ram_0_0_1))))
+          (net dataout9
+            (joined
+              (portRef (member Q 26))
+              (portRef DOB9 (instanceRef pdp_ram_0_0_1))))
+          (net dataout8
+            (joined
+              (portRef (member Q 27))
+              (portRef DOB8 (instanceRef pdp_ram_0_0_1))))
+          (net dataout7
+            (joined
+              (portRef (member Q 28))
+              (portRef DOB7 (instanceRef pdp_ram_0_0_1))))
+          (net dataout6
+            (joined
+              (portRef (member Q 29))
+              (portRef DOB6 (instanceRef pdp_ram_0_0_1))))
+          (net dataout5
+            (joined
+              (portRef (member Q 30))
+              (portRef DOB5 (instanceRef pdp_ram_0_0_1))))
+          (net dataout4
+            (joined
+              (portRef (member Q 31))
+              (portRef DOB4 (instanceRef pdp_ram_0_0_1))))
+          (net dataout3
+            (joined
+              (portRef (member Q 32))
+              (portRef DOB3 (instanceRef pdp_ram_0_0_1))))
+          (net dataout2
+            (joined
+              (portRef (member Q 33))
+              (portRef DOB2 (instanceRef pdp_ram_0_0_1))))
+          (net dataout1
+            (joined
+              (portRef (member Q 34))
+              (portRef DOB1 (instanceRef pdp_ram_0_0_1))))
+          (net dataout0
+            (joined
+              (portRef (member Q 35))
+              (portRef DOB0 (instanceRef pdp_ram_0_0_1))))
+          (net AmFullThresh9
+            (joined
+              (portRef (member AmFullThresh 0))
+              (portRef B1 (instanceRef af_set_cmp_4))))
+          (net AmFullThresh8
+            (joined
+              (portRef (member AmFullThresh 1))
+              (portRef B0 (instanceRef af_set_cmp_4))))
+          (net AmFullThresh7
+            (joined
+              (portRef (member AmFullThresh 2))
+              (portRef B1 (instanceRef af_set_cmp_3))))
+          (net AmFullThresh6
+            (joined
+              (portRef (member AmFullThresh 3))
+              (portRef B0 (instanceRef af_set_cmp_3))))
+          (net AmFullThresh5
+            (joined
+              (portRef (member AmFullThresh 4))
+              (portRef B1 (instanceRef af_set_cmp_2))))
+          (net AmFullThresh4
+            (joined
+              (portRef (member AmFullThresh 5))
+              (portRef B0 (instanceRef af_set_cmp_2))))
+          (net AmFullThresh3
+            (joined
+              (portRef (member AmFullThresh 6))
+              (portRef B1 (instanceRef af_set_cmp_1))))
+          (net AmFullThresh2
+            (joined
+              (portRef (member AmFullThresh 7))
+              (portRef B0 (instanceRef af_set_cmp_1))))
+          (net AmFullThresh1
+            (joined
+              (portRef (member AmFullThresh 8))
+              (portRef B1 (instanceRef af_set_cmp_0))))
+          (net AmFullThresh0
+            (joined
+              (portRef (member AmFullThresh 9))
+              (portRef B0 (instanceRef af_set_cmp_0))))
+          (net reset
+            (joined
+              (portRef Reset)
+              (portRef RSTB (instanceRef pdp_ram_0_0_1))
+              (portRef RSTA (instanceRef pdp_ram_0_0_1))
+              (portRef RSTB (instanceRef pdp_ram_0_1_0))
+              (portRef RSTA (instanceRef pdp_ram_0_1_0))
+              (portRef CD (instanceRef FF_68))
+              (portRef CD (instanceRef FF_67))
+              (portRef CD (instanceRef FF_66))
+              (portRef CD (instanceRef FF_65))
+              (portRef CD (instanceRef FF_64))
+              (portRef CD (instanceRef FF_63))
+              (portRef CD (instanceRef FF_62))
+              (portRef CD (instanceRef FF_61))
+              (portRef CD (instanceRef FF_60))
+              (portRef CD (instanceRef FF_59))
+              (portRef CD (instanceRef FF_58))
+              (portRef PD (instanceRef FF_57))
+              (portRef CD (instanceRef FF_56))
+              (portRef PD (instanceRef FF_55))
+              (portRef CD (instanceRef FF_54))
+              (portRef CD (instanceRef FF_53))
+              (portRef CD (instanceRef FF_52))
+              (portRef CD (instanceRef FF_51))
+              (portRef CD (instanceRef FF_50))
+              (portRef CD (instanceRef FF_49))
+              (portRef CD (instanceRef FF_48))
+              (portRef CD (instanceRef FF_47))
+              (portRef CD (instanceRef FF_46))
+              (portRef CD (instanceRef FF_45))
+              (portRef PD (instanceRef FF_44))
+              (portRef CD (instanceRef FF_43))
+              (portRef CD (instanceRef FF_42))
+              (portRef CD (instanceRef FF_41))
+              (portRef CD (instanceRef FF_40))
+              (portRef CD (instanceRef FF_39))
+              (portRef CD (instanceRef FF_38))
+              (portRef CD (instanceRef FF_37))
+              (portRef CD (instanceRef FF_36))
+              (portRef CD (instanceRef FF_35))
+              (portRef CD (instanceRef FF_34))
+              (portRef CD (instanceRef FF_33))
+              (portRef CD (instanceRef FF_32))
+              (portRef CD (instanceRef FF_31))
+              (portRef CD (instanceRef FF_30))
+              (portRef CD (instanceRef FF_29))
+              (portRef CD (instanceRef FF_28))
+              (portRef CD (instanceRef FF_27))
+              (portRef CD (instanceRef FF_26))
+              (portRef CD (instanceRef FF_25))
+              (portRef CD (instanceRef FF_24))
+              (portRef CD (instanceRef FF_23))
+              (portRef CD (instanceRef FF_22))
+              (portRef CD (instanceRef FF_21))
+              (portRef CD (instanceRef FF_20))
+              (portRef CD (instanceRef FF_19))
+              (portRef CD (instanceRef FF_18))
+              (portRef CD (instanceRef FF_17))
+              (portRef CD (instanceRef FF_16))
+              (portRef CD (instanceRef FF_15))
+              (portRef CD (instanceRef FF_14))
+              (portRef CD (instanceRef FF_13))
+              (portRef CD (instanceRef FF_12))
+              (portRef CD (instanceRef FF_11))
+              (portRef CD (instanceRef FF_10))
+              (portRef CD (instanceRef FF_9))
+              (portRef CD (instanceRef FF_8))
+              (portRef CD (instanceRef FF_7))
+              (portRef CD (instanceRef FF_6))
+              (portRef CD (instanceRef FF_5))
+              (portRef CD (instanceRef FF_4))
+              (portRef CD (instanceRef FF_3))
+              (portRef CD (instanceRef FF_2))
+              (portRef CD (instanceRef FF_1))
+              (portRef CD (instanceRef FF_0))))
+          (net rden
+            (joined
+              (portRef RdEn)
+              (portRef A (instanceRef AND2_t4))))
+          (net wren
+            (joined
+              (portRef WrEn)
+              (portRef A (instanceRef AND2_t5))))
+          (net clk
+            (joined
+              (portRef Clock)
+              (portRef CLKB (instanceRef pdp_ram_0_0_1))
+              (portRef CLKA (instanceRef pdp_ram_0_0_1))
+              (portRef CLKB (instanceRef pdp_ram_0_1_0))
+              (portRef CLKA (instanceRef pdp_ram_0_1_0))
+              (portRef CK (instanceRef FF_68))
+              (portRef CK (instanceRef FF_67))
+              (portRef CK (instanceRef FF_66))
+              (portRef CK (instanceRef FF_65))
+              (portRef CK (instanceRef FF_64))
+              (portRef CK (instanceRef FF_63))
+              (portRef CK (instanceRef FF_62))
+              (portRef CK (instanceRef FF_61))
+              (portRef CK (instanceRef FF_60))
+              (portRef CK (instanceRef FF_59))
+              (portRef CK (instanceRef FF_58))
+              (portRef CK (instanceRef FF_57))
+              (portRef CK (instanceRef FF_56))
+              (portRef CK (instanceRef FF_55))
+              (portRef CK (instanceRef FF_54))
+              (portRef CK (instanceRef FF_53))
+              (portRef CK (instanceRef FF_52))
+              (portRef CK (instanceRef FF_51))
+              (portRef CK (instanceRef FF_50))
+              (portRef CK (instanceRef FF_49))
+              (portRef CK (instanceRef FF_48))
+              (portRef CK (instanceRef FF_47))
+              (portRef CK (instanceRef FF_46))
+              (portRef CK (instanceRef FF_45))
+              (portRef CK (instanceRef FF_44))
+              (portRef CK (instanceRef FF_43))
+              (portRef CK (instanceRef FF_42))
+              (portRef CK (instanceRef FF_41))
+              (portRef CK (instanceRef FF_40))
+              (portRef CK (instanceRef FF_39))
+              (portRef CK (instanceRef FF_38))
+              (portRef CK (instanceRef FF_37))
+              (portRef CK (instanceRef FF_36))
+              (portRef CK (instanceRef FF_35))
+              (portRef CK (instanceRef FF_34))
+              (portRef CK (instanceRef FF_33))
+              (portRef CK (instanceRef FF_32))
+              (portRef CK (instanceRef FF_31))
+              (portRef CK (instanceRef FF_30))
+              (portRef CK (instanceRef FF_29))
+              (portRef CK (instanceRef FF_28))
+              (portRef CK (instanceRef FF_27))
+              (portRef CK (instanceRef FF_26))
+              (portRef CK (instanceRef FF_25))
+              (portRef CK (instanceRef FF_24))
+              (portRef CK (instanceRef FF_23))
+              (portRef CK (instanceRef FF_22))
+              (portRef CK (instanceRef FF_21))
+              (portRef CK (instanceRef FF_20))
+              (portRef CK (instanceRef FF_19))
+              (portRef CK (instanceRef FF_18))
+              (portRef CK (instanceRef FF_17))
+              (portRef CK (instanceRef FF_16))
+              (portRef CK (instanceRef FF_15))
+              (portRef CK (instanceRef FF_14))
+              (portRef CK (instanceRef FF_13))
+              (portRef CK (instanceRef FF_12))
+              (portRef CK (instanceRef FF_11))
+              (portRef CK (instanceRef FF_10))
+              (portRef CK (instanceRef FF_9))
+              (portRef CK (instanceRef FF_8))
+              (portRef CK (instanceRef FF_7))
+              (portRef CK (instanceRef FF_6))
+              (portRef CK (instanceRef FF_5))
+              (portRef CK (instanceRef FF_4))
+              (portRef CK (instanceRef FF_3))
+              (portRef CK (instanceRef FF_2))
+              (portRef CK (instanceRef FF_1))
+              (portRef CK (instanceRef FF_0))))
+          (net datain35
+            (joined
+              (portRef (member Data 0))
+              (portRef DIA17 (instanceRef pdp_ram_0_1_0))))
+          (net datain34
+            (joined
+              (portRef (member Data 1))
+              (portRef DIA16 (instanceRef pdp_ram_0_1_0))))
+          (net datain33
+            (joined
+              (portRef (member Data 2))
+              (portRef DIA15 (instanceRef pdp_ram_0_1_0))))
+          (net datain32
+            (joined
+              (portRef (member Data 3))
+              (portRef DIA14 (instanceRef pdp_ram_0_1_0))))
+          (net datain31
+            (joined
+              (portRef (member Data 4))
+              (portRef DIA13 (instanceRef pdp_ram_0_1_0))))
+          (net datain30
+            (joined
+              (portRef (member Data 5))
+              (portRef DIA12 (instanceRef pdp_ram_0_1_0))))
+          (net datain29
+            (joined
+              (portRef (member Data 6))
+              (portRef DIA11 (instanceRef pdp_ram_0_1_0))))
+          (net datain28
+            (joined
+              (portRef (member Data 7))
+              (portRef DIA10 (instanceRef pdp_ram_0_1_0))))
+          (net datain27
+            (joined
+              (portRef (member Data 8))
+              (portRef DIA9 (instanceRef pdp_ram_0_1_0))))
+          (net datain26
+            (joined
+              (portRef (member Data 9))
+              (portRef DIA8 (instanceRef pdp_ram_0_1_0))))
+          (net datain25
+            (joined
+              (portRef (member Data 10))
+              (portRef DIA7 (instanceRef pdp_ram_0_1_0))))
+          (net datain24
+            (joined
+              (portRef (member Data 11))
+              (portRef DIA6 (instanceRef pdp_ram_0_1_0))))
+          (net datain23
+            (joined
+              (portRef (member Data 12))
+              (portRef DIA5 (instanceRef pdp_ram_0_1_0))))
+          (net datain22
+            (joined
+              (portRef (member Data 13))
+              (portRef DIA4 (instanceRef pdp_ram_0_1_0))))
+          (net datain21
+            (joined
+              (portRef (member Data 14))
+              (portRef DIA3 (instanceRef pdp_ram_0_1_0))))
+          (net datain20
+            (joined
+              (portRef (member Data 15))
+              (portRef DIA2 (instanceRef pdp_ram_0_1_0))))
+          (net datain19
+            (joined
+              (portRef (member Data 16))
+              (portRef DIA1 (instanceRef pdp_ram_0_1_0))))
+          (net datain18
+            (joined
+              (portRef (member Data 17))
+              (portRef DIA0 (instanceRef pdp_ram_0_1_0))))
+          (net datain17
+            (joined
+              (portRef (member Data 18))
+              (portRef DIA17 (instanceRef pdp_ram_0_0_1))))
+          (net datain16
+            (joined
+              (portRef (member Data 19))
+              (portRef DIA16 (instanceRef pdp_ram_0_0_1))))
+          (net datain15
+            (joined
+              (portRef (member Data 20))
+              (portRef DIA15 (instanceRef pdp_ram_0_0_1))))
+          (net datain14
+            (joined
+              (portRef (member Data 21))
+              (portRef DIA14 (instanceRef pdp_ram_0_0_1))))
+          (net datain13
+            (joined
+              (portRef (member Data 22))
+              (portRef DIA13 (instanceRef pdp_ram_0_0_1))))
+          (net datain12
+            (joined
+              (portRef (member Data 23))
+              (portRef DIA12 (instanceRef pdp_ram_0_0_1))))
+          (net datain11
+            (joined
+              (portRef (member Data 24))
+              (portRef DIA11 (instanceRef pdp_ram_0_0_1))))
+          (net datain10
+            (joined
+              (portRef (member Data 25))
+              (portRef DIA10 (instanceRef pdp_ram_0_0_1))))
+          (net datain9
+            (joined
+              (portRef (member Data 26))
+              (portRef DIA9 (instanceRef pdp_ram_0_0_1))))
+          (net datain8
+            (joined
+              (portRef (member Data 27))
+              (portRef DIA8 (instanceRef pdp_ram_0_0_1))))
+          (net datain7
+            (joined
+              (portRef (member Data 28))
+              (portRef DIA7 (instanceRef pdp_ram_0_0_1))))
+          (net datain6
+            (joined
+              (portRef (member Data 29))
+              (portRef DIA6 (instanceRef pdp_ram_0_0_1))))
+          (net datain5
+            (joined
+              (portRef (member Data 30))
+              (portRef DIA5 (instanceRef pdp_ram_0_0_1))))
+          (net datain4
+            (joined
+              (portRef (member Data 31))
+              (portRef DIA4 (instanceRef pdp_ram_0_0_1))))
+          (net datain3
+            (joined
+              (portRef (member Data 32))
+              (portRef DIA3 (instanceRef pdp_ram_0_0_1))))
+          (net datain2
+            (joined
+              (portRef (member Data 33))
+              (portRef DIA2 (instanceRef pdp_ram_0_0_1))))
+          (net datain1
+            (joined
+              (portRef (member Data 34))
+              (portRef DIA1 (instanceRef pdp_ram_0_0_1))))
+          (net datain0
+            (joined
+              (portRef (member Data 35))
+              (portRef DIA0 (instanceRef pdp_ram_0_0_1))))))))
+  (design fifo_36x1k_oreg
+    (cellRef fifo_36x1k_oreg
+      (libraryRef ORCLIB)))
+)

diff --git a/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.fdc b/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.fdc
new file mode 100644 (file)
index 0000000..6fbcac9
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.fdc
@@ -0,0 +1,2 @@
+###==== Start Configuration
+

diff --git a/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.lpc b/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.lpc
new file mode 100644 (file)
index 0000000..2dc804f
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.lpc
@@ -0,0 +1,50 @@
+[Device]
+Family=ecp5um
+PartType=LFE5UM-85F
+PartName=LFE5UM-85F-8MG285C
+SpeedGrade=8
+Package=CSFBGA285
+OperatingCondition=COM
+Status=C
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO
+CoreRevision=5.0
+ModuleName=fifo_36x1k_oreg
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=03/18/2015
+Time=14:40:46
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=1024
+Width=36
+regout=1
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=1
+PfMode=Dynamic - Single Threshold
+PfAssert=508
+PfDeassert=506
+Reset=Async
+Reset1=Sync
+RDataCount=1
+EnECC=0
+EnFWFT=0
+
+[Command]
+cmd_line= -w -n fifo_36x1k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 1024 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill

diff --git a/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.ngd b/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.ngd
new file mode 100644 (file)
index 0000000..f9997bb
Binary files /dev/null and b/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.ngd differ

diff --git a/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.ngo b/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.ngo
new file mode 100644 (file)
index 0000000..f5480a0
Binary files /dev/null and b/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.ngo differ

diff --git a/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.vhd b/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.vhd
new file mode 100644 (file)
index 0000000..d861fe0
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.vhd
@@ -0,0 +1,1095 @@
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80
+-- Module  Version: 5.0
+--/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x1k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 1024 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.fdc 
+
+-- Wed Mar 18 14:40:48 2015
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity fifo_36x1k_oreg is
+    port (
+        Data: in  std_logic_vector(35 downto 0); 
+        Clock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        AmFullThresh: in  std_logic_vector(9 downto 0); 
+        Q: out  std_logic_vector(35 downto 0); 
+        WCNT: out  std_logic_vector(10 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic; 
+        AlmostFull: out  std_logic);
+end fifo_36x1k_oreg;
+
+architecture Structure of fifo_36x1k_oreg is
+
+    -- internal signal declarations
+    signal invout_2: std_logic;
+    signal invout_1: std_logic;
+    signal rden_i_inv: std_logic;
+    signal invout_0: std_logic;
+    signal r_nw: std_logic;
+    signal fcnt_en: std_logic;
+    signal empty_i: std_logic;
+    signal empty_d: std_logic;
+    signal full_i: std_logic;
+    signal full_d: std_logic;
+    signal wptr_0: std_logic;
+    signal wptr_1: std_logic;
+    signal wptr_2: std_logic;
+    signal wptr_3: std_logic;
+    signal wptr_4: std_logic;
+    signal wptr_5: std_logic;
+    signal wptr_6: std_logic;
+    signal wptr_7: std_logic;
+    signal wptr_8: std_logic;
+    signal wptr_9: std_logic;
+    signal wptr_10: std_logic;
+    signal rptr_10: std_logic;
+    signal ifcount_0: std_logic;
+    signal ifcount_1: std_logic;
+    signal bdcnt_bctr_ci: std_logic;
+    signal ifcount_2: std_logic;
+    signal ifcount_3: std_logic;
+    signal co0: std_logic;
+    signal ifcount_4: std_logic;
+    signal ifcount_5: std_logic;
+    signal co1: std_logic;
+    signal ifcount_6: std_logic;
+    signal ifcount_7: std_logic;
+    signal co2: std_logic;
+    signal ifcount_8: std_logic;
+    signal ifcount_9: std_logic;
+    signal co3: std_logic;
+    signal ifcount_10: std_logic;
+    signal co5: std_logic;
+    signal co4: std_logic;
+    signal cmp_ci: std_logic;
+    signal rden_i: std_logic;
+    signal co0_1: std_logic;
+    signal co1_1: std_logic;
+    signal co2_1: std_logic;
+    signal co3_1: std_logic;
+    signal co4_1: std_logic;
+    signal cmp_le_1: std_logic;
+    signal cmp_le_1_c: std_logic;
+    signal cmp_ci_1: std_logic;
+    signal fcount_0: std_logic;
+    signal fcount_1: std_logic;
+    signal co0_2: std_logic;
+    signal fcount_2: std_logic;
+    signal fcount_3: std_logic;
+    signal co1_2: std_logic;
+    signal fcount_4: std_logic;
+    signal fcount_5: std_logic;
+    signal co2_2: std_logic;
+    signal fcount_6: std_logic;
+    signal fcount_7: std_logic;
+    signal co3_2: std_logic;
+    signal fcount_8: std_logic;
+    signal fcount_9: std_logic;
+    signal co4_2: std_logic;
+    signal wren_i_inv: std_logic;
+    signal fcount_10: std_logic;
+    signal cmp_ge_d1: std_logic;
+    signal cmp_ge_d1_c: std_logic;
+    signal iwcount_0: std_logic;
+    signal iwcount_1: std_logic;
+    signal w_ctr_ci: std_logic;
+    signal iwcount_2: std_logic;
+    signal iwcount_3: std_logic;
+    signal co0_3: std_logic;
+    signal iwcount_4: std_logic;
+    signal iwcount_5: std_logic;
+    signal co1_3: std_logic;
+    signal iwcount_6: std_logic;
+    signal iwcount_7: std_logic;
+    signal co2_3: std_logic;
+    signal iwcount_8: std_logic;
+    signal iwcount_9: std_logic;
+    signal co3_3: std_logic;
+    signal iwcount_10: std_logic;
+    signal co5_1: std_logic;
+    signal co4_3: std_logic;
+    signal wcount_10: std_logic;
+    signal ircount_0: std_logic;
+    signal ircount_1: std_logic;
+    signal r_ctr_ci: std_logic;
+    signal rcount_0: std_logic;
+    signal rcount_1: std_logic;
+    signal ircount_2: std_logic;
+    signal ircount_3: std_logic;
+    signal co0_4: std_logic;
+    signal rcount_2: std_logic;
+    signal rcount_3: std_logic;
+    signal ircount_4: std_logic;
+    signal ircount_5: std_logic;
+    signal co1_4: std_logic;
+    signal rcount_4: std_logic;
+    signal rcount_5: std_logic;
+    signal ircount_6: std_logic;
+    signal ircount_7: std_logic;
+    signal co2_4: std_logic;
+    signal rcount_6: std_logic;
+    signal rcount_7: std_logic;
+    signal ircount_8: std_logic;
+    signal ircount_9: std_logic;
+    signal co3_4: std_logic;
+    signal rcount_8: std_logic;
+    signal rcount_9: std_logic;
+    signal ircount_10: std_logic;
+    signal co5_2: std_logic;
+    signal co4_4: std_logic;
+    signal rcount_10: std_logic;
+    signal wcnt_sub_0: std_logic;
+    signal rptr_0: std_logic;
+    signal cnt_con_inv: std_logic;
+    signal wcount_0: std_logic;
+    signal cnt_con: std_logic;
+    signal precin: std_logic;
+    signal wcnt_sub_1: std_logic;
+    signal wcnt_sub_2: std_logic;
+    signal rptr_2: std_logic;
+    signal rptr_1: std_logic;
+    signal wcount_2: std_logic;
+    signal wcount_1: std_logic;
+    signal co0_5: std_logic;
+    signal wcnt_sub_3: std_logic;
+    signal wcnt_sub_4: std_logic;
+    signal rptr_4: std_logic;
+    signal rptr_3: std_logic;
+    signal wcount_4: std_logic;
+    signal wcount_3: std_logic;
+    signal co1_5: std_logic;
+    signal wcnt_sub_5: std_logic;
+    signal wcnt_sub_6: std_logic;
+    signal rptr_6: std_logic;
+    signal rptr_5: std_logic;
+    signal wcount_6: std_logic;
+    signal wcount_5: std_logic;
+    signal co2_5: std_logic;
+    signal wcnt_sub_7: std_logic;
+    signal wcnt_sub_8: std_logic;
+    signal rptr_8: std_logic;
+    signal rptr_7: std_logic;
+    signal wcount_8: std_logic;
+    signal wcount_7: std_logic;
+    signal co3_5: std_logic;
+    signal wcnt_sub_9: std_logic;
+    signal wcnt_sub_10: std_logic;
+    signal rptr_9: std_logic;
+    signal wcnt_sub_msb: std_logic;
+    signal wcount_9: std_logic;
+    signal co4_5: std_logic;
+    signal co5_3d: std_logic;
+    signal co5_3: std_logic;
+    signal wren_i: std_logic;
+    signal cmp_ci_2: std_logic;
+    signal wcnt_reg_0: std_logic;
+    signal wcnt_reg_1: std_logic;
+    signal co0_6: std_logic;
+    signal wcnt_reg_2: std_logic;
+    signal wcnt_reg_3: std_logic;
+    signal co1_6: std_logic;
+    signal wcnt_reg_4: std_logic;
+    signal wcnt_reg_5: std_logic;
+    signal co2_6: std_logic;
+    signal wcnt_reg_6: std_logic;
+    signal wcnt_reg_7: std_logic;
+    signal co3_6: std_logic;
+    signal wcnt_reg_8: std_logic;
+    signal wcnt_reg_9: std_logic;
+    signal co4_6: std_logic;
+    signal wcnt_reg_10: std_logic;
+    signal af_set: std_logic;
+    signal scuba_vhi: std_logic;
+    signal scuba_vlo: std_logic;
+    signal af_set_c: std_logic;
+
+    attribute MEM_LPC_FILE : string; 
+    attribute MEM_INIT_FILE : string; 
+    attribute GSR : string; 
+    attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_36x1k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "fifo_36x1k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is "";
+    attribute GSR of FF_68 : label is "ENABLED";
+    attribute GSR of FF_67 : label is "ENABLED";
+    attribute GSR of FF_66 : label is "ENABLED";
+    attribute GSR of FF_65 : label is "ENABLED";
+    attribute GSR of FF_64 : label is "ENABLED";
+    attribute GSR of FF_63 : label is "ENABLED";
+    attribute GSR of FF_62 : label is "ENABLED";
+    attribute GSR of FF_61 : label is "ENABLED";
+    attribute GSR of FF_60 : label is "ENABLED";
+    attribute GSR of FF_59 : label is "ENABLED";
+    attribute GSR of FF_58 : label is "ENABLED";
+    attribute GSR of FF_57 : label is "ENABLED";
+    attribute GSR of FF_56 : label is "ENABLED";
+    attribute GSR of FF_55 : label is "ENABLED";
+    attribute GSR of FF_54 : label is "ENABLED";
+    attribute GSR of FF_53 : label is "ENABLED";
+    attribute GSR of FF_52 : label is "ENABLED";
+    attribute GSR of FF_51 : label is "ENABLED";
+    attribute GSR of FF_50 : label is "ENABLED";
+    attribute GSR of FF_49 : label is "ENABLED";
+    attribute GSR of FF_48 : label is "ENABLED";
+    attribute GSR of FF_47 : label is "ENABLED";
+    attribute GSR of FF_46 : label is "ENABLED";
+    attribute GSR of FF_45 : label is "ENABLED";
+    attribute GSR of FF_44 : label is "ENABLED";
+    attribute GSR of FF_43 : label is "ENABLED";
+    attribute GSR of FF_42 : label is "ENABLED";
+    attribute GSR of FF_41 : label is "ENABLED";
+    attribute GSR of FF_40 : label is "ENABLED";
+    attribute GSR of FF_39 : label is "ENABLED";
+    attribute GSR of FF_38 : label is "ENABLED";
+    attribute GSR of FF_37 : label is "ENABLED";
+    attribute GSR of FF_36 : label is "ENABLED";
+    attribute GSR of FF_35 : label is "ENABLED";
+    attribute GSR of FF_34 : label is "ENABLED";
+    attribute GSR of FF_33 : label is "ENABLED";
+    attribute GSR of FF_32 : label is "ENABLED";
+    attribute GSR of FF_31 : label is "ENABLED";
+    attribute GSR of FF_30 : label is "ENABLED";
+    attribute GSR of FF_29 : label is "ENABLED";
+    attribute GSR of FF_28 : label is "ENABLED";
+    attribute GSR of FF_27 : label is "ENABLED";
+    attribute GSR of FF_26 : label is "ENABLED";
+    attribute GSR of FF_25 : label is "ENABLED";
+    attribute GSR of FF_24 : label is "ENABLED";
+    attribute GSR of FF_23 : label is "ENABLED";
+    attribute GSR of FF_22 : label is "ENABLED";
+    attribute GSR of FF_21 : label is "ENABLED";
+    attribute GSR of FF_20 : label is "ENABLED";
+    attribute GSR of FF_19 : label is "ENABLED";
+    attribute GSR of FF_18 : label is "ENABLED";
+    attribute GSR of FF_17 : label is "ENABLED";
+    attribute GSR of FF_16 : label is "ENABLED";
+    attribute GSR of FF_15 : label is "ENABLED";
+    attribute GSR of FF_14 : label is "ENABLED";
+    attribute GSR of FF_13 : label is "ENABLED";
+    attribute GSR of FF_12 : label is "ENABLED";
+    attribute GSR of FF_11 : label is "ENABLED";
+    attribute GSR of FF_10 : label is "ENABLED";
+    attribute GSR of FF_9 : label is "ENABLED";
+    attribute GSR of FF_8 : label is "ENABLED";
+    attribute GSR of FF_7 : label is "ENABLED";
+    attribute GSR of FF_6 : label is "ENABLED";
+    attribute GSR of FF_5 : label is "ENABLED";
+    attribute GSR of FF_4 : label is "ENABLED";
+    attribute GSR of FF_3 : label is "ENABLED";
+    attribute GSR of FF_2 : label is "ENABLED";
+    attribute GSR of FF_1 : label is "ENABLED";
+    attribute GSR of FF_0 : label is "ENABLED";
+    attribute syn_keep : boolean;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    AND2_t5: AND2
+        port map (A=>WrEn, B=>invout_2, Z=>wren_i);
+
+    INV_5: INV
+        port map (A=>full_i, Z=>invout_2);
+
+    AND2_t4: AND2
+        port map (A=>RdEn, B=>invout_1, Z=>rden_i);
+
+    INV_4: INV
+        port map (A=>empty_i, Z=>invout_1);
+
+    AND2_t3: AND2
+        port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
+
+    XOR2_t2: XOR2
+        port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
+
+    INV_3: INV
+        port map (A=>rden_i, Z=>rden_i_inv);
+
+    INV_2: INV
+        port map (A=>wren_i, Z=>wren_i_inv);
+
+    LUT4_1: ROM16X1A
+        generic map (initval=> X"3232")
+        port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, 
+            AD0=>empty_i, DO0=>empty_d);
+
+    LUT4_0: ROM16X1A
+        generic map (initval=> X"3232")
+        port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, 
+            AD0=>full_i, DO0=>full_d);
+
+    AND2_t1: AND2
+        port map (A=>rden_i, B=>invout_0, Z=>r_nw);
+
+    INV_1: INV
+        port map (A=>wren_i, Z=>invout_0);
+
+    XOR2_t0: XOR2
+        port map (A=>wcount_10, B=>rptr_10, Z=>wcnt_sub_msb);
+
+    INV_0: INV
+        port map (A=>cnt_con, Z=>cnt_con_inv);
+
+    pdp_ram_0_0_1: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  18, 
+        DATA_WIDTH_A=>  18)
+        port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), 
+            DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), 
+            DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), 
+            DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), 
+            DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), 
+            DIA0=>Data(0), ADA13=>wptr_9, ADA12=>wptr_8, ADA11=>wptr_7, 
+            ADA10=>wptr_6, ADA9=>wptr_5, ADA8=>wptr_4, ADA7=>wptr_3, 
+            ADA6=>wptr_2, ADA5=>wptr_1, ADA4=>wptr_0, ADA3=>scuba_vlo, 
+            ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, 
+            CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, 
+            CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>scuba_vlo, 
+            RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, 
+            DIB0=>scuba_vlo, ADB13=>rptr_9, ADB12=>rptr_8, ADB11=>rptr_7, 
+            ADB10=>rptr_6, ADB9=>rptr_5, ADB8=>rptr_4, ADB7=>rptr_3, 
+            ADB6=>rptr_2, ADB5=>rptr_1, ADB4=>rptr_0, ADB3=>scuba_vlo, 
+            ADB2=>scuba_vlo, ADB1=>scuba_vlo, ADB0=>scuba_vlo, 
+            CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>scuba_vlo, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>Q(17), DOB16=>Q(16), DOB15=>Q(15), 
+            DOB14=>Q(14), DOB13=>Q(13), DOB12=>Q(12), DOB11=>Q(11), 
+            DOB10=>Q(10), DOB9=>Q(9), DOB8=>Q(8), DOB7=>Q(7), DOB6=>Q(6), 
+            DOB5=>Q(5), DOB4=>Q(4), DOB3=>Q(3), DOB2=>Q(2), DOB1=>Q(1), 
+            DOB0=>Q(0));
+
+    pdp_ram_0_1_0: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  18, 
+        DATA_WIDTH_A=>  18)
+        port map (DIA17=>Data(35), DIA16=>Data(34), DIA15=>Data(33), 
+            DIA14=>Data(32), DIA13=>Data(31), DIA12=>Data(30), 
+            DIA11=>Data(29), DIA10=>Data(28), DIA9=>Data(27), 
+            DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), 
+            DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), 
+            DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), 
+            ADA13=>wptr_9, ADA12=>wptr_8, ADA11=>wptr_7, ADA10=>wptr_6, 
+            ADA9=>wptr_5, ADA8=>wptr_4, ADA7=>wptr_3, ADA6=>wptr_2, 
+            ADA5=>wptr_1, ADA4=>wptr_0, ADA3=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vhi, ADA0=>scuba_vhi, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>scuba_vlo, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_9, ADB12=>rptr_8, ADB11=>rptr_7, ADB10=>rptr_6, 
+            ADB9=>rptr_5, ADB8=>rptr_4, ADB7=>rptr_3, ADB6=>rptr_2, 
+            ADB5=>rptr_1, ADB4=>rptr_0, ADB3=>scuba_vlo, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>scuba_vlo, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>Q(35), DOB16=>Q(34), DOB15=>Q(33), 
+            DOB14=>Q(32), DOB13=>Q(31), DOB12=>Q(30), DOB11=>Q(29), 
+            DOB10=>Q(28), DOB9=>Q(27), DOB8=>Q(26), DOB7=>Q(25), 
+            DOB6=>Q(24), DOB5=>Q(23), DOB4=>Q(22), DOB3=>Q(21), 
+            DOB2=>Q(20), DOB1=>Q(19), DOB0=>Q(18));
+
+    FF_68: FD1P3DX
+        port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_0);
+
+    FF_67: FD1P3DX
+        port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_1);
+
+    FF_66: FD1P3DX
+        port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_2);
+
+    FF_65: FD1P3DX
+        port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_3);
+
+    FF_64: FD1P3DX
+        port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_4);
+
+    FF_63: FD1P3DX
+        port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_5);
+
+    FF_62: FD1P3DX
+        port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_6);
+
+    FF_61: FD1P3DX
+        port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_7);
+
+    FF_60: FD1P3DX
+        port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_8);
+
+    FF_59: FD1P3DX
+        port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_9);
+
+    FF_58: FD1P3DX
+        port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_10);
+
+    FF_57: FD1S3BX
+        port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
+
+    FF_56: FD1S3DX
+        port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
+
+    FF_55: FD1P3BX
+        port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset, 
+            Q=>wcount_0);
+
+    FF_54: FD1P3DX
+        port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_1);
+
+    FF_53: FD1P3DX
+        port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_2);
+
+    FF_52: FD1P3DX
+        port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_3);
+
+    FF_51: FD1P3DX
+        port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_4);
+
+    FF_50: FD1P3DX
+        port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_5);
+
+    FF_49: FD1P3DX
+        port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_6);
+
+    FF_48: FD1P3DX
+        port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_7);
+
+    FF_47: FD1P3DX
+        port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_8);
+
+    FF_46: FD1P3DX
+        port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_9);
+
+    FF_45: FD1P3DX
+        port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_10);
+
+    FF_44: FD1P3BX
+        port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset, 
+            Q=>rcount_0);
+
+    FF_43: FD1P3DX
+        port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_1);
+
+    FF_42: FD1P3DX
+        port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_2);
+
+    FF_41: FD1P3DX
+        port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_3);
+
+    FF_40: FD1P3DX
+        port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_4);
+
+    FF_39: FD1P3DX
+        port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_5);
+
+    FF_38: FD1P3DX
+        port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_6);
+
+    FF_37: FD1P3DX
+        port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_7);
+
+    FF_36: FD1P3DX
+        port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_8);
+
+    FF_35: FD1P3DX
+        port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_9);
+
+    FF_34: FD1P3DX
+        port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_10);
+
+    FF_33: FD1P3DX
+        port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_0);
+
+    FF_32: FD1P3DX
+        port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_1);
+
+    FF_31: FD1P3DX
+        port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_2);
+
+    FF_30: FD1P3DX
+        port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_3);
+
+    FF_29: FD1P3DX
+        port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_4);
+
+    FF_28: FD1P3DX
+        port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_5);
+
+    FF_27: FD1P3DX
+        port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_6);
+
+    FF_26: FD1P3DX
+        port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_7);
+
+    FF_25: FD1P3DX
+        port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_8);
+
+    FF_24: FD1P3DX
+        port map (D=>wcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_9);
+
+    FF_23: FD1P3DX
+        port map (D=>wcount_10, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_10);
+
+    FF_22: FD1P3DX
+        port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_0);
+
+    FF_21: FD1P3DX
+        port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_1);
+
+    FF_20: FD1P3DX
+        port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_2);
+
+    FF_19: FD1P3DX
+        port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_3);
+
+    FF_18: FD1P3DX
+        port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_4);
+
+    FF_17: FD1P3DX
+        port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_5);
+
+    FF_16: FD1P3DX
+        port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_6);
+
+    FF_15: FD1P3DX
+        port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_7);
+
+    FF_14: FD1P3DX
+        port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_8);
+
+    FF_13: FD1P3DX
+        port map (D=>rcount_9, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_9);
+
+    FF_12: FD1P3DX
+        port map (D=>rcount_10, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_10);
+
+    FF_11: FD1S3DX
+        port map (D=>wcnt_sub_0, CK=>Clock, CD=>Reset, Q=>wcnt_reg_0);
+
+    FF_10: FD1S3DX
+        port map (D=>wcnt_sub_1, CK=>Clock, CD=>Reset, Q=>wcnt_reg_1);
+
+    FF_9: FD1S3DX
+        port map (D=>wcnt_sub_2, CK=>Clock, CD=>Reset, Q=>wcnt_reg_2);
+
+    FF_8: FD1S3DX
+        port map (D=>wcnt_sub_3, CK=>Clock, CD=>Reset, Q=>wcnt_reg_3);
+
+    FF_7: FD1S3DX
+        port map (D=>wcnt_sub_4, CK=>Clock, CD=>Reset, Q=>wcnt_reg_4);
+
+    FF_6: FD1S3DX
+        port map (D=>wcnt_sub_5, CK=>Clock, CD=>Reset, Q=>wcnt_reg_5);
+
+    FF_5: FD1S3DX
+        port map (D=>wcnt_sub_6, CK=>Clock, CD=>Reset, Q=>wcnt_reg_6);
+
+    FF_4: FD1S3DX
+        port map (D=>wcnt_sub_7, CK=>Clock, CD=>Reset, Q=>wcnt_reg_7);
+
+    FF_3: FD1S3DX
+        port map (D=>wcnt_sub_8, CK=>Clock, CD=>Reset, Q=>wcnt_reg_8);
+
+    FF_2: FD1S3DX
+        port map (D=>wcnt_sub_9, CK=>Clock, CD=>Reset, Q=>wcnt_reg_9);
+
+    FF_1: FD1S3DX
+        port map (D=>wcnt_sub_10, CK=>Clock, CD=>Reset, Q=>wcnt_reg_10);
+
+    FF_0: FD1S3DX
+        port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull);
+
+    bdcnt_bctr_cia: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>'X', S0=>open, S1=>open, COUT=>bdcnt_bctr_ci);
+
+    bdcnt_bctr_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_0, A1=>fcount_1, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>bdcnt_bctr_ci, S0=>ifcount_0, S1=>ifcount_1, COUT=>co0);
+
+    bdcnt_bctr_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co0, S0=>ifcount_2, S1=>ifcount_3, COUT=>co1);
+
+    bdcnt_bctr_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_4, A1=>fcount_5, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co1, S0=>ifcount_4, S1=>ifcount_5, COUT=>co2);
+
+    bdcnt_bctr_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_6, A1=>fcount_7, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co2, S0=>ifcount_6, S1=>ifcount_7, COUT=>co3);
+
+    bdcnt_bctr_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_8, A1=>fcount_9, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co3, S0=>ifcount_8, S1=>ifcount_9, COUT=>co4);
+
+    bdcnt_bctr_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_10, A1=>scuba_vlo, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co4, S0=>ifcount_10, S1=>open, COUT=>co5);
+
+    e_cmp_ci_a: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci);
+
+    e_cmp_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>rden_i, A1=>scuba_vlo, B0=>fcount_0, B1=>fcount_1, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>cmp_ci, S0=>open, S1=>open, COUT=>co0_1);
+
+    e_cmp_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_2, 
+            B1=>fcount_3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co0_1, S0=>open, S1=>open, COUT=>co1_1);
+
+    e_cmp_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_4, 
+            B1=>fcount_5, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co1_1, S0=>open, S1=>open, COUT=>co2_1);
+
+    e_cmp_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_6, 
+            B1=>fcount_7, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co2_1, S0=>open, S1=>open, COUT=>co3_1);
+
+    e_cmp_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_8, 
+            B1=>fcount_9, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co3_1, S0=>open, S1=>open, COUT=>co4_1);
+
+    e_cmp_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_10, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co4_1, S0=>open, S1=>open, 
+            COUT=>cmp_le_1_c);
+
+    a0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>cmp_le_1_c, S0=>cmp_le_1, S1=>open, 
+            COUT=>open);
+
+    g_cmp_ci_a: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_1);
+
+    g_cmp_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>cmp_ci_1, S0=>open, S1=>open, COUT=>co0_2);
+
+    g_cmp_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co0_2, S0=>open, S1=>open, COUT=>co1_2);
+
+    g_cmp_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co1_2, S0=>open, S1=>open, COUT=>co2_2);
+
+    g_cmp_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co2_2, S0=>open, S1=>open, COUT=>co3_2);
+
+    g_cmp_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co3_2, S0=>open, S1=>open, COUT=>co4_2);
+
+    g_cmp_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_10, A1=>scuba_vlo, B0=>wren_i_inv, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co4_2, S0=>open, S1=>open, 
+            COUT=>cmp_ge_d1_c);
+
+    a1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>cmp_ge_d1_c, S0=>cmp_ge_d1, S1=>open, 
+            COUT=>open);
+
+    w_ctr_cia: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>w_ctr_ci);
+
+    w_ctr_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>w_ctr_ci, S0=>iwcount_0, S1=>iwcount_1, 
+            COUT=>co0_3);
+
+    w_ctr_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_2, A1=>wcount_3, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co0_3, S0=>iwcount_2, S1=>iwcount_3, 
+            COUT=>co1_3);
+
+    w_ctr_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_4, A1=>wcount_5, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co1_3, S0=>iwcount_4, S1=>iwcount_5, 
+            COUT=>co2_3);
+
+    w_ctr_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_6, A1=>wcount_7, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co2_3, S0=>iwcount_6, S1=>iwcount_7, 
+            COUT=>co3_3);
+
+    w_ctr_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_8, A1=>wcount_9, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co3_3, S0=>iwcount_8, S1=>iwcount_9, 
+            COUT=>co4_3);
+
+    w_ctr_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_10, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co4_3, S0=>iwcount_10, S1=>open, 
+            COUT=>co5_1);
+
+    r_ctr_cia: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>r_ctr_ci);
+
+    r_ctr_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>r_ctr_ci, S0=>ircount_0, S1=>ircount_1, 
+            COUT=>co0_4);
+
+    r_ctr_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_2, A1=>rcount_3, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co0_4, S0=>ircount_2, S1=>ircount_3, 
+            COUT=>co1_4);
+
+    r_ctr_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_4, A1=>rcount_5, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co1_4, S0=>ircount_4, S1=>ircount_5, 
+            COUT=>co2_4);
+
+    r_ctr_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_6, A1=>rcount_7, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co2_4, S0=>ircount_6, S1=>ircount_7, 
+            COUT=>co3_4);
+
+    r_ctr_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_8, A1=>rcount_9, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co3_4, S0=>ircount_8, S1=>ircount_9, 
+            COUT=>co4_4);
+
+    r_ctr_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_10, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co4_4, S0=>ircount_10, S1=>open, 
+            COUT=>co5_2);
+
+    precin_inst288: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"0000", 
+        INIT0=> X"0000")
+        port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>precin);
+
+    wcnt_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>cnt_con, A1=>wcount_0, B0=>cnt_con_inv, B1=>rptr_0, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>precin, S0=>open, S1=>wcnt_sub_0, COUT=>co0_5);
+
+    wcnt_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_1, A1=>wcount_2, B0=>rptr_1, B1=>rptr_2, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co0_5, S0=>wcnt_sub_1, S1=>wcnt_sub_2, COUT=>co1_5);
+
+    wcnt_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_3, A1=>wcount_4, B0=>rptr_3, B1=>rptr_4, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co1_5, S0=>wcnt_sub_3, S1=>wcnt_sub_4, COUT=>co2_5);
+
+    wcnt_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_5, A1=>wcount_6, B0=>rptr_5, B1=>rptr_6, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co2_5, S0=>wcnt_sub_5, S1=>wcnt_sub_6, COUT=>co3_5);
+
+    wcnt_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_7, A1=>wcount_8, B0=>rptr_7, B1=>rptr_8, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co3_5, S0=>wcnt_sub_7, S1=>wcnt_sub_8, COUT=>co4_5);
+
+    wcnt_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_9, A1=>wcnt_sub_msb, B0=>rptr_9, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co4_5, S0=>wcnt_sub_9, S1=>wcnt_sub_10, 
+            COUT=>co5_3);
+
+    wcntd: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co5_3, S0=>co5_3d, S1=>open, COUT=>open);
+
+    af_set_cmp_ci_a: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_2);
+
+    af_set_cmp_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0), 
+            B1=>AmFullThresh(1), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>cmp_ci_2, S0=>open, 
+            S1=>open, COUT=>co0_6);
+
+    af_set_cmp_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2), 
+            B1=>AmFullThresh(3), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co0_6, S0=>open, S1=>open, 
+            COUT=>co1_6);
+
+    af_set_cmp_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4), 
+            B1=>AmFullThresh(5), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co1_6, S0=>open, S1=>open, 
+            COUT=>co2_6);
+
+    af_set_cmp_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6), 
+            B1=>AmFullThresh(7), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co2_6, S0=>open, S1=>open, 
+            COUT=>co3_6);
+
+    af_set_cmp_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8), 
+            B1=>AmFullThresh(9), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co3_6, S0=>open, S1=>open, 
+            COUT=>co4_6);
+
+    af_set_cmp_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_10, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co4_6, S0=>open, S1=>open, 
+            COUT=>af_set_c);
+
+    scuba_vhi_inst: VHI
+        port map (Z=>scuba_vhi);
+
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    a2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>af_set_c, S0=>af_set, S1=>open, 
+            COUT=>open);
+
+    WCNT(0) <= fcount_0;
+    WCNT(1) <= fcount_1;
+    WCNT(2) <= fcount_2;
+    WCNT(3) <= fcount_3;
+    WCNT(4) <= fcount_4;
+    WCNT(5) <= fcount_5;
+    WCNT(6) <= fcount_6;
+    WCNT(7) <= fcount_7;
+    WCNT(8) <= fcount_8;
+    WCNT(9) <= fcount_9;
+    WCNT(10) <= fcount_10;
+    Empty <= empty_i;
+    Full <= full_i;
+end Structure;

diff --git a/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg_ngd.asd b/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg_ngd.asd
new file mode 100644 (file)
index 0000000..c265c78
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg_ngd.asd
@@ -0,0 +1 @@
+[ActiveSupport NGD]

diff --git a/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.cst b/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.cst
new file mode 100644 (file)
index 0000000..644f757
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.cst
@@ -0,0 +1,3 @@
+Date=03/18/2015
+Time=14:41:09
+

diff --git a/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.edn b/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.edn
new file mode 100644 (file)
index 0000000..7dc903a
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.edn
@@ -0,0 +1,3557 @@
+(edif fifo_36x2k_oreg
+  (edifVersion 2 0 0)
+  (edifLevel 0)
+  (keywordMap (keywordLevel 0))
+  (status
+    (written
+      (timestamp 2015 3 18 14 41 11)
+      (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80"))))
+      (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x2k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 2048 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.fdc ")
+  (library ORCLIB
+    (edifLevel 0)
+    (technology
+      (numberDefinition))
+    (cell CCU2C
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A0
+            (direction INPUT))
+          (port A1
+            (direction INPUT))
+          (port B0
+            (direction INPUT))
+          (port B1
+            (direction INPUT))
+          (port C0
+            (direction INPUT))
+          (port C1
+            (direction INPUT))
+          (port D0
+            (direction INPUT))
+          (port D1
+            (direction INPUT))
+          (port CIN
+            (direction INPUT))
+          (port S0
+            (direction OUTPUT))
+          (port S1
+            (direction OUTPUT))
+          (port COUT
+            (direction OUTPUT)))))
+    (cell AND2
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A
+            (direction INPUT))
+          (port B
+            (direction INPUT))
+          (port Z
+            (direction OUTPUT)))))
+    (cell FD1P3BX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port SP
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port PD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell FD1P3DX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port SP
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port CD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell FD1S3BX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port PD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell FD1S3DX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port CD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell INV
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A
+            (direction INPUT))
+          (port Z
+            (direction OUTPUT)))))
+    (cell ROM16X1A
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port AD3
+            (direction INPUT))
+          (port AD2
+            (direction INPUT))
+          (port AD1
+            (direction INPUT))
+          (port AD0
+            (direction INPUT))
+          (port DO0
+            (direction OUTPUT)))))
+    (cell VHI
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port Z
+            (direction OUTPUT)))))
+    (cell VLO
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port Z
+            (direction OUTPUT)))))
+    (cell XOR2
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A
+            (direction INPUT))
+          (port B
+            (direction INPUT))
+          (port Z
+            (direction OUTPUT)))))
+    (cell DP16KD
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port DIA17
+            (direction INPUT))
+          (port DIA16
+            (direction INPUT))
+          (port DIA15
+            (direction INPUT))
+          (port DIA14
+            (direction INPUT))
+          (port DIA13
+            (direction INPUT))
+          (port DIA12
+            (direction INPUT))
+          (port DIA11
+            (direction INPUT))
+          (port DIA10
+            (direction INPUT))
+          (port DIA9
+            (direction INPUT))
+          (port DIA8
+            (direction INPUT))
+          (port DIA7
+            (direction INPUT))
+          (port DIA6
+            (direction INPUT))
+          (port DIA5
+            (direction INPUT))
+          (port DIA4
+            (direction INPUT))
+          (port DIA3
+            (direction INPUT))
+          (port DIA2
+            (direction INPUT))
+          (port DIA1
+            (direction INPUT))
+          (port DIA0
+            (direction INPUT))
+          (port ADA13
+            (direction INPUT))
+          (port ADA12
+            (direction INPUT))
+          (port ADA11
+            (direction INPUT))
+          (port ADA10
+            (direction INPUT))
+          (port ADA9
+            (direction INPUT))
+          (port ADA8
+            (direction INPUT))
+          (port ADA7
+            (direction INPUT))
+          (port ADA6
+            (direction INPUT))
+          (port ADA5
+            (direction INPUT))
+          (port ADA4
+            (direction INPUT))
+          (port ADA3
+            (direction INPUT))
+          (port ADA2
+            (direction INPUT))
+          (port ADA1
+            (direction INPUT))
+          (port ADA0
+            (direction INPUT))
+          (port CEA
+            (direction INPUT))
+          (port OCEA
+            (direction INPUT))
+          (port CLKA
+            (direction INPUT))
+          (port WEA
+            (direction INPUT))
+          (port CSA2
+            (direction INPUT))
+          (port CSA1
+            (direction INPUT))
+          (port CSA0
+            (direction INPUT))
+          (port RSTA
+            (direction INPUT))
+          (port DIB17
+            (direction INPUT))
+          (port DIB16
+            (direction INPUT))
+          (port DIB15
+            (direction INPUT))
+          (port DIB14
+            (direction INPUT))
+          (port DIB13
+            (direction INPUT))
+          (port DIB12
+            (direction INPUT))
+          (port DIB11
+            (direction INPUT))
+          (port DIB10
+            (direction INPUT))
+          (port DIB9
+            (direction INPUT))
+          (port DIB8
+            (direction INPUT))
+          (port DIB7
+            (direction INPUT))
+          (port DIB6
+            (direction INPUT))
+          (port DIB5
+            (direction INPUT))
+          (port DIB4
+            (direction INPUT))
+          (port DIB3
+            (direction INPUT))
+          (port DIB2
+            (direction INPUT))
+          (port DIB1
+            (direction INPUT))
+          (port DIB0
+            (direction INPUT))
+          (port ADB13
+            (direction INPUT))
+          (port ADB12
+            (direction INPUT))
+          (port ADB11
+            (direction INPUT))
+          (port ADB10
+            (direction INPUT))
+          (port ADB9
+            (direction INPUT))
+          (port ADB8
+            (direction INPUT))
+          (port ADB7
+            (direction INPUT))
+          (port ADB6
+            (direction INPUT))
+          (port ADB5
+            (direction INPUT))
+          (port ADB4
+            (direction INPUT))
+          (port ADB3
+            (direction INPUT))
+          (port ADB2
+            (direction INPUT))
+          (port ADB1
+            (direction INPUT))
+          (port ADB0
+            (direction INPUT))
+          (port CEB
+            (direction INPUT))
+          (port OCEB
+            (direction INPUT))
+          (port CLKB
+            (direction INPUT))
+          (port WEB
+            (direction INPUT))
+          (port CSB2
+            (direction INPUT))
+          (port CSB1
+            (direction INPUT))
+          (port CSB0
+            (direction INPUT))
+          (port RSTB
+            (direction INPUT))
+          (port DOA17
+            (direction OUTPUT))
+          (port DOA16
+            (direction OUTPUT))
+          (port DOA15
+            (direction OUTPUT))
+          (port DOA14
+            (direction OUTPUT))
+          (port DOA13
+            (direction OUTPUT))
+          (port DOA12
+            (direction OUTPUT))
+          (port DOA11
+            (direction OUTPUT))
+          (port DOA10
+            (direction OUTPUT))
+          (port DOA9
+            (direction OUTPUT))
+          (port DOA8
+            (direction OUTPUT))
+          (port DOA7
+            (direction OUTPUT))
+          (port DOA6
+            (direction OUTPUT))
+          (port DOA5
+            (direction OUTPUT))
+          (port DOA4
+            (direction OUTPUT))
+          (port DOA3
+            (direction OUTPUT))
+          (port DOA2
+            (direction OUTPUT))
+          (port DOA1
+            (direction OUTPUT))
+          (port DOA0
+            (direction OUTPUT))
+          (port DOB17
+            (direction OUTPUT))
+          (port DOB16
+            (direction OUTPUT))
+          (port DOB15
+            (direction OUTPUT))
+          (port DOB14
+            (direction OUTPUT))
+          (port DOB13
+            (direction OUTPUT))
+          (port DOB12
+            (direction OUTPUT))
+          (port DOB11
+            (direction OUTPUT))
+          (port DOB10
+            (direction OUTPUT))
+          (port DOB9
+            (direction OUTPUT))
+          (port DOB8
+            (direction OUTPUT))
+          (port DOB7
+            (direction OUTPUT))
+          (port DOB6
+            (direction OUTPUT))
+          (port DOB5
+            (direction OUTPUT))
+          (port DOB4
+            (direction OUTPUT))
+          (port DOB3
+            (direction OUTPUT))
+          (port DOB2
+            (direction OUTPUT))
+          (port DOB1
+            (direction OUTPUT))
+          (port DOB0
+            (direction OUTPUT)))))
+    (cell fifo_36x2k_oreg
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port (array (rename Data "Data(35:0)") 36)
+            (direction INPUT))
+          (port Clock
+            (direction INPUT))
+          (port WrEn
+            (direction INPUT))
+          (port RdEn
+            (direction INPUT))
+          (port Reset
+            (direction INPUT))
+          (port (array (rename AmFullThresh "AmFullThresh(10:0)") 11)
+            (direction INPUT))
+          (port (array (rename Q "Q(35:0)") 36)
+            (direction OUTPUT))
+          (port (array (rename WCNT "WCNT(11:0)") 12)
+            (direction OUTPUT))
+          (port Empty
+            (direction OUTPUT))
+          (port Full
+            (direction OUTPUT))
+          (port AlmostFull
+            (direction OUTPUT)))
+        (property NGD_DRC_MASK (integer 1))
+        (contents
+          (instance AND2_t5
+            (viewRef view1 
+              (cellRef AND2)))
+          (instance INV_5
+            (viewRef view1 
+              (cellRef INV)))
+          (instance AND2_t4
+            (viewRef view1 
+              (cellRef AND2)))
+          (instance INV_4
+            (viewRef view1 
+              (cellRef INV)))
+          (instance AND2_t3
+            (viewRef view1 
+              (cellRef AND2)))
+          (instance XOR2_t2
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance INV_3
+            (viewRef view1 
+              (cellRef INV)))
+          (instance INV_2
+            (viewRef view1 
+              (cellRef INV)))
+          (instance LUT4_1
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x3232")))
+          (instance LUT4_0
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x3232")))
+          (instance AND2_t1
+            (viewRef view1 
+              (cellRef AND2)))
+          (instance INV_1
+            (viewRef view1 
+              (cellRef INV)))
+          (instance XOR2_t0
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance INV_0
+            (viewRef view1 
+              (cellRef INV)))
+          (instance pdp_ram_0_0_3
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x2k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b000"))
+            (property CSDECODE_A
+              (string "0b000"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_0_1_2
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x2k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b000"))
+            (property CSDECODE_A
+              (string "0b000"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_0_2_1
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x2k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b000"))
+            (property CSDECODE_A
+              (string "0b000"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_0_3_0
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x2k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b000"))
+            (property CSDECODE_A
+              (string "0b000"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance FF_74
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_73
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_72
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_71
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_70
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_69
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_68
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_67
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_66
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_65
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_64
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_63
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_62
+            (viewRef view1 
+              (cellRef FD1S3BX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_61
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_60
+            (viewRef view1 
+              (cellRef FD1P3BX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_59
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_58
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_57
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_56
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_55
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_54
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_53
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_52
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_51
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_50
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_49
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_48
+            (viewRef view1 
+              (cellRef FD1P3BX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_47
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_46
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_45
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_44
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_43
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_42
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_41
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_40
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_39
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_38
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_37
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_36
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_35
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_34
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_33
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_32
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_31
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_30
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_29
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_28
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_27
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_26
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_25
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_24
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_23
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_22
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_21
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_20
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_19
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_18
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_17
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_16
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_15
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_14
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_13
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_12
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_11
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_10
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_9
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_8
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_7
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_6
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_5
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_4
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_3
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_2
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_1
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_0
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance bdcnt_bctr_cia
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance bdcnt_bctr_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_ci_a
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance e_cmp_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance a0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance g_cmp_ci_a
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance g_cmp_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance a1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_cia
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_cia
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance precin_inst299
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x0000"))
+            (property INIT0
+              (string "0x0000")))
+          (instance wcnt_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_6
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_ci_a
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance af_set_cmp_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance scuba_vhi_inst
+            (viewRef view1 
+              (cellRef VHI)))
+          (instance scuba_vlo_inst
+            (viewRef view1 
+              (cellRef VLO)))
+          (instance a2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (net invout_2
+            (joined
+              (portRef Z (instanceRef INV_5))
+              (portRef B (instanceRef AND2_t5))))
+          (net invout_1
+            (joined
+              (portRef Z (instanceRef INV_4))
+              (portRef B (instanceRef AND2_t4))))
+          (net rden_i_inv
+            (joined
+              (portRef Z (instanceRef INV_3))
+              (portRef B (instanceRef AND2_t3))))
+          (net invout_0
+            (joined
+              (portRef Z (instanceRef INV_1))
+              (portRef B (instanceRef AND2_t1))))
+          (net r_nw
+            (joined
+              (portRef Z (instanceRef AND2_t1))))
+          (net fcnt_en
+            (joined
+              (portRef SP (instanceRef FF_63))
+              (portRef Z (instanceRef XOR2_t2))
+              (portRef SP (instanceRef FF_74))
+              (portRef SP (instanceRef FF_73))
+              (portRef SP (instanceRef FF_72))
+              (portRef SP (instanceRef FF_71))
+              (portRef SP (instanceRef FF_70))
+              (portRef SP (instanceRef FF_69))
+              (portRef SP (instanceRef FF_68))
+              (portRef SP (instanceRef FF_67))
+              (portRef SP (instanceRef FF_66))
+              (portRef SP (instanceRef FF_65))
+              (portRef SP (instanceRef FF_64))))
+          (net empty_d
+            (joined
+              (portRef D (instanceRef FF_62))
+              (portRef DO0 (instanceRef LUT4_1))))
+          (net full_d
+            (joined
+              (portRef D (instanceRef FF_61))
+              (portRef DO0 (instanceRef LUT4_0))))
+          (net wptr_0
+            (joined
+              (portRef Q (instanceRef FF_36))
+              (portRef ADA3 (instanceRef pdp_ram_0_0_3))
+              (portRef ADA3 (instanceRef pdp_ram_0_1_2))
+              (portRef ADA3 (instanceRef pdp_ram_0_2_1))
+              (portRef ADA3 (instanceRef pdp_ram_0_3_0))))
+          (net wptr_1
+            (joined
+              (portRef Q (instanceRef FF_35))
+              (portRef ADA4 (instanceRef pdp_ram_0_0_3))
+              (portRef ADA4 (instanceRef pdp_ram_0_1_2))
+              (portRef ADA4 (instanceRef pdp_ram_0_2_1))
+              (portRef ADA4 (instanceRef pdp_ram_0_3_0))))
+          (net wptr_2
+            (joined
+              (portRef Q (instanceRef FF_34))
+              (portRef ADA5 (instanceRef pdp_ram_0_0_3))
+              (portRef ADA5 (instanceRef pdp_ram_0_1_2))
+              (portRef ADA5 (instanceRef pdp_ram_0_2_1))
+              (portRef ADA5 (instanceRef pdp_ram_0_3_0))))
+          (net wptr_3
+            (joined
+              (portRef Q (instanceRef FF_33))
+              (portRef ADA6 (instanceRef pdp_ram_0_0_3))
+              (portRef ADA6 (instanceRef pdp_ram_0_1_2))
+              (portRef ADA6 (instanceRef pdp_ram_0_2_1))
+              (portRef ADA6 (instanceRef pdp_ram_0_3_0))))
+          (net wptr_4
+            (joined
+              (portRef Q (instanceRef FF_32))
+              (portRef ADA7 (instanceRef pdp_ram_0_0_3))
+              (portRef ADA7 (instanceRef pdp_ram_0_1_2))
+              (portRef ADA7 (instanceRef pdp_ram_0_2_1))
+              (portRef ADA7 (instanceRef pdp_ram_0_3_0))))
+          (net wptr_5
+            (joined
+              (portRef Q (instanceRef FF_31))
+              (portRef ADA8 (instanceRef pdp_ram_0_0_3))
+              (portRef ADA8 (instanceRef pdp_ram_0_1_2))
+              (portRef ADA8 (instanceRef pdp_ram_0_2_1))
+              (portRef ADA8 (instanceRef pdp_ram_0_3_0))))
+          (net wptr_6
+            (joined
+              (portRef Q (instanceRef FF_30))
+              (portRef ADA9 (instanceRef pdp_ram_0_0_3))
+              (portRef ADA9 (instanceRef pdp_ram_0_1_2))
+              (portRef ADA9 (instanceRef pdp_ram_0_2_1))
+              (portRef ADA9 (instanceRef pdp_ram_0_3_0))))
+          (net wptr_7
+            (joined
+              (portRef Q (instanceRef FF_29))
+              (portRef ADA10 (instanceRef pdp_ram_0_0_3))
+              (portRef ADA10 (instanceRef pdp_ram_0_1_2))
+              (portRef ADA10 (instanceRef pdp_ram_0_2_1))
+              (portRef ADA10 (instanceRef pdp_ram_0_3_0))))
+          (net wptr_8
+            (joined
+              (portRef Q (instanceRef FF_28))
+              (portRef ADA11 (instanceRef pdp_ram_0_0_3))
+              (portRef ADA11 (instanceRef pdp_ram_0_1_2))
+              (portRef ADA11 (instanceRef pdp_ram_0_2_1))
+              (portRef ADA11 (instanceRef pdp_ram_0_3_0))))
+          (net wptr_9
+            (joined
+              (portRef Q (instanceRef FF_27))
+              (portRef ADA12 (instanceRef pdp_ram_0_0_3))
+              (portRef ADA12 (instanceRef pdp_ram_0_1_2))
+              (portRef ADA12 (instanceRef pdp_ram_0_2_1))
+              (portRef ADA12 (instanceRef pdp_ram_0_3_0))))
+          (net wptr_10
+            (joined
+              (portRef Q (instanceRef FF_26))
+              (portRef ADA13 (instanceRef pdp_ram_0_0_3))
+              (portRef ADA13 (instanceRef pdp_ram_0_1_2))
+              (portRef ADA13 (instanceRef pdp_ram_0_2_1))
+              (portRef ADA13 (instanceRef pdp_ram_0_3_0))))
+          (net wptr_11
+            (joined
+              (portRef Q (instanceRef FF_25))))
+          (net rptr_11
+            (joined
+              (portRef Q (instanceRef FF_13))
+              (portRef B (instanceRef XOR2_t0))))
+          (net ifcount_0
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_0))
+              (portRef D (instanceRef FF_74))))
+          (net ifcount_1
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_0))
+              (portRef D (instanceRef FF_73))))
+          (net bdcnt_bctr_ci
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_0))
+              (portRef COUT (instanceRef bdcnt_bctr_cia))))
+          (net ifcount_2
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_1))
+              (portRef D (instanceRef FF_72))))
+          (net ifcount_3
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_1))
+              (portRef D (instanceRef FF_71))))
+          (net co0
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_1))
+              (portRef COUT (instanceRef bdcnt_bctr_0))))
+          (net ifcount_4
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_2))
+              (portRef D (instanceRef FF_70))))
+          (net ifcount_5
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_2))
+              (portRef D (instanceRef FF_69))))
+          (net co1
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_2))
+              (portRef COUT (instanceRef bdcnt_bctr_1))))
+          (net ifcount_6
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_3))
+              (portRef D (instanceRef FF_68))))
+          (net ifcount_7
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_3))
+              (portRef D (instanceRef FF_67))))
+          (net co2
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_3))
+              (portRef COUT (instanceRef bdcnt_bctr_2))))
+          (net ifcount_8
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_4))
+              (portRef D (instanceRef FF_66))))
+          (net ifcount_9
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_4))
+              (portRef D (instanceRef FF_65))))
+          (net co3
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_4))
+              (portRef COUT (instanceRef bdcnt_bctr_3))))
+          (net ifcount_10
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_5))
+              (portRef D (instanceRef FF_64))))
+          (net ifcount_11
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_5))
+              (portRef D (instanceRef FF_63))))
+          (net co5
+            (joined
+              (portRef COUT (instanceRef bdcnt_bctr_5))))
+          (net co4
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_5))
+              (portRef COUT (instanceRef bdcnt_bctr_4))))
+          (net cmp_ci
+            (joined
+              (portRef CIN (instanceRef e_cmp_0))
+              (portRef COUT (instanceRef e_cmp_ci_a))))
+          (net rden_i
+            (joined
+              (portRef A0 (instanceRef e_cmp_0))
+              (portRef Z (instanceRef AND2_t4))
+              (portRef B (instanceRef XOR2_t2))
+              (portRef A (instanceRef INV_3))
+              (portRef AD1 (instanceRef LUT4_0))
+              (portRef A (instanceRef AND2_t1))
+              (portRef CEB (instanceRef pdp_ram_0_0_3))
+              (portRef CEB (instanceRef pdp_ram_0_1_2))
+              (portRef CEB (instanceRef pdp_ram_0_2_1))
+              (portRef CEB (instanceRef pdp_ram_0_3_0))
+              (portRef SP (instanceRef FF_48))
+              (portRef SP (instanceRef FF_47))
+              (portRef SP (instanceRef FF_46))
+              (portRef SP (instanceRef FF_45))
+              (portRef SP (instanceRef FF_44))
+              (portRef SP (instanceRef FF_43))
+              (portRef SP (instanceRef FF_42))
+              (portRef SP (instanceRef FF_41))
+              (portRef SP (instanceRef FF_40))
+              (portRef SP (instanceRef FF_39))
+              (portRef SP (instanceRef FF_38))
+              (portRef SP (instanceRef FF_37))
+              (portRef SP (instanceRef FF_24))
+              (portRef SP (instanceRef FF_23))
+              (portRef SP (instanceRef FF_22))
+              (portRef SP (instanceRef FF_21))
+              (portRef SP (instanceRef FF_20))
+              (portRef SP (instanceRef FF_19))
+              (portRef SP (instanceRef FF_18))
+              (portRef SP (instanceRef FF_17))
+              (portRef SP (instanceRef FF_16))
+              (portRef SP (instanceRef FF_15))
+              (portRef SP (instanceRef FF_14))
+              (portRef SP (instanceRef FF_13))))
+          (net co0_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_1))
+              (portRef COUT (instanceRef e_cmp_0))))
+          (net co1_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_2))
+              (portRef COUT (instanceRef e_cmp_1))))
+          (net co2_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_3))
+              (portRef COUT (instanceRef e_cmp_2))))
+          (net co3_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_4))
+              (portRef COUT (instanceRef e_cmp_3))))
+          (net co4_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_5))
+              (portRef COUT (instanceRef e_cmp_4))))
+          (net cmp_le_1
+            (joined
+              (portRef S0 (instanceRef a0))
+              (portRef AD2 (instanceRef LUT4_1))))
+          (net cmp_le_1_c
+            (joined
+              (portRef CIN (instanceRef a0))
+              (portRef COUT (instanceRef e_cmp_5))))
+          (net cmp_ci_1
+            (joined
+              (portRef CIN (instanceRef g_cmp_0))
+              (portRef COUT (instanceRef g_cmp_ci_a))))
+          (net co0_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_1))
+              (portRef COUT (instanceRef g_cmp_0))))
+          (net co1_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_2))
+              (portRef COUT (instanceRef g_cmp_1))))
+          (net co2_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_3))
+              (portRef COUT (instanceRef g_cmp_2))))
+          (net co3_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_4))
+              (portRef COUT (instanceRef g_cmp_3))))
+          (net co4_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_5))
+              (portRef COUT (instanceRef g_cmp_4))))
+          (net wren_i_inv
+            (joined
+              (portRef B1 (instanceRef g_cmp_5))
+              (portRef Z (instanceRef INV_2))))
+          (net cmp_ge_d1
+            (joined
+              (portRef S0 (instanceRef a1))
+              (portRef AD2 (instanceRef LUT4_0))))
+          (net cmp_ge_d1_c
+            (joined
+              (portRef CIN (instanceRef a1))
+              (portRef COUT (instanceRef g_cmp_5))))
+          (net iwcount_0
+            (joined
+              (portRef S0 (instanceRef w_ctr_0))
+              (portRef D (instanceRef FF_60))))
+          (net iwcount_1
+            (joined
+              (portRef S1 (instanceRef w_ctr_0))
+              (portRef D (instanceRef FF_59))))
+          (net w_ctr_ci
+            (joined
+              (portRef CIN (instanceRef w_ctr_0))
+              (portRef COUT (instanceRef w_ctr_cia))))
+          (net iwcount_2
+            (joined
+              (portRef S0 (instanceRef w_ctr_1))
+              (portRef D (instanceRef FF_58))))
+          (net iwcount_3
+            (joined
+              (portRef S1 (instanceRef w_ctr_1))
+              (portRef D (instanceRef FF_57))))
+          (net co0_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_1))
+              (portRef COUT (instanceRef w_ctr_0))))
+          (net iwcount_4
+            (joined
+              (portRef S0 (instanceRef w_ctr_2))
+              (portRef D (instanceRef FF_56))))
+          (net iwcount_5
+            (joined
+              (portRef S1 (instanceRef w_ctr_2))
+              (portRef D (instanceRef FF_55))))
+          (net co1_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_2))
+              (portRef COUT (instanceRef w_ctr_1))))
+          (net iwcount_6
+            (joined
+              (portRef S0 (instanceRef w_ctr_3))
+              (portRef D (instanceRef FF_54))))
+          (net iwcount_7
+            (joined
+              (portRef S1 (instanceRef w_ctr_3))
+              (portRef D (instanceRef FF_53))))
+          (net co2_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_3))
+              (portRef COUT (instanceRef w_ctr_2))))
+          (net iwcount_8
+            (joined
+              (portRef S0 (instanceRef w_ctr_4))
+              (portRef D (instanceRef FF_52))))
+          (net iwcount_9
+            (joined
+              (portRef S1 (instanceRef w_ctr_4))
+              (portRef D (instanceRef FF_51))))
+          (net co3_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_4))
+              (portRef COUT (instanceRef w_ctr_3))))
+          (net iwcount_10
+            (joined
+              (portRef S0 (instanceRef w_ctr_5))
+              (portRef D (instanceRef FF_50))))
+          (net iwcount_11
+            (joined
+              (portRef S1 (instanceRef w_ctr_5))
+              (portRef D (instanceRef FF_49))))
+          (net co5_1
+            (joined
+              (portRef COUT (instanceRef w_ctr_5))))
+          (net co4_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_5))
+              (portRef COUT (instanceRef w_ctr_4))))
+          (net wcount_11
+            (joined
+              (portRef A1 (instanceRef w_ctr_5))
+              (portRef A (instanceRef XOR2_t0))
+              (portRef Q (instanceRef FF_49))
+              (portRef D (instanceRef FF_25))))
+          (net ircount_0
+            (joined
+              (portRef S0 (instanceRef r_ctr_0))
+              (portRef D (instanceRef FF_48))))
+          (net ircount_1
+            (joined
+              (portRef S1 (instanceRef r_ctr_0))
+              (portRef D (instanceRef FF_47))))
+          (net r_ctr_ci
+            (joined
+              (portRef CIN (instanceRef r_ctr_0))
+              (portRef COUT (instanceRef r_ctr_cia))))
+          (net rcount_0
+            (joined
+              (portRef A0 (instanceRef r_ctr_0))
+              (portRef Q (instanceRef FF_48))
+              (portRef D (instanceRef FF_24))))
+          (net rcount_1
+            (joined
+              (portRef A1 (instanceRef r_ctr_0))
+              (portRef Q (instanceRef FF_47))
+              (portRef D (instanceRef FF_23))))
+          (net ircount_2
+            (joined
+              (portRef S0 (instanceRef r_ctr_1))
+              (portRef D (instanceRef FF_46))))
+          (net ircount_3
+            (joined
+              (portRef S1 (instanceRef r_ctr_1))
+              (portRef D (instanceRef FF_45))))
+          (net co0_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_1))
+              (portRef COUT (instanceRef r_ctr_0))))
+          (net rcount_2
+            (joined
+              (portRef A0 (instanceRef r_ctr_1))
+              (portRef Q (instanceRef FF_46))
+              (portRef D (instanceRef FF_22))))
+          (net rcount_3
+            (joined
+              (portRef A1 (instanceRef r_ctr_1))
+              (portRef Q (instanceRef FF_45))
+              (portRef D (instanceRef FF_21))))
+          (net ircount_4
+            (joined
+              (portRef S0 (instanceRef r_ctr_2))
+              (portRef D (instanceRef FF_44))))
+          (net ircount_5
+            (joined
+              (portRef S1 (instanceRef r_ctr_2))
+              (portRef D (instanceRef FF_43))))
+          (net co1_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_2))
+              (portRef COUT (instanceRef r_ctr_1))))
+          (net rcount_4
+            (joined
+              (portRef A0 (instanceRef r_ctr_2))
+              (portRef Q (instanceRef FF_44))
+              (portRef D (instanceRef FF_20))))
+          (net rcount_5
+            (joined
+              (portRef A1 (instanceRef r_ctr_2))
+              (portRef Q (instanceRef FF_43))
+              (portRef D (instanceRef FF_19))))
+          (net ircount_6
+            (joined
+              (portRef S0 (instanceRef r_ctr_3))
+              (portRef D (instanceRef FF_42))))
+          (net ircount_7
+            (joined
+              (portRef S1 (instanceRef r_ctr_3))
+              (portRef D (instanceRef FF_41))))
+          (net co2_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_3))
+              (portRef COUT (instanceRef r_ctr_2))))
+          (net rcount_6
+            (joined
+              (portRef A0 (instanceRef r_ctr_3))
+              (portRef Q (instanceRef FF_42))
+              (portRef D (instanceRef FF_18))))
+          (net rcount_7
+            (joined
+              (portRef A1 (instanceRef r_ctr_3))
+              (portRef Q (instanceRef FF_41))
+              (portRef D (instanceRef FF_17))))
+          (net ircount_8
+            (joined
+              (portRef S0 (instanceRef r_ctr_4))
+              (portRef D (instanceRef FF_40))))
+          (net ircount_9
+            (joined
+              (portRef S1 (instanceRef r_ctr_4))
+              (portRef D (instanceRef FF_39))))
+          (net co3_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_4))
+              (portRef COUT (instanceRef r_ctr_3))))
+          (net rcount_8
+            (joined
+              (portRef A0 (instanceRef r_ctr_4))
+              (portRef Q (instanceRef FF_40))
+              (portRef D (instanceRef FF_16))))
+          (net rcount_9
+            (joined
+              (portRef A1 (instanceRef r_ctr_4))
+              (portRef Q (instanceRef FF_39))
+              (portRef D (instanceRef FF_15))))
+          (net ircount_10
+            (joined
+              (portRef S0 (instanceRef r_ctr_5))
+              (portRef D (instanceRef FF_38))))
+          (net ircount_11
+            (joined
+              (portRef S1 (instanceRef r_ctr_5))
+              (portRef D (instanceRef FF_37))))
+          (net co5_2
+            (joined
+              (portRef COUT (instanceRef r_ctr_5))))
+          (net co4_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_5))
+              (portRef COUT (instanceRef r_ctr_4))))
+          (net rcount_10
+            (joined
+              (portRef A0 (instanceRef r_ctr_5))
+              (portRef Q (instanceRef FF_38))
+              (portRef D (instanceRef FF_14))))
+          (net rcount_11
+            (joined
+              (portRef A1 (instanceRef r_ctr_5))
+              (portRef Q (instanceRef FF_37))
+              (portRef D (instanceRef FF_13))))
+          (net wcnt_sub_0
+            (joined
+              (portRef S1 (instanceRef wcnt_0))
+              (portRef D (instanceRef FF_12))))
+          (net rptr_0
+            (joined
+              (portRef B1 (instanceRef wcnt_0))
+              (portRef ADB3 (instanceRef pdp_ram_0_0_3))
+              (portRef ADB3 (instanceRef pdp_ram_0_1_2))
+              (portRef ADB3 (instanceRef pdp_ram_0_2_1))
+              (portRef ADB3 (instanceRef pdp_ram_0_3_0))
+              (portRef Q (instanceRef FF_24))))
+          (net cnt_con_inv
+            (joined
+              (portRef B0 (instanceRef wcnt_0))
+              (portRef Z (instanceRef INV_0))))
+          (net wcount_0
+            (joined
+              (portRef A1 (instanceRef wcnt_0))
+              (portRef Q (instanceRef FF_60))
+              (portRef D (instanceRef FF_36))
+              (portRef A0 (instanceRef w_ctr_0))))
+          (net cnt_con
+            (joined
+              (portRef A0 (instanceRef wcnt_0))
+              (portRef Z (instanceRef AND2_t3))
+              (portRef A (instanceRef INV_0))
+              (portRef B1 (instanceRef bdcnt_bctr_cia))
+              (portRef A1 (instanceRef bdcnt_bctr_cia))
+              (portRef B1 (instanceRef bdcnt_bctr_0))
+              (portRef B0 (instanceRef bdcnt_bctr_0))
+              (portRef B1 (instanceRef bdcnt_bctr_1))
+              (portRef B0 (instanceRef bdcnt_bctr_1))
+              (portRef B1 (instanceRef bdcnt_bctr_2))
+              (portRef B0 (instanceRef bdcnt_bctr_2))
+              (portRef B1 (instanceRef bdcnt_bctr_3))
+              (portRef B0 (instanceRef bdcnt_bctr_3))
+              (portRef B1 (instanceRef bdcnt_bctr_4))
+              (portRef B0 (instanceRef bdcnt_bctr_4))
+              (portRef B1 (instanceRef bdcnt_bctr_5))
+              (portRef B0 (instanceRef bdcnt_bctr_5))))
+          (net precin
+            (joined
+              (portRef CIN (instanceRef wcnt_0))
+              (portRef COUT (instanceRef precin_inst299))))
+          (net wcnt_sub_1
+            (joined
+              (portRef S0 (instanceRef wcnt_1))
+              (portRef D (instanceRef FF_11))))
+          (net wcnt_sub_2
+            (joined
+              (portRef S1 (instanceRef wcnt_1))
+              (portRef D (instanceRef FF_10))))
+          (net rptr_2
+            (joined
+              (portRef B1 (instanceRef wcnt_1))
+              (portRef ADB5 (instanceRef pdp_ram_0_0_3))
+              (portRef ADB5 (instanceRef pdp_ram_0_1_2))
+              (portRef ADB5 (instanceRef pdp_ram_0_2_1))
+              (portRef ADB5 (instanceRef pdp_ram_0_3_0))
+              (portRef Q (instanceRef FF_22))))
+          (net rptr_1
+            (joined
+              (portRef B0 (instanceRef wcnt_1))
+              (portRef ADB4 (instanceRef pdp_ram_0_0_3))
+              (portRef ADB4 (instanceRef pdp_ram_0_1_2))
+              (portRef ADB4 (instanceRef pdp_ram_0_2_1))
+              (portRef ADB4 (instanceRef pdp_ram_0_3_0))
+              (portRef Q (instanceRef FF_23))))
+          (net wcount_2
+            (joined
+              (portRef A1 (instanceRef wcnt_1))
+              (portRef Q (instanceRef FF_58))
+              (portRef D (instanceRef FF_34))
+              (portRef A0 (instanceRef w_ctr_1))))
+          (net wcount_1
+            (joined
+              (portRef A0 (instanceRef wcnt_1))
+              (portRef Q (instanceRef FF_59))
+              (portRef D (instanceRef FF_35))
+              (portRef A1 (instanceRef w_ctr_0))))
+          (net co0_5
+            (joined
+              (portRef CIN (instanceRef wcnt_1))
+              (portRef COUT (instanceRef wcnt_0))))
+          (net wcnt_sub_3
+            (joined
+              (portRef S0 (instanceRef wcnt_2))
+              (portRef D (instanceRef FF_9))))
+          (net wcnt_sub_4
+            (joined
+              (portRef S1 (instanceRef wcnt_2))
+              (portRef D (instanceRef FF_8))))
+          (net rptr_4
+            (joined
+              (portRef B1 (instanceRef wcnt_2))
+              (portRef ADB7 (instanceRef pdp_ram_0_0_3))
+              (portRef ADB7 (instanceRef pdp_ram_0_1_2))
+              (portRef ADB7 (instanceRef pdp_ram_0_2_1))
+              (portRef ADB7 (instanceRef pdp_ram_0_3_0))
+              (portRef Q (instanceRef FF_20))))
+          (net rptr_3
+            (joined
+              (portRef B0 (instanceRef wcnt_2))
+              (portRef ADB6 (instanceRef pdp_ram_0_0_3))
+              (portRef ADB6 (instanceRef pdp_ram_0_1_2))
+              (portRef ADB6 (instanceRef pdp_ram_0_2_1))
+              (portRef ADB6 (instanceRef pdp_ram_0_3_0))
+              (portRef Q (instanceRef FF_21))))
+          (net wcount_4
+            (joined
+              (portRef A1 (instanceRef wcnt_2))
+              (portRef Q (instanceRef FF_56))
+              (portRef D (instanceRef FF_32))
+              (portRef A0 (instanceRef w_ctr_2))))
+          (net wcount_3
+            (joined
+              (portRef A0 (instanceRef wcnt_2))
+              (portRef Q (instanceRef FF_57))
+              (portRef D (instanceRef FF_33))
+              (portRef A1 (instanceRef w_ctr_1))))
+          (net co1_5
+            (joined
+              (portRef CIN (instanceRef wcnt_2))
+              (portRef COUT (instanceRef wcnt_1))))
+          (net wcnt_sub_5
+            (joined
+              (portRef S0 (instanceRef wcnt_3))
+              (portRef D (instanceRef FF_7))))
+          (net wcnt_sub_6
+            (joined
+              (portRef S1 (instanceRef wcnt_3))
+              (portRef D (instanceRef FF_6))))
+          (net rptr_6
+            (joined
+              (portRef B1 (instanceRef wcnt_3))
+              (portRef ADB9 (instanceRef pdp_ram_0_0_3))
+              (portRef ADB9 (instanceRef pdp_ram_0_1_2))
+              (portRef ADB9 (instanceRef pdp_ram_0_2_1))
+              (portRef ADB9 (instanceRef pdp_ram_0_3_0))
+              (portRef Q (instanceRef FF_18))))
+          (net rptr_5
+            (joined
+              (portRef B0 (instanceRef wcnt_3))
+              (portRef ADB8 (instanceRef pdp_ram_0_0_3))
+              (portRef ADB8 (instanceRef pdp_ram_0_1_2))
+              (portRef ADB8 (instanceRef pdp_ram_0_2_1))
+              (portRef ADB8 (instanceRef pdp_ram_0_3_0))
+              (portRef Q (instanceRef FF_19))))
+          (net wcount_6
+            (joined
+              (portRef A1 (instanceRef wcnt_3))
+              (portRef Q (instanceRef FF_54))
+              (portRef D (instanceRef FF_30))
+              (portRef A0 (instanceRef w_ctr_3))))
+          (net wcount_5
+            (joined
+              (portRef A0 (instanceRef wcnt_3))
+              (portRef Q (instanceRef FF_55))
+              (portRef D (instanceRef FF_31))
+              (portRef A1 (instanceRef w_ctr_2))))
+          (net co2_5
+            (joined
+              (portRef CIN (instanceRef wcnt_3))
+              (portRef COUT (instanceRef wcnt_2))))
+          (net wcnt_sub_7
+            (joined
+              (portRef S0 (instanceRef wcnt_4))
+              (portRef D (instanceRef FF_5))))
+          (net wcnt_sub_8
+            (joined
+              (portRef S1 (instanceRef wcnt_4))
+              (portRef D (instanceRef FF_4))))
+          (net rptr_8
+            (joined
+              (portRef B1 (instanceRef wcnt_4))
+              (portRef ADB11 (instanceRef pdp_ram_0_0_3))
+              (portRef ADB11 (instanceRef pdp_ram_0_1_2))
+              (portRef ADB11 (instanceRef pdp_ram_0_2_1))
+              (portRef ADB11 (instanceRef pdp_ram_0_3_0))
+              (portRef Q (instanceRef FF_16))))
+          (net rptr_7
+            (joined
+              (portRef B0 (instanceRef wcnt_4))
+              (portRef ADB10 (instanceRef pdp_ram_0_0_3))
+              (portRef ADB10 (instanceRef pdp_ram_0_1_2))
+              (portRef ADB10 (instanceRef pdp_ram_0_2_1))
+              (portRef ADB10 (instanceRef pdp_ram_0_3_0))
+              (portRef Q (instanceRef FF_17))))
+          (net wcount_8
+            (joined
+              (portRef A1 (instanceRef wcnt_4))
+              (portRef Q (instanceRef FF_52))
+              (portRef D (instanceRef FF_28))
+              (portRef A0 (instanceRef w_ctr_4))))
+          (net wcount_7
+            (joined
+              (portRef A0 (instanceRef wcnt_4))
+              (portRef Q (instanceRef FF_53))
+              (portRef D (instanceRef FF_29))
+              (portRef A1 (instanceRef w_ctr_3))))
+          (net co3_5
+            (joined
+              (portRef CIN (instanceRef wcnt_4))
+              (portRef COUT (instanceRef wcnt_3))))
+          (net wcnt_sub_9
+            (joined
+              (portRef S0 (instanceRef wcnt_5))
+              (portRef D (instanceRef FF_3))))
+          (net wcnt_sub_10
+            (joined
+              (portRef S1 (instanceRef wcnt_5))
+              (portRef D (instanceRef FF_2))))
+          (net rptr_10
+            (joined
+              (portRef B1 (instanceRef wcnt_5))
+              (portRef ADB13 (instanceRef pdp_ram_0_0_3))
+              (portRef ADB13 (instanceRef pdp_ram_0_1_2))
+              (portRef ADB13 (instanceRef pdp_ram_0_2_1))
+              (portRef ADB13 (instanceRef pdp_ram_0_3_0))
+              (portRef Q (instanceRef FF_14))))
+          (net rptr_9
+            (joined
+              (portRef B0 (instanceRef wcnt_5))
+              (portRef ADB12 (instanceRef pdp_ram_0_0_3))
+              (portRef ADB12 (instanceRef pdp_ram_0_1_2))
+              (portRef ADB12 (instanceRef pdp_ram_0_2_1))
+              (portRef ADB12 (instanceRef pdp_ram_0_3_0))
+              (portRef Q (instanceRef FF_15))))
+          (net wcount_10
+            (joined
+              (portRef A1 (instanceRef wcnt_5))
+              (portRef Q (instanceRef FF_50))
+              (portRef D (instanceRef FF_26))
+              (portRef A0 (instanceRef w_ctr_5))))
+          (net wcount_9
+            (joined
+              (portRef A0 (instanceRef wcnt_5))
+              (portRef Q (instanceRef FF_51))
+              (portRef D (instanceRef FF_27))
+              (portRef A1 (instanceRef w_ctr_4))))
+          (net co4_5
+            (joined
+              (portRef CIN (instanceRef wcnt_5))
+              (portRef COUT (instanceRef wcnt_4))))
+          (net wcnt_sub_11
+            (joined
+              (portRef S0 (instanceRef wcnt_6))
+              (portRef D (instanceRef FF_1))))
+          (net wcnt_sub_msb
+            (joined
+              (portRef A0 (instanceRef wcnt_6))
+              (portRef Z (instanceRef XOR2_t0))))
+          (net co5_3
+            (joined
+              (portRef CIN (instanceRef wcnt_6))
+              (portRef COUT (instanceRef wcnt_5))))
+          (net wren_i
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_ci_a))
+              (portRef Z (instanceRef AND2_t5))
+              (portRef A (instanceRef AND2_t3))
+              (portRef A (instanceRef XOR2_t2))
+              (portRef A (instanceRef INV_2))
+              (portRef AD1 (instanceRef LUT4_1))
+              (portRef A (instanceRef INV_1))
+              (portRef OCEA (instanceRef pdp_ram_0_0_3))
+              (portRef CEA (instanceRef pdp_ram_0_0_3))
+              (portRef OCEA (instanceRef pdp_ram_0_1_2))
+              (portRef CEA (instanceRef pdp_ram_0_1_2))
+              (portRef OCEA (instanceRef pdp_ram_0_2_1))
+              (portRef CEA (instanceRef pdp_ram_0_2_1))
+              (portRef OCEA (instanceRef pdp_ram_0_3_0))
+              (portRef CEA (instanceRef pdp_ram_0_3_0))
+              (portRef SP (instanceRef FF_60))
+              (portRef SP (instanceRef FF_59))
+              (portRef SP (instanceRef FF_58))
+              (portRef SP (instanceRef FF_57))
+              (portRef SP (instanceRef FF_56))
+              (portRef SP (instanceRef FF_55))
+              (portRef SP (instanceRef FF_54))
+              (portRef SP (instanceRef FF_53))
+              (portRef SP (instanceRef FF_52))
+              (portRef SP (instanceRef FF_51))
+              (portRef SP (instanceRef FF_50))
+              (portRef SP (instanceRef FF_49))
+              (portRef SP (instanceRef FF_36))
+              (portRef SP (instanceRef FF_35))
+              (portRef SP (instanceRef FF_34))
+              (portRef SP (instanceRef FF_33))
+              (portRef SP (instanceRef FF_32))
+              (portRef SP (instanceRef FF_31))
+              (portRef SP (instanceRef FF_30))
+              (portRef SP (instanceRef FF_29))
+              (portRef SP (instanceRef FF_28))
+              (portRef SP (instanceRef FF_27))
+              (portRef SP (instanceRef FF_26))
+              (portRef SP (instanceRef FF_25))
+              (portRef B0 (instanceRef g_cmp_0))
+              (portRef B1 (instanceRef g_cmp_0))
+              (portRef B0 (instanceRef g_cmp_1))
+              (portRef B1 (instanceRef g_cmp_1))
+              (portRef B0 (instanceRef g_cmp_2))
+              (portRef B1 (instanceRef g_cmp_2))
+              (portRef B0 (instanceRef g_cmp_3))
+              (portRef B1 (instanceRef g_cmp_3))
+              (portRef B0 (instanceRef g_cmp_4))
+              (portRef B1 (instanceRef g_cmp_4))
+              (portRef B0 (instanceRef g_cmp_5))
+              (portRef B1 (instanceRef af_set_cmp_ci_a))))
+          (net x
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_ci_a))
+              (portRef CIN (instanceRef bdcnt_bctr_cia))
+              (portRef CIN (instanceRef e_cmp_ci_a))
+              (portRef CIN (instanceRef g_cmp_ci_a))
+              (portRef CIN (instanceRef w_ctr_cia))
+              (portRef CIN (instanceRef r_ctr_cia))
+              (portRef CIN (instanceRef precin_inst299))))
+          (net cmp_ci_2
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_0))
+              (portRef COUT (instanceRef af_set_cmp_ci_a))))
+          (net wcnt_reg_0
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_0))
+              (portRef Q (instanceRef FF_12))))
+          (net wcnt_reg_1
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_0))
+              (portRef Q (instanceRef FF_11))))
+          (net co0_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_1))
+              (portRef COUT (instanceRef af_set_cmp_0))))
+          (net wcnt_reg_2
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_1))
+              (portRef Q (instanceRef FF_10))))
+          (net wcnt_reg_3
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_1))
+              (portRef Q (instanceRef FF_9))))
+          (net co1_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_2))
+              (portRef COUT (instanceRef af_set_cmp_1))))
+          (net wcnt_reg_4
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_2))
+              (portRef Q (instanceRef FF_8))))
+          (net wcnt_reg_5
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_2))
+              (portRef Q (instanceRef FF_7))))
+          (net co2_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_3))
+              (portRef COUT (instanceRef af_set_cmp_2))))
+          (net wcnt_reg_6
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_3))
+              (portRef Q (instanceRef FF_6))))
+          (net wcnt_reg_7
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_3))
+              (portRef Q (instanceRef FF_5))))
+          (net co3_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_4))
+              (portRef COUT (instanceRef af_set_cmp_3))))
+          (net wcnt_reg_8
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_4))
+              (portRef Q (instanceRef FF_4))))
+          (net wcnt_reg_9
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_4))
+              (portRef Q (instanceRef FF_3))))
+          (net co4_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_5))
+              (portRef COUT (instanceRef af_set_cmp_4))))
+          (net wcnt_reg_10
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_5))
+              (portRef Q (instanceRef FF_2))))
+          (net wcnt_reg_11
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_5))
+              (portRef Q (instanceRef FF_1))))
+          (net af_set
+            (joined
+              (portRef S0 (instanceRef a2))
+              (portRef D (instanceRef FF_0))))
+          (net scuba_vhi
+            (joined
+              (portRef Z (instanceRef scuba_vhi_inst))
+              (portRef OCEB (instanceRef pdp_ram_0_0_3))
+              (portRef WEA (instanceRef pdp_ram_0_0_3))
+              (portRef OCEB (instanceRef pdp_ram_0_1_2))
+              (portRef WEA (instanceRef pdp_ram_0_1_2))
+              (portRef OCEB (instanceRef pdp_ram_0_2_1))
+              (portRef WEA (instanceRef pdp_ram_0_2_1))
+              (portRef OCEB (instanceRef pdp_ram_0_3_0))
+              (portRef WEA (instanceRef pdp_ram_0_3_0))
+              (portRef C1 (instanceRef bdcnt_bctr_cia))
+              (portRef C0 (instanceRef bdcnt_bctr_cia))
+              (portRef D1 (instanceRef bdcnt_bctr_cia))
+              (portRef D0 (instanceRef bdcnt_bctr_cia))
+              (portRef D1 (instanceRef bdcnt_bctr_0))
+              (portRef D0 (instanceRef bdcnt_bctr_0))
+              (portRef C1 (instanceRef bdcnt_bctr_0))
+              (portRef C0 (instanceRef bdcnt_bctr_0))
+              (portRef D1 (instanceRef bdcnt_bctr_1))
+              (portRef D0 (instanceRef bdcnt_bctr_1))
+              (portRef C1 (instanceRef bdcnt_bctr_1))
+              (portRef C0 (instanceRef bdcnt_bctr_1))
+              (portRef D1 (instanceRef bdcnt_bctr_2))
+              (portRef D0 (instanceRef bdcnt_bctr_2))
+              (portRef C1 (instanceRef bdcnt_bctr_2))
+              (portRef C0 (instanceRef bdcnt_bctr_2))
+              (portRef D1 (instanceRef bdcnt_bctr_3))
+              (portRef D0 (instanceRef bdcnt_bctr_3))
+              (portRef C1 (instanceRef bdcnt_bctr_3))
+              (portRef C0 (instanceRef bdcnt_bctr_3))
+              (portRef D1 (instanceRef bdcnt_bctr_4))
+              (portRef D0 (instanceRef bdcnt_bctr_4))
+              (portRef C1 (instanceRef bdcnt_bctr_4))
+              (portRef C0 (instanceRef bdcnt_bctr_4))
+              (portRef D1 (instanceRef bdcnt_bctr_5))
+              (portRef D0 (instanceRef bdcnt_bctr_5))
+              (portRef C1 (instanceRef bdcnt_bctr_5))
+              (portRef C0 (instanceRef bdcnt_bctr_5))
+              (portRef C1 (instanceRef e_cmp_ci_a))
+              (portRef C0 (instanceRef e_cmp_ci_a))
+              (portRef D1 (instanceRef e_cmp_ci_a))
+              (portRef D0 (instanceRef e_cmp_ci_a))
+              (portRef B1 (instanceRef e_cmp_ci_a))
+              (portRef B0 (instanceRef e_cmp_ci_a))
+              (portRef A1 (instanceRef e_cmp_ci_a))
+              (portRef A0 (instanceRef e_cmp_ci_a))
+              (portRef D1 (instanceRef e_cmp_0))
+              (portRef D0 (instanceRef e_cmp_0))
+              (portRef C1 (instanceRef e_cmp_0))
+              (portRef C0 (instanceRef e_cmp_0))
+              (portRef D1 (instanceRef e_cmp_1))
+              (portRef D0 (instanceRef e_cmp_1))
+              (portRef C1 (instanceRef e_cmp_1))
+              (portRef C0 (instanceRef e_cmp_1))
+              (portRef D1 (instanceRef e_cmp_2))
+              (portRef D0 (instanceRef e_cmp_2))
+              (portRef C1 (instanceRef e_cmp_2))
+              (portRef C0 (instanceRef e_cmp_2))
+              (portRef D1 (instanceRef e_cmp_3))
+              (portRef D0 (instanceRef e_cmp_3))
+              (portRef C1 (instanceRef e_cmp_3))
+              (portRef C0 (instanceRef e_cmp_3))
+              (portRef D1 (instanceRef e_cmp_4))
+              (portRef D0 (instanceRef e_cmp_4))
+              (portRef C1 (instanceRef e_cmp_4))
+              (portRef C0 (instanceRef e_cmp_4))
+              (portRef D1 (instanceRef e_cmp_5))
+              (portRef D0 (instanceRef e_cmp_5))
+              (portRef C1 (instanceRef e_cmp_5))
+              (portRef C0 (instanceRef e_cmp_5))
+              (portRef C1 (instanceRef a0))
+              (portRef C0 (instanceRef a0))
+              (portRef D1 (instanceRef a0))
+              (portRef D0 (instanceRef a0))
+              (portRef C1 (instanceRef g_cmp_ci_a))
+              (portRef C0 (instanceRef g_cmp_ci_a))
+              (portRef D1 (instanceRef g_cmp_ci_a))
+              (portRef D0 (instanceRef g_cmp_ci_a))
+              (portRef B1 (instanceRef g_cmp_ci_a))
+              (portRef B0 (instanceRef g_cmp_ci_a))
+              (portRef A1 (instanceRef g_cmp_ci_a))
+              (portRef A0 (instanceRef g_cmp_ci_a))
+              (portRef D1 (instanceRef g_cmp_0))
+              (portRef D0 (instanceRef g_cmp_0))
+              (portRef C1 (instanceRef g_cmp_0))
+              (portRef C0 (instanceRef g_cmp_0))
+              (portRef D1 (instanceRef g_cmp_1))
+              (portRef D0 (instanceRef g_cmp_1))
+              (portRef C1 (instanceRef g_cmp_1))
+              (portRef C0 (instanceRef g_cmp_1))
+              (portRef D1 (instanceRef g_cmp_2))
+              (portRef D0 (instanceRef g_cmp_2))
+              (portRef C1 (instanceRef g_cmp_2))
+              (portRef C0 (instanceRef g_cmp_2))
+              (portRef D1 (instanceRef g_cmp_3))
+              (portRef D0 (instanceRef g_cmp_3))
+              (portRef C1 (instanceRef g_cmp_3))
+              (portRef C0 (instanceRef g_cmp_3))
+              (portRef D1 (instanceRef g_cmp_4))
+              (portRef D0 (instanceRef g_cmp_4))
+              (portRef C1 (instanceRef g_cmp_4))
+              (portRef C0 (instanceRef g_cmp_4))
+              (portRef D1 (instanceRef g_cmp_5))
+              (portRef D0 (instanceRef g_cmp_5))
+              (portRef C1 (instanceRef g_cmp_5))
+              (portRef C0 (instanceRef g_cmp_5))
+              (portRef C1 (instanceRef a1))
+              (portRef C0 (instanceRef a1))
+              (portRef D1 (instanceRef a1))
+              (portRef D0 (instanceRef a1))
+              (portRef C1 (instanceRef w_ctr_cia))
+              (portRef C0 (instanceRef w_ctr_cia))
+              (portRef D1 (instanceRef w_ctr_cia))
+              (portRef D0 (instanceRef w_ctr_cia))
+              (portRef B1 (instanceRef w_ctr_cia))
+              (portRef A1 (instanceRef w_ctr_cia))
+              (portRef D1 (instanceRef w_ctr_0))
+              (portRef D0 (instanceRef w_ctr_0))
+              (portRef C1 (instanceRef w_ctr_0))
+              (portRef C0 (instanceRef w_ctr_0))
+              (portRef D1 (instanceRef w_ctr_1))
+              (portRef D0 (instanceRef w_ctr_1))
+              (portRef C1 (instanceRef w_ctr_1))
+              (portRef C0 (instanceRef w_ctr_1))
+              (portRef D1 (instanceRef w_ctr_2))
+              (portRef D0 (instanceRef w_ctr_2))
+              (portRef C1 (instanceRef w_ctr_2))
+              (portRef C0 (instanceRef w_ctr_2))
+              (portRef D1 (instanceRef w_ctr_3))
+              (portRef D0 (instanceRef w_ctr_3))
+              (portRef C1 (instanceRef w_ctr_3))
+              (portRef C0 (instanceRef w_ctr_3))
+              (portRef D1 (instanceRef w_ctr_4))
+              (portRef D0 (instanceRef w_ctr_4))
+              (portRef C1 (instanceRef w_ctr_4))
+              (portRef C0 (instanceRef w_ctr_4))
+              (portRef D1 (instanceRef w_ctr_5))
+              (portRef D0 (instanceRef w_ctr_5))
+              (portRef C1 (instanceRef w_ctr_5))
+              (portRef C0 (instanceRef w_ctr_5))
+              (portRef C1 (instanceRef r_ctr_cia))
+              (portRef C0 (instanceRef r_ctr_cia))
+              (portRef D1 (instanceRef r_ctr_cia))
+              (portRef D0 (instanceRef r_ctr_cia))
+              (portRef B1 (instanceRef r_ctr_cia))
+              (portRef A1 (instanceRef r_ctr_cia))
+              (portRef D1 (instanceRef r_ctr_0))
+              (portRef D0 (instanceRef r_ctr_0))
+              (portRef C1 (instanceRef r_ctr_0))
+              (portRef C0 (instanceRef r_ctr_0))
+              (portRef D1 (instanceRef r_ctr_1))
+              (portRef D0 (instanceRef r_ctr_1))
+              (portRef C1 (instanceRef r_ctr_1))
+              (portRef C0 (instanceRef r_ctr_1))
+              (portRef D1 (instanceRef r_ctr_2))
+              (portRef D0 (instanceRef r_ctr_2))
+              (portRef C1 (instanceRef r_ctr_2))
+              (portRef C0 (instanceRef r_ctr_2))
+              (portRef D1 (instanceRef r_ctr_3))
+              (portRef D0 (instanceRef r_ctr_3))
+              (portRef C1 (instanceRef r_ctr_3))
+              (portRef C0 (instanceRef r_ctr_3))
+              (portRef D1 (instanceRef r_ctr_4))
+              (portRef D0 (instanceRef r_ctr_4))
+              (portRef C1 (instanceRef r_ctr_4))
+              (portRef C0 (instanceRef r_ctr_4))
+              (portRef D1 (instanceRef r_ctr_5))
+              (portRef D0 (instanceRef r_ctr_5))
+              (portRef C1 (instanceRef r_ctr_5))
+              (portRef C0 (instanceRef r_ctr_5))
+              (portRef C1 (instanceRef precin_inst299))
+              (portRef C0 (instanceRef precin_inst299))
+              (portRef D1 (instanceRef precin_inst299))
+              (portRef D0 (instanceRef precin_inst299))
+              (portRef B1 (instanceRef precin_inst299))
+              (portRef B0 (instanceRef precin_inst299))
+              (portRef A1 (instanceRef precin_inst299))
+              (portRef A0 (instanceRef precin_inst299))
+              (portRef C1 (instanceRef wcnt_0))
+              (portRef C0 (instanceRef wcnt_0))
+              (portRef D1 (instanceRef wcnt_0))
+              (portRef D0 (instanceRef wcnt_0))
+              (portRef C1 (instanceRef wcnt_1))
+              (portRef C0 (instanceRef wcnt_1))
+              (portRef D1 (instanceRef wcnt_1))
+              (portRef D0 (instanceRef wcnt_1))
+              (portRef C1 (instanceRef wcnt_2))
+              (portRef C0 (instanceRef wcnt_2))
+              (portRef D1 (instanceRef wcnt_2))
+              (portRef D0 (instanceRef wcnt_2))
+              (portRef C1 (instanceRef wcnt_3))
+              (portRef C0 (instanceRef wcnt_3))
+              (portRef D1 (instanceRef wcnt_3))
+              (portRef D0 (instanceRef wcnt_3))
+              (portRef C1 (instanceRef wcnt_4))
+              (portRef C0 (instanceRef wcnt_4))
+              (portRef D1 (instanceRef wcnt_4))
+              (portRef D0 (instanceRef wcnt_4))
+              (portRef C1 (instanceRef wcnt_5))
+              (portRef C0 (instanceRef wcnt_5))
+              (portRef D1 (instanceRef wcnt_5))
+              (portRef D0 (instanceRef wcnt_5))
+              (portRef C1 (instanceRef wcnt_6))
+              (portRef C0 (instanceRef wcnt_6))
+              (portRef D1 (instanceRef wcnt_6))
+              (portRef D0 (instanceRef wcnt_6))
+              (portRef C1 (instanceRef af_set_cmp_ci_a))
+              (portRef C0 (instanceRef af_set_cmp_ci_a))
+              (portRef D1 (instanceRef af_set_cmp_ci_a))
+              (portRef D0 (instanceRef af_set_cmp_ci_a))
+              (portRef D1 (instanceRef af_set_cmp_0))
+              (portRef D0 (instanceRef af_set_cmp_0))
+              (portRef C1 (instanceRef af_set_cmp_0))
+              (portRef C0 (instanceRef af_set_cmp_0))
+              (portRef D1 (instanceRef af_set_cmp_1))
+              (portRef D0 (instanceRef af_set_cmp_1))
+              (portRef C1 (instanceRef af_set_cmp_1))
+              (portRef C0 (instanceRef af_set_cmp_1))
+              (portRef D1 (instanceRef af_set_cmp_2))
+              (portRef D0 (instanceRef af_set_cmp_2))
+              (portRef C1 (instanceRef af_set_cmp_2))
+              (portRef C0 (instanceRef af_set_cmp_2))
+              (portRef D1 (instanceRef af_set_cmp_3))
+              (portRef D0 (instanceRef af_set_cmp_3))
+              (portRef C1 (instanceRef af_set_cmp_3))
+              (portRef C0 (instanceRef af_set_cmp_3))
+              (portRef D1 (instanceRef af_set_cmp_4))
+              (portRef D0 (instanceRef af_set_cmp_4))
+              (portRef C1 (instanceRef af_set_cmp_4))
+              (portRef C0 (instanceRef af_set_cmp_4))
+              (portRef D1 (instanceRef af_set_cmp_5))
+              (portRef D0 (instanceRef af_set_cmp_5))
+              (portRef C1 (instanceRef af_set_cmp_5))
+              (portRef C0 (instanceRef af_set_cmp_5))
+              (portRef C1 (instanceRef a2))
+              (portRef C0 (instanceRef a2))
+              (portRef D1 (instanceRef a2))
+              (portRef D0 (instanceRef a2))))
+          (net scuba_vlo
+            (joined
+              (portRef Z (instanceRef scuba_vlo_inst))
+              (portRef AD3 (instanceRef LUT4_1))
+              (portRef AD3 (instanceRef LUT4_0))
+              (portRef CSB2 (instanceRef pdp_ram_0_0_3))
+              (portRef CSA2 (instanceRef pdp_ram_0_0_3))
+              (portRef CSB1 (instanceRef pdp_ram_0_0_3))
+              (portRef CSA1 (instanceRef pdp_ram_0_0_3))
+              (portRef CSB0 (instanceRef pdp_ram_0_0_3))
+              (portRef CSA0 (instanceRef pdp_ram_0_0_3))
+              (portRef WEB (instanceRef pdp_ram_0_0_3))
+              (portRef ADB2 (instanceRef pdp_ram_0_0_3))
+              (portRef ADA2 (instanceRef pdp_ram_0_0_3))
+              (portRef ADB1 (instanceRef pdp_ram_0_0_3))
+              (portRef ADA1 (instanceRef pdp_ram_0_0_3))
+              (portRef ADB0 (instanceRef pdp_ram_0_0_3))
+              (portRef ADA0 (instanceRef pdp_ram_0_0_3))
+              (portRef DIB17 (instanceRef pdp_ram_0_0_3))
+              (portRef DIA17 (instanceRef pdp_ram_0_0_3))
+              (portRef DIB16 (instanceRef pdp_ram_0_0_3))
+              (portRef DIA16 (instanceRef pdp_ram_0_0_3))
+              (portRef DIB15 (instanceRef pdp_ram_0_0_3))
+              (portRef DIA15 (instanceRef pdp_ram_0_0_3))
+              (portRef DIB14 (instanceRef pdp_ram_0_0_3))
+              (portRef DIA14 (instanceRef pdp_ram_0_0_3))
+              (portRef DIB13 (instanceRef pdp_ram_0_0_3))
+              (portRef DIA13 (instanceRef pdp_ram_0_0_3))
+              (portRef DIB12 (instanceRef pdp_ram_0_0_3))
+              (portRef DIA12 (instanceRef pdp_ram_0_0_3))
+              (portRef DIB11 (instanceRef pdp_ram_0_0_3))
+              (portRef DIA11 (instanceRef pdp_ram_0_0_3))
+              (portRef DIB10 (instanceRef pdp_ram_0_0_3))
+              (portRef DIA10 (instanceRef pdp_ram_0_0_3))
+              (portRef DIB9 (instanceRef pdp_ram_0_0_3))
+              (portRef DIA9 (instanceRef pdp_ram_0_0_3))
+              (portRef DIB8 (instanceRef pdp_ram_0_0_3))
+              (portRef DIB7 (instanceRef pdp_ram_0_0_3))
+              (portRef DIB6 (instanceRef pdp_ram_0_0_3))
+              (portRef DIB5 (instanceRef pdp_ram_0_0_3))
+              (portRef DIB4 (instanceRef pdp_ram_0_0_3))
+              (portRef DIB3 (instanceRef pdp_ram_0_0_3))
+              (portRef DIB2 (instanceRef pdp_ram_0_0_3))
+              (portRef DIB1 (instanceRef pdp_ram_0_0_3))
+              (portRef DIB0 (instanceRef pdp_ram_0_0_3))
+              (portRef CSB2 (instanceRef pdp_ram_0_1_2))
+              (portRef CSA2 (instanceRef pdp_ram_0_1_2))
+              (portRef CSB1 (instanceRef pdp_ram_0_1_2))
+              (portRef CSA1 (instanceRef pdp_ram_0_1_2))
+              (portRef CSB0 (instanceRef pdp_ram_0_1_2))
+              (portRef CSA0 (instanceRef pdp_ram_0_1_2))
+              (portRef WEB (instanceRef pdp_ram_0_1_2))
+              (portRef ADB2 (instanceRef pdp_ram_0_1_2))
+              (portRef ADA2 (instanceRef pdp_ram_0_1_2))
+              (portRef ADB1 (instanceRef pdp_ram_0_1_2))
+              (portRef ADA1 (instanceRef pdp_ram_0_1_2))
+              (portRef ADB0 (instanceRef pdp_ram_0_1_2))
+              (portRef ADA0 (instanceRef pdp_ram_0_1_2))
+              (portRef DIB17 (instanceRef pdp_ram_0_1_2))
+              (portRef DIA17 (instanceRef pdp_ram_0_1_2))
+              (portRef DIB16 (instanceRef pdp_ram_0_1_2))
+              (portRef DIA16 (instanceRef pdp_ram_0_1_2))
+              (portRef DIB15 (instanceRef pdp_ram_0_1_2))
+              (portRef DIA15 (instanceRef pdp_ram_0_1_2))
+              (portRef DIB14 (instanceRef pdp_ram_0_1_2))
+              (portRef DIA14 (instanceRef pdp_ram_0_1_2))
+              (portRef DIB13 (instanceRef pdp_ram_0_1_2))
+              (portRef DIA13 (instanceRef pdp_ram_0_1_2))
+              (portRef DIB12 (instanceRef pdp_ram_0_1_2))
+              (portRef DIA12 (instanceRef pdp_ram_0_1_2))
+              (portRef DIB11 (instanceRef pdp_ram_0_1_2))
+              (portRef DIA11 (instanceRef pdp_ram_0_1_2))
+              (portRef DIB10 (instanceRef pdp_ram_0_1_2))
+              (portRef DIA10 (instanceRef pdp_ram_0_1_2))
+              (portRef DIB9 (instanceRef pdp_ram_0_1_2))
+              (portRef DIA9 (instanceRef pdp_ram_0_1_2))
+              (portRef DIB8 (instanceRef pdp_ram_0_1_2))
+              (portRef DIB7 (instanceRef pdp_ram_0_1_2))
+              (portRef DIB6 (instanceRef pdp_ram_0_1_2))
+              (portRef DIB5 (instanceRef pdp_ram_0_1_2))
+              (portRef DIB4 (instanceRef pdp_ram_0_1_2))
+              (portRef DIB3 (instanceRef pdp_ram_0_1_2))
+              (portRef DIB2 (instanceRef pdp_ram_0_1_2))
+              (portRef DIB1 (instanceRef pdp_ram_0_1_2))
+              (portRef DIB0 (instanceRef pdp_ram_0_1_2))
+              (portRef CSB2 (instanceRef pdp_ram_0_2_1))
+              (portRef CSA2 (instanceRef pdp_ram_0_2_1))
+              (portRef CSB1 (instanceRef pdp_ram_0_2_1))
+              (portRef CSA1 (instanceRef pdp_ram_0_2_1))
+              (portRef CSB0 (instanceRef pdp_ram_0_2_1))
+              (portRef CSA0 (instanceRef pdp_ram_0_2_1))
+              (portRef WEB (instanceRef pdp_ram_0_2_1))
+              (portRef ADB2 (instanceRef pdp_ram_0_2_1))
+              (portRef ADA2 (instanceRef pdp_ram_0_2_1))
+              (portRef ADB1 (instanceRef pdp_ram_0_2_1))
+              (portRef ADA1 (instanceRef pdp_ram_0_2_1))
+              (portRef ADB0 (instanceRef pdp_ram_0_2_1))
+              (portRef ADA0 (instanceRef pdp_ram_0_2_1))
+              (portRef DIB17 (instanceRef pdp_ram_0_2_1))
+              (portRef DIA17 (instanceRef pdp_ram_0_2_1))
+              (portRef DIB16 (instanceRef pdp_ram_0_2_1))
+              (portRef DIA16 (instanceRef pdp_ram_0_2_1))
+              (portRef DIB15 (instanceRef pdp_ram_0_2_1))
+              (portRef DIA15 (instanceRef pdp_ram_0_2_1))
+              (portRef DIB14 (instanceRef pdp_ram_0_2_1))
+              (portRef DIA14 (instanceRef pdp_ram_0_2_1))
+              (portRef DIB13 (instanceRef pdp_ram_0_2_1))
+              (portRef DIA13 (instanceRef pdp_ram_0_2_1))
+              (portRef DIB12 (instanceRef pdp_ram_0_2_1))
+              (portRef DIA12 (instanceRef pdp_ram_0_2_1))
+              (portRef DIB11 (instanceRef pdp_ram_0_2_1))
+              (portRef DIA11 (instanceRef pdp_ram_0_2_1))
+              (portRef DIB10 (instanceRef pdp_ram_0_2_1))
+              (portRef DIA10 (instanceRef pdp_ram_0_2_1))
+              (portRef DIB9 (instanceRef pdp_ram_0_2_1))
+              (portRef DIA9 (instanceRef pdp_ram_0_2_1))
+              (portRef DIB8 (instanceRef pdp_ram_0_2_1))
+              (portRef DIB7 (instanceRef pdp_ram_0_2_1))
+              (portRef DIB6 (instanceRef pdp_ram_0_2_1))
+              (portRef DIB5 (instanceRef pdp_ram_0_2_1))
+              (portRef DIB4 (instanceRef pdp_ram_0_2_1))
+              (portRef DIB3 (instanceRef pdp_ram_0_2_1))
+              (portRef DIB2 (instanceRef pdp_ram_0_2_1))
+              (portRef DIB1 (instanceRef pdp_ram_0_2_1))
+              (portRef DIB0 (instanceRef pdp_ram_0_2_1))
+              (portRef CSB2 (instanceRef pdp_ram_0_3_0))
+              (portRef CSA2 (instanceRef pdp_ram_0_3_0))
+              (portRef CSB1 (instanceRef pdp_ram_0_3_0))
+              (portRef CSA1 (instanceRef pdp_ram_0_3_0))
+              (portRef CSB0 (instanceRef pdp_ram_0_3_0))
+              (portRef CSA0 (instanceRef pdp_ram_0_3_0))
+              (portRef WEB (instanceRef pdp_ram_0_3_0))
+              (portRef ADB2 (instanceRef pdp_ram_0_3_0))
+              (portRef ADA2 (instanceRef pdp_ram_0_3_0))
+              (portRef ADB1 (instanceRef pdp_ram_0_3_0))
+              (portRef ADA1 (instanceRef pdp_ram_0_3_0))
+              (portRef ADB0 (instanceRef pdp_ram_0_3_0))
+              (portRef ADA0 (instanceRef pdp_ram_0_3_0))
+              (portRef DIB17 (instanceRef pdp_ram_0_3_0))
+              (portRef DIA17 (instanceRef pdp_ram_0_3_0))
+              (portRef DIB16 (instanceRef pdp_ram_0_3_0))
+              (portRef DIA16 (instanceRef pdp_ram_0_3_0))
+              (portRef DIB15 (instanceRef pdp_ram_0_3_0))
+              (portRef DIA15 (instanceRef pdp_ram_0_3_0))
+              (portRef DIB14 (instanceRef pdp_ram_0_3_0))
+              (portRef DIA14 (instanceRef pdp_ram_0_3_0))
+              (portRef DIB13 (instanceRef pdp_ram_0_3_0))
+              (portRef DIA13 (instanceRef pdp_ram_0_3_0))
+              (portRef DIB12 (instanceRef pdp_ram_0_3_0))
+              (portRef DIA12 (instanceRef pdp_ram_0_3_0))
+              (portRef DIB11 (instanceRef pdp_ram_0_3_0))
+              (portRef DIA11 (instanceRef pdp_ram_0_3_0))
+              (portRef DIB10 (instanceRef pdp_ram_0_3_0))
+              (portRef DIA10 (instanceRef pdp_ram_0_3_0))
+              (portRef DIB9 (instanceRef pdp_ram_0_3_0))
+              (portRef DIA9 (instanceRef pdp_ram_0_3_0))
+              (portRef DIB8 (instanceRef pdp_ram_0_3_0))
+              (portRef DIB7 (instanceRef pdp_ram_0_3_0))
+              (portRef DIB6 (instanceRef pdp_ram_0_3_0))
+              (portRef DIB5 (instanceRef pdp_ram_0_3_0))
+              (portRef DIB4 (instanceRef pdp_ram_0_3_0))
+              (portRef DIB3 (instanceRef pdp_ram_0_3_0))
+              (portRef DIB2 (instanceRef pdp_ram_0_3_0))
+              (portRef DIB1 (instanceRef pdp_ram_0_3_0))
+              (portRef DIB0 (instanceRef pdp_ram_0_3_0))
+              (portRef B0 (instanceRef bdcnt_bctr_cia))
+              (portRef A0 (instanceRef bdcnt_bctr_cia))
+              (portRef A1 (instanceRef e_cmp_0))
+              (portRef A0 (instanceRef e_cmp_1))
+              (portRef A1 (instanceRef e_cmp_1))
+              (portRef A0 (instanceRef e_cmp_2))
+              (portRef A1 (instanceRef e_cmp_2))
+              (portRef A0 (instanceRef e_cmp_3))
+              (portRef A1 (instanceRef e_cmp_3))
+              (portRef A0 (instanceRef e_cmp_4))
+              (portRef A1 (instanceRef e_cmp_4))
+              (portRef A0 (instanceRef e_cmp_5))
+              (portRef A1 (instanceRef e_cmp_5))
+              (portRef B1 (instanceRef a0))
+              (portRef B0 (instanceRef a0))
+              (portRef A1 (instanceRef a0))
+              (portRef A0 (instanceRef a0))
+              (portRef B1 (instanceRef a1))
+              (portRef B0 (instanceRef a1))
+              (portRef A1 (instanceRef a1))
+              (portRef A0 (instanceRef a1))
+              (portRef B0 (instanceRef w_ctr_cia))
+              (portRef A0 (instanceRef w_ctr_cia))
+              (portRef B1 (instanceRef w_ctr_0))
+              (portRef B0 (instanceRef w_ctr_0))
+              (portRef B1 (instanceRef w_ctr_1))
+              (portRef B0 (instanceRef w_ctr_1))
+              (portRef B1 (instanceRef w_ctr_2))
+              (portRef B0 (instanceRef w_ctr_2))
+              (portRef B1 (instanceRef w_ctr_3))
+              (portRef B0 (instanceRef w_ctr_3))
+              (portRef B1 (instanceRef w_ctr_4))
+              (portRef B0 (instanceRef w_ctr_4))
+              (portRef B1 (instanceRef w_ctr_5))
+              (portRef B0 (instanceRef w_ctr_5))
+              (portRef B0 (instanceRef r_ctr_cia))
+              (portRef A0 (instanceRef r_ctr_cia))
+              (portRef B1 (instanceRef r_ctr_0))
+              (portRef B0 (instanceRef r_ctr_0))
+              (portRef B1 (instanceRef r_ctr_1))
+              (portRef B0 (instanceRef r_ctr_1))
+              (portRef B1 (instanceRef r_ctr_2))
+              (portRef B0 (instanceRef r_ctr_2))
+              (portRef B1 (instanceRef r_ctr_3))
+              (portRef B0 (instanceRef r_ctr_3))
+              (portRef B1 (instanceRef r_ctr_4))
+              (portRef B0 (instanceRef r_ctr_4))
+              (portRef B1 (instanceRef r_ctr_5))
+              (portRef B0 (instanceRef r_ctr_5))
+              (portRef B1 (instanceRef wcnt_6))
+              (portRef B0 (instanceRef wcnt_6))
+              (portRef A1 (instanceRef wcnt_6))
+              (portRef B0 (instanceRef af_set_cmp_ci_a))
+              (portRef A0 (instanceRef af_set_cmp_ci_a))
+              (portRef B1 (instanceRef af_set_cmp_5))
+              (portRef B1 (instanceRef a2))
+              (portRef B0 (instanceRef a2))
+              (portRef A1 (instanceRef a2))
+              (portRef A0 (instanceRef a2))))
+          (net af_set_c
+            (joined
+              (portRef CIN (instanceRef a2))
+              (portRef COUT (instanceRef af_set_cmp_5))))
+          (net partial_full
+            (joined
+              (portRef AlmostFull)
+              (portRef Q (instanceRef FF_0))))
+          (net Full
+            (joined
+              (portRef Full)
+              (portRef Q (instanceRef FF_61))
+              (portRef A (instanceRef INV_5))
+              (portRef AD0 (instanceRef LUT4_0))))
+          (net Empty
+            (joined
+              (portRef Empty)
+              (portRef Q (instanceRef FF_62))
+              (portRef A (instanceRef INV_4))
+              (portRef AD0 (instanceRef LUT4_1))))
+          (net WCNT11
+            (joined
+              (portRef (member WCNT 0))
+              (portRef A1 (instanceRef g_cmp_5))
+              (portRef Q (instanceRef FF_63))
+              (portRef A1 (instanceRef bdcnt_bctr_5))
+              (portRef B1 (instanceRef e_cmp_5))))
+          (net WCNT10
+            (joined
+              (portRef (member WCNT 1))
+              (portRef A0 (instanceRef g_cmp_5))
+              (portRef Q (instanceRef FF_64))
+              (portRef A0 (instanceRef bdcnt_bctr_5))
+              (portRef B0 (instanceRef e_cmp_5))))
+          (net WCNT9
+            (joined
+              (portRef (member WCNT 2))
+              (portRef A1 (instanceRef g_cmp_4))
+              (portRef Q (instanceRef FF_65))
+              (portRef A1 (instanceRef bdcnt_bctr_4))
+              (portRef B1 (instanceRef e_cmp_4))))
+          (net WCNT8
+            (joined
+              (portRef (member WCNT 3))
+              (portRef A0 (instanceRef g_cmp_4))
+              (portRef Q (instanceRef FF_66))
+              (portRef A0 (instanceRef bdcnt_bctr_4))
+              (portRef B0 (instanceRef e_cmp_4))))
+          (net WCNT7
+            (joined
+              (portRef (member WCNT 4))
+              (portRef A1 (instanceRef g_cmp_3))
+              (portRef Q (instanceRef FF_67))
+              (portRef A1 (instanceRef bdcnt_bctr_3))
+              (portRef B1 (instanceRef e_cmp_3))))
+          (net WCNT6
+            (joined
+              (portRef (member WCNT 5))
+              (portRef A0 (instanceRef g_cmp_3))
+              (portRef Q (instanceRef FF_68))
+              (portRef A0 (instanceRef bdcnt_bctr_3))
+              (portRef B0 (instanceRef e_cmp_3))))
+          (net WCNT5
+            (joined
+              (portRef (member WCNT 6))
+              (portRef A1 (instanceRef g_cmp_2))
+              (portRef Q (instanceRef FF_69))
+              (portRef A1 (instanceRef bdcnt_bctr_2))
+              (portRef B1 (instanceRef e_cmp_2))))
+          (net WCNT4
+            (joined
+              (portRef (member WCNT 7))
+              (portRef A0 (instanceRef g_cmp_2))
+              (portRef Q (instanceRef FF_70))
+              (portRef A0 (instanceRef bdcnt_bctr_2))
+              (portRef B0 (instanceRef e_cmp_2))))
+          (net WCNT3
+            (joined
+              (portRef (member WCNT 8))
+              (portRef A1 (instanceRef g_cmp_1))
+              (portRef Q (instanceRef FF_71))
+              (portRef A1 (instanceRef bdcnt_bctr_1))
+              (portRef B1 (instanceRef e_cmp_1))))
+          (net WCNT2
+            (joined
+              (portRef (member WCNT 9))
+              (portRef A0 (instanceRef g_cmp_1))
+              (portRef Q (instanceRef FF_72))
+              (portRef A0 (instanceRef bdcnt_bctr_1))
+              (portRef B0 (instanceRef e_cmp_1))))
+          (net WCNT1
+            (joined
+              (portRef (member WCNT 10))
+              (portRef A1 (instanceRef g_cmp_0))
+              (portRef Q (instanceRef FF_73))
+              (portRef A1 (instanceRef bdcnt_bctr_0))
+              (portRef B1 (instanceRef e_cmp_0))))
+          (net WCNT0
+            (joined
+              (portRef (member WCNT 11))
+              (portRef A0 (instanceRef g_cmp_0))
+              (portRef Q (instanceRef FF_74))
+              (portRef A0 (instanceRef bdcnt_bctr_0))
+              (portRef B0 (instanceRef e_cmp_0))))
+          (net dataout35
+            (joined
+              (portRef (member Q 0))
+              (portRef DOB8 (instanceRef pdp_ram_0_3_0))))
+          (net dataout34
+            (joined
+              (portRef (member Q 1))
+              (portRef DOB7 (instanceRef pdp_ram_0_3_0))))
+          (net dataout33
+            (joined
+              (portRef (member Q 2))
+              (portRef DOB6 (instanceRef pdp_ram_0_3_0))))
+          (net dataout32
+            (joined
+              (portRef (member Q 3))
+              (portRef DOB5 (instanceRef pdp_ram_0_3_0))))
+          (net dataout31
+            (joined
+              (portRef (member Q 4))
+              (portRef DOB4 (instanceRef pdp_ram_0_3_0))))
+          (net dataout30
+            (joined
+              (portRef (member Q 5))
+              (portRef DOB3 (instanceRef pdp_ram_0_3_0))))
+          (net dataout29
+            (joined
+              (portRef (member Q 6))
+              (portRef DOB2 (instanceRef pdp_ram_0_3_0))))
+          (net dataout28
+            (joined
+              (portRef (member Q 7))
+              (portRef DOB1 (instanceRef pdp_ram_0_3_0))))
+          (net dataout27
+            (joined
+              (portRef (member Q 8))
+              (portRef DOB0 (instanceRef pdp_ram_0_3_0))))
+          (net dataout26
+            (joined
+              (portRef (member Q 9))
+              (portRef DOB8 (instanceRef pdp_ram_0_2_1))))
+          (net dataout25
+            (joined
+              (portRef (member Q 10))
+              (portRef DOB7 (instanceRef pdp_ram_0_2_1))))
+          (net dataout24
+            (joined
+              (portRef (member Q 11))
+              (portRef DOB6 (instanceRef pdp_ram_0_2_1))))
+          (net dataout23
+            (joined
+              (portRef (member Q 12))
+              (portRef DOB5 (instanceRef pdp_ram_0_2_1))))
+          (net dataout22
+            (joined
+              (portRef (member Q 13))
+              (portRef DOB4 (instanceRef pdp_ram_0_2_1))))
+          (net dataout21
+            (joined
+              (portRef (member Q 14))
+              (portRef DOB3 (instanceRef pdp_ram_0_2_1))))
+          (net dataout20
+            (joined
+              (portRef (member Q 15))
+              (portRef DOB2 (instanceRef pdp_ram_0_2_1))))
+          (net dataout19
+            (joined
+              (portRef (member Q 16))
+              (portRef DOB1 (instanceRef pdp_ram_0_2_1))))
+          (net dataout18
+            (joined
+              (portRef (member Q 17))
+              (portRef DOB0 (instanceRef pdp_ram_0_2_1))))
+          (net dataout17
+            (joined
+              (portRef (member Q 18))
+              (portRef DOB8 (instanceRef pdp_ram_0_1_2))))
+          (net dataout16
+            (joined
+              (portRef (member Q 19))
+              (portRef DOB7 (instanceRef pdp_ram_0_1_2))))
+          (net dataout15
+            (joined
+              (portRef (member Q 20))
+              (portRef DOB6 (instanceRef pdp_ram_0_1_2))))
+          (net dataout14
+            (joined
+              (portRef (member Q 21))
+              (portRef DOB5 (instanceRef pdp_ram_0_1_2))))
+          (net dataout13
+            (joined
+              (portRef (member Q 22))
+              (portRef DOB4 (instanceRef pdp_ram_0_1_2))))
+          (net dataout12
+            (joined
+              (portRef (member Q 23))
+              (portRef DOB3 (instanceRef pdp_ram_0_1_2))))
+          (net dataout11
+            (joined
+              (portRef (member Q 24))
+              (portRef DOB2 (instanceRef pdp_ram_0_1_2))))
+          (net dataout10
+            (joined
+              (portRef (member Q 25))
+              (portRef DOB1 (instanceRef pdp_ram_0_1_2))))
+          (net dataout9
+            (joined
+              (portRef (member Q 26))
+              (portRef DOB0 (instanceRef pdp_ram_0_1_2))))
+          (net dataout8
+            (joined
+              (portRef (member Q 27))
+              (portRef DOB8 (instanceRef pdp_ram_0_0_3))))
+          (net dataout7
+            (joined
+              (portRef (member Q 28))
+              (portRef DOB7 (instanceRef pdp_ram_0_0_3))))
+          (net dataout6
+            (joined
+              (portRef (member Q 29))
+              (portRef DOB6 (instanceRef pdp_ram_0_0_3))))
+          (net dataout5
+            (joined
+              (portRef (member Q 30))
+              (portRef DOB5 (instanceRef pdp_ram_0_0_3))))
+          (net dataout4
+            (joined
+              (portRef (member Q 31))
+              (portRef DOB4 (instanceRef pdp_ram_0_0_3))))
+          (net dataout3
+            (joined
+              (portRef (member Q 32))
+              (portRef DOB3 (instanceRef pdp_ram_0_0_3))))
+          (net dataout2
+            (joined
+              (portRef (member Q 33))
+              (portRef DOB2 (instanceRef pdp_ram_0_0_3))))
+          (net dataout1
+            (joined
+              (portRef (member Q 34))
+              (portRef DOB1 (instanceRef pdp_ram_0_0_3))))
+          (net dataout0
+            (joined
+              (portRef (member Q 35))
+              (portRef DOB0 (instanceRef pdp_ram_0_0_3))))
+          (net AmFullThresh10
+            (joined
+              (portRef (member AmFullThresh 0))
+              (portRef B0 (instanceRef af_set_cmp_5))))
+          (net AmFullThresh9
+            (joined
+              (portRef (member AmFullThresh 1))
+              (portRef B1 (instanceRef af_set_cmp_4))))
+          (net AmFullThresh8
+            (joined
+              (portRef (member AmFullThresh 2))
+              (portRef B0 (instanceRef af_set_cmp_4))))
+          (net AmFullThresh7
+            (joined
+              (portRef (member AmFullThresh 3))
+              (portRef B1 (instanceRef af_set_cmp_3))))
+          (net AmFullThresh6
+            (joined
+              (portRef (member AmFullThresh 4))
+              (portRef B0 (instanceRef af_set_cmp_3))))
+          (net AmFullThresh5
+            (joined
+              (portRef (member AmFullThresh 5))
+              (portRef B1 (instanceRef af_set_cmp_2))))
+          (net AmFullThresh4
+            (joined
+              (portRef (member AmFullThresh 6))
+              (portRef B0 (instanceRef af_set_cmp_2))))
+          (net AmFullThresh3
+            (joined
+              (portRef (member AmFullThresh 7))
+              (portRef B1 (instanceRef af_set_cmp_1))))
+          (net AmFullThresh2
+            (joined
+              (portRef (member AmFullThresh 8))
+              (portRef B0 (instanceRef af_set_cmp_1))))
+          (net AmFullThresh1
+            (joined
+              (portRef (member AmFullThresh 9))
+              (portRef B1 (instanceRef af_set_cmp_0))))
+          (net AmFullThresh0
+            (joined
+              (portRef (member AmFullThresh 10))
+              (portRef B0 (instanceRef af_set_cmp_0))))
+          (net reset
+            (joined
+              (portRef Reset)
+              (portRef RSTB (instanceRef pdp_ram_0_0_3))
+              (portRef RSTA (instanceRef pdp_ram_0_0_3))
+              (portRef RSTB (instanceRef pdp_ram_0_1_2))
+              (portRef RSTA (instanceRef pdp_ram_0_1_2))
+              (portRef RSTB (instanceRef pdp_ram_0_2_1))
+              (portRef RSTA (instanceRef pdp_ram_0_2_1))
+              (portRef RSTB (instanceRef pdp_ram_0_3_0))
+              (portRef RSTA (instanceRef pdp_ram_0_3_0))
+              (portRef CD (instanceRef FF_74))
+              (portRef CD (instanceRef FF_73))
+              (portRef CD (instanceRef FF_72))
+              (portRef CD (instanceRef FF_71))
+              (portRef CD (instanceRef FF_70))
+              (portRef CD (instanceRef FF_69))
+              (portRef CD (instanceRef FF_68))
+              (portRef CD (instanceRef FF_67))
+              (portRef CD (instanceRef FF_66))
+              (portRef CD (instanceRef FF_65))
+              (portRef CD (instanceRef FF_64))
+              (portRef CD (instanceRef FF_63))
+              (portRef PD (instanceRef FF_62))
+              (portRef CD (instanceRef FF_61))
+              (portRef PD (instanceRef FF_60))
+              (portRef CD (instanceRef FF_59))
+              (portRef CD (instanceRef FF_58))
+              (portRef CD (instanceRef FF_57))
+              (portRef CD (instanceRef FF_56))
+              (portRef CD (instanceRef FF_55))
+              (portRef CD (instanceRef FF_54))
+              (portRef CD (instanceRef FF_53))
+              (portRef CD (instanceRef FF_52))
+              (portRef CD (instanceRef FF_51))
+              (portRef CD (instanceRef FF_50))
+              (portRef CD (instanceRef FF_49))
+              (portRef PD (instanceRef FF_48))
+              (portRef CD (instanceRef FF_47))
+              (portRef CD (instanceRef FF_46))
+              (portRef CD (instanceRef FF_45))
+              (portRef CD (instanceRef FF_44))
+              (portRef CD (instanceRef FF_43))
+              (portRef CD (instanceRef FF_42))
+              (portRef CD (instanceRef FF_41))
+              (portRef CD (instanceRef FF_40))
+              (portRef CD (instanceRef FF_39))
+              (portRef CD (instanceRef FF_38))
+              (portRef CD (instanceRef FF_37))
+              (portRef CD (instanceRef FF_36))
+              (portRef CD (instanceRef FF_35))
+              (portRef CD (instanceRef FF_34))
+              (portRef CD (instanceRef FF_33))
+              (portRef CD (instanceRef FF_32))
+              (portRef CD (instanceRef FF_31))
+              (portRef CD (instanceRef FF_30))
+              (portRef CD (instanceRef FF_29))
+              (portRef CD (instanceRef FF_28))
+              (portRef CD (instanceRef FF_27))
+              (portRef CD (instanceRef FF_26))
+              (portRef CD (instanceRef FF_25))
+              (portRef CD (instanceRef FF_24))
+              (portRef CD (instanceRef FF_23))
+              (portRef CD (instanceRef FF_22))
+              (portRef CD (instanceRef FF_21))
+              (portRef CD (instanceRef FF_20))
+              (portRef CD (instanceRef FF_19))
+              (portRef CD (instanceRef FF_18))
+              (portRef CD (instanceRef FF_17))
+              (portRef CD (instanceRef FF_16))
+              (portRef CD (instanceRef FF_15))
+              (portRef CD (instanceRef FF_14))
+              (portRef CD (instanceRef FF_13))
+              (portRef CD (instanceRef FF_12))
+              (portRef CD (instanceRef FF_11))
+              (portRef CD (instanceRef FF_10))
+              (portRef CD (instanceRef FF_9))
+              (portRef CD (instanceRef FF_8))
+              (portRef CD (instanceRef FF_7))
+              (portRef CD (instanceRef FF_6))
+              (portRef CD (instanceRef FF_5))
+              (portRef CD (instanceRef FF_4))
+              (portRef CD (instanceRef FF_3))
+              (portRef CD (instanceRef FF_2))
+              (portRef CD (instanceRef FF_1))
+              (portRef CD (instanceRef FF_0))))
+          (net rden
+            (joined
+              (portRef RdEn)
+              (portRef A (instanceRef AND2_t4))))
+          (net wren
+            (joined
+              (portRef WrEn)
+              (portRef A (instanceRef AND2_t5))))
+          (net clk
+            (joined
+              (portRef Clock)
+              (portRef CLKB (instanceRef pdp_ram_0_0_3))
+              (portRef CLKA (instanceRef pdp_ram_0_0_3))
+              (portRef CLKB (instanceRef pdp_ram_0_1_2))
+              (portRef CLKA (instanceRef pdp_ram_0_1_2))
+              (portRef CLKB (instanceRef pdp_ram_0_2_1))
+              (portRef CLKA (instanceRef pdp_ram_0_2_1))
+              (portRef CLKB (instanceRef pdp_ram_0_3_0))
+              (portRef CLKA (instanceRef pdp_ram_0_3_0))
+              (portRef CK (instanceRef FF_74))
+              (portRef CK (instanceRef FF_73))
+              (portRef CK (instanceRef FF_72))
+              (portRef CK (instanceRef FF_71))
+              (portRef CK (instanceRef FF_70))
+              (portRef CK (instanceRef FF_69))
+              (portRef CK (instanceRef FF_68))
+              (portRef CK (instanceRef FF_67))
+              (portRef CK (instanceRef FF_66))
+              (portRef CK (instanceRef FF_65))
+              (portRef CK (instanceRef FF_64))
+              (portRef CK (instanceRef FF_63))
+              (portRef CK (instanceRef FF_62))
+              (portRef CK (instanceRef FF_61))
+              (portRef CK (instanceRef FF_60))
+              (portRef CK (instanceRef FF_59))
+              (portRef CK (instanceRef FF_58))
+              (portRef CK (instanceRef FF_57))
+              (portRef CK (instanceRef FF_56))
+              (portRef CK (instanceRef FF_55))
+              (portRef CK (instanceRef FF_54))
+              (portRef CK (instanceRef FF_53))
+              (portRef CK (instanceRef FF_52))
+              (portRef CK (instanceRef FF_51))
+              (portRef CK (instanceRef FF_50))
+              (portRef CK (instanceRef FF_49))
+              (portRef CK (instanceRef FF_48))
+              (portRef CK (instanceRef FF_47))
+              (portRef CK (instanceRef FF_46))
+              (portRef CK (instanceRef FF_45))
+              (portRef CK (instanceRef FF_44))
+              (portRef CK (instanceRef FF_43))
+              (portRef CK (instanceRef FF_42))
+              (portRef CK (instanceRef FF_41))
+              (portRef CK (instanceRef FF_40))
+              (portRef CK (instanceRef FF_39))
+              (portRef CK (instanceRef FF_38))
+              (portRef CK (instanceRef FF_37))
+              (portRef CK (instanceRef FF_36))
+              (portRef CK (instanceRef FF_35))
+              (portRef CK (instanceRef FF_34))
+              (portRef CK (instanceRef FF_33))
+              (portRef CK (instanceRef FF_32))
+              (portRef CK (instanceRef FF_31))
+              (portRef CK (instanceRef FF_30))
+              (portRef CK (instanceRef FF_29))
+              (portRef CK (instanceRef FF_28))
+              (portRef CK (instanceRef FF_27))
+              (portRef CK (instanceRef FF_26))
+              (portRef CK (instanceRef FF_25))
+              (portRef CK (instanceRef FF_24))
+              (portRef CK (instanceRef FF_23))
+              (portRef CK (instanceRef FF_22))
+              (portRef CK (instanceRef FF_21))
+              (portRef CK (instanceRef FF_20))
+              (portRef CK (instanceRef FF_19))
+              (portRef CK (instanceRef FF_18))
+              (portRef CK (instanceRef FF_17))
+              (portRef CK (instanceRef FF_16))
+              (portRef CK (instanceRef FF_15))
+              (portRef CK (instanceRef FF_14))
+              (portRef CK (instanceRef FF_13))
+              (portRef CK (instanceRef FF_12))
+              (portRef CK (instanceRef FF_11))
+              (portRef CK (instanceRef FF_10))
+              (portRef CK (instanceRef FF_9))
+              (portRef CK (instanceRef FF_8))
+              (portRef CK (instanceRef FF_7))
+              (portRef CK (instanceRef FF_6))
+              (portRef CK (instanceRef FF_5))
+              (portRef CK (instanceRef FF_4))
+              (portRef CK (instanceRef FF_3))
+              (portRef CK (instanceRef FF_2))
+              (portRef CK (instanceRef FF_1))
+              (portRef CK (instanceRef FF_0))))
+          (net datain35
+            (joined
+              (portRef (member Data 0))
+              (portRef DIA8 (instanceRef pdp_ram_0_3_0))))
+          (net datain34
+            (joined
+              (portRef (member Data 1))
+              (portRef DIA7 (instanceRef pdp_ram_0_3_0))))
+          (net datain33
+            (joined
+              (portRef (member Data 2))
+              (portRef DIA6 (instanceRef pdp_ram_0_3_0))))
+          (net datain32
+            (joined
+              (portRef (member Data 3))
+              (portRef DIA5 (instanceRef pdp_ram_0_3_0))))
+          (net datain31
+            (joined
+              (portRef (member Data 4))
+              (portRef DIA4 (instanceRef pdp_ram_0_3_0))))
+          (net datain30
+            (joined
+              (portRef (member Data 5))
+              (portRef DIA3 (instanceRef pdp_ram_0_3_0))))
+          (net datain29
+            (joined
+              (portRef (member Data 6))
+              (portRef DIA2 (instanceRef pdp_ram_0_3_0))))
+          (net datain28
+            (joined
+              (portRef (member Data 7))
+              (portRef DIA1 (instanceRef pdp_ram_0_3_0))))
+          (net datain27
+            (joined
+              (portRef (member Data 8))
+              (portRef DIA0 (instanceRef pdp_ram_0_3_0))))
+          (net datain26
+            (joined
+              (portRef (member Data 9))
+              (portRef DIA8 (instanceRef pdp_ram_0_2_1))))
+          (net datain25
+            (joined
+              (portRef (member Data 10))
+              (portRef DIA7 (instanceRef pdp_ram_0_2_1))))
+          (net datain24
+            (joined
+              (portRef (member Data 11))
+              (portRef DIA6 (instanceRef pdp_ram_0_2_1))))
+          (net datain23
+            (joined
+              (portRef (member Data 12))
+              (portRef DIA5 (instanceRef pdp_ram_0_2_1))))
+          (net datain22
+            (joined
+              (portRef (member Data 13))
+              (portRef DIA4 (instanceRef pdp_ram_0_2_1))))
+          (net datain21
+            (joined
+              (portRef (member Data 14))
+              (portRef DIA3 (instanceRef pdp_ram_0_2_1))))
+          (net datain20
+            (joined
+              (portRef (member Data 15))
+              (portRef DIA2 (instanceRef pdp_ram_0_2_1))))
+          (net datain19
+            (joined
+              (portRef (member Data 16))
+              (portRef DIA1 (instanceRef pdp_ram_0_2_1))))
+          (net datain18
+            (joined
+              (portRef (member Data 17))
+              (portRef DIA0 (instanceRef pdp_ram_0_2_1))))
+          (net datain17
+            (joined
+              (portRef (member Data 18))
+              (portRef DIA8 (instanceRef pdp_ram_0_1_2))))
+          (net datain16
+            (joined
+              (portRef (member Data 19))
+              (portRef DIA7 (instanceRef pdp_ram_0_1_2))))
+          (net datain15
+            (joined
+              (portRef (member Data 20))
+              (portRef DIA6 (instanceRef pdp_ram_0_1_2))))
+          (net datain14
+            (joined
+              (portRef (member Data 21))
+              (portRef DIA5 (instanceRef pdp_ram_0_1_2))))
+          (net datain13
+            (joined
+              (portRef (member Data 22))
+              (portRef DIA4 (instanceRef pdp_ram_0_1_2))))
+          (net datain12
+            (joined
+              (portRef (member Data 23))
+              (portRef DIA3 (instanceRef pdp_ram_0_1_2))))
+          (net datain11
+            (joined
+              (portRef (member Data 24))
+              (portRef DIA2 (instanceRef pdp_ram_0_1_2))))
+          (net datain10
+            (joined
+              (portRef (member Data 25))
+              (portRef DIA1 (instanceRef pdp_ram_0_1_2))))
+          (net datain9
+            (joined
+              (portRef (member Data 26))
+              (portRef DIA0 (instanceRef pdp_ram_0_1_2))))
+          (net datain8
+            (joined
+              (portRef (member Data 27))
+              (portRef DIA8 (instanceRef pdp_ram_0_0_3))))
+          (net datain7
+            (joined
+              (portRef (member Data 28))
+              (portRef DIA7 (instanceRef pdp_ram_0_0_3))))
+          (net datain6
+            (joined
+              (portRef (member Data 29))
+              (portRef DIA6 (instanceRef pdp_ram_0_0_3))))
+          (net datain5
+            (joined
+              (portRef (member Data 30))
+              (portRef DIA5 (instanceRef pdp_ram_0_0_3))))
+          (net datain4
+            (joined
+              (portRef (member Data 31))
+              (portRef DIA4 (instanceRef pdp_ram_0_0_3))))
+          (net datain3
+            (joined
+              (portRef (member Data 32))
+              (portRef DIA3 (instanceRef pdp_ram_0_0_3))))
+          (net datain2
+            (joined
+              (portRef (member Data 33))
+              (portRef DIA2 (instanceRef pdp_ram_0_0_3))))
+          (net datain1
+            (joined
+              (portRef (member Data 34))
+              (portRef DIA1 (instanceRef pdp_ram_0_0_3))))
+          (net datain0
+            (joined
+              (portRef (member Data 35))
+              (portRef DIA0 (instanceRef pdp_ram_0_0_3))))))))
+  (design fifo_36x2k_oreg
+    (cellRef fifo_36x2k_oreg
+      (libraryRef ORCLIB)))
+)

diff --git a/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.fdc b/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.fdc
new file mode 100644 (file)
index 0000000..6fbcac9
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.fdc
@@ -0,0 +1,2 @@
+###==== Start Configuration
+

diff --git a/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.lpc b/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.lpc
new file mode 100644 (file)
index 0000000..9a49b8d
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.lpc
@@ -0,0 +1,50 @@
+[Device]
+Family=ecp5um
+PartType=LFE5UM-85F
+PartName=LFE5UM-85F-8MG285C
+SpeedGrade=8
+Package=CSFBGA285
+OperatingCondition=COM
+Status=C
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO
+CoreRevision=5.0
+ModuleName=fifo_36x2k_oreg
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=03/18/2015
+Time=14:41:09
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=2048
+Width=36
+regout=1
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=1
+PfMode=Dynamic - Single Threshold
+PfAssert=508
+PfDeassert=506
+Reset=Async
+Reset1=Sync
+RDataCount=1
+EnECC=0
+EnFWFT=0
+
+[Command]
+cmd_line= -w -n fifo_36x2k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 2048 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill

diff --git a/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.ngd b/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.ngd
new file mode 100644 (file)
index 0000000..7e0061e
Binary files /dev/null and b/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.ngd differ

diff --git a/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.ngo b/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.ngo
new file mode 100644 (file)
index 0000000..db3ed08
Binary files /dev/null and b/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.ngo differ

diff --git a/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.vhd b/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.vhd
new file mode 100644 (file)
index 0000000..f8f1bfe
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.vhd
@@ -0,0 +1,1218 @@
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80
+-- Module  Version: 5.0
+--/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x2k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 2048 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.fdc 
+
+-- Wed Mar 18 14:41:11 2015
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity fifo_36x2k_oreg is
+    port (
+        Data: in  std_logic_vector(35 downto 0); 
+        Clock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        AmFullThresh: in  std_logic_vector(10 downto 0); 
+        Q: out  std_logic_vector(35 downto 0); 
+        WCNT: out  std_logic_vector(11 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic; 
+        AlmostFull: out  std_logic);
+end fifo_36x2k_oreg;
+
+architecture Structure of fifo_36x2k_oreg is
+
+    -- internal signal declarations
+    signal invout_2: std_logic;
+    signal invout_1: std_logic;
+    signal rden_i_inv: std_logic;
+    signal invout_0: std_logic;
+    signal r_nw: std_logic;
+    signal fcnt_en: std_logic;
+    signal empty_i: std_logic;
+    signal empty_d: std_logic;
+    signal full_i: std_logic;
+    signal full_d: std_logic;
+    signal wptr_0: std_logic;
+    signal wptr_1: std_logic;
+    signal wptr_2: std_logic;
+    signal wptr_3: std_logic;
+    signal wptr_4: std_logic;
+    signal wptr_5: std_logic;
+    signal wptr_6: std_logic;
+    signal wptr_7: std_logic;
+    signal wptr_8: std_logic;
+    signal wptr_9: std_logic;
+    signal wptr_10: std_logic;
+    signal wptr_11: std_logic;
+    signal rptr_11: std_logic;
+    signal ifcount_0: std_logic;
+    signal ifcount_1: std_logic;
+    signal bdcnt_bctr_ci: std_logic;
+    signal ifcount_2: std_logic;
+    signal ifcount_3: std_logic;
+    signal co0: std_logic;
+    signal ifcount_4: std_logic;
+    signal ifcount_5: std_logic;
+    signal co1: std_logic;
+    signal ifcount_6: std_logic;
+    signal ifcount_7: std_logic;
+    signal co2: std_logic;
+    signal ifcount_8: std_logic;
+    signal ifcount_9: std_logic;
+    signal co3: std_logic;
+    signal ifcount_10: std_logic;
+    signal ifcount_11: std_logic;
+    signal co5: std_logic;
+    signal co4: std_logic;
+    signal cmp_ci: std_logic;
+    signal rden_i: std_logic;
+    signal co0_1: std_logic;
+    signal co1_1: std_logic;
+    signal co2_1: std_logic;
+    signal co3_1: std_logic;
+    signal co4_1: std_logic;
+    signal cmp_le_1: std_logic;
+    signal cmp_le_1_c: std_logic;
+    signal cmp_ci_1: std_logic;
+    signal fcount_0: std_logic;
+    signal fcount_1: std_logic;
+    signal co0_2: std_logic;
+    signal fcount_2: std_logic;
+    signal fcount_3: std_logic;
+    signal co1_2: std_logic;
+    signal fcount_4: std_logic;
+    signal fcount_5: std_logic;
+    signal co2_2: std_logic;
+    signal fcount_6: std_logic;
+    signal fcount_7: std_logic;
+    signal co3_2: std_logic;
+    signal fcount_8: std_logic;
+    signal fcount_9: std_logic;
+    signal co4_2: std_logic;
+    signal wren_i_inv: std_logic;
+    signal fcount_10: std_logic;
+    signal fcount_11: std_logic;
+    signal cmp_ge_d1: std_logic;
+    signal cmp_ge_d1_c: std_logic;
+    signal iwcount_0: std_logic;
+    signal iwcount_1: std_logic;
+    signal w_ctr_ci: std_logic;
+    signal iwcount_2: std_logic;
+    signal iwcount_3: std_logic;
+    signal co0_3: std_logic;
+    signal iwcount_4: std_logic;
+    signal iwcount_5: std_logic;
+    signal co1_3: std_logic;
+    signal iwcount_6: std_logic;
+    signal iwcount_7: std_logic;
+    signal co2_3: std_logic;
+    signal iwcount_8: std_logic;
+    signal iwcount_9: std_logic;
+    signal co3_3: std_logic;
+    signal iwcount_10: std_logic;
+    signal iwcount_11: std_logic;
+    signal co5_1: std_logic;
+    signal co4_3: std_logic;
+    signal wcount_11: std_logic;
+    signal ircount_0: std_logic;
+    signal ircount_1: std_logic;
+    signal r_ctr_ci: std_logic;
+    signal rcount_0: std_logic;
+    signal rcount_1: std_logic;
+    signal ircount_2: std_logic;
+    signal ircount_3: std_logic;
+    signal co0_4: std_logic;
+    signal rcount_2: std_logic;
+    signal rcount_3: std_logic;
+    signal ircount_4: std_logic;
+    signal ircount_5: std_logic;
+    signal co1_4: std_logic;
+    signal rcount_4: std_logic;
+    signal rcount_5: std_logic;
+    signal ircount_6: std_logic;
+    signal ircount_7: std_logic;
+    signal co2_4: std_logic;
+    signal rcount_6: std_logic;
+    signal rcount_7: std_logic;
+    signal ircount_8: std_logic;
+    signal ircount_9: std_logic;
+    signal co3_4: std_logic;
+    signal rcount_8: std_logic;
+    signal rcount_9: std_logic;
+    signal ircount_10: std_logic;
+    signal ircount_11: std_logic;
+    signal co5_2: std_logic;
+    signal co4_4: std_logic;
+    signal rcount_10: std_logic;
+    signal rcount_11: std_logic;
+    signal wcnt_sub_0: std_logic;
+    signal rptr_0: std_logic;
+    signal cnt_con_inv: std_logic;
+    signal wcount_0: std_logic;
+    signal cnt_con: std_logic;
+    signal precin: std_logic;
+    signal wcnt_sub_1: std_logic;
+    signal wcnt_sub_2: std_logic;
+    signal rptr_2: std_logic;
+    signal rptr_1: std_logic;
+    signal wcount_2: std_logic;
+    signal wcount_1: std_logic;
+    signal co0_5: std_logic;
+    signal wcnt_sub_3: std_logic;
+    signal wcnt_sub_4: std_logic;
+    signal rptr_4: std_logic;
+    signal rptr_3: std_logic;
+    signal wcount_4: std_logic;
+    signal wcount_3: std_logic;
+    signal co1_5: std_logic;
+    signal wcnt_sub_5: std_logic;
+    signal wcnt_sub_6: std_logic;
+    signal rptr_6: std_logic;
+    signal rptr_5: std_logic;
+    signal wcount_6: std_logic;
+    signal wcount_5: std_logic;
+    signal co2_5: std_logic;
+    signal wcnt_sub_7: std_logic;
+    signal wcnt_sub_8: std_logic;
+    signal rptr_8: std_logic;
+    signal rptr_7: std_logic;
+    signal wcount_8: std_logic;
+    signal wcount_7: std_logic;
+    signal co3_5: std_logic;
+    signal wcnt_sub_9: std_logic;
+    signal wcnt_sub_10: std_logic;
+    signal rptr_10: std_logic;
+    signal rptr_9: std_logic;
+    signal wcount_10: std_logic;
+    signal wcount_9: std_logic;
+    signal co4_5: std_logic;
+    signal wcnt_sub_11: std_logic;
+    signal wcnt_sub_msb: std_logic;
+    signal co5_3: std_logic;
+    signal wren_i: std_logic;
+    signal cmp_ci_2: std_logic;
+    signal wcnt_reg_0: std_logic;
+    signal wcnt_reg_1: std_logic;
+    signal co0_6: std_logic;
+    signal wcnt_reg_2: std_logic;
+    signal wcnt_reg_3: std_logic;
+    signal co1_6: std_logic;
+    signal wcnt_reg_4: std_logic;
+    signal wcnt_reg_5: std_logic;
+    signal co2_6: std_logic;
+    signal wcnt_reg_6: std_logic;
+    signal wcnt_reg_7: std_logic;
+    signal co3_6: std_logic;
+    signal wcnt_reg_8: std_logic;
+    signal wcnt_reg_9: std_logic;
+    signal co4_6: std_logic;
+    signal wcnt_reg_10: std_logic;
+    signal wcnt_reg_11: std_logic;
+    signal af_set: std_logic;
+    signal scuba_vhi: std_logic;
+    signal scuba_vlo: std_logic;
+    signal af_set_c: std_logic;
+
+    attribute MEM_LPC_FILE : string; 
+    attribute MEM_INIT_FILE : string; 
+    attribute GSR : string; 
+    attribute MEM_LPC_FILE of pdp_ram_0_0_3 : label is "fifo_36x2k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_0_3 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_0_1_2 : label is "fifo_36x2k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_1_2 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_0_2_1 : label is "fifo_36x2k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_2_1 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_0_3_0 : label is "fifo_36x2k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_3_0 : label is "";
+    attribute GSR of FF_74 : label is "ENABLED";
+    attribute GSR of FF_73 : label is "ENABLED";
+    attribute GSR of FF_72 : label is "ENABLED";
+    attribute GSR of FF_71 : label is "ENABLED";
+    attribute GSR of FF_70 : label is "ENABLED";
+    attribute GSR of FF_69 : label is "ENABLED";
+    attribute GSR of FF_68 : label is "ENABLED";
+    attribute GSR of FF_67 : label is "ENABLED";
+    attribute GSR of FF_66 : label is "ENABLED";
+    attribute GSR of FF_65 : label is "ENABLED";
+    attribute GSR of FF_64 : label is "ENABLED";
+    attribute GSR of FF_63 : label is "ENABLED";
+    attribute GSR of FF_62 : label is "ENABLED";
+    attribute GSR of FF_61 : label is "ENABLED";
+    attribute GSR of FF_60 : label is "ENABLED";
+    attribute GSR of FF_59 : label is "ENABLED";
+    attribute GSR of FF_58 : label is "ENABLED";
+    attribute GSR of FF_57 : label is "ENABLED";
+    attribute GSR of FF_56 : label is "ENABLED";
+    attribute GSR of FF_55 : label is "ENABLED";
+    attribute GSR of FF_54 : label is "ENABLED";
+    attribute GSR of FF_53 : label is "ENABLED";
+    attribute GSR of FF_52 : label is "ENABLED";
+    attribute GSR of FF_51 : label is "ENABLED";
+    attribute GSR of FF_50 : label is "ENABLED";
+    attribute GSR of FF_49 : label is "ENABLED";
+    attribute GSR of FF_48 : label is "ENABLED";
+    attribute GSR of FF_47 : label is "ENABLED";
+    attribute GSR of FF_46 : label is "ENABLED";
+    attribute GSR of FF_45 : label is "ENABLED";
+    attribute GSR of FF_44 : label is "ENABLED";
+    attribute GSR of FF_43 : label is "ENABLED";
+    attribute GSR of FF_42 : label is "ENABLED";
+    attribute GSR of FF_41 : label is "ENABLED";
+    attribute GSR of FF_40 : label is "ENABLED";
+    attribute GSR of FF_39 : label is "ENABLED";
+    attribute GSR of FF_38 : label is "ENABLED";
+    attribute GSR of FF_37 : label is "ENABLED";
+    attribute GSR of FF_36 : label is "ENABLED";
+    attribute GSR of FF_35 : label is "ENABLED";
+    attribute GSR of FF_34 : label is "ENABLED";
+    attribute GSR of FF_33 : label is "ENABLED";
+    attribute GSR of FF_32 : label is "ENABLED";
+    attribute GSR of FF_31 : label is "ENABLED";
+    attribute GSR of FF_30 : label is "ENABLED";
+    attribute GSR of FF_29 : label is "ENABLED";
+    attribute GSR of FF_28 : label is "ENABLED";
+    attribute GSR of FF_27 : label is "ENABLED";
+    attribute GSR of FF_26 : label is "ENABLED";
+    attribute GSR of FF_25 : label is "ENABLED";
+    attribute GSR of FF_24 : label is "ENABLED";
+    attribute GSR of FF_23 : label is "ENABLED";
+    attribute GSR of FF_22 : label is "ENABLED";
+    attribute GSR of FF_21 : label is "ENABLED";
+    attribute GSR of FF_20 : label is "ENABLED";
+    attribute GSR of FF_19 : label is "ENABLED";
+    attribute GSR of FF_18 : label is "ENABLED";
+    attribute GSR of FF_17 : label is "ENABLED";
+    attribute GSR of FF_16 : label is "ENABLED";
+    attribute GSR of FF_15 : label is "ENABLED";
+    attribute GSR of FF_14 : label is "ENABLED";
+    attribute GSR of FF_13 : label is "ENABLED";
+    attribute GSR of FF_12 : label is "ENABLED";
+    attribute GSR of FF_11 : label is "ENABLED";
+    attribute GSR of FF_10 : label is "ENABLED";
+    attribute GSR of FF_9 : label is "ENABLED";
+    attribute GSR of FF_8 : label is "ENABLED";
+    attribute GSR of FF_7 : label is "ENABLED";
+    attribute GSR of FF_6 : label is "ENABLED";
+    attribute GSR of FF_5 : label is "ENABLED";
+    attribute GSR of FF_4 : label is "ENABLED";
+    attribute GSR of FF_3 : label is "ENABLED";
+    attribute GSR of FF_2 : label is "ENABLED";
+    attribute GSR of FF_1 : label is "ENABLED";
+    attribute GSR of FF_0 : label is "ENABLED";
+    attribute syn_keep : boolean;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    AND2_t5: AND2
+        port map (A=>WrEn, B=>invout_2, Z=>wren_i);
+
+    INV_5: INV
+        port map (A=>full_i, Z=>invout_2);
+
+    AND2_t4: AND2
+        port map (A=>RdEn, B=>invout_1, Z=>rden_i);
+
+    INV_4: INV
+        port map (A=>empty_i, Z=>invout_1);
+
+    AND2_t3: AND2
+        port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
+
+    XOR2_t2: XOR2
+        port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
+
+    INV_3: INV
+        port map (A=>rden_i, Z=>rden_i_inv);
+
+    INV_2: INV
+        port map (A=>wren_i, Z=>wren_i_inv);
+
+    LUT4_1: ROM16X1A
+        generic map (initval=> X"3232")
+        port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, 
+            AD0=>empty_i, DO0=>empty_d);
+
+    LUT4_0: ROM16X1A
+        generic map (initval=> X"3232")
+        port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, 
+            AD0=>full_i, DO0=>full_d);
+
+    AND2_t1: AND2
+        port map (A=>rden_i, B=>invout_0, Z=>r_nw);
+
+    INV_1: INV
+        port map (A=>wren_i, Z=>invout_0);
+
+    XOR2_t0: XOR2
+        port map (A=>wcount_11, B=>rptr_11, Z=>wcnt_sub_msb);
+
+    INV_0: INV
+        port map (A=>cnt_con, Z=>cnt_con_inv);
+
+    pdp_ram_0_0_3: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), 
+            DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), 
+            DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, 
+            ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, 
+            ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, 
+            ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, 
+            CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, 
+            CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>scuba_vlo, 
+            RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, 
+            DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, 
+            ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, 
+            ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, 
+            ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, 
+            CSB0=>scuba_vlo, RSTB=>Reset, DOA17=>open, DOA16=>open, 
+            DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, 
+            DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, 
+            DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, 
+            DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, 
+            DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, 
+            DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>Q(8), DOB7=>Q(7), 
+            DOB6=>Q(6), DOB5=>Q(5), DOB4=>Q(4), DOB3=>Q(3), DOB2=>Q(2), 
+            DOB1=>Q(1), DOB0=>Q(0));
+
+    pdp_ram_0_1_2: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), 
+            DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), 
+            DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>scuba_vlo, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>scuba_vlo, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>Q(17), DOB7=>Q(16), 
+            DOB6=>Q(15), DOB5=>Q(14), DOB4=>Q(13), DOB3=>Q(12), 
+            DOB2=>Q(11), DOB1=>Q(10), DOB0=>Q(9));
+
+    pdp_ram_0_2_1: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), 
+            DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), 
+            DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>scuba_vlo, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>scuba_vlo, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>Q(26), DOB7=>Q(25), 
+            DOB6=>Q(24), DOB5=>Q(23), DOB4=>Q(22), DOB3=>Q(21), 
+            DOB2=>Q(20), DOB1=>Q(19), DOB0=>Q(18));
+
+    pdp_ram_0_3_0: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), 
+            DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), 
+            DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>scuba_vlo, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>scuba_vlo, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>Q(35), DOB7=>Q(34), 
+            DOB6=>Q(33), DOB5=>Q(32), DOB4=>Q(31), DOB3=>Q(30), 
+            DOB2=>Q(29), DOB1=>Q(28), DOB0=>Q(27));
+
+    FF_74: FD1P3DX
+        port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_0);
+
+    FF_73: FD1P3DX
+        port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_1);
+
+    FF_72: FD1P3DX
+        port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_2);
+
+    FF_71: FD1P3DX
+        port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_3);
+
+    FF_70: FD1P3DX
+        port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_4);
+
+    FF_69: FD1P3DX
+        port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_5);
+
+    FF_68: FD1P3DX
+        port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_6);
+
+    FF_67: FD1P3DX
+        port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_7);
+
+    FF_66: FD1P3DX
+        port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_8);
+
+    FF_65: FD1P3DX
+        port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_9);
+
+    FF_64: FD1P3DX
+        port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_10);
+
+    FF_63: FD1P3DX
+        port map (D=>ifcount_11, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_11);
+
+    FF_62: FD1S3BX
+        port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
+
+    FF_61: FD1S3DX
+        port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
+
+    FF_60: FD1P3BX
+        port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset, 
+            Q=>wcount_0);
+
+    FF_59: FD1P3DX
+        port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_1);
+
+    FF_58: FD1P3DX
+        port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_2);
+
+    FF_57: FD1P3DX
+        port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_3);
+
+    FF_56: FD1P3DX
+        port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_4);
+
+    FF_55: FD1P3DX
+        port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_5);
+
+    FF_54: FD1P3DX
+        port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_6);
+
+    FF_53: FD1P3DX
+        port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_7);
+
+    FF_52: FD1P3DX
+        port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_8);
+
+    FF_51: FD1P3DX
+        port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_9);
+
+    FF_50: FD1P3DX
+        port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_10);
+
+    FF_49: FD1P3DX
+        port map (D=>iwcount_11, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_11);
+
+    FF_48: FD1P3BX
+        port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset, 
+            Q=>rcount_0);
+
+    FF_47: FD1P3DX
+        port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_1);
+
+    FF_46: FD1P3DX
+        port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_2);
+
+    FF_45: FD1P3DX
+        port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_3);
+
+    FF_44: FD1P3DX
+        port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_4);
+
+    FF_43: FD1P3DX
+        port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_5);
+
+    FF_42: FD1P3DX
+        port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_6);
+
+    FF_41: FD1P3DX
+        port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_7);
+
+    FF_40: FD1P3DX
+        port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_8);
+
+    FF_39: FD1P3DX
+        port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_9);
+
+    FF_38: FD1P3DX
+        port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_10);
+
+    FF_37: FD1P3DX
+        port map (D=>ircount_11, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_11);
+
+    FF_36: FD1P3DX
+        port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_0);
+
+    FF_35: FD1P3DX
+        port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_1);
+
+    FF_34: FD1P3DX
+        port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_2);
+
+    FF_33: FD1P3DX
+        port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_3);
+
+    FF_32: FD1P3DX
+        port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_4);
+
+    FF_31: FD1P3DX
+        port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_5);
+
+    FF_30: FD1P3DX
+        port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_6);
+
+    FF_29: FD1P3DX
+        port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_7);
+
+    FF_28: FD1P3DX
+        port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_8);
+
+    FF_27: FD1P3DX
+        port map (D=>wcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_9);
+
+    FF_26: FD1P3DX
+        port map (D=>wcount_10, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_10);
+
+    FF_25: FD1P3DX
+        port map (D=>wcount_11, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_11);
+
+    FF_24: FD1P3DX
+        port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_0);
+
+    FF_23: FD1P3DX
+        port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_1);
+
+    FF_22: FD1P3DX
+        port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_2);
+
+    FF_21: FD1P3DX
+        port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_3);
+
+    FF_20: FD1P3DX
+        port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_4);
+
+    FF_19: FD1P3DX
+        port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_5);
+
+    FF_18: FD1P3DX
+        port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_6);
+
+    FF_17: FD1P3DX
+        port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_7);
+
+    FF_16: FD1P3DX
+        port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_8);
+
+    FF_15: FD1P3DX
+        port map (D=>rcount_9, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_9);
+
+    FF_14: FD1P3DX
+        port map (D=>rcount_10, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_10);
+
+    FF_13: FD1P3DX
+        port map (D=>rcount_11, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_11);
+
+    FF_12: FD1S3DX
+        port map (D=>wcnt_sub_0, CK=>Clock, CD=>Reset, Q=>wcnt_reg_0);
+
+    FF_11: FD1S3DX
+        port map (D=>wcnt_sub_1, CK=>Clock, CD=>Reset, Q=>wcnt_reg_1);
+
+    FF_10: FD1S3DX
+        port map (D=>wcnt_sub_2, CK=>Clock, CD=>Reset, Q=>wcnt_reg_2);
+
+    FF_9: FD1S3DX
+        port map (D=>wcnt_sub_3, CK=>Clock, CD=>Reset, Q=>wcnt_reg_3);
+
+    FF_8: FD1S3DX
+        port map (D=>wcnt_sub_4, CK=>Clock, CD=>Reset, Q=>wcnt_reg_4);
+
+    FF_7: FD1S3DX
+        port map (D=>wcnt_sub_5, CK=>Clock, CD=>Reset, Q=>wcnt_reg_5);
+
+    FF_6: FD1S3DX
+        port map (D=>wcnt_sub_6, CK=>Clock, CD=>Reset, Q=>wcnt_reg_6);
+
+    FF_5: FD1S3DX
+        port map (D=>wcnt_sub_7, CK=>Clock, CD=>Reset, Q=>wcnt_reg_7);
+
+    FF_4: FD1S3DX
+        port map (D=>wcnt_sub_8, CK=>Clock, CD=>Reset, Q=>wcnt_reg_8);
+
+    FF_3: FD1S3DX
+        port map (D=>wcnt_sub_9, CK=>Clock, CD=>Reset, Q=>wcnt_reg_9);
+
+    FF_2: FD1S3DX
+        port map (D=>wcnt_sub_10, CK=>Clock, CD=>Reset, Q=>wcnt_reg_10);
+
+    FF_1: FD1S3DX
+        port map (D=>wcnt_sub_11, CK=>Clock, CD=>Reset, Q=>wcnt_reg_11);
+
+    FF_0: FD1S3DX
+        port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull);
+
+    bdcnt_bctr_cia: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>'X', S0=>open, S1=>open, COUT=>bdcnt_bctr_ci);
+
+    bdcnt_bctr_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_0, A1=>fcount_1, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>bdcnt_bctr_ci, S0=>ifcount_0, S1=>ifcount_1, COUT=>co0);
+
+    bdcnt_bctr_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co0, S0=>ifcount_2, S1=>ifcount_3, COUT=>co1);
+
+    bdcnt_bctr_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_4, A1=>fcount_5, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co1, S0=>ifcount_4, S1=>ifcount_5, COUT=>co2);
+
+    bdcnt_bctr_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_6, A1=>fcount_7, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co2, S0=>ifcount_6, S1=>ifcount_7, COUT=>co3);
+
+    bdcnt_bctr_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_8, A1=>fcount_9, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co3, S0=>ifcount_8, S1=>ifcount_9, COUT=>co4);
+
+    bdcnt_bctr_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_10, A1=>fcount_11, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co4, S0=>ifcount_10, S1=>ifcount_11, COUT=>co5);
+
+    e_cmp_ci_a: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci);
+
+    e_cmp_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>rden_i, A1=>scuba_vlo, B0=>fcount_0, B1=>fcount_1, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>cmp_ci, S0=>open, S1=>open, COUT=>co0_1);
+
+    e_cmp_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_2, 
+            B1=>fcount_3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co0_1, S0=>open, S1=>open, COUT=>co1_1);
+
+    e_cmp_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_4, 
+            B1=>fcount_5, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co1_1, S0=>open, S1=>open, COUT=>co2_1);
+
+    e_cmp_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_6, 
+            B1=>fcount_7, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co2_1, S0=>open, S1=>open, COUT=>co3_1);
+
+    e_cmp_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_8, 
+            B1=>fcount_9, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co3_1, S0=>open, S1=>open, COUT=>co4_1);
+
+    e_cmp_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_10, 
+            B1=>fcount_11, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co4_1, S0=>open, S1=>open, 
+            COUT=>cmp_le_1_c);
+
+    a0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>cmp_le_1_c, S0=>cmp_le_1, S1=>open, 
+            COUT=>open);
+
+    g_cmp_ci_a: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_1);
+
+    g_cmp_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>cmp_ci_1, S0=>open, S1=>open, COUT=>co0_2);
+
+    g_cmp_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co0_2, S0=>open, S1=>open, COUT=>co1_2);
+
+    g_cmp_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co1_2, S0=>open, S1=>open, COUT=>co2_2);
+
+    g_cmp_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co2_2, S0=>open, S1=>open, COUT=>co3_2);
+
+    g_cmp_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co3_2, S0=>open, S1=>open, COUT=>co4_2);
+
+    g_cmp_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_10, A1=>fcount_11, B0=>wren_i, 
+            B1=>wren_i_inv, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co4_2, S0=>open, S1=>open, 
+            COUT=>cmp_ge_d1_c);
+
+    a1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>cmp_ge_d1_c, S0=>cmp_ge_d1, S1=>open, 
+            COUT=>open);
+
+    w_ctr_cia: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>w_ctr_ci);
+
+    w_ctr_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>w_ctr_ci, S0=>iwcount_0, S1=>iwcount_1, 
+            COUT=>co0_3);
+
+    w_ctr_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_2, A1=>wcount_3, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co0_3, S0=>iwcount_2, S1=>iwcount_3, 
+            COUT=>co1_3);
+
+    w_ctr_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_4, A1=>wcount_5, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co1_3, S0=>iwcount_4, S1=>iwcount_5, 
+            COUT=>co2_3);
+
+    w_ctr_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_6, A1=>wcount_7, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co2_3, S0=>iwcount_6, S1=>iwcount_7, 
+            COUT=>co3_3);
+
+    w_ctr_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_8, A1=>wcount_9, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co3_3, S0=>iwcount_8, S1=>iwcount_9, 
+            COUT=>co4_3);
+
+    w_ctr_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_10, A1=>wcount_11, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co4_3, S0=>iwcount_10, S1=>iwcount_11, 
+            COUT=>co5_1);
+
+    r_ctr_cia: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>r_ctr_ci);
+
+    r_ctr_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>r_ctr_ci, S0=>ircount_0, S1=>ircount_1, 
+            COUT=>co0_4);
+
+    r_ctr_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_2, A1=>rcount_3, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co0_4, S0=>ircount_2, S1=>ircount_3, 
+            COUT=>co1_4);
+
+    r_ctr_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_4, A1=>rcount_5, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co1_4, S0=>ircount_4, S1=>ircount_5, 
+            COUT=>co2_4);
+
+    r_ctr_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_6, A1=>rcount_7, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co2_4, S0=>ircount_6, S1=>ircount_7, 
+            COUT=>co3_4);
+
+    r_ctr_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_8, A1=>rcount_9, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co3_4, S0=>ircount_8, S1=>ircount_9, 
+            COUT=>co4_4);
+
+    r_ctr_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_10, A1=>rcount_11, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co4_4, S0=>ircount_10, S1=>ircount_11, 
+            COUT=>co5_2);
+
+    precin_inst299: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"0000", 
+        INIT0=> X"0000")
+        port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>precin);
+
+    wcnt_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>cnt_con, A1=>wcount_0, B0=>cnt_con_inv, B1=>rptr_0, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>precin, S0=>open, S1=>wcnt_sub_0, COUT=>co0_5);
+
+    wcnt_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_1, A1=>wcount_2, B0=>rptr_1, B1=>rptr_2, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co0_5, S0=>wcnt_sub_1, S1=>wcnt_sub_2, COUT=>co1_5);
+
+    wcnt_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_3, A1=>wcount_4, B0=>rptr_3, B1=>rptr_4, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co1_5, S0=>wcnt_sub_3, S1=>wcnt_sub_4, COUT=>co2_5);
+
+    wcnt_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_5, A1=>wcount_6, B0=>rptr_5, B1=>rptr_6, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co2_5, S0=>wcnt_sub_5, S1=>wcnt_sub_6, COUT=>co3_5);
+
+    wcnt_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_7, A1=>wcount_8, B0=>rptr_7, B1=>rptr_8, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co3_5, S0=>wcnt_sub_7, S1=>wcnt_sub_8, COUT=>co4_5);
+
+    wcnt_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_9, A1=>wcount_10, B0=>rptr_9, B1=>rptr_10, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co4_5, S0=>wcnt_sub_9, S1=>wcnt_sub_10, COUT=>co5_3);
+
+    wcnt_6: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co5_3, S0=>wcnt_sub_11, S1=>open, 
+            COUT=>open);
+
+    af_set_cmp_ci_a: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_2);
+
+    af_set_cmp_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0), 
+            B1=>AmFullThresh(1), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>cmp_ci_2, S0=>open, 
+            S1=>open, COUT=>co0_6);
+
+    af_set_cmp_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2), 
+            B1=>AmFullThresh(3), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co0_6, S0=>open, S1=>open, 
+            COUT=>co1_6);
+
+    af_set_cmp_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4), 
+            B1=>AmFullThresh(5), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co1_6, S0=>open, S1=>open, 
+            COUT=>co2_6);
+
+    af_set_cmp_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6), 
+            B1=>AmFullThresh(7), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co2_6, S0=>open, S1=>open, 
+            COUT=>co3_6);
+
+    af_set_cmp_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8), 
+            B1=>AmFullThresh(9), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co3_6, S0=>open, S1=>open, 
+            COUT=>co4_6);
+
+    af_set_cmp_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_10, A1=>wcnt_reg_11, B0=>AmFullThresh(10), 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co4_6, S0=>open, S1=>open, 
+            COUT=>af_set_c);
+
+    scuba_vhi_inst: VHI
+        port map (Z=>scuba_vhi);
+
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    a2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>af_set_c, S0=>af_set, S1=>open, 
+            COUT=>open);
+
+    WCNT(0) <= fcount_0;
+    WCNT(1) <= fcount_1;
+    WCNT(2) <= fcount_2;
+    WCNT(3) <= fcount_3;
+    WCNT(4) <= fcount_4;
+    WCNT(5) <= fcount_5;
+    WCNT(6) <= fcount_6;
+    WCNT(7) <= fcount_7;
+    WCNT(8) <= fcount_8;
+    WCNT(9) <= fcount_9;
+    WCNT(10) <= fcount_10;
+    WCNT(11) <= fcount_11;
+    Empty <= empty_i;
+    Full <= full_i;
+end Structure;

diff --git a/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg_ngd.asd b/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg_ngd.asd
new file mode 100644 (file)
index 0000000..c265c78
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg_ngd.asd
@@ -0,0 +1 @@
+[ActiveSupport NGD]

diff --git a/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.cst b/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.cst
new file mode 100644 (file)
index 0000000..318c0e9
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.cst
@@ -0,0 +1,3 @@
+Date=03/18/2015
+Time=14:42:29
+

diff --git a/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.edn b/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.edn
new file mode 100644 (file)
index 0000000..c7477aa
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.edn
@@ -0,0 +1,15178 @@
+(edif fifo_36x32k_oreg
+  (edifVersion 2 0 0)
+  (edifLevel 0)
+  (keywordMap (keywordLevel 0))
+  (status
+    (written
+      (timestamp 2015 3 18 14 42 30)
+      (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80"))))
+      (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x32k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 32768 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.fdc ")
+  (library ORCLIB
+    (edifLevel 0)
+    (technology
+      (numberDefinition))
+    (cell CCU2C
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A0
+            (direction INPUT))
+          (port A1
+            (direction INPUT))
+          (port B0
+            (direction INPUT))
+          (port B1
+            (direction INPUT))
+          (port C0
+            (direction INPUT))
+          (port C1
+            (direction INPUT))
+          (port D0
+            (direction INPUT))
+          (port D1
+            (direction INPUT))
+          (port CIN
+            (direction INPUT))
+          (port S0
+            (direction OUTPUT))
+          (port S1
+            (direction OUTPUT))
+          (port COUT
+            (direction OUTPUT)))))
+    (cell AND2
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A
+            (direction INPUT))
+          (port B
+            (direction INPUT))
+          (port Z
+            (direction OUTPUT)))))
+    (cell FD1P3BX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port SP
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port PD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell FD1P3DX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port SP
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port CD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell FD1S3BX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port PD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell FD1S3DX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port CD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell INV
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A
+            (direction INPUT))
+          (port Z
+            (direction OUTPUT)))))
+    (cell MUX161
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D0
+            (direction INPUT))
+          (port D1
+            (direction INPUT))
+          (port D2
+            (direction INPUT))
+          (port D3
+            (direction INPUT))
+          (port D4
+            (direction INPUT))
+          (port D5
+            (direction INPUT))
+          (port D6
+            (direction INPUT))
+          (port D7
+            (direction INPUT))
+          (port D8
+            (direction INPUT))
+          (port D9
+            (direction INPUT))
+          (port D10
+            (direction INPUT))
+          (port D11
+            (direction INPUT))
+          (port D12
+            (direction INPUT))
+          (port D13
+            (direction INPUT))
+          (port D14
+            (direction INPUT))
+          (port D15
+            (direction INPUT))
+          (port SD1
+            (direction INPUT))
+          (port SD2
+            (direction INPUT))
+          (port SD3
+            (direction INPUT))
+          (port SD4
+            (direction INPUT))
+          (port Z
+            (direction OUTPUT)))))
+    (cell ROM16X1A
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port AD3
+            (direction INPUT))
+          (port AD2
+            (direction INPUT))
+          (port AD1
+            (direction INPUT))
+          (port AD0
+            (direction INPUT))
+          (port DO0
+            (direction OUTPUT)))))
+    (cell VHI
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port Z
+            (direction OUTPUT)))))
+    (cell VLO
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port Z
+            (direction OUTPUT)))))
+    (cell XOR2
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A
+            (direction INPUT))
+          (port B
+            (direction INPUT))
+          (port Z
+            (direction OUTPUT)))))
+    (cell DP16KD
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port DIA17
+            (direction INPUT))
+          (port DIA16
+            (direction INPUT))
+          (port DIA15
+            (direction INPUT))
+          (port DIA14
+            (direction INPUT))
+          (port DIA13
+            (direction INPUT))
+          (port DIA12
+            (direction INPUT))
+          (port DIA11
+            (direction INPUT))
+          (port DIA10
+            (direction INPUT))
+          (port DIA9
+            (direction INPUT))
+          (port DIA8
+            (direction INPUT))
+          (port DIA7
+            (direction INPUT))
+          (port DIA6
+            (direction INPUT))
+          (port DIA5
+            (direction INPUT))
+          (port DIA4
+            (direction INPUT))
+          (port DIA3
+            (direction INPUT))
+          (port DIA2
+            (direction INPUT))
+          (port DIA1
+            (direction INPUT))
+          (port DIA0
+            (direction INPUT))
+          (port ADA13
+            (direction INPUT))
+          (port ADA12
+            (direction INPUT))
+          (port ADA11
+            (direction INPUT))
+          (port ADA10
+            (direction INPUT))
+          (port ADA9
+            (direction INPUT))
+          (port ADA8
+            (direction INPUT))
+          (port ADA7
+            (direction INPUT))
+          (port ADA6
+            (direction INPUT))
+          (port ADA5
+            (direction INPUT))
+          (port ADA4
+            (direction INPUT))
+          (port ADA3
+            (direction INPUT))
+          (port ADA2
+            (direction INPUT))
+          (port ADA1
+            (direction INPUT))
+          (port ADA0
+            (direction INPUT))
+          (port CEA
+            (direction INPUT))
+          (port OCEA
+            (direction INPUT))
+          (port CLKA
+            (direction INPUT))
+          (port WEA
+            (direction INPUT))
+          (port CSA2
+            (direction INPUT))
+          (port CSA1
+            (direction INPUT))
+          (port CSA0
+            (direction INPUT))
+          (port RSTA
+            (direction INPUT))
+          (port DIB17
+            (direction INPUT))
+          (port DIB16
+            (direction INPUT))
+          (port DIB15
+            (direction INPUT))
+          (port DIB14
+            (direction INPUT))
+          (port DIB13
+            (direction INPUT))
+          (port DIB12
+            (direction INPUT))
+          (port DIB11
+            (direction INPUT))
+          (port DIB10
+            (direction INPUT))
+          (port DIB9
+            (direction INPUT))
+          (port DIB8
+            (direction INPUT))
+          (port DIB7
+            (direction INPUT))
+          (port DIB6
+            (direction INPUT))
+          (port DIB5
+            (direction INPUT))
+          (port DIB4
+            (direction INPUT))
+          (port DIB3
+            (direction INPUT))
+          (port DIB2
+            (direction INPUT))
+          (port DIB1
+            (direction INPUT))
+          (port DIB0
+            (direction INPUT))
+          (port ADB13
+            (direction INPUT))
+          (port ADB12
+            (direction INPUT))
+          (port ADB11
+            (direction INPUT))
+          (port ADB10
+            (direction INPUT))
+          (port ADB9
+            (direction INPUT))
+          (port ADB8
+            (direction INPUT))
+          (port ADB7
+            (direction INPUT))
+          (port ADB6
+            (direction INPUT))
+          (port ADB5
+            (direction INPUT))
+          (port ADB4
+            (direction INPUT))
+          (port ADB3
+            (direction INPUT))
+          (port ADB2
+            (direction INPUT))
+          (port ADB1
+            (direction INPUT))
+          (port ADB0
+            (direction INPUT))
+          (port CEB
+            (direction INPUT))
+          (port OCEB
+            (direction INPUT))
+          (port CLKB
+            (direction INPUT))
+          (port WEB
+            (direction INPUT))
+          (port CSB2
+            (direction INPUT))
+          (port CSB1
+            (direction INPUT))
+          (port CSB0
+            (direction INPUT))
+          (port RSTB
+            (direction INPUT))
+          (port DOA17
+            (direction OUTPUT))
+          (port DOA16
+            (direction OUTPUT))
+          (port DOA15
+            (direction OUTPUT))
+          (port DOA14
+            (direction OUTPUT))
+          (port DOA13
+            (direction OUTPUT))
+          (port DOA12
+            (direction OUTPUT))
+          (port DOA11
+            (direction OUTPUT))
+          (port DOA10
+            (direction OUTPUT))
+          (port DOA9
+            (direction OUTPUT))
+          (port DOA8
+            (direction OUTPUT))
+          (port DOA7
+            (direction OUTPUT))
+          (port DOA6
+            (direction OUTPUT))
+          (port DOA5
+            (direction OUTPUT))
+          (port DOA4
+            (direction OUTPUT))
+          (port DOA3
+            (direction OUTPUT))
+          (port DOA2
+            (direction OUTPUT))
+          (port DOA1
+            (direction OUTPUT))
+          (port DOA0
+            (direction OUTPUT))
+          (port DOB17
+            (direction OUTPUT))
+          (port DOB16
+            (direction OUTPUT))
+          (port DOB15
+            (direction OUTPUT))
+          (port DOB14
+            (direction OUTPUT))
+          (port DOB13
+            (direction OUTPUT))
+          (port DOB12
+            (direction OUTPUT))
+          (port DOB11
+            (direction OUTPUT))
+          (port DOB10
+            (direction OUTPUT))
+          (port DOB9
+            (direction OUTPUT))
+          (port DOB8
+            (direction OUTPUT))
+          (port DOB7
+            (direction OUTPUT))
+          (port DOB6
+            (direction OUTPUT))
+          (port DOB5
+            (direction OUTPUT))
+          (port DOB4
+            (direction OUTPUT))
+          (port DOB3
+            (direction OUTPUT))
+          (port DOB2
+            (direction OUTPUT))
+          (port DOB1
+            (direction OUTPUT))
+          (port DOB0
+            (direction OUTPUT)))))
+    (cell fifo_36x32k_oreg
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port (array (rename Data "Data(35:0)") 36)
+            (direction INPUT))
+          (port Clock
+            (direction INPUT))
+          (port WrEn
+            (direction INPUT))
+          (port RdEn
+            (direction INPUT))
+          (port Reset
+            (direction INPUT))
+          (port (array (rename AmFullThresh "AmFullThresh(14:0)") 15)
+            (direction INPUT))
+          (port (array (rename Q "Q(35:0)") 36)
+            (direction OUTPUT))
+          (port (array (rename WCNT "WCNT(15:0)") 16)
+            (direction OUTPUT))
+          (port Empty
+            (direction OUTPUT))
+          (port Full
+            (direction OUTPUT))
+          (port AlmostFull
+            (direction OUTPUT)))
+        (property NGD_DRC_MASK (integer 1))
+        (contents
+          (instance AND2_t5
+            (viewRef view1 
+              (cellRef AND2)))
+          (instance INV_13
+            (viewRef view1 
+              (cellRef INV)))
+          (instance AND2_t4
+            (viewRef view1 
+              (cellRef AND2)))
+          (instance INV_12
+            (viewRef view1 
+              (cellRef INV)))
+          (instance AND2_t3
+            (viewRef view1 
+              (cellRef AND2)))
+          (instance XOR2_t2
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance INV_11
+            (viewRef view1 
+              (cellRef INV)))
+          (instance INV_10
+            (viewRef view1 
+              (cellRef INV)))
+          (instance LUT4_129
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x3232")))
+          (instance LUT4_128
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x3232")))
+          (instance INV_9
+            (viewRef view1 
+              (cellRef INV)))
+          (instance INV_8
+            (viewRef view1 
+              (cellRef INV)))
+          (instance INV_7
+            (viewRef view1 
+              (cellRef INV)))
+          (instance INV_6
+            (viewRef view1 
+              (cellRef INV)))
+          (instance LUT4_127
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance INV_5
+            (viewRef view1 
+              (cellRef INV)))
+          (instance INV_4
+            (viewRef view1 
+              (cellRef INV)))
+          (instance INV_3
+            (viewRef view1 
+              (cellRef INV)))
+          (instance INV_2
+            (viewRef view1 
+              (cellRef INV)))
+          (instance LUT4_126
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_125
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_124
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_123
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_122
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_121
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_120
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_119
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_118
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_117
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_116
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_115
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_114
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_113
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_112
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_111
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_110
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_109
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_108
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_107
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_106
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_105
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_104
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_103
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_102
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_101
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_100
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_99
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_98
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_97
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_96
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_95
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_94
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_93
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_92
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_91
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_90
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_89
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_88
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_87
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_86
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_85
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_84
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_83
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_82
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_81
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_80
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_79
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_78
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_77
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_76
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_75
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_74
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_73
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_72
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_71
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_70
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_69
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_68
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_67
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_66
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_65
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_64
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_63
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_62
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_61
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_60
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_59
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_58
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_57
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_56
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_55
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_54
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_53
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_52
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_51
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_50
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_49
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_48
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_47
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_46
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_45
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_44
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_43
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_42
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_41
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_40
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_39
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_38
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_37
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_36
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_35
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_34
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_33
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_32
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_31
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_30
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_29
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_28
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_27
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_26
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_25
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_24
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_23
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_22
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_21
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_20
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_19
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_18
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_17
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_16
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_15
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_14
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_13
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_12
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_11
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_10
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_9
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_8
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_7
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_6
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_5
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_4
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_3
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_2
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_1
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_0
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance AND2_t1
+            (viewRef view1 
+              (cellRef AND2)))
+          (instance INV_1
+            (viewRef view1 
+              (cellRef INV)))
+          (instance XOR2_t0
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance INV_0
+            (viewRef view1 
+              (cellRef INV)))
+          (instance pdp_ram_0_0_63
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_0_1_62
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_0_2_61
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_0_3_60
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_1_0_59
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_1_1_58
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_1_2_57
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_1_3_56
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_2_0_55
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_2_1_54
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_2_2_53
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_2_3_52
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_3_0_51
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_3_1_50
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_3_2_49
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_3_3_48
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_4_0_47
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_4_1_46
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_4_2_45
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_4_3_44
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_5_0_43
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_5_1_42
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_5_2_41
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_5_3_40
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_6_0_39
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_6_1_38
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_6_2_37
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_6_3_36
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_7_0_35
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_7_1_34
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_7_2_33
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_7_3_32
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_8_0_31
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_8_1_30
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_8_2_29
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_8_3_28
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_9_0_27
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_9_1_26
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_9_2_25
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_9_3_24
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_10_0_23
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_10_1_22
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_10_2_21
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_10_3_20
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_11_0_19
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_11_1_18
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_11_2_17
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_11_3_16
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_12_0_15
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_12_1_14
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_12_2_13
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_12_3_12
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_13_0_11
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_13_1_10
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_13_2_9
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_13_3_8
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_14_0_7
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_14_1_6
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_14_2_5
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_14_3_4
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_15_0_3
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_15_1_2
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_15_2_1
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_15_3_0
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x32k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance FF_106
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_105
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_104
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_103
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_102
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_101
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_100
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_99
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_98
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_97
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_96
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_95
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_94
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_93
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_92
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_91
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_90
+            (viewRef view1 
+              (cellRef FD1S3BX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_89
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_88
+            (viewRef view1 
+              (cellRef FD1P3BX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_87
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_86
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_85
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_84
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_83
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_82
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_81
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_80
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_79
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_78
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_77
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_76
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_75
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_74
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_73
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_72
+            (viewRef view1 
+              (cellRef FD1P3BX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_71
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_70
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_69
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_68
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_67
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_66
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_65
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_64
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_63
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_62
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_61
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_60
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_59
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_58
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_57
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_56
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_55
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_54
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_53
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_52
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_51
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_50
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_49
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_48
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_47
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_46
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_45
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_44
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_43
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_42
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_41
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_40
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_39
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_38
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_37
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_36
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_35
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_34
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_33
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_32
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_31
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_30
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_29
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_28
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_27
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_26
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_25
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_24
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_23
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_22
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_21
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_20
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_19
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_18
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_17
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_16
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_15
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_14
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_13
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_12
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_11
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_10
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_9
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_8
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_7
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_6
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_5
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_4
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_3
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_2
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_1
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_0
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance bdcnt_bctr_cia
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance bdcnt_bctr_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_6
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_7
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_ci_a
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance e_cmp_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_6
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_7
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance a0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance g_cmp_ci_a
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance g_cmp_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_6
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_7
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance a1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_cia
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_6
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_7
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_cia
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_6
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_7
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance mux_35
+            (viewRef view1 
+              (cellRef MUX161)))
+          (instance mux_34
+            (viewRef view1 
+              (cellRef MUX161)))
+          (instance mux_33
+            (viewRef view1 
+              (cellRef MUX161)))
+          (instance mux_32
+            (viewRef view1 
+              (cellRef MUX161)))
+          (instance mux_31
+            (viewRef view1 
+              (cellRef MUX161)))
+          (instance mux_30
+            (viewRef view1 
+              (cellRef MUX161)))
+          (instance mux_29
+            (viewRef view1 
+              (cellRef MUX161)))
+          (instance mux_28
+            (viewRef view1 
+              (cellRef MUX161)))
+          (instance mux_27
+            (viewRef view1 
+              (cellRef MUX161)))
+          (instance mux_26
+            (viewRef view1 
+              (cellRef MUX161)))
+          (instance mux_25
+            (viewRef view1 
+              (cellRef MUX161)))
+          (instance mux_24
+            (viewRef view1 
+              (cellRef MUX161)))
+          (instance mux_23
+            (viewRef view1 
+              (cellRef MUX161)))
+          (instance mux_22
+            (viewRef view1 
+              (cellRef MUX161)))
+          (instance mux_21
+            (viewRef view1 
+              (cellRef MUX161)))
+          (instance mux_20
+            (viewRef view1 
+              (cellRef MUX161)))
+          (instance mux_19
+            (viewRef view1 
+              (cellRef MUX161)))
+          (instance mux_18
+            (viewRef view1 
+              (cellRef MUX161)))
+          (instance mux_17
+            (viewRef view1 
+              (cellRef MUX161)))
+          (instance mux_16
+            (viewRef view1 
+              (cellRef MUX161)))
+          (instance mux_15
+            (viewRef view1 
+              (cellRef MUX161)))
+          (instance mux_14
+            (viewRef view1 
+              (cellRef MUX161)))
+          (instance mux_13
+            (viewRef view1 
+              (cellRef MUX161)))
+          (instance mux_12
+            (viewRef view1 
+              (cellRef MUX161)))
+          (instance mux_11
+            (viewRef view1 
+              (cellRef MUX161)))
+          (instance mux_10
+            (viewRef view1 
+              (cellRef MUX161)))
+          (instance mux_9
+            (viewRef view1 
+              (cellRef MUX161)))
+          (instance mux_8
+            (viewRef view1 
+              (cellRef MUX161)))
+          (instance mux_7
+            (viewRef view1 
+              (cellRef MUX161)))
+          (instance mux_6
+            (viewRef view1 
+              (cellRef MUX161)))
+          (instance mux_5
+            (viewRef view1 
+              (cellRef MUX161)))
+          (instance mux_4
+            (viewRef view1 
+              (cellRef MUX161)))
+          (instance mux_3
+            (viewRef view1 
+              (cellRef MUX161)))
+          (instance mux_2
+            (viewRef view1 
+              (cellRef MUX161)))
+          (instance mux_1
+            (viewRef view1 
+              (cellRef MUX161)))
+          (instance mux_0
+            (viewRef view1 
+              (cellRef MUX161)))
+          (instance precin_inst1073
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x0000"))
+            (property INIT0
+              (string "0x0000")))
+          (instance wcnt_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_6
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_7
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_8
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_ci_a
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance af_set_cmp_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_6
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_7
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance scuba_vhi_inst
+            (viewRef view1 
+              (cellRef VHI)))
+          (instance scuba_vlo_inst
+            (viewRef view1 
+              (cellRef VLO)))
+          (instance a2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (net invout_2
+            (joined
+              (portRef Z (instanceRef INV_13))
+              (portRef B (instanceRef AND2_t5))))
+          (net invout_1
+            (joined
+              (portRef Z (instanceRef INV_12))
+              (portRef B (instanceRef AND2_t4))))
+          (net rden_i_inv
+            (joined
+              (portRef Z (instanceRef INV_11))
+              (portRef B (instanceRef AND2_t3))))
+          (net wptr_14_inv
+            (joined
+              (portRef AD0 (instanceRef LUT4_65))
+              (portRef Z (instanceRef INV_6))
+              (portRef AD0 (instanceRef LUT4_127))
+              (portRef AD0 (instanceRef LUT4_125))
+              (portRef AD0 (instanceRef LUT4_123))
+              (portRef AD0 (instanceRef LUT4_121))
+              (portRef AD0 (instanceRef LUT4_119))
+              (portRef AD0 (instanceRef LUT4_117))
+              (portRef AD0 (instanceRef LUT4_115))
+              (portRef AD0 (instanceRef LUT4_113))
+              (portRef AD0 (instanceRef LUT4_111))
+              (portRef AD0 (instanceRef LUT4_109))
+              (portRef AD0 (instanceRef LUT4_107))
+              (portRef AD0 (instanceRef LUT4_105))
+              (portRef AD0 (instanceRef LUT4_103))
+              (portRef AD0 (instanceRef LUT4_101))
+              (portRef AD0 (instanceRef LUT4_99))
+              (portRef AD0 (instanceRef LUT4_97))
+              (portRef AD0 (instanceRef LUT4_95))
+              (portRef AD0 (instanceRef LUT4_93))
+              (portRef AD0 (instanceRef LUT4_91))
+              (portRef AD0 (instanceRef LUT4_89))
+              (portRef AD0 (instanceRef LUT4_87))
+              (portRef AD0 (instanceRef LUT4_85))
+              (portRef AD0 (instanceRef LUT4_83))
+              (portRef AD0 (instanceRef LUT4_81))
+              (portRef AD0 (instanceRef LUT4_79))
+              (portRef AD0 (instanceRef LUT4_77))
+              (portRef AD0 (instanceRef LUT4_75))
+              (portRef AD0 (instanceRef LUT4_73))
+              (portRef AD0 (instanceRef LUT4_71))
+              (portRef AD0 (instanceRef LUT4_69))
+              (portRef AD0 (instanceRef LUT4_67))))
+          (net rptr_14_inv
+            (joined
+              (portRef AD0 (instanceRef LUT4_64))
+              (portRef Z (instanceRef INV_2))
+              (portRef AD0 (instanceRef LUT4_126))
+              (portRef AD0 (instanceRef LUT4_124))
+              (portRef AD0 (instanceRef LUT4_122))
+              (portRef AD0 (instanceRef LUT4_120))
+              (portRef AD0 (instanceRef LUT4_118))
+              (portRef AD0 (instanceRef LUT4_116))
+              (portRef AD0 (instanceRef LUT4_114))
+              (portRef AD0 (instanceRef LUT4_112))
+              (portRef AD0 (instanceRef LUT4_110))
+              (portRef AD0 (instanceRef LUT4_108))
+              (portRef AD0 (instanceRef LUT4_106))
+              (portRef AD0 (instanceRef LUT4_104))
+              (portRef AD0 (instanceRef LUT4_102))
+              (portRef AD0 (instanceRef LUT4_100))
+              (portRef AD0 (instanceRef LUT4_98))
+              (portRef AD0 (instanceRef LUT4_96))
+              (portRef AD0 (instanceRef LUT4_94))
+              (portRef AD0 (instanceRef LUT4_92))
+              (portRef AD0 (instanceRef LUT4_90))
+              (portRef AD0 (instanceRef LUT4_88))
+              (portRef AD0 (instanceRef LUT4_86))
+              (portRef AD0 (instanceRef LUT4_84))
+              (portRef AD0 (instanceRef LUT4_82))
+              (portRef AD0 (instanceRef LUT4_80))
+              (portRef AD0 (instanceRef LUT4_78))
+              (portRef AD0 (instanceRef LUT4_76))
+              (portRef AD0 (instanceRef LUT4_74))
+              (portRef AD0 (instanceRef LUT4_72))
+              (portRef AD0 (instanceRef LUT4_70))
+              (portRef AD0 (instanceRef LUT4_68))
+              (portRef AD0 (instanceRef LUT4_66))))
+          (net wptr_13_inv
+            (joined
+              (portRef AD1 (instanceRef LUT4_33))
+              (portRef Z (instanceRef INV_7))
+              (portRef AD1 (instanceRef LUT4_127))
+              (portRef AD1 (instanceRef LUT4_125))
+              (portRef AD1 (instanceRef LUT4_123))
+              (portRef AD1 (instanceRef LUT4_121))
+              (portRef AD1 (instanceRef LUT4_119))
+              (portRef AD1 (instanceRef LUT4_117))
+              (portRef AD1 (instanceRef LUT4_115))
+              (portRef AD1 (instanceRef LUT4_113))
+              (portRef AD1 (instanceRef LUT4_111))
+              (portRef AD1 (instanceRef LUT4_109))
+              (portRef AD1 (instanceRef LUT4_107))
+              (portRef AD1 (instanceRef LUT4_105))
+              (portRef AD1 (instanceRef LUT4_103))
+              (portRef AD1 (instanceRef LUT4_101))
+              (portRef AD1 (instanceRef LUT4_99))
+              (portRef AD1 (instanceRef LUT4_97))
+              (portRef AD1 (instanceRef LUT4_63))
+              (portRef AD1 (instanceRef LUT4_61))
+              (portRef AD1 (instanceRef LUT4_59))
+              (portRef AD1 (instanceRef LUT4_57))
+              (portRef AD1 (instanceRef LUT4_55))
+              (portRef AD1 (instanceRef LUT4_53))
+              (portRef AD1 (instanceRef LUT4_51))
+              (portRef AD1 (instanceRef LUT4_49))
+              (portRef AD1 (instanceRef LUT4_47))
+              (portRef AD1 (instanceRef LUT4_45))
+              (portRef AD1 (instanceRef LUT4_43))
+              (portRef AD1 (instanceRef LUT4_41))
+              (portRef AD1 (instanceRef LUT4_39))
+              (portRef AD1 (instanceRef LUT4_37))
+              (portRef AD1 (instanceRef LUT4_35))))
+          (net rptr_13_inv
+            (joined
+              (portRef AD1 (instanceRef LUT4_32))
+              (portRef Z (instanceRef INV_3))
+              (portRef AD1 (instanceRef LUT4_126))
+              (portRef AD1 (instanceRef LUT4_124))
+              (portRef AD1 (instanceRef LUT4_122))
+              (portRef AD1 (instanceRef LUT4_120))
+              (portRef AD1 (instanceRef LUT4_118))
+              (portRef AD1 (instanceRef LUT4_116))
+              (portRef AD1 (instanceRef LUT4_114))
+              (portRef AD1 (instanceRef LUT4_112))
+              (portRef AD1 (instanceRef LUT4_110))
+              (portRef AD1 (instanceRef LUT4_108))
+              (portRef AD1 (instanceRef LUT4_106))
+              (portRef AD1 (instanceRef LUT4_104))
+              (portRef AD1 (instanceRef LUT4_102))
+              (portRef AD1 (instanceRef LUT4_100))
+              (portRef AD1 (instanceRef LUT4_98))
+              (portRef AD1 (instanceRef LUT4_96))
+              (portRef AD1 (instanceRef LUT4_62))
+              (portRef AD1 (instanceRef LUT4_60))
+              (portRef AD1 (instanceRef LUT4_58))
+              (portRef AD1 (instanceRef LUT4_56))
+              (portRef AD1 (instanceRef LUT4_54))
+              (portRef AD1 (instanceRef LUT4_52))
+              (portRef AD1 (instanceRef LUT4_50))
+              (portRef AD1 (instanceRef LUT4_48))
+              (portRef AD1 (instanceRef LUT4_46))
+              (portRef AD1 (instanceRef LUT4_44))
+              (portRef AD1 (instanceRef LUT4_42))
+              (portRef AD1 (instanceRef LUT4_40))
+              (portRef AD1 (instanceRef LUT4_38))
+              (portRef AD1 (instanceRef LUT4_36))
+              (portRef AD1 (instanceRef LUT4_34))))
+          (net wptr_12_inv
+            (joined
+              (portRef AD2 (instanceRef LUT4_17))
+              (portRef Z (instanceRef INV_8))
+              (portRef AD2 (instanceRef LUT4_127))
+              (portRef AD2 (instanceRef LUT4_125))
+              (portRef AD2 (instanceRef LUT4_123))
+              (portRef AD2 (instanceRef LUT4_121))
+              (portRef AD2 (instanceRef LUT4_119))
+              (portRef AD2 (instanceRef LUT4_117))
+              (portRef AD2 (instanceRef LUT4_115))
+              (portRef AD2 (instanceRef LUT4_113))
+              (portRef AD2 (instanceRef LUT4_95))
+              (portRef AD2 (instanceRef LUT4_93))
+              (portRef AD2 (instanceRef LUT4_91))
+              (portRef AD2 (instanceRef LUT4_89))
+              (portRef AD2 (instanceRef LUT4_87))
+              (portRef AD2 (instanceRef LUT4_85))
+              (portRef AD2 (instanceRef LUT4_83))
+              (portRef AD2 (instanceRef LUT4_81))
+              (portRef AD2 (instanceRef LUT4_63))
+              (portRef AD2 (instanceRef LUT4_61))
+              (portRef AD2 (instanceRef LUT4_59))
+              (portRef AD2 (instanceRef LUT4_57))
+              (portRef AD2 (instanceRef LUT4_55))
+              (portRef AD2 (instanceRef LUT4_53))
+              (portRef AD2 (instanceRef LUT4_51))
+              (portRef AD2 (instanceRef LUT4_49))
+              (portRef AD2 (instanceRef LUT4_31))
+              (portRef AD2 (instanceRef LUT4_29))
+              (portRef AD2 (instanceRef LUT4_27))
+              (portRef AD2 (instanceRef LUT4_25))
+              (portRef AD2 (instanceRef LUT4_23))
+              (portRef AD2 (instanceRef LUT4_21))
+              (portRef AD2 (instanceRef LUT4_19))))
+          (net rptr_12_inv
+            (joined
+              (portRef AD2 (instanceRef LUT4_16))
+              (portRef Z (instanceRef INV_4))
+              (portRef AD2 (instanceRef LUT4_126))
+              (portRef AD2 (instanceRef LUT4_124))
+              (portRef AD2 (instanceRef LUT4_122))
+              (portRef AD2 (instanceRef LUT4_120))
+              (portRef AD2 (instanceRef LUT4_118))
+              (portRef AD2 (instanceRef LUT4_116))
+              (portRef AD2 (instanceRef LUT4_114))
+              (portRef AD2 (instanceRef LUT4_112))
+              (portRef AD2 (instanceRef LUT4_94))
+              (portRef AD2 (instanceRef LUT4_92))
+              (portRef AD2 (instanceRef LUT4_90))
+              (portRef AD2 (instanceRef LUT4_88))
+              (portRef AD2 (instanceRef LUT4_86))
+              (portRef AD2 (instanceRef LUT4_84))
+              (portRef AD2 (instanceRef LUT4_82))
+              (portRef AD2 (instanceRef LUT4_80))
+              (portRef AD2 (instanceRef LUT4_62))
+              (portRef AD2 (instanceRef LUT4_60))
+              (portRef AD2 (instanceRef LUT4_58))
+              (portRef AD2 (instanceRef LUT4_56))
+              (portRef AD2 (instanceRef LUT4_54))
+              (portRef AD2 (instanceRef LUT4_52))
+              (portRef AD2 (instanceRef LUT4_50))
+              (portRef AD2 (instanceRef LUT4_48))
+              (portRef AD2 (instanceRef LUT4_30))
+              (portRef AD2 (instanceRef LUT4_28))
+              (portRef AD2 (instanceRef LUT4_26))
+              (portRef AD2 (instanceRef LUT4_24))
+              (portRef AD2 (instanceRef LUT4_22))
+              (portRef AD2 (instanceRef LUT4_20))
+              (portRef AD2 (instanceRef LUT4_18))))
+          (net wptr_11_inv
+            (joined
+              (portRef AD3 (instanceRef LUT4_9))
+              (portRef Z (instanceRef INV_9))
+              (portRef AD3 (instanceRef LUT4_127))
+              (portRef AD3 (instanceRef LUT4_125))
+              (portRef AD3 (instanceRef LUT4_123))
+              (portRef AD3 (instanceRef LUT4_121))
+              (portRef AD3 (instanceRef LUT4_111))
+              (portRef AD3 (instanceRef LUT4_109))
+              (portRef AD3 (instanceRef LUT4_107))
+              (portRef AD3 (instanceRef LUT4_105))
+              (portRef AD3 (instanceRef LUT4_95))
+              (portRef AD3 (instanceRef LUT4_93))
+              (portRef AD3 (instanceRef LUT4_91))
+              (portRef AD3 (instanceRef LUT4_89))
+              (portRef AD3 (instanceRef LUT4_79))
+              (portRef AD3 (instanceRef LUT4_77))
+              (portRef AD3 (instanceRef LUT4_75))
+              (portRef AD3 (instanceRef LUT4_73))
+              (portRef AD3 (instanceRef LUT4_63))
+              (portRef AD3 (instanceRef LUT4_61))
+              (portRef AD3 (instanceRef LUT4_59))
+              (portRef AD3 (instanceRef LUT4_57))
+              (portRef AD3 (instanceRef LUT4_47))
+              (portRef AD3 (instanceRef LUT4_45))
+              (portRef AD3 (instanceRef LUT4_43))
+              (portRef AD3 (instanceRef LUT4_41))
+              (portRef AD3 (instanceRef LUT4_31))
+              (portRef AD3 (instanceRef LUT4_29))
+              (portRef AD3 (instanceRef LUT4_27))
+              (portRef AD3 (instanceRef LUT4_25))
+              (portRef AD3 (instanceRef LUT4_15))
+              (portRef AD3 (instanceRef LUT4_13))
+              (portRef AD3 (instanceRef LUT4_11))))
+          (net rptr_11_inv
+            (joined
+              (portRef AD3 (instanceRef LUT4_8))
+              (portRef Z (instanceRef INV_5))
+              (portRef AD3 (instanceRef LUT4_126))
+              (portRef AD3 (instanceRef LUT4_124))
+              (portRef AD3 (instanceRef LUT4_122))
+              (portRef AD3 (instanceRef LUT4_120))
+              (portRef AD3 (instanceRef LUT4_110))
+              (portRef AD3 (instanceRef LUT4_108))
+              (portRef AD3 (instanceRef LUT4_106))
+              (portRef AD3 (instanceRef LUT4_104))
+              (portRef AD3 (instanceRef LUT4_94))
+              (portRef AD3 (instanceRef LUT4_92))
+              (portRef AD3 (instanceRef LUT4_90))
+              (portRef AD3 (instanceRef LUT4_88))
+              (portRef AD3 (instanceRef LUT4_78))
+              (portRef AD3 (instanceRef LUT4_76))
+              (portRef AD3 (instanceRef LUT4_74))
+              (portRef AD3 (instanceRef LUT4_72))
+              (portRef AD3 (instanceRef LUT4_62))
+              (portRef AD3 (instanceRef LUT4_60))
+              (portRef AD3 (instanceRef LUT4_58))
+              (portRef AD3 (instanceRef LUT4_56))
+              (portRef AD3 (instanceRef LUT4_46))
+              (portRef AD3 (instanceRef LUT4_44))
+              (portRef AD3 (instanceRef LUT4_42))
+              (portRef AD3 (instanceRef LUT4_40))
+              (portRef AD3 (instanceRef LUT4_30))
+              (portRef AD3 (instanceRef LUT4_28))
+              (portRef AD3 (instanceRef LUT4_26))
+              (portRef AD3 (instanceRef LUT4_24))
+              (portRef AD3 (instanceRef LUT4_14))
+              (portRef AD3 (instanceRef LUT4_12))
+              (portRef AD3 (instanceRef LUT4_10))))
+          (net invout_0
+            (joined
+              (portRef Z (instanceRef INV_1))
+              (portRef B (instanceRef AND2_t1))))
+          (net r_nw
+            (joined
+              (portRef Z (instanceRef AND2_t1))))
+          (net dec1_r10
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_0_0_63))
+              (portRef DO0 (instanceRef LUT4_126))))
+          (net dec0_p00
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_0_0_63))
+              (portRef DO0 (instanceRef LUT4_127))))
+          (net dec3_r10
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_0_1_62))
+              (portRef DO0 (instanceRef LUT4_124))))
+          (net dec2_p00
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_0_1_62))
+              (portRef DO0 (instanceRef LUT4_125))))
+          (net dec5_r10
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_0_2_61))
+              (portRef DO0 (instanceRef LUT4_122))))
+          (net dec4_p00
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_0_2_61))
+              (portRef DO0 (instanceRef LUT4_123))))
+          (net dec7_r10
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_0_3_60))
+              (portRef DO0 (instanceRef LUT4_120))))
+          (net dec6_p00
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_0_3_60))
+              (portRef DO0 (instanceRef LUT4_121))))
+          (net dec9_r11
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_1_0_59))
+              (portRef DO0 (instanceRef LUT4_118))))
+          (net dec8_p01
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_1_0_59))
+              (portRef DO0 (instanceRef LUT4_119))))
+          (net dec11_r11
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_1_1_58))
+              (portRef DO0 (instanceRef LUT4_116))))
+          (net dec10_p01
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_1_1_58))
+              (portRef DO0 (instanceRef LUT4_117))))
+          (net dec13_r11
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_1_2_57))
+              (portRef DO0 (instanceRef LUT4_114))))
+          (net dec12_p01
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_1_2_57))
+              (portRef DO0 (instanceRef LUT4_115))))
+          (net dec15_r11
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_1_3_56))
+              (portRef DO0 (instanceRef LUT4_112))))
+          (net dec14_p01
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_1_3_56))
+              (portRef DO0 (instanceRef LUT4_113))))
+          (net dec17_r12
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_2_0_55))
+              (portRef DO0 (instanceRef LUT4_110))))
+          (net dec16_p02
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_2_0_55))
+              (portRef DO0 (instanceRef LUT4_111))))
+          (net dec19_r12
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_2_1_54))
+              (portRef DO0 (instanceRef LUT4_108))))
+          (net dec18_p02
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_2_1_54))
+              (portRef DO0 (instanceRef LUT4_109))))
+          (net dec21_r12
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_2_2_53))
+              (portRef DO0 (instanceRef LUT4_106))))
+          (net dec20_p02
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_2_2_53))
+              (portRef DO0 (instanceRef LUT4_107))))
+          (net dec23_r12
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_2_3_52))
+              (portRef DO0 (instanceRef LUT4_104))))
+          (net dec22_p02
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_2_3_52))
+              (portRef DO0 (instanceRef LUT4_105))))
+          (net dec25_r13
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_3_0_51))
+              (portRef DO0 (instanceRef LUT4_102))))
+          (net dec24_p03
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_3_0_51))
+              (portRef DO0 (instanceRef LUT4_103))))
+          (net dec27_r13
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_3_1_50))
+              (portRef DO0 (instanceRef LUT4_100))))
+          (net dec26_p03
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_3_1_50))
+              (portRef DO0 (instanceRef LUT4_101))))
+          (net dec29_r13
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_3_2_49))
+              (portRef DO0 (instanceRef LUT4_98))))
+          (net dec28_p03
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_3_2_49))
+              (portRef DO0 (instanceRef LUT4_99))))
+          (net dec31_r13
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_3_3_48))
+              (portRef DO0 (instanceRef LUT4_96))))
+          (net dec30_p03
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_3_3_48))
+              (portRef DO0 (instanceRef LUT4_97))))
+          (net dec33_r14
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_4_0_47))
+              (portRef DO0 (instanceRef LUT4_94))))
+          (net dec32_p04
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_4_0_47))
+              (portRef DO0 (instanceRef LUT4_95))))
+          (net dec35_r14
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_4_1_46))
+              (portRef DO0 (instanceRef LUT4_92))))
+          (net dec34_p04
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_4_1_46))
+              (portRef DO0 (instanceRef LUT4_93))))
+          (net dec37_r14
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_4_2_45))
+              (portRef DO0 (instanceRef LUT4_90))))
+          (net dec36_p04
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_4_2_45))
+              (portRef DO0 (instanceRef LUT4_91))))
+          (net dec39_r14
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_4_3_44))
+              (portRef DO0 (instanceRef LUT4_88))))
+          (net dec38_p04
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_4_3_44))
+              (portRef DO0 (instanceRef LUT4_89))))
+          (net dec41_r15
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_5_0_43))
+              (portRef DO0 (instanceRef LUT4_86))))
+          (net dec40_p05
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_5_0_43))
+              (portRef DO0 (instanceRef LUT4_87))))
+          (net dec43_r15
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_5_1_42))
+              (portRef DO0 (instanceRef LUT4_84))))
+          (net dec42_p05
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_5_1_42))
+              (portRef DO0 (instanceRef LUT4_85))))
+          (net dec45_r15
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_5_2_41))
+              (portRef DO0 (instanceRef LUT4_82))))
+          (net dec44_p05
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_5_2_41))
+              (portRef DO0 (instanceRef LUT4_83))))
+          (net dec47_r15
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_5_3_40))
+              (portRef DO0 (instanceRef LUT4_80))))
+          (net dec46_p05
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_5_3_40))
+              (portRef DO0 (instanceRef LUT4_81))))
+          (net dec49_r16
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_6_0_39))
+              (portRef DO0 (instanceRef LUT4_78))))
+          (net dec48_p06
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_6_0_39))
+              (portRef DO0 (instanceRef LUT4_79))))
+          (net dec51_r16
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_6_1_38))
+              (portRef DO0 (instanceRef LUT4_76))))
+          (net dec50_p06
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_6_1_38))
+              (portRef DO0 (instanceRef LUT4_77))))
+          (net dec53_r16
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_6_2_37))
+              (portRef DO0 (instanceRef LUT4_74))))
+          (net dec52_p06
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_6_2_37))
+              (portRef DO0 (instanceRef LUT4_75))))
+          (net dec55_r16
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_6_3_36))
+              (portRef DO0 (instanceRef LUT4_72))))
+          (net dec54_p06
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_6_3_36))
+              (portRef DO0 (instanceRef LUT4_73))))
+          (net dec57_r17
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_7_0_35))
+              (portRef DO0 (instanceRef LUT4_70))))
+          (net dec56_p07
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_7_0_35))
+              (portRef DO0 (instanceRef LUT4_71))))
+          (net dec59_r17
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_7_1_34))
+              (portRef DO0 (instanceRef LUT4_68))))
+          (net dec58_p07
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_7_1_34))
+              (portRef DO0 (instanceRef LUT4_69))))
+          (net dec61_r17
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_7_2_33))
+              (portRef DO0 (instanceRef LUT4_66))))
+          (net dec60_p07
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_7_2_33))
+              (portRef DO0 (instanceRef LUT4_67))))
+          (net dec63_r17
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_7_3_32))
+              (portRef DO0 (instanceRef LUT4_64))))
+          (net dec62_p07
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_7_3_32))
+              (portRef DO0 (instanceRef LUT4_65))))
+          (net dec65_r18
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_8_0_31))
+              (portRef DO0 (instanceRef LUT4_62))))
+          (net dec64_p08
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_8_0_31))
+              (portRef DO0 (instanceRef LUT4_63))))
+          (net dec67_r18
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_8_1_30))
+              (portRef DO0 (instanceRef LUT4_60))))
+          (net dec66_p08
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_8_1_30))
+              (portRef DO0 (instanceRef LUT4_61))))
+          (net dec69_r18
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_8_2_29))
+              (portRef DO0 (instanceRef LUT4_58))))
+          (net dec68_p08
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_8_2_29))
+              (portRef DO0 (instanceRef LUT4_59))))
+          (net dec71_r18
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_8_3_28))
+              (portRef DO0 (instanceRef LUT4_56))))
+          (net dec70_p08
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_8_3_28))
+              (portRef DO0 (instanceRef LUT4_57))))
+          (net dec73_r19
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_9_0_27))
+              (portRef DO0 (instanceRef LUT4_54))))
+          (net dec72_p09
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_9_0_27))
+              (portRef DO0 (instanceRef LUT4_55))))
+          (net dec75_r19
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_9_1_26))
+              (portRef DO0 (instanceRef LUT4_52))))
+          (net dec74_p09
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_9_1_26))
+              (portRef DO0 (instanceRef LUT4_53))))
+          (net dec77_r19
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_9_2_25))
+              (portRef DO0 (instanceRef LUT4_50))))
+          (net dec76_p09
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_9_2_25))
+              (portRef DO0 (instanceRef LUT4_51))))
+          (net dec79_r19
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_9_3_24))
+              (portRef DO0 (instanceRef LUT4_48))))
+          (net dec78_p09
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_9_3_24))
+              (portRef DO0 (instanceRef LUT4_49))))
+          (net dec81_r110
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_10_0_23))
+              (portRef DO0 (instanceRef LUT4_46))))
+          (net dec80_p010
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_10_0_23))
+              (portRef DO0 (instanceRef LUT4_47))))
+          (net dec83_r110
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_10_1_22))
+              (portRef DO0 (instanceRef LUT4_44))))
+          (net dec82_p010
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_10_1_22))
+              (portRef DO0 (instanceRef LUT4_45))))
+          (net dec85_r110
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_10_2_21))
+              (portRef DO0 (instanceRef LUT4_42))))
+          (net dec84_p010
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_10_2_21))
+              (portRef DO0 (instanceRef LUT4_43))))
+          (net dec87_r110
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_10_3_20))
+              (portRef DO0 (instanceRef LUT4_40))))
+          (net dec86_p010
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_10_3_20))
+              (portRef DO0 (instanceRef LUT4_41))))
+          (net dec89_r111
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_11_0_19))
+              (portRef DO0 (instanceRef LUT4_38))))
+          (net dec88_p011
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_11_0_19))
+              (portRef DO0 (instanceRef LUT4_39))))
+          (net dec91_r111
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_11_1_18))
+              (portRef DO0 (instanceRef LUT4_36))))
+          (net dec90_p011
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_11_1_18))
+              (portRef DO0 (instanceRef LUT4_37))))
+          (net dec93_r111
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_11_2_17))
+              (portRef DO0 (instanceRef LUT4_34))))
+          (net dec92_p011
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_11_2_17))
+              (portRef DO0 (instanceRef LUT4_35))))
+          (net dec95_r111
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_11_3_16))
+              (portRef DO0 (instanceRef LUT4_32))))
+          (net dec94_p011
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_11_3_16))
+              (portRef DO0 (instanceRef LUT4_33))))
+          (net dec97_r112
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_12_0_15))
+              (portRef DO0 (instanceRef LUT4_30))))
+          (net dec96_p012
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_12_0_15))
+              (portRef DO0 (instanceRef LUT4_31))))
+          (net dec99_r112
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_12_1_14))
+              (portRef DO0 (instanceRef LUT4_28))))
+          (net dec98_p012
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_12_1_14))
+              (portRef DO0 (instanceRef LUT4_29))))
+          (net dec101_r112
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_12_2_13))
+              (portRef DO0 (instanceRef LUT4_26))))
+          (net dec100_p012
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_12_2_13))
+              (portRef DO0 (instanceRef LUT4_27))))
+          (net dec103_r112
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_12_3_12))
+              (portRef DO0 (instanceRef LUT4_24))))
+          (net dec102_p012
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_12_3_12))
+              (portRef DO0 (instanceRef LUT4_25))))
+          (net dec105_r113
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_13_0_11))
+              (portRef DO0 (instanceRef LUT4_22))))
+          (net dec104_p013
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_13_0_11))
+              (portRef DO0 (instanceRef LUT4_23))))
+          (net dec107_r113
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_13_1_10))
+              (portRef DO0 (instanceRef LUT4_20))))
+          (net dec106_p013
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_13_1_10))
+              (portRef DO0 (instanceRef LUT4_21))))
+          (net dec109_r113
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_13_2_9))
+              (portRef DO0 (instanceRef LUT4_18))))
+          (net dec108_p013
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_13_2_9))
+              (portRef DO0 (instanceRef LUT4_19))))
+          (net dec111_r113
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_13_3_8))
+              (portRef DO0 (instanceRef LUT4_16))))
+          (net dec110_p013
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_13_3_8))
+              (portRef DO0 (instanceRef LUT4_17))))
+          (net dec113_r114
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_14_0_7))
+              (portRef DO0 (instanceRef LUT4_14))))
+          (net dec112_p014
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_14_0_7))
+              (portRef DO0 (instanceRef LUT4_15))))
+          (net dec115_r114
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_14_1_6))
+              (portRef DO0 (instanceRef LUT4_12))))
+          (net dec114_p014
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_14_1_6))
+              (portRef DO0 (instanceRef LUT4_13))))
+          (net dec117_r114
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_14_2_5))
+              (portRef DO0 (instanceRef LUT4_10))))
+          (net dec116_p014
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_14_2_5))
+              (portRef DO0 (instanceRef LUT4_11))))
+          (net dec119_r114
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_14_3_4))
+              (portRef DO0 (instanceRef LUT4_8))))
+          (net dec118_p014
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_14_3_4))
+              (portRef DO0 (instanceRef LUT4_9))))
+          (net dec121_r115
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_15_0_3))
+              (portRef DO0 (instanceRef LUT4_6))))
+          (net dec120_p015
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_15_0_3))
+              (portRef DO0 (instanceRef LUT4_7))))
+          (net dec123_r115
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_15_1_2))
+              (portRef DO0 (instanceRef LUT4_4))))
+          (net dec122_p015
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_15_1_2))
+              (portRef DO0 (instanceRef LUT4_5))))
+          (net dec125_r115
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_15_2_1))
+              (portRef DO0 (instanceRef LUT4_2))))
+          (net dec124_p015
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_15_2_1))
+              (portRef DO0 (instanceRef LUT4_3))))
+          (net dec127_r115
+            (joined
+              (portRef CSB0 (instanceRef pdp_ram_15_3_0))
+              (portRef DO0 (instanceRef LUT4_0))))
+          (net dec126_p015
+            (joined
+              (portRef CSA0 (instanceRef pdp_ram_15_3_0))
+              (portRef DO0 (instanceRef LUT4_1))))
+          (net fcnt_en
+            (joined
+              (portRef SP (instanceRef FF_91))
+              (portRef Z (instanceRef XOR2_t2))
+              (portRef SP (instanceRef FF_106))
+              (portRef SP (instanceRef FF_105))
+              (portRef SP (instanceRef FF_104))
+              (portRef SP (instanceRef FF_103))
+              (portRef SP (instanceRef FF_102))
+              (portRef SP (instanceRef FF_101))
+              (portRef SP (instanceRef FF_100))
+              (portRef SP (instanceRef FF_99))
+              (portRef SP (instanceRef FF_98))
+              (portRef SP (instanceRef FF_97))
+              (portRef SP (instanceRef FF_96))
+              (portRef SP (instanceRef FF_95))
+              (portRef SP (instanceRef FF_94))
+              (portRef SP (instanceRef FF_93))
+              (portRef SP (instanceRef FF_92))))
+          (net empty_d
+            (joined
+              (portRef D (instanceRef FF_90))
+              (portRef DO0 (instanceRef LUT4_129))))
+          (net full_d
+            (joined
+              (portRef D (instanceRef FF_89))
+              (portRef DO0 (instanceRef LUT4_128))))
+          (net wptr_0
+            (joined
+              (portRef Q (instanceRef FF_56))
+              (portRef ADA3 (instanceRef pdp_ram_0_0_63))
+              (portRef ADA3 (instanceRef pdp_ram_0_1_62))
+              (portRef ADA3 (instanceRef pdp_ram_0_2_61))
+              (portRef ADA3 (instanceRef pdp_ram_0_3_60))
+              (portRef ADA3 (instanceRef pdp_ram_1_0_59))
+              (portRef ADA3 (instanceRef pdp_ram_1_1_58))
+              (portRef ADA3 (instanceRef pdp_ram_1_2_57))
+              (portRef ADA3 (instanceRef pdp_ram_1_3_56))
+              (portRef ADA3 (instanceRef pdp_ram_2_0_55))
+              (portRef ADA3 (instanceRef pdp_ram_2_1_54))
+              (portRef ADA3 (instanceRef pdp_ram_2_2_53))
+              (portRef ADA3 (instanceRef pdp_ram_2_3_52))
+              (portRef ADA3 (instanceRef pdp_ram_3_0_51))
+              (portRef ADA3 (instanceRef pdp_ram_3_1_50))
+              (portRef ADA3 (instanceRef pdp_ram_3_2_49))
+              (portRef ADA3 (instanceRef pdp_ram_3_3_48))
+              (portRef ADA3 (instanceRef pdp_ram_4_0_47))
+              (portRef ADA3 (instanceRef pdp_ram_4_1_46))
+              (portRef ADA3 (instanceRef pdp_ram_4_2_45))
+              (portRef ADA3 (instanceRef pdp_ram_4_3_44))
+              (portRef ADA3 (instanceRef pdp_ram_5_0_43))
+              (portRef ADA3 (instanceRef pdp_ram_5_1_42))
+              (portRef ADA3 (instanceRef pdp_ram_5_2_41))
+              (portRef ADA3 (instanceRef pdp_ram_5_3_40))
+              (portRef ADA3 (instanceRef pdp_ram_6_0_39))
+              (portRef ADA3 (instanceRef pdp_ram_6_1_38))
+              (portRef ADA3 (instanceRef pdp_ram_6_2_37))
+              (portRef ADA3 (instanceRef pdp_ram_6_3_36))
+              (portRef ADA3 (instanceRef pdp_ram_7_0_35))
+              (portRef ADA3 (instanceRef pdp_ram_7_1_34))
+              (portRef ADA3 (instanceRef pdp_ram_7_2_33))
+              (portRef ADA3 (instanceRef pdp_ram_7_3_32))
+              (portRef ADA3 (instanceRef pdp_ram_8_0_31))
+              (portRef ADA3 (instanceRef pdp_ram_8_1_30))
+              (portRef ADA3 (instanceRef pdp_ram_8_2_29))
+              (portRef ADA3 (instanceRef pdp_ram_8_3_28))
+              (portRef ADA3 (instanceRef pdp_ram_9_0_27))
+              (portRef ADA3 (instanceRef pdp_ram_9_1_26))
+              (portRef ADA3 (instanceRef pdp_ram_9_2_25))
+              (portRef ADA3 (instanceRef pdp_ram_9_3_24))
+              (portRef ADA3 (instanceRef pdp_ram_10_0_23))
+              (portRef ADA3 (instanceRef pdp_ram_10_1_22))
+              (portRef ADA3 (instanceRef pdp_ram_10_2_21))
+              (portRef ADA3 (instanceRef pdp_ram_10_3_20))
+              (portRef ADA3 (instanceRef pdp_ram_11_0_19))
+              (portRef ADA3 (instanceRef pdp_ram_11_1_18))
+              (portRef ADA3 (instanceRef pdp_ram_11_2_17))
+              (portRef ADA3 (instanceRef pdp_ram_11_3_16))
+              (portRef ADA3 (instanceRef pdp_ram_12_0_15))
+              (portRef ADA3 (instanceRef pdp_ram_12_1_14))
+              (portRef ADA3 (instanceRef pdp_ram_12_2_13))
+              (portRef ADA3 (instanceRef pdp_ram_12_3_12))
+              (portRef ADA3 (instanceRef pdp_ram_13_0_11))
+              (portRef ADA3 (instanceRef pdp_ram_13_1_10))
+              (portRef ADA3 (instanceRef pdp_ram_13_2_9))
+              (portRef ADA3 (instanceRef pdp_ram_13_3_8))
+              (portRef ADA3 (instanceRef pdp_ram_14_0_7))
+              (portRef ADA3 (instanceRef pdp_ram_14_1_6))
+              (portRef ADA3 (instanceRef pdp_ram_14_2_5))
+              (portRef ADA3 (instanceRef pdp_ram_14_3_4))
+              (portRef ADA3 (instanceRef pdp_ram_15_0_3))
+              (portRef ADA3 (instanceRef pdp_ram_15_1_2))
+              (portRef ADA3 (instanceRef pdp_ram_15_2_1))
+              (portRef ADA3 (instanceRef pdp_ram_15_3_0))))
+          (net wptr_1
+            (joined
+              (portRef Q (instanceRef FF_55))
+              (portRef ADA4 (instanceRef pdp_ram_0_0_63))
+              (portRef ADA4 (instanceRef pdp_ram_0_1_62))
+              (portRef ADA4 (instanceRef pdp_ram_0_2_61))
+              (portRef ADA4 (instanceRef pdp_ram_0_3_60))
+              (portRef ADA4 (instanceRef pdp_ram_1_0_59))
+              (portRef ADA4 (instanceRef pdp_ram_1_1_58))
+              (portRef ADA4 (instanceRef pdp_ram_1_2_57))
+              (portRef ADA4 (instanceRef pdp_ram_1_3_56))
+              (portRef ADA4 (instanceRef pdp_ram_2_0_55))
+              (portRef ADA4 (instanceRef pdp_ram_2_1_54))
+              (portRef ADA4 (instanceRef pdp_ram_2_2_53))
+              (portRef ADA4 (instanceRef pdp_ram_2_3_52))
+              (portRef ADA4 (instanceRef pdp_ram_3_0_51))
+              (portRef ADA4 (instanceRef pdp_ram_3_1_50))
+              (portRef ADA4 (instanceRef pdp_ram_3_2_49))
+              (portRef ADA4 (instanceRef pdp_ram_3_3_48))
+              (portRef ADA4 (instanceRef pdp_ram_4_0_47))
+              (portRef ADA4 (instanceRef pdp_ram_4_1_46))
+              (portRef ADA4 (instanceRef pdp_ram_4_2_45))
+              (portRef ADA4 (instanceRef pdp_ram_4_3_44))
+              (portRef ADA4 (instanceRef pdp_ram_5_0_43))
+              (portRef ADA4 (instanceRef pdp_ram_5_1_42))
+              (portRef ADA4 (instanceRef pdp_ram_5_2_41))
+              (portRef ADA4 (instanceRef pdp_ram_5_3_40))
+              (portRef ADA4 (instanceRef pdp_ram_6_0_39))
+              (portRef ADA4 (instanceRef pdp_ram_6_1_38))
+              (portRef ADA4 (instanceRef pdp_ram_6_2_37))
+              (portRef ADA4 (instanceRef pdp_ram_6_3_36))
+              (portRef ADA4 (instanceRef pdp_ram_7_0_35))
+              (portRef ADA4 (instanceRef pdp_ram_7_1_34))
+              (portRef ADA4 (instanceRef pdp_ram_7_2_33))
+              (portRef ADA4 (instanceRef pdp_ram_7_3_32))
+              (portRef ADA4 (instanceRef pdp_ram_8_0_31))
+              (portRef ADA4 (instanceRef pdp_ram_8_1_30))
+              (portRef ADA4 (instanceRef pdp_ram_8_2_29))
+              (portRef ADA4 (instanceRef pdp_ram_8_3_28))
+              (portRef ADA4 (instanceRef pdp_ram_9_0_27))
+              (portRef ADA4 (instanceRef pdp_ram_9_1_26))
+              (portRef ADA4 (instanceRef pdp_ram_9_2_25))
+              (portRef ADA4 (instanceRef pdp_ram_9_3_24))
+              (portRef ADA4 (instanceRef pdp_ram_10_0_23))
+              (portRef ADA4 (instanceRef pdp_ram_10_1_22))
+              (portRef ADA4 (instanceRef pdp_ram_10_2_21))
+              (portRef ADA4 (instanceRef pdp_ram_10_3_20))
+              (portRef ADA4 (instanceRef pdp_ram_11_0_19))
+              (portRef ADA4 (instanceRef pdp_ram_11_1_18))
+              (portRef ADA4 (instanceRef pdp_ram_11_2_17))
+              (portRef ADA4 (instanceRef pdp_ram_11_3_16))
+              (portRef ADA4 (instanceRef pdp_ram_12_0_15))
+              (portRef ADA4 (instanceRef pdp_ram_12_1_14))
+              (portRef ADA4 (instanceRef pdp_ram_12_2_13))
+              (portRef ADA4 (instanceRef pdp_ram_12_3_12))
+              (portRef ADA4 (instanceRef pdp_ram_13_0_11))
+              (portRef ADA4 (instanceRef pdp_ram_13_1_10))
+              (portRef ADA4 (instanceRef pdp_ram_13_2_9))
+              (portRef ADA4 (instanceRef pdp_ram_13_3_8))
+              (portRef ADA4 (instanceRef pdp_ram_14_0_7))
+              (portRef ADA4 (instanceRef pdp_ram_14_1_6))
+              (portRef ADA4 (instanceRef pdp_ram_14_2_5))
+              (portRef ADA4 (instanceRef pdp_ram_14_3_4))
+              (portRef ADA4 (instanceRef pdp_ram_15_0_3))
+              (portRef ADA4 (instanceRef pdp_ram_15_1_2))
+              (portRef ADA4 (instanceRef pdp_ram_15_2_1))
+              (portRef ADA4 (instanceRef pdp_ram_15_3_0))))
+          (net wptr_2
+            (joined
+              (portRef Q (instanceRef FF_54))
+              (portRef ADA5 (instanceRef pdp_ram_0_0_63))
+              (portRef ADA5 (instanceRef pdp_ram_0_1_62))
+              (portRef ADA5 (instanceRef pdp_ram_0_2_61))
+              (portRef ADA5 (instanceRef pdp_ram_0_3_60))
+              (portRef ADA5 (instanceRef pdp_ram_1_0_59))
+              (portRef ADA5 (instanceRef pdp_ram_1_1_58))
+              (portRef ADA5 (instanceRef pdp_ram_1_2_57))
+              (portRef ADA5 (instanceRef pdp_ram_1_3_56))
+              (portRef ADA5 (instanceRef pdp_ram_2_0_55))
+              (portRef ADA5 (instanceRef pdp_ram_2_1_54))
+              (portRef ADA5 (instanceRef pdp_ram_2_2_53))
+              (portRef ADA5 (instanceRef pdp_ram_2_3_52))
+              (portRef ADA5 (instanceRef pdp_ram_3_0_51))
+              (portRef ADA5 (instanceRef pdp_ram_3_1_50))
+              (portRef ADA5 (instanceRef pdp_ram_3_2_49))
+              (portRef ADA5 (instanceRef pdp_ram_3_3_48))
+              (portRef ADA5 (instanceRef pdp_ram_4_0_47))
+              (portRef ADA5 (instanceRef pdp_ram_4_1_46))
+              (portRef ADA5 (instanceRef pdp_ram_4_2_45))
+              (portRef ADA5 (instanceRef pdp_ram_4_3_44))
+              (portRef ADA5 (instanceRef pdp_ram_5_0_43))
+              (portRef ADA5 (instanceRef pdp_ram_5_1_42))
+              (portRef ADA5 (instanceRef pdp_ram_5_2_41))
+              (portRef ADA5 (instanceRef pdp_ram_5_3_40))
+              (portRef ADA5 (instanceRef pdp_ram_6_0_39))
+              (portRef ADA5 (instanceRef pdp_ram_6_1_38))
+              (portRef ADA5 (instanceRef pdp_ram_6_2_37))
+              (portRef ADA5 (instanceRef pdp_ram_6_3_36))
+              (portRef ADA5 (instanceRef pdp_ram_7_0_35))
+              (portRef ADA5 (instanceRef pdp_ram_7_1_34))
+              (portRef ADA5 (instanceRef pdp_ram_7_2_33))
+              (portRef ADA5 (instanceRef pdp_ram_7_3_32))
+              (portRef ADA5 (instanceRef pdp_ram_8_0_31))
+              (portRef ADA5 (instanceRef pdp_ram_8_1_30))
+              (portRef ADA5 (instanceRef pdp_ram_8_2_29))
+              (portRef ADA5 (instanceRef pdp_ram_8_3_28))
+              (portRef ADA5 (instanceRef pdp_ram_9_0_27))
+              (portRef ADA5 (instanceRef pdp_ram_9_1_26))
+              (portRef ADA5 (instanceRef pdp_ram_9_2_25))
+              (portRef ADA5 (instanceRef pdp_ram_9_3_24))
+              (portRef ADA5 (instanceRef pdp_ram_10_0_23))
+              (portRef ADA5 (instanceRef pdp_ram_10_1_22))
+              (portRef ADA5 (instanceRef pdp_ram_10_2_21))
+              (portRef ADA5 (instanceRef pdp_ram_10_3_20))
+              (portRef ADA5 (instanceRef pdp_ram_11_0_19))
+              (portRef ADA5 (instanceRef pdp_ram_11_1_18))
+              (portRef ADA5 (instanceRef pdp_ram_11_2_17))
+              (portRef ADA5 (instanceRef pdp_ram_11_3_16))
+              (portRef ADA5 (instanceRef pdp_ram_12_0_15))
+              (portRef ADA5 (instanceRef pdp_ram_12_1_14))
+              (portRef ADA5 (instanceRef pdp_ram_12_2_13))
+              (portRef ADA5 (instanceRef pdp_ram_12_3_12))
+              (portRef ADA5 (instanceRef pdp_ram_13_0_11))
+              (portRef ADA5 (instanceRef pdp_ram_13_1_10))
+              (portRef ADA5 (instanceRef pdp_ram_13_2_9))
+              (portRef ADA5 (instanceRef pdp_ram_13_3_8))
+              (portRef ADA5 (instanceRef pdp_ram_14_0_7))
+              (portRef ADA5 (instanceRef pdp_ram_14_1_6))
+              (portRef ADA5 (instanceRef pdp_ram_14_2_5))
+              (portRef ADA5 (instanceRef pdp_ram_14_3_4))
+              (portRef ADA5 (instanceRef pdp_ram_15_0_3))
+              (portRef ADA5 (instanceRef pdp_ram_15_1_2))
+              (portRef ADA5 (instanceRef pdp_ram_15_2_1))
+              (portRef ADA5 (instanceRef pdp_ram_15_3_0))))
+          (net wptr_3
+            (joined
+              (portRef Q (instanceRef FF_53))
+              (portRef ADA6 (instanceRef pdp_ram_0_0_63))
+              (portRef ADA6 (instanceRef pdp_ram_0_1_62))
+              (portRef ADA6 (instanceRef pdp_ram_0_2_61))
+              (portRef ADA6 (instanceRef pdp_ram_0_3_60))
+              (portRef ADA6 (instanceRef pdp_ram_1_0_59))
+              (portRef ADA6 (instanceRef pdp_ram_1_1_58))
+              (portRef ADA6 (instanceRef pdp_ram_1_2_57))
+              (portRef ADA6 (instanceRef pdp_ram_1_3_56))
+              (portRef ADA6 (instanceRef pdp_ram_2_0_55))
+              (portRef ADA6 (instanceRef pdp_ram_2_1_54))
+              (portRef ADA6 (instanceRef pdp_ram_2_2_53))
+              (portRef ADA6 (instanceRef pdp_ram_2_3_52))
+              (portRef ADA6 (instanceRef pdp_ram_3_0_51))
+              (portRef ADA6 (instanceRef pdp_ram_3_1_50))
+              (portRef ADA6 (instanceRef pdp_ram_3_2_49))
+              (portRef ADA6 (instanceRef pdp_ram_3_3_48))
+              (portRef ADA6 (instanceRef pdp_ram_4_0_47))
+              (portRef ADA6 (instanceRef pdp_ram_4_1_46))
+              (portRef ADA6 (instanceRef pdp_ram_4_2_45))
+              (portRef ADA6 (instanceRef pdp_ram_4_3_44))
+              (portRef ADA6 (instanceRef pdp_ram_5_0_43))
+              (portRef ADA6 (instanceRef pdp_ram_5_1_42))
+              (portRef ADA6 (instanceRef pdp_ram_5_2_41))
+              (portRef ADA6 (instanceRef pdp_ram_5_3_40))
+              (portRef ADA6 (instanceRef pdp_ram_6_0_39))
+              (portRef ADA6 (instanceRef pdp_ram_6_1_38))
+              (portRef ADA6 (instanceRef pdp_ram_6_2_37))
+              (portRef ADA6 (instanceRef pdp_ram_6_3_36))
+              (portRef ADA6 (instanceRef pdp_ram_7_0_35))
+              (portRef ADA6 (instanceRef pdp_ram_7_1_34))
+              (portRef ADA6 (instanceRef pdp_ram_7_2_33))
+              (portRef ADA6 (instanceRef pdp_ram_7_3_32))
+              (portRef ADA6 (instanceRef pdp_ram_8_0_31))
+              (portRef ADA6 (instanceRef pdp_ram_8_1_30))
+              (portRef ADA6 (instanceRef pdp_ram_8_2_29))
+              (portRef ADA6 (instanceRef pdp_ram_8_3_28))
+              (portRef ADA6 (instanceRef pdp_ram_9_0_27))
+              (portRef ADA6 (instanceRef pdp_ram_9_1_26))
+              (portRef ADA6 (instanceRef pdp_ram_9_2_25))
+              (portRef ADA6 (instanceRef pdp_ram_9_3_24))
+              (portRef ADA6 (instanceRef pdp_ram_10_0_23))
+              (portRef ADA6 (instanceRef pdp_ram_10_1_22))
+              (portRef ADA6 (instanceRef pdp_ram_10_2_21))
+              (portRef ADA6 (instanceRef pdp_ram_10_3_20))
+              (portRef ADA6 (instanceRef pdp_ram_11_0_19))
+              (portRef ADA6 (instanceRef pdp_ram_11_1_18))
+              (portRef ADA6 (instanceRef pdp_ram_11_2_17))
+              (portRef ADA6 (instanceRef pdp_ram_11_3_16))
+              (portRef ADA6 (instanceRef pdp_ram_12_0_15))
+              (portRef ADA6 (instanceRef pdp_ram_12_1_14))
+              (portRef ADA6 (instanceRef pdp_ram_12_2_13))
+              (portRef ADA6 (instanceRef pdp_ram_12_3_12))
+              (portRef ADA6 (instanceRef pdp_ram_13_0_11))
+              (portRef ADA6 (instanceRef pdp_ram_13_1_10))
+              (portRef ADA6 (instanceRef pdp_ram_13_2_9))
+              (portRef ADA6 (instanceRef pdp_ram_13_3_8))
+              (portRef ADA6 (instanceRef pdp_ram_14_0_7))
+              (portRef ADA6 (instanceRef pdp_ram_14_1_6))
+              (portRef ADA6 (instanceRef pdp_ram_14_2_5))
+              (portRef ADA6 (instanceRef pdp_ram_14_3_4))
+              (portRef ADA6 (instanceRef pdp_ram_15_0_3))
+              (portRef ADA6 (instanceRef pdp_ram_15_1_2))
+              (portRef ADA6 (instanceRef pdp_ram_15_2_1))
+              (portRef ADA6 (instanceRef pdp_ram_15_3_0))))
+          (net wptr_4
+            (joined
+              (portRef Q (instanceRef FF_52))
+              (portRef ADA7 (instanceRef pdp_ram_0_0_63))
+              (portRef ADA7 (instanceRef pdp_ram_0_1_62))
+              (portRef ADA7 (instanceRef pdp_ram_0_2_61))
+              (portRef ADA7 (instanceRef pdp_ram_0_3_60))
+              (portRef ADA7 (instanceRef pdp_ram_1_0_59))
+              (portRef ADA7 (instanceRef pdp_ram_1_1_58))
+              (portRef ADA7 (instanceRef pdp_ram_1_2_57))
+              (portRef ADA7 (instanceRef pdp_ram_1_3_56))
+              (portRef ADA7 (instanceRef pdp_ram_2_0_55))
+              (portRef ADA7 (instanceRef pdp_ram_2_1_54))
+              (portRef ADA7 (instanceRef pdp_ram_2_2_53))
+              (portRef ADA7 (instanceRef pdp_ram_2_3_52))
+              (portRef ADA7 (instanceRef pdp_ram_3_0_51))
+              (portRef ADA7 (instanceRef pdp_ram_3_1_50))
+              (portRef ADA7 (instanceRef pdp_ram_3_2_49))
+              (portRef ADA7 (instanceRef pdp_ram_3_3_48))
+              (portRef ADA7 (instanceRef pdp_ram_4_0_47))
+              (portRef ADA7 (instanceRef pdp_ram_4_1_46))
+              (portRef ADA7 (instanceRef pdp_ram_4_2_45))
+              (portRef ADA7 (instanceRef pdp_ram_4_3_44))
+              (portRef ADA7 (instanceRef pdp_ram_5_0_43))
+              (portRef ADA7 (instanceRef pdp_ram_5_1_42))
+              (portRef ADA7 (instanceRef pdp_ram_5_2_41))
+              (portRef ADA7 (instanceRef pdp_ram_5_3_40))
+              (portRef ADA7 (instanceRef pdp_ram_6_0_39))
+              (portRef ADA7 (instanceRef pdp_ram_6_1_38))
+              (portRef ADA7 (instanceRef pdp_ram_6_2_37))
+              (portRef ADA7 (instanceRef pdp_ram_6_3_36))
+              (portRef ADA7 (instanceRef pdp_ram_7_0_35))
+              (portRef ADA7 (instanceRef pdp_ram_7_1_34))
+              (portRef ADA7 (instanceRef pdp_ram_7_2_33))
+              (portRef ADA7 (instanceRef pdp_ram_7_3_32))
+              (portRef ADA7 (instanceRef pdp_ram_8_0_31))
+              (portRef ADA7 (instanceRef pdp_ram_8_1_30))
+              (portRef ADA7 (instanceRef pdp_ram_8_2_29))
+              (portRef ADA7 (instanceRef pdp_ram_8_3_28))
+              (portRef ADA7 (instanceRef pdp_ram_9_0_27))
+              (portRef ADA7 (instanceRef pdp_ram_9_1_26))
+              (portRef ADA7 (instanceRef pdp_ram_9_2_25))
+              (portRef ADA7 (instanceRef pdp_ram_9_3_24))
+              (portRef ADA7 (instanceRef pdp_ram_10_0_23))
+              (portRef ADA7 (instanceRef pdp_ram_10_1_22))
+              (portRef ADA7 (instanceRef pdp_ram_10_2_21))
+              (portRef ADA7 (instanceRef pdp_ram_10_3_20))
+              (portRef ADA7 (instanceRef pdp_ram_11_0_19))
+              (portRef ADA7 (instanceRef pdp_ram_11_1_18))
+              (portRef ADA7 (instanceRef pdp_ram_11_2_17))
+              (portRef ADA7 (instanceRef pdp_ram_11_3_16))
+              (portRef ADA7 (instanceRef pdp_ram_12_0_15))
+              (portRef ADA7 (instanceRef pdp_ram_12_1_14))
+              (portRef ADA7 (instanceRef pdp_ram_12_2_13))
+              (portRef ADA7 (instanceRef pdp_ram_12_3_12))
+              (portRef ADA7 (instanceRef pdp_ram_13_0_11))
+              (portRef ADA7 (instanceRef pdp_ram_13_1_10))
+              (portRef ADA7 (instanceRef pdp_ram_13_2_9))
+              (portRef ADA7 (instanceRef pdp_ram_13_3_8))
+              (portRef ADA7 (instanceRef pdp_ram_14_0_7))
+              (portRef ADA7 (instanceRef pdp_ram_14_1_6))
+              (portRef ADA7 (instanceRef pdp_ram_14_2_5))
+              (portRef ADA7 (instanceRef pdp_ram_14_3_4))
+              (portRef ADA7 (instanceRef pdp_ram_15_0_3))
+              (portRef ADA7 (instanceRef pdp_ram_15_1_2))
+              (portRef ADA7 (instanceRef pdp_ram_15_2_1))
+              (portRef ADA7 (instanceRef pdp_ram_15_3_0))))
+          (net wptr_5
+            (joined
+              (portRef Q (instanceRef FF_51))
+              (portRef ADA8 (instanceRef pdp_ram_0_0_63))
+              (portRef ADA8 (instanceRef pdp_ram_0_1_62))
+              (portRef ADA8 (instanceRef pdp_ram_0_2_61))
+              (portRef ADA8 (instanceRef pdp_ram_0_3_60))
+              (portRef ADA8 (instanceRef pdp_ram_1_0_59))
+              (portRef ADA8 (instanceRef pdp_ram_1_1_58))
+              (portRef ADA8 (instanceRef pdp_ram_1_2_57))
+              (portRef ADA8 (instanceRef pdp_ram_1_3_56))
+              (portRef ADA8 (instanceRef pdp_ram_2_0_55))
+              (portRef ADA8 (instanceRef pdp_ram_2_1_54))
+              (portRef ADA8 (instanceRef pdp_ram_2_2_53))
+              (portRef ADA8 (instanceRef pdp_ram_2_3_52))
+              (portRef ADA8 (instanceRef pdp_ram_3_0_51))
+              (portRef ADA8 (instanceRef pdp_ram_3_1_50))
+              (portRef ADA8 (instanceRef pdp_ram_3_2_49))
+              (portRef ADA8 (instanceRef pdp_ram_3_3_48))
+              (portRef ADA8 (instanceRef pdp_ram_4_0_47))
+              (portRef ADA8 (instanceRef pdp_ram_4_1_46))
+              (portRef ADA8 (instanceRef pdp_ram_4_2_45))
+              (portRef ADA8 (instanceRef pdp_ram_4_3_44))
+              (portRef ADA8 (instanceRef pdp_ram_5_0_43))
+              (portRef ADA8 (instanceRef pdp_ram_5_1_42))
+              (portRef ADA8 (instanceRef pdp_ram_5_2_41))
+              (portRef ADA8 (instanceRef pdp_ram_5_3_40))
+              (portRef ADA8 (instanceRef pdp_ram_6_0_39))
+              (portRef ADA8 (instanceRef pdp_ram_6_1_38))
+              (portRef ADA8 (instanceRef pdp_ram_6_2_37))
+              (portRef ADA8 (instanceRef pdp_ram_6_3_36))
+              (portRef ADA8 (instanceRef pdp_ram_7_0_35))
+              (portRef ADA8 (instanceRef pdp_ram_7_1_34))
+              (portRef ADA8 (instanceRef pdp_ram_7_2_33))
+              (portRef ADA8 (instanceRef pdp_ram_7_3_32))
+              (portRef ADA8 (instanceRef pdp_ram_8_0_31))
+              (portRef ADA8 (instanceRef pdp_ram_8_1_30))
+              (portRef ADA8 (instanceRef pdp_ram_8_2_29))
+              (portRef ADA8 (instanceRef pdp_ram_8_3_28))
+              (portRef ADA8 (instanceRef pdp_ram_9_0_27))
+              (portRef ADA8 (instanceRef pdp_ram_9_1_26))
+              (portRef ADA8 (instanceRef pdp_ram_9_2_25))
+              (portRef ADA8 (instanceRef pdp_ram_9_3_24))
+              (portRef ADA8 (instanceRef pdp_ram_10_0_23))
+              (portRef ADA8 (instanceRef pdp_ram_10_1_22))
+              (portRef ADA8 (instanceRef pdp_ram_10_2_21))
+              (portRef ADA8 (instanceRef pdp_ram_10_3_20))
+              (portRef ADA8 (instanceRef pdp_ram_11_0_19))
+              (portRef ADA8 (instanceRef pdp_ram_11_1_18))
+              (portRef ADA8 (instanceRef pdp_ram_11_2_17))
+              (portRef ADA8 (instanceRef pdp_ram_11_3_16))
+              (portRef ADA8 (instanceRef pdp_ram_12_0_15))
+              (portRef ADA8 (instanceRef pdp_ram_12_1_14))
+              (portRef ADA8 (instanceRef pdp_ram_12_2_13))
+              (portRef ADA8 (instanceRef pdp_ram_12_3_12))
+              (portRef ADA8 (instanceRef pdp_ram_13_0_11))
+              (portRef ADA8 (instanceRef pdp_ram_13_1_10))
+              (portRef ADA8 (instanceRef pdp_ram_13_2_9))
+              (portRef ADA8 (instanceRef pdp_ram_13_3_8))
+              (portRef ADA8 (instanceRef pdp_ram_14_0_7))
+              (portRef ADA8 (instanceRef pdp_ram_14_1_6))
+              (portRef ADA8 (instanceRef pdp_ram_14_2_5))
+              (portRef ADA8 (instanceRef pdp_ram_14_3_4))
+              (portRef ADA8 (instanceRef pdp_ram_15_0_3))
+              (portRef ADA8 (instanceRef pdp_ram_15_1_2))
+              (portRef ADA8 (instanceRef pdp_ram_15_2_1))
+              (portRef ADA8 (instanceRef pdp_ram_15_3_0))))
+          (net wptr_6
+            (joined
+              (portRef Q (instanceRef FF_50))
+              (portRef ADA9 (instanceRef pdp_ram_0_0_63))
+              (portRef ADA9 (instanceRef pdp_ram_0_1_62))
+              (portRef ADA9 (instanceRef pdp_ram_0_2_61))
+              (portRef ADA9 (instanceRef pdp_ram_0_3_60))
+              (portRef ADA9 (instanceRef pdp_ram_1_0_59))
+              (portRef ADA9 (instanceRef pdp_ram_1_1_58))
+              (portRef ADA9 (instanceRef pdp_ram_1_2_57))
+              (portRef ADA9 (instanceRef pdp_ram_1_3_56))
+              (portRef ADA9 (instanceRef pdp_ram_2_0_55))
+              (portRef ADA9 (instanceRef pdp_ram_2_1_54))
+              (portRef ADA9 (instanceRef pdp_ram_2_2_53))
+              (portRef ADA9 (instanceRef pdp_ram_2_3_52))
+              (portRef ADA9 (instanceRef pdp_ram_3_0_51))
+              (portRef ADA9 (instanceRef pdp_ram_3_1_50))
+              (portRef ADA9 (instanceRef pdp_ram_3_2_49))
+              (portRef ADA9 (instanceRef pdp_ram_3_3_48))
+              (portRef ADA9 (instanceRef pdp_ram_4_0_47))
+              (portRef ADA9 (instanceRef pdp_ram_4_1_46))
+              (portRef ADA9 (instanceRef pdp_ram_4_2_45))
+              (portRef ADA9 (instanceRef pdp_ram_4_3_44))
+              (portRef ADA9 (instanceRef pdp_ram_5_0_43))
+              (portRef ADA9 (instanceRef pdp_ram_5_1_42))
+              (portRef ADA9 (instanceRef pdp_ram_5_2_41))
+              (portRef ADA9 (instanceRef pdp_ram_5_3_40))
+              (portRef ADA9 (instanceRef pdp_ram_6_0_39))
+              (portRef ADA9 (instanceRef pdp_ram_6_1_38))
+              (portRef ADA9 (instanceRef pdp_ram_6_2_37))
+              (portRef ADA9 (instanceRef pdp_ram_6_3_36))
+              (portRef ADA9 (instanceRef pdp_ram_7_0_35))
+              (portRef ADA9 (instanceRef pdp_ram_7_1_34))
+              (portRef ADA9 (instanceRef pdp_ram_7_2_33))
+              (portRef ADA9 (instanceRef pdp_ram_7_3_32))
+              (portRef ADA9 (instanceRef pdp_ram_8_0_31))
+              (portRef ADA9 (instanceRef pdp_ram_8_1_30))
+              (portRef ADA9 (instanceRef pdp_ram_8_2_29))
+              (portRef ADA9 (instanceRef pdp_ram_8_3_28))
+              (portRef ADA9 (instanceRef pdp_ram_9_0_27))
+              (portRef ADA9 (instanceRef pdp_ram_9_1_26))
+              (portRef ADA9 (instanceRef pdp_ram_9_2_25))
+              (portRef ADA9 (instanceRef pdp_ram_9_3_24))
+              (portRef ADA9 (instanceRef pdp_ram_10_0_23))
+              (portRef ADA9 (instanceRef pdp_ram_10_1_22))
+              (portRef ADA9 (instanceRef pdp_ram_10_2_21))
+              (portRef ADA9 (instanceRef pdp_ram_10_3_20))
+              (portRef ADA9 (instanceRef pdp_ram_11_0_19))
+              (portRef ADA9 (instanceRef pdp_ram_11_1_18))
+              (portRef ADA9 (instanceRef pdp_ram_11_2_17))
+              (portRef ADA9 (instanceRef pdp_ram_11_3_16))
+              (portRef ADA9 (instanceRef pdp_ram_12_0_15))
+              (portRef ADA9 (instanceRef pdp_ram_12_1_14))
+              (portRef ADA9 (instanceRef pdp_ram_12_2_13))
+              (portRef ADA9 (instanceRef pdp_ram_12_3_12))
+              (portRef ADA9 (instanceRef pdp_ram_13_0_11))
+              (portRef ADA9 (instanceRef pdp_ram_13_1_10))
+              (portRef ADA9 (instanceRef pdp_ram_13_2_9))
+              (portRef ADA9 (instanceRef pdp_ram_13_3_8))
+              (portRef ADA9 (instanceRef pdp_ram_14_0_7))
+              (portRef ADA9 (instanceRef pdp_ram_14_1_6))
+              (portRef ADA9 (instanceRef pdp_ram_14_2_5))
+              (portRef ADA9 (instanceRef pdp_ram_14_3_4))
+              (portRef ADA9 (instanceRef pdp_ram_15_0_3))
+              (portRef ADA9 (instanceRef pdp_ram_15_1_2))
+              (portRef ADA9 (instanceRef pdp_ram_15_2_1))
+              (portRef ADA9 (instanceRef pdp_ram_15_3_0))))
+          (net wptr_7
+            (joined
+              (portRef Q (instanceRef FF_49))
+              (portRef ADA10 (instanceRef pdp_ram_0_0_63))
+              (portRef ADA10 (instanceRef pdp_ram_0_1_62))
+              (portRef ADA10 (instanceRef pdp_ram_0_2_61))
+              (portRef ADA10 (instanceRef pdp_ram_0_3_60))
+              (portRef ADA10 (instanceRef pdp_ram_1_0_59))
+              (portRef ADA10 (instanceRef pdp_ram_1_1_58))
+              (portRef ADA10 (instanceRef pdp_ram_1_2_57))
+              (portRef ADA10 (instanceRef pdp_ram_1_3_56))
+              (portRef ADA10 (instanceRef pdp_ram_2_0_55))
+              (portRef ADA10 (instanceRef pdp_ram_2_1_54))
+              (portRef ADA10 (instanceRef pdp_ram_2_2_53))
+              (portRef ADA10 (instanceRef pdp_ram_2_3_52))
+              (portRef ADA10 (instanceRef pdp_ram_3_0_51))
+              (portRef ADA10 (instanceRef pdp_ram_3_1_50))
+              (portRef ADA10 (instanceRef pdp_ram_3_2_49))
+              (portRef ADA10 (instanceRef pdp_ram_3_3_48))
+              (portRef ADA10 (instanceRef pdp_ram_4_0_47))
+              (portRef ADA10 (instanceRef pdp_ram_4_1_46))
+              (portRef ADA10 (instanceRef pdp_ram_4_2_45))
+              (portRef ADA10 (instanceRef pdp_ram_4_3_44))
+              (portRef ADA10 (instanceRef pdp_ram_5_0_43))
+              (portRef ADA10 (instanceRef pdp_ram_5_1_42))
+              (portRef ADA10 (instanceRef pdp_ram_5_2_41))
+              (portRef ADA10 (instanceRef pdp_ram_5_3_40))
+              (portRef ADA10 (instanceRef pdp_ram_6_0_39))
+              (portRef ADA10 (instanceRef pdp_ram_6_1_38))
+              (portRef ADA10 (instanceRef pdp_ram_6_2_37))
+              (portRef ADA10 (instanceRef pdp_ram_6_3_36))
+              (portRef ADA10 (instanceRef pdp_ram_7_0_35))
+              (portRef ADA10 (instanceRef pdp_ram_7_1_34))
+              (portRef ADA10 (instanceRef pdp_ram_7_2_33))
+              (portRef ADA10 (instanceRef pdp_ram_7_3_32))
+              (portRef ADA10 (instanceRef pdp_ram_8_0_31))
+              (portRef ADA10 (instanceRef pdp_ram_8_1_30))
+              (portRef ADA10 (instanceRef pdp_ram_8_2_29))
+              (portRef ADA10 (instanceRef pdp_ram_8_3_28))
+              (portRef ADA10 (instanceRef pdp_ram_9_0_27))
+              (portRef ADA10 (instanceRef pdp_ram_9_1_26))
+              (portRef ADA10 (instanceRef pdp_ram_9_2_25))
+              (portRef ADA10 (instanceRef pdp_ram_9_3_24))
+              (portRef ADA10 (instanceRef pdp_ram_10_0_23))
+              (portRef ADA10 (instanceRef pdp_ram_10_1_22))
+              (portRef ADA10 (instanceRef pdp_ram_10_2_21))
+              (portRef ADA10 (instanceRef pdp_ram_10_3_20))
+              (portRef ADA10 (instanceRef pdp_ram_11_0_19))
+              (portRef ADA10 (instanceRef pdp_ram_11_1_18))
+              (portRef ADA10 (instanceRef pdp_ram_11_2_17))
+              (portRef ADA10 (instanceRef pdp_ram_11_3_16))
+              (portRef ADA10 (instanceRef pdp_ram_12_0_15))
+              (portRef ADA10 (instanceRef pdp_ram_12_1_14))
+              (portRef ADA10 (instanceRef pdp_ram_12_2_13))
+              (portRef ADA10 (instanceRef pdp_ram_12_3_12))
+              (portRef ADA10 (instanceRef pdp_ram_13_0_11))
+              (portRef ADA10 (instanceRef pdp_ram_13_1_10))
+              (portRef ADA10 (instanceRef pdp_ram_13_2_9))
+              (portRef ADA10 (instanceRef pdp_ram_13_3_8))
+              (portRef ADA10 (instanceRef pdp_ram_14_0_7))
+              (portRef ADA10 (instanceRef pdp_ram_14_1_6))
+              (portRef ADA10 (instanceRef pdp_ram_14_2_5))
+              (portRef ADA10 (instanceRef pdp_ram_14_3_4))
+              (portRef ADA10 (instanceRef pdp_ram_15_0_3))
+              (portRef ADA10 (instanceRef pdp_ram_15_1_2))
+              (portRef ADA10 (instanceRef pdp_ram_15_2_1))
+              (portRef ADA10 (instanceRef pdp_ram_15_3_0))))
+          (net wptr_8
+            (joined
+              (portRef Q (instanceRef FF_48))
+              (portRef ADA11 (instanceRef pdp_ram_0_0_63))
+              (portRef ADA11 (instanceRef pdp_ram_0_1_62))
+              (portRef ADA11 (instanceRef pdp_ram_0_2_61))
+              (portRef ADA11 (instanceRef pdp_ram_0_3_60))
+              (portRef ADA11 (instanceRef pdp_ram_1_0_59))
+              (portRef ADA11 (instanceRef pdp_ram_1_1_58))
+              (portRef ADA11 (instanceRef pdp_ram_1_2_57))
+              (portRef ADA11 (instanceRef pdp_ram_1_3_56))
+              (portRef ADA11 (instanceRef pdp_ram_2_0_55))
+              (portRef ADA11 (instanceRef pdp_ram_2_1_54))
+              (portRef ADA11 (instanceRef pdp_ram_2_2_53))
+              (portRef ADA11 (instanceRef pdp_ram_2_3_52))
+              (portRef ADA11 (instanceRef pdp_ram_3_0_51))
+              (portRef ADA11 (instanceRef pdp_ram_3_1_50))
+              (portRef ADA11 (instanceRef pdp_ram_3_2_49))
+              (portRef ADA11 (instanceRef pdp_ram_3_3_48))
+              (portRef ADA11 (instanceRef pdp_ram_4_0_47))
+              (portRef ADA11 (instanceRef pdp_ram_4_1_46))
+              (portRef ADA11 (instanceRef pdp_ram_4_2_45))
+              (portRef ADA11 (instanceRef pdp_ram_4_3_44))
+              (portRef ADA11 (instanceRef pdp_ram_5_0_43))
+              (portRef ADA11 (instanceRef pdp_ram_5_1_42))
+              (portRef ADA11 (instanceRef pdp_ram_5_2_41))
+              (portRef ADA11 (instanceRef pdp_ram_5_3_40))
+              (portRef ADA11 (instanceRef pdp_ram_6_0_39))
+              (portRef ADA11 (instanceRef pdp_ram_6_1_38))
+              (portRef ADA11 (instanceRef pdp_ram_6_2_37))
+              (portRef ADA11 (instanceRef pdp_ram_6_3_36))
+              (portRef ADA11 (instanceRef pdp_ram_7_0_35))
+              (portRef ADA11 (instanceRef pdp_ram_7_1_34))
+              (portRef ADA11 (instanceRef pdp_ram_7_2_33))
+              (portRef ADA11 (instanceRef pdp_ram_7_3_32))
+              (portRef ADA11 (instanceRef pdp_ram_8_0_31))
+              (portRef ADA11 (instanceRef pdp_ram_8_1_30))
+              (portRef ADA11 (instanceRef pdp_ram_8_2_29))
+              (portRef ADA11 (instanceRef pdp_ram_8_3_28))
+              (portRef ADA11 (instanceRef pdp_ram_9_0_27))
+              (portRef ADA11 (instanceRef pdp_ram_9_1_26))
+              (portRef ADA11 (instanceRef pdp_ram_9_2_25))
+              (portRef ADA11 (instanceRef pdp_ram_9_3_24))
+              (portRef ADA11 (instanceRef pdp_ram_10_0_23))
+              (portRef ADA11 (instanceRef pdp_ram_10_1_22))
+              (portRef ADA11 (instanceRef pdp_ram_10_2_21))
+              (portRef ADA11 (instanceRef pdp_ram_10_3_20))
+              (portRef ADA11 (instanceRef pdp_ram_11_0_19))
+              (portRef ADA11 (instanceRef pdp_ram_11_1_18))
+              (portRef ADA11 (instanceRef pdp_ram_11_2_17))
+              (portRef ADA11 (instanceRef pdp_ram_11_3_16))
+              (portRef ADA11 (instanceRef pdp_ram_12_0_15))
+              (portRef ADA11 (instanceRef pdp_ram_12_1_14))
+              (portRef ADA11 (instanceRef pdp_ram_12_2_13))
+              (portRef ADA11 (instanceRef pdp_ram_12_3_12))
+              (portRef ADA11 (instanceRef pdp_ram_13_0_11))
+              (portRef ADA11 (instanceRef pdp_ram_13_1_10))
+              (portRef ADA11 (instanceRef pdp_ram_13_2_9))
+              (portRef ADA11 (instanceRef pdp_ram_13_3_8))
+              (portRef ADA11 (instanceRef pdp_ram_14_0_7))
+              (portRef ADA11 (instanceRef pdp_ram_14_1_6))
+              (portRef ADA11 (instanceRef pdp_ram_14_2_5))
+              (portRef ADA11 (instanceRef pdp_ram_14_3_4))
+              (portRef ADA11 (instanceRef pdp_ram_15_0_3))
+              (portRef ADA11 (instanceRef pdp_ram_15_1_2))
+              (portRef ADA11 (instanceRef pdp_ram_15_2_1))
+              (portRef ADA11 (instanceRef pdp_ram_15_3_0))))
+          (net wptr_9
+            (joined
+              (portRef Q (instanceRef FF_47))
+              (portRef ADA12 (instanceRef pdp_ram_0_0_63))
+              (portRef ADA12 (instanceRef pdp_ram_0_1_62))
+              (portRef ADA12 (instanceRef pdp_ram_0_2_61))
+              (portRef ADA12 (instanceRef pdp_ram_0_3_60))
+              (portRef ADA12 (instanceRef pdp_ram_1_0_59))
+              (portRef ADA12 (instanceRef pdp_ram_1_1_58))
+              (portRef ADA12 (instanceRef pdp_ram_1_2_57))
+              (portRef ADA12 (instanceRef pdp_ram_1_3_56))
+              (portRef ADA12 (instanceRef pdp_ram_2_0_55))
+              (portRef ADA12 (instanceRef pdp_ram_2_1_54))
+              (portRef ADA12 (instanceRef pdp_ram_2_2_53))
+              (portRef ADA12 (instanceRef pdp_ram_2_3_52))
+              (portRef ADA12 (instanceRef pdp_ram_3_0_51))
+              (portRef ADA12 (instanceRef pdp_ram_3_1_50))
+              (portRef ADA12 (instanceRef pdp_ram_3_2_49))
+              (portRef ADA12 (instanceRef pdp_ram_3_3_48))
+              (portRef ADA12 (instanceRef pdp_ram_4_0_47))
+              (portRef ADA12 (instanceRef pdp_ram_4_1_46))
+              (portRef ADA12 (instanceRef pdp_ram_4_2_45))
+              (portRef ADA12 (instanceRef pdp_ram_4_3_44))
+              (portRef ADA12 (instanceRef pdp_ram_5_0_43))
+              (portRef ADA12 (instanceRef pdp_ram_5_1_42))
+              (portRef ADA12 (instanceRef pdp_ram_5_2_41))
+              (portRef ADA12 (instanceRef pdp_ram_5_3_40))
+              (portRef ADA12 (instanceRef pdp_ram_6_0_39))
+              (portRef ADA12 (instanceRef pdp_ram_6_1_38))
+              (portRef ADA12 (instanceRef pdp_ram_6_2_37))
+              (portRef ADA12 (instanceRef pdp_ram_6_3_36))
+              (portRef ADA12 (instanceRef pdp_ram_7_0_35))
+              (portRef ADA12 (instanceRef pdp_ram_7_1_34))
+              (portRef ADA12 (instanceRef pdp_ram_7_2_33))
+              (portRef ADA12 (instanceRef pdp_ram_7_3_32))
+              (portRef ADA12 (instanceRef pdp_ram_8_0_31))
+              (portRef ADA12 (instanceRef pdp_ram_8_1_30))
+              (portRef ADA12 (instanceRef pdp_ram_8_2_29))
+              (portRef ADA12 (instanceRef pdp_ram_8_3_28))
+              (portRef ADA12 (instanceRef pdp_ram_9_0_27))
+              (portRef ADA12 (instanceRef pdp_ram_9_1_26))
+              (portRef ADA12 (instanceRef pdp_ram_9_2_25))
+              (portRef ADA12 (instanceRef pdp_ram_9_3_24))
+              (portRef ADA12 (instanceRef pdp_ram_10_0_23))
+              (portRef ADA12 (instanceRef pdp_ram_10_1_22))
+              (portRef ADA12 (instanceRef pdp_ram_10_2_21))
+              (portRef ADA12 (instanceRef pdp_ram_10_3_20))
+              (portRef ADA12 (instanceRef pdp_ram_11_0_19))
+              (portRef ADA12 (instanceRef pdp_ram_11_1_18))
+              (portRef ADA12 (instanceRef pdp_ram_11_2_17))
+              (portRef ADA12 (instanceRef pdp_ram_11_3_16))
+              (portRef ADA12 (instanceRef pdp_ram_12_0_15))
+              (portRef ADA12 (instanceRef pdp_ram_12_1_14))
+              (portRef ADA12 (instanceRef pdp_ram_12_2_13))
+              (portRef ADA12 (instanceRef pdp_ram_12_3_12))
+              (portRef ADA12 (instanceRef pdp_ram_13_0_11))
+              (portRef ADA12 (instanceRef pdp_ram_13_1_10))
+              (portRef ADA12 (instanceRef pdp_ram_13_2_9))
+              (portRef ADA12 (instanceRef pdp_ram_13_3_8))
+              (portRef ADA12 (instanceRef pdp_ram_14_0_7))
+              (portRef ADA12 (instanceRef pdp_ram_14_1_6))
+              (portRef ADA12 (instanceRef pdp_ram_14_2_5))
+              (portRef ADA12 (instanceRef pdp_ram_14_3_4))
+              (portRef ADA12 (instanceRef pdp_ram_15_0_3))
+              (portRef ADA12 (instanceRef pdp_ram_15_1_2))
+              (portRef ADA12 (instanceRef pdp_ram_15_2_1))
+              (portRef ADA12 (instanceRef pdp_ram_15_3_0))))
+          (net wptr_10
+            (joined
+              (portRef Q (instanceRef FF_46))
+              (portRef ADA13 (instanceRef pdp_ram_0_0_63))
+              (portRef ADA13 (instanceRef pdp_ram_0_1_62))
+              (portRef ADA13 (instanceRef pdp_ram_0_2_61))
+              (portRef ADA13 (instanceRef pdp_ram_0_3_60))
+              (portRef ADA13 (instanceRef pdp_ram_1_0_59))
+              (portRef ADA13 (instanceRef pdp_ram_1_1_58))
+              (portRef ADA13 (instanceRef pdp_ram_1_2_57))
+              (portRef ADA13 (instanceRef pdp_ram_1_3_56))
+              (portRef ADA13 (instanceRef pdp_ram_2_0_55))
+              (portRef ADA13 (instanceRef pdp_ram_2_1_54))
+              (portRef ADA13 (instanceRef pdp_ram_2_2_53))
+              (portRef ADA13 (instanceRef pdp_ram_2_3_52))
+              (portRef ADA13 (instanceRef pdp_ram_3_0_51))
+              (portRef ADA13 (instanceRef pdp_ram_3_1_50))
+              (portRef ADA13 (instanceRef pdp_ram_3_2_49))
+              (portRef ADA13 (instanceRef pdp_ram_3_3_48))
+              (portRef ADA13 (instanceRef pdp_ram_4_0_47))
+              (portRef ADA13 (instanceRef pdp_ram_4_1_46))
+              (portRef ADA13 (instanceRef pdp_ram_4_2_45))
+              (portRef ADA13 (instanceRef pdp_ram_4_3_44))
+              (portRef ADA13 (instanceRef pdp_ram_5_0_43))
+              (portRef ADA13 (instanceRef pdp_ram_5_1_42))
+              (portRef ADA13 (instanceRef pdp_ram_5_2_41))
+              (portRef ADA13 (instanceRef pdp_ram_5_3_40))
+              (portRef ADA13 (instanceRef pdp_ram_6_0_39))
+              (portRef ADA13 (instanceRef pdp_ram_6_1_38))
+              (portRef ADA13 (instanceRef pdp_ram_6_2_37))
+              (portRef ADA13 (instanceRef pdp_ram_6_3_36))
+              (portRef ADA13 (instanceRef pdp_ram_7_0_35))
+              (portRef ADA13 (instanceRef pdp_ram_7_1_34))
+              (portRef ADA13 (instanceRef pdp_ram_7_2_33))
+              (portRef ADA13 (instanceRef pdp_ram_7_3_32))
+              (portRef ADA13 (instanceRef pdp_ram_8_0_31))
+              (portRef ADA13 (instanceRef pdp_ram_8_1_30))
+              (portRef ADA13 (instanceRef pdp_ram_8_2_29))
+              (portRef ADA13 (instanceRef pdp_ram_8_3_28))
+              (portRef ADA13 (instanceRef pdp_ram_9_0_27))
+              (portRef ADA13 (instanceRef pdp_ram_9_1_26))
+              (portRef ADA13 (instanceRef pdp_ram_9_2_25))
+              (portRef ADA13 (instanceRef pdp_ram_9_3_24))
+              (portRef ADA13 (instanceRef pdp_ram_10_0_23))
+              (portRef ADA13 (instanceRef pdp_ram_10_1_22))
+              (portRef ADA13 (instanceRef pdp_ram_10_2_21))
+              (portRef ADA13 (instanceRef pdp_ram_10_3_20))
+              (portRef ADA13 (instanceRef pdp_ram_11_0_19))
+              (portRef ADA13 (instanceRef pdp_ram_11_1_18))
+              (portRef ADA13 (instanceRef pdp_ram_11_2_17))
+              (portRef ADA13 (instanceRef pdp_ram_11_3_16))
+              (portRef ADA13 (instanceRef pdp_ram_12_0_15))
+              (portRef ADA13 (instanceRef pdp_ram_12_1_14))
+              (portRef ADA13 (instanceRef pdp_ram_12_2_13))
+              (portRef ADA13 (instanceRef pdp_ram_12_3_12))
+              (portRef ADA13 (instanceRef pdp_ram_13_0_11))
+              (portRef ADA13 (instanceRef pdp_ram_13_1_10))
+              (portRef ADA13 (instanceRef pdp_ram_13_2_9))
+              (portRef ADA13 (instanceRef pdp_ram_13_3_8))
+              (portRef ADA13 (instanceRef pdp_ram_14_0_7))
+              (portRef ADA13 (instanceRef pdp_ram_14_1_6))
+              (portRef ADA13 (instanceRef pdp_ram_14_2_5))
+              (portRef ADA13 (instanceRef pdp_ram_14_3_4))
+              (portRef ADA13 (instanceRef pdp_ram_15_0_3))
+              (portRef ADA13 (instanceRef pdp_ram_15_1_2))
+              (portRef ADA13 (instanceRef pdp_ram_15_2_1))
+              (portRef ADA13 (instanceRef pdp_ram_15_3_0))))
+          (net wptr_11
+            (joined
+              (portRef Q (instanceRef FF_45))
+              (portRef A (instanceRef INV_9))
+              (portRef AD3 (instanceRef LUT4_119))
+              (portRef AD3 (instanceRef LUT4_117))
+              (portRef AD3 (instanceRef LUT4_115))
+              (portRef AD3 (instanceRef LUT4_113))
+              (portRef AD3 (instanceRef LUT4_103))
+              (portRef AD3 (instanceRef LUT4_101))
+              (portRef AD3 (instanceRef LUT4_99))
+              (portRef AD3 (instanceRef LUT4_97))
+              (portRef AD3 (instanceRef LUT4_87))
+              (portRef AD3 (instanceRef LUT4_85))
+              (portRef AD3 (instanceRef LUT4_83))
+              (portRef AD3 (instanceRef LUT4_81))
+              (portRef AD3 (instanceRef LUT4_71))
+              (portRef AD3 (instanceRef LUT4_69))
+              (portRef AD3 (instanceRef LUT4_67))
+              (portRef AD3 (instanceRef LUT4_65))
+              (portRef AD3 (instanceRef LUT4_55))
+              (portRef AD3 (instanceRef LUT4_53))
+              (portRef AD3 (instanceRef LUT4_51))
+              (portRef AD3 (instanceRef LUT4_49))
+              (portRef AD3 (instanceRef LUT4_39))
+              (portRef AD3 (instanceRef LUT4_37))
+              (portRef AD3 (instanceRef LUT4_35))
+              (portRef AD3 (instanceRef LUT4_33))
+              (portRef AD3 (instanceRef LUT4_23))
+              (portRef AD3 (instanceRef LUT4_21))
+              (portRef AD3 (instanceRef LUT4_19))
+              (portRef AD3 (instanceRef LUT4_17))
+              (portRef AD3 (instanceRef LUT4_7))
+              (portRef AD3 (instanceRef LUT4_5))
+              (portRef AD3 (instanceRef LUT4_3))
+              (portRef AD3 (instanceRef LUT4_1))))
+          (net wptr_12
+            (joined
+              (portRef Q (instanceRef FF_44))
+              (portRef A (instanceRef INV_8))
+              (portRef AD2 (instanceRef LUT4_111))
+              (portRef AD2 (instanceRef LUT4_109))
+              (portRef AD2 (instanceRef LUT4_107))
+              (portRef AD2 (instanceRef LUT4_105))
+              (portRef AD2 (instanceRef LUT4_103))
+              (portRef AD2 (instanceRef LUT4_101))
+              (portRef AD2 (instanceRef LUT4_99))
+              (portRef AD2 (instanceRef LUT4_97))
+              (portRef AD2 (instanceRef LUT4_79))
+              (portRef AD2 (instanceRef LUT4_77))
+              (portRef AD2 (instanceRef LUT4_75))
+              (portRef AD2 (instanceRef LUT4_73))
+              (portRef AD2 (instanceRef LUT4_71))
+              (portRef AD2 (instanceRef LUT4_69))
+              (portRef AD2 (instanceRef LUT4_67))
+              (portRef AD2 (instanceRef LUT4_65))
+              (portRef AD2 (instanceRef LUT4_47))
+              (portRef AD2 (instanceRef LUT4_45))
+              (portRef AD2 (instanceRef LUT4_43))
+              (portRef AD2 (instanceRef LUT4_41))
+              (portRef AD2 (instanceRef LUT4_39))
+              (portRef AD2 (instanceRef LUT4_37))
+              (portRef AD2 (instanceRef LUT4_35))
+              (portRef AD2 (instanceRef LUT4_33))
+              (portRef AD2 (instanceRef LUT4_15))
+              (portRef AD2 (instanceRef LUT4_13))
+              (portRef AD2 (instanceRef LUT4_11))
+              (portRef AD2 (instanceRef LUT4_9))
+              (portRef AD2 (instanceRef LUT4_7))
+              (portRef AD2 (instanceRef LUT4_5))
+              (portRef AD2 (instanceRef LUT4_3))
+              (portRef AD2 (instanceRef LUT4_1))))
+          (net wptr_13
+            (joined
+              (portRef Q (instanceRef FF_43))
+              (portRef A (instanceRef INV_7))
+              (portRef AD1 (instanceRef LUT4_95))
+              (portRef AD1 (instanceRef LUT4_93))
+              (portRef AD1 (instanceRef LUT4_91))
+              (portRef AD1 (instanceRef LUT4_89))
+              (portRef AD1 (instanceRef LUT4_87))
+              (portRef AD1 (instanceRef LUT4_85))
+              (portRef AD1 (instanceRef LUT4_83))
+              (portRef AD1 (instanceRef LUT4_81))
+              (portRef AD1 (instanceRef LUT4_79))
+              (portRef AD1 (instanceRef LUT4_77))
+              (portRef AD1 (instanceRef LUT4_75))
+              (portRef AD1 (instanceRef LUT4_73))
+              (portRef AD1 (instanceRef LUT4_71))
+              (portRef AD1 (instanceRef LUT4_69))
+              (portRef AD1 (instanceRef LUT4_67))
+              (portRef AD1 (instanceRef LUT4_65))
+              (portRef AD1 (instanceRef LUT4_31))
+              (portRef AD1 (instanceRef LUT4_29))
+              (portRef AD1 (instanceRef LUT4_27))
+              (portRef AD1 (instanceRef LUT4_25))
+              (portRef AD1 (instanceRef LUT4_23))
+              (portRef AD1 (instanceRef LUT4_21))
+              (portRef AD1 (instanceRef LUT4_19))
+              (portRef AD1 (instanceRef LUT4_17))
+              (portRef AD1 (instanceRef LUT4_15))
+              (portRef AD1 (instanceRef LUT4_13))
+              (portRef AD1 (instanceRef LUT4_11))
+              (portRef AD1 (instanceRef LUT4_9))
+              (portRef AD1 (instanceRef LUT4_7))
+              (portRef AD1 (instanceRef LUT4_5))
+              (portRef AD1 (instanceRef LUT4_3))
+              (portRef AD1 (instanceRef LUT4_1))))
+          (net wptr_14
+            (joined
+              (portRef Q (instanceRef FF_42))
+              (portRef A (instanceRef INV_6))
+              (portRef AD0 (instanceRef LUT4_63))
+              (portRef AD0 (instanceRef LUT4_61))
+              (portRef AD0 (instanceRef LUT4_59))
+              (portRef AD0 (instanceRef LUT4_57))
+              (portRef AD0 (instanceRef LUT4_55))
+              (portRef AD0 (instanceRef LUT4_53))
+              (portRef AD0 (instanceRef LUT4_51))
+              (portRef AD0 (instanceRef LUT4_49))
+              (portRef AD0 (instanceRef LUT4_47))
+              (portRef AD0 (instanceRef LUT4_45))
+              (portRef AD0 (instanceRef LUT4_43))
+              (portRef AD0 (instanceRef LUT4_41))
+              (portRef AD0 (instanceRef LUT4_39))
+              (portRef AD0 (instanceRef LUT4_37))
+              (portRef AD0 (instanceRef LUT4_35))
+              (portRef AD0 (instanceRef LUT4_33))
+              (portRef AD0 (instanceRef LUT4_31))
+              (portRef AD0 (instanceRef LUT4_29))
+              (portRef AD0 (instanceRef LUT4_27))
+              (portRef AD0 (instanceRef LUT4_25))
+              (portRef AD0 (instanceRef LUT4_23))
+              (portRef AD0 (instanceRef LUT4_21))
+              (portRef AD0 (instanceRef LUT4_19))
+              (portRef AD0 (instanceRef LUT4_17))
+              (portRef AD0 (instanceRef LUT4_15))
+              (portRef AD0 (instanceRef LUT4_13))
+              (portRef AD0 (instanceRef LUT4_11))
+              (portRef AD0 (instanceRef LUT4_9))
+              (portRef AD0 (instanceRef LUT4_7))
+              (portRef AD0 (instanceRef LUT4_5))
+              (portRef AD0 (instanceRef LUT4_3))
+              (portRef AD0 (instanceRef LUT4_1))))
+          (net wptr_15
+            (joined
+              (portRef Q (instanceRef FF_41))))
+          (net rptr_15
+            (joined
+              (portRef Q (instanceRef FF_25))
+              (portRef B (instanceRef XOR2_t0))))
+          (net rptr_11_ff
+            (joined
+              (portRef D (instanceRef FF_20))
+              (portRef Q (instanceRef FF_24))))
+          (net rptr_12_ff
+            (joined
+              (portRef D (instanceRef FF_19))
+              (portRef Q (instanceRef FF_23))))
+          (net rptr_13_ff
+            (joined
+              (portRef D (instanceRef FF_18))
+              (portRef Q (instanceRef FF_22))))
+          (net rptr_14_ff
+            (joined
+              (portRef D (instanceRef FF_17))
+              (portRef Q (instanceRef FF_21))))
+          (net ifcount_0
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_0))
+              (portRef D (instanceRef FF_106))))
+          (net ifcount_1
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_0))
+              (portRef D (instanceRef FF_105))))
+          (net bdcnt_bctr_ci
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_0))
+              (portRef COUT (instanceRef bdcnt_bctr_cia))))
+          (net ifcount_2
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_1))
+              (portRef D (instanceRef FF_104))))
+          (net ifcount_3
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_1))
+              (portRef D (instanceRef FF_103))))
+          (net co0
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_1))
+              (portRef COUT (instanceRef bdcnt_bctr_0))))
+          (net ifcount_4
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_2))
+              (portRef D (instanceRef FF_102))))
+          (net ifcount_5
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_2))
+              (portRef D (instanceRef FF_101))))
+          (net co1
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_2))
+              (portRef COUT (instanceRef bdcnt_bctr_1))))
+          (net ifcount_6
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_3))
+              (portRef D (instanceRef FF_100))))
+          (net ifcount_7
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_3))
+              (portRef D (instanceRef FF_99))))
+          (net co2
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_3))
+              (portRef COUT (instanceRef bdcnt_bctr_2))))
+          (net ifcount_8
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_4))
+              (portRef D (instanceRef FF_98))))
+          (net ifcount_9
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_4))
+              (portRef D (instanceRef FF_97))))
+          (net co3
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_4))
+              (portRef COUT (instanceRef bdcnt_bctr_3))))
+          (net ifcount_10
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_5))
+              (portRef D (instanceRef FF_96))))
+          (net ifcount_11
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_5))
+              (portRef D (instanceRef FF_95))))
+          (net co4
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_5))
+              (portRef COUT (instanceRef bdcnt_bctr_4))))
+          (net ifcount_12
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_6))
+              (portRef D (instanceRef FF_94))))
+          (net ifcount_13
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_6))
+              (portRef D (instanceRef FF_93))))
+          (net co5
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_6))
+              (portRef COUT (instanceRef bdcnt_bctr_5))))
+          (net ifcount_14
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_7))
+              (portRef D (instanceRef FF_92))))
+          (net ifcount_15
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_7))
+              (portRef D (instanceRef FF_91))))
+          (net co7
+            (joined
+              (portRef COUT (instanceRef bdcnt_bctr_7))))
+          (net co6
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_7))
+              (portRef COUT (instanceRef bdcnt_bctr_6))))
+          (net cmp_ci
+            (joined
+              (portRef CIN (instanceRef e_cmp_0))
+              (portRef COUT (instanceRef e_cmp_ci_a))))
+          (net rden_i
+            (joined
+              (portRef A0 (instanceRef e_cmp_0))
+              (portRef Z (instanceRef AND2_t4))
+              (portRef B (instanceRef XOR2_t2))
+              (portRef A (instanceRef INV_11))
+              (portRef AD1 (instanceRef LUT4_128))
+              (portRef A (instanceRef AND2_t1))
+              (portRef CEB (instanceRef pdp_ram_0_0_63))
+              (portRef CEB (instanceRef pdp_ram_0_1_62))
+              (portRef CEB (instanceRef pdp_ram_0_2_61))
+              (portRef CEB (instanceRef pdp_ram_0_3_60))
+              (portRef CEB (instanceRef pdp_ram_1_0_59))
+              (portRef CEB (instanceRef pdp_ram_1_1_58))
+              (portRef CEB (instanceRef pdp_ram_1_2_57))
+              (portRef CEB (instanceRef pdp_ram_1_3_56))
+              (portRef CEB (instanceRef pdp_ram_2_0_55))
+              (portRef CEB (instanceRef pdp_ram_2_1_54))
+              (portRef CEB (instanceRef pdp_ram_2_2_53))
+              (portRef CEB (instanceRef pdp_ram_2_3_52))
+              (portRef CEB (instanceRef pdp_ram_3_0_51))
+              (portRef CEB (instanceRef pdp_ram_3_1_50))
+              (portRef CEB (instanceRef pdp_ram_3_2_49))
+              (portRef CEB (instanceRef pdp_ram_3_3_48))
+              (portRef CEB (instanceRef pdp_ram_4_0_47))
+              (portRef CEB (instanceRef pdp_ram_4_1_46))
+              (portRef CEB (instanceRef pdp_ram_4_2_45))
+              (portRef CEB (instanceRef pdp_ram_4_3_44))
+              (portRef CEB (instanceRef pdp_ram_5_0_43))
+              (portRef CEB (instanceRef pdp_ram_5_1_42))
+              (portRef CEB (instanceRef pdp_ram_5_2_41))
+              (portRef CEB (instanceRef pdp_ram_5_3_40))
+              (portRef CEB (instanceRef pdp_ram_6_0_39))
+              (portRef CEB (instanceRef pdp_ram_6_1_38))
+              (portRef CEB (instanceRef pdp_ram_6_2_37))
+              (portRef CEB (instanceRef pdp_ram_6_3_36))
+              (portRef CEB (instanceRef pdp_ram_7_0_35))
+              (portRef CEB (instanceRef pdp_ram_7_1_34))
+              (portRef CEB (instanceRef pdp_ram_7_2_33))
+              (portRef CEB (instanceRef pdp_ram_7_3_32))
+              (portRef CEB (instanceRef pdp_ram_8_0_31))
+              (portRef CEB (instanceRef pdp_ram_8_1_30))
+              (portRef CEB (instanceRef pdp_ram_8_2_29))
+              (portRef CEB (instanceRef pdp_ram_8_3_28))
+              (portRef CEB (instanceRef pdp_ram_9_0_27))
+              (portRef CEB (instanceRef pdp_ram_9_1_26))
+              (portRef CEB (instanceRef pdp_ram_9_2_25))
+              (portRef CEB (instanceRef pdp_ram_9_3_24))
+              (portRef CEB (instanceRef pdp_ram_10_0_23))
+              (portRef CEB (instanceRef pdp_ram_10_1_22))
+              (portRef CEB (instanceRef pdp_ram_10_2_21))
+              (portRef CEB (instanceRef pdp_ram_10_3_20))
+              (portRef CEB (instanceRef pdp_ram_11_0_19))
+              (portRef CEB (instanceRef pdp_ram_11_1_18))
+              (portRef CEB (instanceRef pdp_ram_11_2_17))
+              (portRef CEB (instanceRef pdp_ram_11_3_16))
+              (portRef CEB (instanceRef pdp_ram_12_0_15))
+              (portRef CEB (instanceRef pdp_ram_12_1_14))
+              (portRef CEB (instanceRef pdp_ram_12_2_13))
+              (portRef CEB (instanceRef pdp_ram_12_3_12))
+              (portRef CEB (instanceRef pdp_ram_13_0_11))
+              (portRef CEB (instanceRef pdp_ram_13_1_10))
+              (portRef CEB (instanceRef pdp_ram_13_2_9))
+              (portRef CEB (instanceRef pdp_ram_13_3_8))
+              (portRef CEB (instanceRef pdp_ram_14_0_7))
+              (portRef CEB (instanceRef pdp_ram_14_1_6))
+              (portRef CEB (instanceRef pdp_ram_14_2_5))
+              (portRef CEB (instanceRef pdp_ram_14_3_4))
+              (portRef CEB (instanceRef pdp_ram_15_0_3))
+              (portRef CEB (instanceRef pdp_ram_15_1_2))
+              (portRef CEB (instanceRef pdp_ram_15_2_1))
+              (portRef CEB (instanceRef pdp_ram_15_3_0))
+              (portRef SP (instanceRef FF_72))
+              (portRef SP (instanceRef FF_71))
+              (portRef SP (instanceRef FF_70))
+              (portRef SP (instanceRef FF_69))
+              (portRef SP (instanceRef FF_68))
+              (portRef SP (instanceRef FF_67))
+              (portRef SP (instanceRef FF_66))
+              (portRef SP (instanceRef FF_65))
+              (portRef SP (instanceRef FF_64))
+              (portRef SP (instanceRef FF_63))
+              (portRef SP (instanceRef FF_62))
+              (portRef SP (instanceRef FF_61))
+              (portRef SP (instanceRef FF_60))
+              (portRef SP (instanceRef FF_59))
+              (portRef SP (instanceRef FF_58))
+              (portRef SP (instanceRef FF_57))
+              (portRef SP (instanceRef FF_40))
+              (portRef SP (instanceRef FF_39))
+              (portRef SP (instanceRef FF_38))
+              (portRef SP (instanceRef FF_37))
+              (portRef SP (instanceRef FF_36))
+              (portRef SP (instanceRef FF_35))
+              (portRef SP (instanceRef FF_34))
+              (portRef SP (instanceRef FF_33))
+              (portRef SP (instanceRef FF_32))
+              (portRef SP (instanceRef FF_31))
+              (portRef SP (instanceRef FF_30))
+              (portRef SP (instanceRef FF_29))
+              (portRef SP (instanceRef FF_28))
+              (portRef SP (instanceRef FF_27))
+              (portRef SP (instanceRef FF_26))
+              (portRef SP (instanceRef FF_25))
+              (portRef SP (instanceRef FF_24))
+              (portRef SP (instanceRef FF_23))
+              (portRef SP (instanceRef FF_22))
+              (portRef SP (instanceRef FF_21))
+              (portRef SP (instanceRef FF_20))
+              (portRef SP (instanceRef FF_19))
+              (portRef SP (instanceRef FF_18))
+              (portRef SP (instanceRef FF_17))))
+          (net co0_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_1))
+              (portRef COUT (instanceRef e_cmp_0))))
+          (net co1_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_2))
+              (portRef COUT (instanceRef e_cmp_1))))
+          (net co2_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_3))
+              (portRef COUT (instanceRef e_cmp_2))))
+          (net co3_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_4))
+              (portRef COUT (instanceRef e_cmp_3))))
+          (net co4_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_5))
+              (portRef COUT (instanceRef e_cmp_4))))
+          (net co5_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_6))
+              (portRef COUT (instanceRef e_cmp_5))))
+          (net co6_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_7))
+              (portRef COUT (instanceRef e_cmp_6))))
+          (net cmp_le_1
+            (joined
+              (portRef S0 (instanceRef a0))
+              (portRef AD2 (instanceRef LUT4_129))))
+          (net cmp_le_1_c
+            (joined
+              (portRef CIN (instanceRef a0))
+              (portRef COUT (instanceRef e_cmp_7))))
+          (net cmp_ci_1
+            (joined
+              (portRef CIN (instanceRef g_cmp_0))
+              (portRef COUT (instanceRef g_cmp_ci_a))))
+          (net co0_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_1))
+              (portRef COUT (instanceRef g_cmp_0))))
+          (net co1_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_2))
+              (portRef COUT (instanceRef g_cmp_1))))
+          (net co2_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_3))
+              (portRef COUT (instanceRef g_cmp_2))))
+          (net co3_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_4))
+              (portRef COUT (instanceRef g_cmp_3))))
+          (net co4_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_5))
+              (portRef COUT (instanceRef g_cmp_4))))
+          (net co5_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_6))
+              (portRef COUT (instanceRef g_cmp_5))))
+          (net co6_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_7))
+              (portRef COUT (instanceRef g_cmp_6))))
+          (net wren_i_inv
+            (joined
+              (portRef B1 (instanceRef g_cmp_7))
+              (portRef Z (instanceRef INV_10))))
+          (net cmp_ge_d1
+            (joined
+              (portRef S0 (instanceRef a1))
+              (portRef AD2 (instanceRef LUT4_128))))
+          (net cmp_ge_d1_c
+            (joined
+              (portRef CIN (instanceRef a1))
+              (portRef COUT (instanceRef g_cmp_7))))
+          (net iwcount_0
+            (joined
+              (portRef S0 (instanceRef w_ctr_0))
+              (portRef D (instanceRef FF_88))))
+          (net iwcount_1
+            (joined
+              (portRef S1 (instanceRef w_ctr_0))
+              (portRef D (instanceRef FF_87))))
+          (net w_ctr_ci
+            (joined
+              (portRef CIN (instanceRef w_ctr_0))
+              (portRef COUT (instanceRef w_ctr_cia))))
+          (net iwcount_2
+            (joined
+              (portRef S0 (instanceRef w_ctr_1))
+              (portRef D (instanceRef FF_86))))
+          (net iwcount_3
+            (joined
+              (portRef S1 (instanceRef w_ctr_1))
+              (portRef D (instanceRef FF_85))))
+          (net co0_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_1))
+              (portRef COUT (instanceRef w_ctr_0))))
+          (net iwcount_4
+            (joined
+              (portRef S0 (instanceRef w_ctr_2))
+              (portRef D (instanceRef FF_84))))
+          (net iwcount_5
+            (joined
+              (portRef S1 (instanceRef w_ctr_2))
+              (portRef D (instanceRef FF_83))))
+          (net co1_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_2))
+              (portRef COUT (instanceRef w_ctr_1))))
+          (net iwcount_6
+            (joined
+              (portRef S0 (instanceRef w_ctr_3))
+              (portRef D (instanceRef FF_82))))
+          (net iwcount_7
+            (joined
+              (portRef S1 (instanceRef w_ctr_3))
+              (portRef D (instanceRef FF_81))))
+          (net co2_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_3))
+              (portRef COUT (instanceRef w_ctr_2))))
+          (net iwcount_8
+            (joined
+              (portRef S0 (instanceRef w_ctr_4))
+              (portRef D (instanceRef FF_80))))
+          (net iwcount_9
+            (joined
+              (portRef S1 (instanceRef w_ctr_4))
+              (portRef D (instanceRef FF_79))))
+          (net co3_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_4))
+              (portRef COUT (instanceRef w_ctr_3))))
+          (net iwcount_10
+            (joined
+              (portRef S0 (instanceRef w_ctr_5))
+              (portRef D (instanceRef FF_78))))
+          (net iwcount_11
+            (joined
+              (portRef S1 (instanceRef w_ctr_5))
+              (portRef D (instanceRef FF_77))))
+          (net co4_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_5))
+              (portRef COUT (instanceRef w_ctr_4))))
+          (net iwcount_12
+            (joined
+              (portRef S0 (instanceRef w_ctr_6))
+              (portRef D (instanceRef FF_76))))
+          (net iwcount_13
+            (joined
+              (portRef S1 (instanceRef w_ctr_6))
+              (portRef D (instanceRef FF_75))))
+          (net co5_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_6))
+              (portRef COUT (instanceRef w_ctr_5))))
+          (net iwcount_14
+            (joined
+              (portRef S0 (instanceRef w_ctr_7))
+              (portRef D (instanceRef FF_74))))
+          (net iwcount_15
+            (joined
+              (portRef S1 (instanceRef w_ctr_7))
+              (portRef D (instanceRef FF_73))))
+          (net co7_1
+            (joined
+              (portRef COUT (instanceRef w_ctr_7))))
+          (net co6_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_7))
+              (portRef COUT (instanceRef w_ctr_6))))
+          (net wcount_15
+            (joined
+              (portRef A1 (instanceRef w_ctr_7))
+              (portRef A (instanceRef XOR2_t0))
+              (portRef Q (instanceRef FF_73))
+              (portRef D (instanceRef FF_41))))
+          (net ircount_0
+            (joined
+              (portRef S0 (instanceRef r_ctr_0))
+              (portRef D (instanceRef FF_72))))
+          (net ircount_1
+            (joined
+              (portRef S1 (instanceRef r_ctr_0))
+              (portRef D (instanceRef FF_71))))
+          (net r_ctr_ci
+            (joined
+              (portRef CIN (instanceRef r_ctr_0))
+              (portRef COUT (instanceRef r_ctr_cia))))
+          (net rcount_0
+            (joined
+              (portRef A0 (instanceRef r_ctr_0))
+              (portRef Q (instanceRef FF_72))
+              (portRef D (instanceRef FF_40))))
+          (net rcount_1
+            (joined
+              (portRef A1 (instanceRef r_ctr_0))
+              (portRef Q (instanceRef FF_71))
+              (portRef D (instanceRef FF_39))))
+          (net ircount_2
+            (joined
+              (portRef S0 (instanceRef r_ctr_1))
+              (portRef D (instanceRef FF_70))))
+          (net ircount_3
+            (joined
+              (portRef S1 (instanceRef r_ctr_1))
+              (portRef D (instanceRef FF_69))))
+          (net co0_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_1))
+              (portRef COUT (instanceRef r_ctr_0))))
+          (net rcount_2
+            (joined
+              (portRef A0 (instanceRef r_ctr_1))
+              (portRef Q (instanceRef FF_70))
+              (portRef D (instanceRef FF_38))))
+          (net rcount_3
+            (joined
+              (portRef A1 (instanceRef r_ctr_1))
+              (portRef Q (instanceRef FF_69))
+              (portRef D (instanceRef FF_37))))
+          (net ircount_4
+            (joined
+              (portRef S0 (instanceRef r_ctr_2))
+              (portRef D (instanceRef FF_68))))
+          (net ircount_5
+            (joined
+              (portRef S1 (instanceRef r_ctr_2))
+              (portRef D (instanceRef FF_67))))
+          (net co1_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_2))
+              (portRef COUT (instanceRef r_ctr_1))))
+          (net rcount_4
+            (joined
+              (portRef A0 (instanceRef r_ctr_2))
+              (portRef Q (instanceRef FF_68))
+              (portRef D (instanceRef FF_36))))
+          (net rcount_5
+            (joined
+              (portRef A1 (instanceRef r_ctr_2))
+              (portRef Q (instanceRef FF_67))
+              (portRef D (instanceRef FF_35))))
+          (net ircount_6
+            (joined
+              (portRef S0 (instanceRef r_ctr_3))
+              (portRef D (instanceRef FF_66))))
+          (net ircount_7
+            (joined
+              (portRef S1 (instanceRef r_ctr_3))
+              (portRef D (instanceRef FF_65))))
+          (net co2_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_3))
+              (portRef COUT (instanceRef r_ctr_2))))
+          (net rcount_6
+            (joined
+              (portRef A0 (instanceRef r_ctr_3))
+              (portRef Q (instanceRef FF_66))
+              (portRef D (instanceRef FF_34))))
+          (net rcount_7
+            (joined
+              (portRef A1 (instanceRef r_ctr_3))
+              (portRef Q (instanceRef FF_65))
+              (portRef D (instanceRef FF_33))))
+          (net ircount_8
+            (joined
+              (portRef S0 (instanceRef r_ctr_4))
+              (portRef D (instanceRef FF_64))))
+          (net ircount_9
+            (joined
+              (portRef S1 (instanceRef r_ctr_4))
+              (portRef D (instanceRef FF_63))))
+          (net co3_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_4))
+              (portRef COUT (instanceRef r_ctr_3))))
+          (net rcount_8
+            (joined
+              (portRef A0 (instanceRef r_ctr_4))
+              (portRef Q (instanceRef FF_64))
+              (portRef D (instanceRef FF_32))))
+          (net rcount_9
+            (joined
+              (portRef A1 (instanceRef r_ctr_4))
+              (portRef Q (instanceRef FF_63))
+              (portRef D (instanceRef FF_31))))
+          (net ircount_10
+            (joined
+              (portRef S0 (instanceRef r_ctr_5))
+              (portRef D (instanceRef FF_62))))
+          (net ircount_11
+            (joined
+              (portRef S1 (instanceRef r_ctr_5))
+              (portRef D (instanceRef FF_61))))
+          (net co4_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_5))
+              (portRef COUT (instanceRef r_ctr_4))))
+          (net rcount_10
+            (joined
+              (portRef A0 (instanceRef r_ctr_5))
+              (portRef Q (instanceRef FF_62))
+              (portRef D (instanceRef FF_30))))
+          (net rcount_11
+            (joined
+              (portRef A1 (instanceRef r_ctr_5))
+              (portRef Q (instanceRef FF_61))
+              (portRef D (instanceRef FF_29))))
+          (net ircount_12
+            (joined
+              (portRef S0 (instanceRef r_ctr_6))
+              (portRef D (instanceRef FF_60))))
+          (net ircount_13
+            (joined
+              (portRef S1 (instanceRef r_ctr_6))
+              (portRef D (instanceRef FF_59))))
+          (net co5_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_6))
+              (portRef COUT (instanceRef r_ctr_5))))
+          (net rcount_12
+            (joined
+              (portRef A0 (instanceRef r_ctr_6))
+              (portRef Q (instanceRef FF_60))
+              (portRef D (instanceRef FF_28))))
+          (net rcount_13
+            (joined
+              (portRef A1 (instanceRef r_ctr_6))
+              (portRef Q (instanceRef FF_59))
+              (portRef D (instanceRef FF_27))))
+          (net ircount_14
+            (joined
+              (portRef S0 (instanceRef r_ctr_7))
+              (portRef D (instanceRef FF_58))))
+          (net ircount_15
+            (joined
+              (portRef S1 (instanceRef r_ctr_7))
+              (portRef D (instanceRef FF_57))))
+          (net co7_2
+            (joined
+              (portRef COUT (instanceRef r_ctr_7))))
+          (net co6_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_7))
+              (portRef COUT (instanceRef r_ctr_6))))
+          (net rcount_14
+            (joined
+              (portRef A0 (instanceRef r_ctr_7))
+              (portRef Q (instanceRef FF_58))
+              (portRef D (instanceRef FF_26))))
+          (net rcount_15
+            (joined
+              (portRef A1 (instanceRef r_ctr_7))
+              (portRef Q (instanceRef FF_57))
+              (portRef D (instanceRef FF_25))))
+          (net mdout1_15_0
+            (joined
+              (portRef D15 (instanceRef mux_35))
+              (portRef DOB0 (instanceRef pdp_ram_15_0_3))))
+          (net mdout1_14_0
+            (joined
+              (portRef D14 (instanceRef mux_35))
+              (portRef DOB0 (instanceRef pdp_ram_14_0_7))))
+          (net mdout1_13_0
+            (joined
+              (portRef D13 (instanceRef mux_35))
+              (portRef DOB0 (instanceRef pdp_ram_13_0_11))))
+          (net mdout1_12_0
+            (joined
+              (portRef D12 (instanceRef mux_35))
+              (portRef DOB0 (instanceRef pdp_ram_12_0_15))))
+          (net mdout1_11_0
+            (joined
+              (portRef D11 (instanceRef mux_35))
+              (portRef DOB0 (instanceRef pdp_ram_11_0_19))))
+          (net mdout1_10_0
+            (joined
+              (portRef D10 (instanceRef mux_35))
+              (portRef DOB0 (instanceRef pdp_ram_10_0_23))))
+          (net mdout1_9_0
+            (joined
+              (portRef D9 (instanceRef mux_35))
+              (portRef DOB0 (instanceRef pdp_ram_9_0_27))))
+          (net mdout1_8_0
+            (joined
+              (portRef D8 (instanceRef mux_35))
+              (portRef DOB0 (instanceRef pdp_ram_8_0_31))))
+          (net mdout1_7_0
+            (joined
+              (portRef D7 (instanceRef mux_35))
+              (portRef DOB0 (instanceRef pdp_ram_7_0_35))))
+          (net mdout1_6_0
+            (joined
+              (portRef D6 (instanceRef mux_35))
+              (portRef DOB0 (instanceRef pdp_ram_6_0_39))))
+          (net mdout1_5_0
+            (joined
+              (portRef D5 (instanceRef mux_35))
+              (portRef DOB0 (instanceRef pdp_ram_5_0_43))))
+          (net mdout1_4_0
+            (joined
+              (portRef D4 (instanceRef mux_35))
+              (portRef DOB0 (instanceRef pdp_ram_4_0_47))))
+          (net mdout1_3_0
+            (joined
+              (portRef D3 (instanceRef mux_35))
+              (portRef DOB0 (instanceRef pdp_ram_3_0_51))))
+          (net mdout1_2_0
+            (joined
+              (portRef D2 (instanceRef mux_35))
+              (portRef DOB0 (instanceRef pdp_ram_2_0_55))))
+          (net mdout1_1_0
+            (joined
+              (portRef D1 (instanceRef mux_35))
+              (portRef DOB0 (instanceRef pdp_ram_1_0_59))))
+          (net mdout1_0_0
+            (joined
+              (portRef D0 (instanceRef mux_35))
+              (portRef DOB0 (instanceRef pdp_ram_0_0_63))))
+          (net mdout1_15_1
+            (joined
+              (portRef D15 (instanceRef mux_34))
+              (portRef DOB1 (instanceRef pdp_ram_15_0_3))))
+          (net mdout1_14_1
+            (joined
+              (portRef D14 (instanceRef mux_34))
+              (portRef DOB1 (instanceRef pdp_ram_14_0_7))))
+          (net mdout1_13_1
+            (joined
+              (portRef D13 (instanceRef mux_34))
+              (portRef DOB1 (instanceRef pdp_ram_13_0_11))))
+          (net mdout1_12_1
+            (joined
+              (portRef D12 (instanceRef mux_34))
+              (portRef DOB1 (instanceRef pdp_ram_12_0_15))))
+          (net mdout1_11_1
+            (joined
+              (portRef D11 (instanceRef mux_34))
+              (portRef DOB1 (instanceRef pdp_ram_11_0_19))))
+          (net mdout1_10_1
+            (joined
+              (portRef D10 (instanceRef mux_34))
+              (portRef DOB1 (instanceRef pdp_ram_10_0_23))))
+          (net mdout1_9_1
+            (joined
+              (portRef D9 (instanceRef mux_34))
+              (portRef DOB1 (instanceRef pdp_ram_9_0_27))))
+          (net mdout1_8_1
+            (joined
+              (portRef D8 (instanceRef mux_34))
+              (portRef DOB1 (instanceRef pdp_ram_8_0_31))))
+          (net mdout1_7_1
+            (joined
+              (portRef D7 (instanceRef mux_34))
+              (portRef DOB1 (instanceRef pdp_ram_7_0_35))))
+          (net mdout1_6_1
+            (joined
+              (portRef D6 (instanceRef mux_34))
+              (portRef DOB1 (instanceRef pdp_ram_6_0_39))))
+          (net mdout1_5_1
+            (joined
+              (portRef D5 (instanceRef mux_34))
+              (portRef DOB1 (instanceRef pdp_ram_5_0_43))))
+          (net mdout1_4_1
+            (joined
+              (portRef D4 (instanceRef mux_34))
+              (portRef DOB1 (instanceRef pdp_ram_4_0_47))))
+          (net mdout1_3_1
+            (joined
+              (portRef D3 (instanceRef mux_34))
+              (portRef DOB1 (instanceRef pdp_ram_3_0_51))))
+          (net mdout1_2_1
+            (joined
+              (portRef D2 (instanceRef mux_34))
+              (portRef DOB1 (instanceRef pdp_ram_2_0_55))))
+          (net mdout1_1_1
+            (joined
+              (portRef D1 (instanceRef mux_34))
+              (portRef DOB1 (instanceRef pdp_ram_1_0_59))))
+          (net mdout1_0_1
+            (joined
+              (portRef D0 (instanceRef mux_34))
+              (portRef DOB1 (instanceRef pdp_ram_0_0_63))))
+          (net mdout1_15_2
+            (joined
+              (portRef D15 (instanceRef mux_33))
+              (portRef DOB2 (instanceRef pdp_ram_15_0_3))))
+          (net mdout1_14_2
+            (joined
+              (portRef D14 (instanceRef mux_33))
+              (portRef DOB2 (instanceRef pdp_ram_14_0_7))))
+          (net mdout1_13_2
+            (joined
+              (portRef D13 (instanceRef mux_33))
+              (portRef DOB2 (instanceRef pdp_ram_13_0_11))))
+          (net mdout1_12_2
+            (joined
+              (portRef D12 (instanceRef mux_33))
+              (portRef DOB2 (instanceRef pdp_ram_12_0_15))))
+          (net mdout1_11_2
+            (joined
+              (portRef D11 (instanceRef mux_33))
+              (portRef DOB2 (instanceRef pdp_ram_11_0_19))))
+          (net mdout1_10_2
+            (joined
+              (portRef D10 (instanceRef mux_33))
+              (portRef DOB2 (instanceRef pdp_ram_10_0_23))))
+          (net mdout1_9_2
+            (joined
+              (portRef D9 (instanceRef mux_33))
+              (portRef DOB2 (instanceRef pdp_ram_9_0_27))))
+          (net mdout1_8_2
+            (joined
+              (portRef D8 (instanceRef mux_33))
+              (portRef DOB2 (instanceRef pdp_ram_8_0_31))))
+          (net mdout1_7_2
+            (joined
+              (portRef D7 (instanceRef mux_33))
+              (portRef DOB2 (instanceRef pdp_ram_7_0_35))))
+          (net mdout1_6_2
+            (joined
+              (portRef D6 (instanceRef mux_33))
+              (portRef DOB2 (instanceRef pdp_ram_6_0_39))))
+          (net mdout1_5_2
+            (joined
+              (portRef D5 (instanceRef mux_33))
+              (portRef DOB2 (instanceRef pdp_ram_5_0_43))))
+          (net mdout1_4_2
+            (joined
+              (portRef D4 (instanceRef mux_33))
+              (portRef DOB2 (instanceRef pdp_ram_4_0_47))))
+          (net mdout1_3_2
+            (joined
+              (portRef D3 (instanceRef mux_33))
+              (portRef DOB2 (instanceRef pdp_ram_3_0_51))))
+          (net mdout1_2_2
+            (joined
+              (portRef D2 (instanceRef mux_33))
+              (portRef DOB2 (instanceRef pdp_ram_2_0_55))))
+          (net mdout1_1_2
+            (joined
+              (portRef D1 (instanceRef mux_33))
+              (portRef DOB2 (instanceRef pdp_ram_1_0_59))))
+          (net mdout1_0_2
+            (joined
+              (portRef D0 (instanceRef mux_33))
+              (portRef DOB2 (instanceRef pdp_ram_0_0_63))))
+          (net mdout1_15_3
+            (joined
+              (portRef D15 (instanceRef mux_32))
+              (portRef DOB3 (instanceRef pdp_ram_15_0_3))))
+          (net mdout1_14_3
+            (joined
+              (portRef D14 (instanceRef mux_32))
+              (portRef DOB3 (instanceRef pdp_ram_14_0_7))))
+          (net mdout1_13_3
+            (joined
+              (portRef D13 (instanceRef mux_32))
+              (portRef DOB3 (instanceRef pdp_ram_13_0_11))))
+          (net mdout1_12_3
+            (joined
+              (portRef D12 (instanceRef mux_32))
+              (portRef DOB3 (instanceRef pdp_ram_12_0_15))))
+          (net mdout1_11_3
+            (joined
+              (portRef D11 (instanceRef mux_32))
+              (portRef DOB3 (instanceRef pdp_ram_11_0_19))))
+          (net mdout1_10_3
+            (joined
+              (portRef D10 (instanceRef mux_32))
+              (portRef DOB3 (instanceRef pdp_ram_10_0_23))))
+          (net mdout1_9_3
+            (joined
+              (portRef D9 (instanceRef mux_32))
+              (portRef DOB3 (instanceRef pdp_ram_9_0_27))))
+          (net mdout1_8_3
+            (joined
+              (portRef D8 (instanceRef mux_32))
+              (portRef DOB3 (instanceRef pdp_ram_8_0_31))))
+          (net mdout1_7_3
+            (joined
+              (portRef D7 (instanceRef mux_32))
+              (portRef DOB3 (instanceRef pdp_ram_7_0_35))))
+          (net mdout1_6_3
+            (joined
+              (portRef D6 (instanceRef mux_32))
+              (portRef DOB3 (instanceRef pdp_ram_6_0_39))))
+          (net mdout1_5_3
+            (joined
+              (portRef D5 (instanceRef mux_32))
+              (portRef DOB3 (instanceRef pdp_ram_5_0_43))))
+          (net mdout1_4_3
+            (joined
+              (portRef D4 (instanceRef mux_32))
+              (portRef DOB3 (instanceRef pdp_ram_4_0_47))))
+          (net mdout1_3_3
+            (joined
+              (portRef D3 (instanceRef mux_32))
+              (portRef DOB3 (instanceRef pdp_ram_3_0_51))))
+          (net mdout1_2_3
+            (joined
+              (portRef D2 (instanceRef mux_32))
+              (portRef DOB3 (instanceRef pdp_ram_2_0_55))))
+          (net mdout1_1_3
+            (joined
+              (portRef D1 (instanceRef mux_32))
+              (portRef DOB3 (instanceRef pdp_ram_1_0_59))))
+          (net mdout1_0_3
+            (joined
+              (portRef D0 (instanceRef mux_32))
+              (portRef DOB3 (instanceRef pdp_ram_0_0_63))))
+          (net mdout1_15_4
+            (joined
+              (portRef D15 (instanceRef mux_31))
+              (portRef DOB4 (instanceRef pdp_ram_15_0_3))))
+          (net mdout1_14_4
+            (joined
+              (portRef D14 (instanceRef mux_31))
+              (portRef DOB4 (instanceRef pdp_ram_14_0_7))))
+          (net mdout1_13_4
+            (joined
+              (portRef D13 (instanceRef mux_31))
+              (portRef DOB4 (instanceRef pdp_ram_13_0_11))))
+          (net mdout1_12_4
+            (joined
+              (portRef D12 (instanceRef mux_31))
+              (portRef DOB4 (instanceRef pdp_ram_12_0_15))))
+          (net mdout1_11_4
+            (joined
+              (portRef D11 (instanceRef mux_31))
+              (portRef DOB4 (instanceRef pdp_ram_11_0_19))))
+          (net mdout1_10_4
+            (joined
+              (portRef D10 (instanceRef mux_31))
+              (portRef DOB4 (instanceRef pdp_ram_10_0_23))))
+          (net mdout1_9_4
+            (joined
+              (portRef D9 (instanceRef mux_31))
+              (portRef DOB4 (instanceRef pdp_ram_9_0_27))))
+          (net mdout1_8_4
+            (joined
+              (portRef D8 (instanceRef mux_31))
+              (portRef DOB4 (instanceRef pdp_ram_8_0_31))))
+          (net mdout1_7_4
+            (joined
+              (portRef D7 (instanceRef mux_31))
+              (portRef DOB4 (instanceRef pdp_ram_7_0_35))))
+          (net mdout1_6_4
+            (joined
+              (portRef D6 (instanceRef mux_31))
+              (portRef DOB4 (instanceRef pdp_ram_6_0_39))))
+          (net mdout1_5_4
+            (joined
+              (portRef D5 (instanceRef mux_31))
+              (portRef DOB4 (instanceRef pdp_ram_5_0_43))))
+          (net mdout1_4_4
+            (joined
+              (portRef D4 (instanceRef mux_31))
+              (portRef DOB4 (instanceRef pdp_ram_4_0_47))))
+          (net mdout1_3_4
+            (joined
+              (portRef D3 (instanceRef mux_31))
+              (portRef DOB4 (instanceRef pdp_ram_3_0_51))))
+          (net mdout1_2_4
+            (joined
+              (portRef D2 (instanceRef mux_31))
+              (portRef DOB4 (instanceRef pdp_ram_2_0_55))))
+          (net mdout1_1_4
+            (joined
+              (portRef D1 (instanceRef mux_31))
+              (portRef DOB4 (instanceRef pdp_ram_1_0_59))))
+          (net mdout1_0_4
+            (joined
+              (portRef D0 (instanceRef mux_31))
+              (portRef DOB4 (instanceRef pdp_ram_0_0_63))))
+          (net mdout1_15_5
+            (joined
+              (portRef D15 (instanceRef mux_30))
+              (portRef DOB5 (instanceRef pdp_ram_15_0_3))))
+          (net mdout1_14_5
+            (joined
+              (portRef D14 (instanceRef mux_30))
+              (portRef DOB5 (instanceRef pdp_ram_14_0_7))))
+          (net mdout1_13_5
+            (joined
+              (portRef D13 (instanceRef mux_30))
+              (portRef DOB5 (instanceRef pdp_ram_13_0_11))))
+          (net mdout1_12_5
+            (joined
+              (portRef D12 (instanceRef mux_30))
+              (portRef DOB5 (instanceRef pdp_ram_12_0_15))))
+          (net mdout1_11_5
+            (joined
+              (portRef D11 (instanceRef mux_30))
+              (portRef DOB5 (instanceRef pdp_ram_11_0_19))))
+          (net mdout1_10_5
+            (joined
+              (portRef D10 (instanceRef mux_30))
+              (portRef DOB5 (instanceRef pdp_ram_10_0_23))))
+          (net mdout1_9_5
+            (joined
+              (portRef D9 (instanceRef mux_30))
+              (portRef DOB5 (instanceRef pdp_ram_9_0_27))))
+          (net mdout1_8_5
+            (joined
+              (portRef D8 (instanceRef mux_30))
+              (portRef DOB5 (instanceRef pdp_ram_8_0_31))))
+          (net mdout1_7_5
+            (joined
+              (portRef D7 (instanceRef mux_30))
+              (portRef DOB5 (instanceRef pdp_ram_7_0_35))))
+          (net mdout1_6_5
+            (joined
+              (portRef D6 (instanceRef mux_30))
+              (portRef DOB5 (instanceRef pdp_ram_6_0_39))))
+          (net mdout1_5_5
+            (joined
+              (portRef D5 (instanceRef mux_30))
+              (portRef DOB5 (instanceRef pdp_ram_5_0_43))))
+          (net mdout1_4_5
+            (joined
+              (portRef D4 (instanceRef mux_30))
+              (portRef DOB5 (instanceRef pdp_ram_4_0_47))))
+          (net mdout1_3_5
+            (joined
+              (portRef D3 (instanceRef mux_30))
+              (portRef DOB5 (instanceRef pdp_ram_3_0_51))))
+          (net mdout1_2_5
+            (joined
+              (portRef D2 (instanceRef mux_30))
+              (portRef DOB5 (instanceRef pdp_ram_2_0_55))))
+          (net mdout1_1_5
+            (joined
+              (portRef D1 (instanceRef mux_30))
+              (portRef DOB5 (instanceRef pdp_ram_1_0_59))))
+          (net mdout1_0_5
+            (joined
+              (portRef D0 (instanceRef mux_30))
+              (portRef DOB5 (instanceRef pdp_ram_0_0_63))))
+          (net mdout1_15_6
+            (joined
+              (portRef D15 (instanceRef mux_29))
+              (portRef DOB6 (instanceRef pdp_ram_15_0_3))))
+          (net mdout1_14_6
+            (joined
+              (portRef D14 (instanceRef mux_29))
+              (portRef DOB6 (instanceRef pdp_ram_14_0_7))))
+          (net mdout1_13_6
+            (joined
+              (portRef D13 (instanceRef mux_29))
+              (portRef DOB6 (instanceRef pdp_ram_13_0_11))))
+          (net mdout1_12_6
+            (joined
+              (portRef D12 (instanceRef mux_29))
+              (portRef DOB6 (instanceRef pdp_ram_12_0_15))))
+          (net mdout1_11_6
+            (joined
+              (portRef D11 (instanceRef mux_29))
+              (portRef DOB6 (instanceRef pdp_ram_11_0_19))))
+          (net mdout1_10_6
+            (joined
+              (portRef D10 (instanceRef mux_29))
+              (portRef DOB6 (instanceRef pdp_ram_10_0_23))))
+          (net mdout1_9_6
+            (joined
+              (portRef D9 (instanceRef mux_29))
+              (portRef DOB6 (instanceRef pdp_ram_9_0_27))))
+          (net mdout1_8_6
+            (joined
+              (portRef D8 (instanceRef mux_29))
+              (portRef DOB6 (instanceRef pdp_ram_8_0_31))))
+          (net mdout1_7_6
+            (joined
+              (portRef D7 (instanceRef mux_29))
+              (portRef DOB6 (instanceRef pdp_ram_7_0_35))))
+          (net mdout1_6_6
+            (joined
+              (portRef D6 (instanceRef mux_29))
+              (portRef DOB6 (instanceRef pdp_ram_6_0_39))))
+          (net mdout1_5_6
+            (joined
+              (portRef D5 (instanceRef mux_29))
+              (portRef DOB6 (instanceRef pdp_ram_5_0_43))))
+          (net mdout1_4_6
+            (joined
+              (portRef D4 (instanceRef mux_29))
+              (portRef DOB6 (instanceRef pdp_ram_4_0_47))))
+          (net mdout1_3_6
+            (joined
+              (portRef D3 (instanceRef mux_29))
+              (portRef DOB6 (instanceRef pdp_ram_3_0_51))))
+          (net mdout1_2_6
+            (joined
+              (portRef D2 (instanceRef mux_29))
+              (portRef DOB6 (instanceRef pdp_ram_2_0_55))))
+          (net mdout1_1_6
+            (joined
+              (portRef D1 (instanceRef mux_29))
+              (portRef DOB6 (instanceRef pdp_ram_1_0_59))))
+          (net mdout1_0_6
+            (joined
+              (portRef D0 (instanceRef mux_29))
+              (portRef DOB6 (instanceRef pdp_ram_0_0_63))))
+          (net mdout1_15_7
+            (joined
+              (portRef D15 (instanceRef mux_28))
+              (portRef DOB7 (instanceRef pdp_ram_15_0_3))))
+          (net mdout1_14_7
+            (joined
+              (portRef D14 (instanceRef mux_28))
+              (portRef DOB7 (instanceRef pdp_ram_14_0_7))))
+          (net mdout1_13_7
+            (joined
+              (portRef D13 (instanceRef mux_28))
+              (portRef DOB7 (instanceRef pdp_ram_13_0_11))))
+          (net mdout1_12_7
+            (joined
+              (portRef D12 (instanceRef mux_28))
+              (portRef DOB7 (instanceRef pdp_ram_12_0_15))))
+          (net mdout1_11_7
+            (joined
+              (portRef D11 (instanceRef mux_28))
+              (portRef DOB7 (instanceRef pdp_ram_11_0_19))))
+          (net mdout1_10_7
+            (joined
+              (portRef D10 (instanceRef mux_28))
+              (portRef DOB7 (instanceRef pdp_ram_10_0_23))))
+          (net mdout1_9_7
+            (joined
+              (portRef D9 (instanceRef mux_28))
+              (portRef DOB7 (instanceRef pdp_ram_9_0_27))))
+          (net mdout1_8_7
+            (joined
+              (portRef D8 (instanceRef mux_28))
+              (portRef DOB7 (instanceRef pdp_ram_8_0_31))))
+          (net mdout1_7_7
+            (joined
+              (portRef D7 (instanceRef mux_28))
+              (portRef DOB7 (instanceRef pdp_ram_7_0_35))))
+          (net mdout1_6_7
+            (joined
+              (portRef D6 (instanceRef mux_28))
+              (portRef DOB7 (instanceRef pdp_ram_6_0_39))))
+          (net mdout1_5_7
+            (joined
+              (portRef D5 (instanceRef mux_28))
+              (portRef DOB7 (instanceRef pdp_ram_5_0_43))))
+          (net mdout1_4_7
+            (joined
+              (portRef D4 (instanceRef mux_28))
+              (portRef DOB7 (instanceRef pdp_ram_4_0_47))))
+          (net mdout1_3_7
+            (joined
+              (portRef D3 (instanceRef mux_28))
+              (portRef DOB7 (instanceRef pdp_ram_3_0_51))))
+          (net mdout1_2_7
+            (joined
+              (portRef D2 (instanceRef mux_28))
+              (portRef DOB7 (instanceRef pdp_ram_2_0_55))))
+          (net mdout1_1_7
+            (joined
+              (portRef D1 (instanceRef mux_28))
+              (portRef DOB7 (instanceRef pdp_ram_1_0_59))))
+          (net mdout1_0_7
+            (joined
+              (portRef D0 (instanceRef mux_28))
+              (portRef DOB7 (instanceRef pdp_ram_0_0_63))))
+          (net mdout1_15_8
+            (joined
+              (portRef D15 (instanceRef mux_27))
+              (portRef DOB8 (instanceRef pdp_ram_15_0_3))))
+          (net mdout1_14_8
+            (joined
+              (portRef D14 (instanceRef mux_27))
+              (portRef DOB8 (instanceRef pdp_ram_14_0_7))))
+          (net mdout1_13_8
+            (joined
+              (portRef D13 (instanceRef mux_27))
+              (portRef DOB8 (instanceRef pdp_ram_13_0_11))))
+          (net mdout1_12_8
+            (joined
+              (portRef D12 (instanceRef mux_27))
+              (portRef DOB8 (instanceRef pdp_ram_12_0_15))))
+          (net mdout1_11_8
+            (joined
+              (portRef D11 (instanceRef mux_27))
+              (portRef DOB8 (instanceRef pdp_ram_11_0_19))))
+          (net mdout1_10_8
+            (joined
+              (portRef D10 (instanceRef mux_27))
+              (portRef DOB8 (instanceRef pdp_ram_10_0_23))))
+          (net mdout1_9_8
+            (joined
+              (portRef D9 (instanceRef mux_27))
+              (portRef DOB8 (instanceRef pdp_ram_9_0_27))))
+          (net mdout1_8_8
+            (joined
+              (portRef D8 (instanceRef mux_27))
+              (portRef DOB8 (instanceRef pdp_ram_8_0_31))))
+          (net mdout1_7_8
+            (joined
+              (portRef D7 (instanceRef mux_27))
+              (portRef DOB8 (instanceRef pdp_ram_7_0_35))))
+          (net mdout1_6_8
+            (joined
+              (portRef D6 (instanceRef mux_27))
+              (portRef DOB8 (instanceRef pdp_ram_6_0_39))))
+          (net mdout1_5_8
+            (joined
+              (portRef D5 (instanceRef mux_27))
+              (portRef DOB8 (instanceRef pdp_ram_5_0_43))))
+          (net mdout1_4_8
+            (joined
+              (portRef D4 (instanceRef mux_27))
+              (portRef DOB8 (instanceRef pdp_ram_4_0_47))))
+          (net mdout1_3_8
+            (joined
+              (portRef D3 (instanceRef mux_27))
+              (portRef DOB8 (instanceRef pdp_ram_3_0_51))))
+          (net mdout1_2_8
+            (joined
+              (portRef D2 (instanceRef mux_27))
+              (portRef DOB8 (instanceRef pdp_ram_2_0_55))))
+          (net mdout1_1_8
+            (joined
+              (portRef D1 (instanceRef mux_27))
+              (portRef DOB8 (instanceRef pdp_ram_1_0_59))))
+          (net mdout1_0_8
+            (joined
+              (portRef D0 (instanceRef mux_27))
+              (portRef DOB8 (instanceRef pdp_ram_0_0_63))))
+          (net mdout1_15_9
+            (joined
+              (portRef D15 (instanceRef mux_26))
+              (portRef DOB0 (instanceRef pdp_ram_15_1_2))))
+          (net mdout1_14_9
+            (joined
+              (portRef D14 (instanceRef mux_26))
+              (portRef DOB0 (instanceRef pdp_ram_14_1_6))))
+          (net mdout1_13_9
+            (joined
+              (portRef D13 (instanceRef mux_26))
+              (portRef DOB0 (instanceRef pdp_ram_13_1_10))))
+          (net mdout1_12_9
+            (joined
+              (portRef D12 (instanceRef mux_26))
+              (portRef DOB0 (instanceRef pdp_ram_12_1_14))))
+          (net mdout1_11_9
+            (joined
+              (portRef D11 (instanceRef mux_26))
+              (portRef DOB0 (instanceRef pdp_ram_11_1_18))))
+          (net mdout1_10_9
+            (joined
+              (portRef D10 (instanceRef mux_26))
+              (portRef DOB0 (instanceRef pdp_ram_10_1_22))))
+          (net mdout1_9_9
+            (joined
+              (portRef D9 (instanceRef mux_26))
+              (portRef DOB0 (instanceRef pdp_ram_9_1_26))))
+          (net mdout1_8_9
+            (joined
+              (portRef D8 (instanceRef mux_26))
+              (portRef DOB0 (instanceRef pdp_ram_8_1_30))))
+          (net mdout1_7_9
+            (joined
+              (portRef D7 (instanceRef mux_26))
+              (portRef DOB0 (instanceRef pdp_ram_7_1_34))))
+          (net mdout1_6_9
+            (joined
+              (portRef D6 (instanceRef mux_26))
+              (portRef DOB0 (instanceRef pdp_ram_6_1_38))))
+          (net mdout1_5_9
+            (joined
+              (portRef D5 (instanceRef mux_26))
+              (portRef DOB0 (instanceRef pdp_ram_5_1_42))))
+          (net mdout1_4_9
+            (joined
+              (portRef D4 (instanceRef mux_26))
+              (portRef DOB0 (instanceRef pdp_ram_4_1_46))))
+          (net mdout1_3_9
+            (joined
+              (portRef D3 (instanceRef mux_26))
+              (portRef DOB0 (instanceRef pdp_ram_3_1_50))))
+          (net mdout1_2_9
+            (joined
+              (portRef D2 (instanceRef mux_26))
+              (portRef DOB0 (instanceRef pdp_ram_2_1_54))))
+          (net mdout1_1_9
+            (joined
+              (portRef D1 (instanceRef mux_26))
+              (portRef DOB0 (instanceRef pdp_ram_1_1_58))))
+          (net mdout1_0_9
+            (joined
+              (portRef D0 (instanceRef mux_26))
+              (portRef DOB0 (instanceRef pdp_ram_0_1_62))))
+          (net mdout1_15_10
+            (joined
+              (portRef D15 (instanceRef mux_25))
+              (portRef DOB1 (instanceRef pdp_ram_15_1_2))))
+          (net mdout1_14_10
+            (joined
+              (portRef D14 (instanceRef mux_25))
+              (portRef DOB1 (instanceRef pdp_ram_14_1_6))))
+          (net mdout1_13_10
+            (joined
+              (portRef D13 (instanceRef mux_25))
+              (portRef DOB1 (instanceRef pdp_ram_13_1_10))))
+          (net mdout1_12_10
+            (joined
+              (portRef D12 (instanceRef mux_25))
+              (portRef DOB1 (instanceRef pdp_ram_12_1_14))))
+          (net mdout1_11_10
+            (joined
+              (portRef D11 (instanceRef mux_25))
+              (portRef DOB1 (instanceRef pdp_ram_11_1_18))))
+          (net mdout1_10_10
+            (joined
+              (portRef D10 (instanceRef mux_25))
+              (portRef DOB1 (instanceRef pdp_ram_10_1_22))))
+          (net mdout1_9_10
+            (joined
+              (portRef D9 (instanceRef mux_25))
+              (portRef DOB1 (instanceRef pdp_ram_9_1_26))))
+          (net mdout1_8_10
+            (joined
+              (portRef D8 (instanceRef mux_25))
+              (portRef DOB1 (instanceRef pdp_ram_8_1_30))))
+          (net mdout1_7_10
+            (joined
+              (portRef D7 (instanceRef mux_25))
+              (portRef DOB1 (instanceRef pdp_ram_7_1_34))))
+          (net mdout1_6_10
+            (joined
+              (portRef D6 (instanceRef mux_25))
+              (portRef DOB1 (instanceRef pdp_ram_6_1_38))))
+          (net mdout1_5_10
+            (joined
+              (portRef D5 (instanceRef mux_25))
+              (portRef DOB1 (instanceRef pdp_ram_5_1_42))))
+          (net mdout1_4_10
+            (joined
+              (portRef D4 (instanceRef mux_25))
+              (portRef DOB1 (instanceRef pdp_ram_4_1_46))))
+          (net mdout1_3_10
+            (joined
+              (portRef D3 (instanceRef mux_25))
+              (portRef DOB1 (instanceRef pdp_ram_3_1_50))))
+          (net mdout1_2_10
+            (joined
+              (portRef D2 (instanceRef mux_25))
+              (portRef DOB1 (instanceRef pdp_ram_2_1_54))))
+          (net mdout1_1_10
+            (joined
+              (portRef D1 (instanceRef mux_25))
+              (portRef DOB1 (instanceRef pdp_ram_1_1_58))))
+          (net mdout1_0_10
+            (joined
+              (portRef D0 (instanceRef mux_25))
+              (portRef DOB1 (instanceRef pdp_ram_0_1_62))))
+          (net mdout1_15_11
+            (joined
+              (portRef D15 (instanceRef mux_24))
+              (portRef DOB2 (instanceRef pdp_ram_15_1_2))))
+          (net mdout1_14_11
+            (joined
+              (portRef D14 (instanceRef mux_24))
+              (portRef DOB2 (instanceRef pdp_ram_14_1_6))))
+          (net mdout1_13_11
+            (joined
+              (portRef D13 (instanceRef mux_24))
+              (portRef DOB2 (instanceRef pdp_ram_13_1_10))))
+          (net mdout1_12_11
+            (joined
+              (portRef D12 (instanceRef mux_24))
+              (portRef DOB2 (instanceRef pdp_ram_12_1_14))))
+          (net mdout1_11_11
+            (joined
+              (portRef D11 (instanceRef mux_24))
+              (portRef DOB2 (instanceRef pdp_ram_11_1_18))))
+          (net mdout1_10_11
+            (joined
+              (portRef D10 (instanceRef mux_24))
+              (portRef DOB2 (instanceRef pdp_ram_10_1_22))))
+          (net mdout1_9_11
+            (joined
+              (portRef D9 (instanceRef mux_24))
+              (portRef DOB2 (instanceRef pdp_ram_9_1_26))))
+          (net mdout1_8_11
+            (joined
+              (portRef D8 (instanceRef mux_24))
+              (portRef DOB2 (instanceRef pdp_ram_8_1_30))))
+          (net mdout1_7_11
+            (joined
+              (portRef D7 (instanceRef mux_24))
+              (portRef DOB2 (instanceRef pdp_ram_7_1_34))))
+          (net mdout1_6_11
+            (joined
+              (portRef D6 (instanceRef mux_24))
+              (portRef DOB2 (instanceRef pdp_ram_6_1_38))))
+          (net mdout1_5_11
+            (joined
+              (portRef D5 (instanceRef mux_24))
+              (portRef DOB2 (instanceRef pdp_ram_5_1_42))))
+          (net mdout1_4_11
+            (joined
+              (portRef D4 (instanceRef mux_24))
+              (portRef DOB2 (instanceRef pdp_ram_4_1_46))))
+          (net mdout1_3_11
+            (joined
+              (portRef D3 (instanceRef mux_24))
+              (portRef DOB2 (instanceRef pdp_ram_3_1_50))))
+          (net mdout1_2_11
+            (joined
+              (portRef D2 (instanceRef mux_24))
+              (portRef DOB2 (instanceRef pdp_ram_2_1_54))))
+          (net mdout1_1_11
+            (joined
+              (portRef D1 (instanceRef mux_24))
+              (portRef DOB2 (instanceRef pdp_ram_1_1_58))))
+          (net mdout1_0_11
+            (joined
+              (portRef D0 (instanceRef mux_24))
+              (portRef DOB2 (instanceRef pdp_ram_0_1_62))))
+          (net mdout1_15_12
+            (joined
+              (portRef D15 (instanceRef mux_23))
+              (portRef DOB3 (instanceRef pdp_ram_15_1_2))))
+          (net mdout1_14_12
+            (joined
+              (portRef D14 (instanceRef mux_23))
+              (portRef DOB3 (instanceRef pdp_ram_14_1_6))))
+          (net mdout1_13_12
+            (joined
+              (portRef D13 (instanceRef mux_23))
+              (portRef DOB3 (instanceRef pdp_ram_13_1_10))))
+          (net mdout1_12_12
+            (joined
+              (portRef D12 (instanceRef mux_23))
+              (portRef DOB3 (instanceRef pdp_ram_12_1_14))))
+          (net mdout1_11_12
+            (joined
+              (portRef D11 (instanceRef mux_23))
+              (portRef DOB3 (instanceRef pdp_ram_11_1_18))))
+          (net mdout1_10_12
+            (joined
+              (portRef D10 (instanceRef mux_23))
+              (portRef DOB3 (instanceRef pdp_ram_10_1_22))))
+          (net mdout1_9_12
+            (joined
+              (portRef D9 (instanceRef mux_23))
+              (portRef DOB3 (instanceRef pdp_ram_9_1_26))))
+          (net mdout1_8_12
+            (joined
+              (portRef D8 (instanceRef mux_23))
+              (portRef DOB3 (instanceRef pdp_ram_8_1_30))))
+          (net mdout1_7_12
+            (joined
+              (portRef D7 (instanceRef mux_23))
+              (portRef DOB3 (instanceRef pdp_ram_7_1_34))))
+          (net mdout1_6_12
+            (joined
+              (portRef D6 (instanceRef mux_23))
+              (portRef DOB3 (instanceRef pdp_ram_6_1_38))))
+          (net mdout1_5_12
+            (joined
+              (portRef D5 (instanceRef mux_23))
+              (portRef DOB3 (instanceRef pdp_ram_5_1_42))))
+          (net mdout1_4_12
+            (joined
+              (portRef D4 (instanceRef mux_23))
+              (portRef DOB3 (instanceRef pdp_ram_4_1_46))))
+          (net mdout1_3_12
+            (joined
+              (portRef D3 (instanceRef mux_23))
+              (portRef DOB3 (instanceRef pdp_ram_3_1_50))))
+          (net mdout1_2_12
+            (joined
+              (portRef D2 (instanceRef mux_23))
+              (portRef DOB3 (instanceRef pdp_ram_2_1_54))))
+          (net mdout1_1_12
+            (joined
+              (portRef D1 (instanceRef mux_23))
+              (portRef DOB3 (instanceRef pdp_ram_1_1_58))))
+          (net mdout1_0_12
+            (joined
+              (portRef D0 (instanceRef mux_23))
+              (portRef DOB3 (instanceRef pdp_ram_0_1_62))))
+          (net mdout1_15_13
+            (joined
+              (portRef D15 (instanceRef mux_22))
+              (portRef DOB4 (instanceRef pdp_ram_15_1_2))))
+          (net mdout1_14_13
+            (joined
+              (portRef D14 (instanceRef mux_22))
+              (portRef DOB4 (instanceRef pdp_ram_14_1_6))))
+          (net mdout1_13_13
+            (joined
+              (portRef D13 (instanceRef mux_22))
+              (portRef DOB4 (instanceRef pdp_ram_13_1_10))))
+          (net mdout1_12_13
+            (joined
+              (portRef D12 (instanceRef mux_22))
+              (portRef DOB4 (instanceRef pdp_ram_12_1_14))))
+          (net mdout1_11_13
+            (joined
+              (portRef D11 (instanceRef mux_22))
+              (portRef DOB4 (instanceRef pdp_ram_11_1_18))))
+          (net mdout1_10_13
+            (joined
+              (portRef D10 (instanceRef mux_22))
+              (portRef DOB4 (instanceRef pdp_ram_10_1_22))))
+          (net mdout1_9_13
+            (joined
+              (portRef D9 (instanceRef mux_22))
+              (portRef DOB4 (instanceRef pdp_ram_9_1_26))))
+          (net mdout1_8_13
+            (joined
+              (portRef D8 (instanceRef mux_22))
+              (portRef DOB4 (instanceRef pdp_ram_8_1_30))))
+          (net mdout1_7_13
+            (joined
+              (portRef D7 (instanceRef mux_22))
+              (portRef DOB4 (instanceRef pdp_ram_7_1_34))))
+          (net mdout1_6_13
+            (joined
+              (portRef D6 (instanceRef mux_22))
+              (portRef DOB4 (instanceRef pdp_ram_6_1_38))))
+          (net mdout1_5_13
+            (joined
+              (portRef D5 (instanceRef mux_22))
+              (portRef DOB4 (instanceRef pdp_ram_5_1_42))))
+          (net mdout1_4_13
+            (joined
+              (portRef D4 (instanceRef mux_22))
+              (portRef DOB4 (instanceRef pdp_ram_4_1_46))))
+          (net mdout1_3_13
+            (joined
+              (portRef D3 (instanceRef mux_22))
+              (portRef DOB4 (instanceRef pdp_ram_3_1_50))))
+          (net mdout1_2_13
+            (joined
+              (portRef D2 (instanceRef mux_22))
+              (portRef DOB4 (instanceRef pdp_ram_2_1_54))))
+          (net mdout1_1_13
+            (joined
+              (portRef D1 (instanceRef mux_22))
+              (portRef DOB4 (instanceRef pdp_ram_1_1_58))))
+          (net mdout1_0_13
+            (joined
+              (portRef D0 (instanceRef mux_22))
+              (portRef DOB4 (instanceRef pdp_ram_0_1_62))))
+          (net mdout1_15_14
+            (joined
+              (portRef D15 (instanceRef mux_21))
+              (portRef DOB5 (instanceRef pdp_ram_15_1_2))))
+          (net mdout1_14_14
+            (joined
+              (portRef D14 (instanceRef mux_21))
+              (portRef DOB5 (instanceRef pdp_ram_14_1_6))))
+          (net mdout1_13_14
+            (joined
+              (portRef D13 (instanceRef mux_21))
+              (portRef DOB5 (instanceRef pdp_ram_13_1_10))))
+          (net mdout1_12_14
+            (joined
+              (portRef D12 (instanceRef mux_21))
+              (portRef DOB5 (instanceRef pdp_ram_12_1_14))))
+          (net mdout1_11_14
+            (joined
+              (portRef D11 (instanceRef mux_21))
+              (portRef DOB5 (instanceRef pdp_ram_11_1_18))))
+          (net mdout1_10_14
+            (joined
+              (portRef D10 (instanceRef mux_21))
+              (portRef DOB5 (instanceRef pdp_ram_10_1_22))))
+          (net mdout1_9_14
+            (joined
+              (portRef D9 (instanceRef mux_21))
+              (portRef DOB5 (instanceRef pdp_ram_9_1_26))))
+          (net mdout1_8_14
+            (joined
+              (portRef D8 (instanceRef mux_21))
+              (portRef DOB5 (instanceRef pdp_ram_8_1_30))))
+          (net mdout1_7_14
+            (joined
+              (portRef D7 (instanceRef mux_21))
+              (portRef DOB5 (instanceRef pdp_ram_7_1_34))))
+          (net mdout1_6_14
+            (joined
+              (portRef D6 (instanceRef mux_21))
+              (portRef DOB5 (instanceRef pdp_ram_6_1_38))))
+          (net mdout1_5_14
+            (joined
+              (portRef D5 (instanceRef mux_21))
+              (portRef DOB5 (instanceRef pdp_ram_5_1_42))))
+          (net mdout1_4_14
+            (joined
+              (portRef D4 (instanceRef mux_21))
+              (portRef DOB5 (instanceRef pdp_ram_4_1_46))))
+          (net mdout1_3_14
+            (joined
+              (portRef D3 (instanceRef mux_21))
+              (portRef DOB5 (instanceRef pdp_ram_3_1_50))))
+          (net mdout1_2_14
+            (joined
+              (portRef D2 (instanceRef mux_21))
+              (portRef DOB5 (instanceRef pdp_ram_2_1_54))))
+          (net mdout1_1_14
+            (joined
+              (portRef D1 (instanceRef mux_21))
+              (portRef DOB5 (instanceRef pdp_ram_1_1_58))))
+          (net mdout1_0_14
+            (joined
+              (portRef D0 (instanceRef mux_21))
+              (portRef DOB5 (instanceRef pdp_ram_0_1_62))))
+          (net mdout1_15_15
+            (joined
+              (portRef D15 (instanceRef mux_20))
+              (portRef DOB6 (instanceRef pdp_ram_15_1_2))))
+          (net mdout1_14_15
+            (joined
+              (portRef D14 (instanceRef mux_20))
+              (portRef DOB6 (instanceRef pdp_ram_14_1_6))))
+          (net mdout1_13_15
+            (joined
+              (portRef D13 (instanceRef mux_20))
+              (portRef DOB6 (instanceRef pdp_ram_13_1_10))))
+          (net mdout1_12_15
+            (joined
+              (portRef D12 (instanceRef mux_20))
+              (portRef DOB6 (instanceRef pdp_ram_12_1_14))))
+          (net mdout1_11_15
+            (joined
+              (portRef D11 (instanceRef mux_20))
+              (portRef DOB6 (instanceRef pdp_ram_11_1_18))))
+          (net mdout1_10_15
+            (joined
+              (portRef D10 (instanceRef mux_20))
+              (portRef DOB6 (instanceRef pdp_ram_10_1_22))))
+          (net mdout1_9_15
+            (joined
+              (portRef D9 (instanceRef mux_20))
+              (portRef DOB6 (instanceRef pdp_ram_9_1_26))))
+          (net mdout1_8_15
+            (joined
+              (portRef D8 (instanceRef mux_20))
+              (portRef DOB6 (instanceRef pdp_ram_8_1_30))))
+          (net mdout1_7_15
+            (joined
+              (portRef D7 (instanceRef mux_20))
+              (portRef DOB6 (instanceRef pdp_ram_7_1_34))))
+          (net mdout1_6_15
+            (joined
+              (portRef D6 (instanceRef mux_20))
+              (portRef DOB6 (instanceRef pdp_ram_6_1_38))))
+          (net mdout1_5_15
+            (joined
+              (portRef D5 (instanceRef mux_20))
+              (portRef DOB6 (instanceRef pdp_ram_5_1_42))))
+          (net mdout1_4_15
+            (joined
+              (portRef D4 (instanceRef mux_20))
+              (portRef DOB6 (instanceRef pdp_ram_4_1_46))))
+          (net mdout1_3_15
+            (joined
+              (portRef D3 (instanceRef mux_20))
+              (portRef DOB6 (instanceRef pdp_ram_3_1_50))))
+          (net mdout1_2_15
+            (joined
+              (portRef D2 (instanceRef mux_20))
+              (portRef DOB6 (instanceRef pdp_ram_2_1_54))))
+          (net mdout1_1_15
+            (joined
+              (portRef D1 (instanceRef mux_20))
+              (portRef DOB6 (instanceRef pdp_ram_1_1_58))))
+          (net mdout1_0_15
+            (joined
+              (portRef D0 (instanceRef mux_20))
+              (portRef DOB6 (instanceRef pdp_ram_0_1_62))))
+          (net mdout1_15_16
+            (joined
+              (portRef D15 (instanceRef mux_19))
+              (portRef DOB7 (instanceRef pdp_ram_15_1_2))))
+          (net mdout1_14_16
+            (joined
+              (portRef D14 (instanceRef mux_19))
+              (portRef DOB7 (instanceRef pdp_ram_14_1_6))))
+          (net mdout1_13_16
+            (joined
+              (portRef D13 (instanceRef mux_19))
+              (portRef DOB7 (instanceRef pdp_ram_13_1_10))))
+          (net mdout1_12_16
+            (joined
+              (portRef D12 (instanceRef mux_19))
+              (portRef DOB7 (instanceRef pdp_ram_12_1_14))))
+          (net mdout1_11_16
+            (joined
+              (portRef D11 (instanceRef mux_19))
+              (portRef DOB7 (instanceRef pdp_ram_11_1_18))))
+          (net mdout1_10_16
+            (joined
+              (portRef D10 (instanceRef mux_19))
+              (portRef DOB7 (instanceRef pdp_ram_10_1_22))))
+          (net mdout1_9_16
+            (joined
+              (portRef D9 (instanceRef mux_19))
+              (portRef DOB7 (instanceRef pdp_ram_9_1_26))))
+          (net mdout1_8_16
+            (joined
+              (portRef D8 (instanceRef mux_19))
+              (portRef DOB7 (instanceRef pdp_ram_8_1_30))))
+          (net mdout1_7_16
+            (joined
+              (portRef D7 (instanceRef mux_19))
+              (portRef DOB7 (instanceRef pdp_ram_7_1_34))))
+          (net mdout1_6_16
+            (joined
+              (portRef D6 (instanceRef mux_19))
+              (portRef DOB7 (instanceRef pdp_ram_6_1_38))))
+          (net mdout1_5_16
+            (joined
+              (portRef D5 (instanceRef mux_19))
+              (portRef DOB7 (instanceRef pdp_ram_5_1_42))))
+          (net mdout1_4_16
+            (joined
+              (portRef D4 (instanceRef mux_19))
+              (portRef DOB7 (instanceRef pdp_ram_4_1_46))))
+          (net mdout1_3_16
+            (joined
+              (portRef D3 (instanceRef mux_19))
+              (portRef DOB7 (instanceRef pdp_ram_3_1_50))))
+          (net mdout1_2_16
+            (joined
+              (portRef D2 (instanceRef mux_19))
+              (portRef DOB7 (instanceRef pdp_ram_2_1_54))))
+          (net mdout1_1_16
+            (joined
+              (portRef D1 (instanceRef mux_19))
+              (portRef DOB7 (instanceRef pdp_ram_1_1_58))))
+          (net mdout1_0_16
+            (joined
+              (portRef D0 (instanceRef mux_19))
+              (portRef DOB7 (instanceRef pdp_ram_0_1_62))))
+          (net mdout1_15_17
+            (joined
+              (portRef D15 (instanceRef mux_18))
+              (portRef DOB8 (instanceRef pdp_ram_15_1_2))))
+          (net mdout1_14_17
+            (joined
+              (portRef D14 (instanceRef mux_18))
+              (portRef DOB8 (instanceRef pdp_ram_14_1_6))))
+          (net mdout1_13_17
+            (joined
+              (portRef D13 (instanceRef mux_18))
+              (portRef DOB8 (instanceRef pdp_ram_13_1_10))))
+          (net mdout1_12_17
+            (joined
+              (portRef D12 (instanceRef mux_18))
+              (portRef DOB8 (instanceRef pdp_ram_12_1_14))))
+          (net mdout1_11_17
+            (joined
+              (portRef D11 (instanceRef mux_18))
+              (portRef DOB8 (instanceRef pdp_ram_11_1_18))))
+          (net mdout1_10_17
+            (joined
+              (portRef D10 (instanceRef mux_18))
+              (portRef DOB8 (instanceRef pdp_ram_10_1_22))))
+          (net mdout1_9_17
+            (joined
+              (portRef D9 (instanceRef mux_18))
+              (portRef DOB8 (instanceRef pdp_ram_9_1_26))))
+          (net mdout1_8_17
+            (joined
+              (portRef D8 (instanceRef mux_18))
+              (portRef DOB8 (instanceRef pdp_ram_8_1_30))))
+          (net mdout1_7_17
+            (joined
+              (portRef D7 (instanceRef mux_18))
+              (portRef DOB8 (instanceRef pdp_ram_7_1_34))))
+          (net mdout1_6_17
+            (joined
+              (portRef D6 (instanceRef mux_18))
+              (portRef DOB8 (instanceRef pdp_ram_6_1_38))))
+          (net mdout1_5_17
+            (joined
+              (portRef D5 (instanceRef mux_18))
+              (portRef DOB8 (instanceRef pdp_ram_5_1_42))))
+          (net mdout1_4_17
+            (joined
+              (portRef D4 (instanceRef mux_18))
+              (portRef DOB8 (instanceRef pdp_ram_4_1_46))))
+          (net mdout1_3_17
+            (joined
+              (portRef D3 (instanceRef mux_18))
+              (portRef DOB8 (instanceRef pdp_ram_3_1_50))))
+          (net mdout1_2_17
+            (joined
+              (portRef D2 (instanceRef mux_18))
+              (portRef DOB8 (instanceRef pdp_ram_2_1_54))))
+          (net mdout1_1_17
+            (joined
+              (portRef D1 (instanceRef mux_18))
+              (portRef DOB8 (instanceRef pdp_ram_1_1_58))))
+          (net mdout1_0_17
+            (joined
+              (portRef D0 (instanceRef mux_18))
+              (portRef DOB8 (instanceRef pdp_ram_0_1_62))))
+          (net mdout1_15_18
+            (joined
+              (portRef D15 (instanceRef mux_17))
+              (portRef DOB0 (instanceRef pdp_ram_15_2_1))))
+          (net mdout1_14_18
+            (joined
+              (portRef D14 (instanceRef mux_17))
+              (portRef DOB0 (instanceRef pdp_ram_14_2_5))))
+          (net mdout1_13_18
+            (joined
+              (portRef D13 (instanceRef mux_17))
+              (portRef DOB0 (instanceRef pdp_ram_13_2_9))))
+          (net mdout1_12_18
+            (joined
+              (portRef D12 (instanceRef mux_17))
+              (portRef DOB0 (instanceRef pdp_ram_12_2_13))))
+          (net mdout1_11_18
+            (joined
+              (portRef D11 (instanceRef mux_17))
+              (portRef DOB0 (instanceRef pdp_ram_11_2_17))))
+          (net mdout1_10_18
+            (joined
+              (portRef D10 (instanceRef mux_17))
+              (portRef DOB0 (instanceRef pdp_ram_10_2_21))))
+          (net mdout1_9_18
+            (joined
+              (portRef D9 (instanceRef mux_17))
+              (portRef DOB0 (instanceRef pdp_ram_9_2_25))))
+          (net mdout1_8_18
+            (joined
+              (portRef D8 (instanceRef mux_17))
+              (portRef DOB0 (instanceRef pdp_ram_8_2_29))))
+          (net mdout1_7_18
+            (joined
+              (portRef D7 (instanceRef mux_17))
+              (portRef DOB0 (instanceRef pdp_ram_7_2_33))))
+          (net mdout1_6_18
+            (joined
+              (portRef D6 (instanceRef mux_17))
+              (portRef DOB0 (instanceRef pdp_ram_6_2_37))))
+          (net mdout1_5_18
+            (joined
+              (portRef D5 (instanceRef mux_17))
+              (portRef DOB0 (instanceRef pdp_ram_5_2_41))))
+          (net mdout1_4_18
+            (joined
+              (portRef D4 (instanceRef mux_17))
+              (portRef DOB0 (instanceRef pdp_ram_4_2_45))))
+          (net mdout1_3_18
+            (joined
+              (portRef D3 (instanceRef mux_17))
+              (portRef DOB0 (instanceRef pdp_ram_3_2_49))))
+          (net mdout1_2_18
+            (joined
+              (portRef D2 (instanceRef mux_17))
+              (portRef DOB0 (instanceRef pdp_ram_2_2_53))))
+          (net mdout1_1_18
+            (joined
+              (portRef D1 (instanceRef mux_17))
+              (portRef DOB0 (instanceRef pdp_ram_1_2_57))))
+          (net mdout1_0_18
+            (joined
+              (portRef D0 (instanceRef mux_17))
+              (portRef DOB0 (instanceRef pdp_ram_0_2_61))))
+          (net mdout1_15_19
+            (joined
+              (portRef D15 (instanceRef mux_16))
+              (portRef DOB1 (instanceRef pdp_ram_15_2_1))))
+          (net mdout1_14_19
+            (joined
+              (portRef D14 (instanceRef mux_16))
+              (portRef DOB1 (instanceRef pdp_ram_14_2_5))))
+          (net mdout1_13_19
+            (joined
+              (portRef D13 (instanceRef mux_16))
+              (portRef DOB1 (instanceRef pdp_ram_13_2_9))))
+          (net mdout1_12_19
+            (joined
+              (portRef D12 (instanceRef mux_16))
+              (portRef DOB1 (instanceRef pdp_ram_12_2_13))))
+          (net mdout1_11_19
+            (joined
+              (portRef D11 (instanceRef mux_16))
+              (portRef DOB1 (instanceRef pdp_ram_11_2_17))))
+          (net mdout1_10_19
+            (joined
+              (portRef D10 (instanceRef mux_16))
+              (portRef DOB1 (instanceRef pdp_ram_10_2_21))))
+          (net mdout1_9_19
+            (joined
+              (portRef D9 (instanceRef mux_16))
+              (portRef DOB1 (instanceRef pdp_ram_9_2_25))))
+          (net mdout1_8_19
+            (joined
+              (portRef D8 (instanceRef mux_16))
+              (portRef DOB1 (instanceRef pdp_ram_8_2_29))))
+          (net mdout1_7_19
+            (joined
+              (portRef D7 (instanceRef mux_16))
+              (portRef DOB1 (instanceRef pdp_ram_7_2_33))))
+          (net mdout1_6_19
+            (joined
+              (portRef D6 (instanceRef mux_16))
+              (portRef DOB1 (instanceRef pdp_ram_6_2_37))))
+          (net mdout1_5_19
+            (joined
+              (portRef D5 (instanceRef mux_16))
+              (portRef DOB1 (instanceRef pdp_ram_5_2_41))))
+          (net mdout1_4_19
+            (joined
+              (portRef D4 (instanceRef mux_16))
+              (portRef DOB1 (instanceRef pdp_ram_4_2_45))))
+          (net mdout1_3_19
+            (joined
+              (portRef D3 (instanceRef mux_16))
+              (portRef DOB1 (instanceRef pdp_ram_3_2_49))))
+          (net mdout1_2_19
+            (joined
+              (portRef D2 (instanceRef mux_16))
+              (portRef DOB1 (instanceRef pdp_ram_2_2_53))))
+          (net mdout1_1_19
+            (joined
+              (portRef D1 (instanceRef mux_16))
+              (portRef DOB1 (instanceRef pdp_ram_1_2_57))))
+          (net mdout1_0_19
+            (joined
+              (portRef D0 (instanceRef mux_16))
+              (portRef DOB1 (instanceRef pdp_ram_0_2_61))))
+          (net mdout1_15_20
+            (joined
+              (portRef D15 (instanceRef mux_15))
+              (portRef DOB2 (instanceRef pdp_ram_15_2_1))))
+          (net mdout1_14_20
+            (joined
+              (portRef D14 (instanceRef mux_15))
+              (portRef DOB2 (instanceRef pdp_ram_14_2_5))))
+          (net mdout1_13_20
+            (joined
+              (portRef D13 (instanceRef mux_15))
+              (portRef DOB2 (instanceRef pdp_ram_13_2_9))))
+          (net mdout1_12_20
+            (joined
+              (portRef D12 (instanceRef mux_15))
+              (portRef DOB2 (instanceRef pdp_ram_12_2_13))))
+          (net mdout1_11_20
+            (joined
+              (portRef D11 (instanceRef mux_15))
+              (portRef DOB2 (instanceRef pdp_ram_11_2_17))))
+          (net mdout1_10_20
+            (joined
+              (portRef D10 (instanceRef mux_15))
+              (portRef DOB2 (instanceRef pdp_ram_10_2_21))))
+          (net mdout1_9_20
+            (joined
+              (portRef D9 (instanceRef mux_15))
+              (portRef DOB2 (instanceRef pdp_ram_9_2_25))))
+          (net mdout1_8_20
+            (joined
+              (portRef D8 (instanceRef mux_15))
+              (portRef DOB2 (instanceRef pdp_ram_8_2_29))))
+          (net mdout1_7_20
+            (joined
+              (portRef D7 (instanceRef mux_15))
+              (portRef DOB2 (instanceRef pdp_ram_7_2_33))))
+          (net mdout1_6_20
+            (joined
+              (portRef D6 (instanceRef mux_15))
+              (portRef DOB2 (instanceRef pdp_ram_6_2_37))))
+          (net mdout1_5_20
+            (joined
+              (portRef D5 (instanceRef mux_15))
+              (portRef DOB2 (instanceRef pdp_ram_5_2_41))))
+          (net mdout1_4_20
+            (joined
+              (portRef D4 (instanceRef mux_15))
+              (portRef DOB2 (instanceRef pdp_ram_4_2_45))))
+          (net mdout1_3_20
+            (joined
+              (portRef D3 (instanceRef mux_15))
+              (portRef DOB2 (instanceRef pdp_ram_3_2_49))))
+          (net mdout1_2_20
+            (joined
+              (portRef D2 (instanceRef mux_15))
+              (portRef DOB2 (instanceRef pdp_ram_2_2_53))))
+          (net mdout1_1_20
+            (joined
+              (portRef D1 (instanceRef mux_15))
+              (portRef DOB2 (instanceRef pdp_ram_1_2_57))))
+          (net mdout1_0_20
+            (joined
+              (portRef D0 (instanceRef mux_15))
+              (portRef DOB2 (instanceRef pdp_ram_0_2_61))))
+          (net mdout1_15_21
+            (joined
+              (portRef D15 (instanceRef mux_14))
+              (portRef DOB3 (instanceRef pdp_ram_15_2_1))))
+          (net mdout1_14_21
+            (joined
+              (portRef D14 (instanceRef mux_14))
+              (portRef DOB3 (instanceRef pdp_ram_14_2_5))))
+          (net mdout1_13_21
+            (joined
+              (portRef D13 (instanceRef mux_14))
+              (portRef DOB3 (instanceRef pdp_ram_13_2_9))))
+          (net mdout1_12_21
+            (joined
+              (portRef D12 (instanceRef mux_14))
+              (portRef DOB3 (instanceRef pdp_ram_12_2_13))))
+          (net mdout1_11_21
+            (joined
+              (portRef D11 (instanceRef mux_14))
+              (portRef DOB3 (instanceRef pdp_ram_11_2_17))))
+          (net mdout1_10_21
+            (joined
+              (portRef D10 (instanceRef mux_14))
+              (portRef DOB3 (instanceRef pdp_ram_10_2_21))))
+          (net mdout1_9_21
+            (joined
+              (portRef D9 (instanceRef mux_14))
+              (portRef DOB3 (instanceRef pdp_ram_9_2_25))))
+          (net mdout1_8_21
+            (joined
+              (portRef D8 (instanceRef mux_14))
+              (portRef DOB3 (instanceRef pdp_ram_8_2_29))))
+          (net mdout1_7_21
+            (joined
+              (portRef D7 (instanceRef mux_14))
+              (portRef DOB3 (instanceRef pdp_ram_7_2_33))))
+          (net mdout1_6_21
+            (joined
+              (portRef D6 (instanceRef mux_14))
+              (portRef DOB3 (instanceRef pdp_ram_6_2_37))))
+          (net mdout1_5_21
+            (joined
+              (portRef D5 (instanceRef mux_14))
+              (portRef DOB3 (instanceRef pdp_ram_5_2_41))))
+          (net mdout1_4_21
+            (joined
+              (portRef D4 (instanceRef mux_14))
+              (portRef DOB3 (instanceRef pdp_ram_4_2_45))))
+          (net mdout1_3_21
+            (joined
+              (portRef D3 (instanceRef mux_14))
+              (portRef DOB3 (instanceRef pdp_ram_3_2_49))))
+          (net mdout1_2_21
+            (joined
+              (portRef D2 (instanceRef mux_14))
+              (portRef DOB3 (instanceRef pdp_ram_2_2_53))))
+          (net mdout1_1_21
+            (joined
+              (portRef D1 (instanceRef mux_14))
+              (portRef DOB3 (instanceRef pdp_ram_1_2_57))))
+          (net mdout1_0_21
+            (joined
+              (portRef D0 (instanceRef mux_14))
+              (portRef DOB3 (instanceRef pdp_ram_0_2_61))))
+          (net mdout1_15_22
+            (joined
+              (portRef D15 (instanceRef mux_13))
+              (portRef DOB4 (instanceRef pdp_ram_15_2_1))))
+          (net mdout1_14_22
+            (joined
+              (portRef D14 (instanceRef mux_13))
+              (portRef DOB4 (instanceRef pdp_ram_14_2_5))))
+          (net mdout1_13_22
+            (joined
+              (portRef D13 (instanceRef mux_13))
+              (portRef DOB4 (instanceRef pdp_ram_13_2_9))))
+          (net mdout1_12_22
+            (joined
+              (portRef D12 (instanceRef mux_13))
+              (portRef DOB4 (instanceRef pdp_ram_12_2_13))))
+          (net mdout1_11_22
+            (joined
+              (portRef D11 (instanceRef mux_13))
+              (portRef DOB4 (instanceRef pdp_ram_11_2_17))))
+          (net mdout1_10_22
+            (joined
+              (portRef D10 (instanceRef mux_13))
+              (portRef DOB4 (instanceRef pdp_ram_10_2_21))))
+          (net mdout1_9_22
+            (joined
+              (portRef D9 (instanceRef mux_13))
+              (portRef DOB4 (instanceRef pdp_ram_9_2_25))))
+          (net mdout1_8_22
+            (joined
+              (portRef D8 (instanceRef mux_13))
+              (portRef DOB4 (instanceRef pdp_ram_8_2_29))))
+          (net mdout1_7_22
+            (joined
+              (portRef D7 (instanceRef mux_13))
+              (portRef DOB4 (instanceRef pdp_ram_7_2_33))))
+          (net mdout1_6_22
+            (joined
+              (portRef D6 (instanceRef mux_13))
+              (portRef DOB4 (instanceRef pdp_ram_6_2_37))))
+          (net mdout1_5_22
+            (joined
+              (portRef D5 (instanceRef mux_13))
+              (portRef DOB4 (instanceRef pdp_ram_5_2_41))))
+          (net mdout1_4_22
+            (joined
+              (portRef D4 (instanceRef mux_13))
+              (portRef DOB4 (instanceRef pdp_ram_4_2_45))))
+          (net mdout1_3_22
+            (joined
+              (portRef D3 (instanceRef mux_13))
+              (portRef DOB4 (instanceRef pdp_ram_3_2_49))))
+          (net mdout1_2_22
+            (joined
+              (portRef D2 (instanceRef mux_13))
+              (portRef DOB4 (instanceRef pdp_ram_2_2_53))))
+          (net mdout1_1_22
+            (joined
+              (portRef D1 (instanceRef mux_13))
+              (portRef DOB4 (instanceRef pdp_ram_1_2_57))))
+          (net mdout1_0_22
+            (joined
+              (portRef D0 (instanceRef mux_13))
+              (portRef DOB4 (instanceRef pdp_ram_0_2_61))))
+          (net mdout1_15_23
+            (joined
+              (portRef D15 (instanceRef mux_12))
+              (portRef DOB5 (instanceRef pdp_ram_15_2_1))))
+          (net mdout1_14_23
+            (joined
+              (portRef D14 (instanceRef mux_12))
+              (portRef DOB5 (instanceRef pdp_ram_14_2_5))))
+          (net mdout1_13_23
+            (joined
+              (portRef D13 (instanceRef mux_12))
+              (portRef DOB5 (instanceRef pdp_ram_13_2_9))))
+          (net mdout1_12_23
+            (joined
+              (portRef D12 (instanceRef mux_12))
+              (portRef DOB5 (instanceRef pdp_ram_12_2_13))))
+          (net mdout1_11_23
+            (joined
+              (portRef D11 (instanceRef mux_12))
+              (portRef DOB5 (instanceRef pdp_ram_11_2_17))))
+          (net mdout1_10_23
+            (joined
+              (portRef D10 (instanceRef mux_12))
+              (portRef DOB5 (instanceRef pdp_ram_10_2_21))))
+          (net mdout1_9_23
+            (joined
+              (portRef D9 (instanceRef mux_12))
+              (portRef DOB5 (instanceRef pdp_ram_9_2_25))))
+          (net mdout1_8_23
+            (joined
+              (portRef D8 (instanceRef mux_12))
+              (portRef DOB5 (instanceRef pdp_ram_8_2_29))))
+          (net mdout1_7_23
+            (joined
+              (portRef D7 (instanceRef mux_12))
+              (portRef DOB5 (instanceRef pdp_ram_7_2_33))))
+          (net mdout1_6_23
+            (joined
+              (portRef D6 (instanceRef mux_12))
+              (portRef DOB5 (instanceRef pdp_ram_6_2_37))))
+          (net mdout1_5_23
+            (joined
+              (portRef D5 (instanceRef mux_12))
+              (portRef DOB5 (instanceRef pdp_ram_5_2_41))))
+          (net mdout1_4_23
+            (joined
+              (portRef D4 (instanceRef mux_12))
+              (portRef DOB5 (instanceRef pdp_ram_4_2_45))))
+          (net mdout1_3_23
+            (joined
+              (portRef D3 (instanceRef mux_12))
+              (portRef DOB5 (instanceRef pdp_ram_3_2_49))))
+          (net mdout1_2_23
+            (joined
+              (portRef D2 (instanceRef mux_12))
+              (portRef DOB5 (instanceRef pdp_ram_2_2_53))))
+          (net mdout1_1_23
+            (joined
+              (portRef D1 (instanceRef mux_12))
+              (portRef DOB5 (instanceRef pdp_ram_1_2_57))))
+          (net mdout1_0_23
+            (joined
+              (portRef D0 (instanceRef mux_12))
+              (portRef DOB5 (instanceRef pdp_ram_0_2_61))))
+          (net mdout1_15_24
+            (joined
+              (portRef D15 (instanceRef mux_11))
+              (portRef DOB6 (instanceRef pdp_ram_15_2_1))))
+          (net mdout1_14_24
+            (joined
+              (portRef D14 (instanceRef mux_11))
+              (portRef DOB6 (instanceRef pdp_ram_14_2_5))))
+          (net mdout1_13_24
+            (joined
+              (portRef D13 (instanceRef mux_11))
+              (portRef DOB6 (instanceRef pdp_ram_13_2_9))))
+          (net mdout1_12_24
+            (joined
+              (portRef D12 (instanceRef mux_11))
+              (portRef DOB6 (instanceRef pdp_ram_12_2_13))))
+          (net mdout1_11_24
+            (joined
+              (portRef D11 (instanceRef mux_11))
+              (portRef DOB6 (instanceRef pdp_ram_11_2_17))))
+          (net mdout1_10_24
+            (joined
+              (portRef D10 (instanceRef mux_11))
+              (portRef DOB6 (instanceRef pdp_ram_10_2_21))))
+          (net mdout1_9_24
+            (joined
+              (portRef D9 (instanceRef mux_11))
+              (portRef DOB6 (instanceRef pdp_ram_9_2_25))))
+          (net mdout1_8_24
+            (joined
+              (portRef D8 (instanceRef mux_11))
+              (portRef DOB6 (instanceRef pdp_ram_8_2_29))))
+          (net mdout1_7_24
+            (joined
+              (portRef D7 (instanceRef mux_11))
+              (portRef DOB6 (instanceRef pdp_ram_7_2_33))))
+          (net mdout1_6_24
+            (joined
+              (portRef D6 (instanceRef mux_11))
+              (portRef DOB6 (instanceRef pdp_ram_6_2_37))))
+          (net mdout1_5_24
+            (joined
+              (portRef D5 (instanceRef mux_11))
+              (portRef DOB6 (instanceRef pdp_ram_5_2_41))))
+          (net mdout1_4_24
+            (joined
+              (portRef D4 (instanceRef mux_11))
+              (portRef DOB6 (instanceRef pdp_ram_4_2_45))))
+          (net mdout1_3_24
+            (joined
+              (portRef D3 (instanceRef mux_11))
+              (portRef DOB6 (instanceRef pdp_ram_3_2_49))))
+          (net mdout1_2_24
+            (joined
+              (portRef D2 (instanceRef mux_11))
+              (portRef DOB6 (instanceRef pdp_ram_2_2_53))))
+          (net mdout1_1_24
+            (joined
+              (portRef D1 (instanceRef mux_11))
+              (portRef DOB6 (instanceRef pdp_ram_1_2_57))))
+          (net mdout1_0_24
+            (joined
+              (portRef D0 (instanceRef mux_11))
+              (portRef DOB6 (instanceRef pdp_ram_0_2_61))))
+          (net mdout1_15_25
+            (joined
+              (portRef D15 (instanceRef mux_10))
+              (portRef DOB7 (instanceRef pdp_ram_15_2_1))))
+          (net mdout1_14_25
+            (joined
+              (portRef D14 (instanceRef mux_10))
+              (portRef DOB7 (instanceRef pdp_ram_14_2_5))))
+          (net mdout1_13_25
+            (joined
+              (portRef D13 (instanceRef mux_10))
+              (portRef DOB7 (instanceRef pdp_ram_13_2_9))))
+          (net mdout1_12_25
+            (joined
+              (portRef D12 (instanceRef mux_10))
+              (portRef DOB7 (instanceRef pdp_ram_12_2_13))))
+          (net mdout1_11_25
+            (joined
+              (portRef D11 (instanceRef mux_10))
+              (portRef DOB7 (instanceRef pdp_ram_11_2_17))))
+          (net mdout1_10_25
+            (joined
+              (portRef D10 (instanceRef mux_10))
+              (portRef DOB7 (instanceRef pdp_ram_10_2_21))))
+          (net mdout1_9_25
+            (joined
+              (portRef D9 (instanceRef mux_10))
+              (portRef DOB7 (instanceRef pdp_ram_9_2_25))))
+          (net mdout1_8_25
+            (joined
+              (portRef D8 (instanceRef mux_10))
+              (portRef DOB7 (instanceRef pdp_ram_8_2_29))))
+          (net mdout1_7_25
+            (joined
+              (portRef D7 (instanceRef mux_10))
+              (portRef DOB7 (instanceRef pdp_ram_7_2_33))))
+          (net mdout1_6_25
+            (joined
+              (portRef D6 (instanceRef mux_10))
+              (portRef DOB7 (instanceRef pdp_ram_6_2_37))))
+          (net mdout1_5_25
+            (joined
+              (portRef D5 (instanceRef mux_10))
+              (portRef DOB7 (instanceRef pdp_ram_5_2_41))))
+          (net mdout1_4_25
+            (joined
+              (portRef D4 (instanceRef mux_10))
+              (portRef DOB7 (instanceRef pdp_ram_4_2_45))))
+          (net mdout1_3_25
+            (joined
+              (portRef D3 (instanceRef mux_10))
+              (portRef DOB7 (instanceRef pdp_ram_3_2_49))))
+          (net mdout1_2_25
+            (joined
+              (portRef D2 (instanceRef mux_10))
+              (portRef DOB7 (instanceRef pdp_ram_2_2_53))))
+          (net mdout1_1_25
+            (joined
+              (portRef D1 (instanceRef mux_10))
+              (portRef DOB7 (instanceRef pdp_ram_1_2_57))))
+          (net mdout1_0_25
+            (joined
+              (portRef D0 (instanceRef mux_10))
+              (portRef DOB7 (instanceRef pdp_ram_0_2_61))))
+          (net mdout1_15_26
+            (joined
+              (portRef D15 (instanceRef mux_9))
+              (portRef DOB8 (instanceRef pdp_ram_15_2_1))))
+          (net mdout1_14_26
+            (joined
+              (portRef D14 (instanceRef mux_9))
+              (portRef DOB8 (instanceRef pdp_ram_14_2_5))))
+          (net mdout1_13_26
+            (joined
+              (portRef D13 (instanceRef mux_9))
+              (portRef DOB8 (instanceRef pdp_ram_13_2_9))))
+          (net mdout1_12_26
+            (joined
+              (portRef D12 (instanceRef mux_9))
+              (portRef DOB8 (instanceRef pdp_ram_12_2_13))))
+          (net mdout1_11_26
+            (joined
+              (portRef D11 (instanceRef mux_9))
+              (portRef DOB8 (instanceRef pdp_ram_11_2_17))))
+          (net mdout1_10_26
+            (joined
+              (portRef D10 (instanceRef mux_9))
+              (portRef DOB8 (instanceRef pdp_ram_10_2_21))))
+          (net mdout1_9_26
+            (joined
+              (portRef D9 (instanceRef mux_9))
+              (portRef DOB8 (instanceRef pdp_ram_9_2_25))))
+          (net mdout1_8_26
+            (joined
+              (portRef D8 (instanceRef mux_9))
+              (portRef DOB8 (instanceRef pdp_ram_8_2_29))))
+          (net mdout1_7_26
+            (joined
+              (portRef D7 (instanceRef mux_9))
+              (portRef DOB8 (instanceRef pdp_ram_7_2_33))))
+          (net mdout1_6_26
+            (joined
+              (portRef D6 (instanceRef mux_9))
+              (portRef DOB8 (instanceRef pdp_ram_6_2_37))))
+          (net mdout1_5_26
+            (joined
+              (portRef D5 (instanceRef mux_9))
+              (portRef DOB8 (instanceRef pdp_ram_5_2_41))))
+          (net mdout1_4_26
+            (joined
+              (portRef D4 (instanceRef mux_9))
+              (portRef DOB8 (instanceRef pdp_ram_4_2_45))))
+          (net mdout1_3_26
+            (joined
+              (portRef D3 (instanceRef mux_9))
+              (portRef DOB8 (instanceRef pdp_ram_3_2_49))))
+          (net mdout1_2_26
+            (joined
+              (portRef D2 (instanceRef mux_9))
+              (portRef DOB8 (instanceRef pdp_ram_2_2_53))))
+          (net mdout1_1_26
+            (joined
+              (portRef D1 (instanceRef mux_9))
+              (portRef DOB8 (instanceRef pdp_ram_1_2_57))))
+          (net mdout1_0_26
+            (joined
+              (portRef D0 (instanceRef mux_9))
+              (portRef DOB8 (instanceRef pdp_ram_0_2_61))))
+          (net mdout1_15_27
+            (joined
+              (portRef D15 (instanceRef mux_8))
+              (portRef DOB0 (instanceRef pdp_ram_15_3_0))))
+          (net mdout1_14_27
+            (joined
+              (portRef D14 (instanceRef mux_8))
+              (portRef DOB0 (instanceRef pdp_ram_14_3_4))))
+          (net mdout1_13_27
+            (joined
+              (portRef D13 (instanceRef mux_8))
+              (portRef DOB0 (instanceRef pdp_ram_13_3_8))))
+          (net mdout1_12_27
+            (joined
+              (portRef D12 (instanceRef mux_8))
+              (portRef DOB0 (instanceRef pdp_ram_12_3_12))))
+          (net mdout1_11_27
+            (joined
+              (portRef D11 (instanceRef mux_8))
+              (portRef DOB0 (instanceRef pdp_ram_11_3_16))))
+          (net mdout1_10_27
+            (joined
+              (portRef D10 (instanceRef mux_8))
+              (portRef DOB0 (instanceRef pdp_ram_10_3_20))))
+          (net mdout1_9_27
+            (joined
+              (portRef D9 (instanceRef mux_8))
+              (portRef DOB0 (instanceRef pdp_ram_9_3_24))))
+          (net mdout1_8_27
+            (joined
+              (portRef D8 (instanceRef mux_8))
+              (portRef DOB0 (instanceRef pdp_ram_8_3_28))))
+          (net mdout1_7_27
+            (joined
+              (portRef D7 (instanceRef mux_8))
+              (portRef DOB0 (instanceRef pdp_ram_7_3_32))))
+          (net mdout1_6_27
+            (joined
+              (portRef D6 (instanceRef mux_8))
+              (portRef DOB0 (instanceRef pdp_ram_6_3_36))))
+          (net mdout1_5_27
+            (joined
+              (portRef D5 (instanceRef mux_8))
+              (portRef DOB0 (instanceRef pdp_ram_5_3_40))))
+          (net mdout1_4_27
+            (joined
+              (portRef D4 (instanceRef mux_8))
+              (portRef DOB0 (instanceRef pdp_ram_4_3_44))))
+          (net mdout1_3_27
+            (joined
+              (portRef D3 (instanceRef mux_8))
+              (portRef DOB0 (instanceRef pdp_ram_3_3_48))))
+          (net mdout1_2_27
+            (joined
+              (portRef D2 (instanceRef mux_8))
+              (portRef DOB0 (instanceRef pdp_ram_2_3_52))))
+          (net mdout1_1_27
+            (joined
+              (portRef D1 (instanceRef mux_8))
+              (portRef DOB0 (instanceRef pdp_ram_1_3_56))))
+          (net mdout1_0_27
+            (joined
+              (portRef D0 (instanceRef mux_8))
+              (portRef DOB0 (instanceRef pdp_ram_0_3_60))))
+          (net mdout1_15_28
+            (joined
+              (portRef D15 (instanceRef mux_7))
+              (portRef DOB1 (instanceRef pdp_ram_15_3_0))))
+          (net mdout1_14_28
+            (joined
+              (portRef D14 (instanceRef mux_7))
+              (portRef DOB1 (instanceRef pdp_ram_14_3_4))))
+          (net mdout1_13_28
+            (joined
+              (portRef D13 (instanceRef mux_7))
+              (portRef DOB1 (instanceRef pdp_ram_13_3_8))))
+          (net mdout1_12_28
+            (joined
+              (portRef D12 (instanceRef mux_7))
+              (portRef DOB1 (instanceRef pdp_ram_12_3_12))))
+          (net mdout1_11_28
+            (joined
+              (portRef D11 (instanceRef mux_7))
+              (portRef DOB1 (instanceRef pdp_ram_11_3_16))))
+          (net mdout1_10_28
+            (joined
+              (portRef D10 (instanceRef mux_7))
+              (portRef DOB1 (instanceRef pdp_ram_10_3_20))))
+          (net mdout1_9_28
+            (joined
+              (portRef D9 (instanceRef mux_7))
+              (portRef DOB1 (instanceRef pdp_ram_9_3_24))))
+          (net mdout1_8_28
+            (joined
+              (portRef D8 (instanceRef mux_7))
+              (portRef DOB1 (instanceRef pdp_ram_8_3_28))))
+          (net mdout1_7_28
+            (joined
+              (portRef D7 (instanceRef mux_7))
+              (portRef DOB1 (instanceRef pdp_ram_7_3_32))))
+          (net mdout1_6_28
+            (joined
+              (portRef D6 (instanceRef mux_7))
+              (portRef DOB1 (instanceRef pdp_ram_6_3_36))))
+          (net mdout1_5_28
+            (joined
+              (portRef D5 (instanceRef mux_7))
+              (portRef DOB1 (instanceRef pdp_ram_5_3_40))))
+          (net mdout1_4_28
+            (joined
+              (portRef D4 (instanceRef mux_7))
+              (portRef DOB1 (instanceRef pdp_ram_4_3_44))))
+          (net mdout1_3_28
+            (joined
+              (portRef D3 (instanceRef mux_7))
+              (portRef DOB1 (instanceRef pdp_ram_3_3_48))))
+          (net mdout1_2_28
+            (joined
+              (portRef D2 (instanceRef mux_7))
+              (portRef DOB1 (instanceRef pdp_ram_2_3_52))))
+          (net mdout1_1_28
+            (joined
+              (portRef D1 (instanceRef mux_7))
+              (portRef DOB1 (instanceRef pdp_ram_1_3_56))))
+          (net mdout1_0_28
+            (joined
+              (portRef D0 (instanceRef mux_7))
+              (portRef DOB1 (instanceRef pdp_ram_0_3_60))))
+          (net mdout1_15_29
+            (joined
+              (portRef D15 (instanceRef mux_6))
+              (portRef DOB2 (instanceRef pdp_ram_15_3_0))))
+          (net mdout1_14_29
+            (joined
+              (portRef D14 (instanceRef mux_6))
+              (portRef DOB2 (instanceRef pdp_ram_14_3_4))))
+          (net mdout1_13_29
+            (joined
+              (portRef D13 (instanceRef mux_6))
+              (portRef DOB2 (instanceRef pdp_ram_13_3_8))))
+          (net mdout1_12_29
+            (joined
+              (portRef D12 (instanceRef mux_6))
+              (portRef DOB2 (instanceRef pdp_ram_12_3_12))))
+          (net mdout1_11_29
+            (joined
+              (portRef D11 (instanceRef mux_6))
+              (portRef DOB2 (instanceRef pdp_ram_11_3_16))))
+          (net mdout1_10_29
+            (joined
+              (portRef D10 (instanceRef mux_6))
+              (portRef DOB2 (instanceRef pdp_ram_10_3_20))))
+          (net mdout1_9_29
+            (joined
+              (portRef D9 (instanceRef mux_6))
+              (portRef DOB2 (instanceRef pdp_ram_9_3_24))))
+          (net mdout1_8_29
+            (joined
+              (portRef D8 (instanceRef mux_6))
+              (portRef DOB2 (instanceRef pdp_ram_8_3_28))))
+          (net mdout1_7_29
+            (joined
+              (portRef D7 (instanceRef mux_6))
+              (portRef DOB2 (instanceRef pdp_ram_7_3_32))))
+          (net mdout1_6_29
+            (joined
+              (portRef D6 (instanceRef mux_6))
+              (portRef DOB2 (instanceRef pdp_ram_6_3_36))))
+          (net mdout1_5_29
+            (joined
+              (portRef D5 (instanceRef mux_6))
+              (portRef DOB2 (instanceRef pdp_ram_5_3_40))))
+          (net mdout1_4_29
+            (joined
+              (portRef D4 (instanceRef mux_6))
+              (portRef DOB2 (instanceRef pdp_ram_4_3_44))))
+          (net mdout1_3_29
+            (joined
+              (portRef D3 (instanceRef mux_6))
+              (portRef DOB2 (instanceRef pdp_ram_3_3_48))))
+          (net mdout1_2_29
+            (joined
+              (portRef D2 (instanceRef mux_6))
+              (portRef DOB2 (instanceRef pdp_ram_2_3_52))))
+          (net mdout1_1_29
+            (joined
+              (portRef D1 (instanceRef mux_6))
+              (portRef DOB2 (instanceRef pdp_ram_1_3_56))))
+          (net mdout1_0_29
+            (joined
+              (portRef D0 (instanceRef mux_6))
+              (portRef DOB2 (instanceRef pdp_ram_0_3_60))))
+          (net mdout1_15_30
+            (joined
+              (portRef D15 (instanceRef mux_5))
+              (portRef DOB3 (instanceRef pdp_ram_15_3_0))))
+          (net mdout1_14_30
+            (joined
+              (portRef D14 (instanceRef mux_5))
+              (portRef DOB3 (instanceRef pdp_ram_14_3_4))))
+          (net mdout1_13_30
+            (joined
+              (portRef D13 (instanceRef mux_5))
+              (portRef DOB3 (instanceRef pdp_ram_13_3_8))))
+          (net mdout1_12_30
+            (joined
+              (portRef D12 (instanceRef mux_5))
+              (portRef DOB3 (instanceRef pdp_ram_12_3_12))))
+          (net mdout1_11_30
+            (joined
+              (portRef D11 (instanceRef mux_5))
+              (portRef DOB3 (instanceRef pdp_ram_11_3_16))))
+          (net mdout1_10_30
+            (joined
+              (portRef D10 (instanceRef mux_5))
+              (portRef DOB3 (instanceRef pdp_ram_10_3_20))))
+          (net mdout1_9_30
+            (joined
+              (portRef D9 (instanceRef mux_5))
+              (portRef DOB3 (instanceRef pdp_ram_9_3_24))))
+          (net mdout1_8_30
+            (joined
+              (portRef D8 (instanceRef mux_5))
+              (portRef DOB3 (instanceRef pdp_ram_8_3_28))))
+          (net mdout1_7_30
+            (joined
+              (portRef D7 (instanceRef mux_5))
+              (portRef DOB3 (instanceRef pdp_ram_7_3_32))))
+          (net mdout1_6_30
+            (joined
+              (portRef D6 (instanceRef mux_5))
+              (portRef DOB3 (instanceRef pdp_ram_6_3_36))))
+          (net mdout1_5_30
+            (joined
+              (portRef D5 (instanceRef mux_5))
+              (portRef DOB3 (instanceRef pdp_ram_5_3_40))))
+          (net mdout1_4_30
+            (joined
+              (portRef D4 (instanceRef mux_5))
+              (portRef DOB3 (instanceRef pdp_ram_4_3_44))))
+          (net mdout1_3_30
+            (joined
+              (portRef D3 (instanceRef mux_5))
+              (portRef DOB3 (instanceRef pdp_ram_3_3_48))))
+          (net mdout1_2_30
+            (joined
+              (portRef D2 (instanceRef mux_5))
+              (portRef DOB3 (instanceRef pdp_ram_2_3_52))))
+          (net mdout1_1_30
+            (joined
+              (portRef D1 (instanceRef mux_5))
+              (portRef DOB3 (instanceRef pdp_ram_1_3_56))))
+          (net mdout1_0_30
+            (joined
+              (portRef D0 (instanceRef mux_5))
+              (portRef DOB3 (instanceRef pdp_ram_0_3_60))))
+          (net mdout1_15_31
+            (joined
+              (portRef D15 (instanceRef mux_4))
+              (portRef DOB4 (instanceRef pdp_ram_15_3_0))))
+          (net mdout1_14_31
+            (joined
+              (portRef D14 (instanceRef mux_4))
+              (portRef DOB4 (instanceRef pdp_ram_14_3_4))))
+          (net mdout1_13_31
+            (joined
+              (portRef D13 (instanceRef mux_4))
+              (portRef DOB4 (instanceRef pdp_ram_13_3_8))))
+          (net mdout1_12_31
+            (joined
+              (portRef D12 (instanceRef mux_4))
+              (portRef DOB4 (instanceRef pdp_ram_12_3_12))))
+          (net mdout1_11_31
+            (joined
+              (portRef D11 (instanceRef mux_4))
+              (portRef DOB4 (instanceRef pdp_ram_11_3_16))))
+          (net mdout1_10_31
+            (joined
+              (portRef D10 (instanceRef mux_4))
+              (portRef DOB4 (instanceRef pdp_ram_10_3_20))))
+          (net mdout1_9_31
+            (joined
+              (portRef D9 (instanceRef mux_4))
+              (portRef DOB4 (instanceRef pdp_ram_9_3_24))))
+          (net mdout1_8_31
+            (joined
+              (portRef D8 (instanceRef mux_4))
+              (portRef DOB4 (instanceRef pdp_ram_8_3_28))))
+          (net mdout1_7_31
+            (joined
+              (portRef D7 (instanceRef mux_4))
+              (portRef DOB4 (instanceRef pdp_ram_7_3_32))))
+          (net mdout1_6_31
+            (joined
+              (portRef D6 (instanceRef mux_4))
+              (portRef DOB4 (instanceRef pdp_ram_6_3_36))))
+          (net mdout1_5_31
+            (joined
+              (portRef D5 (instanceRef mux_4))
+              (portRef DOB4 (instanceRef pdp_ram_5_3_40))))
+          (net mdout1_4_31
+            (joined
+              (portRef D4 (instanceRef mux_4))
+              (portRef DOB4 (instanceRef pdp_ram_4_3_44))))
+          (net mdout1_3_31
+            (joined
+              (portRef D3 (instanceRef mux_4))
+              (portRef DOB4 (instanceRef pdp_ram_3_3_48))))
+          (net mdout1_2_31
+            (joined
+              (portRef D2 (instanceRef mux_4))
+              (portRef DOB4 (instanceRef pdp_ram_2_3_52))))
+          (net mdout1_1_31
+            (joined
+              (portRef D1 (instanceRef mux_4))
+              (portRef DOB4 (instanceRef pdp_ram_1_3_56))))
+          (net mdout1_0_31
+            (joined
+              (portRef D0 (instanceRef mux_4))
+              (portRef DOB4 (instanceRef pdp_ram_0_3_60))))
+          (net mdout1_15_32
+            (joined
+              (portRef D15 (instanceRef mux_3))
+              (portRef DOB5 (instanceRef pdp_ram_15_3_0))))
+          (net mdout1_14_32
+            (joined
+              (portRef D14 (instanceRef mux_3))
+              (portRef DOB5 (instanceRef pdp_ram_14_3_4))))
+          (net mdout1_13_32
+            (joined
+              (portRef D13 (instanceRef mux_3))
+              (portRef DOB5 (instanceRef pdp_ram_13_3_8))))
+          (net mdout1_12_32
+            (joined
+              (portRef D12 (instanceRef mux_3))
+              (portRef DOB5 (instanceRef pdp_ram_12_3_12))))
+          (net mdout1_11_32
+            (joined
+              (portRef D11 (instanceRef mux_3))
+              (portRef DOB5 (instanceRef pdp_ram_11_3_16))))
+          (net mdout1_10_32
+            (joined
+              (portRef D10 (instanceRef mux_3))
+              (portRef DOB5 (instanceRef pdp_ram_10_3_20))))
+          (net mdout1_9_32
+            (joined
+              (portRef D9 (instanceRef mux_3))
+              (portRef DOB5 (instanceRef pdp_ram_9_3_24))))
+          (net mdout1_8_32
+            (joined
+              (portRef D8 (instanceRef mux_3))
+              (portRef DOB5 (instanceRef pdp_ram_8_3_28))))
+          (net mdout1_7_32
+            (joined
+              (portRef D7 (instanceRef mux_3))
+              (portRef DOB5 (instanceRef pdp_ram_7_3_32))))
+          (net mdout1_6_32
+            (joined
+              (portRef D6 (instanceRef mux_3))
+              (portRef DOB5 (instanceRef pdp_ram_6_3_36))))
+          (net mdout1_5_32
+            (joined
+              (portRef D5 (instanceRef mux_3))
+              (portRef DOB5 (instanceRef pdp_ram_5_3_40))))
+          (net mdout1_4_32
+            (joined
+              (portRef D4 (instanceRef mux_3))
+              (portRef DOB5 (instanceRef pdp_ram_4_3_44))))
+          (net mdout1_3_32
+            (joined
+              (portRef D3 (instanceRef mux_3))
+              (portRef DOB5 (instanceRef pdp_ram_3_3_48))))
+          (net mdout1_2_32
+            (joined
+              (portRef D2 (instanceRef mux_3))
+              (portRef DOB5 (instanceRef pdp_ram_2_3_52))))
+          (net mdout1_1_32
+            (joined
+              (portRef D1 (instanceRef mux_3))
+              (portRef DOB5 (instanceRef pdp_ram_1_3_56))))
+          (net mdout1_0_32
+            (joined
+              (portRef D0 (instanceRef mux_3))
+              (portRef DOB5 (instanceRef pdp_ram_0_3_60))))
+          (net mdout1_15_33
+            (joined
+              (portRef D15 (instanceRef mux_2))
+              (portRef DOB6 (instanceRef pdp_ram_15_3_0))))
+          (net mdout1_14_33
+            (joined
+              (portRef D14 (instanceRef mux_2))
+              (portRef DOB6 (instanceRef pdp_ram_14_3_4))))
+          (net mdout1_13_33
+            (joined
+              (portRef D13 (instanceRef mux_2))
+              (portRef DOB6 (instanceRef pdp_ram_13_3_8))))
+          (net mdout1_12_33
+            (joined
+              (portRef D12 (instanceRef mux_2))
+              (portRef DOB6 (instanceRef pdp_ram_12_3_12))))
+          (net mdout1_11_33
+            (joined
+              (portRef D11 (instanceRef mux_2))
+              (portRef DOB6 (instanceRef pdp_ram_11_3_16))))
+          (net mdout1_10_33
+            (joined
+              (portRef D10 (instanceRef mux_2))
+              (portRef DOB6 (instanceRef pdp_ram_10_3_20))))
+          (net mdout1_9_33
+            (joined
+              (portRef D9 (instanceRef mux_2))
+              (portRef DOB6 (instanceRef pdp_ram_9_3_24))))
+          (net mdout1_8_33
+            (joined
+              (portRef D8 (instanceRef mux_2))
+              (portRef DOB6 (instanceRef pdp_ram_8_3_28))))
+          (net mdout1_7_33
+            (joined
+              (portRef D7 (instanceRef mux_2))
+              (portRef DOB6 (instanceRef pdp_ram_7_3_32))))
+          (net mdout1_6_33
+            (joined
+              (portRef D6 (instanceRef mux_2))
+              (portRef DOB6 (instanceRef pdp_ram_6_3_36))))
+          (net mdout1_5_33
+            (joined
+              (portRef D5 (instanceRef mux_2))
+              (portRef DOB6 (instanceRef pdp_ram_5_3_40))))
+          (net mdout1_4_33
+            (joined
+              (portRef D4 (instanceRef mux_2))
+              (portRef DOB6 (instanceRef pdp_ram_4_3_44))))
+          (net mdout1_3_33
+            (joined
+              (portRef D3 (instanceRef mux_2))
+              (portRef DOB6 (instanceRef pdp_ram_3_3_48))))
+          (net mdout1_2_33
+            (joined
+              (portRef D2 (instanceRef mux_2))
+              (portRef DOB6 (instanceRef pdp_ram_2_3_52))))
+          (net mdout1_1_33
+            (joined
+              (portRef D1 (instanceRef mux_2))
+              (portRef DOB6 (instanceRef pdp_ram_1_3_56))))
+          (net mdout1_0_33
+            (joined
+              (portRef D0 (instanceRef mux_2))
+              (portRef DOB6 (instanceRef pdp_ram_0_3_60))))
+          (net mdout1_15_34
+            (joined
+              (portRef D15 (instanceRef mux_1))
+              (portRef DOB7 (instanceRef pdp_ram_15_3_0))))
+          (net mdout1_14_34
+            (joined
+              (portRef D14 (instanceRef mux_1))
+              (portRef DOB7 (instanceRef pdp_ram_14_3_4))))
+          (net mdout1_13_34
+            (joined
+              (portRef D13 (instanceRef mux_1))
+              (portRef DOB7 (instanceRef pdp_ram_13_3_8))))
+          (net mdout1_12_34
+            (joined
+              (portRef D12 (instanceRef mux_1))
+              (portRef DOB7 (instanceRef pdp_ram_12_3_12))))
+          (net mdout1_11_34
+            (joined
+              (portRef D11 (instanceRef mux_1))
+              (portRef DOB7 (instanceRef pdp_ram_11_3_16))))
+          (net mdout1_10_34
+            (joined
+              (portRef D10 (instanceRef mux_1))
+              (portRef DOB7 (instanceRef pdp_ram_10_3_20))))
+          (net mdout1_9_34
+            (joined
+              (portRef D9 (instanceRef mux_1))
+              (portRef DOB7 (instanceRef pdp_ram_9_3_24))))
+          (net mdout1_8_34
+            (joined
+              (portRef D8 (instanceRef mux_1))
+              (portRef DOB7 (instanceRef pdp_ram_8_3_28))))
+          (net mdout1_7_34
+            (joined
+              (portRef D7 (instanceRef mux_1))
+              (portRef DOB7 (instanceRef pdp_ram_7_3_32))))
+          (net mdout1_6_34
+            (joined
+              (portRef D6 (instanceRef mux_1))
+              (portRef DOB7 (instanceRef pdp_ram_6_3_36))))
+          (net mdout1_5_34
+            (joined
+              (portRef D5 (instanceRef mux_1))
+              (portRef DOB7 (instanceRef pdp_ram_5_3_40))))
+          (net mdout1_4_34
+            (joined
+              (portRef D4 (instanceRef mux_1))
+              (portRef DOB7 (instanceRef pdp_ram_4_3_44))))
+          (net mdout1_3_34
+            (joined
+              (portRef D3 (instanceRef mux_1))
+              (portRef DOB7 (instanceRef pdp_ram_3_3_48))))
+          (net mdout1_2_34
+            (joined
+              (portRef D2 (instanceRef mux_1))
+              (portRef DOB7 (instanceRef pdp_ram_2_3_52))))
+          (net mdout1_1_34
+            (joined
+              (portRef D1 (instanceRef mux_1))
+              (portRef DOB7 (instanceRef pdp_ram_1_3_56))))
+          (net mdout1_0_34
+            (joined
+              (portRef D0 (instanceRef mux_1))
+              (portRef DOB7 (instanceRef pdp_ram_0_3_60))))
+          (net rptr_14_ff2
+            (joined
+              (portRef SD4 (instanceRef mux_0))
+              (portRef Q (instanceRef FF_17))
+              (portRef SD4 (instanceRef mux_35))
+              (portRef SD4 (instanceRef mux_34))
+              (portRef SD4 (instanceRef mux_33))
+              (portRef SD4 (instanceRef mux_32))
+              (portRef SD4 (instanceRef mux_31))
+              (portRef SD4 (instanceRef mux_30))
+              (portRef SD4 (instanceRef mux_29))
+              (portRef SD4 (instanceRef mux_28))
+              (portRef SD4 (instanceRef mux_27))
+              (portRef SD4 (instanceRef mux_26))
+              (portRef SD4 (instanceRef mux_25))
+              (portRef SD4 (instanceRef mux_24))
+              (portRef SD4 (instanceRef mux_23))
+              (portRef SD4 (instanceRef mux_22))
+              (portRef SD4 (instanceRef mux_21))
+              (portRef SD4 (instanceRef mux_20))
+              (portRef SD4 (instanceRef mux_19))
+              (portRef SD4 (instanceRef mux_18))
+              (portRef SD4 (instanceRef mux_17))
+              (portRef SD4 (instanceRef mux_16))
+              (portRef SD4 (instanceRef mux_15))
+              (portRef SD4 (instanceRef mux_14))
+              (portRef SD4 (instanceRef mux_13))
+              (portRef SD4 (instanceRef mux_12))
+              (portRef SD4 (instanceRef mux_11))
+              (portRef SD4 (instanceRef mux_10))
+              (portRef SD4 (instanceRef mux_9))
+              (portRef SD4 (instanceRef mux_8))
+              (portRef SD4 (instanceRef mux_7))
+              (portRef SD4 (instanceRef mux_6))
+              (portRef SD4 (instanceRef mux_5))
+              (portRef SD4 (instanceRef mux_4))
+              (portRef SD4 (instanceRef mux_3))
+              (portRef SD4 (instanceRef mux_2))
+              (portRef SD4 (instanceRef mux_1))))
+          (net rptr_13_ff2
+            (joined
+              (portRef SD3 (instanceRef mux_0))
+              (portRef Q (instanceRef FF_18))
+              (portRef SD3 (instanceRef mux_35))
+              (portRef SD3 (instanceRef mux_34))
+              (portRef SD3 (instanceRef mux_33))
+              (portRef SD3 (instanceRef mux_32))
+              (portRef SD3 (instanceRef mux_31))
+              (portRef SD3 (instanceRef mux_30))
+              (portRef SD3 (instanceRef mux_29))
+              (portRef SD3 (instanceRef mux_28))
+              (portRef SD3 (instanceRef mux_27))
+              (portRef SD3 (instanceRef mux_26))
+              (portRef SD3 (instanceRef mux_25))
+              (portRef SD3 (instanceRef mux_24))
+              (portRef SD3 (instanceRef mux_23))
+              (portRef SD3 (instanceRef mux_22))
+              (portRef SD3 (instanceRef mux_21))
+              (portRef SD3 (instanceRef mux_20))
+              (portRef SD3 (instanceRef mux_19))
+              (portRef SD3 (instanceRef mux_18))
+              (portRef SD3 (instanceRef mux_17))
+              (portRef SD3 (instanceRef mux_16))
+              (portRef SD3 (instanceRef mux_15))
+              (portRef SD3 (instanceRef mux_14))
+              (portRef SD3 (instanceRef mux_13))
+              (portRef SD3 (instanceRef mux_12))
+              (portRef SD3 (instanceRef mux_11))
+              (portRef SD3 (instanceRef mux_10))
+              (portRef SD3 (instanceRef mux_9))
+              (portRef SD3 (instanceRef mux_8))
+              (portRef SD3 (instanceRef mux_7))
+              (portRef SD3 (instanceRef mux_6))
+              (portRef SD3 (instanceRef mux_5))
+              (portRef SD3 (instanceRef mux_4))
+              (portRef SD3 (instanceRef mux_3))
+              (portRef SD3 (instanceRef mux_2))
+              (portRef SD3 (instanceRef mux_1))))
+          (net rptr_12_ff2
+            (joined
+              (portRef SD2 (instanceRef mux_0))
+              (portRef Q (instanceRef FF_19))
+              (portRef SD2 (instanceRef mux_35))
+              (portRef SD2 (instanceRef mux_34))
+              (portRef SD2 (instanceRef mux_33))
+              (portRef SD2 (instanceRef mux_32))
+              (portRef SD2 (instanceRef mux_31))
+              (portRef SD2 (instanceRef mux_30))
+              (portRef SD2 (instanceRef mux_29))
+              (portRef SD2 (instanceRef mux_28))
+              (portRef SD2 (instanceRef mux_27))
+              (portRef SD2 (instanceRef mux_26))
+              (portRef SD2 (instanceRef mux_25))
+              (portRef SD2 (instanceRef mux_24))
+              (portRef SD2 (instanceRef mux_23))
+              (portRef SD2 (instanceRef mux_22))
+              (portRef SD2 (instanceRef mux_21))
+              (portRef SD2 (instanceRef mux_20))
+              (portRef SD2 (instanceRef mux_19))
+              (portRef SD2 (instanceRef mux_18))
+              (portRef SD2 (instanceRef mux_17))
+              (portRef SD2 (instanceRef mux_16))
+              (portRef SD2 (instanceRef mux_15))
+              (portRef SD2 (instanceRef mux_14))
+              (portRef SD2 (instanceRef mux_13))
+              (portRef SD2 (instanceRef mux_12))
+              (portRef SD2 (instanceRef mux_11))
+              (portRef SD2 (instanceRef mux_10))
+              (portRef SD2 (instanceRef mux_9))
+              (portRef SD2 (instanceRef mux_8))
+              (portRef SD2 (instanceRef mux_7))
+              (portRef SD2 (instanceRef mux_6))
+              (portRef SD2 (instanceRef mux_5))
+              (portRef SD2 (instanceRef mux_4))
+              (portRef SD2 (instanceRef mux_3))
+              (portRef SD2 (instanceRef mux_2))
+              (portRef SD2 (instanceRef mux_1))))
+          (net rptr_11_ff2
+            (joined
+              (portRef SD1 (instanceRef mux_0))
+              (portRef Q (instanceRef FF_20))
+              (portRef SD1 (instanceRef mux_35))
+              (portRef SD1 (instanceRef mux_34))
+              (portRef SD1 (instanceRef mux_33))
+              (portRef SD1 (instanceRef mux_32))
+              (portRef SD1 (instanceRef mux_31))
+              (portRef SD1 (instanceRef mux_30))
+              (portRef SD1 (instanceRef mux_29))
+              (portRef SD1 (instanceRef mux_28))
+              (portRef SD1 (instanceRef mux_27))
+              (portRef SD1 (instanceRef mux_26))
+              (portRef SD1 (instanceRef mux_25))
+              (portRef SD1 (instanceRef mux_24))
+              (portRef SD1 (instanceRef mux_23))
+              (portRef SD1 (instanceRef mux_22))
+              (portRef SD1 (instanceRef mux_21))
+              (portRef SD1 (instanceRef mux_20))
+              (portRef SD1 (instanceRef mux_19))
+              (portRef SD1 (instanceRef mux_18))
+              (portRef SD1 (instanceRef mux_17))
+              (portRef SD1 (instanceRef mux_16))
+              (portRef SD1 (instanceRef mux_15))
+              (portRef SD1 (instanceRef mux_14))
+              (portRef SD1 (instanceRef mux_13))
+              (portRef SD1 (instanceRef mux_12))
+              (portRef SD1 (instanceRef mux_11))
+              (portRef SD1 (instanceRef mux_10))
+              (portRef SD1 (instanceRef mux_9))
+              (portRef SD1 (instanceRef mux_8))
+              (portRef SD1 (instanceRef mux_7))
+              (portRef SD1 (instanceRef mux_6))
+              (portRef SD1 (instanceRef mux_5))
+              (portRef SD1 (instanceRef mux_4))
+              (portRef SD1 (instanceRef mux_3))
+              (portRef SD1 (instanceRef mux_2))
+              (portRef SD1 (instanceRef mux_1))))
+          (net mdout1_15_35
+            (joined
+              (portRef D15 (instanceRef mux_0))
+              (portRef DOB8 (instanceRef pdp_ram_15_3_0))))
+          (net mdout1_14_35
+            (joined
+              (portRef D14 (instanceRef mux_0))
+              (portRef DOB8 (instanceRef pdp_ram_14_3_4))))
+          (net mdout1_13_35
+            (joined
+              (portRef D13 (instanceRef mux_0))
+              (portRef DOB8 (instanceRef pdp_ram_13_3_8))))
+          (net mdout1_12_35
+            (joined
+              (portRef D12 (instanceRef mux_0))
+              (portRef DOB8 (instanceRef pdp_ram_12_3_12))))
+          (net mdout1_11_35
+            (joined
+              (portRef D11 (instanceRef mux_0))
+              (portRef DOB8 (instanceRef pdp_ram_11_3_16))))
+          (net mdout1_10_35
+            (joined
+              (portRef D10 (instanceRef mux_0))
+              (portRef DOB8 (instanceRef pdp_ram_10_3_20))))
+          (net mdout1_9_35
+            (joined
+              (portRef D9 (instanceRef mux_0))
+              (portRef DOB8 (instanceRef pdp_ram_9_3_24))))
+          (net mdout1_8_35
+            (joined
+              (portRef D8 (instanceRef mux_0))
+              (portRef DOB8 (instanceRef pdp_ram_8_3_28))))
+          (net mdout1_7_35
+            (joined
+              (portRef D7 (instanceRef mux_0))
+              (portRef DOB8 (instanceRef pdp_ram_7_3_32))))
+          (net mdout1_6_35
+            (joined
+              (portRef D6 (instanceRef mux_0))
+              (portRef DOB8 (instanceRef pdp_ram_6_3_36))))
+          (net mdout1_5_35
+            (joined
+              (portRef D5 (instanceRef mux_0))
+              (portRef DOB8 (instanceRef pdp_ram_5_3_40))))
+          (net mdout1_4_35
+            (joined
+              (portRef D4 (instanceRef mux_0))
+              (portRef DOB8 (instanceRef pdp_ram_4_3_44))))
+          (net mdout1_3_35
+            (joined
+              (portRef D3 (instanceRef mux_0))
+              (portRef DOB8 (instanceRef pdp_ram_3_3_48))))
+          (net mdout1_2_35
+            (joined
+              (portRef D2 (instanceRef mux_0))
+              (portRef DOB8 (instanceRef pdp_ram_2_3_52))))
+          (net mdout1_1_35
+            (joined
+              (portRef D1 (instanceRef mux_0))
+              (portRef DOB8 (instanceRef pdp_ram_1_3_56))))
+          (net mdout1_0_35
+            (joined
+              (portRef D0 (instanceRef mux_0))
+              (portRef DOB8 (instanceRef pdp_ram_0_3_60))))
+          (net wcnt_sub_0
+            (joined
+              (portRef S1 (instanceRef wcnt_0))
+              (portRef D (instanceRef FF_16))))
+          (net rptr_0
+            (joined
+              (portRef B1 (instanceRef wcnt_0))
+              (portRef ADB3 (instanceRef pdp_ram_0_0_63))
+              (portRef ADB3 (instanceRef pdp_ram_0_1_62))
+              (portRef ADB3 (instanceRef pdp_ram_0_2_61))
+              (portRef ADB3 (instanceRef pdp_ram_0_3_60))
+              (portRef ADB3 (instanceRef pdp_ram_1_0_59))
+              (portRef ADB3 (instanceRef pdp_ram_1_1_58))
+              (portRef ADB3 (instanceRef pdp_ram_1_2_57))
+              (portRef ADB3 (instanceRef pdp_ram_1_3_56))
+              (portRef ADB3 (instanceRef pdp_ram_2_0_55))
+              (portRef ADB3 (instanceRef pdp_ram_2_1_54))
+              (portRef ADB3 (instanceRef pdp_ram_2_2_53))
+              (portRef ADB3 (instanceRef pdp_ram_2_3_52))
+              (portRef ADB3 (instanceRef pdp_ram_3_0_51))
+              (portRef ADB3 (instanceRef pdp_ram_3_1_50))
+              (portRef ADB3 (instanceRef pdp_ram_3_2_49))
+              (portRef ADB3 (instanceRef pdp_ram_3_3_48))
+              (portRef ADB3 (instanceRef pdp_ram_4_0_47))
+              (portRef ADB3 (instanceRef pdp_ram_4_1_46))
+              (portRef ADB3 (instanceRef pdp_ram_4_2_45))
+              (portRef ADB3 (instanceRef pdp_ram_4_3_44))
+              (portRef ADB3 (instanceRef pdp_ram_5_0_43))
+              (portRef ADB3 (instanceRef pdp_ram_5_1_42))
+              (portRef ADB3 (instanceRef pdp_ram_5_2_41))
+              (portRef ADB3 (instanceRef pdp_ram_5_3_40))
+              (portRef ADB3 (instanceRef pdp_ram_6_0_39))
+              (portRef ADB3 (instanceRef pdp_ram_6_1_38))
+              (portRef ADB3 (instanceRef pdp_ram_6_2_37))
+              (portRef ADB3 (instanceRef pdp_ram_6_3_36))
+              (portRef ADB3 (instanceRef pdp_ram_7_0_35))
+              (portRef ADB3 (instanceRef pdp_ram_7_1_34))
+              (portRef ADB3 (instanceRef pdp_ram_7_2_33))
+              (portRef ADB3 (instanceRef pdp_ram_7_3_32))
+              (portRef ADB3 (instanceRef pdp_ram_8_0_31))
+              (portRef ADB3 (instanceRef pdp_ram_8_1_30))
+              (portRef ADB3 (instanceRef pdp_ram_8_2_29))
+              (portRef ADB3 (instanceRef pdp_ram_8_3_28))
+              (portRef ADB3 (instanceRef pdp_ram_9_0_27))
+              (portRef ADB3 (instanceRef pdp_ram_9_1_26))
+              (portRef ADB3 (instanceRef pdp_ram_9_2_25))
+              (portRef ADB3 (instanceRef pdp_ram_9_3_24))
+              (portRef ADB3 (instanceRef pdp_ram_10_0_23))
+              (portRef ADB3 (instanceRef pdp_ram_10_1_22))
+              (portRef ADB3 (instanceRef pdp_ram_10_2_21))
+              (portRef ADB3 (instanceRef pdp_ram_10_3_20))
+              (portRef ADB3 (instanceRef pdp_ram_11_0_19))
+              (portRef ADB3 (instanceRef pdp_ram_11_1_18))
+              (portRef ADB3 (instanceRef pdp_ram_11_2_17))
+              (portRef ADB3 (instanceRef pdp_ram_11_3_16))
+              (portRef ADB3 (instanceRef pdp_ram_12_0_15))
+              (portRef ADB3 (instanceRef pdp_ram_12_1_14))
+              (portRef ADB3 (instanceRef pdp_ram_12_2_13))
+              (portRef ADB3 (instanceRef pdp_ram_12_3_12))
+              (portRef ADB3 (instanceRef pdp_ram_13_0_11))
+              (portRef ADB3 (instanceRef pdp_ram_13_1_10))
+              (portRef ADB3 (instanceRef pdp_ram_13_2_9))
+              (portRef ADB3 (instanceRef pdp_ram_13_3_8))
+              (portRef ADB3 (instanceRef pdp_ram_14_0_7))
+              (portRef ADB3 (instanceRef pdp_ram_14_1_6))
+              (portRef ADB3 (instanceRef pdp_ram_14_2_5))
+              (portRef ADB3 (instanceRef pdp_ram_14_3_4))
+              (portRef ADB3 (instanceRef pdp_ram_15_0_3))
+              (portRef ADB3 (instanceRef pdp_ram_15_1_2))
+              (portRef ADB3 (instanceRef pdp_ram_15_2_1))
+              (portRef ADB3 (instanceRef pdp_ram_15_3_0))
+              (portRef Q (instanceRef FF_40))))
+          (net cnt_con_inv
+            (joined
+              (portRef B0 (instanceRef wcnt_0))
+              (portRef Z (instanceRef INV_0))))
+          (net wcount_0
+            (joined
+              (portRef A1 (instanceRef wcnt_0))
+              (portRef Q (instanceRef FF_88))
+              (portRef D (instanceRef FF_56))
+              (portRef A0 (instanceRef w_ctr_0))))
+          (net cnt_con
+            (joined
+              (portRef A0 (instanceRef wcnt_0))
+              (portRef Z (instanceRef AND2_t3))
+              (portRef A (instanceRef INV_0))
+              (portRef B1 (instanceRef bdcnt_bctr_cia))
+              (portRef A1 (instanceRef bdcnt_bctr_cia))
+              (portRef B1 (instanceRef bdcnt_bctr_0))
+              (portRef B0 (instanceRef bdcnt_bctr_0))
+              (portRef B1 (instanceRef bdcnt_bctr_1))
+              (portRef B0 (instanceRef bdcnt_bctr_1))
+              (portRef B1 (instanceRef bdcnt_bctr_2))
+              (portRef B0 (instanceRef bdcnt_bctr_2))
+              (portRef B1 (instanceRef bdcnt_bctr_3))
+              (portRef B0 (instanceRef bdcnt_bctr_3))
+              (portRef B1 (instanceRef bdcnt_bctr_4))
+              (portRef B0 (instanceRef bdcnt_bctr_4))
+              (portRef B1 (instanceRef bdcnt_bctr_5))
+              (portRef B0 (instanceRef bdcnt_bctr_5))
+              (portRef B1 (instanceRef bdcnt_bctr_6))
+              (portRef B0 (instanceRef bdcnt_bctr_6))
+              (portRef B1 (instanceRef bdcnt_bctr_7))
+              (portRef B0 (instanceRef bdcnt_bctr_7))))
+          (net precin
+            (joined
+              (portRef CIN (instanceRef wcnt_0))
+              (portRef COUT (instanceRef precin_inst1073))))
+          (net wcnt_sub_1
+            (joined
+              (portRef S0 (instanceRef wcnt_1))
+              (portRef D (instanceRef FF_15))))
+          (net wcnt_sub_2
+            (joined
+              (portRef S1 (instanceRef wcnt_1))
+              (portRef D (instanceRef FF_14))))
+          (net rptr_2
+            (joined
+              (portRef B1 (instanceRef wcnt_1))
+              (portRef ADB5 (instanceRef pdp_ram_0_0_63))
+              (portRef ADB5 (instanceRef pdp_ram_0_1_62))
+              (portRef ADB5 (instanceRef pdp_ram_0_2_61))
+              (portRef ADB5 (instanceRef pdp_ram_0_3_60))
+              (portRef ADB5 (instanceRef pdp_ram_1_0_59))
+              (portRef ADB5 (instanceRef pdp_ram_1_1_58))
+              (portRef ADB5 (instanceRef pdp_ram_1_2_57))
+              (portRef ADB5 (instanceRef pdp_ram_1_3_56))
+              (portRef ADB5 (instanceRef pdp_ram_2_0_55))
+              (portRef ADB5 (instanceRef pdp_ram_2_1_54))
+              (portRef ADB5 (instanceRef pdp_ram_2_2_53))
+              (portRef ADB5 (instanceRef pdp_ram_2_3_52))
+              (portRef ADB5 (instanceRef pdp_ram_3_0_51))
+              (portRef ADB5 (instanceRef pdp_ram_3_1_50))
+              (portRef ADB5 (instanceRef pdp_ram_3_2_49))
+              (portRef ADB5 (instanceRef pdp_ram_3_3_48))
+              (portRef ADB5 (instanceRef pdp_ram_4_0_47))
+              (portRef ADB5 (instanceRef pdp_ram_4_1_46))
+              (portRef ADB5 (instanceRef pdp_ram_4_2_45))
+              (portRef ADB5 (instanceRef pdp_ram_4_3_44))
+              (portRef ADB5 (instanceRef pdp_ram_5_0_43))
+              (portRef ADB5 (instanceRef pdp_ram_5_1_42))
+              (portRef ADB5 (instanceRef pdp_ram_5_2_41))
+              (portRef ADB5 (instanceRef pdp_ram_5_3_40))
+              (portRef ADB5 (instanceRef pdp_ram_6_0_39))
+              (portRef ADB5 (instanceRef pdp_ram_6_1_38))
+              (portRef ADB5 (instanceRef pdp_ram_6_2_37))
+              (portRef ADB5 (instanceRef pdp_ram_6_3_36))
+              (portRef ADB5 (instanceRef pdp_ram_7_0_35))
+              (portRef ADB5 (instanceRef pdp_ram_7_1_34))
+              (portRef ADB5 (instanceRef pdp_ram_7_2_33))
+              (portRef ADB5 (instanceRef pdp_ram_7_3_32))
+              (portRef ADB5 (instanceRef pdp_ram_8_0_31))
+              (portRef ADB5 (instanceRef pdp_ram_8_1_30))
+              (portRef ADB5 (instanceRef pdp_ram_8_2_29))
+              (portRef ADB5 (instanceRef pdp_ram_8_3_28))
+              (portRef ADB5 (instanceRef pdp_ram_9_0_27))
+              (portRef ADB5 (instanceRef pdp_ram_9_1_26))
+              (portRef ADB5 (instanceRef pdp_ram_9_2_25))
+              (portRef ADB5 (instanceRef pdp_ram_9_3_24))
+              (portRef ADB5 (instanceRef pdp_ram_10_0_23))
+              (portRef ADB5 (instanceRef pdp_ram_10_1_22))
+              (portRef ADB5 (instanceRef pdp_ram_10_2_21))
+              (portRef ADB5 (instanceRef pdp_ram_10_3_20))
+              (portRef ADB5 (instanceRef pdp_ram_11_0_19))
+              (portRef ADB5 (instanceRef pdp_ram_11_1_18))
+              (portRef ADB5 (instanceRef pdp_ram_11_2_17))
+              (portRef ADB5 (instanceRef pdp_ram_11_3_16))
+              (portRef ADB5 (instanceRef pdp_ram_12_0_15))
+              (portRef ADB5 (instanceRef pdp_ram_12_1_14))
+              (portRef ADB5 (instanceRef pdp_ram_12_2_13))
+              (portRef ADB5 (instanceRef pdp_ram_12_3_12))
+              (portRef ADB5 (instanceRef pdp_ram_13_0_11))
+              (portRef ADB5 (instanceRef pdp_ram_13_1_10))
+              (portRef ADB5 (instanceRef pdp_ram_13_2_9))
+              (portRef ADB5 (instanceRef pdp_ram_13_3_8))
+              (portRef ADB5 (instanceRef pdp_ram_14_0_7))
+              (portRef ADB5 (instanceRef pdp_ram_14_1_6))
+              (portRef ADB5 (instanceRef pdp_ram_14_2_5))
+              (portRef ADB5 (instanceRef pdp_ram_14_3_4))
+              (portRef ADB5 (instanceRef pdp_ram_15_0_3))
+              (portRef ADB5 (instanceRef pdp_ram_15_1_2))
+              (portRef ADB5 (instanceRef pdp_ram_15_2_1))
+              (portRef ADB5 (instanceRef pdp_ram_15_3_0))
+              (portRef Q (instanceRef FF_38))))
+          (net rptr_1
+            (joined
+              (portRef B0 (instanceRef wcnt_1))
+              (portRef ADB4 (instanceRef pdp_ram_0_0_63))
+              (portRef ADB4 (instanceRef pdp_ram_0_1_62))
+              (portRef ADB4 (instanceRef pdp_ram_0_2_61))
+              (portRef ADB4 (instanceRef pdp_ram_0_3_60))
+              (portRef ADB4 (instanceRef pdp_ram_1_0_59))
+              (portRef ADB4 (instanceRef pdp_ram_1_1_58))
+              (portRef ADB4 (instanceRef pdp_ram_1_2_57))
+              (portRef ADB4 (instanceRef pdp_ram_1_3_56))
+              (portRef ADB4 (instanceRef pdp_ram_2_0_55))
+              (portRef ADB4 (instanceRef pdp_ram_2_1_54))
+              (portRef ADB4 (instanceRef pdp_ram_2_2_53))
+              (portRef ADB4 (instanceRef pdp_ram_2_3_52))
+              (portRef ADB4 (instanceRef pdp_ram_3_0_51))
+              (portRef ADB4 (instanceRef pdp_ram_3_1_50))
+              (portRef ADB4 (instanceRef pdp_ram_3_2_49))
+              (portRef ADB4 (instanceRef pdp_ram_3_3_48))
+              (portRef ADB4 (instanceRef pdp_ram_4_0_47))
+              (portRef ADB4 (instanceRef pdp_ram_4_1_46))
+              (portRef ADB4 (instanceRef pdp_ram_4_2_45))
+              (portRef ADB4 (instanceRef pdp_ram_4_3_44))
+              (portRef ADB4 (instanceRef pdp_ram_5_0_43))
+              (portRef ADB4 (instanceRef pdp_ram_5_1_42))
+              (portRef ADB4 (instanceRef pdp_ram_5_2_41))
+              (portRef ADB4 (instanceRef pdp_ram_5_3_40))
+              (portRef ADB4 (instanceRef pdp_ram_6_0_39))
+              (portRef ADB4 (instanceRef pdp_ram_6_1_38))
+              (portRef ADB4 (instanceRef pdp_ram_6_2_37))
+              (portRef ADB4 (instanceRef pdp_ram_6_3_36))
+              (portRef ADB4 (instanceRef pdp_ram_7_0_35))
+              (portRef ADB4 (instanceRef pdp_ram_7_1_34))
+              (portRef ADB4 (instanceRef pdp_ram_7_2_33))
+              (portRef ADB4 (instanceRef pdp_ram_7_3_32))
+              (portRef ADB4 (instanceRef pdp_ram_8_0_31))
+              (portRef ADB4 (instanceRef pdp_ram_8_1_30))
+              (portRef ADB4 (instanceRef pdp_ram_8_2_29))
+              (portRef ADB4 (instanceRef pdp_ram_8_3_28))
+              (portRef ADB4 (instanceRef pdp_ram_9_0_27))
+              (portRef ADB4 (instanceRef pdp_ram_9_1_26))
+              (portRef ADB4 (instanceRef pdp_ram_9_2_25))
+              (portRef ADB4 (instanceRef pdp_ram_9_3_24))
+              (portRef ADB4 (instanceRef pdp_ram_10_0_23))
+              (portRef ADB4 (instanceRef pdp_ram_10_1_22))
+              (portRef ADB4 (instanceRef pdp_ram_10_2_21))
+              (portRef ADB4 (instanceRef pdp_ram_10_3_20))
+              (portRef ADB4 (instanceRef pdp_ram_11_0_19))
+              (portRef ADB4 (instanceRef pdp_ram_11_1_18))
+              (portRef ADB4 (instanceRef pdp_ram_11_2_17))
+              (portRef ADB4 (instanceRef pdp_ram_11_3_16))
+              (portRef ADB4 (instanceRef pdp_ram_12_0_15))
+              (portRef ADB4 (instanceRef pdp_ram_12_1_14))
+              (portRef ADB4 (instanceRef pdp_ram_12_2_13))
+              (portRef ADB4 (instanceRef pdp_ram_12_3_12))
+              (portRef ADB4 (instanceRef pdp_ram_13_0_11))
+              (portRef ADB4 (instanceRef pdp_ram_13_1_10))
+              (portRef ADB4 (instanceRef pdp_ram_13_2_9))
+              (portRef ADB4 (instanceRef pdp_ram_13_3_8))
+              (portRef ADB4 (instanceRef pdp_ram_14_0_7))
+              (portRef ADB4 (instanceRef pdp_ram_14_1_6))
+              (portRef ADB4 (instanceRef pdp_ram_14_2_5))
+              (portRef ADB4 (instanceRef pdp_ram_14_3_4))
+              (portRef ADB4 (instanceRef pdp_ram_15_0_3))
+              (portRef ADB4 (instanceRef pdp_ram_15_1_2))
+              (portRef ADB4 (instanceRef pdp_ram_15_2_1))
+              (portRef ADB4 (instanceRef pdp_ram_15_3_0))
+              (portRef Q (instanceRef FF_39))))
+          (net wcount_2
+            (joined
+              (portRef A1 (instanceRef wcnt_1))
+              (portRef Q (instanceRef FF_86))
+              (portRef D (instanceRef FF_54))
+              (portRef A0 (instanceRef w_ctr_1))))
+          (net wcount_1
+            (joined
+              (portRef A0 (instanceRef wcnt_1))
+              (portRef Q (instanceRef FF_87))
+              (portRef D (instanceRef FF_55))
+              (portRef A1 (instanceRef w_ctr_0))))
+          (net co0_5
+            (joined
+              (portRef CIN (instanceRef wcnt_1))
+              (portRef COUT (instanceRef wcnt_0))))
+          (net wcnt_sub_3
+            (joined
+              (portRef S0 (instanceRef wcnt_2))
+              (portRef D (instanceRef FF_13))))
+          (net wcnt_sub_4
+            (joined
+              (portRef S1 (instanceRef wcnt_2))
+              (portRef D (instanceRef FF_12))))
+          (net rptr_4
+            (joined
+              (portRef B1 (instanceRef wcnt_2))
+              (portRef ADB7 (instanceRef pdp_ram_0_0_63))
+              (portRef ADB7 (instanceRef pdp_ram_0_1_62))
+              (portRef ADB7 (instanceRef pdp_ram_0_2_61))
+              (portRef ADB7 (instanceRef pdp_ram_0_3_60))
+              (portRef ADB7 (instanceRef pdp_ram_1_0_59))
+              (portRef ADB7 (instanceRef pdp_ram_1_1_58))
+              (portRef ADB7 (instanceRef pdp_ram_1_2_57))
+              (portRef ADB7 (instanceRef pdp_ram_1_3_56))
+              (portRef ADB7 (instanceRef pdp_ram_2_0_55))
+              (portRef ADB7 (instanceRef pdp_ram_2_1_54))
+              (portRef ADB7 (instanceRef pdp_ram_2_2_53))
+              (portRef ADB7 (instanceRef pdp_ram_2_3_52))
+              (portRef ADB7 (instanceRef pdp_ram_3_0_51))
+              (portRef ADB7 (instanceRef pdp_ram_3_1_50))
+              (portRef ADB7 (instanceRef pdp_ram_3_2_49))
+              (portRef ADB7 (instanceRef pdp_ram_3_3_48))
+              (portRef ADB7 (instanceRef pdp_ram_4_0_47))
+              (portRef ADB7 (instanceRef pdp_ram_4_1_46))
+              (portRef ADB7 (instanceRef pdp_ram_4_2_45))
+              (portRef ADB7 (instanceRef pdp_ram_4_3_44))
+              (portRef ADB7 (instanceRef pdp_ram_5_0_43))
+              (portRef ADB7 (instanceRef pdp_ram_5_1_42))
+              (portRef ADB7 (instanceRef pdp_ram_5_2_41))
+              (portRef ADB7 (instanceRef pdp_ram_5_3_40))
+              (portRef ADB7 (instanceRef pdp_ram_6_0_39))
+              (portRef ADB7 (instanceRef pdp_ram_6_1_38))
+              (portRef ADB7 (instanceRef pdp_ram_6_2_37))
+              (portRef ADB7 (instanceRef pdp_ram_6_3_36))
+              (portRef ADB7 (instanceRef pdp_ram_7_0_35))
+              (portRef ADB7 (instanceRef pdp_ram_7_1_34))
+              (portRef ADB7 (instanceRef pdp_ram_7_2_33))
+              (portRef ADB7 (instanceRef pdp_ram_7_3_32))
+              (portRef ADB7 (instanceRef pdp_ram_8_0_31))
+              (portRef ADB7 (instanceRef pdp_ram_8_1_30))
+              (portRef ADB7 (instanceRef pdp_ram_8_2_29))
+              (portRef ADB7 (instanceRef pdp_ram_8_3_28))
+              (portRef ADB7 (instanceRef pdp_ram_9_0_27))
+              (portRef ADB7 (instanceRef pdp_ram_9_1_26))
+              (portRef ADB7 (instanceRef pdp_ram_9_2_25))
+              (portRef ADB7 (instanceRef pdp_ram_9_3_24))
+              (portRef ADB7 (instanceRef pdp_ram_10_0_23))
+              (portRef ADB7 (instanceRef pdp_ram_10_1_22))
+              (portRef ADB7 (instanceRef pdp_ram_10_2_21))
+              (portRef ADB7 (instanceRef pdp_ram_10_3_20))
+              (portRef ADB7 (instanceRef pdp_ram_11_0_19))
+              (portRef ADB7 (instanceRef pdp_ram_11_1_18))
+              (portRef ADB7 (instanceRef pdp_ram_11_2_17))
+              (portRef ADB7 (instanceRef pdp_ram_11_3_16))
+              (portRef ADB7 (instanceRef pdp_ram_12_0_15))
+              (portRef ADB7 (instanceRef pdp_ram_12_1_14))
+              (portRef ADB7 (instanceRef pdp_ram_12_2_13))
+              (portRef ADB7 (instanceRef pdp_ram_12_3_12))
+              (portRef ADB7 (instanceRef pdp_ram_13_0_11))
+              (portRef ADB7 (instanceRef pdp_ram_13_1_10))
+              (portRef ADB7 (instanceRef pdp_ram_13_2_9))
+              (portRef ADB7 (instanceRef pdp_ram_13_3_8))
+              (portRef ADB7 (instanceRef pdp_ram_14_0_7))
+              (portRef ADB7 (instanceRef pdp_ram_14_1_6))
+              (portRef ADB7 (instanceRef pdp_ram_14_2_5))
+              (portRef ADB7 (instanceRef pdp_ram_14_3_4))
+              (portRef ADB7 (instanceRef pdp_ram_15_0_3))
+              (portRef ADB7 (instanceRef pdp_ram_15_1_2))
+              (portRef ADB7 (instanceRef pdp_ram_15_2_1))
+              (portRef ADB7 (instanceRef pdp_ram_15_3_0))
+              (portRef Q (instanceRef FF_36))))
+          (net rptr_3
+            (joined
+              (portRef B0 (instanceRef wcnt_2))
+              (portRef ADB6 (instanceRef pdp_ram_0_0_63))
+              (portRef ADB6 (instanceRef pdp_ram_0_1_62))
+              (portRef ADB6 (instanceRef pdp_ram_0_2_61))
+              (portRef ADB6 (instanceRef pdp_ram_0_3_60))
+              (portRef ADB6 (instanceRef pdp_ram_1_0_59))
+              (portRef ADB6 (instanceRef pdp_ram_1_1_58))
+              (portRef ADB6 (instanceRef pdp_ram_1_2_57))
+              (portRef ADB6 (instanceRef pdp_ram_1_3_56))
+              (portRef ADB6 (instanceRef pdp_ram_2_0_55))
+              (portRef ADB6 (instanceRef pdp_ram_2_1_54))
+              (portRef ADB6 (instanceRef pdp_ram_2_2_53))
+              (portRef ADB6 (instanceRef pdp_ram_2_3_52))
+              (portRef ADB6 (instanceRef pdp_ram_3_0_51))
+              (portRef ADB6 (instanceRef pdp_ram_3_1_50))
+              (portRef ADB6 (instanceRef pdp_ram_3_2_49))
+              (portRef ADB6 (instanceRef pdp_ram_3_3_48))
+              (portRef ADB6 (instanceRef pdp_ram_4_0_47))
+              (portRef ADB6 (instanceRef pdp_ram_4_1_46))
+              (portRef ADB6 (instanceRef pdp_ram_4_2_45))
+              (portRef ADB6 (instanceRef pdp_ram_4_3_44))
+              (portRef ADB6 (instanceRef pdp_ram_5_0_43))
+              (portRef ADB6 (instanceRef pdp_ram_5_1_42))
+              (portRef ADB6 (instanceRef pdp_ram_5_2_41))
+              (portRef ADB6 (instanceRef pdp_ram_5_3_40))
+              (portRef ADB6 (instanceRef pdp_ram_6_0_39))
+              (portRef ADB6 (instanceRef pdp_ram_6_1_38))
+              (portRef ADB6 (instanceRef pdp_ram_6_2_37))
+              (portRef ADB6 (instanceRef pdp_ram_6_3_36))
+              (portRef ADB6 (instanceRef pdp_ram_7_0_35))
+              (portRef ADB6 (instanceRef pdp_ram_7_1_34))
+              (portRef ADB6 (instanceRef pdp_ram_7_2_33))
+              (portRef ADB6 (instanceRef pdp_ram_7_3_32))
+              (portRef ADB6 (instanceRef pdp_ram_8_0_31))
+              (portRef ADB6 (instanceRef pdp_ram_8_1_30))
+              (portRef ADB6 (instanceRef pdp_ram_8_2_29))
+              (portRef ADB6 (instanceRef pdp_ram_8_3_28))
+              (portRef ADB6 (instanceRef pdp_ram_9_0_27))
+              (portRef ADB6 (instanceRef pdp_ram_9_1_26))
+              (portRef ADB6 (instanceRef pdp_ram_9_2_25))
+              (portRef ADB6 (instanceRef pdp_ram_9_3_24))
+              (portRef ADB6 (instanceRef pdp_ram_10_0_23))
+              (portRef ADB6 (instanceRef pdp_ram_10_1_22))
+              (portRef ADB6 (instanceRef pdp_ram_10_2_21))
+              (portRef ADB6 (instanceRef pdp_ram_10_3_20))
+              (portRef ADB6 (instanceRef pdp_ram_11_0_19))
+              (portRef ADB6 (instanceRef pdp_ram_11_1_18))
+              (portRef ADB6 (instanceRef pdp_ram_11_2_17))
+              (portRef ADB6 (instanceRef pdp_ram_11_3_16))
+              (portRef ADB6 (instanceRef pdp_ram_12_0_15))
+              (portRef ADB6 (instanceRef pdp_ram_12_1_14))
+              (portRef ADB6 (instanceRef pdp_ram_12_2_13))
+              (portRef ADB6 (instanceRef pdp_ram_12_3_12))
+              (portRef ADB6 (instanceRef pdp_ram_13_0_11))
+              (portRef ADB6 (instanceRef pdp_ram_13_1_10))
+              (portRef ADB6 (instanceRef pdp_ram_13_2_9))
+              (portRef ADB6 (instanceRef pdp_ram_13_3_8))
+              (portRef ADB6 (instanceRef pdp_ram_14_0_7))
+              (portRef ADB6 (instanceRef pdp_ram_14_1_6))
+              (portRef ADB6 (instanceRef pdp_ram_14_2_5))
+              (portRef ADB6 (instanceRef pdp_ram_14_3_4))
+              (portRef ADB6 (instanceRef pdp_ram_15_0_3))
+              (portRef ADB6 (instanceRef pdp_ram_15_1_2))
+              (portRef ADB6 (instanceRef pdp_ram_15_2_1))
+              (portRef ADB6 (instanceRef pdp_ram_15_3_0))
+              (portRef Q (instanceRef FF_37))))
+          (net wcount_4
+            (joined
+              (portRef A1 (instanceRef wcnt_2))
+              (portRef Q (instanceRef FF_84))
+              (portRef D (instanceRef FF_52))
+              (portRef A0 (instanceRef w_ctr_2))))
+          (net wcount_3
+            (joined
+              (portRef A0 (instanceRef wcnt_2))
+              (portRef Q (instanceRef FF_85))
+              (portRef D (instanceRef FF_53))
+              (portRef A1 (instanceRef w_ctr_1))))
+          (net co1_5
+            (joined
+              (portRef CIN (instanceRef wcnt_2))
+              (portRef COUT (instanceRef wcnt_1))))
+          (net wcnt_sub_5
+            (joined
+              (portRef S0 (instanceRef wcnt_3))
+              (portRef D (instanceRef FF_11))))
+          (net wcnt_sub_6
+            (joined
+              (portRef S1 (instanceRef wcnt_3))
+              (portRef D (instanceRef FF_10))))
+          (net rptr_6
+            (joined
+              (portRef B1 (instanceRef wcnt_3))
+              (portRef ADB9 (instanceRef pdp_ram_0_0_63))
+              (portRef ADB9 (instanceRef pdp_ram_0_1_62))
+              (portRef ADB9 (instanceRef pdp_ram_0_2_61))
+              (portRef ADB9 (instanceRef pdp_ram_0_3_60))
+              (portRef ADB9 (instanceRef pdp_ram_1_0_59))
+              (portRef ADB9 (instanceRef pdp_ram_1_1_58))
+              (portRef ADB9 (instanceRef pdp_ram_1_2_57))
+              (portRef ADB9 (instanceRef pdp_ram_1_3_56))
+              (portRef ADB9 (instanceRef pdp_ram_2_0_55))
+              (portRef ADB9 (instanceRef pdp_ram_2_1_54))
+              (portRef ADB9 (instanceRef pdp_ram_2_2_53))
+              (portRef ADB9 (instanceRef pdp_ram_2_3_52))
+              (portRef ADB9 (instanceRef pdp_ram_3_0_51))
+              (portRef ADB9 (instanceRef pdp_ram_3_1_50))
+              (portRef ADB9 (instanceRef pdp_ram_3_2_49))
+              (portRef ADB9 (instanceRef pdp_ram_3_3_48))
+              (portRef ADB9 (instanceRef pdp_ram_4_0_47))
+              (portRef ADB9 (instanceRef pdp_ram_4_1_46))
+              (portRef ADB9 (instanceRef pdp_ram_4_2_45))
+              (portRef ADB9 (instanceRef pdp_ram_4_3_44))
+              (portRef ADB9 (instanceRef pdp_ram_5_0_43))
+              (portRef ADB9 (instanceRef pdp_ram_5_1_42))
+              (portRef ADB9 (instanceRef pdp_ram_5_2_41))
+              (portRef ADB9 (instanceRef pdp_ram_5_3_40))
+              (portRef ADB9 (instanceRef pdp_ram_6_0_39))
+              (portRef ADB9 (instanceRef pdp_ram_6_1_38))
+              (portRef ADB9 (instanceRef pdp_ram_6_2_37))
+              (portRef ADB9 (instanceRef pdp_ram_6_3_36))
+              (portRef ADB9 (instanceRef pdp_ram_7_0_35))
+              (portRef ADB9 (instanceRef pdp_ram_7_1_34))
+              (portRef ADB9 (instanceRef pdp_ram_7_2_33))
+              (portRef ADB9 (instanceRef pdp_ram_7_3_32))
+              (portRef ADB9 (instanceRef pdp_ram_8_0_31))
+              (portRef ADB9 (instanceRef pdp_ram_8_1_30))
+              (portRef ADB9 (instanceRef pdp_ram_8_2_29))
+              (portRef ADB9 (instanceRef pdp_ram_8_3_28))
+              (portRef ADB9 (instanceRef pdp_ram_9_0_27))
+              (portRef ADB9 (instanceRef pdp_ram_9_1_26))
+              (portRef ADB9 (instanceRef pdp_ram_9_2_25))
+              (portRef ADB9 (instanceRef pdp_ram_9_3_24))
+              (portRef ADB9 (instanceRef pdp_ram_10_0_23))
+              (portRef ADB9 (instanceRef pdp_ram_10_1_22))
+              (portRef ADB9 (instanceRef pdp_ram_10_2_21))
+              (portRef ADB9 (instanceRef pdp_ram_10_3_20))
+              (portRef ADB9 (instanceRef pdp_ram_11_0_19))
+              (portRef ADB9 (instanceRef pdp_ram_11_1_18))
+              (portRef ADB9 (instanceRef pdp_ram_11_2_17))
+              (portRef ADB9 (instanceRef pdp_ram_11_3_16))
+              (portRef ADB9 (instanceRef pdp_ram_12_0_15))
+              (portRef ADB9 (instanceRef pdp_ram_12_1_14))
+              (portRef ADB9 (instanceRef pdp_ram_12_2_13))
+              (portRef ADB9 (instanceRef pdp_ram_12_3_12))
+              (portRef ADB9 (instanceRef pdp_ram_13_0_11))
+              (portRef ADB9 (instanceRef pdp_ram_13_1_10))
+              (portRef ADB9 (instanceRef pdp_ram_13_2_9))
+              (portRef ADB9 (instanceRef pdp_ram_13_3_8))
+              (portRef ADB9 (instanceRef pdp_ram_14_0_7))
+              (portRef ADB9 (instanceRef pdp_ram_14_1_6))
+              (portRef ADB9 (instanceRef pdp_ram_14_2_5))
+              (portRef ADB9 (instanceRef pdp_ram_14_3_4))
+              (portRef ADB9 (instanceRef pdp_ram_15_0_3))
+              (portRef ADB9 (instanceRef pdp_ram_15_1_2))
+              (portRef ADB9 (instanceRef pdp_ram_15_2_1))
+              (portRef ADB9 (instanceRef pdp_ram_15_3_0))
+              (portRef Q (instanceRef FF_34))))
+          (net rptr_5
+            (joined
+              (portRef B0 (instanceRef wcnt_3))
+              (portRef ADB8 (instanceRef pdp_ram_0_0_63))
+              (portRef ADB8 (instanceRef pdp_ram_0_1_62))
+              (portRef ADB8 (instanceRef pdp_ram_0_2_61))
+              (portRef ADB8 (instanceRef pdp_ram_0_3_60))
+              (portRef ADB8 (instanceRef pdp_ram_1_0_59))
+              (portRef ADB8 (instanceRef pdp_ram_1_1_58))
+              (portRef ADB8 (instanceRef pdp_ram_1_2_57))
+              (portRef ADB8 (instanceRef pdp_ram_1_3_56))
+              (portRef ADB8 (instanceRef pdp_ram_2_0_55))
+              (portRef ADB8 (instanceRef pdp_ram_2_1_54))
+              (portRef ADB8 (instanceRef pdp_ram_2_2_53))
+              (portRef ADB8 (instanceRef pdp_ram_2_3_52))
+              (portRef ADB8 (instanceRef pdp_ram_3_0_51))
+              (portRef ADB8 (instanceRef pdp_ram_3_1_50))
+              (portRef ADB8 (instanceRef pdp_ram_3_2_49))
+              (portRef ADB8 (instanceRef pdp_ram_3_3_48))
+              (portRef ADB8 (instanceRef pdp_ram_4_0_47))
+              (portRef ADB8 (instanceRef pdp_ram_4_1_46))
+              (portRef ADB8 (instanceRef pdp_ram_4_2_45))
+              (portRef ADB8 (instanceRef pdp_ram_4_3_44))
+              (portRef ADB8 (instanceRef pdp_ram_5_0_43))
+              (portRef ADB8 (instanceRef pdp_ram_5_1_42))
+              (portRef ADB8 (instanceRef pdp_ram_5_2_41))
+              (portRef ADB8 (instanceRef pdp_ram_5_3_40))
+              (portRef ADB8 (instanceRef pdp_ram_6_0_39))
+              (portRef ADB8 (instanceRef pdp_ram_6_1_38))
+              (portRef ADB8 (instanceRef pdp_ram_6_2_37))
+              (portRef ADB8 (instanceRef pdp_ram_6_3_36))
+              (portRef ADB8 (instanceRef pdp_ram_7_0_35))
+              (portRef ADB8 (instanceRef pdp_ram_7_1_34))
+              (portRef ADB8 (instanceRef pdp_ram_7_2_33))
+              (portRef ADB8 (instanceRef pdp_ram_7_3_32))
+              (portRef ADB8 (instanceRef pdp_ram_8_0_31))
+              (portRef ADB8 (instanceRef pdp_ram_8_1_30))
+              (portRef ADB8 (instanceRef pdp_ram_8_2_29))
+              (portRef ADB8 (instanceRef pdp_ram_8_3_28))
+              (portRef ADB8 (instanceRef pdp_ram_9_0_27))
+              (portRef ADB8 (instanceRef pdp_ram_9_1_26))
+              (portRef ADB8 (instanceRef pdp_ram_9_2_25))
+              (portRef ADB8 (instanceRef pdp_ram_9_3_24))
+              (portRef ADB8 (instanceRef pdp_ram_10_0_23))
+              (portRef ADB8 (instanceRef pdp_ram_10_1_22))
+              (portRef ADB8 (instanceRef pdp_ram_10_2_21))
+              (portRef ADB8 (instanceRef pdp_ram_10_3_20))
+              (portRef ADB8 (instanceRef pdp_ram_11_0_19))
+              (portRef ADB8 (instanceRef pdp_ram_11_1_18))
+              (portRef ADB8 (instanceRef pdp_ram_11_2_17))
+              (portRef ADB8 (instanceRef pdp_ram_11_3_16))
+              (portRef ADB8 (instanceRef pdp_ram_12_0_15))
+              (portRef ADB8 (instanceRef pdp_ram_12_1_14))
+              (portRef ADB8 (instanceRef pdp_ram_12_2_13))
+              (portRef ADB8 (instanceRef pdp_ram_12_3_12))
+              (portRef ADB8 (instanceRef pdp_ram_13_0_11))
+              (portRef ADB8 (instanceRef pdp_ram_13_1_10))
+              (portRef ADB8 (instanceRef pdp_ram_13_2_9))
+              (portRef ADB8 (instanceRef pdp_ram_13_3_8))
+              (portRef ADB8 (instanceRef pdp_ram_14_0_7))
+              (portRef ADB8 (instanceRef pdp_ram_14_1_6))
+              (portRef ADB8 (instanceRef pdp_ram_14_2_5))
+              (portRef ADB8 (instanceRef pdp_ram_14_3_4))
+              (portRef ADB8 (instanceRef pdp_ram_15_0_3))
+              (portRef ADB8 (instanceRef pdp_ram_15_1_2))
+              (portRef ADB8 (instanceRef pdp_ram_15_2_1))
+              (portRef ADB8 (instanceRef pdp_ram_15_3_0))
+              (portRef Q (instanceRef FF_35))))
+          (net wcount_6
+            (joined
+              (portRef A1 (instanceRef wcnt_3))
+              (portRef Q (instanceRef FF_82))
+              (portRef D (instanceRef FF_50))
+              (portRef A0 (instanceRef w_ctr_3))))
+          (net wcount_5
+            (joined
+              (portRef A0 (instanceRef wcnt_3))
+              (portRef Q (instanceRef FF_83))
+              (portRef D (instanceRef FF_51))
+              (portRef A1 (instanceRef w_ctr_2))))
+          (net co2_5
+            (joined
+              (portRef CIN (instanceRef wcnt_3))
+              (portRef COUT (instanceRef wcnt_2))))
+          (net wcnt_sub_7
+            (joined
+              (portRef S0 (instanceRef wcnt_4))
+              (portRef D (instanceRef FF_9))))
+          (net wcnt_sub_8
+            (joined
+              (portRef S1 (instanceRef wcnt_4))
+              (portRef D (instanceRef FF_8))))
+          (net rptr_8
+            (joined
+              (portRef B1 (instanceRef wcnt_4))
+              (portRef ADB11 (instanceRef pdp_ram_0_0_63))
+              (portRef ADB11 (instanceRef pdp_ram_0_1_62))
+              (portRef ADB11 (instanceRef pdp_ram_0_2_61))
+              (portRef ADB11 (instanceRef pdp_ram_0_3_60))
+              (portRef ADB11 (instanceRef pdp_ram_1_0_59))
+              (portRef ADB11 (instanceRef pdp_ram_1_1_58))
+              (portRef ADB11 (instanceRef pdp_ram_1_2_57))
+              (portRef ADB11 (instanceRef pdp_ram_1_3_56))
+              (portRef ADB11 (instanceRef pdp_ram_2_0_55))
+              (portRef ADB11 (instanceRef pdp_ram_2_1_54))
+              (portRef ADB11 (instanceRef pdp_ram_2_2_53))
+              (portRef ADB11 (instanceRef pdp_ram_2_3_52))
+              (portRef ADB11 (instanceRef pdp_ram_3_0_51))
+              (portRef ADB11 (instanceRef pdp_ram_3_1_50))
+              (portRef ADB11 (instanceRef pdp_ram_3_2_49))
+              (portRef ADB11 (instanceRef pdp_ram_3_3_48))
+              (portRef ADB11 (instanceRef pdp_ram_4_0_47))
+              (portRef ADB11 (instanceRef pdp_ram_4_1_46))
+              (portRef ADB11 (instanceRef pdp_ram_4_2_45))
+              (portRef ADB11 (instanceRef pdp_ram_4_3_44))
+              (portRef ADB11 (instanceRef pdp_ram_5_0_43))
+              (portRef ADB11 (instanceRef pdp_ram_5_1_42))
+              (portRef ADB11 (instanceRef pdp_ram_5_2_41))
+              (portRef ADB11 (instanceRef pdp_ram_5_3_40))
+              (portRef ADB11 (instanceRef pdp_ram_6_0_39))
+              (portRef ADB11 (instanceRef pdp_ram_6_1_38))
+              (portRef ADB11 (instanceRef pdp_ram_6_2_37))
+              (portRef ADB11 (instanceRef pdp_ram_6_3_36))
+              (portRef ADB11 (instanceRef pdp_ram_7_0_35))
+              (portRef ADB11 (instanceRef pdp_ram_7_1_34))
+              (portRef ADB11 (instanceRef pdp_ram_7_2_33))
+              (portRef ADB11 (instanceRef pdp_ram_7_3_32))
+              (portRef ADB11 (instanceRef pdp_ram_8_0_31))
+              (portRef ADB11 (instanceRef pdp_ram_8_1_30))
+              (portRef ADB11 (instanceRef pdp_ram_8_2_29))
+              (portRef ADB11 (instanceRef pdp_ram_8_3_28))
+              (portRef ADB11 (instanceRef pdp_ram_9_0_27))
+              (portRef ADB11 (instanceRef pdp_ram_9_1_26))
+              (portRef ADB11 (instanceRef pdp_ram_9_2_25))
+              (portRef ADB11 (instanceRef pdp_ram_9_3_24))
+              (portRef ADB11 (instanceRef pdp_ram_10_0_23))
+              (portRef ADB11 (instanceRef pdp_ram_10_1_22))
+              (portRef ADB11 (instanceRef pdp_ram_10_2_21))
+              (portRef ADB11 (instanceRef pdp_ram_10_3_20))
+              (portRef ADB11 (instanceRef pdp_ram_11_0_19))
+              (portRef ADB11 (instanceRef pdp_ram_11_1_18))
+              (portRef ADB11 (instanceRef pdp_ram_11_2_17))
+              (portRef ADB11 (instanceRef pdp_ram_11_3_16))
+              (portRef ADB11 (instanceRef pdp_ram_12_0_15))
+              (portRef ADB11 (instanceRef pdp_ram_12_1_14))
+              (portRef ADB11 (instanceRef pdp_ram_12_2_13))
+              (portRef ADB11 (instanceRef pdp_ram_12_3_12))
+              (portRef ADB11 (instanceRef pdp_ram_13_0_11))
+              (portRef ADB11 (instanceRef pdp_ram_13_1_10))
+              (portRef ADB11 (instanceRef pdp_ram_13_2_9))
+              (portRef ADB11 (instanceRef pdp_ram_13_3_8))
+              (portRef ADB11 (instanceRef pdp_ram_14_0_7))
+              (portRef ADB11 (instanceRef pdp_ram_14_1_6))
+              (portRef ADB11 (instanceRef pdp_ram_14_2_5))
+              (portRef ADB11 (instanceRef pdp_ram_14_3_4))
+              (portRef ADB11 (instanceRef pdp_ram_15_0_3))
+              (portRef ADB11 (instanceRef pdp_ram_15_1_2))
+              (portRef ADB11 (instanceRef pdp_ram_15_2_1))
+              (portRef ADB11 (instanceRef pdp_ram_15_3_0))
+              (portRef Q (instanceRef FF_32))))
+          (net rptr_7
+            (joined
+              (portRef B0 (instanceRef wcnt_4))
+              (portRef ADB10 (instanceRef pdp_ram_0_0_63))
+              (portRef ADB10 (instanceRef pdp_ram_0_1_62))
+              (portRef ADB10 (instanceRef pdp_ram_0_2_61))
+              (portRef ADB10 (instanceRef pdp_ram_0_3_60))
+              (portRef ADB10 (instanceRef pdp_ram_1_0_59))
+              (portRef ADB10 (instanceRef pdp_ram_1_1_58))
+              (portRef ADB10 (instanceRef pdp_ram_1_2_57))
+              (portRef ADB10 (instanceRef pdp_ram_1_3_56))
+              (portRef ADB10 (instanceRef pdp_ram_2_0_55))
+              (portRef ADB10 (instanceRef pdp_ram_2_1_54))
+              (portRef ADB10 (instanceRef pdp_ram_2_2_53))
+              (portRef ADB10 (instanceRef pdp_ram_2_3_52))
+              (portRef ADB10 (instanceRef pdp_ram_3_0_51))
+              (portRef ADB10 (instanceRef pdp_ram_3_1_50))
+              (portRef ADB10 (instanceRef pdp_ram_3_2_49))
+              (portRef ADB10 (instanceRef pdp_ram_3_3_48))
+              (portRef ADB10 (instanceRef pdp_ram_4_0_47))
+              (portRef ADB10 (instanceRef pdp_ram_4_1_46))
+              (portRef ADB10 (instanceRef pdp_ram_4_2_45))
+              (portRef ADB10 (instanceRef pdp_ram_4_3_44))
+              (portRef ADB10 (instanceRef pdp_ram_5_0_43))
+              (portRef ADB10 (instanceRef pdp_ram_5_1_42))
+              (portRef ADB10 (instanceRef pdp_ram_5_2_41))
+              (portRef ADB10 (instanceRef pdp_ram_5_3_40))
+              (portRef ADB10 (instanceRef pdp_ram_6_0_39))
+              (portRef ADB10 (instanceRef pdp_ram_6_1_38))
+              (portRef ADB10 (instanceRef pdp_ram_6_2_37))
+              (portRef ADB10 (instanceRef pdp_ram_6_3_36))
+              (portRef ADB10 (instanceRef pdp_ram_7_0_35))
+              (portRef ADB10 (instanceRef pdp_ram_7_1_34))
+              (portRef ADB10 (instanceRef pdp_ram_7_2_33))
+              (portRef ADB10 (instanceRef pdp_ram_7_3_32))
+              (portRef ADB10 (instanceRef pdp_ram_8_0_31))
+              (portRef ADB10 (instanceRef pdp_ram_8_1_30))
+              (portRef ADB10 (instanceRef pdp_ram_8_2_29))
+              (portRef ADB10 (instanceRef pdp_ram_8_3_28))
+              (portRef ADB10 (instanceRef pdp_ram_9_0_27))
+              (portRef ADB10 (instanceRef pdp_ram_9_1_26))
+              (portRef ADB10 (instanceRef pdp_ram_9_2_25))
+              (portRef ADB10 (instanceRef pdp_ram_9_3_24))
+              (portRef ADB10 (instanceRef pdp_ram_10_0_23))
+              (portRef ADB10 (instanceRef pdp_ram_10_1_22))
+              (portRef ADB10 (instanceRef pdp_ram_10_2_21))
+              (portRef ADB10 (instanceRef pdp_ram_10_3_20))
+              (portRef ADB10 (instanceRef pdp_ram_11_0_19))
+              (portRef ADB10 (instanceRef pdp_ram_11_1_18))
+              (portRef ADB10 (instanceRef pdp_ram_11_2_17))
+              (portRef ADB10 (instanceRef pdp_ram_11_3_16))
+              (portRef ADB10 (instanceRef pdp_ram_12_0_15))
+              (portRef ADB10 (instanceRef pdp_ram_12_1_14))
+              (portRef ADB10 (instanceRef pdp_ram_12_2_13))
+              (portRef ADB10 (instanceRef pdp_ram_12_3_12))
+              (portRef ADB10 (instanceRef pdp_ram_13_0_11))
+              (portRef ADB10 (instanceRef pdp_ram_13_1_10))
+              (portRef ADB10 (instanceRef pdp_ram_13_2_9))
+              (portRef ADB10 (instanceRef pdp_ram_13_3_8))
+              (portRef ADB10 (instanceRef pdp_ram_14_0_7))
+              (portRef ADB10 (instanceRef pdp_ram_14_1_6))
+              (portRef ADB10 (instanceRef pdp_ram_14_2_5))
+              (portRef ADB10 (instanceRef pdp_ram_14_3_4))
+              (portRef ADB10 (instanceRef pdp_ram_15_0_3))
+              (portRef ADB10 (instanceRef pdp_ram_15_1_2))
+              (portRef ADB10 (instanceRef pdp_ram_15_2_1))
+              (portRef ADB10 (instanceRef pdp_ram_15_3_0))
+              (portRef Q (instanceRef FF_33))))
+          (net wcount_8
+            (joined
+              (portRef A1 (instanceRef wcnt_4))
+              (portRef Q (instanceRef FF_80))
+              (portRef D (instanceRef FF_48))
+              (portRef A0 (instanceRef w_ctr_4))))
+          (net wcount_7
+            (joined
+              (portRef A0 (instanceRef wcnt_4))
+              (portRef Q (instanceRef FF_81))
+              (portRef D (instanceRef FF_49))
+              (portRef A1 (instanceRef w_ctr_3))))
+          (net co3_5
+            (joined
+              (portRef CIN (instanceRef wcnt_4))
+              (portRef COUT (instanceRef wcnt_3))))
+          (net wcnt_sub_9
+            (joined
+              (portRef S0 (instanceRef wcnt_5))
+              (portRef D (instanceRef FF_7))))
+          (net wcnt_sub_10
+            (joined
+              (portRef S1 (instanceRef wcnt_5))
+              (portRef D (instanceRef FF_6))))
+          (net rptr_10
+            (joined
+              (portRef B1 (instanceRef wcnt_5))
+              (portRef ADB13 (instanceRef pdp_ram_0_0_63))
+              (portRef ADB13 (instanceRef pdp_ram_0_1_62))
+              (portRef ADB13 (instanceRef pdp_ram_0_2_61))
+              (portRef ADB13 (instanceRef pdp_ram_0_3_60))
+              (portRef ADB13 (instanceRef pdp_ram_1_0_59))
+              (portRef ADB13 (instanceRef pdp_ram_1_1_58))
+              (portRef ADB13 (instanceRef pdp_ram_1_2_57))
+              (portRef ADB13 (instanceRef pdp_ram_1_3_56))
+              (portRef ADB13 (instanceRef pdp_ram_2_0_55))
+              (portRef ADB13 (instanceRef pdp_ram_2_1_54))
+              (portRef ADB13 (instanceRef pdp_ram_2_2_53))
+              (portRef ADB13 (instanceRef pdp_ram_2_3_52))
+              (portRef ADB13 (instanceRef pdp_ram_3_0_51))
+              (portRef ADB13 (instanceRef pdp_ram_3_1_50))
+              (portRef ADB13 (instanceRef pdp_ram_3_2_49))
+              (portRef ADB13 (instanceRef pdp_ram_3_3_48))
+              (portRef ADB13 (instanceRef pdp_ram_4_0_47))
+              (portRef ADB13 (instanceRef pdp_ram_4_1_46))
+              (portRef ADB13 (instanceRef pdp_ram_4_2_45))
+              (portRef ADB13 (instanceRef pdp_ram_4_3_44))
+              (portRef ADB13 (instanceRef pdp_ram_5_0_43))
+              (portRef ADB13 (instanceRef pdp_ram_5_1_42))
+              (portRef ADB13 (instanceRef pdp_ram_5_2_41))
+              (portRef ADB13 (instanceRef pdp_ram_5_3_40))
+              (portRef ADB13 (instanceRef pdp_ram_6_0_39))
+              (portRef ADB13 (instanceRef pdp_ram_6_1_38))
+              (portRef ADB13 (instanceRef pdp_ram_6_2_37))
+              (portRef ADB13 (instanceRef pdp_ram_6_3_36))
+              (portRef ADB13 (instanceRef pdp_ram_7_0_35))
+              (portRef ADB13 (instanceRef pdp_ram_7_1_34))
+              (portRef ADB13 (instanceRef pdp_ram_7_2_33))
+              (portRef ADB13 (instanceRef pdp_ram_7_3_32))
+              (portRef ADB13 (instanceRef pdp_ram_8_0_31))
+              (portRef ADB13 (instanceRef pdp_ram_8_1_30))
+              (portRef ADB13 (instanceRef pdp_ram_8_2_29))
+              (portRef ADB13 (instanceRef pdp_ram_8_3_28))
+              (portRef ADB13 (instanceRef pdp_ram_9_0_27))
+              (portRef ADB13 (instanceRef pdp_ram_9_1_26))
+              (portRef ADB13 (instanceRef pdp_ram_9_2_25))
+              (portRef ADB13 (instanceRef pdp_ram_9_3_24))
+              (portRef ADB13 (instanceRef pdp_ram_10_0_23))
+              (portRef ADB13 (instanceRef pdp_ram_10_1_22))
+              (portRef ADB13 (instanceRef pdp_ram_10_2_21))
+              (portRef ADB13 (instanceRef pdp_ram_10_3_20))
+              (portRef ADB13 (instanceRef pdp_ram_11_0_19))
+              (portRef ADB13 (instanceRef pdp_ram_11_1_18))
+              (portRef ADB13 (instanceRef pdp_ram_11_2_17))
+              (portRef ADB13 (instanceRef pdp_ram_11_3_16))
+              (portRef ADB13 (instanceRef pdp_ram_12_0_15))
+              (portRef ADB13 (instanceRef pdp_ram_12_1_14))
+              (portRef ADB13 (instanceRef pdp_ram_12_2_13))
+              (portRef ADB13 (instanceRef pdp_ram_12_3_12))
+              (portRef ADB13 (instanceRef pdp_ram_13_0_11))
+              (portRef ADB13 (instanceRef pdp_ram_13_1_10))
+              (portRef ADB13 (instanceRef pdp_ram_13_2_9))
+              (portRef ADB13 (instanceRef pdp_ram_13_3_8))
+              (portRef ADB13 (instanceRef pdp_ram_14_0_7))
+              (portRef ADB13 (instanceRef pdp_ram_14_1_6))
+              (portRef ADB13 (instanceRef pdp_ram_14_2_5))
+              (portRef ADB13 (instanceRef pdp_ram_14_3_4))
+              (portRef ADB13 (instanceRef pdp_ram_15_0_3))
+              (portRef ADB13 (instanceRef pdp_ram_15_1_2))
+              (portRef ADB13 (instanceRef pdp_ram_15_2_1))
+              (portRef ADB13 (instanceRef pdp_ram_15_3_0))
+              (portRef Q (instanceRef FF_30))))
+          (net rptr_9
+            (joined
+              (portRef B0 (instanceRef wcnt_5))
+              (portRef ADB12 (instanceRef pdp_ram_0_0_63))
+              (portRef ADB12 (instanceRef pdp_ram_0_1_62))
+              (portRef ADB12 (instanceRef pdp_ram_0_2_61))
+              (portRef ADB12 (instanceRef pdp_ram_0_3_60))
+              (portRef ADB12 (instanceRef pdp_ram_1_0_59))
+              (portRef ADB12 (instanceRef pdp_ram_1_1_58))
+              (portRef ADB12 (instanceRef pdp_ram_1_2_57))
+              (portRef ADB12 (instanceRef pdp_ram_1_3_56))
+              (portRef ADB12 (instanceRef pdp_ram_2_0_55))
+              (portRef ADB12 (instanceRef pdp_ram_2_1_54))
+              (portRef ADB12 (instanceRef pdp_ram_2_2_53))
+              (portRef ADB12 (instanceRef pdp_ram_2_3_52))
+              (portRef ADB12 (instanceRef pdp_ram_3_0_51))
+              (portRef ADB12 (instanceRef pdp_ram_3_1_50))
+              (portRef ADB12 (instanceRef pdp_ram_3_2_49))
+              (portRef ADB12 (instanceRef pdp_ram_3_3_48))
+              (portRef ADB12 (instanceRef pdp_ram_4_0_47))
+              (portRef ADB12 (instanceRef pdp_ram_4_1_46))
+              (portRef ADB12 (instanceRef pdp_ram_4_2_45))
+              (portRef ADB12 (instanceRef pdp_ram_4_3_44))
+              (portRef ADB12 (instanceRef pdp_ram_5_0_43))
+              (portRef ADB12 (instanceRef pdp_ram_5_1_42))
+              (portRef ADB12 (instanceRef pdp_ram_5_2_41))
+              (portRef ADB12 (instanceRef pdp_ram_5_3_40))
+              (portRef ADB12 (instanceRef pdp_ram_6_0_39))
+              (portRef ADB12 (instanceRef pdp_ram_6_1_38))
+              (portRef ADB12 (instanceRef pdp_ram_6_2_37))
+              (portRef ADB12 (instanceRef pdp_ram_6_3_36))
+              (portRef ADB12 (instanceRef pdp_ram_7_0_35))
+              (portRef ADB12 (instanceRef pdp_ram_7_1_34))
+              (portRef ADB12 (instanceRef pdp_ram_7_2_33))
+              (portRef ADB12 (instanceRef pdp_ram_7_3_32))
+              (portRef ADB12 (instanceRef pdp_ram_8_0_31))
+              (portRef ADB12 (instanceRef pdp_ram_8_1_30))
+              (portRef ADB12 (instanceRef pdp_ram_8_2_29))
+              (portRef ADB12 (instanceRef pdp_ram_8_3_28))
+              (portRef ADB12 (instanceRef pdp_ram_9_0_27))
+              (portRef ADB12 (instanceRef pdp_ram_9_1_26))
+              (portRef ADB12 (instanceRef pdp_ram_9_2_25))
+              (portRef ADB12 (instanceRef pdp_ram_9_3_24))
+              (portRef ADB12 (instanceRef pdp_ram_10_0_23))
+              (portRef ADB12 (instanceRef pdp_ram_10_1_22))
+              (portRef ADB12 (instanceRef pdp_ram_10_2_21))
+              (portRef ADB12 (instanceRef pdp_ram_10_3_20))
+              (portRef ADB12 (instanceRef pdp_ram_11_0_19))
+              (portRef ADB12 (instanceRef pdp_ram_11_1_18))
+              (portRef ADB12 (instanceRef pdp_ram_11_2_17))
+              (portRef ADB12 (instanceRef pdp_ram_11_3_16))
+              (portRef ADB12 (instanceRef pdp_ram_12_0_15))
+              (portRef ADB12 (instanceRef pdp_ram_12_1_14))
+              (portRef ADB12 (instanceRef pdp_ram_12_2_13))
+              (portRef ADB12 (instanceRef pdp_ram_12_3_12))
+              (portRef ADB12 (instanceRef pdp_ram_13_0_11))
+              (portRef ADB12 (instanceRef pdp_ram_13_1_10))
+              (portRef ADB12 (instanceRef pdp_ram_13_2_9))
+              (portRef ADB12 (instanceRef pdp_ram_13_3_8))
+              (portRef ADB12 (instanceRef pdp_ram_14_0_7))
+              (portRef ADB12 (instanceRef pdp_ram_14_1_6))
+              (portRef ADB12 (instanceRef pdp_ram_14_2_5))
+              (portRef ADB12 (instanceRef pdp_ram_14_3_4))
+              (portRef ADB12 (instanceRef pdp_ram_15_0_3))
+              (portRef ADB12 (instanceRef pdp_ram_15_1_2))
+              (portRef ADB12 (instanceRef pdp_ram_15_2_1))
+              (portRef ADB12 (instanceRef pdp_ram_15_3_0))
+              (portRef Q (instanceRef FF_31))))
+          (net wcount_10
+            (joined
+              (portRef A1 (instanceRef wcnt_5))
+              (portRef Q (instanceRef FF_78))
+              (portRef D (instanceRef FF_46))
+              (portRef A0 (instanceRef w_ctr_5))))
+          (net wcount_9
+            (joined
+              (portRef A0 (instanceRef wcnt_5))
+              (portRef Q (instanceRef FF_79))
+              (portRef D (instanceRef FF_47))
+              (portRef A1 (instanceRef w_ctr_4))))
+          (net co4_5
+            (joined
+              (portRef CIN (instanceRef wcnt_5))
+              (portRef COUT (instanceRef wcnt_4))))
+          (net wcnt_sub_11
+            (joined
+              (portRef S0 (instanceRef wcnt_6))
+              (portRef D (instanceRef FF_5))))
+          (net wcnt_sub_12
+            (joined
+              (portRef S1 (instanceRef wcnt_6))
+              (portRef D (instanceRef FF_4))))
+          (net rptr_12
+            (joined
+              (portRef B1 (instanceRef wcnt_6))
+              (portRef A (instanceRef INV_4))
+              (portRef AD2 (instanceRef LUT4_110))
+              (portRef AD2 (instanceRef LUT4_108))
+              (portRef AD2 (instanceRef LUT4_106))
+              (portRef AD2 (instanceRef LUT4_104))
+              (portRef AD2 (instanceRef LUT4_102))
+              (portRef AD2 (instanceRef LUT4_100))
+              (portRef AD2 (instanceRef LUT4_98))
+              (portRef AD2 (instanceRef LUT4_96))
+              (portRef AD2 (instanceRef LUT4_78))
+              (portRef AD2 (instanceRef LUT4_76))
+              (portRef AD2 (instanceRef LUT4_74))
+              (portRef AD2 (instanceRef LUT4_72))
+              (portRef AD2 (instanceRef LUT4_70))
+              (portRef AD2 (instanceRef LUT4_68))
+              (portRef AD2 (instanceRef LUT4_66))
+              (portRef AD2 (instanceRef LUT4_64))
+              (portRef AD2 (instanceRef LUT4_46))
+              (portRef AD2 (instanceRef LUT4_44))
+              (portRef AD2 (instanceRef LUT4_42))
+              (portRef AD2 (instanceRef LUT4_40))
+              (portRef AD2 (instanceRef LUT4_38))
+              (portRef AD2 (instanceRef LUT4_36))
+              (portRef AD2 (instanceRef LUT4_34))
+              (portRef AD2 (instanceRef LUT4_32))
+              (portRef AD2 (instanceRef LUT4_14))
+              (portRef AD2 (instanceRef LUT4_12))
+              (portRef AD2 (instanceRef LUT4_10))
+              (portRef AD2 (instanceRef LUT4_8))
+              (portRef AD2 (instanceRef LUT4_6))
+              (portRef AD2 (instanceRef LUT4_4))
+              (portRef AD2 (instanceRef LUT4_2))
+              (portRef AD2 (instanceRef LUT4_0))
+              (portRef Q (instanceRef FF_28))
+              (portRef D (instanceRef FF_23))))
+          (net rptr_11
+            (joined
+              (portRef B0 (instanceRef wcnt_6))
+              (portRef A (instanceRef INV_5))
+              (portRef AD3 (instanceRef LUT4_118))
+              (portRef AD3 (instanceRef LUT4_116))
+              (portRef AD3 (instanceRef LUT4_114))
+              (portRef AD3 (instanceRef LUT4_112))
+              (portRef AD3 (instanceRef LUT4_102))
+              (portRef AD3 (instanceRef LUT4_100))
+              (portRef AD3 (instanceRef LUT4_98))
+              (portRef AD3 (instanceRef LUT4_96))
+              (portRef AD3 (instanceRef LUT4_86))
+              (portRef AD3 (instanceRef LUT4_84))
+              (portRef AD3 (instanceRef LUT4_82))
+              (portRef AD3 (instanceRef LUT4_80))
+              (portRef AD3 (instanceRef LUT4_70))
+              (portRef AD3 (instanceRef LUT4_68))
+              (portRef AD3 (instanceRef LUT4_66))
+              (portRef AD3 (instanceRef LUT4_64))
+              (portRef AD3 (instanceRef LUT4_54))
+              (portRef AD3 (instanceRef LUT4_52))
+              (portRef AD3 (instanceRef LUT4_50))
+              (portRef AD3 (instanceRef LUT4_48))
+              (portRef AD3 (instanceRef LUT4_38))
+              (portRef AD3 (instanceRef LUT4_36))
+              (portRef AD3 (instanceRef LUT4_34))
+              (portRef AD3 (instanceRef LUT4_32))
+              (portRef AD3 (instanceRef LUT4_22))
+              (portRef AD3 (instanceRef LUT4_20))
+              (portRef AD3 (instanceRef LUT4_18))
+              (portRef AD3 (instanceRef LUT4_16))
+              (portRef AD3 (instanceRef LUT4_6))
+              (portRef AD3 (instanceRef LUT4_4))
+              (portRef AD3 (instanceRef LUT4_2))
+              (portRef AD3 (instanceRef LUT4_0))
+              (portRef Q (instanceRef FF_29))
+              (portRef D (instanceRef FF_24))))
+          (net wcount_12
+            (joined
+              (portRef A1 (instanceRef wcnt_6))
+              (portRef Q (instanceRef FF_76))
+              (portRef D (instanceRef FF_44))
+              (portRef A0 (instanceRef w_ctr_6))))
+          (net wcount_11
+            (joined
+              (portRef A0 (instanceRef wcnt_6))
+              (portRef Q (instanceRef FF_77))
+              (portRef D (instanceRef FF_45))
+              (portRef A1 (instanceRef w_ctr_5))))
+          (net co5_5
+            (joined
+              (portRef CIN (instanceRef wcnt_6))
+              (portRef COUT (instanceRef wcnt_5))))
+          (net wcnt_sub_13
+            (joined
+              (portRef S0 (instanceRef wcnt_7))
+              (portRef D (instanceRef FF_3))))
+          (net wcnt_sub_14
+            (joined
+              (portRef S1 (instanceRef wcnt_7))
+              (portRef D (instanceRef FF_2))))
+          (net rptr_14
+            (joined
+              (portRef B1 (instanceRef wcnt_7))
+              (portRef A (instanceRef INV_2))
+              (portRef AD0 (instanceRef LUT4_62))
+              (portRef AD0 (instanceRef LUT4_60))
+              (portRef AD0 (instanceRef LUT4_58))
+              (portRef AD0 (instanceRef LUT4_56))
+              (portRef AD0 (instanceRef LUT4_54))
+              (portRef AD0 (instanceRef LUT4_52))
+              (portRef AD0 (instanceRef LUT4_50))
+              (portRef AD0 (instanceRef LUT4_48))
+              (portRef AD0 (instanceRef LUT4_46))
+              (portRef AD0 (instanceRef LUT4_44))
+              (portRef AD0 (instanceRef LUT4_42))
+              (portRef AD0 (instanceRef LUT4_40))
+              (portRef AD0 (instanceRef LUT4_38))
+              (portRef AD0 (instanceRef LUT4_36))
+              (portRef AD0 (instanceRef LUT4_34))
+              (portRef AD0 (instanceRef LUT4_32))
+              (portRef AD0 (instanceRef LUT4_30))
+              (portRef AD0 (instanceRef LUT4_28))
+              (portRef AD0 (instanceRef LUT4_26))
+              (portRef AD0 (instanceRef LUT4_24))
+              (portRef AD0 (instanceRef LUT4_22))
+              (portRef AD0 (instanceRef LUT4_20))
+              (portRef AD0 (instanceRef LUT4_18))
+              (portRef AD0 (instanceRef LUT4_16))
+              (portRef AD0 (instanceRef LUT4_14))
+              (portRef AD0 (instanceRef LUT4_12))
+              (portRef AD0 (instanceRef LUT4_10))
+              (portRef AD0 (instanceRef LUT4_8))
+              (portRef AD0 (instanceRef LUT4_6))
+              (portRef AD0 (instanceRef LUT4_4))
+              (portRef AD0 (instanceRef LUT4_2))
+              (portRef AD0 (instanceRef LUT4_0))
+              (portRef Q (instanceRef FF_26))
+              (portRef D (instanceRef FF_21))))
+          (net rptr_13
+            (joined
+              (portRef B0 (instanceRef wcnt_7))
+              (portRef A (instanceRef INV_3))
+              (portRef AD1 (instanceRef LUT4_94))
+              (portRef AD1 (instanceRef LUT4_92))
+              (portRef AD1 (instanceRef LUT4_90))
+              (portRef AD1 (instanceRef LUT4_88))
+              (portRef AD1 (instanceRef LUT4_86))
+              (portRef AD1 (instanceRef LUT4_84))
+              (portRef AD1 (instanceRef LUT4_82))
+              (portRef AD1 (instanceRef LUT4_80))
+              (portRef AD1 (instanceRef LUT4_78))
+              (portRef AD1 (instanceRef LUT4_76))
+              (portRef AD1 (instanceRef LUT4_74))
+              (portRef AD1 (instanceRef LUT4_72))
+              (portRef AD1 (instanceRef LUT4_70))
+              (portRef AD1 (instanceRef LUT4_68))
+              (portRef AD1 (instanceRef LUT4_66))
+              (portRef AD1 (instanceRef LUT4_64))
+              (portRef AD1 (instanceRef LUT4_30))
+              (portRef AD1 (instanceRef LUT4_28))
+              (portRef AD1 (instanceRef LUT4_26))
+              (portRef AD1 (instanceRef LUT4_24))
+              (portRef AD1 (instanceRef LUT4_22))
+              (portRef AD1 (instanceRef LUT4_20))
+              (portRef AD1 (instanceRef LUT4_18))
+              (portRef AD1 (instanceRef LUT4_16))
+              (portRef AD1 (instanceRef LUT4_14))
+              (portRef AD1 (instanceRef LUT4_12))
+              (portRef AD1 (instanceRef LUT4_10))
+              (portRef AD1 (instanceRef LUT4_8))
+              (portRef AD1 (instanceRef LUT4_6))
+              (portRef AD1 (instanceRef LUT4_4))
+              (portRef AD1 (instanceRef LUT4_2))
+              (portRef AD1 (instanceRef LUT4_0))
+              (portRef Q (instanceRef FF_27))
+              (portRef D (instanceRef FF_22))))
+          (net wcount_14
+            (joined
+              (portRef A1 (instanceRef wcnt_7))
+              (portRef Q (instanceRef FF_74))
+              (portRef D (instanceRef FF_42))
+              (portRef A0 (instanceRef w_ctr_7))))
+          (net wcount_13
+            (joined
+              (portRef A0 (instanceRef wcnt_7))
+              (portRef Q (instanceRef FF_75))
+              (portRef D (instanceRef FF_43))
+              (portRef A1 (instanceRef w_ctr_6))))
+          (net co6_5
+            (joined
+              (portRef CIN (instanceRef wcnt_7))
+              (portRef COUT (instanceRef wcnt_6))))
+          (net wcnt_sub_15
+            (joined
+              (portRef S0 (instanceRef wcnt_8))
+              (portRef D (instanceRef FF_1))))
+          (net wcnt_sub_msb
+            (joined
+              (portRef A0 (instanceRef wcnt_8))
+              (portRef Z (instanceRef XOR2_t0))))
+          (net co7_3
+            (joined
+              (portRef CIN (instanceRef wcnt_8))
+              (portRef COUT (instanceRef wcnt_7))))
+          (net wren_i
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_ci_a))
+              (portRef Z (instanceRef AND2_t5))
+              (portRef A (instanceRef AND2_t3))
+              (portRef A (instanceRef XOR2_t2))
+              (portRef A (instanceRef INV_10))
+              (portRef AD1 (instanceRef LUT4_129))
+              (portRef A (instanceRef INV_1))
+              (portRef OCEA (instanceRef pdp_ram_0_0_63))
+              (portRef CEA (instanceRef pdp_ram_0_0_63))
+              (portRef OCEA (instanceRef pdp_ram_0_1_62))
+              (portRef CEA (instanceRef pdp_ram_0_1_62))
+              (portRef OCEA (instanceRef pdp_ram_0_2_61))
+              (portRef CEA (instanceRef pdp_ram_0_2_61))
+              (portRef OCEA (instanceRef pdp_ram_0_3_60))
+              (portRef CEA (instanceRef pdp_ram_0_3_60))
+              (portRef OCEA (instanceRef pdp_ram_1_0_59))
+              (portRef CEA (instanceRef pdp_ram_1_0_59))
+              (portRef OCEA (instanceRef pdp_ram_1_1_58))
+              (portRef CEA (instanceRef pdp_ram_1_1_58))
+              (portRef OCEA (instanceRef pdp_ram_1_2_57))
+              (portRef CEA (instanceRef pdp_ram_1_2_57))
+              (portRef OCEA (instanceRef pdp_ram_1_3_56))
+              (portRef CEA (instanceRef pdp_ram_1_3_56))
+              (portRef OCEA (instanceRef pdp_ram_2_0_55))
+              (portRef CEA (instanceRef pdp_ram_2_0_55))
+              (portRef OCEA (instanceRef pdp_ram_2_1_54))
+              (portRef CEA (instanceRef pdp_ram_2_1_54))
+              (portRef OCEA (instanceRef pdp_ram_2_2_53))
+              (portRef CEA (instanceRef pdp_ram_2_2_53))
+              (portRef OCEA (instanceRef pdp_ram_2_3_52))
+              (portRef CEA (instanceRef pdp_ram_2_3_52))
+              (portRef OCEA (instanceRef pdp_ram_3_0_51))
+              (portRef CEA (instanceRef pdp_ram_3_0_51))
+              (portRef OCEA (instanceRef pdp_ram_3_1_50))
+              (portRef CEA (instanceRef pdp_ram_3_1_50))
+              (portRef OCEA (instanceRef pdp_ram_3_2_49))
+              (portRef CEA (instanceRef pdp_ram_3_2_49))
+              (portRef OCEA (instanceRef pdp_ram_3_3_48))
+              (portRef CEA (instanceRef pdp_ram_3_3_48))
+              (portRef OCEA (instanceRef pdp_ram_4_0_47))
+              (portRef CEA (instanceRef pdp_ram_4_0_47))
+              (portRef OCEA (instanceRef pdp_ram_4_1_46))
+              (portRef CEA (instanceRef pdp_ram_4_1_46))
+              (portRef OCEA (instanceRef pdp_ram_4_2_45))
+              (portRef CEA (instanceRef pdp_ram_4_2_45))
+              (portRef OCEA (instanceRef pdp_ram_4_3_44))
+              (portRef CEA (instanceRef pdp_ram_4_3_44))
+              (portRef OCEA (instanceRef pdp_ram_5_0_43))
+              (portRef CEA (instanceRef pdp_ram_5_0_43))
+              (portRef OCEA (instanceRef pdp_ram_5_1_42))
+              (portRef CEA (instanceRef pdp_ram_5_1_42))
+              (portRef OCEA (instanceRef pdp_ram_5_2_41))
+              (portRef CEA (instanceRef pdp_ram_5_2_41))
+              (portRef OCEA (instanceRef pdp_ram_5_3_40))
+              (portRef CEA (instanceRef pdp_ram_5_3_40))
+              (portRef OCEA (instanceRef pdp_ram_6_0_39))
+              (portRef CEA (instanceRef pdp_ram_6_0_39))
+              (portRef OCEA (instanceRef pdp_ram_6_1_38))
+              (portRef CEA (instanceRef pdp_ram_6_1_38))
+              (portRef OCEA (instanceRef pdp_ram_6_2_37))
+              (portRef CEA (instanceRef pdp_ram_6_2_37))
+              (portRef OCEA (instanceRef pdp_ram_6_3_36))
+              (portRef CEA (instanceRef pdp_ram_6_3_36))
+              (portRef OCEA (instanceRef pdp_ram_7_0_35))
+              (portRef CEA (instanceRef pdp_ram_7_0_35))
+              (portRef OCEA (instanceRef pdp_ram_7_1_34))
+              (portRef CEA (instanceRef pdp_ram_7_1_34))
+              (portRef OCEA (instanceRef pdp_ram_7_2_33))
+              (portRef CEA (instanceRef pdp_ram_7_2_33))
+              (portRef OCEA (instanceRef pdp_ram_7_3_32))
+              (portRef CEA (instanceRef pdp_ram_7_3_32))
+              (portRef OCEA (instanceRef pdp_ram_8_0_31))
+              (portRef CEA (instanceRef pdp_ram_8_0_31))
+              (portRef OCEA (instanceRef pdp_ram_8_1_30))
+              (portRef CEA (instanceRef pdp_ram_8_1_30))
+              (portRef OCEA (instanceRef pdp_ram_8_2_29))
+              (portRef CEA (instanceRef pdp_ram_8_2_29))
+              (portRef OCEA (instanceRef pdp_ram_8_3_28))
+              (portRef CEA (instanceRef pdp_ram_8_3_28))
+              (portRef OCEA (instanceRef pdp_ram_9_0_27))
+              (portRef CEA (instanceRef pdp_ram_9_0_27))
+              (portRef OCEA (instanceRef pdp_ram_9_1_26))
+              (portRef CEA (instanceRef pdp_ram_9_1_26))
+              (portRef OCEA (instanceRef pdp_ram_9_2_25))
+              (portRef CEA (instanceRef pdp_ram_9_2_25))
+              (portRef OCEA (instanceRef pdp_ram_9_3_24))
+              (portRef CEA (instanceRef pdp_ram_9_3_24))
+              (portRef OCEA (instanceRef pdp_ram_10_0_23))
+              (portRef CEA (instanceRef pdp_ram_10_0_23))
+              (portRef OCEA (instanceRef pdp_ram_10_1_22))
+              (portRef CEA (instanceRef pdp_ram_10_1_22))
+              (portRef OCEA (instanceRef pdp_ram_10_2_21))
+              (portRef CEA (instanceRef pdp_ram_10_2_21))
+              (portRef OCEA (instanceRef pdp_ram_10_3_20))
+              (portRef CEA (instanceRef pdp_ram_10_3_20))
+              (portRef OCEA (instanceRef pdp_ram_11_0_19))
+              (portRef CEA (instanceRef pdp_ram_11_0_19))
+              (portRef OCEA (instanceRef pdp_ram_11_1_18))
+              (portRef CEA (instanceRef pdp_ram_11_1_18))
+              (portRef OCEA (instanceRef pdp_ram_11_2_17))
+              (portRef CEA (instanceRef pdp_ram_11_2_17))
+              (portRef OCEA (instanceRef pdp_ram_11_3_16))
+              (portRef CEA (instanceRef pdp_ram_11_3_16))
+              (portRef OCEA (instanceRef pdp_ram_12_0_15))
+              (portRef CEA (instanceRef pdp_ram_12_0_15))
+              (portRef OCEA (instanceRef pdp_ram_12_1_14))
+              (portRef CEA (instanceRef pdp_ram_12_1_14))
+              (portRef OCEA (instanceRef pdp_ram_12_2_13))
+              (portRef CEA (instanceRef pdp_ram_12_2_13))
+              (portRef OCEA (instanceRef pdp_ram_12_3_12))
+              (portRef CEA (instanceRef pdp_ram_12_3_12))
+              (portRef OCEA (instanceRef pdp_ram_13_0_11))
+              (portRef CEA (instanceRef pdp_ram_13_0_11))
+              (portRef OCEA (instanceRef pdp_ram_13_1_10))
+              (portRef CEA (instanceRef pdp_ram_13_1_10))
+              (portRef OCEA (instanceRef pdp_ram_13_2_9))
+              (portRef CEA (instanceRef pdp_ram_13_2_9))
+              (portRef OCEA (instanceRef pdp_ram_13_3_8))
+              (portRef CEA (instanceRef pdp_ram_13_3_8))
+              (portRef OCEA (instanceRef pdp_ram_14_0_7))
+              (portRef CEA (instanceRef pdp_ram_14_0_7))
+              (portRef OCEA (instanceRef pdp_ram_14_1_6))
+              (portRef CEA (instanceRef pdp_ram_14_1_6))
+              (portRef OCEA (instanceRef pdp_ram_14_2_5))
+              (portRef CEA (instanceRef pdp_ram_14_2_5))
+              (portRef OCEA (instanceRef pdp_ram_14_3_4))
+              (portRef CEA (instanceRef pdp_ram_14_3_4))
+              (portRef OCEA (instanceRef pdp_ram_15_0_3))
+              (portRef CEA (instanceRef pdp_ram_15_0_3))
+              (portRef OCEA (instanceRef pdp_ram_15_1_2))
+              (portRef CEA (instanceRef pdp_ram_15_1_2))
+              (portRef OCEA (instanceRef pdp_ram_15_2_1))
+              (portRef CEA (instanceRef pdp_ram_15_2_1))
+              (portRef OCEA (instanceRef pdp_ram_15_3_0))
+              (portRef CEA (instanceRef pdp_ram_15_3_0))
+              (portRef SP (instanceRef FF_88))
+              (portRef SP (instanceRef FF_87))
+              (portRef SP (instanceRef FF_86))
+              (portRef SP (instanceRef FF_85))
+              (portRef SP (instanceRef FF_84))
+              (portRef SP (instanceRef FF_83))
+              (portRef SP (instanceRef FF_82))
+              (portRef SP (instanceRef FF_81))
+              (portRef SP (instanceRef FF_80))
+              (portRef SP (instanceRef FF_79))
+              (portRef SP (instanceRef FF_78))
+              (portRef SP (instanceRef FF_77))
+              (portRef SP (instanceRef FF_76))
+              (portRef SP (instanceRef FF_75))
+              (portRef SP (instanceRef FF_74))
+              (portRef SP (instanceRef FF_73))
+              (portRef SP (instanceRef FF_56))
+              (portRef SP (instanceRef FF_55))
+              (portRef SP (instanceRef FF_54))
+              (portRef SP (instanceRef FF_53))
+              (portRef SP (instanceRef FF_52))
+              (portRef SP (instanceRef FF_51))
+              (portRef SP (instanceRef FF_50))
+              (portRef SP (instanceRef FF_49))
+              (portRef SP (instanceRef FF_48))
+              (portRef SP (instanceRef FF_47))
+              (portRef SP (instanceRef FF_46))
+              (portRef SP (instanceRef FF_45))
+              (portRef SP (instanceRef FF_44))
+              (portRef SP (instanceRef FF_43))
+              (portRef SP (instanceRef FF_42))
+              (portRef SP (instanceRef FF_41))
+              (portRef B0 (instanceRef g_cmp_0))
+              (portRef B1 (instanceRef g_cmp_0))
+              (portRef B0 (instanceRef g_cmp_1))
+              (portRef B1 (instanceRef g_cmp_1))
+              (portRef B0 (instanceRef g_cmp_2))
+              (portRef B1 (instanceRef g_cmp_2))
+              (portRef B0 (instanceRef g_cmp_3))
+              (portRef B1 (instanceRef g_cmp_3))
+              (portRef B0 (instanceRef g_cmp_4))
+              (portRef B1 (instanceRef g_cmp_4))
+              (portRef B0 (instanceRef g_cmp_5))
+              (portRef B1 (instanceRef g_cmp_5))
+              (portRef B0 (instanceRef g_cmp_6))
+              (portRef B1 (instanceRef g_cmp_6))
+              (portRef B0 (instanceRef g_cmp_7))
+              (portRef B1 (instanceRef af_set_cmp_ci_a))))
+          (net x
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_ci_a))
+              (portRef CIN (instanceRef bdcnt_bctr_cia))
+              (portRef CIN (instanceRef e_cmp_ci_a))
+              (portRef CIN (instanceRef g_cmp_ci_a))
+              (portRef CIN (instanceRef w_ctr_cia))
+              (portRef CIN (instanceRef r_ctr_cia))
+              (portRef CIN (instanceRef precin_inst1073))))
+          (net cmp_ci_2
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_0))
+              (portRef COUT (instanceRef af_set_cmp_ci_a))))
+          (net wcnt_reg_0
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_0))
+              (portRef Q (instanceRef FF_16))))
+          (net wcnt_reg_1
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_0))
+              (portRef Q (instanceRef FF_15))))
+          (net co0_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_1))
+              (portRef COUT (instanceRef af_set_cmp_0))))
+          (net wcnt_reg_2
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_1))
+              (portRef Q (instanceRef FF_14))))
+          (net wcnt_reg_3
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_1))
+              (portRef Q (instanceRef FF_13))))
+          (net co1_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_2))
+              (portRef COUT (instanceRef af_set_cmp_1))))
+          (net wcnt_reg_4
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_2))
+              (portRef Q (instanceRef FF_12))))
+          (net wcnt_reg_5
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_2))
+              (portRef Q (instanceRef FF_11))))
+          (net co2_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_3))
+              (portRef COUT (instanceRef af_set_cmp_2))))
+          (net wcnt_reg_6
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_3))
+              (portRef Q (instanceRef FF_10))))
+          (net wcnt_reg_7
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_3))
+              (portRef Q (instanceRef FF_9))))
+          (net co3_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_4))
+              (portRef COUT (instanceRef af_set_cmp_3))))
+          (net wcnt_reg_8
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_4))
+              (portRef Q (instanceRef FF_8))))
+          (net wcnt_reg_9
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_4))
+              (portRef Q (instanceRef FF_7))))
+          (net co4_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_5))
+              (portRef COUT (instanceRef af_set_cmp_4))))
+          (net wcnt_reg_10
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_5))
+              (portRef Q (instanceRef FF_6))))
+          (net wcnt_reg_11
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_5))
+              (portRef Q (instanceRef FF_5))))
+          (net co5_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_6))
+              (portRef COUT (instanceRef af_set_cmp_5))))
+          (net wcnt_reg_12
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_6))
+              (portRef Q (instanceRef FF_4))))
+          (net wcnt_reg_13
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_6))
+              (portRef Q (instanceRef FF_3))))
+          (net co6_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_7))
+              (portRef COUT (instanceRef af_set_cmp_6))))
+          (net wcnt_reg_14
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_7))
+              (portRef Q (instanceRef FF_2))))
+          (net wcnt_reg_15
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_7))
+              (portRef Q (instanceRef FF_1))))
+          (net af_set
+            (joined
+              (portRef S0 (instanceRef a2))
+              (portRef D (instanceRef FF_0))))
+          (net scuba_vhi
+            (joined
+              (portRef Z (instanceRef scuba_vhi_inst))
+              (portRef OCEB (instanceRef pdp_ram_0_0_63))
+              (portRef WEA (instanceRef pdp_ram_0_0_63))
+              (portRef OCEB (instanceRef pdp_ram_0_1_62))
+              (portRef WEA (instanceRef pdp_ram_0_1_62))
+              (portRef OCEB (instanceRef pdp_ram_0_2_61))
+              (portRef WEA (instanceRef pdp_ram_0_2_61))
+              (portRef OCEB (instanceRef pdp_ram_0_3_60))
+              (portRef WEA (instanceRef pdp_ram_0_3_60))
+              (portRef OCEB (instanceRef pdp_ram_1_0_59))
+              (portRef WEA (instanceRef pdp_ram_1_0_59))
+              (portRef OCEB (instanceRef pdp_ram_1_1_58))
+              (portRef WEA (instanceRef pdp_ram_1_1_58))
+              (portRef OCEB (instanceRef pdp_ram_1_2_57))
+              (portRef WEA (instanceRef pdp_ram_1_2_57))
+              (portRef OCEB (instanceRef pdp_ram_1_3_56))
+              (portRef WEA (instanceRef pdp_ram_1_3_56))
+              (portRef OCEB (instanceRef pdp_ram_2_0_55))
+              (portRef WEA (instanceRef pdp_ram_2_0_55))
+              (portRef OCEB (instanceRef pdp_ram_2_1_54))
+              (portRef WEA (instanceRef pdp_ram_2_1_54))
+              (portRef OCEB (instanceRef pdp_ram_2_2_53))
+              (portRef WEA (instanceRef pdp_ram_2_2_53))
+              (portRef OCEB (instanceRef pdp_ram_2_3_52))
+              (portRef WEA (instanceRef pdp_ram_2_3_52))
+              (portRef OCEB (instanceRef pdp_ram_3_0_51))
+              (portRef WEA (instanceRef pdp_ram_3_0_51))
+              (portRef OCEB (instanceRef pdp_ram_3_1_50))
+              (portRef WEA (instanceRef pdp_ram_3_1_50))
+              (portRef OCEB (instanceRef pdp_ram_3_2_49))
+              (portRef WEA (instanceRef pdp_ram_3_2_49))
+              (portRef OCEB (instanceRef pdp_ram_3_3_48))
+              (portRef WEA (instanceRef pdp_ram_3_3_48))
+              (portRef OCEB (instanceRef pdp_ram_4_0_47))
+              (portRef WEA (instanceRef pdp_ram_4_0_47))
+              (portRef OCEB (instanceRef pdp_ram_4_1_46))
+              (portRef WEA (instanceRef pdp_ram_4_1_46))
+              (portRef OCEB (instanceRef pdp_ram_4_2_45))
+              (portRef WEA (instanceRef pdp_ram_4_2_45))
+              (portRef OCEB (instanceRef pdp_ram_4_3_44))
+              (portRef WEA (instanceRef pdp_ram_4_3_44))
+              (portRef OCEB (instanceRef pdp_ram_5_0_43))
+              (portRef WEA (instanceRef pdp_ram_5_0_43))
+              (portRef OCEB (instanceRef pdp_ram_5_1_42))
+              (portRef WEA (instanceRef pdp_ram_5_1_42))
+              (portRef OCEB (instanceRef pdp_ram_5_2_41))
+              (portRef WEA (instanceRef pdp_ram_5_2_41))
+              (portRef OCEB (instanceRef pdp_ram_5_3_40))
+              (portRef WEA (instanceRef pdp_ram_5_3_40))
+              (portRef OCEB (instanceRef pdp_ram_6_0_39))
+              (portRef WEA (instanceRef pdp_ram_6_0_39))
+              (portRef OCEB (instanceRef pdp_ram_6_1_38))
+              (portRef WEA (instanceRef pdp_ram_6_1_38))
+              (portRef OCEB (instanceRef pdp_ram_6_2_37))
+              (portRef WEA (instanceRef pdp_ram_6_2_37))
+              (portRef OCEB (instanceRef pdp_ram_6_3_36))
+              (portRef WEA (instanceRef pdp_ram_6_3_36))
+              (portRef OCEB (instanceRef pdp_ram_7_0_35))
+              (portRef WEA (instanceRef pdp_ram_7_0_35))
+              (portRef OCEB (instanceRef pdp_ram_7_1_34))
+              (portRef WEA (instanceRef pdp_ram_7_1_34))
+              (portRef OCEB (instanceRef pdp_ram_7_2_33))
+              (portRef WEA (instanceRef pdp_ram_7_2_33))
+              (portRef OCEB (instanceRef pdp_ram_7_3_32))
+              (portRef WEA (instanceRef pdp_ram_7_3_32))
+              (portRef OCEB (instanceRef pdp_ram_8_0_31))
+              (portRef WEA (instanceRef pdp_ram_8_0_31))
+              (portRef OCEB (instanceRef pdp_ram_8_1_30))
+              (portRef WEA (instanceRef pdp_ram_8_1_30))
+              (portRef OCEB (instanceRef pdp_ram_8_2_29))
+              (portRef WEA (instanceRef pdp_ram_8_2_29))
+              (portRef OCEB (instanceRef pdp_ram_8_3_28))
+              (portRef WEA (instanceRef pdp_ram_8_3_28))
+              (portRef OCEB (instanceRef pdp_ram_9_0_27))
+              (portRef WEA (instanceRef pdp_ram_9_0_27))
+              (portRef OCEB (instanceRef pdp_ram_9_1_26))
+              (portRef WEA (instanceRef pdp_ram_9_1_26))
+              (portRef OCEB (instanceRef pdp_ram_9_2_25))
+              (portRef WEA (instanceRef pdp_ram_9_2_25))
+              (portRef OCEB (instanceRef pdp_ram_9_3_24))
+              (portRef WEA (instanceRef pdp_ram_9_3_24))
+              (portRef OCEB (instanceRef pdp_ram_10_0_23))
+              (portRef WEA (instanceRef pdp_ram_10_0_23))
+              (portRef OCEB (instanceRef pdp_ram_10_1_22))
+              (portRef WEA (instanceRef pdp_ram_10_1_22))
+              (portRef OCEB (instanceRef pdp_ram_10_2_21))
+              (portRef WEA (instanceRef pdp_ram_10_2_21))
+              (portRef OCEB (instanceRef pdp_ram_10_3_20))
+              (portRef WEA (instanceRef pdp_ram_10_3_20))
+              (portRef OCEB (instanceRef pdp_ram_11_0_19))
+              (portRef WEA (instanceRef pdp_ram_11_0_19))
+              (portRef OCEB (instanceRef pdp_ram_11_1_18))
+              (portRef WEA (instanceRef pdp_ram_11_1_18))
+              (portRef OCEB (instanceRef pdp_ram_11_2_17))
+              (portRef WEA (instanceRef pdp_ram_11_2_17))
+              (portRef OCEB (instanceRef pdp_ram_11_3_16))
+              (portRef WEA (instanceRef pdp_ram_11_3_16))
+              (portRef OCEB (instanceRef pdp_ram_12_0_15))
+              (portRef WEA (instanceRef pdp_ram_12_0_15))
+              (portRef OCEB (instanceRef pdp_ram_12_1_14))
+              (portRef WEA (instanceRef pdp_ram_12_1_14))
+              (portRef OCEB (instanceRef pdp_ram_12_2_13))
+              (portRef WEA (instanceRef pdp_ram_12_2_13))
+              (portRef OCEB (instanceRef pdp_ram_12_3_12))
+              (portRef WEA (instanceRef pdp_ram_12_3_12))
+              (portRef OCEB (instanceRef pdp_ram_13_0_11))
+              (portRef WEA (instanceRef pdp_ram_13_0_11))
+              (portRef OCEB (instanceRef pdp_ram_13_1_10))
+              (portRef WEA (instanceRef pdp_ram_13_1_10))
+              (portRef OCEB (instanceRef pdp_ram_13_2_9))
+              (portRef WEA (instanceRef pdp_ram_13_2_9))
+              (portRef OCEB (instanceRef pdp_ram_13_3_8))
+              (portRef WEA (instanceRef pdp_ram_13_3_8))
+              (portRef OCEB (instanceRef pdp_ram_14_0_7))
+              (portRef WEA (instanceRef pdp_ram_14_0_7))
+              (portRef OCEB (instanceRef pdp_ram_14_1_6))
+              (portRef WEA (instanceRef pdp_ram_14_1_6))
+              (portRef OCEB (instanceRef pdp_ram_14_2_5))
+              (portRef WEA (instanceRef pdp_ram_14_2_5))
+              (portRef OCEB (instanceRef pdp_ram_14_3_4))
+              (portRef WEA (instanceRef pdp_ram_14_3_4))
+              (portRef OCEB (instanceRef pdp_ram_15_0_3))
+              (portRef WEA (instanceRef pdp_ram_15_0_3))
+              (portRef OCEB (instanceRef pdp_ram_15_1_2))
+              (portRef WEA (instanceRef pdp_ram_15_1_2))
+              (portRef OCEB (instanceRef pdp_ram_15_2_1))
+              (portRef WEA (instanceRef pdp_ram_15_2_1))
+              (portRef OCEB (instanceRef pdp_ram_15_3_0))
+              (portRef WEA (instanceRef pdp_ram_15_3_0))
+              (portRef C1 (instanceRef bdcnt_bctr_cia))
+              (portRef C0 (instanceRef bdcnt_bctr_cia))
+              (portRef D1 (instanceRef bdcnt_bctr_cia))
+              (portRef D0 (instanceRef bdcnt_bctr_cia))
+              (portRef D1 (instanceRef bdcnt_bctr_0))
+              (portRef D0 (instanceRef bdcnt_bctr_0))
+              (portRef C1 (instanceRef bdcnt_bctr_0))
+              (portRef C0 (instanceRef bdcnt_bctr_0))
+              (portRef D1 (instanceRef bdcnt_bctr_1))
+              (portRef D0 (instanceRef bdcnt_bctr_1))
+              (portRef C1 (instanceRef bdcnt_bctr_1))
+              (portRef C0 (instanceRef bdcnt_bctr_1))
+              (portRef D1 (instanceRef bdcnt_bctr_2))
+              (portRef D0 (instanceRef bdcnt_bctr_2))
+              (portRef C1 (instanceRef bdcnt_bctr_2))
+              (portRef C0 (instanceRef bdcnt_bctr_2))
+              (portRef D1 (instanceRef bdcnt_bctr_3))
+              (portRef D0 (instanceRef bdcnt_bctr_3))
+              (portRef C1 (instanceRef bdcnt_bctr_3))
+              (portRef C0 (instanceRef bdcnt_bctr_3))
+              (portRef D1 (instanceRef bdcnt_bctr_4))
+              (portRef D0 (instanceRef bdcnt_bctr_4))
+              (portRef C1 (instanceRef bdcnt_bctr_4))
+              (portRef C0 (instanceRef bdcnt_bctr_4))
+              (portRef D1 (instanceRef bdcnt_bctr_5))
+              (portRef D0 (instanceRef bdcnt_bctr_5))
+              (portRef C1 (instanceRef bdcnt_bctr_5))
+              (portRef C0 (instanceRef bdcnt_bctr_5))
+              (portRef D1 (instanceRef bdcnt_bctr_6))
+              (portRef D0 (instanceRef bdcnt_bctr_6))
+              (portRef C1 (instanceRef bdcnt_bctr_6))
+              (portRef C0 (instanceRef bdcnt_bctr_6))
+              (portRef D1 (instanceRef bdcnt_bctr_7))
+              (portRef D0 (instanceRef bdcnt_bctr_7))
+              (portRef C1 (instanceRef bdcnt_bctr_7))
+              (portRef C0 (instanceRef bdcnt_bctr_7))
+              (portRef C1 (instanceRef e_cmp_ci_a))
+              (portRef C0 (instanceRef e_cmp_ci_a))
+              (portRef D1 (instanceRef e_cmp_ci_a))
+              (portRef D0 (instanceRef e_cmp_ci_a))
+              (portRef B1 (instanceRef e_cmp_ci_a))
+              (portRef B0 (instanceRef e_cmp_ci_a))
+              (portRef A1 (instanceRef e_cmp_ci_a))
+              (portRef A0 (instanceRef e_cmp_ci_a))
+              (portRef D1 (instanceRef e_cmp_0))
+              (portRef D0 (instanceRef e_cmp_0))
+              (portRef C1 (instanceRef e_cmp_0))
+              (portRef C0 (instanceRef e_cmp_0))
+              (portRef D1 (instanceRef e_cmp_1))
+              (portRef D0 (instanceRef e_cmp_1))
+              (portRef C1 (instanceRef e_cmp_1))
+              (portRef C0 (instanceRef e_cmp_1))
+              (portRef D1 (instanceRef e_cmp_2))
+              (portRef D0 (instanceRef e_cmp_2))
+              (portRef C1 (instanceRef e_cmp_2))
+              (portRef C0 (instanceRef e_cmp_2))
+              (portRef D1 (instanceRef e_cmp_3))
+              (portRef D0 (instanceRef e_cmp_3))
+              (portRef C1 (instanceRef e_cmp_3))
+              (portRef C0 (instanceRef e_cmp_3))
+              (portRef D1 (instanceRef e_cmp_4))
+              (portRef D0 (instanceRef e_cmp_4))
+              (portRef C1 (instanceRef e_cmp_4))
+              (portRef C0 (instanceRef e_cmp_4))
+              (portRef D1 (instanceRef e_cmp_5))
+              (portRef D0 (instanceRef e_cmp_5))
+              (portRef C1 (instanceRef e_cmp_5))
+              (portRef C0 (instanceRef e_cmp_5))
+              (portRef D1 (instanceRef e_cmp_6))
+              (portRef D0 (instanceRef e_cmp_6))
+              (portRef C1 (instanceRef e_cmp_6))
+              (portRef C0 (instanceRef e_cmp_6))
+              (portRef D1 (instanceRef e_cmp_7))
+              (portRef D0 (instanceRef e_cmp_7))
+              (portRef C1 (instanceRef e_cmp_7))
+              (portRef C0 (instanceRef e_cmp_7))
+              (portRef C1 (instanceRef a0))
+              (portRef C0 (instanceRef a0))
+              (portRef D1 (instanceRef a0))
+              (portRef D0 (instanceRef a0))
+              (portRef C1 (instanceRef g_cmp_ci_a))
+              (portRef C0 (instanceRef g_cmp_ci_a))
+              (portRef D1 (instanceRef g_cmp_ci_a))
+              (portRef D0 (instanceRef g_cmp_ci_a))
+              (portRef B1 (instanceRef g_cmp_ci_a))
+              (portRef B0 (instanceRef g_cmp_ci_a))
+              (portRef A1 (instanceRef g_cmp_ci_a))
+              (portRef A0 (instanceRef g_cmp_ci_a))
+              (portRef D1 (instanceRef g_cmp_0))
+              (portRef D0 (instanceRef g_cmp_0))
+              (portRef C1 (instanceRef g_cmp_0))
+              (portRef C0 (instanceRef g_cmp_0))
+              (portRef D1 (instanceRef g_cmp_1))
+              (portRef D0 (instanceRef g_cmp_1))
+              (portRef C1 (instanceRef g_cmp_1))
+              (portRef C0 (instanceRef g_cmp_1))
+              (portRef D1 (instanceRef g_cmp_2))
+              (portRef D0 (instanceRef g_cmp_2))
+              (portRef C1 (instanceRef g_cmp_2))
+              (portRef C0 (instanceRef g_cmp_2))
+              (portRef D1 (instanceRef g_cmp_3))
+              (portRef D0 (instanceRef g_cmp_3))
+              (portRef C1 (instanceRef g_cmp_3))
+              (portRef C0 (instanceRef g_cmp_3))
+              (portRef D1 (instanceRef g_cmp_4))
+              (portRef D0 (instanceRef g_cmp_4))
+              (portRef C1 (instanceRef g_cmp_4))
+              (portRef C0 (instanceRef g_cmp_4))
+              (portRef D1 (instanceRef g_cmp_5))
+              (portRef D0 (instanceRef g_cmp_5))
+              (portRef C1 (instanceRef g_cmp_5))
+              (portRef C0 (instanceRef g_cmp_5))
+              (portRef D1 (instanceRef g_cmp_6))
+              (portRef D0 (instanceRef g_cmp_6))
+              (portRef C1 (instanceRef g_cmp_6))
+              (portRef C0 (instanceRef g_cmp_6))
+              (portRef D1 (instanceRef g_cmp_7))
+              (portRef D0 (instanceRef g_cmp_7))
+              (portRef C1 (instanceRef g_cmp_7))
+              (portRef C0 (instanceRef g_cmp_7))
+              (portRef C1 (instanceRef a1))
+              (portRef C0 (instanceRef a1))
+              (portRef D1 (instanceRef a1))
+              (portRef D0 (instanceRef a1))
+              (portRef C1 (instanceRef w_ctr_cia))
+              (portRef C0 (instanceRef w_ctr_cia))
+              (portRef D1 (instanceRef w_ctr_cia))
+              (portRef D0 (instanceRef w_ctr_cia))
+              (portRef B1 (instanceRef w_ctr_cia))
+              (portRef A1 (instanceRef w_ctr_cia))
+              (portRef D1 (instanceRef w_ctr_0))
+              (portRef D0 (instanceRef w_ctr_0))
+              (portRef C1 (instanceRef w_ctr_0))
+              (portRef C0 (instanceRef w_ctr_0))
+              (portRef D1 (instanceRef w_ctr_1))
+              (portRef D0 (instanceRef w_ctr_1))
+              (portRef C1 (instanceRef w_ctr_1))
+              (portRef C0 (instanceRef w_ctr_1))
+              (portRef D1 (instanceRef w_ctr_2))
+              (portRef D0 (instanceRef w_ctr_2))
+              (portRef C1 (instanceRef w_ctr_2))
+              (portRef C0 (instanceRef w_ctr_2))
+              (portRef D1 (instanceRef w_ctr_3))
+              (portRef D0 (instanceRef w_ctr_3))
+              (portRef C1 (instanceRef w_ctr_3))
+              (portRef C0 (instanceRef w_ctr_3))
+              (portRef D1 (instanceRef w_ctr_4))
+              (portRef D0 (instanceRef w_ctr_4))
+              (portRef C1 (instanceRef w_ctr_4))
+              (portRef C0 (instanceRef w_ctr_4))
+              (portRef D1 (instanceRef w_ctr_5))
+              (portRef D0 (instanceRef w_ctr_5))
+              (portRef C1 (instanceRef w_ctr_5))
+              (portRef C0 (instanceRef w_ctr_5))
+              (portRef D1 (instanceRef w_ctr_6))
+              (portRef D0 (instanceRef w_ctr_6))
+              (portRef C1 (instanceRef w_ctr_6))
+              (portRef C0 (instanceRef w_ctr_6))
+              (portRef D1 (instanceRef w_ctr_7))
+              (portRef D0 (instanceRef w_ctr_7))
+              (portRef C1 (instanceRef w_ctr_7))
+              (portRef C0 (instanceRef w_ctr_7))
+              (portRef C1 (instanceRef r_ctr_cia))
+              (portRef C0 (instanceRef r_ctr_cia))
+              (portRef D1 (instanceRef r_ctr_cia))
+              (portRef D0 (instanceRef r_ctr_cia))
+              (portRef B1 (instanceRef r_ctr_cia))
+              (portRef A1 (instanceRef r_ctr_cia))
+              (portRef D1 (instanceRef r_ctr_0))
+              (portRef D0 (instanceRef r_ctr_0))
+              (portRef C1 (instanceRef r_ctr_0))
+              (portRef C0 (instanceRef r_ctr_0))
+              (portRef D1 (instanceRef r_ctr_1))
+              (portRef D0 (instanceRef r_ctr_1))
+              (portRef C1 (instanceRef r_ctr_1))
+              (portRef C0 (instanceRef r_ctr_1))
+              (portRef D1 (instanceRef r_ctr_2))
+              (portRef D0 (instanceRef r_ctr_2))
+              (portRef C1 (instanceRef r_ctr_2))
+              (portRef C0 (instanceRef r_ctr_2))
+              (portRef D1 (instanceRef r_ctr_3))
+              (portRef D0 (instanceRef r_ctr_3))
+              (portRef C1 (instanceRef r_ctr_3))
+              (portRef C0 (instanceRef r_ctr_3))
+              (portRef D1 (instanceRef r_ctr_4))
+              (portRef D0 (instanceRef r_ctr_4))
+              (portRef C1 (instanceRef r_ctr_4))
+              (portRef C0 (instanceRef r_ctr_4))
+              (portRef D1 (instanceRef r_ctr_5))
+              (portRef D0 (instanceRef r_ctr_5))
+              (portRef C1 (instanceRef r_ctr_5))
+              (portRef C0 (instanceRef r_ctr_5))
+              (portRef D1 (instanceRef r_ctr_6))
+              (portRef D0 (instanceRef r_ctr_6))
+              (portRef C1 (instanceRef r_ctr_6))
+              (portRef C0 (instanceRef r_ctr_6))
+              (portRef D1 (instanceRef r_ctr_7))
+              (portRef D0 (instanceRef r_ctr_7))
+              (portRef C1 (instanceRef r_ctr_7))
+              (portRef C0 (instanceRef r_ctr_7))
+              (portRef C1 (instanceRef precin_inst1073))
+              (portRef C0 (instanceRef precin_inst1073))
+              (portRef D1 (instanceRef precin_inst1073))
+              (portRef D0 (instanceRef precin_inst1073))
+              (portRef B1 (instanceRef precin_inst1073))
+              (portRef B0 (instanceRef precin_inst1073))
+              (portRef A1 (instanceRef precin_inst1073))
+              (portRef A0 (instanceRef precin_inst1073))
+              (portRef C1 (instanceRef wcnt_0))
+              (portRef C0 (instanceRef wcnt_0))
+              (portRef D1 (instanceRef wcnt_0))
+              (portRef D0 (instanceRef wcnt_0))
+              (portRef C1 (instanceRef wcnt_1))
+              (portRef C0 (instanceRef wcnt_1))
+              (portRef D1 (instanceRef wcnt_1))
+              (portRef D0 (instanceRef wcnt_1))
+              (portRef C1 (instanceRef wcnt_2))
+              (portRef C0 (instanceRef wcnt_2))
+              (portRef D1 (instanceRef wcnt_2))
+              (portRef D0 (instanceRef wcnt_2))
+              (portRef C1 (instanceRef wcnt_3))
+              (portRef C0 (instanceRef wcnt_3))
+              (portRef D1 (instanceRef wcnt_3))
+              (portRef D0 (instanceRef wcnt_3))
+              (portRef C1 (instanceRef wcnt_4))
+              (portRef C0 (instanceRef wcnt_4))
+              (portRef D1 (instanceRef wcnt_4))
+              (portRef D0 (instanceRef wcnt_4))
+              (portRef C1 (instanceRef wcnt_5))
+              (portRef C0 (instanceRef wcnt_5))
+              (portRef D1 (instanceRef wcnt_5))
+              (portRef D0 (instanceRef wcnt_5))
+              (portRef C1 (instanceRef wcnt_6))
+              (portRef C0 (instanceRef wcnt_6))
+              (portRef D1 (instanceRef wcnt_6))
+              (portRef D0 (instanceRef wcnt_6))
+              (portRef C1 (instanceRef wcnt_7))
+              (portRef C0 (instanceRef wcnt_7))
+              (portRef D1 (instanceRef wcnt_7))
+              (portRef D0 (instanceRef wcnt_7))
+              (portRef C1 (instanceRef wcnt_8))
+              (portRef C0 (instanceRef wcnt_8))
+              (portRef D1 (instanceRef wcnt_8))
+              (portRef D0 (instanceRef wcnt_8))
+              (portRef C1 (instanceRef af_set_cmp_ci_a))
+              (portRef C0 (instanceRef af_set_cmp_ci_a))
+              (portRef D1 (instanceRef af_set_cmp_ci_a))
+              (portRef D0 (instanceRef af_set_cmp_ci_a))
+              (portRef D1 (instanceRef af_set_cmp_0))
+              (portRef D0 (instanceRef af_set_cmp_0))
+              (portRef C1 (instanceRef af_set_cmp_0))
+              (portRef C0 (instanceRef af_set_cmp_0))
+              (portRef D1 (instanceRef af_set_cmp_1))
+              (portRef D0 (instanceRef af_set_cmp_1))
+              (portRef C1 (instanceRef af_set_cmp_1))
+              (portRef C0 (instanceRef af_set_cmp_1))
+              (portRef D1 (instanceRef af_set_cmp_2))
+              (portRef D0 (instanceRef af_set_cmp_2))
+              (portRef C1 (instanceRef af_set_cmp_2))
+              (portRef C0 (instanceRef af_set_cmp_2))
+              (portRef D1 (instanceRef af_set_cmp_3))
+              (portRef D0 (instanceRef af_set_cmp_3))
+              (portRef C1 (instanceRef af_set_cmp_3))
+              (portRef C0 (instanceRef af_set_cmp_3))
+              (portRef D1 (instanceRef af_set_cmp_4))
+              (portRef D0 (instanceRef af_set_cmp_4))
+              (portRef C1 (instanceRef af_set_cmp_4))
+              (portRef C0 (instanceRef af_set_cmp_4))
+              (portRef D1 (instanceRef af_set_cmp_5))
+              (portRef D0 (instanceRef af_set_cmp_5))
+              (portRef C1 (instanceRef af_set_cmp_5))
+              (portRef C0 (instanceRef af_set_cmp_5))
+              (portRef D1 (instanceRef af_set_cmp_6))
+              (portRef D0 (instanceRef af_set_cmp_6))
+              (portRef C1 (instanceRef af_set_cmp_6))
+              (portRef C0 (instanceRef af_set_cmp_6))
+              (portRef D1 (instanceRef af_set_cmp_7))
+              (portRef D0 (instanceRef af_set_cmp_7))
+              (portRef C1 (instanceRef af_set_cmp_7))
+              (portRef C0 (instanceRef af_set_cmp_7))
+              (portRef C1 (instanceRef a2))
+              (portRef C0 (instanceRef a2))
+              (portRef D1 (instanceRef a2))
+              (portRef D0 (instanceRef a2))))
+          (net scuba_vlo
+            (joined
+              (portRef Z (instanceRef scuba_vlo_inst))
+              (portRef AD3 (instanceRef LUT4_129))
+              (portRef AD3 (instanceRef LUT4_128))
+              (portRef CSB2 (instanceRef pdp_ram_0_0_63))
+              (portRef CSA2 (instanceRef pdp_ram_0_0_63))
+              (portRef CSB1 (instanceRef pdp_ram_0_0_63))
+              (portRef CSA1 (instanceRef pdp_ram_0_0_63))
+              (portRef WEB (instanceRef pdp_ram_0_0_63))
+              (portRef ADB2 (instanceRef pdp_ram_0_0_63))
+              (portRef ADA2 (instanceRef pdp_ram_0_0_63))
+              (portRef ADB1 (instanceRef pdp_ram_0_0_63))
+              (portRef ADA1 (instanceRef pdp_ram_0_0_63))
+              (portRef ADB0 (instanceRef pdp_ram_0_0_63))
+              (portRef ADA0 (instanceRef pdp_ram_0_0_63))
+              (portRef DIB17 (instanceRef pdp_ram_0_0_63))
+              (portRef DIA17 (instanceRef pdp_ram_0_0_63))
+              (portRef DIB16 (instanceRef pdp_ram_0_0_63))
+              (portRef DIA16 (instanceRef pdp_ram_0_0_63))
+              (portRef DIB15 (instanceRef pdp_ram_0_0_63))
+              (portRef DIA15 (instanceRef pdp_ram_0_0_63))
+              (portRef DIB14 (instanceRef pdp_ram_0_0_63))
+              (portRef DIA14 (instanceRef pdp_ram_0_0_63))
+              (portRef DIB13 (instanceRef pdp_ram_0_0_63))
+              (portRef DIA13 (instanceRef pdp_ram_0_0_63))
+              (portRef DIB12 (instanceRef pdp_ram_0_0_63))
+              (portRef DIA12 (instanceRef pdp_ram_0_0_63))
+              (portRef DIB11 (instanceRef pdp_ram_0_0_63))
+              (portRef DIA11 (instanceRef pdp_ram_0_0_63))
+              (portRef DIB10 (instanceRef pdp_ram_0_0_63))
+              (portRef DIA10 (instanceRef pdp_ram_0_0_63))
+              (portRef DIB9 (instanceRef pdp_ram_0_0_63))
+              (portRef DIA9 (instanceRef pdp_ram_0_0_63))
+              (portRef DIB8 (instanceRef pdp_ram_0_0_63))
+              (portRef DIB7 (instanceRef pdp_ram_0_0_63))
+              (portRef DIB6 (instanceRef pdp_ram_0_0_63))
+              (portRef DIB5 (instanceRef pdp_ram_0_0_63))
+              (portRef DIB4 (instanceRef pdp_ram_0_0_63))
+              (portRef DIB3 (instanceRef pdp_ram_0_0_63))
+              (portRef DIB2 (instanceRef pdp_ram_0_0_63))
+              (portRef DIB1 (instanceRef pdp_ram_0_0_63))
+              (portRef DIB0 (instanceRef pdp_ram_0_0_63))
+              (portRef CSB2 (instanceRef pdp_ram_0_1_62))
+              (portRef CSA2 (instanceRef pdp_ram_0_1_62))
+              (portRef CSB1 (instanceRef pdp_ram_0_1_62))
+              (portRef CSA1 (instanceRef pdp_ram_0_1_62))
+              (portRef WEB (instanceRef pdp_ram_0_1_62))
+              (portRef ADB2 (instanceRef pdp_ram_0_1_62))
+              (portRef ADA2 (instanceRef pdp_ram_0_1_62))
+              (portRef ADB1 (instanceRef pdp_ram_0_1_62))
+              (portRef ADA1 (instanceRef pdp_ram_0_1_62))
+              (portRef ADB0 (instanceRef pdp_ram_0_1_62))
+              (portRef ADA0 (instanceRef pdp_ram_0_1_62))
+              (portRef DIB17 (instanceRef pdp_ram_0_1_62))
+              (portRef DIA17 (instanceRef pdp_ram_0_1_62))
+              (portRef DIB16 (instanceRef pdp_ram_0_1_62))
+              (portRef DIA16 (instanceRef pdp_ram_0_1_62))
+              (portRef DIB15 (instanceRef pdp_ram_0_1_62))
+              (portRef DIA15 (instanceRef pdp_ram_0_1_62))
+              (portRef DIB14 (instanceRef pdp_ram_0_1_62))
+              (portRef DIA14 (instanceRef pdp_ram_0_1_62))
+              (portRef DIB13 (instanceRef pdp_ram_0_1_62))
+              (portRef DIA13 (instanceRef pdp_ram_0_1_62))
+              (portRef DIB12 (instanceRef pdp_ram_0_1_62))
+              (portRef DIA12 (instanceRef pdp_ram_0_1_62))
+              (portRef DIB11 (instanceRef pdp_ram_0_1_62))
+              (portRef DIA11 (instanceRef pdp_ram_0_1_62))
+              (portRef DIB10 (instanceRef pdp_ram_0_1_62))
+              (portRef DIA10 (instanceRef pdp_ram_0_1_62))
+              (portRef DIB9 (instanceRef pdp_ram_0_1_62))
+              (portRef DIA9 (instanceRef pdp_ram_0_1_62))
+              (portRef DIB8 (instanceRef pdp_ram_0_1_62))
+              (portRef DIB7 (instanceRef pdp_ram_0_1_62))
+              (portRef DIB6 (instanceRef pdp_ram_0_1_62))
+              (portRef DIB5 (instanceRef pdp_ram_0_1_62))
+              (portRef DIB4 (instanceRef pdp_ram_0_1_62))
+              (portRef DIB3 (instanceRef pdp_ram_0_1_62))
+              (portRef DIB2 (instanceRef pdp_ram_0_1_62))
+              (portRef DIB1 (instanceRef pdp_ram_0_1_62))
+              (portRef DIB0 (instanceRef pdp_ram_0_1_62))
+              (portRef CSB2 (instanceRef pdp_ram_0_2_61))
+              (portRef CSA2 (instanceRef pdp_ram_0_2_61))
+              (portRef CSB1 (instanceRef pdp_ram_0_2_61))
+              (portRef CSA1 (instanceRef pdp_ram_0_2_61))
+              (portRef WEB (instanceRef pdp_ram_0_2_61))
+              (portRef ADB2 (instanceRef pdp_ram_0_2_61))
+              (portRef ADA2 (instanceRef pdp_ram_0_2_61))
+              (portRef ADB1 (instanceRef pdp_ram_0_2_61))
+              (portRef ADA1 (instanceRef pdp_ram_0_2_61))
+              (portRef ADB0 (instanceRef pdp_ram_0_2_61))
+              (portRef ADA0 (instanceRef pdp_ram_0_2_61))
+              (portRef DIB17 (instanceRef pdp_ram_0_2_61))
+              (portRef DIA17 (instanceRef pdp_ram_0_2_61))
+              (portRef DIB16 (instanceRef pdp_ram_0_2_61))
+              (portRef DIA16 (instanceRef pdp_ram_0_2_61))
+              (portRef DIB15 (instanceRef pdp_ram_0_2_61))
+              (portRef DIA15 (instanceRef pdp_ram_0_2_61))
+              (portRef DIB14 (instanceRef pdp_ram_0_2_61))
+              (portRef DIA14 (instanceRef pdp_ram_0_2_61))
+              (portRef DIB13 (instanceRef pdp_ram_0_2_61))
+              (portRef DIA13 (instanceRef pdp_ram_0_2_61))
+              (portRef DIB12 (instanceRef pdp_ram_0_2_61))
+              (portRef DIA12 (instanceRef pdp_ram_0_2_61))
+              (portRef DIB11 (instanceRef pdp_ram_0_2_61))
+              (portRef DIA11 (instanceRef pdp_ram_0_2_61))
+              (portRef DIB10 (instanceRef pdp_ram_0_2_61))
+              (portRef DIA10 (instanceRef pdp_ram_0_2_61))
+              (portRef DIB9 (instanceRef pdp_ram_0_2_61))
+              (portRef DIA9 (instanceRef pdp_ram_0_2_61))
+              (portRef DIB8 (instanceRef pdp_ram_0_2_61))
+              (portRef DIB7 (instanceRef pdp_ram_0_2_61))
+              (portRef DIB6 (instanceRef pdp_ram_0_2_61))
+              (portRef DIB5 (instanceRef pdp_ram_0_2_61))
+              (portRef DIB4 (instanceRef pdp_ram_0_2_61))
+              (portRef DIB3 (instanceRef pdp_ram_0_2_61))
+              (portRef DIB2 (instanceRef pdp_ram_0_2_61))
+              (portRef DIB1 (instanceRef pdp_ram_0_2_61))
+              (portRef DIB0 (instanceRef pdp_ram_0_2_61))
+              (portRef CSB2 (instanceRef pdp_ram_0_3_60))
+              (portRef CSA2 (instanceRef pdp_ram_0_3_60))
+              (portRef CSB1 (instanceRef pdp_ram_0_3_60))
+              (portRef CSA1 (instanceRef pdp_ram_0_3_60))
+              (portRef WEB (instanceRef pdp_ram_0_3_60))
+              (portRef ADB2 (instanceRef pdp_ram_0_3_60))
+              (portRef ADA2 (instanceRef pdp_ram_0_3_60))
+              (portRef ADB1 (instanceRef pdp_ram_0_3_60))
+              (portRef ADA1 (instanceRef pdp_ram_0_3_60))
+              (portRef ADB0 (instanceRef pdp_ram_0_3_60))
+              (portRef ADA0 (instanceRef pdp_ram_0_3_60))
+              (portRef DIB17 (instanceRef pdp_ram_0_3_60))
+              (portRef DIA17 (instanceRef pdp_ram_0_3_60))
+              (portRef DIB16 (instanceRef pdp_ram_0_3_60))
+              (portRef DIA16 (instanceRef pdp_ram_0_3_60))
+              (portRef DIB15 (instanceRef pdp_ram_0_3_60))
+              (portRef DIA15 (instanceRef pdp_ram_0_3_60))
+              (portRef DIB14 (instanceRef pdp_ram_0_3_60))
+              (portRef DIA14 (instanceRef pdp_ram_0_3_60))
+              (portRef DIB13 (instanceRef pdp_ram_0_3_60))
+              (portRef DIA13 (instanceRef pdp_ram_0_3_60))
+              (portRef DIB12 (instanceRef pdp_ram_0_3_60))
+              (portRef DIA12 (instanceRef pdp_ram_0_3_60))
+              (portRef DIB11 (instanceRef pdp_ram_0_3_60))
+              (portRef DIA11 (instanceRef pdp_ram_0_3_60))
+              (portRef DIB10 (instanceRef pdp_ram_0_3_60))
+              (portRef DIA10 (instanceRef pdp_ram_0_3_60))
+              (portRef DIB9 (instanceRef pdp_ram_0_3_60))
+              (portRef DIA9 (instanceRef pdp_ram_0_3_60))
+              (portRef DIB8 (instanceRef pdp_ram_0_3_60))
+              (portRef DIB7 (instanceRef pdp_ram_0_3_60))
+              (portRef DIB6 (instanceRef pdp_ram_0_3_60))
+              (portRef DIB5 (instanceRef pdp_ram_0_3_60))
+              (portRef DIB4 (instanceRef pdp_ram_0_3_60))
+              (portRef DIB3 (instanceRef pdp_ram_0_3_60))
+              (portRef DIB2 (instanceRef pdp_ram_0_3_60))
+              (portRef DIB1 (instanceRef pdp_ram_0_3_60))
+              (portRef DIB0 (instanceRef pdp_ram_0_3_60))
+              (portRef CSB2 (instanceRef pdp_ram_1_0_59))
+              (portRef CSA2 (instanceRef pdp_ram_1_0_59))
+              (portRef CSB1 (instanceRef pdp_ram_1_0_59))
+              (portRef CSA1 (instanceRef pdp_ram_1_0_59))
+              (portRef WEB (instanceRef pdp_ram_1_0_59))
+              (portRef ADB2 (instanceRef pdp_ram_1_0_59))
+              (portRef ADA2 (instanceRef pdp_ram_1_0_59))
+              (portRef ADB1 (instanceRef pdp_ram_1_0_59))
+              (portRef ADA1 (instanceRef pdp_ram_1_0_59))
+              (portRef ADB0 (instanceRef pdp_ram_1_0_59))
+              (portRef ADA0 (instanceRef pdp_ram_1_0_59))
+              (portRef DIB17 (instanceRef pdp_ram_1_0_59))
+              (portRef DIA17 (instanceRef pdp_ram_1_0_59))
+              (portRef DIB16 (instanceRef pdp_ram_1_0_59))
+              (portRef DIA16 (instanceRef pdp_ram_1_0_59))
+              (portRef DIB15 (instanceRef pdp_ram_1_0_59))
+              (portRef DIA15 (instanceRef pdp_ram_1_0_59))
+              (portRef DIB14 (instanceRef pdp_ram_1_0_59))
+              (portRef DIA14 (instanceRef pdp_ram_1_0_59))
+              (portRef DIB13 (instanceRef pdp_ram_1_0_59))
+              (portRef DIA13 (instanceRef pdp_ram_1_0_59))
+              (portRef DIB12 (instanceRef pdp_ram_1_0_59))
+              (portRef DIA12 (instanceRef pdp_ram_1_0_59))
+              (portRef DIB11 (instanceRef pdp_ram_1_0_59))
+              (portRef DIA11 (instanceRef pdp_ram_1_0_59))
+              (portRef DIB10 (instanceRef pdp_ram_1_0_59))
+              (portRef DIA10 (instanceRef pdp_ram_1_0_59))
+              (portRef DIB9 (instanceRef pdp_ram_1_0_59))
+              (portRef DIA9 (instanceRef pdp_ram_1_0_59))
+              (portRef DIB8 (instanceRef pdp_ram_1_0_59))
+              (portRef DIB7 (instanceRef pdp_ram_1_0_59))
+              (portRef DIB6 (instanceRef pdp_ram_1_0_59))
+              (portRef DIB5 (instanceRef pdp_ram_1_0_59))
+              (portRef DIB4 (instanceRef pdp_ram_1_0_59))
+              (portRef DIB3 (instanceRef pdp_ram_1_0_59))
+              (portRef DIB2 (instanceRef pdp_ram_1_0_59))
+              (portRef DIB1 (instanceRef pdp_ram_1_0_59))
+              (portRef DIB0 (instanceRef pdp_ram_1_0_59))
+              (portRef CSB2 (instanceRef pdp_ram_1_1_58))
+              (portRef CSA2 (instanceRef pdp_ram_1_1_58))
+              (portRef CSB1 (instanceRef pdp_ram_1_1_58))
+              (portRef CSA1 (instanceRef pdp_ram_1_1_58))
+              (portRef WEB (instanceRef pdp_ram_1_1_58))
+              (portRef ADB2 (instanceRef pdp_ram_1_1_58))
+              (portRef ADA2 (instanceRef pdp_ram_1_1_58))
+              (portRef ADB1 (instanceRef pdp_ram_1_1_58))
+              (portRef ADA1 (instanceRef pdp_ram_1_1_58))
+              (portRef ADB0 (instanceRef pdp_ram_1_1_58))
+              (portRef ADA0 (instanceRef pdp_ram_1_1_58))
+              (portRef DIB17 (instanceRef pdp_ram_1_1_58))
+              (portRef DIA17 (instanceRef pdp_ram_1_1_58))
+              (portRef DIB16 (instanceRef pdp_ram_1_1_58))
+              (portRef DIA16 (instanceRef pdp_ram_1_1_58))
+              (portRef DIB15 (instanceRef pdp_ram_1_1_58))
+              (portRef DIA15 (instanceRef pdp_ram_1_1_58))
+              (portRef DIB14 (instanceRef pdp_ram_1_1_58))
+              (portRef DIA14 (instanceRef pdp_ram_1_1_58))
+              (portRef DIB13 (instanceRef pdp_ram_1_1_58))
+              (portRef DIA13 (instanceRef pdp_ram_1_1_58))
+              (portRef DIB12 (instanceRef pdp_ram_1_1_58))
+              (portRef DIA12 (instanceRef pdp_ram_1_1_58))
+              (portRef DIB11 (instanceRef pdp_ram_1_1_58))
+              (portRef DIA11 (instanceRef pdp_ram_1_1_58))
+              (portRef DIB10 (instanceRef pdp_ram_1_1_58))
+              (portRef DIA10 (instanceRef pdp_ram_1_1_58))
+              (portRef DIB9 (instanceRef pdp_ram_1_1_58))
+              (portRef DIA9 (instanceRef pdp_ram_1_1_58))
+              (portRef DIB8 (instanceRef pdp_ram_1_1_58))
+              (portRef DIB7 (instanceRef pdp_ram_1_1_58))
+              (portRef DIB6 (instanceRef pdp_ram_1_1_58))
+              (portRef DIB5 (instanceRef pdp_ram_1_1_58))
+              (portRef DIB4 (instanceRef pdp_ram_1_1_58))
+              (portRef DIB3 (instanceRef pdp_ram_1_1_58))
+              (portRef DIB2 (instanceRef pdp_ram_1_1_58))
+              (portRef DIB1 (instanceRef pdp_ram_1_1_58))
+              (portRef DIB0 (instanceRef pdp_ram_1_1_58))
+              (portRef CSB2 (instanceRef pdp_ram_1_2_57))
+              (portRef CSA2 (instanceRef pdp_ram_1_2_57))
+              (portRef CSB1 (instanceRef pdp_ram_1_2_57))
+              (portRef CSA1 (instanceRef pdp_ram_1_2_57))
+              (portRef WEB (instanceRef pdp_ram_1_2_57))
+              (portRef ADB2 (instanceRef pdp_ram_1_2_57))
+              (portRef ADA2 (instanceRef pdp_ram_1_2_57))
+              (portRef ADB1 (instanceRef pdp_ram_1_2_57))
+              (portRef ADA1 (instanceRef pdp_ram_1_2_57))
+              (portRef ADB0 (instanceRef pdp_ram_1_2_57))
+              (portRef ADA0 (instanceRef pdp_ram_1_2_57))
+              (portRef DIB17 (instanceRef pdp_ram_1_2_57))
+              (portRef DIA17 (instanceRef pdp_ram_1_2_57))
+              (portRef DIB16 (instanceRef pdp_ram_1_2_57))
+              (portRef DIA16 (instanceRef pdp_ram_1_2_57))
+              (portRef DIB15 (instanceRef pdp_ram_1_2_57))
+              (portRef DIA15 (instanceRef pdp_ram_1_2_57))
+              (portRef DIB14 (instanceRef pdp_ram_1_2_57))
+              (portRef DIA14 (instanceRef pdp_ram_1_2_57))
+              (portRef DIB13 (instanceRef pdp_ram_1_2_57))
+              (portRef DIA13 (instanceRef pdp_ram_1_2_57))
+              (portRef DIB12 (instanceRef pdp_ram_1_2_57))
+              (portRef DIA12 (instanceRef pdp_ram_1_2_57))
+              (portRef DIB11 (instanceRef pdp_ram_1_2_57))
+              (portRef DIA11 (instanceRef pdp_ram_1_2_57))
+              (portRef DIB10 (instanceRef pdp_ram_1_2_57))
+              (portRef DIA10 (instanceRef pdp_ram_1_2_57))
+              (portRef DIB9 (instanceRef pdp_ram_1_2_57))
+              (portRef DIA9 (instanceRef pdp_ram_1_2_57))
+              (portRef DIB8 (instanceRef pdp_ram_1_2_57))
+              (portRef DIB7 (instanceRef pdp_ram_1_2_57))
+              (portRef DIB6 (instanceRef pdp_ram_1_2_57))
+              (portRef DIB5 (instanceRef pdp_ram_1_2_57))
+              (portRef DIB4 (instanceRef pdp_ram_1_2_57))
+              (portRef DIB3 (instanceRef pdp_ram_1_2_57))
+              (portRef DIB2 (instanceRef pdp_ram_1_2_57))
+              (portRef DIB1 (instanceRef pdp_ram_1_2_57))
+              (portRef DIB0 (instanceRef pdp_ram_1_2_57))
+              (portRef CSB2 (instanceRef pdp_ram_1_3_56))
+              (portRef CSA2 (instanceRef pdp_ram_1_3_56))
+              (portRef CSB1 (instanceRef pdp_ram_1_3_56))
+              (portRef CSA1 (instanceRef pdp_ram_1_3_56))
+              (portRef WEB (instanceRef pdp_ram_1_3_56))
+              (portRef ADB2 (instanceRef pdp_ram_1_3_56))
+              (portRef ADA2 (instanceRef pdp_ram_1_3_56))
+              (portRef ADB1 (instanceRef pdp_ram_1_3_56))
+              (portRef ADA1 (instanceRef pdp_ram_1_3_56))
+              (portRef ADB0 (instanceRef pdp_ram_1_3_56))
+              (portRef ADA0 (instanceRef pdp_ram_1_3_56))
+              (portRef DIB17 (instanceRef pdp_ram_1_3_56))
+              (portRef DIA17 (instanceRef pdp_ram_1_3_56))
+              (portRef DIB16 (instanceRef pdp_ram_1_3_56))
+              (portRef DIA16 (instanceRef pdp_ram_1_3_56))
+              (portRef DIB15 (instanceRef pdp_ram_1_3_56))
+              (portRef DIA15 (instanceRef pdp_ram_1_3_56))
+              (portRef DIB14 (instanceRef pdp_ram_1_3_56))
+              (portRef DIA14 (instanceRef pdp_ram_1_3_56))
+              (portRef DIB13 (instanceRef pdp_ram_1_3_56))
+              (portRef DIA13 (instanceRef pdp_ram_1_3_56))
+              (portRef DIB12 (instanceRef pdp_ram_1_3_56))
+              (portRef DIA12 (instanceRef pdp_ram_1_3_56))
+              (portRef DIB11 (instanceRef pdp_ram_1_3_56))
+              (portRef DIA11 (instanceRef pdp_ram_1_3_56))
+              (portRef DIB10 (instanceRef pdp_ram_1_3_56))
+              (portRef DIA10 (instanceRef pdp_ram_1_3_56))
+              (portRef DIB9 (instanceRef pdp_ram_1_3_56))
+              (portRef DIA9 (instanceRef pdp_ram_1_3_56))
+              (portRef DIB8 (instanceRef pdp_ram_1_3_56))
+              (portRef DIB7 (instanceRef pdp_ram_1_3_56))
+              (portRef DIB6 (instanceRef pdp_ram_1_3_56))
+              (portRef DIB5 (instanceRef pdp_ram_1_3_56))
+              (portRef DIB4 (instanceRef pdp_ram_1_3_56))
+              (portRef DIB3 (instanceRef pdp_ram_1_3_56))
+              (portRef DIB2 (instanceRef pdp_ram_1_3_56))
+              (portRef DIB1 (instanceRef pdp_ram_1_3_56))
+              (portRef DIB0 (instanceRef pdp_ram_1_3_56))
+              (portRef CSB2 (instanceRef pdp_ram_2_0_55))
+              (portRef CSA2 (instanceRef pdp_ram_2_0_55))
+              (portRef CSB1 (instanceRef pdp_ram_2_0_55))
+              (portRef CSA1 (instanceRef pdp_ram_2_0_55))
+              (portRef WEB (instanceRef pdp_ram_2_0_55))
+              (portRef ADB2 (instanceRef pdp_ram_2_0_55))
+              (portRef ADA2 (instanceRef pdp_ram_2_0_55))
+              (portRef ADB1 (instanceRef pdp_ram_2_0_55))
+              (portRef ADA1 (instanceRef pdp_ram_2_0_55))
+              (portRef ADB0 (instanceRef pdp_ram_2_0_55))
+              (portRef ADA0 (instanceRef pdp_ram_2_0_55))
+              (portRef DIB17 (instanceRef pdp_ram_2_0_55))
+              (portRef DIA17 (instanceRef pdp_ram_2_0_55))
+              (portRef DIB16 (instanceRef pdp_ram_2_0_55))
+              (portRef DIA16 (instanceRef pdp_ram_2_0_55))
+              (portRef DIB15 (instanceRef pdp_ram_2_0_55))
+              (portRef DIA15 (instanceRef pdp_ram_2_0_55))
+              (portRef DIB14 (instanceRef pdp_ram_2_0_55))
+              (portRef DIA14 (instanceRef pdp_ram_2_0_55))
+              (portRef DIB13 (instanceRef pdp_ram_2_0_55))
+              (portRef DIA13 (instanceRef pdp_ram_2_0_55))
+              (portRef DIB12 (instanceRef pdp_ram_2_0_55))
+              (portRef DIA12 (instanceRef pdp_ram_2_0_55))
+              (portRef DIB11 (instanceRef pdp_ram_2_0_55))
+              (portRef DIA11 (instanceRef pdp_ram_2_0_55))
+              (portRef DIB10 (instanceRef pdp_ram_2_0_55))
+              (portRef DIA10 (instanceRef pdp_ram_2_0_55))
+              (portRef DIB9 (instanceRef pdp_ram_2_0_55))
+              (portRef DIA9 (instanceRef pdp_ram_2_0_55))
+              (portRef DIB8 (instanceRef pdp_ram_2_0_55))
+              (portRef DIB7 (instanceRef pdp_ram_2_0_55))
+              (portRef DIB6 (instanceRef pdp_ram_2_0_55))
+              (portRef DIB5 (instanceRef pdp_ram_2_0_55))
+              (portRef DIB4 (instanceRef pdp_ram_2_0_55))
+              (portRef DIB3 (instanceRef pdp_ram_2_0_55))
+              (portRef DIB2 (instanceRef pdp_ram_2_0_55))
+              (portRef DIB1 (instanceRef pdp_ram_2_0_55))
+              (portRef DIB0 (instanceRef pdp_ram_2_0_55))
+              (portRef CSB2 (instanceRef pdp_ram_2_1_54))
+              (portRef CSA2 (instanceRef pdp_ram_2_1_54))
+              (portRef CSB1 (instanceRef pdp_ram_2_1_54))
+              (portRef CSA1 (instanceRef pdp_ram_2_1_54))
+              (portRef WEB (instanceRef pdp_ram_2_1_54))
+              (portRef ADB2 (instanceRef pdp_ram_2_1_54))
+              (portRef ADA2 (instanceRef pdp_ram_2_1_54))
+              (portRef ADB1 (instanceRef pdp_ram_2_1_54))
+              (portRef ADA1 (instanceRef pdp_ram_2_1_54))
+              (portRef ADB0 (instanceRef pdp_ram_2_1_54))
+              (portRef ADA0 (instanceRef pdp_ram_2_1_54))
+              (portRef DIB17 (instanceRef pdp_ram_2_1_54))
+              (portRef DIA17 (instanceRef pdp_ram_2_1_54))
+              (portRef DIB16 (instanceRef pdp_ram_2_1_54))
+              (portRef DIA16 (instanceRef pdp_ram_2_1_54))
+              (portRef DIB15 (instanceRef pdp_ram_2_1_54))
+              (portRef DIA15 (instanceRef pdp_ram_2_1_54))
+              (portRef DIB14 (instanceRef pdp_ram_2_1_54))
+              (portRef DIA14 (instanceRef pdp_ram_2_1_54))
+              (portRef DIB13 (instanceRef pdp_ram_2_1_54))
+              (portRef DIA13 (instanceRef pdp_ram_2_1_54))
+              (portRef DIB12 (instanceRef pdp_ram_2_1_54))
+              (portRef DIA12 (instanceRef pdp_ram_2_1_54))
+              (portRef DIB11 (instanceRef pdp_ram_2_1_54))
+              (portRef DIA11 (instanceRef pdp_ram_2_1_54))
+              (portRef DIB10 (instanceRef pdp_ram_2_1_54))
+              (portRef DIA10 (instanceRef pdp_ram_2_1_54))
+              (portRef DIB9 (instanceRef pdp_ram_2_1_54))
+              (portRef DIA9 (instanceRef pdp_ram_2_1_54))
+              (portRef DIB8 (instanceRef pdp_ram_2_1_54))
+              (portRef DIB7 (instanceRef pdp_ram_2_1_54))
+              (portRef DIB6 (instanceRef pdp_ram_2_1_54))
+              (portRef DIB5 (instanceRef pdp_ram_2_1_54))
+              (portRef DIB4 (instanceRef pdp_ram_2_1_54))
+              (portRef DIB3 (instanceRef pdp_ram_2_1_54))
+              (portRef DIB2 (instanceRef pdp_ram_2_1_54))
+              (portRef DIB1 (instanceRef pdp_ram_2_1_54))
+              (portRef DIB0 (instanceRef pdp_ram_2_1_54))
+              (portRef CSB2 (instanceRef pdp_ram_2_2_53))
+              (portRef CSA2 (instanceRef pdp_ram_2_2_53))
+              (portRef CSB1 (instanceRef pdp_ram_2_2_53))
+              (portRef CSA1 (instanceRef pdp_ram_2_2_53))
+              (portRef WEB (instanceRef pdp_ram_2_2_53))
+              (portRef ADB2 (instanceRef pdp_ram_2_2_53))
+              (portRef ADA2 (instanceRef pdp_ram_2_2_53))
+              (portRef ADB1 (instanceRef pdp_ram_2_2_53))
+              (portRef ADA1 (instanceRef pdp_ram_2_2_53))
+              (portRef ADB0 (instanceRef pdp_ram_2_2_53))
+              (portRef ADA0 (instanceRef pdp_ram_2_2_53))
+              (portRef DIB17 (instanceRef pdp_ram_2_2_53))
+              (portRef DIA17 (instanceRef pdp_ram_2_2_53))
+              (portRef DIB16 (instanceRef pdp_ram_2_2_53))
+              (portRef DIA16 (instanceRef pdp_ram_2_2_53))
+              (portRef DIB15 (instanceRef pdp_ram_2_2_53))
+              (portRef DIA15 (instanceRef pdp_ram_2_2_53))
+              (portRef DIB14 (instanceRef pdp_ram_2_2_53))
+              (portRef DIA14 (instanceRef pdp_ram_2_2_53))
+              (portRef DIB13 (instanceRef pdp_ram_2_2_53))
+              (portRef DIA13 (instanceRef pdp_ram_2_2_53))
+              (portRef DIB12 (instanceRef pdp_ram_2_2_53))
+              (portRef DIA12 (instanceRef pdp_ram_2_2_53))
+              (portRef DIB11 (instanceRef pdp_ram_2_2_53))
+              (portRef DIA11 (instanceRef pdp_ram_2_2_53))
+              (portRef DIB10 (instanceRef pdp_ram_2_2_53))
+              (portRef DIA10 (instanceRef pdp_ram_2_2_53))
+              (portRef DIB9 (instanceRef pdp_ram_2_2_53))
+              (portRef DIA9 (instanceRef pdp_ram_2_2_53))
+              (portRef DIB8 (instanceRef pdp_ram_2_2_53))
+              (portRef DIB7 (instanceRef pdp_ram_2_2_53))
+              (portRef DIB6 (instanceRef pdp_ram_2_2_53))
+              (portRef DIB5 (instanceRef pdp_ram_2_2_53))
+              (portRef DIB4 (instanceRef pdp_ram_2_2_53))
+              (portRef DIB3 (instanceRef pdp_ram_2_2_53))
+              (portRef DIB2 (instanceRef pdp_ram_2_2_53))
+              (portRef DIB1 (instanceRef pdp_ram_2_2_53))
+              (portRef DIB0 (instanceRef pdp_ram_2_2_53))
+              (portRef CSB2 (instanceRef pdp_ram_2_3_52))
+              (portRef CSA2 (instanceRef pdp_ram_2_3_52))
+              (portRef CSB1 (instanceRef pdp_ram_2_3_52))
+              (portRef CSA1 (instanceRef pdp_ram_2_3_52))
+              (portRef WEB (instanceRef pdp_ram_2_3_52))
+              (portRef ADB2 (instanceRef pdp_ram_2_3_52))
+              (portRef ADA2 (instanceRef pdp_ram_2_3_52))
+              (portRef ADB1 (instanceRef pdp_ram_2_3_52))
+              (portRef ADA1 (instanceRef pdp_ram_2_3_52))
+              (portRef ADB0 (instanceRef pdp_ram_2_3_52))
+              (portRef ADA0 (instanceRef pdp_ram_2_3_52))
+              (portRef DIB17 (instanceRef pdp_ram_2_3_52))
+              (portRef DIA17 (instanceRef pdp_ram_2_3_52))
+              (portRef DIB16 (instanceRef pdp_ram_2_3_52))
+              (portRef DIA16 (instanceRef pdp_ram_2_3_52))
+              (portRef DIB15 (instanceRef pdp_ram_2_3_52))
+              (portRef DIA15 (instanceRef pdp_ram_2_3_52))
+              (portRef DIB14 (instanceRef pdp_ram_2_3_52))
+              (portRef DIA14 (instanceRef pdp_ram_2_3_52))
+              (portRef DIB13 (instanceRef pdp_ram_2_3_52))
+              (portRef DIA13 (instanceRef pdp_ram_2_3_52))
+              (portRef DIB12 (instanceRef pdp_ram_2_3_52))
+              (portRef DIA12 (instanceRef pdp_ram_2_3_52))
+              (portRef DIB11 (instanceRef pdp_ram_2_3_52))
+              (portRef DIA11 (instanceRef pdp_ram_2_3_52))
+              (portRef DIB10 (instanceRef pdp_ram_2_3_52))
+              (portRef DIA10 (instanceRef pdp_ram_2_3_52))
+              (portRef DIB9 (instanceRef pdp_ram_2_3_52))
+              (portRef DIA9 (instanceRef pdp_ram_2_3_52))
+              (portRef DIB8 (instanceRef pdp_ram_2_3_52))
+              (portRef DIB7 (instanceRef pdp_ram_2_3_52))
+              (portRef DIB6 (instanceRef pdp_ram_2_3_52))
+              (portRef DIB5 (instanceRef pdp_ram_2_3_52))
+              (portRef DIB4 (instanceRef pdp_ram_2_3_52))
+              (portRef DIB3 (instanceRef pdp_ram_2_3_52))
+              (portRef DIB2 (instanceRef pdp_ram_2_3_52))
+              (portRef DIB1 (instanceRef pdp_ram_2_3_52))
+              (portRef DIB0 (instanceRef pdp_ram_2_3_52))
+              (portRef CSB2 (instanceRef pdp_ram_3_0_51))
+              (portRef CSA2 (instanceRef pdp_ram_3_0_51))
+              (portRef CSB1 (instanceRef pdp_ram_3_0_51))
+              (portRef CSA1 (instanceRef pdp_ram_3_0_51))
+              (portRef WEB (instanceRef pdp_ram_3_0_51))
+              (portRef ADB2 (instanceRef pdp_ram_3_0_51))
+              (portRef ADA2 (instanceRef pdp_ram_3_0_51))
+              (portRef ADB1 (instanceRef pdp_ram_3_0_51))
+              (portRef ADA1 (instanceRef pdp_ram_3_0_51))
+              (portRef ADB0 (instanceRef pdp_ram_3_0_51))
+              (portRef ADA0 (instanceRef pdp_ram_3_0_51))
+              (portRef DIB17 (instanceRef pdp_ram_3_0_51))
+              (portRef DIA17 (instanceRef pdp_ram_3_0_51))
+              (portRef DIB16 (instanceRef pdp_ram_3_0_51))
+              (portRef DIA16 (instanceRef pdp_ram_3_0_51))
+              (portRef DIB15 (instanceRef pdp_ram_3_0_51))
+              (portRef DIA15 (instanceRef pdp_ram_3_0_51))
+              (portRef DIB14 (instanceRef pdp_ram_3_0_51))
+              (portRef DIA14 (instanceRef pdp_ram_3_0_51))
+              (portRef DIB13 (instanceRef pdp_ram_3_0_51))
+              (portRef DIA13 (instanceRef pdp_ram_3_0_51))
+              (portRef DIB12 (instanceRef pdp_ram_3_0_51))
+              (portRef DIA12 (instanceRef pdp_ram_3_0_51))
+              (portRef DIB11 (instanceRef pdp_ram_3_0_51))
+              (portRef DIA11 (instanceRef pdp_ram_3_0_51))
+              (portRef DIB10 (instanceRef pdp_ram_3_0_51))
+              (portRef DIA10 (instanceRef pdp_ram_3_0_51))
+              (portRef DIB9 (instanceRef pdp_ram_3_0_51))
+              (portRef DIA9 (instanceRef pdp_ram_3_0_51))
+              (portRef DIB8 (instanceRef pdp_ram_3_0_51))
+              (portRef DIB7 (instanceRef pdp_ram_3_0_51))
+              (portRef DIB6 (instanceRef pdp_ram_3_0_51))
+              (portRef DIB5 (instanceRef pdp_ram_3_0_51))
+              (portRef DIB4 (instanceRef pdp_ram_3_0_51))
+              (portRef DIB3 (instanceRef pdp_ram_3_0_51))
+              (portRef DIB2 (instanceRef pdp_ram_3_0_51))
+              (portRef DIB1 (instanceRef pdp_ram_3_0_51))
+              (portRef DIB0 (instanceRef pdp_ram_3_0_51))
+              (portRef CSB2 (instanceRef pdp_ram_3_1_50))
+              (portRef CSA2 (instanceRef pdp_ram_3_1_50))
+              (portRef CSB1 (instanceRef pdp_ram_3_1_50))
+              (portRef CSA1 (instanceRef pdp_ram_3_1_50))
+              (portRef WEB (instanceRef pdp_ram_3_1_50))
+              (portRef ADB2 (instanceRef pdp_ram_3_1_50))
+              (portRef ADA2 (instanceRef pdp_ram_3_1_50))
+              (portRef ADB1 (instanceRef pdp_ram_3_1_50))
+              (portRef ADA1 (instanceRef pdp_ram_3_1_50))
+              (portRef ADB0 (instanceRef pdp_ram_3_1_50))
+              (portRef ADA0 (instanceRef pdp_ram_3_1_50))
+              (portRef DIB17 (instanceRef pdp_ram_3_1_50))
+              (portRef DIA17 (instanceRef pdp_ram_3_1_50))
+              (portRef DIB16 (instanceRef pdp_ram_3_1_50))
+              (portRef DIA16 (instanceRef pdp_ram_3_1_50))
+              (portRef DIB15 (instanceRef pdp_ram_3_1_50))
+              (portRef DIA15 (instanceRef pdp_ram_3_1_50))
+              (portRef DIB14 (instanceRef pdp_ram_3_1_50))
+              (portRef DIA14 (instanceRef pdp_ram_3_1_50))
+              (portRef DIB13 (instanceRef pdp_ram_3_1_50))
+              (portRef DIA13 (instanceRef pdp_ram_3_1_50))
+              (portRef DIB12 (instanceRef pdp_ram_3_1_50))
+              (portRef DIA12 (instanceRef pdp_ram_3_1_50))
+              (portRef DIB11 (instanceRef pdp_ram_3_1_50))
+              (portRef DIA11 (instanceRef pdp_ram_3_1_50))
+              (portRef DIB10 (instanceRef pdp_ram_3_1_50))
+              (portRef DIA10 (instanceRef pdp_ram_3_1_50))
+              (portRef DIB9 (instanceRef pdp_ram_3_1_50))
+              (portRef DIA9 (instanceRef pdp_ram_3_1_50))
+              (portRef DIB8 (instanceRef pdp_ram_3_1_50))
+              (portRef DIB7 (instanceRef pdp_ram_3_1_50))
+              (portRef DIB6 (instanceRef pdp_ram_3_1_50))
+              (portRef DIB5 (instanceRef pdp_ram_3_1_50))
+              (portRef DIB4 (instanceRef pdp_ram_3_1_50))
+              (portRef DIB3 (instanceRef pdp_ram_3_1_50))
+              (portRef DIB2 (instanceRef pdp_ram_3_1_50))
+              (portRef DIB1 (instanceRef pdp_ram_3_1_50))
+              (portRef DIB0 (instanceRef pdp_ram_3_1_50))
+              (portRef CSB2 (instanceRef pdp_ram_3_2_49))
+              (portRef CSA2 (instanceRef pdp_ram_3_2_49))
+              (portRef CSB1 (instanceRef pdp_ram_3_2_49))
+              (portRef CSA1 (instanceRef pdp_ram_3_2_49))
+              (portRef WEB (instanceRef pdp_ram_3_2_49))
+              (portRef ADB2 (instanceRef pdp_ram_3_2_49))
+              (portRef ADA2 (instanceRef pdp_ram_3_2_49))
+              (portRef ADB1 (instanceRef pdp_ram_3_2_49))
+              (portRef ADA1 (instanceRef pdp_ram_3_2_49))
+              (portRef ADB0 (instanceRef pdp_ram_3_2_49))
+              (portRef ADA0 (instanceRef pdp_ram_3_2_49))
+              (portRef DIB17 (instanceRef pdp_ram_3_2_49))
+              (portRef DIA17 (instanceRef pdp_ram_3_2_49))
+              (portRef DIB16 (instanceRef pdp_ram_3_2_49))
+              (portRef DIA16 (instanceRef pdp_ram_3_2_49))
+              (portRef DIB15 (instanceRef pdp_ram_3_2_49))
+              (portRef DIA15 (instanceRef pdp_ram_3_2_49))
+              (portRef DIB14 (instanceRef pdp_ram_3_2_49))
+              (portRef DIA14 (instanceRef pdp_ram_3_2_49))
+              (portRef DIB13 (instanceRef pdp_ram_3_2_49))
+              (portRef DIA13 (instanceRef pdp_ram_3_2_49))
+              (portRef DIB12 (instanceRef pdp_ram_3_2_49))
+              (portRef DIA12 (instanceRef pdp_ram_3_2_49))
+              (portRef DIB11 (instanceRef pdp_ram_3_2_49))
+              (portRef DIA11 (instanceRef pdp_ram_3_2_49))
+              (portRef DIB10 (instanceRef pdp_ram_3_2_49))
+              (portRef DIA10 (instanceRef pdp_ram_3_2_49))
+              (portRef DIB9 (instanceRef pdp_ram_3_2_49))
+              (portRef DIA9 (instanceRef pdp_ram_3_2_49))
+              (portRef DIB8 (instanceRef pdp_ram_3_2_49))
+              (portRef DIB7 (instanceRef pdp_ram_3_2_49))
+              (portRef DIB6 (instanceRef pdp_ram_3_2_49))
+              (portRef DIB5 (instanceRef pdp_ram_3_2_49))
+              (portRef DIB4 (instanceRef pdp_ram_3_2_49))
+              (portRef DIB3 (instanceRef pdp_ram_3_2_49))
+              (portRef DIB2 (instanceRef pdp_ram_3_2_49))
+              (portRef DIB1 (instanceRef pdp_ram_3_2_49))
+              (portRef DIB0 (instanceRef pdp_ram_3_2_49))
+              (portRef CSB2 (instanceRef pdp_ram_3_3_48))
+              (portRef CSA2 (instanceRef pdp_ram_3_3_48))
+              (portRef CSB1 (instanceRef pdp_ram_3_3_48))
+              (portRef CSA1 (instanceRef pdp_ram_3_3_48))
+              (portRef WEB (instanceRef pdp_ram_3_3_48))
+              (portRef ADB2 (instanceRef pdp_ram_3_3_48))
+              (portRef ADA2 (instanceRef pdp_ram_3_3_48))
+              (portRef ADB1 (instanceRef pdp_ram_3_3_48))
+              (portRef ADA1 (instanceRef pdp_ram_3_3_48))
+              (portRef ADB0 (instanceRef pdp_ram_3_3_48))
+              (portRef ADA0 (instanceRef pdp_ram_3_3_48))
+              (portRef DIB17 (instanceRef pdp_ram_3_3_48))
+              (portRef DIA17 (instanceRef pdp_ram_3_3_48))
+              (portRef DIB16 (instanceRef pdp_ram_3_3_48))
+              (portRef DIA16 (instanceRef pdp_ram_3_3_48))
+              (portRef DIB15 (instanceRef pdp_ram_3_3_48))
+              (portRef DIA15 (instanceRef pdp_ram_3_3_48))
+              (portRef DIB14 (instanceRef pdp_ram_3_3_48))
+              (portRef DIA14 (instanceRef pdp_ram_3_3_48))
+              (portRef DIB13 (instanceRef pdp_ram_3_3_48))
+              (portRef DIA13 (instanceRef pdp_ram_3_3_48))
+              (portRef DIB12 (instanceRef pdp_ram_3_3_48))
+              (portRef DIA12 (instanceRef pdp_ram_3_3_48))
+              (portRef DIB11 (instanceRef pdp_ram_3_3_48))
+              (portRef DIA11 (instanceRef pdp_ram_3_3_48))
+              (portRef DIB10 (instanceRef pdp_ram_3_3_48))
+              (portRef DIA10 (instanceRef pdp_ram_3_3_48))
+              (portRef DIB9 (instanceRef pdp_ram_3_3_48))
+              (portRef DIA9 (instanceRef pdp_ram_3_3_48))
+              (portRef DIB8 (instanceRef pdp_ram_3_3_48))
+              (portRef DIB7 (instanceRef pdp_ram_3_3_48))
+              (portRef DIB6 (instanceRef pdp_ram_3_3_48))
+              (portRef DIB5 (instanceRef pdp_ram_3_3_48))
+              (portRef DIB4 (instanceRef pdp_ram_3_3_48))
+              (portRef DIB3 (instanceRef pdp_ram_3_3_48))
+              (portRef DIB2 (instanceRef pdp_ram_3_3_48))
+              (portRef DIB1 (instanceRef pdp_ram_3_3_48))
+              (portRef DIB0 (instanceRef pdp_ram_3_3_48))
+              (portRef CSB2 (instanceRef pdp_ram_4_0_47))
+              (portRef CSA2 (instanceRef pdp_ram_4_0_47))
+              (portRef CSB1 (instanceRef pdp_ram_4_0_47))
+              (portRef CSA1 (instanceRef pdp_ram_4_0_47))
+              (portRef WEB (instanceRef pdp_ram_4_0_47))
+              (portRef ADB2 (instanceRef pdp_ram_4_0_47))
+              (portRef ADA2 (instanceRef pdp_ram_4_0_47))
+              (portRef ADB1 (instanceRef pdp_ram_4_0_47))
+              (portRef ADA1 (instanceRef pdp_ram_4_0_47))
+              (portRef ADB0 (instanceRef pdp_ram_4_0_47))
+              (portRef ADA0 (instanceRef pdp_ram_4_0_47))
+              (portRef DIB17 (instanceRef pdp_ram_4_0_47))
+              (portRef DIA17 (instanceRef pdp_ram_4_0_47))
+              (portRef DIB16 (instanceRef pdp_ram_4_0_47))
+              (portRef DIA16 (instanceRef pdp_ram_4_0_47))
+              (portRef DIB15 (instanceRef pdp_ram_4_0_47))
+              (portRef DIA15 (instanceRef pdp_ram_4_0_47))
+              (portRef DIB14 (instanceRef pdp_ram_4_0_47))
+              (portRef DIA14 (instanceRef pdp_ram_4_0_47))
+              (portRef DIB13 (instanceRef pdp_ram_4_0_47))
+              (portRef DIA13 (instanceRef pdp_ram_4_0_47))
+              (portRef DIB12 (instanceRef pdp_ram_4_0_47))
+              (portRef DIA12 (instanceRef pdp_ram_4_0_47))
+              (portRef DIB11 (instanceRef pdp_ram_4_0_47))
+              (portRef DIA11 (instanceRef pdp_ram_4_0_47))
+              (portRef DIB10 (instanceRef pdp_ram_4_0_47))
+              (portRef DIA10 (instanceRef pdp_ram_4_0_47))
+              (portRef DIB9 (instanceRef pdp_ram_4_0_47))
+              (portRef DIA9 (instanceRef pdp_ram_4_0_47))
+              (portRef DIB8 (instanceRef pdp_ram_4_0_47))
+              (portRef DIB7 (instanceRef pdp_ram_4_0_47))
+              (portRef DIB6 (instanceRef pdp_ram_4_0_47))
+              (portRef DIB5 (instanceRef pdp_ram_4_0_47))
+              (portRef DIB4 (instanceRef pdp_ram_4_0_47))
+              (portRef DIB3 (instanceRef pdp_ram_4_0_47))
+              (portRef DIB2 (instanceRef pdp_ram_4_0_47))
+              (portRef DIB1 (instanceRef pdp_ram_4_0_47))
+              (portRef DIB0 (instanceRef pdp_ram_4_0_47))
+              (portRef CSB2 (instanceRef pdp_ram_4_1_46))
+              (portRef CSA2 (instanceRef pdp_ram_4_1_46))
+              (portRef CSB1 (instanceRef pdp_ram_4_1_46))
+              (portRef CSA1 (instanceRef pdp_ram_4_1_46))
+              (portRef WEB (instanceRef pdp_ram_4_1_46))
+              (portRef ADB2 (instanceRef pdp_ram_4_1_46))
+              (portRef ADA2 (instanceRef pdp_ram_4_1_46))
+              (portRef ADB1 (instanceRef pdp_ram_4_1_46))
+              (portRef ADA1 (instanceRef pdp_ram_4_1_46))
+              (portRef ADB0 (instanceRef pdp_ram_4_1_46))
+              (portRef ADA0 (instanceRef pdp_ram_4_1_46))
+              (portRef DIB17 (instanceRef pdp_ram_4_1_46))
+              (portRef DIA17 (instanceRef pdp_ram_4_1_46))
+              (portRef DIB16 (instanceRef pdp_ram_4_1_46))
+              (portRef DIA16 (instanceRef pdp_ram_4_1_46))
+              (portRef DIB15 (instanceRef pdp_ram_4_1_46))
+              (portRef DIA15 (instanceRef pdp_ram_4_1_46))
+              (portRef DIB14 (instanceRef pdp_ram_4_1_46))
+              (portRef DIA14 (instanceRef pdp_ram_4_1_46))
+              (portRef DIB13 (instanceRef pdp_ram_4_1_46))
+              (portRef DIA13 (instanceRef pdp_ram_4_1_46))
+              (portRef DIB12 (instanceRef pdp_ram_4_1_46))
+              (portRef DIA12 (instanceRef pdp_ram_4_1_46))
+              (portRef DIB11 (instanceRef pdp_ram_4_1_46))
+              (portRef DIA11 (instanceRef pdp_ram_4_1_46))
+              (portRef DIB10 (instanceRef pdp_ram_4_1_46))
+              (portRef DIA10 (instanceRef pdp_ram_4_1_46))
+              (portRef DIB9 (instanceRef pdp_ram_4_1_46))
+              (portRef DIA9 (instanceRef pdp_ram_4_1_46))
+              (portRef DIB8 (instanceRef pdp_ram_4_1_46))
+              (portRef DIB7 (instanceRef pdp_ram_4_1_46))
+              (portRef DIB6 (instanceRef pdp_ram_4_1_46))
+              (portRef DIB5 (instanceRef pdp_ram_4_1_46))
+              (portRef DIB4 (instanceRef pdp_ram_4_1_46))
+              (portRef DIB3 (instanceRef pdp_ram_4_1_46))
+              (portRef DIB2 (instanceRef pdp_ram_4_1_46))
+              (portRef DIB1 (instanceRef pdp_ram_4_1_46))
+              (portRef DIB0 (instanceRef pdp_ram_4_1_46))
+              (portRef CSB2 (instanceRef pdp_ram_4_2_45))
+              (portRef CSA2 (instanceRef pdp_ram_4_2_45))
+              (portRef CSB1 (instanceRef pdp_ram_4_2_45))
+              (portRef CSA1 (instanceRef pdp_ram_4_2_45))
+              (portRef WEB (instanceRef pdp_ram_4_2_45))
+              (portRef ADB2 (instanceRef pdp_ram_4_2_45))
+              (portRef ADA2 (instanceRef pdp_ram_4_2_45))
+              (portRef ADB1 (instanceRef pdp_ram_4_2_45))
+              (portRef ADA1 (instanceRef pdp_ram_4_2_45))
+              (portRef ADB0 (instanceRef pdp_ram_4_2_45))
+              (portRef ADA0 (instanceRef pdp_ram_4_2_45))
+              (portRef DIB17 (instanceRef pdp_ram_4_2_45))
+              (portRef DIA17 (instanceRef pdp_ram_4_2_45))
+              (portRef DIB16 (instanceRef pdp_ram_4_2_45))
+              (portRef DIA16 (instanceRef pdp_ram_4_2_45))
+              (portRef DIB15 (instanceRef pdp_ram_4_2_45))
+              (portRef DIA15 (instanceRef pdp_ram_4_2_45))
+              (portRef DIB14 (instanceRef pdp_ram_4_2_45))
+              (portRef DIA14 (instanceRef pdp_ram_4_2_45))
+              (portRef DIB13 (instanceRef pdp_ram_4_2_45))
+              (portRef DIA13 (instanceRef pdp_ram_4_2_45))
+              (portRef DIB12 (instanceRef pdp_ram_4_2_45))
+              (portRef DIA12 (instanceRef pdp_ram_4_2_45))
+              (portRef DIB11 (instanceRef pdp_ram_4_2_45))
+              (portRef DIA11 (instanceRef pdp_ram_4_2_45))
+              (portRef DIB10 (instanceRef pdp_ram_4_2_45))
+              (portRef DIA10 (instanceRef pdp_ram_4_2_45))
+              (portRef DIB9 (instanceRef pdp_ram_4_2_45))
+              (portRef DIA9 (instanceRef pdp_ram_4_2_45))
+              (portRef DIB8 (instanceRef pdp_ram_4_2_45))
+              (portRef DIB7 (instanceRef pdp_ram_4_2_45))
+              (portRef DIB6 (instanceRef pdp_ram_4_2_45))
+              (portRef DIB5 (instanceRef pdp_ram_4_2_45))
+              (portRef DIB4 (instanceRef pdp_ram_4_2_45))
+              (portRef DIB3 (instanceRef pdp_ram_4_2_45))
+              (portRef DIB2 (instanceRef pdp_ram_4_2_45))
+              (portRef DIB1 (instanceRef pdp_ram_4_2_45))
+              (portRef DIB0 (instanceRef pdp_ram_4_2_45))
+              (portRef CSB2 (instanceRef pdp_ram_4_3_44))
+              (portRef CSA2 (instanceRef pdp_ram_4_3_44))
+              (portRef CSB1 (instanceRef pdp_ram_4_3_44))
+              (portRef CSA1 (instanceRef pdp_ram_4_3_44))
+              (portRef WEB (instanceRef pdp_ram_4_3_44))
+              (portRef ADB2 (instanceRef pdp_ram_4_3_44))
+              (portRef ADA2 (instanceRef pdp_ram_4_3_44))
+              (portRef ADB1 (instanceRef pdp_ram_4_3_44))
+              (portRef ADA1 (instanceRef pdp_ram_4_3_44))
+              (portRef ADB0 (instanceRef pdp_ram_4_3_44))
+              (portRef ADA0 (instanceRef pdp_ram_4_3_44))
+              (portRef DIB17 (instanceRef pdp_ram_4_3_44))
+              (portRef DIA17 (instanceRef pdp_ram_4_3_44))
+              (portRef DIB16 (instanceRef pdp_ram_4_3_44))
+              (portRef DIA16 (instanceRef pdp_ram_4_3_44))
+              (portRef DIB15 (instanceRef pdp_ram_4_3_44))
+              (portRef DIA15 (instanceRef pdp_ram_4_3_44))
+              (portRef DIB14 (instanceRef pdp_ram_4_3_44))
+              (portRef DIA14 (instanceRef pdp_ram_4_3_44))
+              (portRef DIB13 (instanceRef pdp_ram_4_3_44))
+              (portRef DIA13 (instanceRef pdp_ram_4_3_44))
+              (portRef DIB12 (instanceRef pdp_ram_4_3_44))
+              (portRef DIA12 (instanceRef pdp_ram_4_3_44))
+              (portRef DIB11 (instanceRef pdp_ram_4_3_44))
+              (portRef DIA11 (instanceRef pdp_ram_4_3_44))
+              (portRef DIB10 (instanceRef pdp_ram_4_3_44))
+              (portRef DIA10 (instanceRef pdp_ram_4_3_44))
+              (portRef DIB9 (instanceRef pdp_ram_4_3_44))
+              (portRef DIA9 (instanceRef pdp_ram_4_3_44))
+              (portRef DIB8 (instanceRef pdp_ram_4_3_44))
+              (portRef DIB7 (instanceRef pdp_ram_4_3_44))
+              (portRef DIB6 (instanceRef pdp_ram_4_3_44))
+              (portRef DIB5 (instanceRef pdp_ram_4_3_44))
+              (portRef DIB4 (instanceRef pdp_ram_4_3_44))
+              (portRef DIB3 (instanceRef pdp_ram_4_3_44))
+              (portRef DIB2 (instanceRef pdp_ram_4_3_44))
+              (portRef DIB1 (instanceRef pdp_ram_4_3_44))
+              (portRef DIB0 (instanceRef pdp_ram_4_3_44))
+              (portRef CSB2 (instanceRef pdp_ram_5_0_43))
+              (portRef CSA2 (instanceRef pdp_ram_5_0_43))
+              (portRef CSB1 (instanceRef pdp_ram_5_0_43))
+              (portRef CSA1 (instanceRef pdp_ram_5_0_43))
+              (portRef WEB (instanceRef pdp_ram_5_0_43))
+              (portRef ADB2 (instanceRef pdp_ram_5_0_43))
+              (portRef ADA2 (instanceRef pdp_ram_5_0_43))
+              (portRef ADB1 (instanceRef pdp_ram_5_0_43))
+              (portRef ADA1 (instanceRef pdp_ram_5_0_43))
+              (portRef ADB0 (instanceRef pdp_ram_5_0_43))
+              (portRef ADA0 (instanceRef pdp_ram_5_0_43))
+              (portRef DIB17 (instanceRef pdp_ram_5_0_43))
+              (portRef DIA17 (instanceRef pdp_ram_5_0_43))
+              (portRef DIB16 (instanceRef pdp_ram_5_0_43))
+              (portRef DIA16 (instanceRef pdp_ram_5_0_43))
+              (portRef DIB15 (instanceRef pdp_ram_5_0_43))
+              (portRef DIA15 (instanceRef pdp_ram_5_0_43))
+              (portRef DIB14 (instanceRef pdp_ram_5_0_43))
+              (portRef DIA14 (instanceRef pdp_ram_5_0_43))
+              (portRef DIB13 (instanceRef pdp_ram_5_0_43))
+              (portRef DIA13 (instanceRef pdp_ram_5_0_43))
+              (portRef DIB12 (instanceRef pdp_ram_5_0_43))
+              (portRef DIA12 (instanceRef pdp_ram_5_0_43))
+              (portRef DIB11 (instanceRef pdp_ram_5_0_43))
+              (portRef DIA11 (instanceRef pdp_ram_5_0_43))
+              (portRef DIB10 (instanceRef pdp_ram_5_0_43))
+              (portRef DIA10 (instanceRef pdp_ram_5_0_43))
+              (portRef DIB9 (instanceRef pdp_ram_5_0_43))
+              (portRef DIA9 (instanceRef pdp_ram_5_0_43))
+              (portRef DIB8 (instanceRef pdp_ram_5_0_43))
+              (portRef DIB7 (instanceRef pdp_ram_5_0_43))
+              (portRef DIB6 (instanceRef pdp_ram_5_0_43))
+              (portRef DIB5 (instanceRef pdp_ram_5_0_43))
+              (portRef DIB4 (instanceRef pdp_ram_5_0_43))
+              (portRef DIB3 (instanceRef pdp_ram_5_0_43))
+              (portRef DIB2 (instanceRef pdp_ram_5_0_43))
+              (portRef DIB1 (instanceRef pdp_ram_5_0_43))
+              (portRef DIB0 (instanceRef pdp_ram_5_0_43))
+              (portRef CSB2 (instanceRef pdp_ram_5_1_42))
+              (portRef CSA2 (instanceRef pdp_ram_5_1_42))
+              (portRef CSB1 (instanceRef pdp_ram_5_1_42))
+              (portRef CSA1 (instanceRef pdp_ram_5_1_42))
+              (portRef WEB (instanceRef pdp_ram_5_1_42))
+              (portRef ADB2 (instanceRef pdp_ram_5_1_42))
+              (portRef ADA2 (instanceRef pdp_ram_5_1_42))
+              (portRef ADB1 (instanceRef pdp_ram_5_1_42))
+              (portRef ADA1 (instanceRef pdp_ram_5_1_42))
+              (portRef ADB0 (instanceRef pdp_ram_5_1_42))
+              (portRef ADA0 (instanceRef pdp_ram_5_1_42))
+              (portRef DIB17 (instanceRef pdp_ram_5_1_42))
+              (portRef DIA17 (instanceRef pdp_ram_5_1_42))
+              (portRef DIB16 (instanceRef pdp_ram_5_1_42))
+              (portRef DIA16 (instanceRef pdp_ram_5_1_42))
+              (portRef DIB15 (instanceRef pdp_ram_5_1_42))
+              (portRef DIA15 (instanceRef pdp_ram_5_1_42))
+              (portRef DIB14 (instanceRef pdp_ram_5_1_42))
+              (portRef DIA14 (instanceRef pdp_ram_5_1_42))
+              (portRef DIB13 (instanceRef pdp_ram_5_1_42))
+              (portRef DIA13 (instanceRef pdp_ram_5_1_42))
+              (portRef DIB12 (instanceRef pdp_ram_5_1_42))
+              (portRef DIA12 (instanceRef pdp_ram_5_1_42))
+              (portRef DIB11 (instanceRef pdp_ram_5_1_42))
+              (portRef DIA11 (instanceRef pdp_ram_5_1_42))
+              (portRef DIB10 (instanceRef pdp_ram_5_1_42))
+              (portRef DIA10 (instanceRef pdp_ram_5_1_42))
+              (portRef DIB9 (instanceRef pdp_ram_5_1_42))
+              (portRef DIA9 (instanceRef pdp_ram_5_1_42))
+              (portRef DIB8 (instanceRef pdp_ram_5_1_42))
+              (portRef DIB7 (instanceRef pdp_ram_5_1_42))
+              (portRef DIB6 (instanceRef pdp_ram_5_1_42))
+              (portRef DIB5 (instanceRef pdp_ram_5_1_42))
+              (portRef DIB4 (instanceRef pdp_ram_5_1_42))
+              (portRef DIB3 (instanceRef pdp_ram_5_1_42))
+              (portRef DIB2 (instanceRef pdp_ram_5_1_42))
+              (portRef DIB1 (instanceRef pdp_ram_5_1_42))
+              (portRef DIB0 (instanceRef pdp_ram_5_1_42))
+              (portRef CSB2 (instanceRef pdp_ram_5_2_41))
+              (portRef CSA2 (instanceRef pdp_ram_5_2_41))
+              (portRef CSB1 (instanceRef pdp_ram_5_2_41))
+              (portRef CSA1 (instanceRef pdp_ram_5_2_41))
+              (portRef WEB (instanceRef pdp_ram_5_2_41))
+              (portRef ADB2 (instanceRef pdp_ram_5_2_41))
+              (portRef ADA2 (instanceRef pdp_ram_5_2_41))
+              (portRef ADB1 (instanceRef pdp_ram_5_2_41))
+              (portRef ADA1 (instanceRef pdp_ram_5_2_41))
+              (portRef ADB0 (instanceRef pdp_ram_5_2_41))
+              (portRef ADA0 (instanceRef pdp_ram_5_2_41))
+              (portRef DIB17 (instanceRef pdp_ram_5_2_41))
+              (portRef DIA17 (instanceRef pdp_ram_5_2_41))
+              (portRef DIB16 (instanceRef pdp_ram_5_2_41))
+              (portRef DIA16 (instanceRef pdp_ram_5_2_41))
+              (portRef DIB15 (instanceRef pdp_ram_5_2_41))
+              (portRef DIA15 (instanceRef pdp_ram_5_2_41))
+              (portRef DIB14 (instanceRef pdp_ram_5_2_41))
+              (portRef DIA14 (instanceRef pdp_ram_5_2_41))
+              (portRef DIB13 (instanceRef pdp_ram_5_2_41))
+              (portRef DIA13 (instanceRef pdp_ram_5_2_41))
+              (portRef DIB12 (instanceRef pdp_ram_5_2_41))
+              (portRef DIA12 (instanceRef pdp_ram_5_2_41))
+              (portRef DIB11 (instanceRef pdp_ram_5_2_41))
+              (portRef DIA11 (instanceRef pdp_ram_5_2_41))
+              (portRef DIB10 (instanceRef pdp_ram_5_2_41))
+              (portRef DIA10 (instanceRef pdp_ram_5_2_41))
+              (portRef DIB9 (instanceRef pdp_ram_5_2_41))
+              (portRef DIA9 (instanceRef pdp_ram_5_2_41))
+              (portRef DIB8 (instanceRef pdp_ram_5_2_41))
+              (portRef DIB7 (instanceRef pdp_ram_5_2_41))
+              (portRef DIB6 (instanceRef pdp_ram_5_2_41))
+              (portRef DIB5 (instanceRef pdp_ram_5_2_41))
+              (portRef DIB4 (instanceRef pdp_ram_5_2_41))
+              (portRef DIB3 (instanceRef pdp_ram_5_2_41))
+              (portRef DIB2 (instanceRef pdp_ram_5_2_41))
+              (portRef DIB1 (instanceRef pdp_ram_5_2_41))
+              (portRef DIB0 (instanceRef pdp_ram_5_2_41))
+              (portRef CSB2 (instanceRef pdp_ram_5_3_40))
+              (portRef CSA2 (instanceRef pdp_ram_5_3_40))
+              (portRef CSB1 (instanceRef pdp_ram_5_3_40))
+              (portRef CSA1 (instanceRef pdp_ram_5_3_40))
+              (portRef WEB (instanceRef pdp_ram_5_3_40))
+              (portRef ADB2 (instanceRef pdp_ram_5_3_40))
+              (portRef ADA2 (instanceRef pdp_ram_5_3_40))
+              (portRef ADB1 (instanceRef pdp_ram_5_3_40))
+              (portRef ADA1 (instanceRef pdp_ram_5_3_40))
+              (portRef ADB0 (instanceRef pdp_ram_5_3_40))
+              (portRef ADA0 (instanceRef pdp_ram_5_3_40))
+              (portRef DIB17 (instanceRef pdp_ram_5_3_40))
+              (portRef DIA17 (instanceRef pdp_ram_5_3_40))
+              (portRef DIB16 (instanceRef pdp_ram_5_3_40))
+              (portRef DIA16 (instanceRef pdp_ram_5_3_40))
+              (portRef DIB15 (instanceRef pdp_ram_5_3_40))
+              (portRef DIA15 (instanceRef pdp_ram_5_3_40))
+              (portRef DIB14 (instanceRef pdp_ram_5_3_40))
+              (portRef DIA14 (instanceRef pdp_ram_5_3_40))
+              (portRef DIB13 (instanceRef pdp_ram_5_3_40))
+              (portRef DIA13 (instanceRef pdp_ram_5_3_40))
+              (portRef DIB12 (instanceRef pdp_ram_5_3_40))
+              (portRef DIA12 (instanceRef pdp_ram_5_3_40))
+              (portRef DIB11 (instanceRef pdp_ram_5_3_40))
+              (portRef DIA11 (instanceRef pdp_ram_5_3_40))
+              (portRef DIB10 (instanceRef pdp_ram_5_3_40))
+              (portRef DIA10 (instanceRef pdp_ram_5_3_40))
+              (portRef DIB9 (instanceRef pdp_ram_5_3_40))
+              (portRef DIA9 (instanceRef pdp_ram_5_3_40))
+              (portRef DIB8 (instanceRef pdp_ram_5_3_40))
+              (portRef DIB7 (instanceRef pdp_ram_5_3_40))
+              (portRef DIB6 (instanceRef pdp_ram_5_3_40))
+              (portRef DIB5 (instanceRef pdp_ram_5_3_40))
+              (portRef DIB4 (instanceRef pdp_ram_5_3_40))
+              (portRef DIB3 (instanceRef pdp_ram_5_3_40))
+              (portRef DIB2 (instanceRef pdp_ram_5_3_40))
+              (portRef DIB1 (instanceRef pdp_ram_5_3_40))
+              (portRef DIB0 (instanceRef pdp_ram_5_3_40))
+              (portRef CSB2 (instanceRef pdp_ram_6_0_39))
+              (portRef CSA2 (instanceRef pdp_ram_6_0_39))
+              (portRef CSB1 (instanceRef pdp_ram_6_0_39))
+              (portRef CSA1 (instanceRef pdp_ram_6_0_39))
+              (portRef WEB (instanceRef pdp_ram_6_0_39))
+              (portRef ADB2 (instanceRef pdp_ram_6_0_39))
+              (portRef ADA2 (instanceRef pdp_ram_6_0_39))
+              (portRef ADB1 (instanceRef pdp_ram_6_0_39))
+              (portRef ADA1 (instanceRef pdp_ram_6_0_39))
+              (portRef ADB0 (instanceRef pdp_ram_6_0_39))
+              (portRef ADA0 (instanceRef pdp_ram_6_0_39))
+              (portRef DIB17 (instanceRef pdp_ram_6_0_39))
+              (portRef DIA17 (instanceRef pdp_ram_6_0_39))
+              (portRef DIB16 (instanceRef pdp_ram_6_0_39))
+              (portRef DIA16 (instanceRef pdp_ram_6_0_39))
+              (portRef DIB15 (instanceRef pdp_ram_6_0_39))
+              (portRef DIA15 (instanceRef pdp_ram_6_0_39))
+              (portRef DIB14 (instanceRef pdp_ram_6_0_39))
+              (portRef DIA14 (instanceRef pdp_ram_6_0_39))
+              (portRef DIB13 (instanceRef pdp_ram_6_0_39))
+              (portRef DIA13 (instanceRef pdp_ram_6_0_39))
+              (portRef DIB12 (instanceRef pdp_ram_6_0_39))
+              (portRef DIA12 (instanceRef pdp_ram_6_0_39))
+              (portRef DIB11 (instanceRef pdp_ram_6_0_39))
+              (portRef DIA11 (instanceRef pdp_ram_6_0_39))
+              (portRef DIB10 (instanceRef pdp_ram_6_0_39))
+              (portRef DIA10 (instanceRef pdp_ram_6_0_39))
+              (portRef DIB9 (instanceRef pdp_ram_6_0_39))
+              (portRef DIA9 (instanceRef pdp_ram_6_0_39))
+              (portRef DIB8 (instanceRef pdp_ram_6_0_39))
+              (portRef DIB7 (instanceRef pdp_ram_6_0_39))
+              (portRef DIB6 (instanceRef pdp_ram_6_0_39))
+              (portRef DIB5 (instanceRef pdp_ram_6_0_39))
+              (portRef DIB4 (instanceRef pdp_ram_6_0_39))
+              (portRef DIB3 (instanceRef pdp_ram_6_0_39))
+              (portRef DIB2 (instanceRef pdp_ram_6_0_39))
+              (portRef DIB1 (instanceRef pdp_ram_6_0_39))
+              (portRef DIB0 (instanceRef pdp_ram_6_0_39))
+              (portRef CSB2 (instanceRef pdp_ram_6_1_38))
+              (portRef CSA2 (instanceRef pdp_ram_6_1_38))
+              (portRef CSB1 (instanceRef pdp_ram_6_1_38))
+              (portRef CSA1 (instanceRef pdp_ram_6_1_38))
+              (portRef WEB (instanceRef pdp_ram_6_1_38))
+              (portRef ADB2 (instanceRef pdp_ram_6_1_38))
+              (portRef ADA2 (instanceRef pdp_ram_6_1_38))
+              (portRef ADB1 (instanceRef pdp_ram_6_1_38))
+              (portRef ADA1 (instanceRef pdp_ram_6_1_38))
+              (portRef ADB0 (instanceRef pdp_ram_6_1_38))
+              (portRef ADA0 (instanceRef pdp_ram_6_1_38))
+              (portRef DIB17 (instanceRef pdp_ram_6_1_38))
+              (portRef DIA17 (instanceRef pdp_ram_6_1_38))
+              (portRef DIB16 (instanceRef pdp_ram_6_1_38))
+              (portRef DIA16 (instanceRef pdp_ram_6_1_38))
+              (portRef DIB15 (instanceRef pdp_ram_6_1_38))
+              (portRef DIA15 (instanceRef pdp_ram_6_1_38))
+              (portRef DIB14 (instanceRef pdp_ram_6_1_38))
+              (portRef DIA14 (instanceRef pdp_ram_6_1_38))
+              (portRef DIB13 (instanceRef pdp_ram_6_1_38))
+              (portRef DIA13 (instanceRef pdp_ram_6_1_38))
+              (portRef DIB12 (instanceRef pdp_ram_6_1_38))
+              (portRef DIA12 (instanceRef pdp_ram_6_1_38))
+              (portRef DIB11 (instanceRef pdp_ram_6_1_38))
+              (portRef DIA11 (instanceRef pdp_ram_6_1_38))
+              (portRef DIB10 (instanceRef pdp_ram_6_1_38))
+              (portRef DIA10 (instanceRef pdp_ram_6_1_38))
+              (portRef DIB9 (instanceRef pdp_ram_6_1_38))
+              (portRef DIA9 (instanceRef pdp_ram_6_1_38))
+              (portRef DIB8 (instanceRef pdp_ram_6_1_38))
+              (portRef DIB7 (instanceRef pdp_ram_6_1_38))
+              (portRef DIB6 (instanceRef pdp_ram_6_1_38))
+              (portRef DIB5 (instanceRef pdp_ram_6_1_38))
+              (portRef DIB4 (instanceRef pdp_ram_6_1_38))
+              (portRef DIB3 (instanceRef pdp_ram_6_1_38))
+              (portRef DIB2 (instanceRef pdp_ram_6_1_38))
+              (portRef DIB1 (instanceRef pdp_ram_6_1_38))
+              (portRef DIB0 (instanceRef pdp_ram_6_1_38))
+              (portRef CSB2 (instanceRef pdp_ram_6_2_37))
+              (portRef CSA2 (instanceRef pdp_ram_6_2_37))
+              (portRef CSB1 (instanceRef pdp_ram_6_2_37))
+              (portRef CSA1 (instanceRef pdp_ram_6_2_37))
+              (portRef WEB (instanceRef pdp_ram_6_2_37))
+              (portRef ADB2 (instanceRef pdp_ram_6_2_37))
+              (portRef ADA2 (instanceRef pdp_ram_6_2_37))
+              (portRef ADB1 (instanceRef pdp_ram_6_2_37))
+              (portRef ADA1 (instanceRef pdp_ram_6_2_37))
+              (portRef ADB0 (instanceRef pdp_ram_6_2_37))
+              (portRef ADA0 (instanceRef pdp_ram_6_2_37))
+              (portRef DIB17 (instanceRef pdp_ram_6_2_37))
+              (portRef DIA17 (instanceRef pdp_ram_6_2_37))
+              (portRef DIB16 (instanceRef pdp_ram_6_2_37))
+              (portRef DIA16 (instanceRef pdp_ram_6_2_37))
+              (portRef DIB15 (instanceRef pdp_ram_6_2_37))
+              (portRef DIA15 (instanceRef pdp_ram_6_2_37))
+              (portRef DIB14 (instanceRef pdp_ram_6_2_37))
+              (portRef DIA14 (instanceRef pdp_ram_6_2_37))
+              (portRef DIB13 (instanceRef pdp_ram_6_2_37))
+              (portRef DIA13 (instanceRef pdp_ram_6_2_37))
+              (portRef DIB12 (instanceRef pdp_ram_6_2_37))
+              (portRef DIA12 (instanceRef pdp_ram_6_2_37))
+              (portRef DIB11 (instanceRef pdp_ram_6_2_37))
+              (portRef DIA11 (instanceRef pdp_ram_6_2_37))
+              (portRef DIB10 (instanceRef pdp_ram_6_2_37))
+              (portRef DIA10 (instanceRef pdp_ram_6_2_37))
+              (portRef DIB9 (instanceRef pdp_ram_6_2_37))
+              (portRef DIA9 (instanceRef pdp_ram_6_2_37))
+              (portRef DIB8 (instanceRef pdp_ram_6_2_37))
+              (portRef DIB7 (instanceRef pdp_ram_6_2_37))
+              (portRef DIB6 (instanceRef pdp_ram_6_2_37))
+              (portRef DIB5 (instanceRef pdp_ram_6_2_37))
+              (portRef DIB4 (instanceRef pdp_ram_6_2_37))
+              (portRef DIB3 (instanceRef pdp_ram_6_2_37))
+              (portRef DIB2 (instanceRef pdp_ram_6_2_37))
+              (portRef DIB1 (instanceRef pdp_ram_6_2_37))
+              (portRef DIB0 (instanceRef pdp_ram_6_2_37))
+              (portRef CSB2 (instanceRef pdp_ram_6_3_36))
+              (portRef CSA2 (instanceRef pdp_ram_6_3_36))
+              (portRef CSB1 (instanceRef pdp_ram_6_3_36))
+              (portRef CSA1 (instanceRef pdp_ram_6_3_36))
+              (portRef WEB (instanceRef pdp_ram_6_3_36))
+              (portRef ADB2 (instanceRef pdp_ram_6_3_36))
+              (portRef ADA2 (instanceRef pdp_ram_6_3_36))
+              (portRef ADB1 (instanceRef pdp_ram_6_3_36))
+              (portRef ADA1 (instanceRef pdp_ram_6_3_36))
+              (portRef ADB0 (instanceRef pdp_ram_6_3_36))
+              (portRef ADA0 (instanceRef pdp_ram_6_3_36))
+              (portRef DIB17 (instanceRef pdp_ram_6_3_36))
+              (portRef DIA17 (instanceRef pdp_ram_6_3_36))
+              (portRef DIB16 (instanceRef pdp_ram_6_3_36))
+              (portRef DIA16 (instanceRef pdp_ram_6_3_36))
+              (portRef DIB15 (instanceRef pdp_ram_6_3_36))
+              (portRef DIA15 (instanceRef pdp_ram_6_3_36))
+              (portRef DIB14 (instanceRef pdp_ram_6_3_36))
+              (portRef DIA14 (instanceRef pdp_ram_6_3_36))
+              (portRef DIB13 (instanceRef pdp_ram_6_3_36))
+              (portRef DIA13 (instanceRef pdp_ram_6_3_36))
+              (portRef DIB12 (instanceRef pdp_ram_6_3_36))
+              (portRef DIA12 (instanceRef pdp_ram_6_3_36))
+              (portRef DIB11 (instanceRef pdp_ram_6_3_36))
+              (portRef DIA11 (instanceRef pdp_ram_6_3_36))
+              (portRef DIB10 (instanceRef pdp_ram_6_3_36))
+              (portRef DIA10 (instanceRef pdp_ram_6_3_36))
+              (portRef DIB9 (instanceRef pdp_ram_6_3_36))
+              (portRef DIA9 (instanceRef pdp_ram_6_3_36))
+              (portRef DIB8 (instanceRef pdp_ram_6_3_36))
+              (portRef DIB7 (instanceRef pdp_ram_6_3_36))
+              (portRef DIB6 (instanceRef pdp_ram_6_3_36))
+              (portRef DIB5 (instanceRef pdp_ram_6_3_36))
+              (portRef DIB4 (instanceRef pdp_ram_6_3_36))
+              (portRef DIB3 (instanceRef pdp_ram_6_3_36))
+              (portRef DIB2 (instanceRef pdp_ram_6_3_36))
+              (portRef DIB1 (instanceRef pdp_ram_6_3_36))
+              (portRef DIB0 (instanceRef pdp_ram_6_3_36))
+              (portRef CSB2 (instanceRef pdp_ram_7_0_35))
+              (portRef CSA2 (instanceRef pdp_ram_7_0_35))
+              (portRef CSB1 (instanceRef pdp_ram_7_0_35))
+              (portRef CSA1 (instanceRef pdp_ram_7_0_35))
+              (portRef WEB (instanceRef pdp_ram_7_0_35))
+              (portRef ADB2 (instanceRef pdp_ram_7_0_35))
+              (portRef ADA2 (instanceRef pdp_ram_7_0_35))
+              (portRef ADB1 (instanceRef pdp_ram_7_0_35))
+              (portRef ADA1 (instanceRef pdp_ram_7_0_35))
+              (portRef ADB0 (instanceRef pdp_ram_7_0_35))
+              (portRef ADA0 (instanceRef pdp_ram_7_0_35))
+              (portRef DIB17 (instanceRef pdp_ram_7_0_35))
+              (portRef DIA17 (instanceRef pdp_ram_7_0_35))
+              (portRef DIB16 (instanceRef pdp_ram_7_0_35))
+              (portRef DIA16 (instanceRef pdp_ram_7_0_35))
+              (portRef DIB15 (instanceRef pdp_ram_7_0_35))
+              (portRef DIA15 (instanceRef pdp_ram_7_0_35))
+              (portRef DIB14 (instanceRef pdp_ram_7_0_35))
+              (portRef DIA14 (instanceRef pdp_ram_7_0_35))
+              (portRef DIB13 (instanceRef pdp_ram_7_0_35))
+              (portRef DIA13 (instanceRef pdp_ram_7_0_35))
+              (portRef DIB12 (instanceRef pdp_ram_7_0_35))
+              (portRef DIA12 (instanceRef pdp_ram_7_0_35))
+              (portRef DIB11 (instanceRef pdp_ram_7_0_35))
+              (portRef DIA11 (instanceRef pdp_ram_7_0_35))
+              (portRef DIB10 (instanceRef pdp_ram_7_0_35))
+              (portRef DIA10 (instanceRef pdp_ram_7_0_35))
+              (portRef DIB9 (instanceRef pdp_ram_7_0_35))
+              (portRef DIA9 (instanceRef pdp_ram_7_0_35))
+              (portRef DIB8 (instanceRef pdp_ram_7_0_35))
+              (portRef DIB7 (instanceRef pdp_ram_7_0_35))
+              (portRef DIB6 (instanceRef pdp_ram_7_0_35))
+              (portRef DIB5 (instanceRef pdp_ram_7_0_35))
+              (portRef DIB4 (instanceRef pdp_ram_7_0_35))
+              (portRef DIB3 (instanceRef pdp_ram_7_0_35))
+              (portRef DIB2 (instanceRef pdp_ram_7_0_35))
+              (portRef DIB1 (instanceRef pdp_ram_7_0_35))
+              (portRef DIB0 (instanceRef pdp_ram_7_0_35))
+              (portRef CSB2 (instanceRef pdp_ram_7_1_34))
+              (portRef CSA2 (instanceRef pdp_ram_7_1_34))
+              (portRef CSB1 (instanceRef pdp_ram_7_1_34))
+              (portRef CSA1 (instanceRef pdp_ram_7_1_34))
+              (portRef WEB (instanceRef pdp_ram_7_1_34))
+              (portRef ADB2 (instanceRef pdp_ram_7_1_34))
+              (portRef ADA2 (instanceRef pdp_ram_7_1_34))
+              (portRef ADB1 (instanceRef pdp_ram_7_1_34))
+              (portRef ADA1 (instanceRef pdp_ram_7_1_34))
+              (portRef ADB0 (instanceRef pdp_ram_7_1_34))
+              (portRef ADA0 (instanceRef pdp_ram_7_1_34))
+              (portRef DIB17 (instanceRef pdp_ram_7_1_34))
+              (portRef DIA17 (instanceRef pdp_ram_7_1_34))
+              (portRef DIB16 (instanceRef pdp_ram_7_1_34))
+              (portRef DIA16 (instanceRef pdp_ram_7_1_34))
+              (portRef DIB15 (instanceRef pdp_ram_7_1_34))
+              (portRef DIA15 (instanceRef pdp_ram_7_1_34))
+              (portRef DIB14 (instanceRef pdp_ram_7_1_34))
+              (portRef DIA14 (instanceRef pdp_ram_7_1_34))
+              (portRef DIB13 (instanceRef pdp_ram_7_1_34))
+              (portRef DIA13 (instanceRef pdp_ram_7_1_34))
+              (portRef DIB12 (instanceRef pdp_ram_7_1_34))
+              (portRef DIA12 (instanceRef pdp_ram_7_1_34))
+              (portRef DIB11 (instanceRef pdp_ram_7_1_34))
+              (portRef DIA11 (instanceRef pdp_ram_7_1_34))
+              (portRef DIB10 (instanceRef pdp_ram_7_1_34))
+              (portRef DIA10 (instanceRef pdp_ram_7_1_34))
+              (portRef DIB9 (instanceRef pdp_ram_7_1_34))
+              (portRef DIA9 (instanceRef pdp_ram_7_1_34))
+              (portRef DIB8 (instanceRef pdp_ram_7_1_34))
+              (portRef DIB7 (instanceRef pdp_ram_7_1_34))
+              (portRef DIB6 (instanceRef pdp_ram_7_1_34))
+              (portRef DIB5 (instanceRef pdp_ram_7_1_34))
+              (portRef DIB4 (instanceRef pdp_ram_7_1_34))
+              (portRef DIB3 (instanceRef pdp_ram_7_1_34))
+              (portRef DIB2 (instanceRef pdp_ram_7_1_34))
+              (portRef DIB1 (instanceRef pdp_ram_7_1_34))
+              (portRef DIB0 (instanceRef pdp_ram_7_1_34))
+              (portRef CSB2 (instanceRef pdp_ram_7_2_33))
+              (portRef CSA2 (instanceRef pdp_ram_7_2_33))
+              (portRef CSB1 (instanceRef pdp_ram_7_2_33))
+              (portRef CSA1 (instanceRef pdp_ram_7_2_33))
+              (portRef WEB (instanceRef pdp_ram_7_2_33))
+              (portRef ADB2 (instanceRef pdp_ram_7_2_33))
+              (portRef ADA2 (instanceRef pdp_ram_7_2_33))
+              (portRef ADB1 (instanceRef pdp_ram_7_2_33))
+              (portRef ADA1 (instanceRef pdp_ram_7_2_33))
+              (portRef ADB0 (instanceRef pdp_ram_7_2_33))
+              (portRef ADA0 (instanceRef pdp_ram_7_2_33))
+              (portRef DIB17 (instanceRef pdp_ram_7_2_33))
+              (portRef DIA17 (instanceRef pdp_ram_7_2_33))
+              (portRef DIB16 (instanceRef pdp_ram_7_2_33))
+              (portRef DIA16 (instanceRef pdp_ram_7_2_33))
+              (portRef DIB15 (instanceRef pdp_ram_7_2_33))
+              (portRef DIA15 (instanceRef pdp_ram_7_2_33))
+              (portRef DIB14 (instanceRef pdp_ram_7_2_33))
+              (portRef DIA14 (instanceRef pdp_ram_7_2_33))
+              (portRef DIB13 (instanceRef pdp_ram_7_2_33))
+              (portRef DIA13 (instanceRef pdp_ram_7_2_33))
+              (portRef DIB12 (instanceRef pdp_ram_7_2_33))
+              (portRef DIA12 (instanceRef pdp_ram_7_2_33))
+              (portRef DIB11 (instanceRef pdp_ram_7_2_33))
+              (portRef DIA11 (instanceRef pdp_ram_7_2_33))
+              (portRef DIB10 (instanceRef pdp_ram_7_2_33))
+              (portRef DIA10 (instanceRef pdp_ram_7_2_33))
+              (portRef DIB9 (instanceRef pdp_ram_7_2_33))
+              (portRef DIA9 (instanceRef pdp_ram_7_2_33))
+              (portRef DIB8 (instanceRef pdp_ram_7_2_33))
+              (portRef DIB7 (instanceRef pdp_ram_7_2_33))
+              (portRef DIB6 (instanceRef pdp_ram_7_2_33))
+              (portRef DIB5 (instanceRef pdp_ram_7_2_33))
+              (portRef DIB4 (instanceRef pdp_ram_7_2_33))
+              (portRef DIB3 (instanceRef pdp_ram_7_2_33))
+              (portRef DIB2 (instanceRef pdp_ram_7_2_33))
+              (portRef DIB1 (instanceRef pdp_ram_7_2_33))
+              (portRef DIB0 (instanceRef pdp_ram_7_2_33))
+              (portRef CSB2 (instanceRef pdp_ram_7_3_32))
+              (portRef CSA2 (instanceRef pdp_ram_7_3_32))
+              (portRef CSB1 (instanceRef pdp_ram_7_3_32))
+              (portRef CSA1 (instanceRef pdp_ram_7_3_32))
+              (portRef WEB (instanceRef pdp_ram_7_3_32))
+              (portRef ADB2 (instanceRef pdp_ram_7_3_32))
+              (portRef ADA2 (instanceRef pdp_ram_7_3_32))
+              (portRef ADB1 (instanceRef pdp_ram_7_3_32))
+              (portRef ADA1 (instanceRef pdp_ram_7_3_32))
+              (portRef ADB0 (instanceRef pdp_ram_7_3_32))
+              (portRef ADA0 (instanceRef pdp_ram_7_3_32))
+              (portRef DIB17 (instanceRef pdp_ram_7_3_32))
+              (portRef DIA17 (instanceRef pdp_ram_7_3_32))
+              (portRef DIB16 (instanceRef pdp_ram_7_3_32))
+              (portRef DIA16 (instanceRef pdp_ram_7_3_32))
+              (portRef DIB15 (instanceRef pdp_ram_7_3_32))
+              (portRef DIA15 (instanceRef pdp_ram_7_3_32))
+              (portRef DIB14 (instanceRef pdp_ram_7_3_32))
+              (portRef DIA14 (instanceRef pdp_ram_7_3_32))
+              (portRef DIB13 (instanceRef pdp_ram_7_3_32))
+              (portRef DIA13 (instanceRef pdp_ram_7_3_32))
+              (portRef DIB12 (instanceRef pdp_ram_7_3_32))
+              (portRef DIA12 (instanceRef pdp_ram_7_3_32))
+              (portRef DIB11 (instanceRef pdp_ram_7_3_32))
+              (portRef DIA11 (instanceRef pdp_ram_7_3_32))
+              (portRef DIB10 (instanceRef pdp_ram_7_3_32))
+              (portRef DIA10 (instanceRef pdp_ram_7_3_32))
+              (portRef DIB9 (instanceRef pdp_ram_7_3_32))
+              (portRef DIA9 (instanceRef pdp_ram_7_3_32))
+              (portRef DIB8 (instanceRef pdp_ram_7_3_32))
+              (portRef DIB7 (instanceRef pdp_ram_7_3_32))
+              (portRef DIB6 (instanceRef pdp_ram_7_3_32))
+              (portRef DIB5 (instanceRef pdp_ram_7_3_32))
+              (portRef DIB4 (instanceRef pdp_ram_7_3_32))
+              (portRef DIB3 (instanceRef pdp_ram_7_3_32))
+              (portRef DIB2 (instanceRef pdp_ram_7_3_32))
+              (portRef DIB1 (instanceRef pdp_ram_7_3_32))
+              (portRef DIB0 (instanceRef pdp_ram_7_3_32))
+              (portRef CSB2 (instanceRef pdp_ram_8_0_31))
+              (portRef CSA2 (instanceRef pdp_ram_8_0_31))
+              (portRef CSB1 (instanceRef pdp_ram_8_0_31))
+              (portRef CSA1 (instanceRef pdp_ram_8_0_31))
+              (portRef WEB (instanceRef pdp_ram_8_0_31))
+              (portRef ADB2 (instanceRef pdp_ram_8_0_31))
+              (portRef ADA2 (instanceRef pdp_ram_8_0_31))
+              (portRef ADB1 (instanceRef pdp_ram_8_0_31))
+              (portRef ADA1 (instanceRef pdp_ram_8_0_31))
+              (portRef ADB0 (instanceRef pdp_ram_8_0_31))
+              (portRef ADA0 (instanceRef pdp_ram_8_0_31))
+              (portRef DIB17 (instanceRef pdp_ram_8_0_31))
+              (portRef DIA17 (instanceRef pdp_ram_8_0_31))
+              (portRef DIB16 (instanceRef pdp_ram_8_0_31))
+              (portRef DIA16 (instanceRef pdp_ram_8_0_31))
+              (portRef DIB15 (instanceRef pdp_ram_8_0_31))
+              (portRef DIA15 (instanceRef pdp_ram_8_0_31))
+              (portRef DIB14 (instanceRef pdp_ram_8_0_31))
+              (portRef DIA14 (instanceRef pdp_ram_8_0_31))
+              (portRef DIB13 (instanceRef pdp_ram_8_0_31))
+              (portRef DIA13 (instanceRef pdp_ram_8_0_31))
+              (portRef DIB12 (instanceRef pdp_ram_8_0_31))
+              (portRef DIA12 (instanceRef pdp_ram_8_0_31))
+              (portRef DIB11 (instanceRef pdp_ram_8_0_31))
+              (portRef DIA11 (instanceRef pdp_ram_8_0_31))
+              (portRef DIB10 (instanceRef pdp_ram_8_0_31))
+              (portRef DIA10 (instanceRef pdp_ram_8_0_31))
+              (portRef DIB9 (instanceRef pdp_ram_8_0_31))
+              (portRef DIA9 (instanceRef pdp_ram_8_0_31))
+              (portRef DIB8 (instanceRef pdp_ram_8_0_31))
+              (portRef DIB7 (instanceRef pdp_ram_8_0_31))
+              (portRef DIB6 (instanceRef pdp_ram_8_0_31))
+              (portRef DIB5 (instanceRef pdp_ram_8_0_31))
+              (portRef DIB4 (instanceRef pdp_ram_8_0_31))
+              (portRef DIB3 (instanceRef pdp_ram_8_0_31))
+              (portRef DIB2 (instanceRef pdp_ram_8_0_31))
+              (portRef DIB1 (instanceRef pdp_ram_8_0_31))
+              (portRef DIB0 (instanceRef pdp_ram_8_0_31))
+              (portRef CSB2 (instanceRef pdp_ram_8_1_30))
+              (portRef CSA2 (instanceRef pdp_ram_8_1_30))
+              (portRef CSB1 (instanceRef pdp_ram_8_1_30))
+              (portRef CSA1 (instanceRef pdp_ram_8_1_30))
+              (portRef WEB (instanceRef pdp_ram_8_1_30))
+              (portRef ADB2 (instanceRef pdp_ram_8_1_30))
+              (portRef ADA2 (instanceRef pdp_ram_8_1_30))
+              (portRef ADB1 (instanceRef pdp_ram_8_1_30))
+              (portRef ADA1 (instanceRef pdp_ram_8_1_30))
+              (portRef ADB0 (instanceRef pdp_ram_8_1_30))
+              (portRef ADA0 (instanceRef pdp_ram_8_1_30))
+              (portRef DIB17 (instanceRef pdp_ram_8_1_30))
+              (portRef DIA17 (instanceRef pdp_ram_8_1_30))
+              (portRef DIB16 (instanceRef pdp_ram_8_1_30))
+              (portRef DIA16 (instanceRef pdp_ram_8_1_30))
+              (portRef DIB15 (instanceRef pdp_ram_8_1_30))
+              (portRef DIA15 (instanceRef pdp_ram_8_1_30))
+              (portRef DIB14 (instanceRef pdp_ram_8_1_30))
+              (portRef DIA14 (instanceRef pdp_ram_8_1_30))
+              (portRef DIB13 (instanceRef pdp_ram_8_1_30))
+              (portRef DIA13 (instanceRef pdp_ram_8_1_30))
+              (portRef DIB12 (instanceRef pdp_ram_8_1_30))
+              (portRef DIA12 (instanceRef pdp_ram_8_1_30))
+              (portRef DIB11 (instanceRef pdp_ram_8_1_30))
+              (portRef DIA11 (instanceRef pdp_ram_8_1_30))
+              (portRef DIB10 (instanceRef pdp_ram_8_1_30))
+              (portRef DIA10 (instanceRef pdp_ram_8_1_30))
+              (portRef DIB9 (instanceRef pdp_ram_8_1_30))
+              (portRef DIA9 (instanceRef pdp_ram_8_1_30))
+              (portRef DIB8 (instanceRef pdp_ram_8_1_30))
+              (portRef DIB7 (instanceRef pdp_ram_8_1_30))
+              (portRef DIB6 (instanceRef pdp_ram_8_1_30))
+              (portRef DIB5 (instanceRef pdp_ram_8_1_30))
+              (portRef DIB4 (instanceRef pdp_ram_8_1_30))
+              (portRef DIB3 (instanceRef pdp_ram_8_1_30))
+              (portRef DIB2 (instanceRef pdp_ram_8_1_30))
+              (portRef DIB1 (instanceRef pdp_ram_8_1_30))
+              (portRef DIB0 (instanceRef pdp_ram_8_1_30))
+              (portRef CSB2 (instanceRef pdp_ram_8_2_29))
+              (portRef CSA2 (instanceRef pdp_ram_8_2_29))
+              (portRef CSB1 (instanceRef pdp_ram_8_2_29))
+              (portRef CSA1 (instanceRef pdp_ram_8_2_29))
+              (portRef WEB (instanceRef pdp_ram_8_2_29))
+              (portRef ADB2 (instanceRef pdp_ram_8_2_29))
+              (portRef ADA2 (instanceRef pdp_ram_8_2_29))
+              (portRef ADB1 (instanceRef pdp_ram_8_2_29))
+              (portRef ADA1 (instanceRef pdp_ram_8_2_29))
+              (portRef ADB0 (instanceRef pdp_ram_8_2_29))
+              (portRef ADA0 (instanceRef pdp_ram_8_2_29))
+              (portRef DIB17 (instanceRef pdp_ram_8_2_29))
+              (portRef DIA17 (instanceRef pdp_ram_8_2_29))
+              (portRef DIB16 (instanceRef pdp_ram_8_2_29))
+              (portRef DIA16 (instanceRef pdp_ram_8_2_29))
+              (portRef DIB15 (instanceRef pdp_ram_8_2_29))
+              (portRef DIA15 (instanceRef pdp_ram_8_2_29))
+              (portRef DIB14 (instanceRef pdp_ram_8_2_29))
+              (portRef DIA14 (instanceRef pdp_ram_8_2_29))
+              (portRef DIB13 (instanceRef pdp_ram_8_2_29))
+              (portRef DIA13 (instanceRef pdp_ram_8_2_29))
+              (portRef DIB12 (instanceRef pdp_ram_8_2_29))
+              (portRef DIA12 (instanceRef pdp_ram_8_2_29))
+              (portRef DIB11 (instanceRef pdp_ram_8_2_29))
+              (portRef DIA11 (instanceRef pdp_ram_8_2_29))
+              (portRef DIB10 (instanceRef pdp_ram_8_2_29))
+              (portRef DIA10 (instanceRef pdp_ram_8_2_29))
+              (portRef DIB9 (instanceRef pdp_ram_8_2_29))
+              (portRef DIA9 (instanceRef pdp_ram_8_2_29))
+              (portRef DIB8 (instanceRef pdp_ram_8_2_29))
+              (portRef DIB7 (instanceRef pdp_ram_8_2_29))
+              (portRef DIB6 (instanceRef pdp_ram_8_2_29))
+              (portRef DIB5 (instanceRef pdp_ram_8_2_29))
+              (portRef DIB4 (instanceRef pdp_ram_8_2_29))
+              (portRef DIB3 (instanceRef pdp_ram_8_2_29))
+              (portRef DIB2 (instanceRef pdp_ram_8_2_29))
+              (portRef DIB1 (instanceRef pdp_ram_8_2_29))
+              (portRef DIB0 (instanceRef pdp_ram_8_2_29))
+              (portRef CSB2 (instanceRef pdp_ram_8_3_28))
+              (portRef CSA2 (instanceRef pdp_ram_8_3_28))
+              (portRef CSB1 (instanceRef pdp_ram_8_3_28))
+              (portRef CSA1 (instanceRef pdp_ram_8_3_28))
+              (portRef WEB (instanceRef pdp_ram_8_3_28))
+              (portRef ADB2 (instanceRef pdp_ram_8_3_28))
+              (portRef ADA2 (instanceRef pdp_ram_8_3_28))
+              (portRef ADB1 (instanceRef pdp_ram_8_3_28))
+              (portRef ADA1 (instanceRef pdp_ram_8_3_28))
+              (portRef ADB0 (instanceRef pdp_ram_8_3_28))
+              (portRef ADA0 (instanceRef pdp_ram_8_3_28))
+              (portRef DIB17 (instanceRef pdp_ram_8_3_28))
+              (portRef DIA17 (instanceRef pdp_ram_8_3_28))
+              (portRef DIB16 (instanceRef pdp_ram_8_3_28))
+              (portRef DIA16 (instanceRef pdp_ram_8_3_28))
+              (portRef DIB15 (instanceRef pdp_ram_8_3_28))
+              (portRef DIA15 (instanceRef pdp_ram_8_3_28))
+              (portRef DIB14 (instanceRef pdp_ram_8_3_28))
+              (portRef DIA14 (instanceRef pdp_ram_8_3_28))
+              (portRef DIB13 (instanceRef pdp_ram_8_3_28))
+              (portRef DIA13 (instanceRef pdp_ram_8_3_28))
+              (portRef DIB12 (instanceRef pdp_ram_8_3_28))
+              (portRef DIA12 (instanceRef pdp_ram_8_3_28))
+              (portRef DIB11 (instanceRef pdp_ram_8_3_28))
+              (portRef DIA11 (instanceRef pdp_ram_8_3_28))
+              (portRef DIB10 (instanceRef pdp_ram_8_3_28))
+              (portRef DIA10 (instanceRef pdp_ram_8_3_28))
+              (portRef DIB9 (instanceRef pdp_ram_8_3_28))
+              (portRef DIA9 (instanceRef pdp_ram_8_3_28))
+              (portRef DIB8 (instanceRef pdp_ram_8_3_28))
+              (portRef DIB7 (instanceRef pdp_ram_8_3_28))
+              (portRef DIB6 (instanceRef pdp_ram_8_3_28))
+              (portRef DIB5 (instanceRef pdp_ram_8_3_28))
+              (portRef DIB4 (instanceRef pdp_ram_8_3_28))
+              (portRef DIB3 (instanceRef pdp_ram_8_3_28))
+              (portRef DIB2 (instanceRef pdp_ram_8_3_28))
+              (portRef DIB1 (instanceRef pdp_ram_8_3_28))
+              (portRef DIB0 (instanceRef pdp_ram_8_3_28))
+              (portRef CSB2 (instanceRef pdp_ram_9_0_27))
+              (portRef CSA2 (instanceRef pdp_ram_9_0_27))
+              (portRef CSB1 (instanceRef pdp_ram_9_0_27))
+              (portRef CSA1 (instanceRef pdp_ram_9_0_27))
+              (portRef WEB (instanceRef pdp_ram_9_0_27))
+              (portRef ADB2 (instanceRef pdp_ram_9_0_27))
+              (portRef ADA2 (instanceRef pdp_ram_9_0_27))
+              (portRef ADB1 (instanceRef pdp_ram_9_0_27))
+              (portRef ADA1 (instanceRef pdp_ram_9_0_27))
+              (portRef ADB0 (instanceRef pdp_ram_9_0_27))
+              (portRef ADA0 (instanceRef pdp_ram_9_0_27))
+              (portRef DIB17 (instanceRef pdp_ram_9_0_27))
+              (portRef DIA17 (instanceRef pdp_ram_9_0_27))
+              (portRef DIB16 (instanceRef pdp_ram_9_0_27))
+              (portRef DIA16 (instanceRef pdp_ram_9_0_27))
+              (portRef DIB15 (instanceRef pdp_ram_9_0_27))
+              (portRef DIA15 (instanceRef pdp_ram_9_0_27))
+              (portRef DIB14 (instanceRef pdp_ram_9_0_27))
+              (portRef DIA14 (instanceRef pdp_ram_9_0_27))
+              (portRef DIB13 (instanceRef pdp_ram_9_0_27))
+              (portRef DIA13 (instanceRef pdp_ram_9_0_27))
+              (portRef DIB12 (instanceRef pdp_ram_9_0_27))
+              (portRef DIA12 (instanceRef pdp_ram_9_0_27))
+              (portRef DIB11 (instanceRef pdp_ram_9_0_27))
+              (portRef DIA11 (instanceRef pdp_ram_9_0_27))
+              (portRef DIB10 (instanceRef pdp_ram_9_0_27))
+              (portRef DIA10 (instanceRef pdp_ram_9_0_27))
+              (portRef DIB9 (instanceRef pdp_ram_9_0_27))
+              (portRef DIA9 (instanceRef pdp_ram_9_0_27))
+              (portRef DIB8 (instanceRef pdp_ram_9_0_27))
+              (portRef DIB7 (instanceRef pdp_ram_9_0_27))
+              (portRef DIB6 (instanceRef pdp_ram_9_0_27))
+              (portRef DIB5 (instanceRef pdp_ram_9_0_27))
+              (portRef DIB4 (instanceRef pdp_ram_9_0_27))
+              (portRef DIB3 (instanceRef pdp_ram_9_0_27))
+              (portRef DIB2 (instanceRef pdp_ram_9_0_27))
+              (portRef DIB1 (instanceRef pdp_ram_9_0_27))
+              (portRef DIB0 (instanceRef pdp_ram_9_0_27))
+              (portRef CSB2 (instanceRef pdp_ram_9_1_26))
+              (portRef CSA2 (instanceRef pdp_ram_9_1_26))
+              (portRef CSB1 (instanceRef pdp_ram_9_1_26))
+              (portRef CSA1 (instanceRef pdp_ram_9_1_26))
+              (portRef WEB (instanceRef pdp_ram_9_1_26))
+              (portRef ADB2 (instanceRef pdp_ram_9_1_26))
+              (portRef ADA2 (instanceRef pdp_ram_9_1_26))
+              (portRef ADB1 (instanceRef pdp_ram_9_1_26))
+              (portRef ADA1 (instanceRef pdp_ram_9_1_26))
+              (portRef ADB0 (instanceRef pdp_ram_9_1_26))
+              (portRef ADA0 (instanceRef pdp_ram_9_1_26))
+              (portRef DIB17 (instanceRef pdp_ram_9_1_26))
+              (portRef DIA17 (instanceRef pdp_ram_9_1_26))
+              (portRef DIB16 (instanceRef pdp_ram_9_1_26))
+              (portRef DIA16 (instanceRef pdp_ram_9_1_26))
+              (portRef DIB15 (instanceRef pdp_ram_9_1_26))
+              (portRef DIA15 (instanceRef pdp_ram_9_1_26))
+              (portRef DIB14 (instanceRef pdp_ram_9_1_26))
+              (portRef DIA14 (instanceRef pdp_ram_9_1_26))
+              (portRef DIB13 (instanceRef pdp_ram_9_1_26))
+              (portRef DIA13 (instanceRef pdp_ram_9_1_26))
+              (portRef DIB12 (instanceRef pdp_ram_9_1_26))
+              (portRef DIA12 (instanceRef pdp_ram_9_1_26))
+              (portRef DIB11 (instanceRef pdp_ram_9_1_26))
+              (portRef DIA11 (instanceRef pdp_ram_9_1_26))
+              (portRef DIB10 (instanceRef pdp_ram_9_1_26))
+              (portRef DIA10 (instanceRef pdp_ram_9_1_26))
+              (portRef DIB9 (instanceRef pdp_ram_9_1_26))
+              (portRef DIA9 (instanceRef pdp_ram_9_1_26))
+              (portRef DIB8 (instanceRef pdp_ram_9_1_26))
+              (portRef DIB7 (instanceRef pdp_ram_9_1_26))
+              (portRef DIB6 (instanceRef pdp_ram_9_1_26))
+              (portRef DIB5 (instanceRef pdp_ram_9_1_26))
+              (portRef DIB4 (instanceRef pdp_ram_9_1_26))
+              (portRef DIB3 (instanceRef pdp_ram_9_1_26))
+              (portRef DIB2 (instanceRef pdp_ram_9_1_26))
+              (portRef DIB1 (instanceRef pdp_ram_9_1_26))
+              (portRef DIB0 (instanceRef pdp_ram_9_1_26))
+              (portRef CSB2 (instanceRef pdp_ram_9_2_25))
+              (portRef CSA2 (instanceRef pdp_ram_9_2_25))
+              (portRef CSB1 (instanceRef pdp_ram_9_2_25))
+              (portRef CSA1 (instanceRef pdp_ram_9_2_25))
+              (portRef WEB (instanceRef pdp_ram_9_2_25))
+              (portRef ADB2 (instanceRef pdp_ram_9_2_25))
+              (portRef ADA2 (instanceRef pdp_ram_9_2_25))
+              (portRef ADB1 (instanceRef pdp_ram_9_2_25))
+              (portRef ADA1 (instanceRef pdp_ram_9_2_25))
+              (portRef ADB0 (instanceRef pdp_ram_9_2_25))
+              (portRef ADA0 (instanceRef pdp_ram_9_2_25))
+              (portRef DIB17 (instanceRef pdp_ram_9_2_25))
+              (portRef DIA17 (instanceRef pdp_ram_9_2_25))
+              (portRef DIB16 (instanceRef pdp_ram_9_2_25))
+              (portRef DIA16 (instanceRef pdp_ram_9_2_25))
+              (portRef DIB15 (instanceRef pdp_ram_9_2_25))
+              (portRef DIA15 (instanceRef pdp_ram_9_2_25))
+              (portRef DIB14 (instanceRef pdp_ram_9_2_25))
+              (portRef DIA14 (instanceRef pdp_ram_9_2_25))
+              (portRef DIB13 (instanceRef pdp_ram_9_2_25))
+              (portRef DIA13 (instanceRef pdp_ram_9_2_25))
+              (portRef DIB12 (instanceRef pdp_ram_9_2_25))
+              (portRef DIA12 (instanceRef pdp_ram_9_2_25))
+              (portRef DIB11 (instanceRef pdp_ram_9_2_25))
+              (portRef DIA11 (instanceRef pdp_ram_9_2_25))
+              (portRef DIB10 (instanceRef pdp_ram_9_2_25))
+              (portRef DIA10 (instanceRef pdp_ram_9_2_25))
+              (portRef DIB9 (instanceRef pdp_ram_9_2_25))
+              (portRef DIA9 (instanceRef pdp_ram_9_2_25))
+              (portRef DIB8 (instanceRef pdp_ram_9_2_25))
+              (portRef DIB7 (instanceRef pdp_ram_9_2_25))
+              (portRef DIB6 (instanceRef pdp_ram_9_2_25))
+              (portRef DIB5 (instanceRef pdp_ram_9_2_25))
+              (portRef DIB4 (instanceRef pdp_ram_9_2_25))
+              (portRef DIB3 (instanceRef pdp_ram_9_2_25))
+              (portRef DIB2 (instanceRef pdp_ram_9_2_25))
+              (portRef DIB1 (instanceRef pdp_ram_9_2_25))
+              (portRef DIB0 (instanceRef pdp_ram_9_2_25))
+              (portRef CSB2 (instanceRef pdp_ram_9_3_24))
+              (portRef CSA2 (instanceRef pdp_ram_9_3_24))
+              (portRef CSB1 (instanceRef pdp_ram_9_3_24))
+              (portRef CSA1 (instanceRef pdp_ram_9_3_24))
+              (portRef WEB (instanceRef pdp_ram_9_3_24))
+              (portRef ADB2 (instanceRef pdp_ram_9_3_24))
+              (portRef ADA2 (instanceRef pdp_ram_9_3_24))
+              (portRef ADB1 (instanceRef pdp_ram_9_3_24))
+              (portRef ADA1 (instanceRef pdp_ram_9_3_24))
+              (portRef ADB0 (instanceRef pdp_ram_9_3_24))
+              (portRef ADA0 (instanceRef pdp_ram_9_3_24))
+              (portRef DIB17 (instanceRef pdp_ram_9_3_24))
+              (portRef DIA17 (instanceRef pdp_ram_9_3_24))
+              (portRef DIB16 (instanceRef pdp_ram_9_3_24))
+              (portRef DIA16 (instanceRef pdp_ram_9_3_24))
+              (portRef DIB15 (instanceRef pdp_ram_9_3_24))
+              (portRef DIA15 (instanceRef pdp_ram_9_3_24))
+              (portRef DIB14 (instanceRef pdp_ram_9_3_24))
+              (portRef DIA14 (instanceRef pdp_ram_9_3_24))
+              (portRef DIB13 (instanceRef pdp_ram_9_3_24))
+              (portRef DIA13 (instanceRef pdp_ram_9_3_24))
+              (portRef DIB12 (instanceRef pdp_ram_9_3_24))
+              (portRef DIA12 (instanceRef pdp_ram_9_3_24))
+              (portRef DIB11 (instanceRef pdp_ram_9_3_24))
+              (portRef DIA11 (instanceRef pdp_ram_9_3_24))
+              (portRef DIB10 (instanceRef pdp_ram_9_3_24))
+              (portRef DIA10 (instanceRef pdp_ram_9_3_24))
+              (portRef DIB9 (instanceRef pdp_ram_9_3_24))
+              (portRef DIA9 (instanceRef pdp_ram_9_3_24))
+              (portRef DIB8 (instanceRef pdp_ram_9_3_24))
+              (portRef DIB7 (instanceRef pdp_ram_9_3_24))
+              (portRef DIB6 (instanceRef pdp_ram_9_3_24))
+              (portRef DIB5 (instanceRef pdp_ram_9_3_24))
+              (portRef DIB4 (instanceRef pdp_ram_9_3_24))
+              (portRef DIB3 (instanceRef pdp_ram_9_3_24))
+              (portRef DIB2 (instanceRef pdp_ram_9_3_24))
+              (portRef DIB1 (instanceRef pdp_ram_9_3_24))
+              (portRef DIB0 (instanceRef pdp_ram_9_3_24))
+              (portRef CSB2 (instanceRef pdp_ram_10_0_23))
+              (portRef CSA2 (instanceRef pdp_ram_10_0_23))
+              (portRef CSB1 (instanceRef pdp_ram_10_0_23))
+              (portRef CSA1 (instanceRef pdp_ram_10_0_23))
+              (portRef WEB (instanceRef pdp_ram_10_0_23))
+              (portRef ADB2 (instanceRef pdp_ram_10_0_23))
+              (portRef ADA2 (instanceRef pdp_ram_10_0_23))
+              (portRef ADB1 (instanceRef pdp_ram_10_0_23))
+              (portRef ADA1 (instanceRef pdp_ram_10_0_23))
+              (portRef ADB0 (instanceRef pdp_ram_10_0_23))
+              (portRef ADA0 (instanceRef pdp_ram_10_0_23))
+              (portRef DIB17 (instanceRef pdp_ram_10_0_23))
+              (portRef DIA17 (instanceRef pdp_ram_10_0_23))
+              (portRef DIB16 (instanceRef pdp_ram_10_0_23))
+              (portRef DIA16 (instanceRef pdp_ram_10_0_23))
+              (portRef DIB15 (instanceRef pdp_ram_10_0_23))
+              (portRef DIA15 (instanceRef pdp_ram_10_0_23))
+              (portRef DIB14 (instanceRef pdp_ram_10_0_23))
+              (portRef DIA14 (instanceRef pdp_ram_10_0_23))
+              (portRef DIB13 (instanceRef pdp_ram_10_0_23))
+              (portRef DIA13 (instanceRef pdp_ram_10_0_23))
+              (portRef DIB12 (instanceRef pdp_ram_10_0_23))
+              (portRef DIA12 (instanceRef pdp_ram_10_0_23))
+              (portRef DIB11 (instanceRef pdp_ram_10_0_23))
+              (portRef DIA11 (instanceRef pdp_ram_10_0_23))
+              (portRef DIB10 (instanceRef pdp_ram_10_0_23))
+              (portRef DIA10 (instanceRef pdp_ram_10_0_23))
+              (portRef DIB9 (instanceRef pdp_ram_10_0_23))
+              (portRef DIA9 (instanceRef pdp_ram_10_0_23))
+              (portRef DIB8 (instanceRef pdp_ram_10_0_23))
+              (portRef DIB7 (instanceRef pdp_ram_10_0_23))
+              (portRef DIB6 (instanceRef pdp_ram_10_0_23))
+              (portRef DIB5 (instanceRef pdp_ram_10_0_23))
+              (portRef DIB4 (instanceRef pdp_ram_10_0_23))
+              (portRef DIB3 (instanceRef pdp_ram_10_0_23))
+              (portRef DIB2 (instanceRef pdp_ram_10_0_23))
+              (portRef DIB1 (instanceRef pdp_ram_10_0_23))
+              (portRef DIB0 (instanceRef pdp_ram_10_0_23))
+              (portRef CSB2 (instanceRef pdp_ram_10_1_22))
+              (portRef CSA2 (instanceRef pdp_ram_10_1_22))
+              (portRef CSB1 (instanceRef pdp_ram_10_1_22))
+              (portRef CSA1 (instanceRef pdp_ram_10_1_22))
+              (portRef WEB (instanceRef pdp_ram_10_1_22))
+              (portRef ADB2 (instanceRef pdp_ram_10_1_22))
+              (portRef ADA2 (instanceRef pdp_ram_10_1_22))
+              (portRef ADB1 (instanceRef pdp_ram_10_1_22))
+              (portRef ADA1 (instanceRef pdp_ram_10_1_22))
+              (portRef ADB0 (instanceRef pdp_ram_10_1_22))
+              (portRef ADA0 (instanceRef pdp_ram_10_1_22))
+              (portRef DIB17 (instanceRef pdp_ram_10_1_22))
+              (portRef DIA17 (instanceRef pdp_ram_10_1_22))
+              (portRef DIB16 (instanceRef pdp_ram_10_1_22))
+              (portRef DIA16 (instanceRef pdp_ram_10_1_22))
+              (portRef DIB15 (instanceRef pdp_ram_10_1_22))
+              (portRef DIA15 (instanceRef pdp_ram_10_1_22))
+              (portRef DIB14 (instanceRef pdp_ram_10_1_22))
+              (portRef DIA14 (instanceRef pdp_ram_10_1_22))
+              (portRef DIB13 (instanceRef pdp_ram_10_1_22))
+              (portRef DIA13 (instanceRef pdp_ram_10_1_22))
+              (portRef DIB12 (instanceRef pdp_ram_10_1_22))
+              (portRef DIA12 (instanceRef pdp_ram_10_1_22))
+              (portRef DIB11 (instanceRef pdp_ram_10_1_22))
+              (portRef DIA11 (instanceRef pdp_ram_10_1_22))
+              (portRef DIB10 (instanceRef pdp_ram_10_1_22))
+              (portRef DIA10 (instanceRef pdp_ram_10_1_22))
+              (portRef DIB9 (instanceRef pdp_ram_10_1_22))
+              (portRef DIA9 (instanceRef pdp_ram_10_1_22))
+              (portRef DIB8 (instanceRef pdp_ram_10_1_22))
+              (portRef DIB7 (instanceRef pdp_ram_10_1_22))
+              (portRef DIB6 (instanceRef pdp_ram_10_1_22))
+              (portRef DIB5 (instanceRef pdp_ram_10_1_22))
+              (portRef DIB4 (instanceRef pdp_ram_10_1_22))
+              (portRef DIB3 (instanceRef pdp_ram_10_1_22))
+              (portRef DIB2 (instanceRef pdp_ram_10_1_22))
+              (portRef DIB1 (instanceRef pdp_ram_10_1_22))
+              (portRef DIB0 (instanceRef pdp_ram_10_1_22))
+              (portRef CSB2 (instanceRef pdp_ram_10_2_21))
+              (portRef CSA2 (instanceRef pdp_ram_10_2_21))
+              (portRef CSB1 (instanceRef pdp_ram_10_2_21))
+              (portRef CSA1 (instanceRef pdp_ram_10_2_21))
+              (portRef WEB (instanceRef pdp_ram_10_2_21))
+              (portRef ADB2 (instanceRef pdp_ram_10_2_21))
+              (portRef ADA2 (instanceRef pdp_ram_10_2_21))
+              (portRef ADB1 (instanceRef pdp_ram_10_2_21))
+              (portRef ADA1 (instanceRef pdp_ram_10_2_21))
+              (portRef ADB0 (instanceRef pdp_ram_10_2_21))
+              (portRef ADA0 (instanceRef pdp_ram_10_2_21))
+              (portRef DIB17 (instanceRef pdp_ram_10_2_21))
+              (portRef DIA17 (instanceRef pdp_ram_10_2_21))
+              (portRef DIB16 (instanceRef pdp_ram_10_2_21))
+              (portRef DIA16 (instanceRef pdp_ram_10_2_21))
+              (portRef DIB15 (instanceRef pdp_ram_10_2_21))
+              (portRef DIA15 (instanceRef pdp_ram_10_2_21))
+              (portRef DIB14 (instanceRef pdp_ram_10_2_21))
+              (portRef DIA14 (instanceRef pdp_ram_10_2_21))
+              (portRef DIB13 (instanceRef pdp_ram_10_2_21))
+              (portRef DIA13 (instanceRef pdp_ram_10_2_21))
+              (portRef DIB12 (instanceRef pdp_ram_10_2_21))
+              (portRef DIA12 (instanceRef pdp_ram_10_2_21))
+              (portRef DIB11 (instanceRef pdp_ram_10_2_21))
+              (portRef DIA11 (instanceRef pdp_ram_10_2_21))
+              (portRef DIB10 (instanceRef pdp_ram_10_2_21))
+              (portRef DIA10 (instanceRef pdp_ram_10_2_21))
+              (portRef DIB9 (instanceRef pdp_ram_10_2_21))
+              (portRef DIA9 (instanceRef pdp_ram_10_2_21))
+              (portRef DIB8 (instanceRef pdp_ram_10_2_21))
+              (portRef DIB7 (instanceRef pdp_ram_10_2_21))
+              (portRef DIB6 (instanceRef pdp_ram_10_2_21))
+              (portRef DIB5 (instanceRef pdp_ram_10_2_21))
+              (portRef DIB4 (instanceRef pdp_ram_10_2_21))
+              (portRef DIB3 (instanceRef pdp_ram_10_2_21))
+              (portRef DIB2 (instanceRef pdp_ram_10_2_21))
+              (portRef DIB1 (instanceRef pdp_ram_10_2_21))
+              (portRef DIB0 (instanceRef pdp_ram_10_2_21))
+              (portRef CSB2 (instanceRef pdp_ram_10_3_20))
+              (portRef CSA2 (instanceRef pdp_ram_10_3_20))
+              (portRef CSB1 (instanceRef pdp_ram_10_3_20))
+              (portRef CSA1 (instanceRef pdp_ram_10_3_20))
+              (portRef WEB (instanceRef pdp_ram_10_3_20))
+              (portRef ADB2 (instanceRef pdp_ram_10_3_20))
+              (portRef ADA2 (instanceRef pdp_ram_10_3_20))
+              (portRef ADB1 (instanceRef pdp_ram_10_3_20))
+              (portRef ADA1 (instanceRef pdp_ram_10_3_20))
+              (portRef ADB0 (instanceRef pdp_ram_10_3_20))
+              (portRef ADA0 (instanceRef pdp_ram_10_3_20))
+              (portRef DIB17 (instanceRef pdp_ram_10_3_20))
+              (portRef DIA17 (instanceRef pdp_ram_10_3_20))
+              (portRef DIB16 (instanceRef pdp_ram_10_3_20))
+              (portRef DIA16 (instanceRef pdp_ram_10_3_20))
+              (portRef DIB15 (instanceRef pdp_ram_10_3_20))
+              (portRef DIA15 (instanceRef pdp_ram_10_3_20))
+              (portRef DIB14 (instanceRef pdp_ram_10_3_20))
+              (portRef DIA14 (instanceRef pdp_ram_10_3_20))
+              (portRef DIB13 (instanceRef pdp_ram_10_3_20))
+              (portRef DIA13 (instanceRef pdp_ram_10_3_20))
+              (portRef DIB12 (instanceRef pdp_ram_10_3_20))
+              (portRef DIA12 (instanceRef pdp_ram_10_3_20))
+              (portRef DIB11 (instanceRef pdp_ram_10_3_20))
+              (portRef DIA11 (instanceRef pdp_ram_10_3_20))
+              (portRef DIB10 (instanceRef pdp_ram_10_3_20))
+              (portRef DIA10 (instanceRef pdp_ram_10_3_20))
+              (portRef DIB9 (instanceRef pdp_ram_10_3_20))
+              (portRef DIA9 (instanceRef pdp_ram_10_3_20))
+              (portRef DIB8 (instanceRef pdp_ram_10_3_20))
+              (portRef DIB7 (instanceRef pdp_ram_10_3_20))
+              (portRef DIB6 (instanceRef pdp_ram_10_3_20))
+              (portRef DIB5 (instanceRef pdp_ram_10_3_20))
+              (portRef DIB4 (instanceRef pdp_ram_10_3_20))
+              (portRef DIB3 (instanceRef pdp_ram_10_3_20))
+              (portRef DIB2 (instanceRef pdp_ram_10_3_20))
+              (portRef DIB1 (instanceRef pdp_ram_10_3_20))
+              (portRef DIB0 (instanceRef pdp_ram_10_3_20))
+              (portRef CSB2 (instanceRef pdp_ram_11_0_19))
+              (portRef CSA2 (instanceRef pdp_ram_11_0_19))
+              (portRef CSB1 (instanceRef pdp_ram_11_0_19))
+              (portRef CSA1 (instanceRef pdp_ram_11_0_19))
+              (portRef WEB (instanceRef pdp_ram_11_0_19))
+              (portRef ADB2 (instanceRef pdp_ram_11_0_19))
+              (portRef ADA2 (instanceRef pdp_ram_11_0_19))
+              (portRef ADB1 (instanceRef pdp_ram_11_0_19))
+              (portRef ADA1 (instanceRef pdp_ram_11_0_19))
+              (portRef ADB0 (instanceRef pdp_ram_11_0_19))
+              (portRef ADA0 (instanceRef pdp_ram_11_0_19))
+              (portRef DIB17 (instanceRef pdp_ram_11_0_19))
+              (portRef DIA17 (instanceRef pdp_ram_11_0_19))
+              (portRef DIB16 (instanceRef pdp_ram_11_0_19))
+              (portRef DIA16 (instanceRef pdp_ram_11_0_19))
+              (portRef DIB15 (instanceRef pdp_ram_11_0_19))
+              (portRef DIA15 (instanceRef pdp_ram_11_0_19))
+              (portRef DIB14 (instanceRef pdp_ram_11_0_19))
+              (portRef DIA14 (instanceRef pdp_ram_11_0_19))
+              (portRef DIB13 (instanceRef pdp_ram_11_0_19))
+              (portRef DIA13 (instanceRef pdp_ram_11_0_19))
+              (portRef DIB12 (instanceRef pdp_ram_11_0_19))
+              (portRef DIA12 (instanceRef pdp_ram_11_0_19))
+              (portRef DIB11 (instanceRef pdp_ram_11_0_19))
+              (portRef DIA11 (instanceRef pdp_ram_11_0_19))
+              (portRef DIB10 (instanceRef pdp_ram_11_0_19))
+              (portRef DIA10 (instanceRef pdp_ram_11_0_19))
+              (portRef DIB9 (instanceRef pdp_ram_11_0_19))
+              (portRef DIA9 (instanceRef pdp_ram_11_0_19))
+              (portRef DIB8 (instanceRef pdp_ram_11_0_19))
+              (portRef DIB7 (instanceRef pdp_ram_11_0_19))
+              (portRef DIB6 (instanceRef pdp_ram_11_0_19))
+              (portRef DIB5 (instanceRef pdp_ram_11_0_19))
+              (portRef DIB4 (instanceRef pdp_ram_11_0_19))
+              (portRef DIB3 (instanceRef pdp_ram_11_0_19))
+              (portRef DIB2 (instanceRef pdp_ram_11_0_19))
+              (portRef DIB1 (instanceRef pdp_ram_11_0_19))
+              (portRef DIB0 (instanceRef pdp_ram_11_0_19))
+              (portRef CSB2 (instanceRef pdp_ram_11_1_18))
+              (portRef CSA2 (instanceRef pdp_ram_11_1_18))
+              (portRef CSB1 (instanceRef pdp_ram_11_1_18))
+              (portRef CSA1 (instanceRef pdp_ram_11_1_18))
+              (portRef WEB (instanceRef pdp_ram_11_1_18))
+              (portRef ADB2 (instanceRef pdp_ram_11_1_18))
+              (portRef ADA2 (instanceRef pdp_ram_11_1_18))
+              (portRef ADB1 (instanceRef pdp_ram_11_1_18))
+              (portRef ADA1 (instanceRef pdp_ram_11_1_18))
+              (portRef ADB0 (instanceRef pdp_ram_11_1_18))
+              (portRef ADA0 (instanceRef pdp_ram_11_1_18))
+              (portRef DIB17 (instanceRef pdp_ram_11_1_18))
+              (portRef DIA17 (instanceRef pdp_ram_11_1_18))
+              (portRef DIB16 (instanceRef pdp_ram_11_1_18))
+              (portRef DIA16 (instanceRef pdp_ram_11_1_18))
+              (portRef DIB15 (instanceRef pdp_ram_11_1_18))
+              (portRef DIA15 (instanceRef pdp_ram_11_1_18))
+              (portRef DIB14 (instanceRef pdp_ram_11_1_18))
+              (portRef DIA14 (instanceRef pdp_ram_11_1_18))
+              (portRef DIB13 (instanceRef pdp_ram_11_1_18))
+              (portRef DIA13 (instanceRef pdp_ram_11_1_18))
+              (portRef DIB12 (instanceRef pdp_ram_11_1_18))
+              (portRef DIA12 (instanceRef pdp_ram_11_1_18))
+              (portRef DIB11 (instanceRef pdp_ram_11_1_18))
+              (portRef DIA11 (instanceRef pdp_ram_11_1_18))
+              (portRef DIB10 (instanceRef pdp_ram_11_1_18))
+              (portRef DIA10 (instanceRef pdp_ram_11_1_18))
+              (portRef DIB9 (instanceRef pdp_ram_11_1_18))
+              (portRef DIA9 (instanceRef pdp_ram_11_1_18))
+              (portRef DIB8 (instanceRef pdp_ram_11_1_18))
+              (portRef DIB7 (instanceRef pdp_ram_11_1_18))
+              (portRef DIB6 (instanceRef pdp_ram_11_1_18))
+              (portRef DIB5 (instanceRef pdp_ram_11_1_18))
+              (portRef DIB4 (instanceRef pdp_ram_11_1_18))
+              (portRef DIB3 (instanceRef pdp_ram_11_1_18))
+              (portRef DIB2 (instanceRef pdp_ram_11_1_18))
+              (portRef DIB1 (instanceRef pdp_ram_11_1_18))
+              (portRef DIB0 (instanceRef pdp_ram_11_1_18))
+              (portRef CSB2 (instanceRef pdp_ram_11_2_17))
+              (portRef CSA2 (instanceRef pdp_ram_11_2_17))
+              (portRef CSB1 (instanceRef pdp_ram_11_2_17))
+              (portRef CSA1 (instanceRef pdp_ram_11_2_17))
+              (portRef WEB (instanceRef pdp_ram_11_2_17))
+              (portRef ADB2 (instanceRef pdp_ram_11_2_17))
+              (portRef ADA2 (instanceRef pdp_ram_11_2_17))
+              (portRef ADB1 (instanceRef pdp_ram_11_2_17))
+              (portRef ADA1 (instanceRef pdp_ram_11_2_17))
+              (portRef ADB0 (instanceRef pdp_ram_11_2_17))
+              (portRef ADA0 (instanceRef pdp_ram_11_2_17))
+              (portRef DIB17 (instanceRef pdp_ram_11_2_17))
+              (portRef DIA17 (instanceRef pdp_ram_11_2_17))
+              (portRef DIB16 (instanceRef pdp_ram_11_2_17))
+              (portRef DIA16 (instanceRef pdp_ram_11_2_17))
+              (portRef DIB15 (instanceRef pdp_ram_11_2_17))
+              (portRef DIA15 (instanceRef pdp_ram_11_2_17))
+              (portRef DIB14 (instanceRef pdp_ram_11_2_17))
+              (portRef DIA14 (instanceRef pdp_ram_11_2_17))
+              (portRef DIB13 (instanceRef pdp_ram_11_2_17))
+              (portRef DIA13 (instanceRef pdp_ram_11_2_17))
+              (portRef DIB12 (instanceRef pdp_ram_11_2_17))
+              (portRef DIA12 (instanceRef pdp_ram_11_2_17))
+              (portRef DIB11 (instanceRef pdp_ram_11_2_17))
+              (portRef DIA11 (instanceRef pdp_ram_11_2_17))
+              (portRef DIB10 (instanceRef pdp_ram_11_2_17))
+              (portRef DIA10 (instanceRef pdp_ram_11_2_17))
+              (portRef DIB9 (instanceRef pdp_ram_11_2_17))
+              (portRef DIA9 (instanceRef pdp_ram_11_2_17))
+              (portRef DIB8 (instanceRef pdp_ram_11_2_17))
+              (portRef DIB7 (instanceRef pdp_ram_11_2_17))
+              (portRef DIB6 (instanceRef pdp_ram_11_2_17))
+              (portRef DIB5 (instanceRef pdp_ram_11_2_17))
+              (portRef DIB4 (instanceRef pdp_ram_11_2_17))
+              (portRef DIB3 (instanceRef pdp_ram_11_2_17))
+              (portRef DIB2 (instanceRef pdp_ram_11_2_17))
+              (portRef DIB1 (instanceRef pdp_ram_11_2_17))
+              (portRef DIB0 (instanceRef pdp_ram_11_2_17))
+              (portRef CSB2 (instanceRef pdp_ram_11_3_16))
+              (portRef CSA2 (instanceRef pdp_ram_11_3_16))
+              (portRef CSB1 (instanceRef pdp_ram_11_3_16))
+              (portRef CSA1 (instanceRef pdp_ram_11_3_16))
+              (portRef WEB (instanceRef pdp_ram_11_3_16))
+              (portRef ADB2 (instanceRef pdp_ram_11_3_16))
+              (portRef ADA2 (instanceRef pdp_ram_11_3_16))
+              (portRef ADB1 (instanceRef pdp_ram_11_3_16))
+              (portRef ADA1 (instanceRef pdp_ram_11_3_16))
+              (portRef ADB0 (instanceRef pdp_ram_11_3_16))
+              (portRef ADA0 (instanceRef pdp_ram_11_3_16))
+              (portRef DIB17 (instanceRef pdp_ram_11_3_16))
+              (portRef DIA17 (instanceRef pdp_ram_11_3_16))
+              (portRef DIB16 (instanceRef pdp_ram_11_3_16))
+              (portRef DIA16 (instanceRef pdp_ram_11_3_16))
+              (portRef DIB15 (instanceRef pdp_ram_11_3_16))
+              (portRef DIA15 (instanceRef pdp_ram_11_3_16))
+              (portRef DIB14 (instanceRef pdp_ram_11_3_16))
+              (portRef DIA14 (instanceRef pdp_ram_11_3_16))
+              (portRef DIB13 (instanceRef pdp_ram_11_3_16))
+              (portRef DIA13 (instanceRef pdp_ram_11_3_16))
+              (portRef DIB12 (instanceRef pdp_ram_11_3_16))
+              (portRef DIA12 (instanceRef pdp_ram_11_3_16))
+              (portRef DIB11 (instanceRef pdp_ram_11_3_16))
+              (portRef DIA11 (instanceRef pdp_ram_11_3_16))
+              (portRef DIB10 (instanceRef pdp_ram_11_3_16))
+              (portRef DIA10 (instanceRef pdp_ram_11_3_16))
+              (portRef DIB9 (instanceRef pdp_ram_11_3_16))
+              (portRef DIA9 (instanceRef pdp_ram_11_3_16))
+              (portRef DIB8 (instanceRef pdp_ram_11_3_16))
+              (portRef DIB7 (instanceRef pdp_ram_11_3_16))
+              (portRef DIB6 (instanceRef pdp_ram_11_3_16))
+              (portRef DIB5 (instanceRef pdp_ram_11_3_16))
+              (portRef DIB4 (instanceRef pdp_ram_11_3_16))
+              (portRef DIB3 (instanceRef pdp_ram_11_3_16))
+              (portRef DIB2 (instanceRef pdp_ram_11_3_16))
+              (portRef DIB1 (instanceRef pdp_ram_11_3_16))
+              (portRef DIB0 (instanceRef pdp_ram_11_3_16))
+              (portRef CSB2 (instanceRef pdp_ram_12_0_15))
+              (portRef CSA2 (instanceRef pdp_ram_12_0_15))
+              (portRef CSB1 (instanceRef pdp_ram_12_0_15))
+              (portRef CSA1 (instanceRef pdp_ram_12_0_15))
+              (portRef WEB (instanceRef pdp_ram_12_0_15))
+              (portRef ADB2 (instanceRef pdp_ram_12_0_15))
+              (portRef ADA2 (instanceRef pdp_ram_12_0_15))
+              (portRef ADB1 (instanceRef pdp_ram_12_0_15))
+              (portRef ADA1 (instanceRef pdp_ram_12_0_15))
+              (portRef ADB0 (instanceRef pdp_ram_12_0_15))
+              (portRef ADA0 (instanceRef pdp_ram_12_0_15))
+              (portRef DIB17 (instanceRef pdp_ram_12_0_15))
+              (portRef DIA17 (instanceRef pdp_ram_12_0_15))
+              (portRef DIB16 (instanceRef pdp_ram_12_0_15))
+              (portRef DIA16 (instanceRef pdp_ram_12_0_15))
+              (portRef DIB15 (instanceRef pdp_ram_12_0_15))
+              (portRef DIA15 (instanceRef pdp_ram_12_0_15))
+              (portRef DIB14 (instanceRef pdp_ram_12_0_15))
+              (portRef DIA14 (instanceRef pdp_ram_12_0_15))
+              (portRef DIB13 (instanceRef pdp_ram_12_0_15))
+              (portRef DIA13 (instanceRef pdp_ram_12_0_15))
+              (portRef DIB12 (instanceRef pdp_ram_12_0_15))
+              (portRef DIA12 (instanceRef pdp_ram_12_0_15))
+              (portRef DIB11 (instanceRef pdp_ram_12_0_15))
+              (portRef DIA11 (instanceRef pdp_ram_12_0_15))
+              (portRef DIB10 (instanceRef pdp_ram_12_0_15))
+              (portRef DIA10 (instanceRef pdp_ram_12_0_15))
+              (portRef DIB9 (instanceRef pdp_ram_12_0_15))
+              (portRef DIA9 (instanceRef pdp_ram_12_0_15))
+              (portRef DIB8 (instanceRef pdp_ram_12_0_15))
+              (portRef DIB7 (instanceRef pdp_ram_12_0_15))
+              (portRef DIB6 (instanceRef pdp_ram_12_0_15))
+              (portRef DIB5 (instanceRef pdp_ram_12_0_15))
+              (portRef DIB4 (instanceRef pdp_ram_12_0_15))
+              (portRef DIB3 (instanceRef pdp_ram_12_0_15))
+              (portRef DIB2 (instanceRef pdp_ram_12_0_15))
+              (portRef DIB1 (instanceRef pdp_ram_12_0_15))
+              (portRef DIB0 (instanceRef pdp_ram_12_0_15))
+              (portRef CSB2 (instanceRef pdp_ram_12_1_14))
+              (portRef CSA2 (instanceRef pdp_ram_12_1_14))
+              (portRef CSB1 (instanceRef pdp_ram_12_1_14))
+              (portRef CSA1 (instanceRef pdp_ram_12_1_14))
+              (portRef WEB (instanceRef pdp_ram_12_1_14))
+              (portRef ADB2 (instanceRef pdp_ram_12_1_14))
+              (portRef ADA2 (instanceRef pdp_ram_12_1_14))
+              (portRef ADB1 (instanceRef pdp_ram_12_1_14))
+              (portRef ADA1 (instanceRef pdp_ram_12_1_14))
+              (portRef ADB0 (instanceRef pdp_ram_12_1_14))
+              (portRef ADA0 (instanceRef pdp_ram_12_1_14))
+              (portRef DIB17 (instanceRef pdp_ram_12_1_14))
+              (portRef DIA17 (instanceRef pdp_ram_12_1_14))
+              (portRef DIB16 (instanceRef pdp_ram_12_1_14))
+              (portRef DIA16 (instanceRef pdp_ram_12_1_14))
+              (portRef DIB15 (instanceRef pdp_ram_12_1_14))
+              (portRef DIA15 (instanceRef pdp_ram_12_1_14))
+              (portRef DIB14 (instanceRef pdp_ram_12_1_14))
+              (portRef DIA14 (instanceRef pdp_ram_12_1_14))
+              (portRef DIB13 (instanceRef pdp_ram_12_1_14))
+              (portRef DIA13 (instanceRef pdp_ram_12_1_14))
+              (portRef DIB12 (instanceRef pdp_ram_12_1_14))
+              (portRef DIA12 (instanceRef pdp_ram_12_1_14))
+              (portRef DIB11 (instanceRef pdp_ram_12_1_14))
+              (portRef DIA11 (instanceRef pdp_ram_12_1_14))
+              (portRef DIB10 (instanceRef pdp_ram_12_1_14))
+              (portRef DIA10 (instanceRef pdp_ram_12_1_14))
+              (portRef DIB9 (instanceRef pdp_ram_12_1_14))
+              (portRef DIA9 (instanceRef pdp_ram_12_1_14))
+              (portRef DIB8 (instanceRef pdp_ram_12_1_14))
+              (portRef DIB7 (instanceRef pdp_ram_12_1_14))
+              (portRef DIB6 (instanceRef pdp_ram_12_1_14))
+              (portRef DIB5 (instanceRef pdp_ram_12_1_14))
+              (portRef DIB4 (instanceRef pdp_ram_12_1_14))
+              (portRef DIB3 (instanceRef pdp_ram_12_1_14))
+              (portRef DIB2 (instanceRef pdp_ram_12_1_14))
+              (portRef DIB1 (instanceRef pdp_ram_12_1_14))
+              (portRef DIB0 (instanceRef pdp_ram_12_1_14))
+              (portRef CSB2 (instanceRef pdp_ram_12_2_13))
+              (portRef CSA2 (instanceRef pdp_ram_12_2_13))
+              (portRef CSB1 (instanceRef pdp_ram_12_2_13))
+              (portRef CSA1 (instanceRef pdp_ram_12_2_13))
+              (portRef WEB (instanceRef pdp_ram_12_2_13))
+              (portRef ADB2 (instanceRef pdp_ram_12_2_13))
+              (portRef ADA2 (instanceRef pdp_ram_12_2_13))
+              (portRef ADB1 (instanceRef pdp_ram_12_2_13))
+              (portRef ADA1 (instanceRef pdp_ram_12_2_13))
+              (portRef ADB0 (instanceRef pdp_ram_12_2_13))
+              (portRef ADA0 (instanceRef pdp_ram_12_2_13))
+              (portRef DIB17 (instanceRef pdp_ram_12_2_13))
+              (portRef DIA17 (instanceRef pdp_ram_12_2_13))
+              (portRef DIB16 (instanceRef pdp_ram_12_2_13))
+              (portRef DIA16 (instanceRef pdp_ram_12_2_13))
+              (portRef DIB15 (instanceRef pdp_ram_12_2_13))
+              (portRef DIA15 (instanceRef pdp_ram_12_2_13))
+              (portRef DIB14 (instanceRef pdp_ram_12_2_13))
+              (portRef DIA14 (instanceRef pdp_ram_12_2_13))
+              (portRef DIB13 (instanceRef pdp_ram_12_2_13))
+              (portRef DIA13 (instanceRef pdp_ram_12_2_13))
+              (portRef DIB12 (instanceRef pdp_ram_12_2_13))
+              (portRef DIA12 (instanceRef pdp_ram_12_2_13))
+              (portRef DIB11 (instanceRef pdp_ram_12_2_13))
+              (portRef DIA11 (instanceRef pdp_ram_12_2_13))
+              (portRef DIB10 (instanceRef pdp_ram_12_2_13))
+              (portRef DIA10 (instanceRef pdp_ram_12_2_13))
+              (portRef DIB9 (instanceRef pdp_ram_12_2_13))
+              (portRef DIA9 (instanceRef pdp_ram_12_2_13))
+              (portRef DIB8 (instanceRef pdp_ram_12_2_13))
+              (portRef DIB7 (instanceRef pdp_ram_12_2_13))
+              (portRef DIB6 (instanceRef pdp_ram_12_2_13))
+              (portRef DIB5 (instanceRef pdp_ram_12_2_13))
+              (portRef DIB4 (instanceRef pdp_ram_12_2_13))
+              (portRef DIB3 (instanceRef pdp_ram_12_2_13))
+              (portRef DIB2 (instanceRef pdp_ram_12_2_13))
+              (portRef DIB1 (instanceRef pdp_ram_12_2_13))
+              (portRef DIB0 (instanceRef pdp_ram_12_2_13))
+              (portRef CSB2 (instanceRef pdp_ram_12_3_12))
+              (portRef CSA2 (instanceRef pdp_ram_12_3_12))
+              (portRef CSB1 (instanceRef pdp_ram_12_3_12))
+              (portRef CSA1 (instanceRef pdp_ram_12_3_12))
+              (portRef WEB (instanceRef pdp_ram_12_3_12))
+              (portRef ADB2 (instanceRef pdp_ram_12_3_12))
+              (portRef ADA2 (instanceRef pdp_ram_12_3_12))
+              (portRef ADB1 (instanceRef pdp_ram_12_3_12))
+              (portRef ADA1 (instanceRef pdp_ram_12_3_12))
+              (portRef ADB0 (instanceRef pdp_ram_12_3_12))
+              (portRef ADA0 (instanceRef pdp_ram_12_3_12))
+              (portRef DIB17 (instanceRef pdp_ram_12_3_12))
+              (portRef DIA17 (instanceRef pdp_ram_12_3_12))
+              (portRef DIB16 (instanceRef pdp_ram_12_3_12))
+              (portRef DIA16 (instanceRef pdp_ram_12_3_12))
+              (portRef DIB15 (instanceRef pdp_ram_12_3_12))
+              (portRef DIA15 (instanceRef pdp_ram_12_3_12))
+              (portRef DIB14 (instanceRef pdp_ram_12_3_12))
+              (portRef DIA14 (instanceRef pdp_ram_12_3_12))
+              (portRef DIB13 (instanceRef pdp_ram_12_3_12))
+              (portRef DIA13 (instanceRef pdp_ram_12_3_12))
+              (portRef DIB12 (instanceRef pdp_ram_12_3_12))
+              (portRef DIA12 (instanceRef pdp_ram_12_3_12))
+              (portRef DIB11 (instanceRef pdp_ram_12_3_12))
+              (portRef DIA11 (instanceRef pdp_ram_12_3_12))
+              (portRef DIB10 (instanceRef pdp_ram_12_3_12))
+              (portRef DIA10 (instanceRef pdp_ram_12_3_12))
+              (portRef DIB9 (instanceRef pdp_ram_12_3_12))
+              (portRef DIA9 (instanceRef pdp_ram_12_3_12))
+              (portRef DIB8 (instanceRef pdp_ram_12_3_12))
+              (portRef DIB7 (instanceRef pdp_ram_12_3_12))
+              (portRef DIB6 (instanceRef pdp_ram_12_3_12))
+              (portRef DIB5 (instanceRef pdp_ram_12_3_12))
+              (portRef DIB4 (instanceRef pdp_ram_12_3_12))
+              (portRef DIB3 (instanceRef pdp_ram_12_3_12))
+              (portRef DIB2 (instanceRef pdp_ram_12_3_12))
+              (portRef DIB1 (instanceRef pdp_ram_12_3_12))
+              (portRef DIB0 (instanceRef pdp_ram_12_3_12))
+              (portRef CSB2 (instanceRef pdp_ram_13_0_11))
+              (portRef CSA2 (instanceRef pdp_ram_13_0_11))
+              (portRef CSB1 (instanceRef pdp_ram_13_0_11))
+              (portRef CSA1 (instanceRef pdp_ram_13_0_11))
+              (portRef WEB (instanceRef pdp_ram_13_0_11))
+              (portRef ADB2 (instanceRef pdp_ram_13_0_11))
+              (portRef ADA2 (instanceRef pdp_ram_13_0_11))
+              (portRef ADB1 (instanceRef pdp_ram_13_0_11))
+              (portRef ADA1 (instanceRef pdp_ram_13_0_11))
+              (portRef ADB0 (instanceRef pdp_ram_13_0_11))
+              (portRef ADA0 (instanceRef pdp_ram_13_0_11))
+              (portRef DIB17 (instanceRef pdp_ram_13_0_11))
+              (portRef DIA17 (instanceRef pdp_ram_13_0_11))
+              (portRef DIB16 (instanceRef pdp_ram_13_0_11))
+              (portRef DIA16 (instanceRef pdp_ram_13_0_11))
+              (portRef DIB15 (instanceRef pdp_ram_13_0_11))
+              (portRef DIA15 (instanceRef pdp_ram_13_0_11))
+              (portRef DIB14 (instanceRef pdp_ram_13_0_11))
+              (portRef DIA14 (instanceRef pdp_ram_13_0_11))
+              (portRef DIB13 (instanceRef pdp_ram_13_0_11))
+              (portRef DIA13 (instanceRef pdp_ram_13_0_11))
+              (portRef DIB12 (instanceRef pdp_ram_13_0_11))
+              (portRef DIA12 (instanceRef pdp_ram_13_0_11))
+              (portRef DIB11 (instanceRef pdp_ram_13_0_11))
+              (portRef DIA11 (instanceRef pdp_ram_13_0_11))
+              (portRef DIB10 (instanceRef pdp_ram_13_0_11))
+              (portRef DIA10 (instanceRef pdp_ram_13_0_11))
+              (portRef DIB9 (instanceRef pdp_ram_13_0_11))
+              (portRef DIA9 (instanceRef pdp_ram_13_0_11))
+              (portRef DIB8 (instanceRef pdp_ram_13_0_11))
+              (portRef DIB7 (instanceRef pdp_ram_13_0_11))
+              (portRef DIB6 (instanceRef pdp_ram_13_0_11))
+              (portRef DIB5 (instanceRef pdp_ram_13_0_11))
+              (portRef DIB4 (instanceRef pdp_ram_13_0_11))
+              (portRef DIB3 (instanceRef pdp_ram_13_0_11))
+              (portRef DIB2 (instanceRef pdp_ram_13_0_11))
+              (portRef DIB1 (instanceRef pdp_ram_13_0_11))
+              (portRef DIB0 (instanceRef pdp_ram_13_0_11))
+              (portRef CSB2 (instanceRef pdp_ram_13_1_10))
+              (portRef CSA2 (instanceRef pdp_ram_13_1_10))
+              (portRef CSB1 (instanceRef pdp_ram_13_1_10))
+              (portRef CSA1 (instanceRef pdp_ram_13_1_10))
+              (portRef WEB (instanceRef pdp_ram_13_1_10))
+              (portRef ADB2 (instanceRef pdp_ram_13_1_10))
+              (portRef ADA2 (instanceRef pdp_ram_13_1_10))
+              (portRef ADB1 (instanceRef pdp_ram_13_1_10))
+              (portRef ADA1 (instanceRef pdp_ram_13_1_10))
+              (portRef ADB0 (instanceRef pdp_ram_13_1_10))
+              (portRef ADA0 (instanceRef pdp_ram_13_1_10))
+              (portRef DIB17 (instanceRef pdp_ram_13_1_10))
+              (portRef DIA17 (instanceRef pdp_ram_13_1_10))
+              (portRef DIB16 (instanceRef pdp_ram_13_1_10))
+              (portRef DIA16 (instanceRef pdp_ram_13_1_10))
+              (portRef DIB15 (instanceRef pdp_ram_13_1_10))
+              (portRef DIA15 (instanceRef pdp_ram_13_1_10))
+              (portRef DIB14 (instanceRef pdp_ram_13_1_10))
+              (portRef DIA14 (instanceRef pdp_ram_13_1_10))
+              (portRef DIB13 (instanceRef pdp_ram_13_1_10))
+              (portRef DIA13 (instanceRef pdp_ram_13_1_10))
+              (portRef DIB12 (instanceRef pdp_ram_13_1_10))
+              (portRef DIA12 (instanceRef pdp_ram_13_1_10))
+              (portRef DIB11 (instanceRef pdp_ram_13_1_10))
+              (portRef DIA11 (instanceRef pdp_ram_13_1_10))
+              (portRef DIB10 (instanceRef pdp_ram_13_1_10))
+              (portRef DIA10 (instanceRef pdp_ram_13_1_10))
+              (portRef DIB9 (instanceRef pdp_ram_13_1_10))
+              (portRef DIA9 (instanceRef pdp_ram_13_1_10))
+              (portRef DIB8 (instanceRef pdp_ram_13_1_10))
+              (portRef DIB7 (instanceRef pdp_ram_13_1_10))
+              (portRef DIB6 (instanceRef pdp_ram_13_1_10))
+              (portRef DIB5 (instanceRef pdp_ram_13_1_10))
+              (portRef DIB4 (instanceRef pdp_ram_13_1_10))
+              (portRef DIB3 (instanceRef pdp_ram_13_1_10))
+              (portRef DIB2 (instanceRef pdp_ram_13_1_10))
+              (portRef DIB1 (instanceRef pdp_ram_13_1_10))
+              (portRef DIB0 (instanceRef pdp_ram_13_1_10))
+              (portRef CSB2 (instanceRef pdp_ram_13_2_9))
+              (portRef CSA2 (instanceRef pdp_ram_13_2_9))
+              (portRef CSB1 (instanceRef pdp_ram_13_2_9))
+              (portRef CSA1 (instanceRef pdp_ram_13_2_9))
+              (portRef WEB (instanceRef pdp_ram_13_2_9))
+              (portRef ADB2 (instanceRef pdp_ram_13_2_9))
+              (portRef ADA2 (instanceRef pdp_ram_13_2_9))
+              (portRef ADB1 (instanceRef pdp_ram_13_2_9))
+              (portRef ADA1 (instanceRef pdp_ram_13_2_9))
+              (portRef ADB0 (instanceRef pdp_ram_13_2_9))
+              (portRef ADA0 (instanceRef pdp_ram_13_2_9))
+              (portRef DIB17 (instanceRef pdp_ram_13_2_9))
+              (portRef DIA17 (instanceRef pdp_ram_13_2_9))
+              (portRef DIB16 (instanceRef pdp_ram_13_2_9))
+              (portRef DIA16 (instanceRef pdp_ram_13_2_9))
+              (portRef DIB15 (instanceRef pdp_ram_13_2_9))
+              (portRef DIA15 (instanceRef pdp_ram_13_2_9))
+              (portRef DIB14 (instanceRef pdp_ram_13_2_9))
+              (portRef DIA14 (instanceRef pdp_ram_13_2_9))
+              (portRef DIB13 (instanceRef pdp_ram_13_2_9))
+              (portRef DIA13 (instanceRef pdp_ram_13_2_9))
+              (portRef DIB12 (instanceRef pdp_ram_13_2_9))
+              (portRef DIA12 (instanceRef pdp_ram_13_2_9))
+              (portRef DIB11 (instanceRef pdp_ram_13_2_9))
+              (portRef DIA11 (instanceRef pdp_ram_13_2_9))
+              (portRef DIB10 (instanceRef pdp_ram_13_2_9))
+              (portRef DIA10 (instanceRef pdp_ram_13_2_9))
+              (portRef DIB9 (instanceRef pdp_ram_13_2_9))
+              (portRef DIA9 (instanceRef pdp_ram_13_2_9))
+              (portRef DIB8 (instanceRef pdp_ram_13_2_9))
+              (portRef DIB7 (instanceRef pdp_ram_13_2_9))
+              (portRef DIB6 (instanceRef pdp_ram_13_2_9))
+              (portRef DIB5 (instanceRef pdp_ram_13_2_9))
+              (portRef DIB4 (instanceRef pdp_ram_13_2_9))
+              (portRef DIB3 (instanceRef pdp_ram_13_2_9))
+              (portRef DIB2 (instanceRef pdp_ram_13_2_9))
+              (portRef DIB1 (instanceRef pdp_ram_13_2_9))
+              (portRef DIB0 (instanceRef pdp_ram_13_2_9))
+              (portRef CSB2 (instanceRef pdp_ram_13_3_8))
+              (portRef CSA2 (instanceRef pdp_ram_13_3_8))
+              (portRef CSB1 (instanceRef pdp_ram_13_3_8))
+              (portRef CSA1 (instanceRef pdp_ram_13_3_8))
+              (portRef WEB (instanceRef pdp_ram_13_3_8))
+              (portRef ADB2 (instanceRef pdp_ram_13_3_8))
+              (portRef ADA2 (instanceRef pdp_ram_13_3_8))
+              (portRef ADB1 (instanceRef pdp_ram_13_3_8))
+              (portRef ADA1 (instanceRef pdp_ram_13_3_8))
+              (portRef ADB0 (instanceRef pdp_ram_13_3_8))
+              (portRef ADA0 (instanceRef pdp_ram_13_3_8))
+              (portRef DIB17 (instanceRef pdp_ram_13_3_8))
+              (portRef DIA17 (instanceRef pdp_ram_13_3_8))
+              (portRef DIB16 (instanceRef pdp_ram_13_3_8))
+              (portRef DIA16 (instanceRef pdp_ram_13_3_8))
+              (portRef DIB15 (instanceRef pdp_ram_13_3_8))
+              (portRef DIA15 (instanceRef pdp_ram_13_3_8))
+              (portRef DIB14 (instanceRef pdp_ram_13_3_8))
+              (portRef DIA14 (instanceRef pdp_ram_13_3_8))
+              (portRef DIB13 (instanceRef pdp_ram_13_3_8))
+              (portRef DIA13 (instanceRef pdp_ram_13_3_8))
+              (portRef DIB12 (instanceRef pdp_ram_13_3_8))
+              (portRef DIA12 (instanceRef pdp_ram_13_3_8))
+              (portRef DIB11 (instanceRef pdp_ram_13_3_8))
+              (portRef DIA11 (instanceRef pdp_ram_13_3_8))
+              (portRef DIB10 (instanceRef pdp_ram_13_3_8))
+              (portRef DIA10 (instanceRef pdp_ram_13_3_8))
+              (portRef DIB9 (instanceRef pdp_ram_13_3_8))
+              (portRef DIA9 (instanceRef pdp_ram_13_3_8))
+              (portRef DIB8 (instanceRef pdp_ram_13_3_8))
+              (portRef DIB7 (instanceRef pdp_ram_13_3_8))
+              (portRef DIB6 (instanceRef pdp_ram_13_3_8))
+              (portRef DIB5 (instanceRef pdp_ram_13_3_8))
+              (portRef DIB4 (instanceRef pdp_ram_13_3_8))
+              (portRef DIB3 (instanceRef pdp_ram_13_3_8))
+              (portRef DIB2 (instanceRef pdp_ram_13_3_8))
+              (portRef DIB1 (instanceRef pdp_ram_13_3_8))
+              (portRef DIB0 (instanceRef pdp_ram_13_3_8))
+              (portRef CSB2 (instanceRef pdp_ram_14_0_7))
+              (portRef CSA2 (instanceRef pdp_ram_14_0_7))
+              (portRef CSB1 (instanceRef pdp_ram_14_0_7))
+              (portRef CSA1 (instanceRef pdp_ram_14_0_7))
+              (portRef WEB (instanceRef pdp_ram_14_0_7))
+              (portRef ADB2 (instanceRef pdp_ram_14_0_7))
+              (portRef ADA2 (instanceRef pdp_ram_14_0_7))
+              (portRef ADB1 (instanceRef pdp_ram_14_0_7))
+              (portRef ADA1 (instanceRef pdp_ram_14_0_7))
+              (portRef ADB0 (instanceRef pdp_ram_14_0_7))
+              (portRef ADA0 (instanceRef pdp_ram_14_0_7))
+              (portRef DIB17 (instanceRef pdp_ram_14_0_7))
+              (portRef DIA17 (instanceRef pdp_ram_14_0_7))
+              (portRef DIB16 (instanceRef pdp_ram_14_0_7))
+              (portRef DIA16 (instanceRef pdp_ram_14_0_7))
+              (portRef DIB15 (instanceRef pdp_ram_14_0_7))
+              (portRef DIA15 (instanceRef pdp_ram_14_0_7))
+              (portRef DIB14 (instanceRef pdp_ram_14_0_7))
+              (portRef DIA14 (instanceRef pdp_ram_14_0_7))
+              (portRef DIB13 (instanceRef pdp_ram_14_0_7))
+              (portRef DIA13 (instanceRef pdp_ram_14_0_7))
+              (portRef DIB12 (instanceRef pdp_ram_14_0_7))
+              (portRef DIA12 (instanceRef pdp_ram_14_0_7))
+              (portRef DIB11 (instanceRef pdp_ram_14_0_7))
+              (portRef DIA11 (instanceRef pdp_ram_14_0_7))
+              (portRef DIB10 (instanceRef pdp_ram_14_0_7))
+              (portRef DIA10 (instanceRef pdp_ram_14_0_7))
+              (portRef DIB9 (instanceRef pdp_ram_14_0_7))
+              (portRef DIA9 (instanceRef pdp_ram_14_0_7))
+              (portRef DIB8 (instanceRef pdp_ram_14_0_7))
+              (portRef DIB7 (instanceRef pdp_ram_14_0_7))
+              (portRef DIB6 (instanceRef pdp_ram_14_0_7))
+              (portRef DIB5 (instanceRef pdp_ram_14_0_7))
+              (portRef DIB4 (instanceRef pdp_ram_14_0_7))
+              (portRef DIB3 (instanceRef pdp_ram_14_0_7))
+              (portRef DIB2 (instanceRef pdp_ram_14_0_7))
+              (portRef DIB1 (instanceRef pdp_ram_14_0_7))
+              (portRef DIB0 (instanceRef pdp_ram_14_0_7))
+              (portRef CSB2 (instanceRef pdp_ram_14_1_6))
+              (portRef CSA2 (instanceRef pdp_ram_14_1_6))
+              (portRef CSB1 (instanceRef pdp_ram_14_1_6))
+              (portRef CSA1 (instanceRef pdp_ram_14_1_6))
+              (portRef WEB (instanceRef pdp_ram_14_1_6))
+              (portRef ADB2 (instanceRef pdp_ram_14_1_6))
+              (portRef ADA2 (instanceRef pdp_ram_14_1_6))
+              (portRef ADB1 (instanceRef pdp_ram_14_1_6))
+              (portRef ADA1 (instanceRef pdp_ram_14_1_6))
+              (portRef ADB0 (instanceRef pdp_ram_14_1_6))
+              (portRef ADA0 (instanceRef pdp_ram_14_1_6))
+              (portRef DIB17 (instanceRef pdp_ram_14_1_6))
+              (portRef DIA17 (instanceRef pdp_ram_14_1_6))
+              (portRef DIB16 (instanceRef pdp_ram_14_1_6))
+              (portRef DIA16 (instanceRef pdp_ram_14_1_6))
+              (portRef DIB15 (instanceRef pdp_ram_14_1_6))
+              (portRef DIA15 (instanceRef pdp_ram_14_1_6))
+              (portRef DIB14 (instanceRef pdp_ram_14_1_6))
+              (portRef DIA14 (instanceRef pdp_ram_14_1_6))
+              (portRef DIB13 (instanceRef pdp_ram_14_1_6))
+              (portRef DIA13 (instanceRef pdp_ram_14_1_6))
+              (portRef DIB12 (instanceRef pdp_ram_14_1_6))
+              (portRef DIA12 (instanceRef pdp_ram_14_1_6))
+              (portRef DIB11 (instanceRef pdp_ram_14_1_6))
+              (portRef DIA11 (instanceRef pdp_ram_14_1_6))
+              (portRef DIB10 (instanceRef pdp_ram_14_1_6))
+              (portRef DIA10 (instanceRef pdp_ram_14_1_6))
+              (portRef DIB9 (instanceRef pdp_ram_14_1_6))
+              (portRef DIA9 (instanceRef pdp_ram_14_1_6))
+              (portRef DIB8 (instanceRef pdp_ram_14_1_6))
+              (portRef DIB7 (instanceRef pdp_ram_14_1_6))
+              (portRef DIB6 (instanceRef pdp_ram_14_1_6))
+              (portRef DIB5 (instanceRef pdp_ram_14_1_6))
+              (portRef DIB4 (instanceRef pdp_ram_14_1_6))
+              (portRef DIB3 (instanceRef pdp_ram_14_1_6))
+              (portRef DIB2 (instanceRef pdp_ram_14_1_6))
+              (portRef DIB1 (instanceRef pdp_ram_14_1_6))
+              (portRef DIB0 (instanceRef pdp_ram_14_1_6))
+              (portRef CSB2 (instanceRef pdp_ram_14_2_5))
+              (portRef CSA2 (instanceRef pdp_ram_14_2_5))
+              (portRef CSB1 (instanceRef pdp_ram_14_2_5))
+              (portRef CSA1 (instanceRef pdp_ram_14_2_5))
+              (portRef WEB (instanceRef pdp_ram_14_2_5))
+              (portRef ADB2 (instanceRef pdp_ram_14_2_5))
+              (portRef ADA2 (instanceRef pdp_ram_14_2_5))
+              (portRef ADB1 (instanceRef pdp_ram_14_2_5))
+              (portRef ADA1 (instanceRef pdp_ram_14_2_5))
+              (portRef ADB0 (instanceRef pdp_ram_14_2_5))
+              (portRef ADA0 (instanceRef pdp_ram_14_2_5))
+              (portRef DIB17 (instanceRef pdp_ram_14_2_5))
+              (portRef DIA17 (instanceRef pdp_ram_14_2_5))
+              (portRef DIB16 (instanceRef pdp_ram_14_2_5))
+              (portRef DIA16 (instanceRef pdp_ram_14_2_5))
+              (portRef DIB15 (instanceRef pdp_ram_14_2_5))
+              (portRef DIA15 (instanceRef pdp_ram_14_2_5))
+              (portRef DIB14 (instanceRef pdp_ram_14_2_5))
+              (portRef DIA14 (instanceRef pdp_ram_14_2_5))
+              (portRef DIB13 (instanceRef pdp_ram_14_2_5))
+              (portRef DIA13 (instanceRef pdp_ram_14_2_5))
+              (portRef DIB12 (instanceRef pdp_ram_14_2_5))
+              (portRef DIA12 (instanceRef pdp_ram_14_2_5))
+              (portRef DIB11 (instanceRef pdp_ram_14_2_5))
+              (portRef DIA11 (instanceRef pdp_ram_14_2_5))
+              (portRef DIB10 (instanceRef pdp_ram_14_2_5))
+              (portRef DIA10 (instanceRef pdp_ram_14_2_5))
+              (portRef DIB9 (instanceRef pdp_ram_14_2_5))
+              (portRef DIA9 (instanceRef pdp_ram_14_2_5))
+              (portRef DIB8 (instanceRef pdp_ram_14_2_5))
+              (portRef DIB7 (instanceRef pdp_ram_14_2_5))
+              (portRef DIB6 (instanceRef pdp_ram_14_2_5))
+              (portRef DIB5 (instanceRef pdp_ram_14_2_5))
+              (portRef DIB4 (instanceRef pdp_ram_14_2_5))
+              (portRef DIB3 (instanceRef pdp_ram_14_2_5))
+              (portRef DIB2 (instanceRef pdp_ram_14_2_5))
+              (portRef DIB1 (instanceRef pdp_ram_14_2_5))
+              (portRef DIB0 (instanceRef pdp_ram_14_2_5))
+              (portRef CSB2 (instanceRef pdp_ram_14_3_4))
+              (portRef CSA2 (instanceRef pdp_ram_14_3_4))
+              (portRef CSB1 (instanceRef pdp_ram_14_3_4))
+              (portRef CSA1 (instanceRef pdp_ram_14_3_4))
+              (portRef WEB (instanceRef pdp_ram_14_3_4))
+              (portRef ADB2 (instanceRef pdp_ram_14_3_4))
+              (portRef ADA2 (instanceRef pdp_ram_14_3_4))
+              (portRef ADB1 (instanceRef pdp_ram_14_3_4))
+              (portRef ADA1 (instanceRef pdp_ram_14_3_4))
+              (portRef ADB0 (instanceRef pdp_ram_14_3_4))
+              (portRef ADA0 (instanceRef pdp_ram_14_3_4))
+              (portRef DIB17 (instanceRef pdp_ram_14_3_4))
+              (portRef DIA17 (instanceRef pdp_ram_14_3_4))
+              (portRef DIB16 (instanceRef pdp_ram_14_3_4))
+              (portRef DIA16 (instanceRef pdp_ram_14_3_4))
+              (portRef DIB15 (instanceRef pdp_ram_14_3_4))
+              (portRef DIA15 (instanceRef pdp_ram_14_3_4))
+              (portRef DIB14 (instanceRef pdp_ram_14_3_4))
+              (portRef DIA14 (instanceRef pdp_ram_14_3_4))
+              (portRef DIB13 (instanceRef pdp_ram_14_3_4))
+              (portRef DIA13 (instanceRef pdp_ram_14_3_4))
+              (portRef DIB12 (instanceRef pdp_ram_14_3_4))
+              (portRef DIA12 (instanceRef pdp_ram_14_3_4))
+              (portRef DIB11 (instanceRef pdp_ram_14_3_4))
+              (portRef DIA11 (instanceRef pdp_ram_14_3_4))
+              (portRef DIB10 (instanceRef pdp_ram_14_3_4))
+              (portRef DIA10 (instanceRef pdp_ram_14_3_4))
+              (portRef DIB9 (instanceRef pdp_ram_14_3_4))
+              (portRef DIA9 (instanceRef pdp_ram_14_3_4))
+              (portRef DIB8 (instanceRef pdp_ram_14_3_4))
+              (portRef DIB7 (instanceRef pdp_ram_14_3_4))
+              (portRef DIB6 (instanceRef pdp_ram_14_3_4))
+              (portRef DIB5 (instanceRef pdp_ram_14_3_4))
+              (portRef DIB4 (instanceRef pdp_ram_14_3_4))
+              (portRef DIB3 (instanceRef pdp_ram_14_3_4))
+              (portRef DIB2 (instanceRef pdp_ram_14_3_4))
+              (portRef DIB1 (instanceRef pdp_ram_14_3_4))
+              (portRef DIB0 (instanceRef pdp_ram_14_3_4))
+              (portRef CSB2 (instanceRef pdp_ram_15_0_3))
+              (portRef CSA2 (instanceRef pdp_ram_15_0_3))
+              (portRef CSB1 (instanceRef pdp_ram_15_0_3))
+              (portRef CSA1 (instanceRef pdp_ram_15_0_3))
+              (portRef WEB (instanceRef pdp_ram_15_0_3))
+              (portRef ADB2 (instanceRef pdp_ram_15_0_3))
+              (portRef ADA2 (instanceRef pdp_ram_15_0_3))
+              (portRef ADB1 (instanceRef pdp_ram_15_0_3))
+              (portRef ADA1 (instanceRef pdp_ram_15_0_3))
+              (portRef ADB0 (instanceRef pdp_ram_15_0_3))
+              (portRef ADA0 (instanceRef pdp_ram_15_0_3))
+              (portRef DIB17 (instanceRef pdp_ram_15_0_3))
+              (portRef DIA17 (instanceRef pdp_ram_15_0_3))
+              (portRef DIB16 (instanceRef pdp_ram_15_0_3))
+              (portRef DIA16 (instanceRef pdp_ram_15_0_3))
+              (portRef DIB15 (instanceRef pdp_ram_15_0_3))
+              (portRef DIA15 (instanceRef pdp_ram_15_0_3))
+              (portRef DIB14 (instanceRef pdp_ram_15_0_3))
+              (portRef DIA14 (instanceRef pdp_ram_15_0_3))
+              (portRef DIB13 (instanceRef pdp_ram_15_0_3))
+              (portRef DIA13 (instanceRef pdp_ram_15_0_3))
+              (portRef DIB12 (instanceRef pdp_ram_15_0_3))
+              (portRef DIA12 (instanceRef pdp_ram_15_0_3))
+              (portRef DIB11 (instanceRef pdp_ram_15_0_3))
+              (portRef DIA11 (instanceRef pdp_ram_15_0_3))
+              (portRef DIB10 (instanceRef pdp_ram_15_0_3))
+              (portRef DIA10 (instanceRef pdp_ram_15_0_3))
+              (portRef DIB9 (instanceRef pdp_ram_15_0_3))
+              (portRef DIA9 (instanceRef pdp_ram_15_0_3))
+              (portRef DIB8 (instanceRef pdp_ram_15_0_3))
+              (portRef DIB7 (instanceRef pdp_ram_15_0_3))
+              (portRef DIB6 (instanceRef pdp_ram_15_0_3))
+              (portRef DIB5 (instanceRef pdp_ram_15_0_3))
+              (portRef DIB4 (instanceRef pdp_ram_15_0_3))
+              (portRef DIB3 (instanceRef pdp_ram_15_0_3))
+              (portRef DIB2 (instanceRef pdp_ram_15_0_3))
+              (portRef DIB1 (instanceRef pdp_ram_15_0_3))
+              (portRef DIB0 (instanceRef pdp_ram_15_0_3))
+              (portRef CSB2 (instanceRef pdp_ram_15_1_2))
+              (portRef CSA2 (instanceRef pdp_ram_15_1_2))
+              (portRef CSB1 (instanceRef pdp_ram_15_1_2))
+              (portRef CSA1 (instanceRef pdp_ram_15_1_2))
+              (portRef WEB (instanceRef pdp_ram_15_1_2))
+              (portRef ADB2 (instanceRef pdp_ram_15_1_2))
+              (portRef ADA2 (instanceRef pdp_ram_15_1_2))
+              (portRef ADB1 (instanceRef pdp_ram_15_1_2))
+              (portRef ADA1 (instanceRef pdp_ram_15_1_2))
+              (portRef ADB0 (instanceRef pdp_ram_15_1_2))
+              (portRef ADA0 (instanceRef pdp_ram_15_1_2))
+              (portRef DIB17 (instanceRef pdp_ram_15_1_2))
+              (portRef DIA17 (instanceRef pdp_ram_15_1_2))
+              (portRef DIB16 (instanceRef pdp_ram_15_1_2))
+              (portRef DIA16 (instanceRef pdp_ram_15_1_2))
+              (portRef DIB15 (instanceRef pdp_ram_15_1_2))
+              (portRef DIA15 (instanceRef pdp_ram_15_1_2))
+              (portRef DIB14 (instanceRef pdp_ram_15_1_2))
+              (portRef DIA14 (instanceRef pdp_ram_15_1_2))
+              (portRef DIB13 (instanceRef pdp_ram_15_1_2))
+              (portRef DIA13 (instanceRef pdp_ram_15_1_2))
+              (portRef DIB12 (instanceRef pdp_ram_15_1_2))
+              (portRef DIA12 (instanceRef pdp_ram_15_1_2))
+              (portRef DIB11 (instanceRef pdp_ram_15_1_2))
+              (portRef DIA11 (instanceRef pdp_ram_15_1_2))
+              (portRef DIB10 (instanceRef pdp_ram_15_1_2))
+              (portRef DIA10 (instanceRef pdp_ram_15_1_2))
+              (portRef DIB9 (instanceRef pdp_ram_15_1_2))
+              (portRef DIA9 (instanceRef pdp_ram_15_1_2))
+              (portRef DIB8 (instanceRef pdp_ram_15_1_2))
+              (portRef DIB7 (instanceRef pdp_ram_15_1_2))
+              (portRef DIB6 (instanceRef pdp_ram_15_1_2))
+              (portRef DIB5 (instanceRef pdp_ram_15_1_2))
+              (portRef DIB4 (instanceRef pdp_ram_15_1_2))
+              (portRef DIB3 (instanceRef pdp_ram_15_1_2))
+              (portRef DIB2 (instanceRef pdp_ram_15_1_2))
+              (portRef DIB1 (instanceRef pdp_ram_15_1_2))
+              (portRef DIB0 (instanceRef pdp_ram_15_1_2))
+              (portRef CSB2 (instanceRef pdp_ram_15_2_1))
+              (portRef CSA2 (instanceRef pdp_ram_15_2_1))
+              (portRef CSB1 (instanceRef pdp_ram_15_2_1))
+              (portRef CSA1 (instanceRef pdp_ram_15_2_1))
+              (portRef WEB (instanceRef pdp_ram_15_2_1))
+              (portRef ADB2 (instanceRef pdp_ram_15_2_1))
+              (portRef ADA2 (instanceRef pdp_ram_15_2_1))
+              (portRef ADB1 (instanceRef pdp_ram_15_2_1))
+              (portRef ADA1 (instanceRef pdp_ram_15_2_1))
+              (portRef ADB0 (instanceRef pdp_ram_15_2_1))
+              (portRef ADA0 (instanceRef pdp_ram_15_2_1))
+              (portRef DIB17 (instanceRef pdp_ram_15_2_1))
+              (portRef DIA17 (instanceRef pdp_ram_15_2_1))
+              (portRef DIB16 (instanceRef pdp_ram_15_2_1))
+              (portRef DIA16 (instanceRef pdp_ram_15_2_1))
+              (portRef DIB15 (instanceRef pdp_ram_15_2_1))
+              (portRef DIA15 (instanceRef pdp_ram_15_2_1))
+              (portRef DIB14 (instanceRef pdp_ram_15_2_1))
+              (portRef DIA14 (instanceRef pdp_ram_15_2_1))
+              (portRef DIB13 (instanceRef pdp_ram_15_2_1))
+              (portRef DIA13 (instanceRef pdp_ram_15_2_1))
+              (portRef DIB12 (instanceRef pdp_ram_15_2_1))
+              (portRef DIA12 (instanceRef pdp_ram_15_2_1))
+              (portRef DIB11 (instanceRef pdp_ram_15_2_1))
+              (portRef DIA11 (instanceRef pdp_ram_15_2_1))
+              (portRef DIB10 (instanceRef pdp_ram_15_2_1))
+              (portRef DIA10 (instanceRef pdp_ram_15_2_1))
+              (portRef DIB9 (instanceRef pdp_ram_15_2_1))
+              (portRef DIA9 (instanceRef pdp_ram_15_2_1))
+              (portRef DIB8 (instanceRef pdp_ram_15_2_1))
+              (portRef DIB7 (instanceRef pdp_ram_15_2_1))
+              (portRef DIB6 (instanceRef pdp_ram_15_2_1))
+              (portRef DIB5 (instanceRef pdp_ram_15_2_1))
+              (portRef DIB4 (instanceRef pdp_ram_15_2_1))
+              (portRef DIB3 (instanceRef pdp_ram_15_2_1))
+              (portRef DIB2 (instanceRef pdp_ram_15_2_1))
+              (portRef DIB1 (instanceRef pdp_ram_15_2_1))
+              (portRef DIB0 (instanceRef pdp_ram_15_2_1))
+              (portRef CSB2 (instanceRef pdp_ram_15_3_0))
+              (portRef CSA2 (instanceRef pdp_ram_15_3_0))
+              (portRef CSB1 (instanceRef pdp_ram_15_3_0))
+              (portRef CSA1 (instanceRef pdp_ram_15_3_0))
+              (portRef WEB (instanceRef pdp_ram_15_3_0))
+              (portRef ADB2 (instanceRef pdp_ram_15_3_0))
+              (portRef ADA2 (instanceRef pdp_ram_15_3_0))
+              (portRef ADB1 (instanceRef pdp_ram_15_3_0))
+              (portRef ADA1 (instanceRef pdp_ram_15_3_0))
+              (portRef ADB0 (instanceRef pdp_ram_15_3_0))
+              (portRef ADA0 (instanceRef pdp_ram_15_3_0))
+              (portRef DIB17 (instanceRef pdp_ram_15_3_0))
+              (portRef DIA17 (instanceRef pdp_ram_15_3_0))
+              (portRef DIB16 (instanceRef pdp_ram_15_3_0))
+              (portRef DIA16 (instanceRef pdp_ram_15_3_0))
+              (portRef DIB15 (instanceRef pdp_ram_15_3_0))
+              (portRef DIA15 (instanceRef pdp_ram_15_3_0))
+              (portRef DIB14 (instanceRef pdp_ram_15_3_0))
+              (portRef DIA14 (instanceRef pdp_ram_15_3_0))
+              (portRef DIB13 (instanceRef pdp_ram_15_3_0))
+              (portRef DIA13 (instanceRef pdp_ram_15_3_0))
+              (portRef DIB12 (instanceRef pdp_ram_15_3_0))
+              (portRef DIA12 (instanceRef pdp_ram_15_3_0))
+              (portRef DIB11 (instanceRef pdp_ram_15_3_0))
+              (portRef DIA11 (instanceRef pdp_ram_15_3_0))
+              (portRef DIB10 (instanceRef pdp_ram_15_3_0))
+              (portRef DIA10 (instanceRef pdp_ram_15_3_0))
+              (portRef DIB9 (instanceRef pdp_ram_15_3_0))
+              (portRef DIA9 (instanceRef pdp_ram_15_3_0))
+              (portRef DIB8 (instanceRef pdp_ram_15_3_0))
+              (portRef DIB7 (instanceRef pdp_ram_15_3_0))
+              (portRef DIB6 (instanceRef pdp_ram_15_3_0))
+              (portRef DIB5 (instanceRef pdp_ram_15_3_0))
+              (portRef DIB4 (instanceRef pdp_ram_15_3_0))
+              (portRef DIB3 (instanceRef pdp_ram_15_3_0))
+              (portRef DIB2 (instanceRef pdp_ram_15_3_0))
+              (portRef DIB1 (instanceRef pdp_ram_15_3_0))
+              (portRef DIB0 (instanceRef pdp_ram_15_3_0))
+              (portRef CD (instanceRef FF_24))
+              (portRef CD (instanceRef FF_23))
+              (portRef CD (instanceRef FF_22))
+              (portRef CD (instanceRef FF_21))
+              (portRef CD (instanceRef FF_20))
+              (portRef CD (instanceRef FF_19))
+              (portRef CD (instanceRef FF_18))
+              (portRef CD (instanceRef FF_17))
+              (portRef B0 (instanceRef bdcnt_bctr_cia))
+              (portRef A0 (instanceRef bdcnt_bctr_cia))
+              (portRef A1 (instanceRef e_cmp_0))
+              (portRef A0 (instanceRef e_cmp_1))
+              (portRef A1 (instanceRef e_cmp_1))
+              (portRef A0 (instanceRef e_cmp_2))
+              (portRef A1 (instanceRef e_cmp_2))
+              (portRef A0 (instanceRef e_cmp_3))
+              (portRef A1 (instanceRef e_cmp_3))
+              (portRef A0 (instanceRef e_cmp_4))
+              (portRef A1 (instanceRef e_cmp_4))
+              (portRef A0 (instanceRef e_cmp_5))
+              (portRef A1 (instanceRef e_cmp_5))
+              (portRef A0 (instanceRef e_cmp_6))
+              (portRef A1 (instanceRef e_cmp_6))
+              (portRef A0 (instanceRef e_cmp_7))
+              (portRef A1 (instanceRef e_cmp_7))
+              (portRef B1 (instanceRef a0))
+              (portRef B0 (instanceRef a0))
+              (portRef A1 (instanceRef a0))
+              (portRef A0 (instanceRef a0))
+              (portRef B1 (instanceRef a1))
+              (portRef B0 (instanceRef a1))
+              (portRef A1 (instanceRef a1))
+              (portRef A0 (instanceRef a1))
+              (portRef B0 (instanceRef w_ctr_cia))
+              (portRef A0 (instanceRef w_ctr_cia))
+              (portRef B1 (instanceRef w_ctr_0))
+              (portRef B0 (instanceRef w_ctr_0))
+              (portRef B1 (instanceRef w_ctr_1))
+              (portRef B0 (instanceRef w_ctr_1))
+              (portRef B1 (instanceRef w_ctr_2))
+              (portRef B0 (instanceRef w_ctr_2))
+              (portRef B1 (instanceRef w_ctr_3))
+              (portRef B0 (instanceRef w_ctr_3))
+              (portRef B1 (instanceRef w_ctr_4))
+              (portRef B0 (instanceRef w_ctr_4))
+              (portRef B1 (instanceRef w_ctr_5))
+              (portRef B0 (instanceRef w_ctr_5))
+              (portRef B1 (instanceRef w_ctr_6))
+              (portRef B0 (instanceRef w_ctr_6))
+              (portRef B1 (instanceRef w_ctr_7))
+              (portRef B0 (instanceRef w_ctr_7))
+              (portRef B0 (instanceRef r_ctr_cia))
+              (portRef A0 (instanceRef r_ctr_cia))
+              (portRef B1 (instanceRef r_ctr_0))
+              (portRef B0 (instanceRef r_ctr_0))
+              (portRef B1 (instanceRef r_ctr_1))
+              (portRef B0 (instanceRef r_ctr_1))
+              (portRef B1 (instanceRef r_ctr_2))
+              (portRef B0 (instanceRef r_ctr_2))
+              (portRef B1 (instanceRef r_ctr_3))
+              (portRef B0 (instanceRef r_ctr_3))
+              (portRef B1 (instanceRef r_ctr_4))
+              (portRef B0 (instanceRef r_ctr_4))
+              (portRef B1 (instanceRef r_ctr_5))
+              (portRef B0 (instanceRef r_ctr_5))
+              (portRef B1 (instanceRef r_ctr_6))
+              (portRef B0 (instanceRef r_ctr_6))
+              (portRef B1 (instanceRef r_ctr_7))
+              (portRef B0 (instanceRef r_ctr_7))
+              (portRef B1 (instanceRef wcnt_8))
+              (portRef B0 (instanceRef wcnt_8))
+              (portRef A1 (instanceRef wcnt_8))
+              (portRef B0 (instanceRef af_set_cmp_ci_a))
+              (portRef A0 (instanceRef af_set_cmp_ci_a))
+              (portRef B1 (instanceRef af_set_cmp_7))
+              (portRef B1 (instanceRef a2))
+              (portRef B0 (instanceRef a2))
+              (portRef A1 (instanceRef a2))
+              (portRef A0 (instanceRef a2))))
+          (net af_set_c
+            (joined
+              (portRef CIN (instanceRef a2))
+              (portRef COUT (instanceRef af_set_cmp_7))))
+          (net partial_full
+            (joined
+              (portRef AlmostFull)
+              (portRef Q (instanceRef FF_0))))
+          (net Full
+            (joined
+              (portRef Full)
+              (portRef Q (instanceRef FF_89))
+              (portRef A (instanceRef INV_13))
+              (portRef AD0 (instanceRef LUT4_128))))
+          (net Empty
+            (joined
+              (portRef Empty)
+              (portRef Q (instanceRef FF_90))
+              (portRef A (instanceRef INV_12))
+              (portRef AD0 (instanceRef LUT4_129))))
+          (net WCNT15
+            (joined
+              (portRef (member WCNT 0))
+              (portRef A1 (instanceRef g_cmp_7))
+              (portRef Q (instanceRef FF_91))
+              (portRef A1 (instanceRef bdcnt_bctr_7))
+              (portRef B1 (instanceRef e_cmp_7))))
+          (net WCNT14
+            (joined
+              (portRef (member WCNT 1))
+              (portRef A0 (instanceRef g_cmp_7))
+              (portRef Q (instanceRef FF_92))
+              (portRef A0 (instanceRef bdcnt_bctr_7))
+              (portRef B0 (instanceRef e_cmp_7))))
+          (net WCNT13
+            (joined
+              (portRef (member WCNT 2))
+              (portRef A1 (instanceRef g_cmp_6))
+              (portRef Q (instanceRef FF_93))
+              (portRef A1 (instanceRef bdcnt_bctr_6))
+              (portRef B1 (instanceRef e_cmp_6))))
+          (net WCNT12
+            (joined
+              (portRef (member WCNT 3))
+              (portRef A0 (instanceRef g_cmp_6))
+              (portRef Q (instanceRef FF_94))
+              (portRef A0 (instanceRef bdcnt_bctr_6))
+              (portRef B0 (instanceRef e_cmp_6))))
+          (net WCNT11
+            (joined
+              (portRef (member WCNT 4))
+              (portRef A1 (instanceRef g_cmp_5))
+              (portRef Q (instanceRef FF_95))
+              (portRef A1 (instanceRef bdcnt_bctr_5))
+              (portRef B1 (instanceRef e_cmp_5))))
+          (net WCNT10
+            (joined
+              (portRef (member WCNT 5))
+              (portRef A0 (instanceRef g_cmp_5))
+              (portRef Q (instanceRef FF_96))
+              (portRef A0 (instanceRef bdcnt_bctr_5))
+              (portRef B0 (instanceRef e_cmp_5))))
+          (net WCNT9
+            (joined
+              (portRef (member WCNT 6))
+              (portRef A1 (instanceRef g_cmp_4))
+              (portRef Q (instanceRef FF_97))
+              (portRef A1 (instanceRef bdcnt_bctr_4))
+              (portRef B1 (instanceRef e_cmp_4))))
+          (net WCNT8
+            (joined
+              (portRef (member WCNT 7))
+              (portRef A0 (instanceRef g_cmp_4))
+              (portRef Q (instanceRef FF_98))
+              (portRef A0 (instanceRef bdcnt_bctr_4))
+              (portRef B0 (instanceRef e_cmp_4))))
+          (net WCNT7
+            (joined
+              (portRef (member WCNT 8))
+              (portRef A1 (instanceRef g_cmp_3))
+              (portRef Q (instanceRef FF_99))
+              (portRef A1 (instanceRef bdcnt_bctr_3))
+              (portRef B1 (instanceRef e_cmp_3))))
+          (net WCNT6
+            (joined
+              (portRef (member WCNT 9))
+              (portRef A0 (instanceRef g_cmp_3))
+              (portRef Q (instanceRef FF_100))
+              (portRef A0 (instanceRef bdcnt_bctr_3))
+              (portRef B0 (instanceRef e_cmp_3))))
+          (net WCNT5
+            (joined
+              (portRef (member WCNT 10))
+              (portRef A1 (instanceRef g_cmp_2))
+              (portRef Q (instanceRef FF_101))
+              (portRef A1 (instanceRef bdcnt_bctr_2))
+              (portRef B1 (instanceRef e_cmp_2))))
+          (net WCNT4
+            (joined
+              (portRef (member WCNT 11))
+              (portRef A0 (instanceRef g_cmp_2))
+              (portRef Q (instanceRef FF_102))
+              (portRef A0 (instanceRef bdcnt_bctr_2))
+              (portRef B0 (instanceRef e_cmp_2))))
+          (net WCNT3
+            (joined
+              (portRef (member WCNT 12))
+              (portRef A1 (instanceRef g_cmp_1))
+              (portRef Q (instanceRef FF_103))
+              (portRef A1 (instanceRef bdcnt_bctr_1))
+              (portRef B1 (instanceRef e_cmp_1))))
+          (net WCNT2
+            (joined
+              (portRef (member WCNT 13))
+              (portRef A0 (instanceRef g_cmp_1))
+              (portRef Q (instanceRef FF_104))
+              (portRef A0 (instanceRef bdcnt_bctr_1))
+              (portRef B0 (instanceRef e_cmp_1))))
+          (net WCNT1
+            (joined
+              (portRef (member WCNT 14))
+              (portRef A1 (instanceRef g_cmp_0))
+              (portRef Q (instanceRef FF_105))
+              (portRef A1 (instanceRef bdcnt_bctr_0))
+              (portRef B1 (instanceRef e_cmp_0))))
+          (net WCNT0
+            (joined
+              (portRef (member WCNT 15))
+              (portRef A0 (instanceRef g_cmp_0))
+              (portRef Q (instanceRef FF_106))
+              (portRef A0 (instanceRef bdcnt_bctr_0))
+              (portRef B0 (instanceRef e_cmp_0))))
+          (net dataout35
+            (joined
+              (portRef (member Q 0))
+              (portRef Z (instanceRef mux_0))))
+          (net dataout34
+            (joined
+              (portRef (member Q 1))
+              (portRef Z (instanceRef mux_1))))
+          (net dataout33
+            (joined
+              (portRef (member Q 2))
+              (portRef Z (instanceRef mux_2))))
+          (net dataout32
+            (joined
+              (portRef (member Q 3))
+              (portRef Z (instanceRef mux_3))))
+          (net dataout31
+            (joined
+              (portRef (member Q 4))
+              (portRef Z (instanceRef mux_4))))
+          (net dataout30
+            (joined
+              (portRef (member Q 5))
+              (portRef Z (instanceRef mux_5))))
+          (net dataout29
+            (joined
+              (portRef (member Q 6))
+              (portRef Z (instanceRef mux_6))))
+          (net dataout28
+            (joined
+              (portRef (member Q 7))
+              (portRef Z (instanceRef mux_7))))
+          (net dataout27
+            (joined
+              (portRef (member Q 8))
+              (portRef Z (instanceRef mux_8))))
+          (net dataout26
+            (joined
+              (portRef (member Q 9))
+              (portRef Z (instanceRef mux_9))))
+          (net dataout25
+            (joined
+              (portRef (member Q 10))
+              (portRef Z (instanceRef mux_10))))
+          (net dataout24
+            (joined
+              (portRef (member Q 11))
+              (portRef Z (instanceRef mux_11))))
+          (net dataout23
+            (joined
+              (portRef (member Q 12))
+              (portRef Z (instanceRef mux_12))))
+          (net dataout22
+            (joined
+              (portRef (member Q 13))
+              (portRef Z (instanceRef mux_13))))
+          (net dataout21
+            (joined
+              (portRef (member Q 14))
+              (portRef Z (instanceRef mux_14))))
+          (net dataout20
+            (joined
+              (portRef (member Q 15))
+              (portRef Z (instanceRef mux_15))))
+          (net dataout19
+            (joined
+              (portRef (member Q 16))
+              (portRef Z (instanceRef mux_16))))
+          (net dataout18
+            (joined
+              (portRef (member Q 17))
+              (portRef Z (instanceRef mux_17))))
+          (net dataout17
+            (joined
+              (portRef (member Q 18))
+              (portRef Z (instanceRef mux_18))))
+          (net dataout16
+            (joined
+              (portRef (member Q 19))
+              (portRef Z (instanceRef mux_19))))
+          (net dataout15
+            (joined
+              (portRef (member Q 20))
+              (portRef Z (instanceRef mux_20))))
+          (net dataout14
+            (joined
+              (portRef (member Q 21))
+              (portRef Z (instanceRef mux_21))))
+          (net dataout13
+            (joined
+              (portRef (member Q 22))
+              (portRef Z (instanceRef mux_22))))
+          (net dataout12
+            (joined
+              (portRef (member Q 23))
+              (portRef Z (instanceRef mux_23))))
+          (net dataout11
+            (joined
+              (portRef (member Q 24))
+              (portRef Z (instanceRef mux_24))))
+          (net dataout10
+            (joined
+              (portRef (member Q 25))
+              (portRef Z (instanceRef mux_25))))
+          (net dataout9
+            (joined
+              (portRef (member Q 26))
+              (portRef Z (instanceRef mux_26))))
+          (net dataout8
+            (joined
+              (portRef (member Q 27))
+              (portRef Z (instanceRef mux_27))))
+          (net dataout7
+            (joined
+              (portRef (member Q 28))
+              (portRef Z (instanceRef mux_28))))
+          (net dataout6
+            (joined
+              (portRef (member Q 29))
+              (portRef Z (instanceRef mux_29))))
+          (net dataout5
+            (joined
+              (portRef (member Q 30))
+              (portRef Z (instanceRef mux_30))))
+          (net dataout4
+            (joined
+              (portRef (member Q 31))
+              (portRef Z (instanceRef mux_31))))
+          (net dataout3
+            (joined
+              (portRef (member Q 32))
+              (portRef Z (instanceRef mux_32))))
+          (net dataout2
+            (joined
+              (portRef (member Q 33))
+              (portRef Z (instanceRef mux_33))))
+          (net dataout1
+            (joined
+              (portRef (member Q 34))
+              (portRef Z (instanceRef mux_34))))
+          (net dataout0
+            (joined
+              (portRef (member Q 35))
+              (portRef Z (instanceRef mux_35))))
+          (net AmFullThresh14
+            (joined
+              (portRef (member AmFullThresh 0))
+              (portRef B0 (instanceRef af_set_cmp_7))))
+          (net AmFullThresh13
+            (joined
+              (portRef (member AmFullThresh 1))
+              (portRef B1 (instanceRef af_set_cmp_6))))
+          (net AmFullThresh12
+            (joined
+              (portRef (member AmFullThresh 2))
+              (portRef B0 (instanceRef af_set_cmp_6))))
+          (net AmFullThresh11
+            (joined
+              (portRef (member AmFullThresh 3))
+              (portRef B1 (instanceRef af_set_cmp_5))))
+          (net AmFullThresh10
+            (joined
+              (portRef (member AmFullThresh 4))
+              (portRef B0 (instanceRef af_set_cmp_5))))
+          (net AmFullThresh9
+            (joined
+              (portRef (member AmFullThresh 5))
+              (portRef B1 (instanceRef af_set_cmp_4))))
+          (net AmFullThresh8
+            (joined
+              (portRef (member AmFullThresh 6))
+              (portRef B0 (instanceRef af_set_cmp_4))))
+          (net AmFullThresh7
+            (joined
+              (portRef (member AmFullThresh 7))
+              (portRef B1 (instanceRef af_set_cmp_3))))
+          (net AmFullThresh6
+            (joined
+              (portRef (member AmFullThresh 8))
+              (portRef B0 (instanceRef af_set_cmp_3))))
+          (net AmFullThresh5
+            (joined
+              (portRef (member AmFullThresh 9))
+              (portRef B1 (instanceRef af_set_cmp_2))))
+          (net AmFullThresh4
+            (joined
+              (portRef (member AmFullThresh 10))
+              (portRef B0 (instanceRef af_set_cmp_2))))
+          (net AmFullThresh3
+            (joined
+              (portRef (member AmFullThresh 11))
+              (portRef B1 (instanceRef af_set_cmp_1))))
+          (net AmFullThresh2
+            (joined
+              (portRef (member AmFullThresh 12))
+              (portRef B0 (instanceRef af_set_cmp_1))))
+          (net AmFullThresh1
+            (joined
+              (portRef (member AmFullThresh 13))
+              (portRef B1 (instanceRef af_set_cmp_0))))
+          (net AmFullThresh0
+            (joined
+              (portRef (member AmFullThresh 14))
+              (portRef B0 (instanceRef af_set_cmp_0))))
+          (net reset
+            (joined
+              (portRef Reset)
+              (portRef RSTB (instanceRef pdp_ram_0_0_63))
+              (portRef RSTA (instanceRef pdp_ram_0_0_63))
+              (portRef RSTB (instanceRef pdp_ram_0_1_62))
+              (portRef RSTA (instanceRef pdp_ram_0_1_62))
+              (portRef RSTB (instanceRef pdp_ram_0_2_61))
+              (portRef RSTA (instanceRef pdp_ram_0_2_61))
+              (portRef RSTB (instanceRef pdp_ram_0_3_60))
+              (portRef RSTA (instanceRef pdp_ram_0_3_60))
+              (portRef RSTB (instanceRef pdp_ram_1_0_59))
+              (portRef RSTA (instanceRef pdp_ram_1_0_59))
+              (portRef RSTB (instanceRef pdp_ram_1_1_58))
+              (portRef RSTA (instanceRef pdp_ram_1_1_58))
+              (portRef RSTB (instanceRef pdp_ram_1_2_57))
+              (portRef RSTA (instanceRef pdp_ram_1_2_57))
+              (portRef RSTB (instanceRef pdp_ram_1_3_56))
+              (portRef RSTA (instanceRef pdp_ram_1_3_56))
+              (portRef RSTB (instanceRef pdp_ram_2_0_55))
+              (portRef RSTA (instanceRef pdp_ram_2_0_55))
+              (portRef RSTB (instanceRef pdp_ram_2_1_54))
+              (portRef RSTA (instanceRef pdp_ram_2_1_54))
+              (portRef RSTB (instanceRef pdp_ram_2_2_53))
+              (portRef RSTA (instanceRef pdp_ram_2_2_53))
+              (portRef RSTB (instanceRef pdp_ram_2_3_52))
+              (portRef RSTA (instanceRef pdp_ram_2_3_52))
+              (portRef RSTB (instanceRef pdp_ram_3_0_51))
+              (portRef RSTA (instanceRef pdp_ram_3_0_51))
+              (portRef RSTB (instanceRef pdp_ram_3_1_50))
+              (portRef RSTA (instanceRef pdp_ram_3_1_50))
+              (portRef RSTB (instanceRef pdp_ram_3_2_49))
+              (portRef RSTA (instanceRef pdp_ram_3_2_49))
+              (portRef RSTB (instanceRef pdp_ram_3_3_48))
+              (portRef RSTA (instanceRef pdp_ram_3_3_48))
+              (portRef RSTB (instanceRef pdp_ram_4_0_47))
+              (portRef RSTA (instanceRef pdp_ram_4_0_47))
+              (portRef RSTB (instanceRef pdp_ram_4_1_46))
+              (portRef RSTA (instanceRef pdp_ram_4_1_46))
+              (portRef RSTB (instanceRef pdp_ram_4_2_45))
+              (portRef RSTA (instanceRef pdp_ram_4_2_45))
+              (portRef RSTB (instanceRef pdp_ram_4_3_44))
+              (portRef RSTA (instanceRef pdp_ram_4_3_44))
+              (portRef RSTB (instanceRef pdp_ram_5_0_43))
+              (portRef RSTA (instanceRef pdp_ram_5_0_43))
+              (portRef RSTB (instanceRef pdp_ram_5_1_42))
+              (portRef RSTA (instanceRef pdp_ram_5_1_42))
+              (portRef RSTB (instanceRef pdp_ram_5_2_41))
+              (portRef RSTA (instanceRef pdp_ram_5_2_41))
+              (portRef RSTB (instanceRef pdp_ram_5_3_40))
+              (portRef RSTA (instanceRef pdp_ram_5_3_40))
+              (portRef RSTB (instanceRef pdp_ram_6_0_39))
+              (portRef RSTA (instanceRef pdp_ram_6_0_39))
+              (portRef RSTB (instanceRef pdp_ram_6_1_38))
+              (portRef RSTA (instanceRef pdp_ram_6_1_38))
+              (portRef RSTB (instanceRef pdp_ram_6_2_37))
+              (portRef RSTA (instanceRef pdp_ram_6_2_37))
+              (portRef RSTB (instanceRef pdp_ram_6_3_36))
+              (portRef RSTA (instanceRef pdp_ram_6_3_36))
+              (portRef RSTB (instanceRef pdp_ram_7_0_35))
+              (portRef RSTA (instanceRef pdp_ram_7_0_35))
+              (portRef RSTB (instanceRef pdp_ram_7_1_34))
+              (portRef RSTA (instanceRef pdp_ram_7_1_34))
+              (portRef RSTB (instanceRef pdp_ram_7_2_33))
+              (portRef RSTA (instanceRef pdp_ram_7_2_33))
+              (portRef RSTB (instanceRef pdp_ram_7_3_32))
+              (portRef RSTA (instanceRef pdp_ram_7_3_32))
+              (portRef RSTB (instanceRef pdp_ram_8_0_31))
+              (portRef RSTA (instanceRef pdp_ram_8_0_31))
+              (portRef RSTB (instanceRef pdp_ram_8_1_30))
+              (portRef RSTA (instanceRef pdp_ram_8_1_30))
+              (portRef RSTB (instanceRef pdp_ram_8_2_29))
+              (portRef RSTA (instanceRef pdp_ram_8_2_29))
+              (portRef RSTB (instanceRef pdp_ram_8_3_28))
+              (portRef RSTA (instanceRef pdp_ram_8_3_28))
+              (portRef RSTB (instanceRef pdp_ram_9_0_27))
+              (portRef RSTA (instanceRef pdp_ram_9_0_27))
+              (portRef RSTB (instanceRef pdp_ram_9_1_26))
+              (portRef RSTA (instanceRef pdp_ram_9_1_26))
+              (portRef RSTB (instanceRef pdp_ram_9_2_25))
+              (portRef RSTA (instanceRef pdp_ram_9_2_25))
+              (portRef RSTB (instanceRef pdp_ram_9_3_24))
+              (portRef RSTA (instanceRef pdp_ram_9_3_24))
+              (portRef RSTB (instanceRef pdp_ram_10_0_23))
+              (portRef RSTA (instanceRef pdp_ram_10_0_23))
+              (portRef RSTB (instanceRef pdp_ram_10_1_22))
+              (portRef RSTA (instanceRef pdp_ram_10_1_22))
+              (portRef RSTB (instanceRef pdp_ram_10_2_21))
+              (portRef RSTA (instanceRef pdp_ram_10_2_21))
+              (portRef RSTB (instanceRef pdp_ram_10_3_20))
+              (portRef RSTA (instanceRef pdp_ram_10_3_20))
+              (portRef RSTB (instanceRef pdp_ram_11_0_19))
+              (portRef RSTA (instanceRef pdp_ram_11_0_19))
+              (portRef RSTB (instanceRef pdp_ram_11_1_18))
+              (portRef RSTA (instanceRef pdp_ram_11_1_18))
+              (portRef RSTB (instanceRef pdp_ram_11_2_17))
+              (portRef RSTA (instanceRef pdp_ram_11_2_17))
+              (portRef RSTB (instanceRef pdp_ram_11_3_16))
+              (portRef RSTA (instanceRef pdp_ram_11_3_16))
+              (portRef RSTB (instanceRef pdp_ram_12_0_15))
+              (portRef RSTA (instanceRef pdp_ram_12_0_15))
+              (portRef RSTB (instanceRef pdp_ram_12_1_14))
+              (portRef RSTA (instanceRef pdp_ram_12_1_14))
+              (portRef RSTB (instanceRef pdp_ram_12_2_13))
+              (portRef RSTA (instanceRef pdp_ram_12_2_13))
+              (portRef RSTB (instanceRef pdp_ram_12_3_12))
+              (portRef RSTA (instanceRef pdp_ram_12_3_12))
+              (portRef RSTB (instanceRef pdp_ram_13_0_11))
+              (portRef RSTA (instanceRef pdp_ram_13_0_11))
+              (portRef RSTB (instanceRef pdp_ram_13_1_10))
+              (portRef RSTA (instanceRef pdp_ram_13_1_10))
+              (portRef RSTB (instanceRef pdp_ram_13_2_9))
+              (portRef RSTA (instanceRef pdp_ram_13_2_9))
+              (portRef RSTB (instanceRef pdp_ram_13_3_8))
+              (portRef RSTA (instanceRef pdp_ram_13_3_8))
+              (portRef RSTB (instanceRef pdp_ram_14_0_7))
+              (portRef RSTA (instanceRef pdp_ram_14_0_7))
+              (portRef RSTB (instanceRef pdp_ram_14_1_6))
+              (portRef RSTA (instanceRef pdp_ram_14_1_6))
+              (portRef RSTB (instanceRef pdp_ram_14_2_5))
+              (portRef RSTA (instanceRef pdp_ram_14_2_5))
+              (portRef RSTB (instanceRef pdp_ram_14_3_4))
+              (portRef RSTA (instanceRef pdp_ram_14_3_4))
+              (portRef RSTB (instanceRef pdp_ram_15_0_3))
+              (portRef RSTA (instanceRef pdp_ram_15_0_3))
+              (portRef RSTB (instanceRef pdp_ram_15_1_2))
+              (portRef RSTA (instanceRef pdp_ram_15_1_2))
+              (portRef RSTB (instanceRef pdp_ram_15_2_1))
+              (portRef RSTA (instanceRef pdp_ram_15_2_1))
+              (portRef RSTB (instanceRef pdp_ram_15_3_0))
+              (portRef RSTA (instanceRef pdp_ram_15_3_0))
+              (portRef CD (instanceRef FF_106))
+              (portRef CD (instanceRef FF_105))
+              (portRef CD (instanceRef FF_104))
+              (portRef CD (instanceRef FF_103))
+              (portRef CD (instanceRef FF_102))
+              (portRef CD (instanceRef FF_101))
+              (portRef CD (instanceRef FF_100))
+              (portRef CD (instanceRef FF_99))
+              (portRef CD (instanceRef FF_98))
+              (portRef CD (instanceRef FF_97))
+              (portRef CD (instanceRef FF_96))
+              (portRef CD (instanceRef FF_95))
+              (portRef CD (instanceRef FF_94))
+              (portRef CD (instanceRef FF_93))
+              (portRef CD (instanceRef FF_92))
+              (portRef CD (instanceRef FF_91))
+              (portRef PD (instanceRef FF_90))
+              (portRef CD (instanceRef FF_89))
+              (portRef PD (instanceRef FF_88))
+              (portRef CD (instanceRef FF_87))
+              (portRef CD (instanceRef FF_86))
+              (portRef CD (instanceRef FF_85))
+              (portRef CD (instanceRef FF_84))
+              (portRef CD (instanceRef FF_83))
+              (portRef CD (instanceRef FF_82))
+              (portRef CD (instanceRef FF_81))
+              (portRef CD (instanceRef FF_80))
+              (portRef CD (instanceRef FF_79))
+              (portRef CD (instanceRef FF_78))
+              (portRef CD (instanceRef FF_77))
+              (portRef CD (instanceRef FF_76))
+              (portRef CD (instanceRef FF_75))
+              (portRef CD (instanceRef FF_74))
+              (portRef CD (instanceRef FF_73))
+              (portRef PD (instanceRef FF_72))
+              (portRef CD (instanceRef FF_71))
+              (portRef CD (instanceRef FF_70))
+              (portRef CD (instanceRef FF_69))
+              (portRef CD (instanceRef FF_68))
+              (portRef CD (instanceRef FF_67))
+              (portRef CD (instanceRef FF_66))
+              (portRef CD (instanceRef FF_65))
+              (portRef CD (instanceRef FF_64))
+              (portRef CD (instanceRef FF_63))
+              (portRef CD (instanceRef FF_62))
+              (portRef CD (instanceRef FF_61))
+              (portRef CD (instanceRef FF_60))
+              (portRef CD (instanceRef FF_59))
+              (portRef CD (instanceRef FF_58))
+              (portRef CD (instanceRef FF_57))
+              (portRef CD (instanceRef FF_56))
+              (portRef CD (instanceRef FF_55))
+              (portRef CD (instanceRef FF_54))
+              (portRef CD (instanceRef FF_53))
+              (portRef CD (instanceRef FF_52))
+              (portRef CD (instanceRef FF_51))
+              (portRef CD (instanceRef FF_50))
+              (portRef CD (instanceRef FF_49))
+              (portRef CD (instanceRef FF_48))
+              (portRef CD (instanceRef FF_47))
+              (portRef CD (instanceRef FF_46))
+              (portRef CD (instanceRef FF_45))
+              (portRef CD (instanceRef FF_44))
+              (portRef CD (instanceRef FF_43))
+              (portRef CD (instanceRef FF_42))
+              (portRef CD (instanceRef FF_41))
+              (portRef CD (instanceRef FF_40))
+              (portRef CD (instanceRef FF_39))
+              (portRef CD (instanceRef FF_38))
+              (portRef CD (instanceRef FF_37))
+              (portRef CD (instanceRef FF_36))
+              (portRef CD (instanceRef FF_35))
+              (portRef CD (instanceRef FF_34))
+              (portRef CD (instanceRef FF_33))
+              (portRef CD (instanceRef FF_32))
+              (portRef CD (instanceRef FF_31))
+              (portRef CD (instanceRef FF_30))
+              (portRef CD (instanceRef FF_29))
+              (portRef CD (instanceRef FF_28))
+              (portRef CD (instanceRef FF_27))
+              (portRef CD (instanceRef FF_26))
+              (portRef CD (instanceRef FF_25))
+              (portRef CD (instanceRef FF_16))
+              (portRef CD (instanceRef FF_15))
+              (portRef CD (instanceRef FF_14))
+              (portRef CD (instanceRef FF_13))
+              (portRef CD (instanceRef FF_12))
+              (portRef CD (instanceRef FF_11))
+              (portRef CD (instanceRef FF_10))
+              (portRef CD (instanceRef FF_9))
+              (portRef CD (instanceRef FF_8))
+              (portRef CD (instanceRef FF_7))
+              (portRef CD (instanceRef FF_6))
+              (portRef CD (instanceRef FF_5))
+              (portRef CD (instanceRef FF_4))
+              (portRef CD (instanceRef FF_3))
+              (portRef CD (instanceRef FF_2))
+              (portRef CD (instanceRef FF_1))
+              (portRef CD (instanceRef FF_0))))
+          (net rden
+            (joined
+              (portRef RdEn)
+              (portRef A (instanceRef AND2_t4))))
+          (net wren
+            (joined
+              (portRef WrEn)
+              (portRef A (instanceRef AND2_t5))))
+          (net clk
+            (joined
+              (portRef Clock)
+              (portRef CLKB (instanceRef pdp_ram_0_0_63))
+              (portRef CLKA (instanceRef pdp_ram_0_0_63))
+              (portRef CLKB (instanceRef pdp_ram_0_1_62))
+              (portRef CLKA (instanceRef pdp_ram_0_1_62))
+              (portRef CLKB (instanceRef pdp_ram_0_2_61))
+              (portRef CLKA (instanceRef pdp_ram_0_2_61))
+              (portRef CLKB (instanceRef pdp_ram_0_3_60))
+              (portRef CLKA (instanceRef pdp_ram_0_3_60))
+              (portRef CLKB (instanceRef pdp_ram_1_0_59))
+              (portRef CLKA (instanceRef pdp_ram_1_0_59))
+              (portRef CLKB (instanceRef pdp_ram_1_1_58))
+              (portRef CLKA (instanceRef pdp_ram_1_1_58))
+              (portRef CLKB (instanceRef pdp_ram_1_2_57))
+              (portRef CLKA (instanceRef pdp_ram_1_2_57))
+              (portRef CLKB (instanceRef pdp_ram_1_3_56))
+              (portRef CLKA (instanceRef pdp_ram_1_3_56))
+              (portRef CLKB (instanceRef pdp_ram_2_0_55))
+              (portRef CLKA (instanceRef pdp_ram_2_0_55))
+              (portRef CLKB (instanceRef pdp_ram_2_1_54))
+              (portRef CLKA (instanceRef pdp_ram_2_1_54))
+              (portRef CLKB (instanceRef pdp_ram_2_2_53))
+              (portRef CLKA (instanceRef pdp_ram_2_2_53))
+              (portRef CLKB (instanceRef pdp_ram_2_3_52))
+              (portRef CLKA (instanceRef pdp_ram_2_3_52))
+              (portRef CLKB (instanceRef pdp_ram_3_0_51))
+              (portRef CLKA (instanceRef pdp_ram_3_0_51))
+              (portRef CLKB (instanceRef pdp_ram_3_1_50))
+              (portRef CLKA (instanceRef pdp_ram_3_1_50))
+              (portRef CLKB (instanceRef pdp_ram_3_2_49))
+              (portRef CLKA (instanceRef pdp_ram_3_2_49))
+              (portRef CLKB (instanceRef pdp_ram_3_3_48))
+              (portRef CLKA (instanceRef pdp_ram_3_3_48))
+              (portRef CLKB (instanceRef pdp_ram_4_0_47))
+              (portRef CLKA (instanceRef pdp_ram_4_0_47))
+              (portRef CLKB (instanceRef pdp_ram_4_1_46))
+              (portRef CLKA (instanceRef pdp_ram_4_1_46))
+              (portRef CLKB (instanceRef pdp_ram_4_2_45))
+              (portRef CLKA (instanceRef pdp_ram_4_2_45))
+              (portRef CLKB (instanceRef pdp_ram_4_3_44))
+              (portRef CLKA (instanceRef pdp_ram_4_3_44))
+              (portRef CLKB (instanceRef pdp_ram_5_0_43))
+              (portRef CLKA (instanceRef pdp_ram_5_0_43))
+              (portRef CLKB (instanceRef pdp_ram_5_1_42))
+              (portRef CLKA (instanceRef pdp_ram_5_1_42))
+              (portRef CLKB (instanceRef pdp_ram_5_2_41))
+              (portRef CLKA (instanceRef pdp_ram_5_2_41))
+              (portRef CLKB (instanceRef pdp_ram_5_3_40))
+              (portRef CLKA (instanceRef pdp_ram_5_3_40))
+              (portRef CLKB (instanceRef pdp_ram_6_0_39))
+              (portRef CLKA (instanceRef pdp_ram_6_0_39))
+              (portRef CLKB (instanceRef pdp_ram_6_1_38))
+              (portRef CLKA (instanceRef pdp_ram_6_1_38))
+              (portRef CLKB (instanceRef pdp_ram_6_2_37))
+              (portRef CLKA (instanceRef pdp_ram_6_2_37))
+              (portRef CLKB (instanceRef pdp_ram_6_3_36))
+              (portRef CLKA (instanceRef pdp_ram_6_3_36))
+              (portRef CLKB (instanceRef pdp_ram_7_0_35))
+              (portRef CLKA (instanceRef pdp_ram_7_0_35))
+              (portRef CLKB (instanceRef pdp_ram_7_1_34))
+              (portRef CLKA (instanceRef pdp_ram_7_1_34))
+              (portRef CLKB (instanceRef pdp_ram_7_2_33))
+              (portRef CLKA (instanceRef pdp_ram_7_2_33))
+              (portRef CLKB (instanceRef pdp_ram_7_3_32))
+              (portRef CLKA (instanceRef pdp_ram_7_3_32))
+              (portRef CLKB (instanceRef pdp_ram_8_0_31))
+              (portRef CLKA (instanceRef pdp_ram_8_0_31))
+              (portRef CLKB (instanceRef pdp_ram_8_1_30))
+              (portRef CLKA (instanceRef pdp_ram_8_1_30))
+              (portRef CLKB (instanceRef pdp_ram_8_2_29))
+              (portRef CLKA (instanceRef pdp_ram_8_2_29))
+              (portRef CLKB (instanceRef pdp_ram_8_3_28))
+              (portRef CLKA (instanceRef pdp_ram_8_3_28))
+              (portRef CLKB (instanceRef pdp_ram_9_0_27))
+              (portRef CLKA (instanceRef pdp_ram_9_0_27))
+              (portRef CLKB (instanceRef pdp_ram_9_1_26))
+              (portRef CLKA (instanceRef pdp_ram_9_1_26))
+              (portRef CLKB (instanceRef pdp_ram_9_2_25))
+              (portRef CLKA (instanceRef pdp_ram_9_2_25))
+              (portRef CLKB (instanceRef pdp_ram_9_3_24))
+              (portRef CLKA (instanceRef pdp_ram_9_3_24))
+              (portRef CLKB (instanceRef pdp_ram_10_0_23))
+              (portRef CLKA (instanceRef pdp_ram_10_0_23))
+              (portRef CLKB (instanceRef pdp_ram_10_1_22))
+              (portRef CLKA (instanceRef pdp_ram_10_1_22))
+              (portRef CLKB (instanceRef pdp_ram_10_2_21))
+              (portRef CLKA (instanceRef pdp_ram_10_2_21))
+              (portRef CLKB (instanceRef pdp_ram_10_3_20))
+              (portRef CLKA (instanceRef pdp_ram_10_3_20))
+              (portRef CLKB (instanceRef pdp_ram_11_0_19))
+              (portRef CLKA (instanceRef pdp_ram_11_0_19))
+              (portRef CLKB (instanceRef pdp_ram_11_1_18))
+              (portRef CLKA (instanceRef pdp_ram_11_1_18))
+              (portRef CLKB (instanceRef pdp_ram_11_2_17))
+              (portRef CLKA (instanceRef pdp_ram_11_2_17))
+              (portRef CLKB (instanceRef pdp_ram_11_3_16))
+              (portRef CLKA (instanceRef pdp_ram_11_3_16))
+              (portRef CLKB (instanceRef pdp_ram_12_0_15))
+              (portRef CLKA (instanceRef pdp_ram_12_0_15))
+              (portRef CLKB (instanceRef pdp_ram_12_1_14))
+              (portRef CLKA (instanceRef pdp_ram_12_1_14))
+              (portRef CLKB (instanceRef pdp_ram_12_2_13))
+              (portRef CLKA (instanceRef pdp_ram_12_2_13))
+              (portRef CLKB (instanceRef pdp_ram_12_3_12))
+              (portRef CLKA (instanceRef pdp_ram_12_3_12))
+              (portRef CLKB (instanceRef pdp_ram_13_0_11))
+              (portRef CLKA (instanceRef pdp_ram_13_0_11))
+              (portRef CLKB (instanceRef pdp_ram_13_1_10))
+              (portRef CLKA (instanceRef pdp_ram_13_1_10))
+              (portRef CLKB (instanceRef pdp_ram_13_2_9))
+              (portRef CLKA (instanceRef pdp_ram_13_2_9))
+              (portRef CLKB (instanceRef pdp_ram_13_3_8))
+              (portRef CLKA (instanceRef pdp_ram_13_3_8))
+              (portRef CLKB (instanceRef pdp_ram_14_0_7))
+              (portRef CLKA (instanceRef pdp_ram_14_0_7))
+              (portRef CLKB (instanceRef pdp_ram_14_1_6))
+              (portRef CLKA (instanceRef pdp_ram_14_1_6))
+              (portRef CLKB (instanceRef pdp_ram_14_2_5))
+              (portRef CLKA (instanceRef pdp_ram_14_2_5))
+              (portRef CLKB (instanceRef pdp_ram_14_3_4))
+              (portRef CLKA (instanceRef pdp_ram_14_3_4))
+              (portRef CLKB (instanceRef pdp_ram_15_0_3))
+              (portRef CLKA (instanceRef pdp_ram_15_0_3))
+              (portRef CLKB (instanceRef pdp_ram_15_1_2))
+              (portRef CLKA (instanceRef pdp_ram_15_1_2))
+              (portRef CLKB (instanceRef pdp_ram_15_2_1))
+              (portRef CLKA (instanceRef pdp_ram_15_2_1))
+              (portRef CLKB (instanceRef pdp_ram_15_3_0))
+              (portRef CLKA (instanceRef pdp_ram_15_3_0))
+              (portRef CK (instanceRef FF_106))
+              (portRef CK (instanceRef FF_105))
+              (portRef CK (instanceRef FF_104))
+              (portRef CK (instanceRef FF_103))
+              (portRef CK (instanceRef FF_102))
+              (portRef CK (instanceRef FF_101))
+              (portRef CK (instanceRef FF_100))
+              (portRef CK (instanceRef FF_99))
+              (portRef CK (instanceRef FF_98))
+              (portRef CK (instanceRef FF_97))
+              (portRef CK (instanceRef FF_96))
+              (portRef CK (instanceRef FF_95))
+              (portRef CK (instanceRef FF_94))
+              (portRef CK (instanceRef FF_93))
+              (portRef CK (instanceRef FF_92))
+              (portRef CK (instanceRef FF_91))
+              (portRef CK (instanceRef FF_90))
+              (portRef CK (instanceRef FF_89))
+              (portRef CK (instanceRef FF_88))
+              (portRef CK (instanceRef FF_87))
+              (portRef CK (instanceRef FF_86))
+              (portRef CK (instanceRef FF_85))
+              (portRef CK (instanceRef FF_84))
+              (portRef CK (instanceRef FF_83))
+              (portRef CK (instanceRef FF_82))
+              (portRef CK (instanceRef FF_81))
+              (portRef CK (instanceRef FF_80))
+              (portRef CK (instanceRef FF_79))
+              (portRef CK (instanceRef FF_78))
+              (portRef CK (instanceRef FF_77))
+              (portRef CK (instanceRef FF_76))
+              (portRef CK (instanceRef FF_75))
+              (portRef CK (instanceRef FF_74))
+              (portRef CK (instanceRef FF_73))
+              (portRef CK (instanceRef FF_72))
+              (portRef CK (instanceRef FF_71))
+              (portRef CK (instanceRef FF_70))
+              (portRef CK (instanceRef FF_69))
+              (portRef CK (instanceRef FF_68))
+              (portRef CK (instanceRef FF_67))
+              (portRef CK (instanceRef FF_66))
+              (portRef CK (instanceRef FF_65))
+              (portRef CK (instanceRef FF_64))
+              (portRef CK (instanceRef FF_63))
+              (portRef CK (instanceRef FF_62))
+              (portRef CK (instanceRef FF_61))
+              (portRef CK (instanceRef FF_60))
+              (portRef CK (instanceRef FF_59))
+              (portRef CK (instanceRef FF_58))
+              (portRef CK (instanceRef FF_57))
+              (portRef CK (instanceRef FF_56))
+              (portRef CK (instanceRef FF_55))
+              (portRef CK (instanceRef FF_54))
+              (portRef CK (instanceRef FF_53))
+              (portRef CK (instanceRef FF_52))
+              (portRef CK (instanceRef FF_51))
+              (portRef CK (instanceRef FF_50))
+              (portRef CK (instanceRef FF_49))
+              (portRef CK (instanceRef FF_48))
+              (portRef CK (instanceRef FF_47))
+              (portRef CK (instanceRef FF_46))
+              (portRef CK (instanceRef FF_45))
+              (portRef CK (instanceRef FF_44))
+              (portRef CK (instanceRef FF_43))
+              (portRef CK (instanceRef FF_42))
+              (portRef CK (instanceRef FF_41))
+              (portRef CK (instanceRef FF_40))
+              (portRef CK (instanceRef FF_39))
+              (portRef CK (instanceRef FF_38))
+              (portRef CK (instanceRef FF_37))
+              (portRef CK (instanceRef FF_36))
+              (portRef CK (instanceRef FF_35))
+              (portRef CK (instanceRef FF_34))
+              (portRef CK (instanceRef FF_33))
+              (portRef CK (instanceRef FF_32))
+              (portRef CK (instanceRef FF_31))
+              (portRef CK (instanceRef FF_30))
+              (portRef CK (instanceRef FF_29))
+              (portRef CK (instanceRef FF_28))
+              (portRef CK (instanceRef FF_27))
+              (portRef CK (instanceRef FF_26))
+              (portRef CK (instanceRef FF_25))
+              (portRef CK (instanceRef FF_24))
+              (portRef CK (instanceRef FF_23))
+              (portRef CK (instanceRef FF_22))
+              (portRef CK (instanceRef FF_21))
+              (portRef CK (instanceRef FF_20))
+              (portRef CK (instanceRef FF_19))
+              (portRef CK (instanceRef FF_18))
+              (portRef CK (instanceRef FF_17))
+              (portRef CK (instanceRef FF_16))
+              (portRef CK (instanceRef FF_15))
+              (portRef CK (instanceRef FF_14))
+              (portRef CK (instanceRef FF_13))
+              (portRef CK (instanceRef FF_12))
+              (portRef CK (instanceRef FF_11))
+              (portRef CK (instanceRef FF_10))
+              (portRef CK (instanceRef FF_9))
+              (portRef CK (instanceRef FF_8))
+              (portRef CK (instanceRef FF_7))
+              (portRef CK (instanceRef FF_6))
+              (portRef CK (instanceRef FF_5))
+              (portRef CK (instanceRef FF_4))
+              (portRef CK (instanceRef FF_3))
+              (portRef CK (instanceRef FF_2))
+              (portRef CK (instanceRef FF_1))
+              (portRef CK (instanceRef FF_0))))
+          (net datain35
+            (joined
+              (portRef (member Data 0))
+              (portRef DIA8 (instanceRef pdp_ram_0_3_60))
+              (portRef DIA8 (instanceRef pdp_ram_1_3_56))
+              (portRef DIA8 (instanceRef pdp_ram_2_3_52))
+              (portRef DIA8 (instanceRef pdp_ram_3_3_48))
+              (portRef DIA8 (instanceRef pdp_ram_4_3_44))
+              (portRef DIA8 (instanceRef pdp_ram_5_3_40))
+              (portRef DIA8 (instanceRef pdp_ram_6_3_36))
+              (portRef DIA8 (instanceRef pdp_ram_7_3_32))
+              (portRef DIA8 (instanceRef pdp_ram_8_3_28))
+              (portRef DIA8 (instanceRef pdp_ram_9_3_24))
+              (portRef DIA8 (instanceRef pdp_ram_10_3_20))
+              (portRef DIA8 (instanceRef pdp_ram_11_3_16))
+              (portRef DIA8 (instanceRef pdp_ram_12_3_12))
+              (portRef DIA8 (instanceRef pdp_ram_13_3_8))
+              (portRef DIA8 (instanceRef pdp_ram_14_3_4))
+              (portRef DIA8 (instanceRef pdp_ram_15_3_0))))
+          (net datain34
+            (joined
+              (portRef (member Data 1))
+              (portRef DIA7 (instanceRef pdp_ram_0_3_60))
+              (portRef DIA7 (instanceRef pdp_ram_1_3_56))
+              (portRef DIA7 (instanceRef pdp_ram_2_3_52))
+              (portRef DIA7 (instanceRef pdp_ram_3_3_48))
+              (portRef DIA7 (instanceRef pdp_ram_4_3_44))
+              (portRef DIA7 (instanceRef pdp_ram_5_3_40))
+              (portRef DIA7 (instanceRef pdp_ram_6_3_36))
+              (portRef DIA7 (instanceRef pdp_ram_7_3_32))
+              (portRef DIA7 (instanceRef pdp_ram_8_3_28))
+              (portRef DIA7 (instanceRef pdp_ram_9_3_24))
+              (portRef DIA7 (instanceRef pdp_ram_10_3_20))
+              (portRef DIA7 (instanceRef pdp_ram_11_3_16))
+              (portRef DIA7 (instanceRef pdp_ram_12_3_12))
+              (portRef DIA7 (instanceRef pdp_ram_13_3_8))
+              (portRef DIA7 (instanceRef pdp_ram_14_3_4))
+              (portRef DIA7 (instanceRef pdp_ram_15_3_0))))
+          (net datain33
+            (joined
+              (portRef (member Data 2))
+              (portRef DIA6 (instanceRef pdp_ram_0_3_60))
+              (portRef DIA6 (instanceRef pdp_ram_1_3_56))
+              (portRef DIA6 (instanceRef pdp_ram_2_3_52))
+              (portRef DIA6 (instanceRef pdp_ram_3_3_48))
+              (portRef DIA6 (instanceRef pdp_ram_4_3_44))
+              (portRef DIA6 (instanceRef pdp_ram_5_3_40))
+              (portRef DIA6 (instanceRef pdp_ram_6_3_36))
+              (portRef DIA6 (instanceRef pdp_ram_7_3_32))
+              (portRef DIA6 (instanceRef pdp_ram_8_3_28))
+              (portRef DIA6 (instanceRef pdp_ram_9_3_24))
+              (portRef DIA6 (instanceRef pdp_ram_10_3_20))
+              (portRef DIA6 (instanceRef pdp_ram_11_3_16))
+              (portRef DIA6 (instanceRef pdp_ram_12_3_12))
+              (portRef DIA6 (instanceRef pdp_ram_13_3_8))
+              (portRef DIA6 (instanceRef pdp_ram_14_3_4))
+              (portRef DIA6 (instanceRef pdp_ram_15_3_0))))
+          (net datain32
+            (joined
+              (portRef (member Data 3))
+              (portRef DIA5 (instanceRef pdp_ram_0_3_60))
+              (portRef DIA5 (instanceRef pdp_ram_1_3_56))
+              (portRef DIA5 (instanceRef pdp_ram_2_3_52))
+              (portRef DIA5 (instanceRef pdp_ram_3_3_48))
+              (portRef DIA5 (instanceRef pdp_ram_4_3_44))
+              (portRef DIA5 (instanceRef pdp_ram_5_3_40))
+              (portRef DIA5 (instanceRef pdp_ram_6_3_36))
+              (portRef DIA5 (instanceRef pdp_ram_7_3_32))
+              (portRef DIA5 (instanceRef pdp_ram_8_3_28))
+              (portRef DIA5 (instanceRef pdp_ram_9_3_24))
+              (portRef DIA5 (instanceRef pdp_ram_10_3_20))
+              (portRef DIA5 (instanceRef pdp_ram_11_3_16))
+              (portRef DIA5 (instanceRef pdp_ram_12_3_12))
+              (portRef DIA5 (instanceRef pdp_ram_13_3_8))
+              (portRef DIA5 (instanceRef pdp_ram_14_3_4))
+              (portRef DIA5 (instanceRef pdp_ram_15_3_0))))
+          (net datain31
+            (joined
+              (portRef (member Data 4))
+              (portRef DIA4 (instanceRef pdp_ram_0_3_60))
+              (portRef DIA4 (instanceRef pdp_ram_1_3_56))
+              (portRef DIA4 (instanceRef pdp_ram_2_3_52))
+              (portRef DIA4 (instanceRef pdp_ram_3_3_48))
+              (portRef DIA4 (instanceRef pdp_ram_4_3_44))
+              (portRef DIA4 (instanceRef pdp_ram_5_3_40))
+              (portRef DIA4 (instanceRef pdp_ram_6_3_36))
+              (portRef DIA4 (instanceRef pdp_ram_7_3_32))
+              (portRef DIA4 (instanceRef pdp_ram_8_3_28))
+              (portRef DIA4 (instanceRef pdp_ram_9_3_24))
+              (portRef DIA4 (instanceRef pdp_ram_10_3_20))
+              (portRef DIA4 (instanceRef pdp_ram_11_3_16))
+              (portRef DIA4 (instanceRef pdp_ram_12_3_12))
+              (portRef DIA4 (instanceRef pdp_ram_13_3_8))
+              (portRef DIA4 (instanceRef pdp_ram_14_3_4))
+              (portRef DIA4 (instanceRef pdp_ram_15_3_0))))
+          (net datain30
+            (joined
+              (portRef (member Data 5))
+              (portRef DIA3 (instanceRef pdp_ram_0_3_60))
+              (portRef DIA3 (instanceRef pdp_ram_1_3_56))
+              (portRef DIA3 (instanceRef pdp_ram_2_3_52))
+              (portRef DIA3 (instanceRef pdp_ram_3_3_48))
+              (portRef DIA3 (instanceRef pdp_ram_4_3_44))
+              (portRef DIA3 (instanceRef pdp_ram_5_3_40))
+              (portRef DIA3 (instanceRef pdp_ram_6_3_36))
+              (portRef DIA3 (instanceRef pdp_ram_7_3_32))
+              (portRef DIA3 (instanceRef pdp_ram_8_3_28))
+              (portRef DIA3 (instanceRef pdp_ram_9_3_24))
+              (portRef DIA3 (instanceRef pdp_ram_10_3_20))
+              (portRef DIA3 (instanceRef pdp_ram_11_3_16))
+              (portRef DIA3 (instanceRef pdp_ram_12_3_12))
+              (portRef DIA3 (instanceRef pdp_ram_13_3_8))
+              (portRef DIA3 (instanceRef pdp_ram_14_3_4))
+              (portRef DIA3 (instanceRef pdp_ram_15_3_0))))
+          (net datain29
+            (joined
+              (portRef (member Data 6))
+              (portRef DIA2 (instanceRef pdp_ram_0_3_60))
+              (portRef DIA2 (instanceRef pdp_ram_1_3_56))
+              (portRef DIA2 (instanceRef pdp_ram_2_3_52))
+              (portRef DIA2 (instanceRef pdp_ram_3_3_48))
+              (portRef DIA2 (instanceRef pdp_ram_4_3_44))
+              (portRef DIA2 (instanceRef pdp_ram_5_3_40))
+              (portRef DIA2 (instanceRef pdp_ram_6_3_36))
+              (portRef DIA2 (instanceRef pdp_ram_7_3_32))
+              (portRef DIA2 (instanceRef pdp_ram_8_3_28))
+              (portRef DIA2 (instanceRef pdp_ram_9_3_24))
+              (portRef DIA2 (instanceRef pdp_ram_10_3_20))
+              (portRef DIA2 (instanceRef pdp_ram_11_3_16))
+              (portRef DIA2 (instanceRef pdp_ram_12_3_12))
+              (portRef DIA2 (instanceRef pdp_ram_13_3_8))
+              (portRef DIA2 (instanceRef pdp_ram_14_3_4))
+              (portRef DIA2 (instanceRef pdp_ram_15_3_0))))
+          (net datain28
+            (joined
+              (portRef (member Data 7))
+              (portRef DIA1 (instanceRef pdp_ram_0_3_60))
+              (portRef DIA1 (instanceRef pdp_ram_1_3_56))
+              (portRef DIA1 (instanceRef pdp_ram_2_3_52))
+              (portRef DIA1 (instanceRef pdp_ram_3_3_48))
+              (portRef DIA1 (instanceRef pdp_ram_4_3_44))
+              (portRef DIA1 (instanceRef pdp_ram_5_3_40))
+              (portRef DIA1 (instanceRef pdp_ram_6_3_36))
+              (portRef DIA1 (instanceRef pdp_ram_7_3_32))
+              (portRef DIA1 (instanceRef pdp_ram_8_3_28))
+              (portRef DIA1 (instanceRef pdp_ram_9_3_24))
+              (portRef DIA1 (instanceRef pdp_ram_10_3_20))
+              (portRef DIA1 (instanceRef pdp_ram_11_3_16))
+              (portRef DIA1 (instanceRef pdp_ram_12_3_12))
+              (portRef DIA1 (instanceRef pdp_ram_13_3_8))
+              (portRef DIA1 (instanceRef pdp_ram_14_3_4))
+              (portRef DIA1 (instanceRef pdp_ram_15_3_0))))
+          (net datain27
+            (joined
+              (portRef (member Data 8))
+              (portRef DIA0 (instanceRef pdp_ram_0_3_60))
+              (portRef DIA0 (instanceRef pdp_ram_1_3_56))
+              (portRef DIA0 (instanceRef pdp_ram_2_3_52))
+              (portRef DIA0 (instanceRef pdp_ram_3_3_48))
+              (portRef DIA0 (instanceRef pdp_ram_4_3_44))
+              (portRef DIA0 (instanceRef pdp_ram_5_3_40))
+              (portRef DIA0 (instanceRef pdp_ram_6_3_36))
+              (portRef DIA0 (instanceRef pdp_ram_7_3_32))
+              (portRef DIA0 (instanceRef pdp_ram_8_3_28))
+              (portRef DIA0 (instanceRef pdp_ram_9_3_24))
+              (portRef DIA0 (instanceRef pdp_ram_10_3_20))
+              (portRef DIA0 (instanceRef pdp_ram_11_3_16))
+              (portRef DIA0 (instanceRef pdp_ram_12_3_12))
+              (portRef DIA0 (instanceRef pdp_ram_13_3_8))
+              (portRef DIA0 (instanceRef pdp_ram_14_3_4))
+              (portRef DIA0 (instanceRef pdp_ram_15_3_0))))
+          (net datain26
+            (joined
+              (portRef (member Data 9))
+              (portRef DIA8 (instanceRef pdp_ram_0_2_61))
+              (portRef DIA8 (instanceRef pdp_ram_1_2_57))
+              (portRef DIA8 (instanceRef pdp_ram_2_2_53))
+              (portRef DIA8 (instanceRef pdp_ram_3_2_49))
+              (portRef DIA8 (instanceRef pdp_ram_4_2_45))
+              (portRef DIA8 (instanceRef pdp_ram_5_2_41))
+              (portRef DIA8 (instanceRef pdp_ram_6_2_37))
+              (portRef DIA8 (instanceRef pdp_ram_7_2_33))
+              (portRef DIA8 (instanceRef pdp_ram_8_2_29))
+              (portRef DIA8 (instanceRef pdp_ram_9_2_25))
+              (portRef DIA8 (instanceRef pdp_ram_10_2_21))
+              (portRef DIA8 (instanceRef pdp_ram_11_2_17))
+              (portRef DIA8 (instanceRef pdp_ram_12_2_13))
+              (portRef DIA8 (instanceRef pdp_ram_13_2_9))
+              (portRef DIA8 (instanceRef pdp_ram_14_2_5))
+              (portRef DIA8 (instanceRef pdp_ram_15_2_1))))
+          (net datain25
+            (joined
+              (portRef (member Data 10))
+              (portRef DIA7 (instanceRef pdp_ram_0_2_61))
+              (portRef DIA7 (instanceRef pdp_ram_1_2_57))
+              (portRef DIA7 (instanceRef pdp_ram_2_2_53))
+              (portRef DIA7 (instanceRef pdp_ram_3_2_49))
+              (portRef DIA7 (instanceRef pdp_ram_4_2_45))
+              (portRef DIA7 (instanceRef pdp_ram_5_2_41))
+              (portRef DIA7 (instanceRef pdp_ram_6_2_37))
+              (portRef DIA7 (instanceRef pdp_ram_7_2_33))
+              (portRef DIA7 (instanceRef pdp_ram_8_2_29))
+              (portRef DIA7 (instanceRef pdp_ram_9_2_25))
+              (portRef DIA7 (instanceRef pdp_ram_10_2_21))
+              (portRef DIA7 (instanceRef pdp_ram_11_2_17))
+              (portRef DIA7 (instanceRef pdp_ram_12_2_13))
+              (portRef DIA7 (instanceRef pdp_ram_13_2_9))
+              (portRef DIA7 (instanceRef pdp_ram_14_2_5))
+              (portRef DIA7 (instanceRef pdp_ram_15_2_1))))
+          (net datain24
+            (joined
+              (portRef (member Data 11))
+              (portRef DIA6 (instanceRef pdp_ram_0_2_61))
+              (portRef DIA6 (instanceRef pdp_ram_1_2_57))
+              (portRef DIA6 (instanceRef pdp_ram_2_2_53))
+              (portRef DIA6 (instanceRef pdp_ram_3_2_49))
+              (portRef DIA6 (instanceRef pdp_ram_4_2_45))
+              (portRef DIA6 (instanceRef pdp_ram_5_2_41))
+              (portRef DIA6 (instanceRef pdp_ram_6_2_37))
+              (portRef DIA6 (instanceRef pdp_ram_7_2_33))
+              (portRef DIA6 (instanceRef pdp_ram_8_2_29))
+              (portRef DIA6 (instanceRef pdp_ram_9_2_25))
+              (portRef DIA6 (instanceRef pdp_ram_10_2_21))
+              (portRef DIA6 (instanceRef pdp_ram_11_2_17))
+              (portRef DIA6 (instanceRef pdp_ram_12_2_13))
+              (portRef DIA6 (instanceRef pdp_ram_13_2_9))
+              (portRef DIA6 (instanceRef pdp_ram_14_2_5))
+              (portRef DIA6 (instanceRef pdp_ram_15_2_1))))
+          (net datain23
+            (joined
+              (portRef (member Data 12))
+              (portRef DIA5 (instanceRef pdp_ram_0_2_61))
+              (portRef DIA5 (instanceRef pdp_ram_1_2_57))
+              (portRef DIA5 (instanceRef pdp_ram_2_2_53))
+              (portRef DIA5 (instanceRef pdp_ram_3_2_49))
+              (portRef DIA5 (instanceRef pdp_ram_4_2_45))
+              (portRef DIA5 (instanceRef pdp_ram_5_2_41))
+              (portRef DIA5 (instanceRef pdp_ram_6_2_37))
+              (portRef DIA5 (instanceRef pdp_ram_7_2_33))
+              (portRef DIA5 (instanceRef pdp_ram_8_2_29))
+              (portRef DIA5 (instanceRef pdp_ram_9_2_25))
+              (portRef DIA5 (instanceRef pdp_ram_10_2_21))
+              (portRef DIA5 (instanceRef pdp_ram_11_2_17))
+              (portRef DIA5 (instanceRef pdp_ram_12_2_13))
+              (portRef DIA5 (instanceRef pdp_ram_13_2_9))
+              (portRef DIA5 (instanceRef pdp_ram_14_2_5))
+              (portRef DIA5 (instanceRef pdp_ram_15_2_1))))
+          (net datain22
+            (joined
+              (portRef (member Data 13))
+              (portRef DIA4 (instanceRef pdp_ram_0_2_61))
+              (portRef DIA4 (instanceRef pdp_ram_1_2_57))
+              (portRef DIA4 (instanceRef pdp_ram_2_2_53))
+              (portRef DIA4 (instanceRef pdp_ram_3_2_49))
+              (portRef DIA4 (instanceRef pdp_ram_4_2_45))
+              (portRef DIA4 (instanceRef pdp_ram_5_2_41))
+              (portRef DIA4 (instanceRef pdp_ram_6_2_37))
+              (portRef DIA4 (instanceRef pdp_ram_7_2_33))
+              (portRef DIA4 (instanceRef pdp_ram_8_2_29))
+              (portRef DIA4 (instanceRef pdp_ram_9_2_25))
+              (portRef DIA4 (instanceRef pdp_ram_10_2_21))
+              (portRef DIA4 (instanceRef pdp_ram_11_2_17))
+              (portRef DIA4 (instanceRef pdp_ram_12_2_13))
+              (portRef DIA4 (instanceRef pdp_ram_13_2_9))
+              (portRef DIA4 (instanceRef pdp_ram_14_2_5))
+              (portRef DIA4 (instanceRef pdp_ram_15_2_1))))
+          (net datain21
+            (joined
+              (portRef (member Data 14))
+              (portRef DIA3 (instanceRef pdp_ram_0_2_61))
+              (portRef DIA3 (instanceRef pdp_ram_1_2_57))
+              (portRef DIA3 (instanceRef pdp_ram_2_2_53))
+              (portRef DIA3 (instanceRef pdp_ram_3_2_49))
+              (portRef DIA3 (instanceRef pdp_ram_4_2_45))
+              (portRef DIA3 (instanceRef pdp_ram_5_2_41))
+              (portRef DIA3 (instanceRef pdp_ram_6_2_37))
+              (portRef DIA3 (instanceRef pdp_ram_7_2_33))
+              (portRef DIA3 (instanceRef pdp_ram_8_2_29))
+              (portRef DIA3 (instanceRef pdp_ram_9_2_25))
+              (portRef DIA3 (instanceRef pdp_ram_10_2_21))
+              (portRef DIA3 (instanceRef pdp_ram_11_2_17))
+              (portRef DIA3 (instanceRef pdp_ram_12_2_13))
+              (portRef DIA3 (instanceRef pdp_ram_13_2_9))
+              (portRef DIA3 (instanceRef pdp_ram_14_2_5))
+              (portRef DIA3 (instanceRef pdp_ram_15_2_1))))
+          (net datain20
+            (joined
+              (portRef (member Data 15))
+              (portRef DIA2 (instanceRef pdp_ram_0_2_61))
+              (portRef DIA2 (instanceRef pdp_ram_1_2_57))
+              (portRef DIA2 (instanceRef pdp_ram_2_2_53))
+              (portRef DIA2 (instanceRef pdp_ram_3_2_49))
+              (portRef DIA2 (instanceRef pdp_ram_4_2_45))
+              (portRef DIA2 (instanceRef pdp_ram_5_2_41))
+              (portRef DIA2 (instanceRef pdp_ram_6_2_37))
+              (portRef DIA2 (instanceRef pdp_ram_7_2_33))
+              (portRef DIA2 (instanceRef pdp_ram_8_2_29))
+              (portRef DIA2 (instanceRef pdp_ram_9_2_25))
+              (portRef DIA2 (instanceRef pdp_ram_10_2_21))
+              (portRef DIA2 (instanceRef pdp_ram_11_2_17))
+              (portRef DIA2 (instanceRef pdp_ram_12_2_13))
+              (portRef DIA2 (instanceRef pdp_ram_13_2_9))
+              (portRef DIA2 (instanceRef pdp_ram_14_2_5))
+              (portRef DIA2 (instanceRef pdp_ram_15_2_1))))
+          (net datain19
+            (joined
+              (portRef (member Data 16))
+              (portRef DIA1 (instanceRef pdp_ram_0_2_61))
+              (portRef DIA1 (instanceRef pdp_ram_1_2_57))
+              (portRef DIA1 (instanceRef pdp_ram_2_2_53))
+              (portRef DIA1 (instanceRef pdp_ram_3_2_49))
+              (portRef DIA1 (instanceRef pdp_ram_4_2_45))
+              (portRef DIA1 (instanceRef pdp_ram_5_2_41))
+              (portRef DIA1 (instanceRef pdp_ram_6_2_37))
+              (portRef DIA1 (instanceRef pdp_ram_7_2_33))
+              (portRef DIA1 (instanceRef pdp_ram_8_2_29))
+              (portRef DIA1 (instanceRef pdp_ram_9_2_25))
+              (portRef DIA1 (instanceRef pdp_ram_10_2_21))
+              (portRef DIA1 (instanceRef pdp_ram_11_2_17))
+              (portRef DIA1 (instanceRef pdp_ram_12_2_13))
+              (portRef DIA1 (instanceRef pdp_ram_13_2_9))
+              (portRef DIA1 (instanceRef pdp_ram_14_2_5))
+              (portRef DIA1 (instanceRef pdp_ram_15_2_1))))
+          (net datain18
+            (joined
+              (portRef (member Data 17))
+              (portRef DIA0 (instanceRef pdp_ram_0_2_61))
+              (portRef DIA0 (instanceRef pdp_ram_1_2_57))
+              (portRef DIA0 (instanceRef pdp_ram_2_2_53))
+              (portRef DIA0 (instanceRef pdp_ram_3_2_49))
+              (portRef DIA0 (instanceRef pdp_ram_4_2_45))
+              (portRef DIA0 (instanceRef pdp_ram_5_2_41))
+              (portRef DIA0 (instanceRef pdp_ram_6_2_37))
+              (portRef DIA0 (instanceRef pdp_ram_7_2_33))
+              (portRef DIA0 (instanceRef pdp_ram_8_2_29))
+              (portRef DIA0 (instanceRef pdp_ram_9_2_25))
+              (portRef DIA0 (instanceRef pdp_ram_10_2_21))
+              (portRef DIA0 (instanceRef pdp_ram_11_2_17))
+              (portRef DIA0 (instanceRef pdp_ram_12_2_13))
+              (portRef DIA0 (instanceRef pdp_ram_13_2_9))
+              (portRef DIA0 (instanceRef pdp_ram_14_2_5))
+              (portRef DIA0 (instanceRef pdp_ram_15_2_1))))
+          (net datain17
+            (joined
+              (portRef (member Data 18))
+              (portRef DIA8 (instanceRef pdp_ram_0_1_62))
+              (portRef DIA8 (instanceRef pdp_ram_1_1_58))
+              (portRef DIA8 (instanceRef pdp_ram_2_1_54))
+              (portRef DIA8 (instanceRef pdp_ram_3_1_50))
+              (portRef DIA8 (instanceRef pdp_ram_4_1_46))
+              (portRef DIA8 (instanceRef pdp_ram_5_1_42))
+              (portRef DIA8 (instanceRef pdp_ram_6_1_38))
+              (portRef DIA8 (instanceRef pdp_ram_7_1_34))
+              (portRef DIA8 (instanceRef pdp_ram_8_1_30))
+              (portRef DIA8 (instanceRef pdp_ram_9_1_26))
+              (portRef DIA8 (instanceRef pdp_ram_10_1_22))
+              (portRef DIA8 (instanceRef pdp_ram_11_1_18))
+              (portRef DIA8 (instanceRef pdp_ram_12_1_14))
+              (portRef DIA8 (instanceRef pdp_ram_13_1_10))
+              (portRef DIA8 (instanceRef pdp_ram_14_1_6))
+              (portRef DIA8 (instanceRef pdp_ram_15_1_2))))
+          (net datain16
+            (joined
+              (portRef (member Data 19))
+              (portRef DIA7 (instanceRef pdp_ram_0_1_62))
+              (portRef DIA7 (instanceRef pdp_ram_1_1_58))
+              (portRef DIA7 (instanceRef pdp_ram_2_1_54))
+              (portRef DIA7 (instanceRef pdp_ram_3_1_50))
+              (portRef DIA7 (instanceRef pdp_ram_4_1_46))
+              (portRef DIA7 (instanceRef pdp_ram_5_1_42))
+              (portRef DIA7 (instanceRef pdp_ram_6_1_38))
+              (portRef DIA7 (instanceRef pdp_ram_7_1_34))
+              (portRef DIA7 (instanceRef pdp_ram_8_1_30))
+              (portRef DIA7 (instanceRef pdp_ram_9_1_26))
+              (portRef DIA7 (instanceRef pdp_ram_10_1_22))
+              (portRef DIA7 (instanceRef pdp_ram_11_1_18))
+              (portRef DIA7 (instanceRef pdp_ram_12_1_14))
+              (portRef DIA7 (instanceRef pdp_ram_13_1_10))
+              (portRef DIA7 (instanceRef pdp_ram_14_1_6))
+              (portRef DIA7 (instanceRef pdp_ram_15_1_2))))
+          (net datain15
+            (joined
+              (portRef (member Data 20))
+              (portRef DIA6 (instanceRef pdp_ram_0_1_62))
+              (portRef DIA6 (instanceRef pdp_ram_1_1_58))
+              (portRef DIA6 (instanceRef pdp_ram_2_1_54))
+              (portRef DIA6 (instanceRef pdp_ram_3_1_50))
+              (portRef DIA6 (instanceRef pdp_ram_4_1_46))
+              (portRef DIA6 (instanceRef pdp_ram_5_1_42))
+              (portRef DIA6 (instanceRef pdp_ram_6_1_38))
+              (portRef DIA6 (instanceRef pdp_ram_7_1_34))
+              (portRef DIA6 (instanceRef pdp_ram_8_1_30))
+              (portRef DIA6 (instanceRef pdp_ram_9_1_26))
+              (portRef DIA6 (instanceRef pdp_ram_10_1_22))
+              (portRef DIA6 (instanceRef pdp_ram_11_1_18))
+              (portRef DIA6 (instanceRef pdp_ram_12_1_14))
+              (portRef DIA6 (instanceRef pdp_ram_13_1_10))
+              (portRef DIA6 (instanceRef pdp_ram_14_1_6))
+              (portRef DIA6 (instanceRef pdp_ram_15_1_2))))
+          (net datain14
+            (joined
+              (portRef (member Data 21))
+              (portRef DIA5 (instanceRef pdp_ram_0_1_62))
+              (portRef DIA5 (instanceRef pdp_ram_1_1_58))
+              (portRef DIA5 (instanceRef pdp_ram_2_1_54))
+              (portRef DIA5 (instanceRef pdp_ram_3_1_50))
+              (portRef DIA5 (instanceRef pdp_ram_4_1_46))
+              (portRef DIA5 (instanceRef pdp_ram_5_1_42))
+              (portRef DIA5 (instanceRef pdp_ram_6_1_38))
+              (portRef DIA5 (instanceRef pdp_ram_7_1_34))
+              (portRef DIA5 (instanceRef pdp_ram_8_1_30))
+              (portRef DIA5 (instanceRef pdp_ram_9_1_26))
+              (portRef DIA5 (instanceRef pdp_ram_10_1_22))
+              (portRef DIA5 (instanceRef pdp_ram_11_1_18))
+              (portRef DIA5 (instanceRef pdp_ram_12_1_14))
+              (portRef DIA5 (instanceRef pdp_ram_13_1_10))
+              (portRef DIA5 (instanceRef pdp_ram_14_1_6))
+              (portRef DIA5 (instanceRef pdp_ram_15_1_2))))
+          (net datain13
+            (joined
+              (portRef (member Data 22))
+              (portRef DIA4 (instanceRef pdp_ram_0_1_62))
+              (portRef DIA4 (instanceRef pdp_ram_1_1_58))
+              (portRef DIA4 (instanceRef pdp_ram_2_1_54))
+              (portRef DIA4 (instanceRef pdp_ram_3_1_50))
+              (portRef DIA4 (instanceRef pdp_ram_4_1_46))
+              (portRef DIA4 (instanceRef pdp_ram_5_1_42))
+              (portRef DIA4 (instanceRef pdp_ram_6_1_38))
+              (portRef DIA4 (instanceRef pdp_ram_7_1_34))
+              (portRef DIA4 (instanceRef pdp_ram_8_1_30))
+              (portRef DIA4 (instanceRef pdp_ram_9_1_26))
+              (portRef DIA4 (instanceRef pdp_ram_10_1_22))
+              (portRef DIA4 (instanceRef pdp_ram_11_1_18))
+              (portRef DIA4 (instanceRef pdp_ram_12_1_14))
+              (portRef DIA4 (instanceRef pdp_ram_13_1_10))
+              (portRef DIA4 (instanceRef pdp_ram_14_1_6))
+              (portRef DIA4 (instanceRef pdp_ram_15_1_2))))
+          (net datain12
+            (joined
+              (portRef (member Data 23))
+              (portRef DIA3 (instanceRef pdp_ram_0_1_62))
+              (portRef DIA3 (instanceRef pdp_ram_1_1_58))
+              (portRef DIA3 (instanceRef pdp_ram_2_1_54))
+              (portRef DIA3 (instanceRef pdp_ram_3_1_50))
+              (portRef DIA3 (instanceRef pdp_ram_4_1_46))
+              (portRef DIA3 (instanceRef pdp_ram_5_1_42))
+              (portRef DIA3 (instanceRef pdp_ram_6_1_38))
+              (portRef DIA3 (instanceRef pdp_ram_7_1_34))
+              (portRef DIA3 (instanceRef pdp_ram_8_1_30))
+              (portRef DIA3 (instanceRef pdp_ram_9_1_26))
+              (portRef DIA3 (instanceRef pdp_ram_10_1_22))
+              (portRef DIA3 (instanceRef pdp_ram_11_1_18))
+              (portRef DIA3 (instanceRef pdp_ram_12_1_14))
+              (portRef DIA3 (instanceRef pdp_ram_13_1_10))
+              (portRef DIA3 (instanceRef pdp_ram_14_1_6))
+              (portRef DIA3 (instanceRef pdp_ram_15_1_2))))
+          (net datain11
+            (joined
+              (portRef (member Data 24))
+              (portRef DIA2 (instanceRef pdp_ram_0_1_62))
+              (portRef DIA2 (instanceRef pdp_ram_1_1_58))
+              (portRef DIA2 (instanceRef pdp_ram_2_1_54))
+              (portRef DIA2 (instanceRef pdp_ram_3_1_50))
+              (portRef DIA2 (instanceRef pdp_ram_4_1_46))
+              (portRef DIA2 (instanceRef pdp_ram_5_1_42))
+              (portRef DIA2 (instanceRef pdp_ram_6_1_38))
+              (portRef DIA2 (instanceRef pdp_ram_7_1_34))
+              (portRef DIA2 (instanceRef pdp_ram_8_1_30))
+              (portRef DIA2 (instanceRef pdp_ram_9_1_26))
+              (portRef DIA2 (instanceRef pdp_ram_10_1_22))
+              (portRef DIA2 (instanceRef pdp_ram_11_1_18))
+              (portRef DIA2 (instanceRef pdp_ram_12_1_14))
+              (portRef DIA2 (instanceRef pdp_ram_13_1_10))
+              (portRef DIA2 (instanceRef pdp_ram_14_1_6))
+              (portRef DIA2 (instanceRef pdp_ram_15_1_2))))
+          (net datain10
+            (joined
+              (portRef (member Data 25))
+              (portRef DIA1 (instanceRef pdp_ram_0_1_62))
+              (portRef DIA1 (instanceRef pdp_ram_1_1_58))
+              (portRef DIA1 (instanceRef pdp_ram_2_1_54))
+              (portRef DIA1 (instanceRef pdp_ram_3_1_50))
+              (portRef DIA1 (instanceRef pdp_ram_4_1_46))
+              (portRef DIA1 (instanceRef pdp_ram_5_1_42))
+              (portRef DIA1 (instanceRef pdp_ram_6_1_38))
+              (portRef DIA1 (instanceRef pdp_ram_7_1_34))
+              (portRef DIA1 (instanceRef pdp_ram_8_1_30))
+              (portRef DIA1 (instanceRef pdp_ram_9_1_26))
+              (portRef DIA1 (instanceRef pdp_ram_10_1_22))
+              (portRef DIA1 (instanceRef pdp_ram_11_1_18))
+              (portRef DIA1 (instanceRef pdp_ram_12_1_14))
+              (portRef DIA1 (instanceRef pdp_ram_13_1_10))
+              (portRef DIA1 (instanceRef pdp_ram_14_1_6))
+              (portRef DIA1 (instanceRef pdp_ram_15_1_2))))
+          (net datain9
+            (joined
+              (portRef (member Data 26))
+              (portRef DIA0 (instanceRef pdp_ram_0_1_62))
+              (portRef DIA0 (instanceRef pdp_ram_1_1_58))
+              (portRef DIA0 (instanceRef pdp_ram_2_1_54))
+              (portRef DIA0 (instanceRef pdp_ram_3_1_50))
+              (portRef DIA0 (instanceRef pdp_ram_4_1_46))
+              (portRef DIA0 (instanceRef pdp_ram_5_1_42))
+              (portRef DIA0 (instanceRef pdp_ram_6_1_38))
+              (portRef DIA0 (instanceRef pdp_ram_7_1_34))
+              (portRef DIA0 (instanceRef pdp_ram_8_1_30))
+              (portRef DIA0 (instanceRef pdp_ram_9_1_26))
+              (portRef DIA0 (instanceRef pdp_ram_10_1_22))
+              (portRef DIA0 (instanceRef pdp_ram_11_1_18))
+              (portRef DIA0 (instanceRef pdp_ram_12_1_14))
+              (portRef DIA0 (instanceRef pdp_ram_13_1_10))
+              (portRef DIA0 (instanceRef pdp_ram_14_1_6))
+              (portRef DIA0 (instanceRef pdp_ram_15_1_2))))
+          (net datain8
+            (joined
+              (portRef (member Data 27))
+              (portRef DIA8 (instanceRef pdp_ram_0_0_63))
+              (portRef DIA8 (instanceRef pdp_ram_1_0_59))
+              (portRef DIA8 (instanceRef pdp_ram_2_0_55))
+              (portRef DIA8 (instanceRef pdp_ram_3_0_51))
+              (portRef DIA8 (instanceRef pdp_ram_4_0_47))
+              (portRef DIA8 (instanceRef pdp_ram_5_0_43))
+              (portRef DIA8 (instanceRef pdp_ram_6_0_39))
+              (portRef DIA8 (instanceRef pdp_ram_7_0_35))
+              (portRef DIA8 (instanceRef pdp_ram_8_0_31))
+              (portRef DIA8 (instanceRef pdp_ram_9_0_27))
+              (portRef DIA8 (instanceRef pdp_ram_10_0_23))
+              (portRef DIA8 (instanceRef pdp_ram_11_0_19))
+              (portRef DIA8 (instanceRef pdp_ram_12_0_15))
+              (portRef DIA8 (instanceRef pdp_ram_13_0_11))
+              (portRef DIA8 (instanceRef pdp_ram_14_0_7))
+              (portRef DIA8 (instanceRef pdp_ram_15_0_3))))
+          (net datain7
+            (joined
+              (portRef (member Data 28))
+              (portRef DIA7 (instanceRef pdp_ram_0_0_63))
+              (portRef DIA7 (instanceRef pdp_ram_1_0_59))
+              (portRef DIA7 (instanceRef pdp_ram_2_0_55))
+              (portRef DIA7 (instanceRef pdp_ram_3_0_51))
+              (portRef DIA7 (instanceRef pdp_ram_4_0_47))
+              (portRef DIA7 (instanceRef pdp_ram_5_0_43))
+              (portRef DIA7 (instanceRef pdp_ram_6_0_39))
+              (portRef DIA7 (instanceRef pdp_ram_7_0_35))
+              (portRef DIA7 (instanceRef pdp_ram_8_0_31))
+              (portRef DIA7 (instanceRef pdp_ram_9_0_27))
+              (portRef DIA7 (instanceRef pdp_ram_10_0_23))
+              (portRef DIA7 (instanceRef pdp_ram_11_0_19))
+              (portRef DIA7 (instanceRef pdp_ram_12_0_15))
+              (portRef DIA7 (instanceRef pdp_ram_13_0_11))
+              (portRef DIA7 (instanceRef pdp_ram_14_0_7))
+              (portRef DIA7 (instanceRef pdp_ram_15_0_3))))
+          (net datain6
+            (joined
+              (portRef (member Data 29))
+              (portRef DIA6 (instanceRef pdp_ram_0_0_63))
+              (portRef DIA6 (instanceRef pdp_ram_1_0_59))
+              (portRef DIA6 (instanceRef pdp_ram_2_0_55))
+              (portRef DIA6 (instanceRef pdp_ram_3_0_51))
+              (portRef DIA6 (instanceRef pdp_ram_4_0_47))
+              (portRef DIA6 (instanceRef pdp_ram_5_0_43))
+              (portRef DIA6 (instanceRef pdp_ram_6_0_39))
+              (portRef DIA6 (instanceRef pdp_ram_7_0_35))
+              (portRef DIA6 (instanceRef pdp_ram_8_0_31))
+              (portRef DIA6 (instanceRef pdp_ram_9_0_27))
+              (portRef DIA6 (instanceRef pdp_ram_10_0_23))
+              (portRef DIA6 (instanceRef pdp_ram_11_0_19))
+              (portRef DIA6 (instanceRef pdp_ram_12_0_15))
+              (portRef DIA6 (instanceRef pdp_ram_13_0_11))
+              (portRef DIA6 (instanceRef pdp_ram_14_0_7))
+              (portRef DIA6 (instanceRef pdp_ram_15_0_3))))
+          (net datain5
+            (joined
+              (portRef (member Data 30))
+              (portRef DIA5 (instanceRef pdp_ram_0_0_63))
+              (portRef DIA5 (instanceRef pdp_ram_1_0_59))
+              (portRef DIA5 (instanceRef pdp_ram_2_0_55))
+              (portRef DIA5 (instanceRef pdp_ram_3_0_51))
+              (portRef DIA5 (instanceRef pdp_ram_4_0_47))
+              (portRef DIA5 (instanceRef pdp_ram_5_0_43))
+              (portRef DIA5 (instanceRef pdp_ram_6_0_39))
+              (portRef DIA5 (instanceRef pdp_ram_7_0_35))
+              (portRef DIA5 (instanceRef pdp_ram_8_0_31))
+              (portRef DIA5 (instanceRef pdp_ram_9_0_27))
+              (portRef DIA5 (instanceRef pdp_ram_10_0_23))
+              (portRef DIA5 (instanceRef pdp_ram_11_0_19))
+              (portRef DIA5 (instanceRef pdp_ram_12_0_15))
+              (portRef DIA5 (instanceRef pdp_ram_13_0_11))
+              (portRef DIA5 (instanceRef pdp_ram_14_0_7))
+              (portRef DIA5 (instanceRef pdp_ram_15_0_3))))
+          (net datain4
+            (joined
+              (portRef (member Data 31))
+              (portRef DIA4 (instanceRef pdp_ram_0_0_63))
+              (portRef DIA4 (instanceRef pdp_ram_1_0_59))
+              (portRef DIA4 (instanceRef pdp_ram_2_0_55))
+              (portRef DIA4 (instanceRef pdp_ram_3_0_51))
+              (portRef DIA4 (instanceRef pdp_ram_4_0_47))
+              (portRef DIA4 (instanceRef pdp_ram_5_0_43))
+              (portRef DIA4 (instanceRef pdp_ram_6_0_39))
+              (portRef DIA4 (instanceRef pdp_ram_7_0_35))
+              (portRef DIA4 (instanceRef pdp_ram_8_0_31))
+              (portRef DIA4 (instanceRef pdp_ram_9_0_27))
+              (portRef DIA4 (instanceRef pdp_ram_10_0_23))
+              (portRef DIA4 (instanceRef pdp_ram_11_0_19))
+              (portRef DIA4 (instanceRef pdp_ram_12_0_15))
+              (portRef DIA4 (instanceRef pdp_ram_13_0_11))
+              (portRef DIA4 (instanceRef pdp_ram_14_0_7))
+              (portRef DIA4 (instanceRef pdp_ram_15_0_3))))
+          (net datain3
+            (joined
+              (portRef (member Data 32))
+              (portRef DIA3 (instanceRef pdp_ram_0_0_63))
+              (portRef DIA3 (instanceRef pdp_ram_1_0_59))
+              (portRef DIA3 (instanceRef pdp_ram_2_0_55))
+              (portRef DIA3 (instanceRef pdp_ram_3_0_51))
+              (portRef DIA3 (instanceRef pdp_ram_4_0_47))
+              (portRef DIA3 (instanceRef pdp_ram_5_0_43))
+              (portRef DIA3 (instanceRef pdp_ram_6_0_39))
+              (portRef DIA3 (instanceRef pdp_ram_7_0_35))
+              (portRef DIA3 (instanceRef pdp_ram_8_0_31))
+              (portRef DIA3 (instanceRef pdp_ram_9_0_27))
+              (portRef DIA3 (instanceRef pdp_ram_10_0_23))
+              (portRef DIA3 (instanceRef pdp_ram_11_0_19))
+              (portRef DIA3 (instanceRef pdp_ram_12_0_15))
+              (portRef DIA3 (instanceRef pdp_ram_13_0_11))
+              (portRef DIA3 (instanceRef pdp_ram_14_0_7))
+              (portRef DIA3 (instanceRef pdp_ram_15_0_3))))
+          (net datain2
+            (joined
+              (portRef (member Data 33))
+              (portRef DIA2 (instanceRef pdp_ram_0_0_63))
+              (portRef DIA2 (instanceRef pdp_ram_1_0_59))
+              (portRef DIA2 (instanceRef pdp_ram_2_0_55))
+              (portRef DIA2 (instanceRef pdp_ram_3_0_51))
+              (portRef DIA2 (instanceRef pdp_ram_4_0_47))
+              (portRef DIA2 (instanceRef pdp_ram_5_0_43))
+              (portRef DIA2 (instanceRef pdp_ram_6_0_39))
+              (portRef DIA2 (instanceRef pdp_ram_7_0_35))
+              (portRef DIA2 (instanceRef pdp_ram_8_0_31))
+              (portRef DIA2 (instanceRef pdp_ram_9_0_27))
+              (portRef DIA2 (instanceRef pdp_ram_10_0_23))
+              (portRef DIA2 (instanceRef pdp_ram_11_0_19))
+              (portRef DIA2 (instanceRef pdp_ram_12_0_15))
+              (portRef DIA2 (instanceRef pdp_ram_13_0_11))
+              (portRef DIA2 (instanceRef pdp_ram_14_0_7))
+              (portRef DIA2 (instanceRef pdp_ram_15_0_3))))
+          (net datain1
+            (joined
+              (portRef (member Data 34))
+              (portRef DIA1 (instanceRef pdp_ram_0_0_63))
+              (portRef DIA1 (instanceRef pdp_ram_1_0_59))
+              (portRef DIA1 (instanceRef pdp_ram_2_0_55))
+              (portRef DIA1 (instanceRef pdp_ram_3_0_51))
+              (portRef DIA1 (instanceRef pdp_ram_4_0_47))
+              (portRef DIA1 (instanceRef pdp_ram_5_0_43))
+              (portRef DIA1 (instanceRef pdp_ram_6_0_39))
+              (portRef DIA1 (instanceRef pdp_ram_7_0_35))
+              (portRef DIA1 (instanceRef pdp_ram_8_0_31))
+              (portRef DIA1 (instanceRef pdp_ram_9_0_27))
+              (portRef DIA1 (instanceRef pdp_ram_10_0_23))
+              (portRef DIA1 (instanceRef pdp_ram_11_0_19))
+              (portRef DIA1 (instanceRef pdp_ram_12_0_15))
+              (portRef DIA1 (instanceRef pdp_ram_13_0_11))
+              (portRef DIA1 (instanceRef pdp_ram_14_0_7))
+              (portRef DIA1 (instanceRef pdp_ram_15_0_3))))
+          (net datain0
+            (joined
+              (portRef (member Data 35))
+              (portRef DIA0 (instanceRef pdp_ram_0_0_63))
+              (portRef DIA0 (instanceRef pdp_ram_1_0_59))
+              (portRef DIA0 (instanceRef pdp_ram_2_0_55))
+              (portRef DIA0 (instanceRef pdp_ram_3_0_51))
+              (portRef DIA0 (instanceRef pdp_ram_4_0_47))
+              (portRef DIA0 (instanceRef pdp_ram_5_0_43))
+              (portRef DIA0 (instanceRef pdp_ram_6_0_39))
+              (portRef DIA0 (instanceRef pdp_ram_7_0_35))
+              (portRef DIA0 (instanceRef pdp_ram_8_0_31))
+              (portRef DIA0 (instanceRef pdp_ram_9_0_27))
+              (portRef DIA0 (instanceRef pdp_ram_10_0_23))
+              (portRef DIA0 (instanceRef pdp_ram_11_0_19))
+              (portRef DIA0 (instanceRef pdp_ram_12_0_15))
+              (portRef DIA0 (instanceRef pdp_ram_13_0_11))
+              (portRef DIA0 (instanceRef pdp_ram_14_0_7))
+              (portRef DIA0 (instanceRef pdp_ram_15_0_3))))))))
+  (design fifo_36x32k_oreg
+    (cellRef fifo_36x32k_oreg
+      (libraryRef ORCLIB)))
+)

diff --git a/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.fdc b/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.fdc
new file mode 100644 (file)
index 0000000..6fbcac9
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.fdc
@@ -0,0 +1,2 @@
+###==== Start Configuration
+

diff --git a/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.lpc b/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.lpc
new file mode 100644 (file)
index 0000000..6a11f2a
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.lpc
@@ -0,0 +1,50 @@
+[Device]
+Family=ecp5um
+PartType=LFE5UM-85F
+PartName=LFE5UM-85F-8MG285C
+SpeedGrade=8
+Package=CSFBGA285
+OperatingCondition=COM
+Status=C
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO
+CoreRevision=5.0
+ModuleName=fifo_36x32k_oreg
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=03/18/2015
+Time=14:42:29
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=32768
+Width=36
+regout=1
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=1
+PfMode=Dynamic - Single Threshold
+PfAssert=508
+PfDeassert=506
+Reset=Async
+Reset1=Sync
+RDataCount=1
+EnECC=0
+EnFWFT=0
+
+[Command]
+cmd_line= -w -n fifo_36x32k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 32768 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill

diff --git a/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.ngd b/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.ngd
new file mode 100644 (file)
index 0000000..2c537bd
Binary files /dev/null and b/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.ngd differ

diff --git a/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.ngo b/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.ngo
new file mode 100644 (file)
index 0000000..24133b2
Binary files /dev/null and b/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.ngo differ

diff --git a/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.vhd b/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.vhd
new file mode 100644 (file)
index 0000000..481cbdb
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.vhd
@@ -0,0 +1,5813 @@
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80
+-- Module  Version: 5.0
+--/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x32k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 32768 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.fdc 
+
+-- Wed Mar 18 14:42:30 2015
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity fifo_36x32k_oreg is
+    port (
+        Data: in  std_logic_vector(35 downto 0); 
+        Clock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        AmFullThresh: in  std_logic_vector(14 downto 0); 
+        Q: out  std_logic_vector(35 downto 0); 
+        WCNT: out  std_logic_vector(15 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic; 
+        AlmostFull: out  std_logic);
+end fifo_36x32k_oreg;
+
+architecture Structure of fifo_36x32k_oreg is
+
+    -- internal signal declarations
+    signal invout_2: std_logic;
+    signal invout_1: std_logic;
+    signal rden_i_inv: std_logic;
+    signal wptr_14_inv: std_logic;
+    signal rptr_14_inv: std_logic;
+    signal wptr_13_inv: std_logic;
+    signal rptr_13_inv: std_logic;
+    signal wptr_12_inv: std_logic;
+    signal rptr_12_inv: std_logic;
+    signal wptr_11_inv: std_logic;
+    signal rptr_11_inv: std_logic;
+    signal invout_0: std_logic;
+    signal r_nw: std_logic;
+    signal dec1_r10: std_logic;
+    signal dec0_p00: std_logic;
+    signal dec3_r10: std_logic;
+    signal dec2_p00: std_logic;
+    signal dec5_r10: std_logic;
+    signal dec4_p00: std_logic;
+    signal dec7_r10: std_logic;
+    signal dec6_p00: std_logic;
+    signal dec9_r11: std_logic;
+    signal dec8_p01: std_logic;
+    signal dec11_r11: std_logic;
+    signal dec10_p01: std_logic;
+    signal dec13_r11: std_logic;
+    signal dec12_p01: std_logic;
+    signal dec15_r11: std_logic;
+    signal dec14_p01: std_logic;
+    signal dec17_r12: std_logic;
+    signal dec16_p02: std_logic;
+    signal dec19_r12: std_logic;
+    signal dec18_p02: std_logic;
+    signal dec21_r12: std_logic;
+    signal dec20_p02: std_logic;
+    signal dec23_r12: std_logic;
+    signal dec22_p02: std_logic;
+    signal dec25_r13: std_logic;
+    signal dec24_p03: std_logic;
+    signal dec27_r13: std_logic;
+    signal dec26_p03: std_logic;
+    signal dec29_r13: std_logic;
+    signal dec28_p03: std_logic;
+    signal dec31_r13: std_logic;
+    signal dec30_p03: std_logic;
+    signal dec33_r14: std_logic;
+    signal dec32_p04: std_logic;
+    signal dec35_r14: std_logic;
+    signal dec34_p04: std_logic;
+    signal dec37_r14: std_logic;
+    signal dec36_p04: std_logic;
+    signal dec39_r14: std_logic;
+    signal dec38_p04: std_logic;
+    signal dec41_r15: std_logic;
+    signal dec40_p05: std_logic;
+    signal dec43_r15: std_logic;
+    signal dec42_p05: std_logic;
+    signal dec45_r15: std_logic;
+    signal dec44_p05: std_logic;
+    signal dec47_r15: std_logic;
+    signal dec46_p05: std_logic;
+    signal dec49_r16: std_logic;
+    signal dec48_p06: std_logic;
+    signal dec51_r16: std_logic;
+    signal dec50_p06: std_logic;
+    signal dec53_r16: std_logic;
+    signal dec52_p06: std_logic;
+    signal dec55_r16: std_logic;
+    signal dec54_p06: std_logic;
+    signal dec57_r17: std_logic;
+    signal dec56_p07: std_logic;
+    signal dec59_r17: std_logic;
+    signal dec58_p07: std_logic;
+    signal dec61_r17: std_logic;
+    signal dec60_p07: std_logic;
+    signal dec63_r17: std_logic;
+    signal dec62_p07: std_logic;
+    signal dec65_r18: std_logic;
+    signal dec64_p08: std_logic;
+    signal dec67_r18: std_logic;
+    signal dec66_p08: std_logic;
+    signal dec69_r18: std_logic;
+    signal dec68_p08: std_logic;
+    signal dec71_r18: std_logic;
+    signal dec70_p08: std_logic;
+    signal dec73_r19: std_logic;
+    signal dec72_p09: std_logic;
+    signal dec75_r19: std_logic;
+    signal dec74_p09: std_logic;
+    signal dec77_r19: std_logic;
+    signal dec76_p09: std_logic;
+    signal dec79_r19: std_logic;
+    signal dec78_p09: std_logic;
+    signal dec81_r110: std_logic;
+    signal dec80_p010: std_logic;
+    signal dec83_r110: std_logic;
+    signal dec82_p010: std_logic;
+    signal dec85_r110: std_logic;
+    signal dec84_p010: std_logic;
+    signal dec87_r110: std_logic;
+    signal dec86_p010: std_logic;
+    signal dec89_r111: std_logic;
+    signal dec88_p011: std_logic;
+    signal dec91_r111: std_logic;
+    signal dec90_p011: std_logic;
+    signal dec93_r111: std_logic;
+    signal dec92_p011: std_logic;
+    signal dec95_r111: std_logic;
+    signal dec94_p011: std_logic;
+    signal dec97_r112: std_logic;
+    signal dec96_p012: std_logic;
+    signal dec99_r112: std_logic;
+    signal dec98_p012: std_logic;
+    signal dec101_r112: std_logic;
+    signal dec100_p012: std_logic;
+    signal dec103_r112: std_logic;
+    signal dec102_p012: std_logic;
+    signal dec105_r113: std_logic;
+    signal dec104_p013: std_logic;
+    signal dec107_r113: std_logic;
+    signal dec106_p013: std_logic;
+    signal dec109_r113: std_logic;
+    signal dec108_p013: std_logic;
+    signal dec111_r113: std_logic;
+    signal dec110_p013: std_logic;
+    signal dec113_r114: std_logic;
+    signal dec112_p014: std_logic;
+    signal dec115_r114: std_logic;
+    signal dec114_p014: std_logic;
+    signal dec117_r114: std_logic;
+    signal dec116_p014: std_logic;
+    signal dec119_r114: std_logic;
+    signal dec118_p014: std_logic;
+    signal dec121_r115: std_logic;
+    signal dec120_p015: std_logic;
+    signal dec123_r115: std_logic;
+    signal dec122_p015: std_logic;
+    signal dec125_r115: std_logic;
+    signal dec124_p015: std_logic;
+    signal dec127_r115: std_logic;
+    signal dec126_p015: std_logic;
+    signal fcnt_en: std_logic;
+    signal empty_i: std_logic;
+    signal empty_d: std_logic;
+    signal full_i: std_logic;
+    signal full_d: std_logic;
+    signal wptr_0: std_logic;
+    signal wptr_1: std_logic;
+    signal wptr_2: std_logic;
+    signal wptr_3: std_logic;
+    signal wptr_4: std_logic;
+    signal wptr_5: std_logic;
+    signal wptr_6: std_logic;
+    signal wptr_7: std_logic;
+    signal wptr_8: std_logic;
+    signal wptr_9: std_logic;
+    signal wptr_10: std_logic;
+    signal wptr_11: std_logic;
+    signal wptr_12: std_logic;
+    signal wptr_13: std_logic;
+    signal wptr_14: std_logic;
+    signal wptr_15: std_logic;
+    signal rptr_15: std_logic;
+    signal rptr_11_ff: std_logic;
+    signal rptr_12_ff: std_logic;
+    signal rptr_13_ff: std_logic;
+    signal rptr_14_ff: std_logic;
+    signal ifcount_0: std_logic;
+    signal ifcount_1: std_logic;
+    signal bdcnt_bctr_ci: std_logic;
+    signal ifcount_2: std_logic;
+    signal ifcount_3: std_logic;
+    signal co0: std_logic;
+    signal ifcount_4: std_logic;
+    signal ifcount_5: std_logic;
+    signal co1: std_logic;
+    signal ifcount_6: std_logic;
+    signal ifcount_7: std_logic;
+    signal co2: std_logic;
+    signal ifcount_8: std_logic;
+    signal ifcount_9: std_logic;
+    signal co3: std_logic;
+    signal ifcount_10: std_logic;
+    signal ifcount_11: std_logic;
+    signal co4: std_logic;
+    signal ifcount_12: std_logic;
+    signal ifcount_13: std_logic;
+    signal co5: std_logic;
+    signal ifcount_14: std_logic;
+    signal ifcount_15: std_logic;
+    signal co7: std_logic;
+    signal co6: std_logic;
+    signal cmp_ci: std_logic;
+    signal rden_i: std_logic;
+    signal co0_1: std_logic;
+    signal co1_1: std_logic;
+    signal co2_1: std_logic;
+    signal co3_1: std_logic;
+    signal co4_1: std_logic;
+    signal co5_1: std_logic;
+    signal co6_1: std_logic;
+    signal cmp_le_1: std_logic;
+    signal cmp_le_1_c: std_logic;
+    signal cmp_ci_1: std_logic;
+    signal fcount_0: std_logic;
+    signal fcount_1: std_logic;
+    signal co0_2: std_logic;
+    signal fcount_2: std_logic;
+    signal fcount_3: std_logic;
+    signal co1_2: std_logic;
+    signal fcount_4: std_logic;
+    signal fcount_5: std_logic;
+    signal co2_2: std_logic;
+    signal fcount_6: std_logic;
+    signal fcount_7: std_logic;
+    signal co3_2: std_logic;
+    signal fcount_8: std_logic;
+    signal fcount_9: std_logic;
+    signal co4_2: std_logic;
+    signal fcount_10: std_logic;
+    signal fcount_11: std_logic;
+    signal co5_2: std_logic;
+    signal fcount_12: std_logic;
+    signal fcount_13: std_logic;
+    signal co6_2: std_logic;
+    signal wren_i_inv: std_logic;
+    signal fcount_14: std_logic;
+    signal fcount_15: std_logic;
+    signal cmp_ge_d1: std_logic;
+    signal cmp_ge_d1_c: std_logic;
+    signal iwcount_0: std_logic;
+    signal iwcount_1: std_logic;
+    signal w_ctr_ci: std_logic;
+    signal iwcount_2: std_logic;
+    signal iwcount_3: std_logic;
+    signal co0_3: std_logic;
+    signal iwcount_4: std_logic;
+    signal iwcount_5: std_logic;
+    signal co1_3: std_logic;
+    signal iwcount_6: std_logic;
+    signal iwcount_7: std_logic;
+    signal co2_3: std_logic;
+    signal iwcount_8: std_logic;
+    signal iwcount_9: std_logic;
+    signal co3_3: std_logic;
+    signal iwcount_10: std_logic;
+    signal iwcount_11: std_logic;
+    signal co4_3: std_logic;
+    signal iwcount_12: std_logic;
+    signal iwcount_13: std_logic;
+    signal co5_3: std_logic;
+    signal iwcount_14: std_logic;
+    signal iwcount_15: std_logic;
+    signal co7_1: std_logic;
+    signal co6_3: std_logic;
+    signal wcount_15: std_logic;
+    signal ircount_0: std_logic;
+    signal ircount_1: std_logic;
+    signal r_ctr_ci: std_logic;
+    signal rcount_0: std_logic;
+    signal rcount_1: std_logic;
+    signal ircount_2: std_logic;
+    signal ircount_3: std_logic;
+    signal co0_4: std_logic;
+    signal rcount_2: std_logic;
+    signal rcount_3: std_logic;
+    signal ircount_4: std_logic;
+    signal ircount_5: std_logic;
+    signal co1_4: std_logic;
+    signal rcount_4: std_logic;
+    signal rcount_5: std_logic;
+    signal ircount_6: std_logic;
+    signal ircount_7: std_logic;
+    signal co2_4: std_logic;
+    signal rcount_6: std_logic;
+    signal rcount_7: std_logic;
+    signal ircount_8: std_logic;
+    signal ircount_9: std_logic;
+    signal co3_4: std_logic;
+    signal rcount_8: std_logic;
+    signal rcount_9: std_logic;
+    signal ircount_10: std_logic;
+    signal ircount_11: std_logic;
+    signal co4_4: std_logic;
+    signal rcount_10: std_logic;
+    signal rcount_11: std_logic;
+    signal ircount_12: std_logic;
+    signal ircount_13: std_logic;
+    signal co5_4: std_logic;
+    signal rcount_12: std_logic;
+    signal rcount_13: std_logic;
+    signal ircount_14: std_logic;
+    signal ircount_15: std_logic;
+    signal co7_2: std_logic;
+    signal co6_4: std_logic;
+    signal rcount_14: std_logic;
+    signal rcount_15: std_logic;
+    signal mdout1_15_0: std_logic;
+    signal mdout1_14_0: std_logic;
+    signal mdout1_13_0: std_logic;
+    signal mdout1_12_0: std_logic;
+    signal mdout1_11_0: std_logic;
+    signal mdout1_10_0: std_logic;
+    signal mdout1_9_0: std_logic;
+    signal mdout1_8_0: std_logic;
+    signal mdout1_7_0: std_logic;
+    signal mdout1_6_0: std_logic;
+    signal mdout1_5_0: std_logic;
+    signal mdout1_4_0: std_logic;
+    signal mdout1_3_0: std_logic;
+    signal mdout1_2_0: std_logic;
+    signal mdout1_1_0: std_logic;
+    signal mdout1_0_0: std_logic;
+    signal mdout1_15_1: std_logic;
+    signal mdout1_14_1: std_logic;
+    signal mdout1_13_1: std_logic;
+    signal mdout1_12_1: std_logic;
+    signal mdout1_11_1: std_logic;
+    signal mdout1_10_1: std_logic;
+    signal mdout1_9_1: std_logic;
+    signal mdout1_8_1: std_logic;
+    signal mdout1_7_1: std_logic;
+    signal mdout1_6_1: std_logic;
+    signal mdout1_5_1: std_logic;
+    signal mdout1_4_1: std_logic;
+    signal mdout1_3_1: std_logic;
+    signal mdout1_2_1: std_logic;
+    signal mdout1_1_1: std_logic;
+    signal mdout1_0_1: std_logic;
+    signal mdout1_15_2: std_logic;
+    signal mdout1_14_2: std_logic;
+    signal mdout1_13_2: std_logic;
+    signal mdout1_12_2: std_logic;
+    signal mdout1_11_2: std_logic;
+    signal mdout1_10_2: std_logic;
+    signal mdout1_9_2: std_logic;
+    signal mdout1_8_2: std_logic;
+    signal mdout1_7_2: std_logic;
+    signal mdout1_6_2: std_logic;
+    signal mdout1_5_2: std_logic;
+    signal mdout1_4_2: std_logic;
+    signal mdout1_3_2: std_logic;
+    signal mdout1_2_2: std_logic;
+    signal mdout1_1_2: std_logic;
+    signal mdout1_0_2: std_logic;
+    signal mdout1_15_3: std_logic;
+    signal mdout1_14_3: std_logic;
+    signal mdout1_13_3: std_logic;
+    signal mdout1_12_3: std_logic;
+    signal mdout1_11_3: std_logic;
+    signal mdout1_10_3: std_logic;
+    signal mdout1_9_3: std_logic;
+    signal mdout1_8_3: std_logic;
+    signal mdout1_7_3: std_logic;
+    signal mdout1_6_3: std_logic;
+    signal mdout1_5_3: std_logic;
+    signal mdout1_4_3: std_logic;
+    signal mdout1_3_3: std_logic;
+    signal mdout1_2_3: std_logic;
+    signal mdout1_1_3: std_logic;
+    signal mdout1_0_3: std_logic;
+    signal mdout1_15_4: std_logic;
+    signal mdout1_14_4: std_logic;
+    signal mdout1_13_4: std_logic;
+    signal mdout1_12_4: std_logic;
+    signal mdout1_11_4: std_logic;
+    signal mdout1_10_4: std_logic;
+    signal mdout1_9_4: std_logic;
+    signal mdout1_8_4: std_logic;
+    signal mdout1_7_4: std_logic;
+    signal mdout1_6_4: std_logic;
+    signal mdout1_5_4: std_logic;
+    signal mdout1_4_4: std_logic;
+    signal mdout1_3_4: std_logic;
+    signal mdout1_2_4: std_logic;
+    signal mdout1_1_4: std_logic;
+    signal mdout1_0_4: std_logic;
+    signal mdout1_15_5: std_logic;
+    signal mdout1_14_5: std_logic;
+    signal mdout1_13_5: std_logic;
+    signal mdout1_12_5: std_logic;
+    signal mdout1_11_5: std_logic;
+    signal mdout1_10_5: std_logic;
+    signal mdout1_9_5: std_logic;
+    signal mdout1_8_5: std_logic;
+    signal mdout1_7_5: std_logic;
+    signal mdout1_6_5: std_logic;
+    signal mdout1_5_5: std_logic;
+    signal mdout1_4_5: std_logic;
+    signal mdout1_3_5: std_logic;
+    signal mdout1_2_5: std_logic;
+    signal mdout1_1_5: std_logic;
+    signal mdout1_0_5: std_logic;
+    signal mdout1_15_6: std_logic;
+    signal mdout1_14_6: std_logic;
+    signal mdout1_13_6: std_logic;
+    signal mdout1_12_6: std_logic;
+    signal mdout1_11_6: std_logic;
+    signal mdout1_10_6: std_logic;
+    signal mdout1_9_6: std_logic;
+    signal mdout1_8_6: std_logic;
+    signal mdout1_7_6: std_logic;
+    signal mdout1_6_6: std_logic;
+    signal mdout1_5_6: std_logic;
+    signal mdout1_4_6: std_logic;
+    signal mdout1_3_6: std_logic;
+    signal mdout1_2_6: std_logic;
+    signal mdout1_1_6: std_logic;
+    signal mdout1_0_6: std_logic;
+    signal mdout1_15_7: std_logic;
+    signal mdout1_14_7: std_logic;
+    signal mdout1_13_7: std_logic;
+    signal mdout1_12_7: std_logic;
+    signal mdout1_11_7: std_logic;
+    signal mdout1_10_7: std_logic;
+    signal mdout1_9_7: std_logic;
+    signal mdout1_8_7: std_logic;
+    signal mdout1_7_7: std_logic;
+    signal mdout1_6_7: std_logic;
+    signal mdout1_5_7: std_logic;
+    signal mdout1_4_7: std_logic;
+    signal mdout1_3_7: std_logic;
+    signal mdout1_2_7: std_logic;
+    signal mdout1_1_7: std_logic;
+    signal mdout1_0_7: std_logic;
+    signal mdout1_15_8: std_logic;
+    signal mdout1_14_8: std_logic;
+    signal mdout1_13_8: std_logic;
+    signal mdout1_12_8: std_logic;
+    signal mdout1_11_8: std_logic;
+    signal mdout1_10_8: std_logic;
+    signal mdout1_9_8: std_logic;
+    signal mdout1_8_8: std_logic;
+    signal mdout1_7_8: std_logic;
+    signal mdout1_6_8: std_logic;
+    signal mdout1_5_8: std_logic;
+    signal mdout1_4_8: std_logic;
+    signal mdout1_3_8: std_logic;
+    signal mdout1_2_8: std_logic;
+    signal mdout1_1_8: std_logic;
+    signal mdout1_0_8: std_logic;
+    signal mdout1_15_9: std_logic;
+    signal mdout1_14_9: std_logic;
+    signal mdout1_13_9: std_logic;
+    signal mdout1_12_9: std_logic;
+    signal mdout1_11_9: std_logic;
+    signal mdout1_10_9: std_logic;
+    signal mdout1_9_9: std_logic;
+    signal mdout1_8_9: std_logic;
+    signal mdout1_7_9: std_logic;
+    signal mdout1_6_9: std_logic;
+    signal mdout1_5_9: std_logic;
+    signal mdout1_4_9: std_logic;
+    signal mdout1_3_9: std_logic;
+    signal mdout1_2_9: std_logic;
+    signal mdout1_1_9: std_logic;
+    signal mdout1_0_9: std_logic;
+    signal mdout1_15_10: std_logic;
+    signal mdout1_14_10: std_logic;
+    signal mdout1_13_10: std_logic;
+    signal mdout1_12_10: std_logic;
+    signal mdout1_11_10: std_logic;
+    signal mdout1_10_10: std_logic;
+    signal mdout1_9_10: std_logic;
+    signal mdout1_8_10: std_logic;
+    signal mdout1_7_10: std_logic;
+    signal mdout1_6_10: std_logic;
+    signal mdout1_5_10: std_logic;
+    signal mdout1_4_10: std_logic;
+    signal mdout1_3_10: std_logic;
+    signal mdout1_2_10: std_logic;
+    signal mdout1_1_10: std_logic;
+    signal mdout1_0_10: std_logic;
+    signal mdout1_15_11: std_logic;
+    signal mdout1_14_11: std_logic;
+    signal mdout1_13_11: std_logic;
+    signal mdout1_12_11: std_logic;
+    signal mdout1_11_11: std_logic;
+    signal mdout1_10_11: std_logic;
+    signal mdout1_9_11: std_logic;
+    signal mdout1_8_11: std_logic;
+    signal mdout1_7_11: std_logic;
+    signal mdout1_6_11: std_logic;
+    signal mdout1_5_11: std_logic;
+    signal mdout1_4_11: std_logic;
+    signal mdout1_3_11: std_logic;
+    signal mdout1_2_11: std_logic;
+    signal mdout1_1_11: std_logic;
+    signal mdout1_0_11: std_logic;
+    signal mdout1_15_12: std_logic;
+    signal mdout1_14_12: std_logic;
+    signal mdout1_13_12: std_logic;
+    signal mdout1_12_12: std_logic;
+    signal mdout1_11_12: std_logic;
+    signal mdout1_10_12: std_logic;
+    signal mdout1_9_12: std_logic;
+    signal mdout1_8_12: std_logic;
+    signal mdout1_7_12: std_logic;
+    signal mdout1_6_12: std_logic;
+    signal mdout1_5_12: std_logic;
+    signal mdout1_4_12: std_logic;
+    signal mdout1_3_12: std_logic;
+    signal mdout1_2_12: std_logic;
+    signal mdout1_1_12: std_logic;
+    signal mdout1_0_12: std_logic;
+    signal mdout1_15_13: std_logic;
+    signal mdout1_14_13: std_logic;
+    signal mdout1_13_13: std_logic;
+    signal mdout1_12_13: std_logic;
+    signal mdout1_11_13: std_logic;
+    signal mdout1_10_13: std_logic;
+    signal mdout1_9_13: std_logic;
+    signal mdout1_8_13: std_logic;
+    signal mdout1_7_13: std_logic;
+    signal mdout1_6_13: std_logic;
+    signal mdout1_5_13: std_logic;
+    signal mdout1_4_13: std_logic;
+    signal mdout1_3_13: std_logic;
+    signal mdout1_2_13: std_logic;
+    signal mdout1_1_13: std_logic;
+    signal mdout1_0_13: std_logic;
+    signal mdout1_15_14: std_logic;
+    signal mdout1_14_14: std_logic;
+    signal mdout1_13_14: std_logic;
+    signal mdout1_12_14: std_logic;
+    signal mdout1_11_14: std_logic;
+    signal mdout1_10_14: std_logic;
+    signal mdout1_9_14: std_logic;
+    signal mdout1_8_14: std_logic;
+    signal mdout1_7_14: std_logic;
+    signal mdout1_6_14: std_logic;
+    signal mdout1_5_14: std_logic;
+    signal mdout1_4_14: std_logic;
+    signal mdout1_3_14: std_logic;
+    signal mdout1_2_14: std_logic;
+    signal mdout1_1_14: std_logic;
+    signal mdout1_0_14: std_logic;
+    signal mdout1_15_15: std_logic;
+    signal mdout1_14_15: std_logic;
+    signal mdout1_13_15: std_logic;
+    signal mdout1_12_15: std_logic;
+    signal mdout1_11_15: std_logic;
+    signal mdout1_10_15: std_logic;
+    signal mdout1_9_15: std_logic;
+    signal mdout1_8_15: std_logic;
+    signal mdout1_7_15: std_logic;
+    signal mdout1_6_15: std_logic;
+    signal mdout1_5_15: std_logic;
+    signal mdout1_4_15: std_logic;
+    signal mdout1_3_15: std_logic;
+    signal mdout1_2_15: std_logic;
+    signal mdout1_1_15: std_logic;
+    signal mdout1_0_15: std_logic;
+    signal mdout1_15_16: std_logic;
+    signal mdout1_14_16: std_logic;
+    signal mdout1_13_16: std_logic;
+    signal mdout1_12_16: std_logic;
+    signal mdout1_11_16: std_logic;
+    signal mdout1_10_16: std_logic;
+    signal mdout1_9_16: std_logic;
+    signal mdout1_8_16: std_logic;
+    signal mdout1_7_16: std_logic;
+    signal mdout1_6_16: std_logic;
+    signal mdout1_5_16: std_logic;
+    signal mdout1_4_16: std_logic;
+    signal mdout1_3_16: std_logic;
+    signal mdout1_2_16: std_logic;
+    signal mdout1_1_16: std_logic;
+    signal mdout1_0_16: std_logic;
+    signal mdout1_15_17: std_logic;
+    signal mdout1_14_17: std_logic;
+    signal mdout1_13_17: std_logic;
+    signal mdout1_12_17: std_logic;
+    signal mdout1_11_17: std_logic;
+    signal mdout1_10_17: std_logic;
+    signal mdout1_9_17: std_logic;
+    signal mdout1_8_17: std_logic;
+    signal mdout1_7_17: std_logic;
+    signal mdout1_6_17: std_logic;
+    signal mdout1_5_17: std_logic;
+    signal mdout1_4_17: std_logic;
+    signal mdout1_3_17: std_logic;
+    signal mdout1_2_17: std_logic;
+    signal mdout1_1_17: std_logic;
+    signal mdout1_0_17: std_logic;
+    signal mdout1_15_18: std_logic;
+    signal mdout1_14_18: std_logic;
+    signal mdout1_13_18: std_logic;
+    signal mdout1_12_18: std_logic;
+    signal mdout1_11_18: std_logic;
+    signal mdout1_10_18: std_logic;
+    signal mdout1_9_18: std_logic;
+    signal mdout1_8_18: std_logic;
+    signal mdout1_7_18: std_logic;
+    signal mdout1_6_18: std_logic;
+    signal mdout1_5_18: std_logic;
+    signal mdout1_4_18: std_logic;
+    signal mdout1_3_18: std_logic;
+    signal mdout1_2_18: std_logic;
+    signal mdout1_1_18: std_logic;
+    signal mdout1_0_18: std_logic;
+    signal mdout1_15_19: std_logic;
+    signal mdout1_14_19: std_logic;
+    signal mdout1_13_19: std_logic;
+    signal mdout1_12_19: std_logic;
+    signal mdout1_11_19: std_logic;
+    signal mdout1_10_19: std_logic;
+    signal mdout1_9_19: std_logic;
+    signal mdout1_8_19: std_logic;
+    signal mdout1_7_19: std_logic;
+    signal mdout1_6_19: std_logic;
+    signal mdout1_5_19: std_logic;
+    signal mdout1_4_19: std_logic;
+    signal mdout1_3_19: std_logic;
+    signal mdout1_2_19: std_logic;
+    signal mdout1_1_19: std_logic;
+    signal mdout1_0_19: std_logic;
+    signal mdout1_15_20: std_logic;
+    signal mdout1_14_20: std_logic;
+    signal mdout1_13_20: std_logic;
+    signal mdout1_12_20: std_logic;
+    signal mdout1_11_20: std_logic;
+    signal mdout1_10_20: std_logic;
+    signal mdout1_9_20: std_logic;
+    signal mdout1_8_20: std_logic;
+    signal mdout1_7_20: std_logic;
+    signal mdout1_6_20: std_logic;
+    signal mdout1_5_20: std_logic;
+    signal mdout1_4_20: std_logic;
+    signal mdout1_3_20: std_logic;
+    signal mdout1_2_20: std_logic;
+    signal mdout1_1_20: std_logic;
+    signal mdout1_0_20: std_logic;
+    signal mdout1_15_21: std_logic;
+    signal mdout1_14_21: std_logic;
+    signal mdout1_13_21: std_logic;
+    signal mdout1_12_21: std_logic;
+    signal mdout1_11_21: std_logic;
+    signal mdout1_10_21: std_logic;
+    signal mdout1_9_21: std_logic;
+    signal mdout1_8_21: std_logic;
+    signal mdout1_7_21: std_logic;
+    signal mdout1_6_21: std_logic;
+    signal mdout1_5_21: std_logic;
+    signal mdout1_4_21: std_logic;
+    signal mdout1_3_21: std_logic;
+    signal mdout1_2_21: std_logic;
+    signal mdout1_1_21: std_logic;
+    signal mdout1_0_21: std_logic;
+    signal mdout1_15_22: std_logic;
+    signal mdout1_14_22: std_logic;
+    signal mdout1_13_22: std_logic;
+    signal mdout1_12_22: std_logic;
+    signal mdout1_11_22: std_logic;
+    signal mdout1_10_22: std_logic;
+    signal mdout1_9_22: std_logic;
+    signal mdout1_8_22: std_logic;
+    signal mdout1_7_22: std_logic;
+    signal mdout1_6_22: std_logic;
+    signal mdout1_5_22: std_logic;
+    signal mdout1_4_22: std_logic;
+    signal mdout1_3_22: std_logic;
+    signal mdout1_2_22: std_logic;
+    signal mdout1_1_22: std_logic;
+    signal mdout1_0_22: std_logic;
+    signal mdout1_15_23: std_logic;
+    signal mdout1_14_23: std_logic;
+    signal mdout1_13_23: std_logic;
+    signal mdout1_12_23: std_logic;
+    signal mdout1_11_23: std_logic;
+    signal mdout1_10_23: std_logic;
+    signal mdout1_9_23: std_logic;
+    signal mdout1_8_23: std_logic;
+    signal mdout1_7_23: std_logic;
+    signal mdout1_6_23: std_logic;
+    signal mdout1_5_23: std_logic;
+    signal mdout1_4_23: std_logic;
+    signal mdout1_3_23: std_logic;
+    signal mdout1_2_23: std_logic;
+    signal mdout1_1_23: std_logic;
+    signal mdout1_0_23: std_logic;
+    signal mdout1_15_24: std_logic;
+    signal mdout1_14_24: std_logic;
+    signal mdout1_13_24: std_logic;
+    signal mdout1_12_24: std_logic;
+    signal mdout1_11_24: std_logic;
+    signal mdout1_10_24: std_logic;
+    signal mdout1_9_24: std_logic;
+    signal mdout1_8_24: std_logic;
+    signal mdout1_7_24: std_logic;
+    signal mdout1_6_24: std_logic;
+    signal mdout1_5_24: std_logic;
+    signal mdout1_4_24: std_logic;
+    signal mdout1_3_24: std_logic;
+    signal mdout1_2_24: std_logic;
+    signal mdout1_1_24: std_logic;
+    signal mdout1_0_24: std_logic;
+    signal mdout1_15_25: std_logic;
+    signal mdout1_14_25: std_logic;
+    signal mdout1_13_25: std_logic;
+    signal mdout1_12_25: std_logic;
+    signal mdout1_11_25: std_logic;
+    signal mdout1_10_25: std_logic;
+    signal mdout1_9_25: std_logic;
+    signal mdout1_8_25: std_logic;
+    signal mdout1_7_25: std_logic;
+    signal mdout1_6_25: std_logic;
+    signal mdout1_5_25: std_logic;
+    signal mdout1_4_25: std_logic;
+    signal mdout1_3_25: std_logic;
+    signal mdout1_2_25: std_logic;
+    signal mdout1_1_25: std_logic;
+    signal mdout1_0_25: std_logic;
+    signal mdout1_15_26: std_logic;
+    signal mdout1_14_26: std_logic;
+    signal mdout1_13_26: std_logic;
+    signal mdout1_12_26: std_logic;
+    signal mdout1_11_26: std_logic;
+    signal mdout1_10_26: std_logic;
+    signal mdout1_9_26: std_logic;
+    signal mdout1_8_26: std_logic;
+    signal mdout1_7_26: std_logic;
+    signal mdout1_6_26: std_logic;
+    signal mdout1_5_26: std_logic;
+    signal mdout1_4_26: std_logic;
+    signal mdout1_3_26: std_logic;
+    signal mdout1_2_26: std_logic;
+    signal mdout1_1_26: std_logic;
+    signal mdout1_0_26: std_logic;
+    signal mdout1_15_27: std_logic;
+    signal mdout1_14_27: std_logic;
+    signal mdout1_13_27: std_logic;
+    signal mdout1_12_27: std_logic;
+    signal mdout1_11_27: std_logic;
+    signal mdout1_10_27: std_logic;
+    signal mdout1_9_27: std_logic;
+    signal mdout1_8_27: std_logic;
+    signal mdout1_7_27: std_logic;
+    signal mdout1_6_27: std_logic;
+    signal mdout1_5_27: std_logic;
+    signal mdout1_4_27: std_logic;
+    signal mdout1_3_27: std_logic;
+    signal mdout1_2_27: std_logic;
+    signal mdout1_1_27: std_logic;
+    signal mdout1_0_27: std_logic;
+    signal mdout1_15_28: std_logic;
+    signal mdout1_14_28: std_logic;
+    signal mdout1_13_28: std_logic;
+    signal mdout1_12_28: std_logic;
+    signal mdout1_11_28: std_logic;
+    signal mdout1_10_28: std_logic;
+    signal mdout1_9_28: std_logic;
+    signal mdout1_8_28: std_logic;
+    signal mdout1_7_28: std_logic;
+    signal mdout1_6_28: std_logic;
+    signal mdout1_5_28: std_logic;
+    signal mdout1_4_28: std_logic;
+    signal mdout1_3_28: std_logic;
+    signal mdout1_2_28: std_logic;
+    signal mdout1_1_28: std_logic;
+    signal mdout1_0_28: std_logic;
+    signal mdout1_15_29: std_logic;
+    signal mdout1_14_29: std_logic;
+    signal mdout1_13_29: std_logic;
+    signal mdout1_12_29: std_logic;
+    signal mdout1_11_29: std_logic;
+    signal mdout1_10_29: std_logic;
+    signal mdout1_9_29: std_logic;
+    signal mdout1_8_29: std_logic;
+    signal mdout1_7_29: std_logic;
+    signal mdout1_6_29: std_logic;
+    signal mdout1_5_29: std_logic;
+    signal mdout1_4_29: std_logic;
+    signal mdout1_3_29: std_logic;
+    signal mdout1_2_29: std_logic;
+    signal mdout1_1_29: std_logic;
+    signal mdout1_0_29: std_logic;
+    signal mdout1_15_30: std_logic;
+    signal mdout1_14_30: std_logic;
+    signal mdout1_13_30: std_logic;
+    signal mdout1_12_30: std_logic;
+    signal mdout1_11_30: std_logic;
+    signal mdout1_10_30: std_logic;
+    signal mdout1_9_30: std_logic;
+    signal mdout1_8_30: std_logic;
+    signal mdout1_7_30: std_logic;
+    signal mdout1_6_30: std_logic;
+    signal mdout1_5_30: std_logic;
+    signal mdout1_4_30: std_logic;
+    signal mdout1_3_30: std_logic;
+    signal mdout1_2_30: std_logic;
+    signal mdout1_1_30: std_logic;
+    signal mdout1_0_30: std_logic;
+    signal mdout1_15_31: std_logic;
+    signal mdout1_14_31: std_logic;
+    signal mdout1_13_31: std_logic;
+    signal mdout1_12_31: std_logic;
+    signal mdout1_11_31: std_logic;
+    signal mdout1_10_31: std_logic;
+    signal mdout1_9_31: std_logic;
+    signal mdout1_8_31: std_logic;
+    signal mdout1_7_31: std_logic;
+    signal mdout1_6_31: std_logic;
+    signal mdout1_5_31: std_logic;
+    signal mdout1_4_31: std_logic;
+    signal mdout1_3_31: std_logic;
+    signal mdout1_2_31: std_logic;
+    signal mdout1_1_31: std_logic;
+    signal mdout1_0_31: std_logic;
+    signal mdout1_15_32: std_logic;
+    signal mdout1_14_32: std_logic;
+    signal mdout1_13_32: std_logic;
+    signal mdout1_12_32: std_logic;
+    signal mdout1_11_32: std_logic;
+    signal mdout1_10_32: std_logic;
+    signal mdout1_9_32: std_logic;
+    signal mdout1_8_32: std_logic;
+    signal mdout1_7_32: std_logic;
+    signal mdout1_6_32: std_logic;
+    signal mdout1_5_32: std_logic;
+    signal mdout1_4_32: std_logic;
+    signal mdout1_3_32: std_logic;
+    signal mdout1_2_32: std_logic;
+    signal mdout1_1_32: std_logic;
+    signal mdout1_0_32: std_logic;
+    signal mdout1_15_33: std_logic;
+    signal mdout1_14_33: std_logic;
+    signal mdout1_13_33: std_logic;
+    signal mdout1_12_33: std_logic;
+    signal mdout1_11_33: std_logic;
+    signal mdout1_10_33: std_logic;
+    signal mdout1_9_33: std_logic;
+    signal mdout1_8_33: std_logic;
+    signal mdout1_7_33: std_logic;
+    signal mdout1_6_33: std_logic;
+    signal mdout1_5_33: std_logic;
+    signal mdout1_4_33: std_logic;
+    signal mdout1_3_33: std_logic;
+    signal mdout1_2_33: std_logic;
+    signal mdout1_1_33: std_logic;
+    signal mdout1_0_33: std_logic;
+    signal mdout1_15_34: std_logic;
+    signal mdout1_14_34: std_logic;
+    signal mdout1_13_34: std_logic;
+    signal mdout1_12_34: std_logic;
+    signal mdout1_11_34: std_logic;
+    signal mdout1_10_34: std_logic;
+    signal mdout1_9_34: std_logic;
+    signal mdout1_8_34: std_logic;
+    signal mdout1_7_34: std_logic;
+    signal mdout1_6_34: std_logic;
+    signal mdout1_5_34: std_logic;
+    signal mdout1_4_34: std_logic;
+    signal mdout1_3_34: std_logic;
+    signal mdout1_2_34: std_logic;
+    signal mdout1_1_34: std_logic;
+    signal mdout1_0_34: std_logic;
+    signal rptr_14_ff2: std_logic;
+    signal rptr_13_ff2: std_logic;
+    signal rptr_12_ff2: std_logic;
+    signal rptr_11_ff2: std_logic;
+    signal mdout1_15_35: std_logic;
+    signal mdout1_14_35: std_logic;
+    signal mdout1_13_35: std_logic;
+    signal mdout1_12_35: std_logic;
+    signal mdout1_11_35: std_logic;
+    signal mdout1_10_35: std_logic;
+    signal mdout1_9_35: std_logic;
+    signal mdout1_8_35: std_logic;
+    signal mdout1_7_35: std_logic;
+    signal mdout1_6_35: std_logic;
+    signal mdout1_5_35: std_logic;
+    signal mdout1_4_35: std_logic;
+    signal mdout1_3_35: std_logic;
+    signal mdout1_2_35: std_logic;
+    signal mdout1_1_35: std_logic;
+    signal mdout1_0_35: std_logic;
+    signal wcnt_sub_0: std_logic;
+    signal rptr_0: std_logic;
+    signal cnt_con_inv: std_logic;
+    signal wcount_0: std_logic;
+    signal cnt_con: std_logic;
+    signal precin: std_logic;
+    signal wcnt_sub_1: std_logic;
+    signal wcnt_sub_2: std_logic;
+    signal rptr_2: std_logic;
+    signal rptr_1: std_logic;
+    signal wcount_2: std_logic;
+    signal wcount_1: std_logic;
+    signal co0_5: std_logic;
+    signal wcnt_sub_3: std_logic;
+    signal wcnt_sub_4: std_logic;
+    signal rptr_4: std_logic;
+    signal rptr_3: std_logic;
+    signal wcount_4: std_logic;
+    signal wcount_3: std_logic;
+    signal co1_5: std_logic;
+    signal wcnt_sub_5: std_logic;
+    signal wcnt_sub_6: std_logic;
+    signal rptr_6: std_logic;
+    signal rptr_5: std_logic;
+    signal wcount_6: std_logic;
+    signal wcount_5: std_logic;
+    signal co2_5: std_logic;
+    signal wcnt_sub_7: std_logic;
+    signal wcnt_sub_8: std_logic;
+    signal rptr_8: std_logic;
+    signal rptr_7: std_logic;
+    signal wcount_8: std_logic;
+    signal wcount_7: std_logic;
+    signal co3_5: std_logic;
+    signal wcnt_sub_9: std_logic;
+    signal wcnt_sub_10: std_logic;
+    signal rptr_10: std_logic;
+    signal rptr_9: std_logic;
+    signal wcount_10: std_logic;
+    signal wcount_9: std_logic;
+    signal co4_5: std_logic;
+    signal wcnt_sub_11: std_logic;
+    signal wcnt_sub_12: std_logic;
+    signal rptr_12: std_logic;
+    signal rptr_11: std_logic;
+    signal wcount_12: std_logic;
+    signal wcount_11: std_logic;
+    signal co5_5: std_logic;
+    signal wcnt_sub_13: std_logic;
+    signal wcnt_sub_14: std_logic;
+    signal rptr_14: std_logic;
+    signal rptr_13: std_logic;
+    signal wcount_14: std_logic;
+    signal wcount_13: std_logic;
+    signal co6_5: std_logic;
+    signal wcnt_sub_15: std_logic;
+    signal wcnt_sub_msb: std_logic;
+    signal co7_3: std_logic;
+    signal wren_i: std_logic;
+    signal cmp_ci_2: std_logic;
+    signal wcnt_reg_0: std_logic;
+    signal wcnt_reg_1: std_logic;
+    signal co0_6: std_logic;
+    signal wcnt_reg_2: std_logic;
+    signal wcnt_reg_3: std_logic;
+    signal co1_6: std_logic;
+    signal wcnt_reg_4: std_logic;
+    signal wcnt_reg_5: std_logic;
+    signal co2_6: std_logic;
+    signal wcnt_reg_6: std_logic;
+    signal wcnt_reg_7: std_logic;
+    signal co3_6: std_logic;
+    signal wcnt_reg_8: std_logic;
+    signal wcnt_reg_9: std_logic;
+    signal co4_6: std_logic;
+    signal wcnt_reg_10: std_logic;
+    signal wcnt_reg_11: std_logic;
+    signal co5_6: std_logic;
+    signal wcnt_reg_12: std_logic;
+    signal wcnt_reg_13: std_logic;
+    signal co6_6: std_logic;
+    signal wcnt_reg_14: std_logic;
+    signal wcnt_reg_15: std_logic;
+    signal af_set: std_logic;
+    signal scuba_vhi: std_logic;
+    signal scuba_vlo: std_logic;
+    signal af_set_c: std_logic;
+
+    attribute MEM_LPC_FILE : string; 
+    attribute MEM_INIT_FILE : string; 
+    attribute GSR : string; 
+    attribute MEM_LPC_FILE of pdp_ram_0_0_63 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_0_63 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_0_1_62 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_1_62 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_0_2_61 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_2_61 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_0_3_60 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_3_60 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_1_0_59 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_1_0_59 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_1_1_58 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_1_1_58 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_1_2_57 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_1_2_57 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_1_3_56 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_1_3_56 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_2_0_55 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_2_0_55 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_2_1_54 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_2_1_54 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_2_2_53 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_2_2_53 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_2_3_52 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_2_3_52 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_3_0_51 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_3_0_51 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_3_1_50 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_3_1_50 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_3_2_49 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_3_2_49 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_3_3_48 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_3_3_48 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_4_0_47 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_4_0_47 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_4_1_46 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_4_1_46 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_4_2_45 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_4_2_45 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_4_3_44 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_4_3_44 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_5_0_43 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_5_0_43 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_5_1_42 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_5_1_42 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_5_2_41 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_5_2_41 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_5_3_40 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_5_3_40 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_6_0_39 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_6_0_39 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_6_1_38 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_6_1_38 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_6_2_37 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_6_2_37 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_6_3_36 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_6_3_36 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_7_0_35 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_7_0_35 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_7_1_34 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_7_1_34 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_7_2_33 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_7_2_33 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_7_3_32 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_7_3_32 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_8_0_31 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_8_0_31 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_8_1_30 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_8_1_30 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_8_2_29 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_8_2_29 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_8_3_28 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_8_3_28 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_9_0_27 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_9_0_27 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_9_1_26 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_9_1_26 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_9_2_25 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_9_2_25 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_9_3_24 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_9_3_24 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_10_0_23 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_10_0_23 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_10_1_22 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_10_1_22 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_10_2_21 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_10_2_21 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_10_3_20 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_10_3_20 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_11_0_19 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_11_0_19 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_11_1_18 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_11_1_18 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_11_2_17 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_11_2_17 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_11_3_16 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_11_3_16 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_12_0_15 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_12_0_15 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_12_1_14 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_12_1_14 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_12_2_13 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_12_2_13 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_12_3_12 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_12_3_12 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_13_0_11 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_13_0_11 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_13_1_10 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_13_1_10 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_13_2_9 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_13_2_9 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_13_3_8 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_13_3_8 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_14_0_7 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_14_0_7 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_14_1_6 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_14_1_6 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_14_2_5 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_14_2_5 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_14_3_4 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_14_3_4 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_15_0_3 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_15_0_3 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_15_1_2 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_15_1_2 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_15_2_1 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_15_2_1 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_15_3_0 : label is "fifo_36x32k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_15_3_0 : label is "";
+    attribute GSR of FF_106 : label is "ENABLED";
+    attribute GSR of FF_105 : label is "ENABLED";
+    attribute GSR of FF_104 : label is "ENABLED";
+    attribute GSR of FF_103 : label is "ENABLED";
+    attribute GSR of FF_102 : label is "ENABLED";
+    attribute GSR of FF_101 : label is "ENABLED";
+    attribute GSR of FF_100 : label is "ENABLED";
+    attribute GSR of FF_99 : label is "ENABLED";
+    attribute GSR of FF_98 : label is "ENABLED";
+    attribute GSR of FF_97 : label is "ENABLED";
+    attribute GSR of FF_96 : label is "ENABLED";
+    attribute GSR of FF_95 : label is "ENABLED";
+    attribute GSR of FF_94 : label is "ENABLED";
+    attribute GSR of FF_93 : label is "ENABLED";
+    attribute GSR of FF_92 : label is "ENABLED";
+    attribute GSR of FF_91 : label is "ENABLED";
+    attribute GSR of FF_90 : label is "ENABLED";
+    attribute GSR of FF_89 : label is "ENABLED";
+    attribute GSR of FF_88 : label is "ENABLED";
+    attribute GSR of FF_87 : label is "ENABLED";
+    attribute GSR of FF_86 : label is "ENABLED";
+    attribute GSR of FF_85 : label is "ENABLED";
+    attribute GSR of FF_84 : label is "ENABLED";
+    attribute GSR of FF_83 : label is "ENABLED";
+    attribute GSR of FF_82 : label is "ENABLED";
+    attribute GSR of FF_81 : label is "ENABLED";
+    attribute GSR of FF_80 : label is "ENABLED";
+    attribute GSR of FF_79 : label is "ENABLED";
+    attribute GSR of FF_78 : label is "ENABLED";
+    attribute GSR of FF_77 : label is "ENABLED";
+    attribute GSR of FF_76 : label is "ENABLED";
+    attribute GSR of FF_75 : label is "ENABLED";
+    attribute GSR of FF_74 : label is "ENABLED";
+    attribute GSR of FF_73 : label is "ENABLED";
+    attribute GSR of FF_72 : label is "ENABLED";
+    attribute GSR of FF_71 : label is "ENABLED";
+    attribute GSR of FF_70 : label is "ENABLED";
+    attribute GSR of FF_69 : label is "ENABLED";
+    attribute GSR of FF_68 : label is "ENABLED";
+    attribute GSR of FF_67 : label is "ENABLED";
+    attribute GSR of FF_66 : label is "ENABLED";
+    attribute GSR of FF_65 : label is "ENABLED";
+    attribute GSR of FF_64 : label is "ENABLED";
+    attribute GSR of FF_63 : label is "ENABLED";
+    attribute GSR of FF_62 : label is "ENABLED";
+    attribute GSR of FF_61 : label is "ENABLED";
+    attribute GSR of FF_60 : label is "ENABLED";
+    attribute GSR of FF_59 : label is "ENABLED";
+    attribute GSR of FF_58 : label is "ENABLED";
+    attribute GSR of FF_57 : label is "ENABLED";
+    attribute GSR of FF_56 : label is "ENABLED";
+    attribute GSR of FF_55 : label is "ENABLED";
+    attribute GSR of FF_54 : label is "ENABLED";
+    attribute GSR of FF_53 : label is "ENABLED";
+    attribute GSR of FF_52 : label is "ENABLED";
+    attribute GSR of FF_51 : label is "ENABLED";
+    attribute GSR of FF_50 : label is "ENABLED";
+    attribute GSR of FF_49 : label is "ENABLED";
+    attribute GSR of FF_48 : label is "ENABLED";
+    attribute GSR of FF_47 : label is "ENABLED";
+    attribute GSR of FF_46 : label is "ENABLED";
+    attribute GSR of FF_45 : label is "ENABLED";
+    attribute GSR of FF_44 : label is "ENABLED";
+    attribute GSR of FF_43 : label is "ENABLED";
+    attribute GSR of FF_42 : label is "ENABLED";
+    attribute GSR of FF_41 : label is "ENABLED";
+    attribute GSR of FF_40 : label is "ENABLED";
+    attribute GSR of FF_39 : label is "ENABLED";
+    attribute GSR of FF_38 : label is "ENABLED";
+    attribute GSR of FF_37 : label is "ENABLED";
+    attribute GSR of FF_36 : label is "ENABLED";
+    attribute GSR of FF_35 : label is "ENABLED";
+    attribute GSR of FF_34 : label is "ENABLED";
+    attribute GSR of FF_33 : label is "ENABLED";
+    attribute GSR of FF_32 : label is "ENABLED";
+    attribute GSR of FF_31 : label is "ENABLED";
+    attribute GSR of FF_30 : label is "ENABLED";
+    attribute GSR of FF_29 : label is "ENABLED";
+    attribute GSR of FF_28 : label is "ENABLED";
+    attribute GSR of FF_27 : label is "ENABLED";
+    attribute GSR of FF_26 : label is "ENABLED";
+    attribute GSR of FF_25 : label is "ENABLED";
+    attribute GSR of FF_24 : label is "ENABLED";
+    attribute GSR of FF_23 : label is "ENABLED";
+    attribute GSR of FF_22 : label is "ENABLED";
+    attribute GSR of FF_21 : label is "ENABLED";
+    attribute GSR of FF_20 : label is "ENABLED";
+    attribute GSR of FF_19 : label is "ENABLED";
+    attribute GSR of FF_18 : label is "ENABLED";
+    attribute GSR of FF_17 : label is "ENABLED";
+    attribute GSR of FF_16 : label is "ENABLED";
+    attribute GSR of FF_15 : label is "ENABLED";
+    attribute GSR of FF_14 : label is "ENABLED";
+    attribute GSR of FF_13 : label is "ENABLED";
+    attribute GSR of FF_12 : label is "ENABLED";
+    attribute GSR of FF_11 : label is "ENABLED";
+    attribute GSR of FF_10 : label is "ENABLED";
+    attribute GSR of FF_9 : label is "ENABLED";
+    attribute GSR of FF_8 : label is "ENABLED";
+    attribute GSR of FF_7 : label is "ENABLED";
+    attribute GSR of FF_6 : label is "ENABLED";
+    attribute GSR of FF_5 : label is "ENABLED";
+    attribute GSR of FF_4 : label is "ENABLED";
+    attribute GSR of FF_3 : label is "ENABLED";
+    attribute GSR of FF_2 : label is "ENABLED";
+    attribute GSR of FF_1 : label is "ENABLED";
+    attribute GSR of FF_0 : label is "ENABLED";
+    attribute syn_keep : boolean;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    AND2_t5: AND2
+        port map (A=>WrEn, B=>invout_2, Z=>wren_i);
+
+    INV_13: INV
+        port map (A=>full_i, Z=>invout_2);
+
+    AND2_t4: AND2
+        port map (A=>RdEn, B=>invout_1, Z=>rden_i);
+
+    INV_12: INV
+        port map (A=>empty_i, Z=>invout_1);
+
+    AND2_t3: AND2
+        port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
+
+    XOR2_t2: XOR2
+        port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
+
+    INV_11: INV
+        port map (A=>rden_i, Z=>rden_i_inv);
+
+    INV_10: INV
+        port map (A=>wren_i, Z=>wren_i_inv);
+
+    LUT4_129: ROM16X1A
+        generic map (initval=> X"3232")
+        port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, 
+            AD0=>empty_i, DO0=>empty_d);
+
+    LUT4_128: ROM16X1A
+        generic map (initval=> X"3232")
+        port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, 
+            AD0=>full_i, DO0=>full_d);
+
+    INV_9: INV
+        port map (A=>wptr_11, Z=>wptr_11_inv);
+
+    INV_8: INV
+        port map (A=>wptr_12, Z=>wptr_12_inv);
+
+    INV_7: INV
+        port map (A=>wptr_13, Z=>wptr_13_inv);
+
+    INV_6: INV
+        port map (A=>wptr_14, Z=>wptr_14_inv);
+
+    LUT4_127: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, 
+            AD0=>wptr_14_inv, DO0=>dec0_p00);
+
+    INV_5: INV
+        port map (A=>rptr_11, Z=>rptr_11_inv);
+
+    INV_4: INV
+        port map (A=>rptr_12, Z=>rptr_12_inv);
+
+    INV_3: INV
+        port map (A=>rptr_13, Z=>rptr_13_inv);
+
+    INV_2: INV
+        port map (A=>rptr_14, Z=>rptr_14_inv);
+
+    LUT4_126: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, 
+            AD0=>rptr_14_inv, DO0=>dec1_r10);
+
+    LUT4_125: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, 
+            AD0=>wptr_14_inv, DO0=>dec2_p00);
+
+    LUT4_124: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, 
+            AD0=>rptr_14_inv, DO0=>dec3_r10);
+
+    LUT4_123: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, 
+            AD0=>wptr_14_inv, DO0=>dec4_p00);
+
+    LUT4_122: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, 
+            AD0=>rptr_14_inv, DO0=>dec5_r10);
+
+    LUT4_121: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, 
+            AD0=>wptr_14_inv, DO0=>dec6_p00);
+
+    LUT4_120: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, 
+            AD0=>rptr_14_inv, DO0=>dec7_r10);
+
+    LUT4_119: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, 
+            AD0=>wptr_14_inv, DO0=>dec8_p01);
+
+    LUT4_118: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, 
+            AD0=>rptr_14_inv, DO0=>dec9_r11);
+
+    LUT4_117: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, 
+            AD0=>wptr_14_inv, DO0=>dec10_p01);
+
+    LUT4_116: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, 
+            AD0=>rptr_14_inv, DO0=>dec11_r11);
+
+    LUT4_115: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, 
+            AD0=>wptr_14_inv, DO0=>dec12_p01);
+
+    LUT4_114: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, 
+            AD0=>rptr_14_inv, DO0=>dec13_r11);
+
+    LUT4_113: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, 
+            AD0=>wptr_14_inv, DO0=>dec14_p01);
+
+    LUT4_112: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, 
+            AD0=>rptr_14_inv, DO0=>dec15_r11);
+
+    LUT4_111: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, 
+            AD0=>wptr_14_inv, DO0=>dec16_p02);
+
+    LUT4_110: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, 
+            AD0=>rptr_14_inv, DO0=>dec17_r12);
+
+    LUT4_109: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, 
+            AD0=>wptr_14_inv, DO0=>dec18_p02);
+
+    LUT4_108: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, 
+            AD0=>rptr_14_inv, DO0=>dec19_r12);
+
+    LUT4_107: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, 
+            AD0=>wptr_14_inv, DO0=>dec20_p02);
+
+    LUT4_106: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, 
+            AD0=>rptr_14_inv, DO0=>dec21_r12);
+
+    LUT4_105: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, 
+            AD0=>wptr_14_inv, DO0=>dec22_p02);
+
+    LUT4_104: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, 
+            AD0=>rptr_14_inv, DO0=>dec23_r12);
+
+    LUT4_103: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, 
+            AD0=>wptr_14_inv, DO0=>dec24_p03);
+
+    LUT4_102: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, 
+            AD0=>rptr_14_inv, DO0=>dec25_r13);
+
+    LUT4_101: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, 
+            AD0=>wptr_14_inv, DO0=>dec26_p03);
+
+    LUT4_100: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, 
+            AD0=>rptr_14_inv, DO0=>dec27_r13);
+
+    LUT4_99: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, 
+            AD0=>wptr_14_inv, DO0=>dec28_p03);
+
+    LUT4_98: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, 
+            AD0=>rptr_14_inv, DO0=>dec29_r13);
+
+    LUT4_97: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, 
+            AD0=>wptr_14_inv, DO0=>dec30_p03);
+
+    LUT4_96: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, 
+            AD0=>rptr_14_inv, DO0=>dec31_r13);
+
+    LUT4_95: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, 
+            AD0=>wptr_14_inv, DO0=>dec32_p04);
+
+    LUT4_94: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, 
+            AD0=>rptr_14_inv, DO0=>dec33_r14);
+
+    LUT4_93: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, 
+            AD0=>wptr_14_inv, DO0=>dec34_p04);
+
+    LUT4_92: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, 
+            AD0=>rptr_14_inv, DO0=>dec35_r14);
+
+    LUT4_91: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, 
+            AD0=>wptr_14_inv, DO0=>dec36_p04);
+
+    LUT4_90: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, 
+            AD0=>rptr_14_inv, DO0=>dec37_r14);
+
+    LUT4_89: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, 
+            AD0=>wptr_14_inv, DO0=>dec38_p04);
+
+    LUT4_88: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, 
+            AD0=>rptr_14_inv, DO0=>dec39_r14);
+
+    LUT4_87: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, 
+            AD0=>wptr_14_inv, DO0=>dec40_p05);
+
+    LUT4_86: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, 
+            AD0=>rptr_14_inv, DO0=>dec41_r15);
+
+    LUT4_85: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, 
+            AD0=>wptr_14_inv, DO0=>dec42_p05);
+
+    LUT4_84: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, 
+            AD0=>rptr_14_inv, DO0=>dec43_r15);
+
+    LUT4_83: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, 
+            AD0=>wptr_14_inv, DO0=>dec44_p05);
+
+    LUT4_82: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, 
+            AD0=>rptr_14_inv, DO0=>dec45_r15);
+
+    LUT4_81: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, 
+            AD0=>wptr_14_inv, DO0=>dec46_p05);
+
+    LUT4_80: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, 
+            AD0=>rptr_14_inv, DO0=>dec47_r15);
+
+    LUT4_79: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, 
+            AD0=>wptr_14_inv, DO0=>dec48_p06);
+
+    LUT4_78: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, 
+            AD0=>rptr_14_inv, DO0=>dec49_r16);
+
+    LUT4_77: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, 
+            AD0=>wptr_14_inv, DO0=>dec50_p06);
+
+    LUT4_76: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, 
+            AD0=>rptr_14_inv, DO0=>dec51_r16);
+
+    LUT4_75: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, 
+            AD0=>wptr_14_inv, DO0=>dec52_p06);
+
+    LUT4_74: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, 
+            AD0=>rptr_14_inv, DO0=>dec53_r16);
+
+    LUT4_73: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, 
+            AD0=>wptr_14_inv, DO0=>dec54_p06);
+
+    LUT4_72: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, 
+            AD0=>rptr_14_inv, DO0=>dec55_r16);
+
+    LUT4_71: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, 
+            AD0=>wptr_14_inv, DO0=>dec56_p07);
+
+    LUT4_70: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, 
+            AD0=>rptr_14_inv, DO0=>dec57_r17);
+
+    LUT4_69: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, 
+            AD0=>wptr_14_inv, DO0=>dec58_p07);
+
+    LUT4_68: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, 
+            AD0=>rptr_14_inv, DO0=>dec59_r17);
+
+    LUT4_67: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, 
+            AD0=>wptr_14_inv, DO0=>dec60_p07);
+
+    LUT4_66: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, 
+            AD0=>rptr_14_inv, DO0=>dec61_r17);
+
+    LUT4_65: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, 
+            AD0=>wptr_14_inv, DO0=>dec62_p07);
+
+    LUT4_64: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, 
+            AD0=>rptr_14_inv, DO0=>dec63_r17);
+
+    LUT4_63: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, 
+            AD0=>wptr_14, DO0=>dec64_p08);
+
+    LUT4_62: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, 
+            AD0=>rptr_14, DO0=>dec65_r18);
+
+    LUT4_61: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, 
+            AD0=>wptr_14, DO0=>dec66_p08);
+
+    LUT4_60: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, 
+            AD0=>rptr_14, DO0=>dec67_r18);
+
+    LUT4_59: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, 
+            AD0=>wptr_14, DO0=>dec68_p08);
+
+    LUT4_58: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, 
+            AD0=>rptr_14, DO0=>dec69_r18);
+
+    LUT4_57: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, 
+            AD0=>wptr_14, DO0=>dec70_p08);
+
+    LUT4_56: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, 
+            AD0=>rptr_14, DO0=>dec71_r18);
+
+    LUT4_55: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, 
+            AD0=>wptr_14, DO0=>dec72_p09);
+
+    LUT4_54: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, 
+            AD0=>rptr_14, DO0=>dec73_r19);
+
+    LUT4_53: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, 
+            AD0=>wptr_14, DO0=>dec74_p09);
+
+    LUT4_52: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, 
+            AD0=>rptr_14, DO0=>dec75_r19);
+
+    LUT4_51: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, 
+            AD0=>wptr_14, DO0=>dec76_p09);
+
+    LUT4_50: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, 
+            AD0=>rptr_14, DO0=>dec77_r19);
+
+    LUT4_49: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, 
+            AD0=>wptr_14, DO0=>dec78_p09);
+
+    LUT4_48: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, 
+            AD0=>rptr_14, DO0=>dec79_r19);
+
+    LUT4_47: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, 
+            AD0=>wptr_14, DO0=>dec80_p010);
+
+    LUT4_46: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, 
+            AD0=>rptr_14, DO0=>dec81_r110);
+
+    LUT4_45: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, 
+            AD0=>wptr_14, DO0=>dec82_p010);
+
+    LUT4_44: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, 
+            AD0=>rptr_14, DO0=>dec83_r110);
+
+    LUT4_43: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, 
+            AD0=>wptr_14, DO0=>dec84_p010);
+
+    LUT4_42: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, 
+            AD0=>rptr_14, DO0=>dec85_r110);
+
+    LUT4_41: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, 
+            AD0=>wptr_14, DO0=>dec86_p010);
+
+    LUT4_40: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, 
+            AD0=>rptr_14, DO0=>dec87_r110);
+
+    LUT4_39: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, 
+            AD0=>wptr_14, DO0=>dec88_p011);
+
+    LUT4_38: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, 
+            AD0=>rptr_14, DO0=>dec89_r111);
+
+    LUT4_37: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, 
+            AD0=>wptr_14, DO0=>dec90_p011);
+
+    LUT4_36: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, 
+            AD0=>rptr_14, DO0=>dec91_r111);
+
+    LUT4_35: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, 
+            AD0=>wptr_14, DO0=>dec92_p011);
+
+    LUT4_34: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, 
+            AD0=>rptr_14, DO0=>dec93_r111);
+
+    LUT4_33: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, 
+            AD0=>wptr_14, DO0=>dec94_p011);
+
+    LUT4_32: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, 
+            AD0=>rptr_14, DO0=>dec95_r111);
+
+    LUT4_31: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, 
+            AD0=>wptr_14, DO0=>dec96_p012);
+
+    LUT4_30: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, 
+            AD0=>rptr_14, DO0=>dec97_r112);
+
+    LUT4_29: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, 
+            AD0=>wptr_14, DO0=>dec98_p012);
+
+    LUT4_28: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, 
+            AD0=>rptr_14, DO0=>dec99_r112);
+
+    LUT4_27: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, 
+            AD0=>wptr_14, DO0=>dec100_p012);
+
+    LUT4_26: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, 
+            AD0=>rptr_14, DO0=>dec101_r112);
+
+    LUT4_25: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, 
+            AD0=>wptr_14, DO0=>dec102_p012);
+
+    LUT4_24: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, 
+            AD0=>rptr_14, DO0=>dec103_r112);
+
+    LUT4_23: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, 
+            AD0=>wptr_14, DO0=>dec104_p013);
+
+    LUT4_22: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, 
+            AD0=>rptr_14, DO0=>dec105_r113);
+
+    LUT4_21: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, 
+            AD0=>wptr_14, DO0=>dec106_p013);
+
+    LUT4_20: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, 
+            AD0=>rptr_14, DO0=>dec107_r113);
+
+    LUT4_19: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, 
+            AD0=>wptr_14, DO0=>dec108_p013);
+
+    LUT4_18: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, 
+            AD0=>rptr_14, DO0=>dec109_r113);
+
+    LUT4_17: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, 
+            AD0=>wptr_14, DO0=>dec110_p013);
+
+    LUT4_16: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, 
+            AD0=>rptr_14, DO0=>dec111_r113);
+
+    LUT4_15: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, 
+            AD0=>wptr_14, DO0=>dec112_p014);
+
+    LUT4_14: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, 
+            AD0=>rptr_14, DO0=>dec113_r114);
+
+    LUT4_13: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, 
+            AD0=>wptr_14, DO0=>dec114_p014);
+
+    LUT4_12: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, 
+            AD0=>rptr_14, DO0=>dec115_r114);
+
+    LUT4_11: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, 
+            AD0=>wptr_14, DO0=>dec116_p014);
+
+    LUT4_10: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, 
+            AD0=>rptr_14, DO0=>dec117_r114);
+
+    LUT4_9: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, 
+            AD0=>wptr_14, DO0=>dec118_p014);
+
+    LUT4_8: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, 
+            AD0=>rptr_14, DO0=>dec119_r114);
+
+    LUT4_7: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14, 
+            DO0=>dec120_p015);
+
+    LUT4_6: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, 
+            DO0=>dec121_r115);
+
+    LUT4_5: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14, 
+            DO0=>dec122_p015);
+
+    LUT4_4: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, 
+            DO0=>dec123_r115);
+
+    LUT4_3: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14, 
+            DO0=>dec124_p015);
+
+    LUT4_2: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, 
+            DO0=>dec125_r115);
+
+    LUT4_1: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14, 
+            DO0=>dec126_p015);
+
+    LUT4_0: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, 
+            DO0=>dec127_r115);
+
+    AND2_t1: AND2
+        port map (A=>rden_i, B=>invout_0, Z=>r_nw);
+
+    INV_1: INV
+        port map (A=>wren_i, Z=>invout_0);
+
+    XOR2_t0: XOR2
+        port map (A=>wcount_15, B=>rptr_15, Z=>wcnt_sub_msb);
+
+    INV_0: INV
+        port map (A=>cnt_con, Z=>cnt_con_inv);
+
+    pdp_ram_0_0_63: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), 
+            DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), 
+            DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, 
+            ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, 
+            ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, 
+            ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, 
+            CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, 
+            CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec0_p00, 
+            RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, 
+            DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, 
+            ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, 
+            ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, 
+            ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, 
+            CSB0=>dec1_r10, RSTB=>Reset, DOA17=>open, DOA16=>open, 
+            DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, 
+            DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, 
+            DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, 
+            DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, 
+            DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, 
+            DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_0_8, 
+            DOB7=>mdout1_0_7, DOB6=>mdout1_0_6, DOB5=>mdout1_0_5, 
+            DOB4=>mdout1_0_4, DOB3=>mdout1_0_3, DOB2=>mdout1_0_2, 
+            DOB1=>mdout1_0_1, DOB0=>mdout1_0_0);
+
+    pdp_ram_0_1_62: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), 
+            DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), 
+            DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec2_p00, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec3_r10, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_0_17, 
+            DOB7=>mdout1_0_16, DOB6=>mdout1_0_15, DOB5=>mdout1_0_14, 
+            DOB4=>mdout1_0_13, DOB3=>mdout1_0_12, DOB2=>mdout1_0_11, 
+            DOB1=>mdout1_0_10, DOB0=>mdout1_0_9);
+
+    pdp_ram_0_2_61: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), 
+            DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), 
+            DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec4_p00, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec5_r10, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_0_26, 
+            DOB7=>mdout1_0_25, DOB6=>mdout1_0_24, DOB5=>mdout1_0_23, 
+            DOB4=>mdout1_0_22, DOB3=>mdout1_0_21, DOB2=>mdout1_0_20, 
+            DOB1=>mdout1_0_19, DOB0=>mdout1_0_18);
+
+    pdp_ram_0_3_60: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), 
+            DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), 
+            DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec6_p00, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec7_r10, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_0_35, 
+            DOB7=>mdout1_0_34, DOB6=>mdout1_0_33, DOB5=>mdout1_0_32, 
+            DOB4=>mdout1_0_31, DOB3=>mdout1_0_30, DOB2=>mdout1_0_29, 
+            DOB1=>mdout1_0_28, DOB0=>mdout1_0_27);
+
+    pdp_ram_1_0_59: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), 
+            DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), 
+            DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, 
+            ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, 
+            ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, 
+            ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, 
+            CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, 
+            CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec8_p01, 
+            RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, 
+            DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, 
+            ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, 
+            ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, 
+            ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, 
+            CSB0=>dec9_r11, RSTB=>Reset, DOA17=>open, DOA16=>open, 
+            DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, 
+            DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, 
+            DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, 
+            DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, 
+            DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, 
+            DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_1_8, 
+            DOB7=>mdout1_1_7, DOB6=>mdout1_1_6, DOB5=>mdout1_1_5, 
+            DOB4=>mdout1_1_4, DOB3=>mdout1_1_3, DOB2=>mdout1_1_2, 
+            DOB1=>mdout1_1_1, DOB0=>mdout1_1_0);
+
+    pdp_ram_1_1_58: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), 
+            DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), 
+            DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec10_p01, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec11_r11, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_1_17, 
+            DOB7=>mdout1_1_16, DOB6=>mdout1_1_15, DOB5=>mdout1_1_14, 
+            DOB4=>mdout1_1_13, DOB3=>mdout1_1_12, DOB2=>mdout1_1_11, 
+            DOB1=>mdout1_1_10, DOB0=>mdout1_1_9);
+
+    pdp_ram_1_2_57: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), 
+            DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), 
+            DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec12_p01, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec13_r11, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_1_26, 
+            DOB7=>mdout1_1_25, DOB6=>mdout1_1_24, DOB5=>mdout1_1_23, 
+            DOB4=>mdout1_1_22, DOB3=>mdout1_1_21, DOB2=>mdout1_1_20, 
+            DOB1=>mdout1_1_19, DOB0=>mdout1_1_18);
+
+    pdp_ram_1_3_56: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), 
+            DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), 
+            DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec14_p01, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec15_r11, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_1_35, 
+            DOB7=>mdout1_1_34, DOB6=>mdout1_1_33, DOB5=>mdout1_1_32, 
+            DOB4=>mdout1_1_31, DOB3=>mdout1_1_30, DOB2=>mdout1_1_29, 
+            DOB1=>mdout1_1_28, DOB0=>mdout1_1_27);
+
+    pdp_ram_2_0_55: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), 
+            DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), 
+            DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, 
+            ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, 
+            ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, 
+            ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, 
+            CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, 
+            CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec16_p02, 
+            RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, 
+            DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, 
+            ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, 
+            ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, 
+            ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, 
+            CSB0=>dec17_r12, RSTB=>Reset, DOA17=>open, DOA16=>open, 
+            DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, 
+            DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, 
+            DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, 
+            DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, 
+            DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, 
+            DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_2_8, 
+            DOB7=>mdout1_2_7, DOB6=>mdout1_2_6, DOB5=>mdout1_2_5, 
+            DOB4=>mdout1_2_4, DOB3=>mdout1_2_3, DOB2=>mdout1_2_2, 
+            DOB1=>mdout1_2_1, DOB0=>mdout1_2_0);
+
+    pdp_ram_2_1_54: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), 
+            DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), 
+            DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec18_p02, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec19_r12, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_2_17, 
+            DOB7=>mdout1_2_16, DOB6=>mdout1_2_15, DOB5=>mdout1_2_14, 
+            DOB4=>mdout1_2_13, DOB3=>mdout1_2_12, DOB2=>mdout1_2_11, 
+            DOB1=>mdout1_2_10, DOB0=>mdout1_2_9);
+
+    pdp_ram_2_2_53: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), 
+            DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), 
+            DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec20_p02, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec21_r12, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_2_26, 
+            DOB7=>mdout1_2_25, DOB6=>mdout1_2_24, DOB5=>mdout1_2_23, 
+            DOB4=>mdout1_2_22, DOB3=>mdout1_2_21, DOB2=>mdout1_2_20, 
+            DOB1=>mdout1_2_19, DOB0=>mdout1_2_18);
+
+    pdp_ram_2_3_52: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), 
+            DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), 
+            DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec22_p02, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec23_r12, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_2_35, 
+            DOB7=>mdout1_2_34, DOB6=>mdout1_2_33, DOB5=>mdout1_2_32, 
+            DOB4=>mdout1_2_31, DOB3=>mdout1_2_30, DOB2=>mdout1_2_29, 
+            DOB1=>mdout1_2_28, DOB0=>mdout1_2_27);
+
+    pdp_ram_3_0_51: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), 
+            DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), 
+            DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, 
+            ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, 
+            ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, 
+            ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, 
+            CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, 
+            CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec24_p03, 
+            RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, 
+            DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, 
+            ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, 
+            ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, 
+            ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, 
+            CSB0=>dec25_r13, RSTB=>Reset, DOA17=>open, DOA16=>open, 
+            DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, 
+            DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, 
+            DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, 
+            DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, 
+            DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, 
+            DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_3_8, 
+            DOB7=>mdout1_3_7, DOB6=>mdout1_3_6, DOB5=>mdout1_3_5, 
+            DOB4=>mdout1_3_4, DOB3=>mdout1_3_3, DOB2=>mdout1_3_2, 
+            DOB1=>mdout1_3_1, DOB0=>mdout1_3_0);
+
+    pdp_ram_3_1_50: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), 
+            DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), 
+            DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec26_p03, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec27_r13, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_3_17, 
+            DOB7=>mdout1_3_16, DOB6=>mdout1_3_15, DOB5=>mdout1_3_14, 
+            DOB4=>mdout1_3_13, DOB3=>mdout1_3_12, DOB2=>mdout1_3_11, 
+            DOB1=>mdout1_3_10, DOB0=>mdout1_3_9);
+
+    pdp_ram_3_2_49: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), 
+            DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), 
+            DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec28_p03, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec29_r13, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_3_26, 
+            DOB7=>mdout1_3_25, DOB6=>mdout1_3_24, DOB5=>mdout1_3_23, 
+            DOB4=>mdout1_3_22, DOB3=>mdout1_3_21, DOB2=>mdout1_3_20, 
+            DOB1=>mdout1_3_19, DOB0=>mdout1_3_18);
+
+    pdp_ram_3_3_48: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), 
+            DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), 
+            DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec30_p03, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec31_r13, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_3_35, 
+            DOB7=>mdout1_3_34, DOB6=>mdout1_3_33, DOB5=>mdout1_3_32, 
+            DOB4=>mdout1_3_31, DOB3=>mdout1_3_30, DOB2=>mdout1_3_29, 
+            DOB1=>mdout1_3_28, DOB0=>mdout1_3_27);
+
+    pdp_ram_4_0_47: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), 
+            DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), 
+            DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, 
+            ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, 
+            ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, 
+            ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, 
+            CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, 
+            CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec32_p04, 
+            RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, 
+            DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, 
+            ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, 
+            ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, 
+            ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, 
+            CSB0=>dec33_r14, RSTB=>Reset, DOA17=>open, DOA16=>open, 
+            DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, 
+            DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, 
+            DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, 
+            DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, 
+            DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, 
+            DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_4_8, 
+            DOB7=>mdout1_4_7, DOB6=>mdout1_4_6, DOB5=>mdout1_4_5, 
+            DOB4=>mdout1_4_4, DOB3=>mdout1_4_3, DOB2=>mdout1_4_2, 
+            DOB1=>mdout1_4_1, DOB0=>mdout1_4_0);
+
+    pdp_ram_4_1_46: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), 
+            DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), 
+            DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec34_p04, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec35_r14, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_4_17, 
+            DOB7=>mdout1_4_16, DOB6=>mdout1_4_15, DOB5=>mdout1_4_14, 
+            DOB4=>mdout1_4_13, DOB3=>mdout1_4_12, DOB2=>mdout1_4_11, 
+            DOB1=>mdout1_4_10, DOB0=>mdout1_4_9);
+
+    pdp_ram_4_2_45: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), 
+            DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), 
+            DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec36_p04, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec37_r14, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_4_26, 
+            DOB7=>mdout1_4_25, DOB6=>mdout1_4_24, DOB5=>mdout1_4_23, 
+            DOB4=>mdout1_4_22, DOB3=>mdout1_4_21, DOB2=>mdout1_4_20, 
+            DOB1=>mdout1_4_19, DOB0=>mdout1_4_18);
+
+    pdp_ram_4_3_44: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), 
+            DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), 
+            DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec38_p04, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec39_r14, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_4_35, 
+            DOB7=>mdout1_4_34, DOB6=>mdout1_4_33, DOB5=>mdout1_4_32, 
+            DOB4=>mdout1_4_31, DOB3=>mdout1_4_30, DOB2=>mdout1_4_29, 
+            DOB1=>mdout1_4_28, DOB0=>mdout1_4_27);
+
+    pdp_ram_5_0_43: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), 
+            DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), 
+            DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, 
+            ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, 
+            ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, 
+            ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, 
+            CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, 
+            CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec40_p05, 
+            RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, 
+            DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, 
+            ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, 
+            ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, 
+            ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, 
+            CSB0=>dec41_r15, RSTB=>Reset, DOA17=>open, DOA16=>open, 
+            DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, 
+            DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, 
+            DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, 
+            DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, 
+            DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, 
+            DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_5_8, 
+            DOB7=>mdout1_5_7, DOB6=>mdout1_5_6, DOB5=>mdout1_5_5, 
+            DOB4=>mdout1_5_4, DOB3=>mdout1_5_3, DOB2=>mdout1_5_2, 
+            DOB1=>mdout1_5_1, DOB0=>mdout1_5_0);
+
+    pdp_ram_5_1_42: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), 
+            DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), 
+            DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec42_p05, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec43_r15, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_5_17, 
+            DOB7=>mdout1_5_16, DOB6=>mdout1_5_15, DOB5=>mdout1_5_14, 
+            DOB4=>mdout1_5_13, DOB3=>mdout1_5_12, DOB2=>mdout1_5_11, 
+            DOB1=>mdout1_5_10, DOB0=>mdout1_5_9);
+
+    pdp_ram_5_2_41: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), 
+            DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), 
+            DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec44_p05, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec45_r15, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_5_26, 
+            DOB7=>mdout1_5_25, DOB6=>mdout1_5_24, DOB5=>mdout1_5_23, 
+            DOB4=>mdout1_5_22, DOB3=>mdout1_5_21, DOB2=>mdout1_5_20, 
+            DOB1=>mdout1_5_19, DOB0=>mdout1_5_18);
+
+    pdp_ram_5_3_40: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), 
+            DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), 
+            DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec46_p05, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec47_r15, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_5_35, 
+            DOB7=>mdout1_5_34, DOB6=>mdout1_5_33, DOB5=>mdout1_5_32, 
+            DOB4=>mdout1_5_31, DOB3=>mdout1_5_30, DOB2=>mdout1_5_29, 
+            DOB1=>mdout1_5_28, DOB0=>mdout1_5_27);
+
+    pdp_ram_6_0_39: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), 
+            DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), 
+            DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, 
+            ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, 
+            ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, 
+            ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, 
+            CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, 
+            CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec48_p06, 
+            RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, 
+            DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, 
+            ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, 
+            ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, 
+            ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, 
+            CSB0=>dec49_r16, RSTB=>Reset, DOA17=>open, DOA16=>open, 
+            DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, 
+            DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, 
+            DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, 
+            DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, 
+            DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, 
+            DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_6_8, 
+            DOB7=>mdout1_6_7, DOB6=>mdout1_6_6, DOB5=>mdout1_6_5, 
+            DOB4=>mdout1_6_4, DOB3=>mdout1_6_3, DOB2=>mdout1_6_2, 
+            DOB1=>mdout1_6_1, DOB0=>mdout1_6_0);
+
+    pdp_ram_6_1_38: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), 
+            DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), 
+            DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec50_p06, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec51_r16, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_6_17, 
+            DOB7=>mdout1_6_16, DOB6=>mdout1_6_15, DOB5=>mdout1_6_14, 
+            DOB4=>mdout1_6_13, DOB3=>mdout1_6_12, DOB2=>mdout1_6_11, 
+            DOB1=>mdout1_6_10, DOB0=>mdout1_6_9);
+
+    pdp_ram_6_2_37: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), 
+            DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), 
+            DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec52_p06, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec53_r16, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_6_26, 
+            DOB7=>mdout1_6_25, DOB6=>mdout1_6_24, DOB5=>mdout1_6_23, 
+            DOB4=>mdout1_6_22, DOB3=>mdout1_6_21, DOB2=>mdout1_6_20, 
+            DOB1=>mdout1_6_19, DOB0=>mdout1_6_18);
+
+    pdp_ram_6_3_36: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), 
+            DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), 
+            DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec54_p06, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec55_r16, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_6_35, 
+            DOB7=>mdout1_6_34, DOB6=>mdout1_6_33, DOB5=>mdout1_6_32, 
+            DOB4=>mdout1_6_31, DOB3=>mdout1_6_30, DOB2=>mdout1_6_29, 
+            DOB1=>mdout1_6_28, DOB0=>mdout1_6_27);
+
+    pdp_ram_7_0_35: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), 
+            DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), 
+            DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, 
+            ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, 
+            ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, 
+            ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, 
+            CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, 
+            CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec56_p07, 
+            RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, 
+            DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, 
+            ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, 
+            ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, 
+            ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, 
+            CSB0=>dec57_r17, RSTB=>Reset, DOA17=>open, DOA16=>open, 
+            DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, 
+            DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, 
+            DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, 
+            DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, 
+            DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, 
+            DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_7_8, 
+            DOB7=>mdout1_7_7, DOB6=>mdout1_7_6, DOB5=>mdout1_7_5, 
+            DOB4=>mdout1_7_4, DOB3=>mdout1_7_3, DOB2=>mdout1_7_2, 
+            DOB1=>mdout1_7_1, DOB0=>mdout1_7_0);
+
+    pdp_ram_7_1_34: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), 
+            DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), 
+            DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec58_p07, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec59_r17, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_7_17, 
+            DOB7=>mdout1_7_16, DOB6=>mdout1_7_15, DOB5=>mdout1_7_14, 
+            DOB4=>mdout1_7_13, DOB3=>mdout1_7_12, DOB2=>mdout1_7_11, 
+            DOB1=>mdout1_7_10, DOB0=>mdout1_7_9);
+
+    pdp_ram_7_2_33: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), 
+            DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), 
+            DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec60_p07, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec61_r17, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_7_26, 
+            DOB7=>mdout1_7_25, DOB6=>mdout1_7_24, DOB5=>mdout1_7_23, 
+            DOB4=>mdout1_7_22, DOB3=>mdout1_7_21, DOB2=>mdout1_7_20, 
+            DOB1=>mdout1_7_19, DOB0=>mdout1_7_18);
+
+    pdp_ram_7_3_32: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), 
+            DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), 
+            DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec62_p07, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec63_r17, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_7_35, 
+            DOB7=>mdout1_7_34, DOB6=>mdout1_7_33, DOB5=>mdout1_7_32, 
+            DOB4=>mdout1_7_31, DOB3=>mdout1_7_30, DOB2=>mdout1_7_29, 
+            DOB1=>mdout1_7_28, DOB0=>mdout1_7_27);
+
+    pdp_ram_8_0_31: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), 
+            DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), 
+            DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, 
+            ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, 
+            ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, 
+            ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, 
+            CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, 
+            CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec64_p08, 
+            RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, 
+            DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, 
+            ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, 
+            ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, 
+            ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, 
+            CSB0=>dec65_r18, RSTB=>Reset, DOA17=>open, DOA16=>open, 
+            DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, 
+            DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, 
+            DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, 
+            DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, 
+            DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, 
+            DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_8_8, 
+            DOB7=>mdout1_8_7, DOB6=>mdout1_8_6, DOB5=>mdout1_8_5, 
+            DOB4=>mdout1_8_4, DOB3=>mdout1_8_3, DOB2=>mdout1_8_2, 
+            DOB1=>mdout1_8_1, DOB0=>mdout1_8_0);
+
+    pdp_ram_8_1_30: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), 
+            DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), 
+            DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec66_p08, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec67_r18, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_8_17, 
+            DOB7=>mdout1_8_16, DOB6=>mdout1_8_15, DOB5=>mdout1_8_14, 
+            DOB4=>mdout1_8_13, DOB3=>mdout1_8_12, DOB2=>mdout1_8_11, 
+            DOB1=>mdout1_8_10, DOB0=>mdout1_8_9);
+
+    pdp_ram_8_2_29: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), 
+            DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), 
+            DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec68_p08, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec69_r18, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_8_26, 
+            DOB7=>mdout1_8_25, DOB6=>mdout1_8_24, DOB5=>mdout1_8_23, 
+            DOB4=>mdout1_8_22, DOB3=>mdout1_8_21, DOB2=>mdout1_8_20, 
+            DOB1=>mdout1_8_19, DOB0=>mdout1_8_18);
+
+    pdp_ram_8_3_28: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), 
+            DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), 
+            DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec70_p08, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec71_r18, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_8_35, 
+            DOB7=>mdout1_8_34, DOB6=>mdout1_8_33, DOB5=>mdout1_8_32, 
+            DOB4=>mdout1_8_31, DOB3=>mdout1_8_30, DOB2=>mdout1_8_29, 
+            DOB1=>mdout1_8_28, DOB0=>mdout1_8_27);
+
+    pdp_ram_9_0_27: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), 
+            DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), 
+            DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, 
+            ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, 
+            ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, 
+            ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, 
+            CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, 
+            CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec72_p09, 
+            RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, 
+            DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, 
+            ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, 
+            ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, 
+            ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, 
+            CSB0=>dec73_r19, RSTB=>Reset, DOA17=>open, DOA16=>open, 
+            DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, 
+            DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, 
+            DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, 
+            DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, 
+            DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, 
+            DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_9_8, 
+            DOB7=>mdout1_9_7, DOB6=>mdout1_9_6, DOB5=>mdout1_9_5, 
+            DOB4=>mdout1_9_4, DOB3=>mdout1_9_3, DOB2=>mdout1_9_2, 
+            DOB1=>mdout1_9_1, DOB0=>mdout1_9_0);
+
+    pdp_ram_9_1_26: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), 
+            DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), 
+            DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec74_p09, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec75_r19, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_9_17, 
+            DOB7=>mdout1_9_16, DOB6=>mdout1_9_15, DOB5=>mdout1_9_14, 
+            DOB4=>mdout1_9_13, DOB3=>mdout1_9_12, DOB2=>mdout1_9_11, 
+            DOB1=>mdout1_9_10, DOB0=>mdout1_9_9);
+
+    pdp_ram_9_2_25: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), 
+            DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), 
+            DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec76_p09, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec77_r19, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_9_26, 
+            DOB7=>mdout1_9_25, DOB6=>mdout1_9_24, DOB5=>mdout1_9_23, 
+            DOB4=>mdout1_9_22, DOB3=>mdout1_9_21, DOB2=>mdout1_9_20, 
+            DOB1=>mdout1_9_19, DOB0=>mdout1_9_18);
+
+    pdp_ram_9_3_24: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), 
+            DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), 
+            DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec78_p09, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec79_r19, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_9_35, 
+            DOB7=>mdout1_9_34, DOB6=>mdout1_9_33, DOB5=>mdout1_9_32, 
+            DOB4=>mdout1_9_31, DOB3=>mdout1_9_30, DOB2=>mdout1_9_29, 
+            DOB1=>mdout1_9_28, DOB0=>mdout1_9_27);
+
+    pdp_ram_10_0_23: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), 
+            DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), 
+            DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, 
+            ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, 
+            ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, 
+            ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, 
+            CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, 
+            CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec80_p010, 
+            RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, 
+            DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, 
+            ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, 
+            ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, 
+            ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, 
+            CSB0=>dec81_r110, RSTB=>Reset, DOA17=>open, DOA16=>open, 
+            DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, 
+            DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, 
+            DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, 
+            DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, 
+            DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, 
+            DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_10_8, 
+            DOB7=>mdout1_10_7, DOB6=>mdout1_10_6, DOB5=>mdout1_10_5, 
+            DOB4=>mdout1_10_4, DOB3=>mdout1_10_3, DOB2=>mdout1_10_2, 
+            DOB1=>mdout1_10_1, DOB0=>mdout1_10_0);
+
+    pdp_ram_10_1_22: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), 
+            DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), 
+            DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec82_p010, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec83_r110, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_10_17, 
+            DOB7=>mdout1_10_16, DOB6=>mdout1_10_15, DOB5=>mdout1_10_14, 
+            DOB4=>mdout1_10_13, DOB3=>mdout1_10_12, DOB2=>mdout1_10_11, 
+            DOB1=>mdout1_10_10, DOB0=>mdout1_10_9);
+
+    pdp_ram_10_2_21: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), 
+            DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), 
+            DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec84_p010, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec85_r110, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_10_26, 
+            DOB7=>mdout1_10_25, DOB6=>mdout1_10_24, DOB5=>mdout1_10_23, 
+            DOB4=>mdout1_10_22, DOB3=>mdout1_10_21, DOB2=>mdout1_10_20, 
+            DOB1=>mdout1_10_19, DOB0=>mdout1_10_18);
+
+    pdp_ram_10_3_20: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), 
+            DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), 
+            DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec86_p010, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec87_r110, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_10_35, 
+            DOB7=>mdout1_10_34, DOB6=>mdout1_10_33, DOB5=>mdout1_10_32, 
+            DOB4=>mdout1_10_31, DOB3=>mdout1_10_30, DOB2=>mdout1_10_29, 
+            DOB1=>mdout1_10_28, DOB0=>mdout1_10_27);
+
+    pdp_ram_11_0_19: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), 
+            DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), 
+            DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, 
+            ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, 
+            ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, 
+            ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, 
+            CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, 
+            CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec88_p011, 
+            RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, 
+            DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, 
+            ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, 
+            ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, 
+            ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, 
+            CSB0=>dec89_r111, RSTB=>Reset, DOA17=>open, DOA16=>open, 
+            DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, 
+            DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, 
+            DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, 
+            DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, 
+            DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, 
+            DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_11_8, 
+            DOB7=>mdout1_11_7, DOB6=>mdout1_11_6, DOB5=>mdout1_11_5, 
+            DOB4=>mdout1_11_4, DOB3=>mdout1_11_3, DOB2=>mdout1_11_2, 
+            DOB1=>mdout1_11_1, DOB0=>mdout1_11_0);
+
+    pdp_ram_11_1_18: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), 
+            DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), 
+            DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec90_p011, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec91_r111, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_11_17, 
+            DOB7=>mdout1_11_16, DOB6=>mdout1_11_15, DOB5=>mdout1_11_14, 
+            DOB4=>mdout1_11_13, DOB3=>mdout1_11_12, DOB2=>mdout1_11_11, 
+            DOB1=>mdout1_11_10, DOB0=>mdout1_11_9);
+
+    pdp_ram_11_2_17: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), 
+            DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), 
+            DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec92_p011, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec93_r111, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_11_26, 
+            DOB7=>mdout1_11_25, DOB6=>mdout1_11_24, DOB5=>mdout1_11_23, 
+            DOB4=>mdout1_11_22, DOB3=>mdout1_11_21, DOB2=>mdout1_11_20, 
+            DOB1=>mdout1_11_19, DOB0=>mdout1_11_18);
+
+    pdp_ram_11_3_16: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), 
+            DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), 
+            DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec94_p011, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec95_r111, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_11_35, 
+            DOB7=>mdout1_11_34, DOB6=>mdout1_11_33, DOB5=>mdout1_11_32, 
+            DOB4=>mdout1_11_31, DOB3=>mdout1_11_30, DOB2=>mdout1_11_29, 
+            DOB1=>mdout1_11_28, DOB0=>mdout1_11_27);
+
+    pdp_ram_12_0_15: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), 
+            DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), 
+            DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, 
+            ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, 
+            ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, 
+            ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, 
+            CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, 
+            CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec96_p012, 
+            RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, 
+            DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, 
+            ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, 
+            ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, 
+            ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, 
+            CSB0=>dec97_r112, RSTB=>Reset, DOA17=>open, DOA16=>open, 
+            DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, 
+            DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, 
+            DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, 
+            DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, 
+            DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, 
+            DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_12_8, 
+            DOB7=>mdout1_12_7, DOB6=>mdout1_12_6, DOB5=>mdout1_12_5, 
+            DOB4=>mdout1_12_4, DOB3=>mdout1_12_3, DOB2=>mdout1_12_2, 
+            DOB1=>mdout1_12_1, DOB0=>mdout1_12_0);
+
+    pdp_ram_12_1_14: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), 
+            DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), 
+            DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec98_p012, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec99_r112, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_12_17, 
+            DOB7=>mdout1_12_16, DOB6=>mdout1_12_15, DOB5=>mdout1_12_14, 
+            DOB4=>mdout1_12_13, DOB3=>mdout1_12_12, DOB2=>mdout1_12_11, 
+            DOB1=>mdout1_12_10, DOB0=>mdout1_12_9);
+
+    pdp_ram_12_2_13: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), 
+            DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), 
+            DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec100_p012, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec101_r112, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_12_26, 
+            DOB7=>mdout1_12_25, DOB6=>mdout1_12_24, DOB5=>mdout1_12_23, 
+            DOB4=>mdout1_12_22, DOB3=>mdout1_12_21, DOB2=>mdout1_12_20, 
+            DOB1=>mdout1_12_19, DOB0=>mdout1_12_18);
+
+    pdp_ram_12_3_12: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), 
+            DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), 
+            DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec102_p012, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec103_r112, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_12_35, 
+            DOB7=>mdout1_12_34, DOB6=>mdout1_12_33, DOB5=>mdout1_12_32, 
+            DOB4=>mdout1_12_31, DOB3=>mdout1_12_30, DOB2=>mdout1_12_29, 
+            DOB1=>mdout1_12_28, DOB0=>mdout1_12_27);
+
+    pdp_ram_13_0_11: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), 
+            DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), 
+            DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, 
+            ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, 
+            ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, 
+            ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, 
+            CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, 
+            CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec104_p013, 
+            RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, 
+            DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, 
+            ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, 
+            ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, 
+            ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, 
+            CSB0=>dec105_r113, RSTB=>Reset, DOA17=>open, DOA16=>open, 
+            DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, 
+            DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, 
+            DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, 
+            DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, 
+            DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, 
+            DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_13_8, 
+            DOB7=>mdout1_13_7, DOB6=>mdout1_13_6, DOB5=>mdout1_13_5, 
+            DOB4=>mdout1_13_4, DOB3=>mdout1_13_3, DOB2=>mdout1_13_2, 
+            DOB1=>mdout1_13_1, DOB0=>mdout1_13_0);
+
+    pdp_ram_13_1_10: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), 
+            DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), 
+            DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec106_p013, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec107_r113, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_13_17, 
+            DOB7=>mdout1_13_16, DOB6=>mdout1_13_15, DOB5=>mdout1_13_14, 
+            DOB4=>mdout1_13_13, DOB3=>mdout1_13_12, DOB2=>mdout1_13_11, 
+            DOB1=>mdout1_13_10, DOB0=>mdout1_13_9);
+
+    pdp_ram_13_2_9: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), 
+            DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), 
+            DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec108_p013, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec109_r113, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_13_26, 
+            DOB7=>mdout1_13_25, DOB6=>mdout1_13_24, DOB5=>mdout1_13_23, 
+            DOB4=>mdout1_13_22, DOB3=>mdout1_13_21, DOB2=>mdout1_13_20, 
+            DOB1=>mdout1_13_19, DOB0=>mdout1_13_18);
+
+    pdp_ram_13_3_8: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), 
+            DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), 
+            DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec110_p013, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec111_r113, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_13_35, 
+            DOB7=>mdout1_13_34, DOB6=>mdout1_13_33, DOB5=>mdout1_13_32, 
+            DOB4=>mdout1_13_31, DOB3=>mdout1_13_30, DOB2=>mdout1_13_29, 
+            DOB1=>mdout1_13_28, DOB0=>mdout1_13_27);
+
+    pdp_ram_14_0_7: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), 
+            DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), 
+            DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, 
+            ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, 
+            ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, 
+            ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, 
+            CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, 
+            CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec112_p014, 
+            RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, 
+            DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, 
+            ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, 
+            ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, 
+            ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, 
+            CSB0=>dec113_r114, RSTB=>Reset, DOA17=>open, DOA16=>open, 
+            DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, 
+            DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, 
+            DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, 
+            DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, 
+            DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, 
+            DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_14_8, 
+            DOB7=>mdout1_14_7, DOB6=>mdout1_14_6, DOB5=>mdout1_14_5, 
+            DOB4=>mdout1_14_4, DOB3=>mdout1_14_3, DOB2=>mdout1_14_2, 
+            DOB1=>mdout1_14_1, DOB0=>mdout1_14_0);
+
+    pdp_ram_14_1_6: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), 
+            DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), 
+            DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec114_p014, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec115_r114, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_14_17, 
+            DOB7=>mdout1_14_16, DOB6=>mdout1_14_15, DOB5=>mdout1_14_14, 
+            DOB4=>mdout1_14_13, DOB3=>mdout1_14_12, DOB2=>mdout1_14_11, 
+            DOB1=>mdout1_14_10, DOB0=>mdout1_14_9);
+
+    pdp_ram_14_2_5: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), 
+            DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), 
+            DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec116_p014, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec117_r114, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_14_26, 
+            DOB7=>mdout1_14_25, DOB6=>mdout1_14_24, DOB5=>mdout1_14_23, 
+            DOB4=>mdout1_14_22, DOB3=>mdout1_14_21, DOB2=>mdout1_14_20, 
+            DOB1=>mdout1_14_19, DOB0=>mdout1_14_18);
+
+    pdp_ram_14_3_4: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), 
+            DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), 
+            DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec118_p014, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec119_r114, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_14_35, 
+            DOB7=>mdout1_14_34, DOB6=>mdout1_14_33, DOB5=>mdout1_14_32, 
+            DOB4=>mdout1_14_31, DOB3=>mdout1_14_30, DOB2=>mdout1_14_29, 
+            DOB1=>mdout1_14_28, DOB0=>mdout1_14_27);
+
+    pdp_ram_15_0_3: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), 
+            DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), 
+            DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, 
+            ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, 
+            ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, 
+            ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, 
+            CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, 
+            CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec120_p015, 
+            RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, 
+            DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, 
+            ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, 
+            ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, 
+            ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, 
+            CSB0=>dec121_r115, RSTB=>Reset, DOA17=>open, DOA16=>open, 
+            DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, 
+            DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, 
+            DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, 
+            DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, 
+            DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, 
+            DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_15_8, 
+            DOB7=>mdout1_15_7, DOB6=>mdout1_15_6, DOB5=>mdout1_15_5, 
+            DOB4=>mdout1_15_4, DOB3=>mdout1_15_3, DOB2=>mdout1_15_2, 
+            DOB1=>mdout1_15_1, DOB0=>mdout1_15_0);
+
+    pdp_ram_15_1_2: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), 
+            DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), 
+            DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec122_p015, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec123_r115, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_15_17, 
+            DOB7=>mdout1_15_16, DOB6=>mdout1_15_15, DOB5=>mdout1_15_14, 
+            DOB4=>mdout1_15_13, DOB3=>mdout1_15_12, DOB2=>mdout1_15_11, 
+            DOB1=>mdout1_15_10, DOB0=>mdout1_15_9);
+
+    pdp_ram_15_2_1: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), 
+            DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), 
+            DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec124_p015, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec125_r115, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_15_26, 
+            DOB7=>mdout1_15_25, DOB6=>mdout1_15_24, DOB5=>mdout1_15_23, 
+            DOB4=>mdout1_15_22, DOB3=>mdout1_15_21, DOB2=>mdout1_15_20, 
+            DOB1=>mdout1_15_19, DOB0=>mdout1_15_18);
+
+    pdp_ram_15_3_0: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), 
+            DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), 
+            DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>dec126_p015, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec127_r115, 
+            RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, 
+            DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, 
+            DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, 
+            DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, 
+            DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, 
+            DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, 
+            DOB10=>open, DOB9=>open, DOB8=>mdout1_15_35, 
+            DOB7=>mdout1_15_34, DOB6=>mdout1_15_33, DOB5=>mdout1_15_32, 
+            DOB4=>mdout1_15_31, DOB3=>mdout1_15_30, DOB2=>mdout1_15_29, 
+            DOB1=>mdout1_15_28, DOB0=>mdout1_15_27);
+
+    FF_106: FD1P3DX
+        port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_0);
+
+    FF_105: FD1P3DX
+        port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_1);
+
+    FF_104: FD1P3DX
+        port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_2);
+
+    FF_103: FD1P3DX
+        port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_3);
+
+    FF_102: FD1P3DX
+        port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_4);
+
+    FF_101: FD1P3DX
+        port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_5);
+
+    FF_100: FD1P3DX
+        port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_6);
+
+    FF_99: FD1P3DX
+        port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_7);
+
+    FF_98: FD1P3DX
+        port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_8);
+
+    FF_97: FD1P3DX
+        port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_9);
+
+    FF_96: FD1P3DX
+        port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_10);
+
+    FF_95: FD1P3DX
+        port map (D=>ifcount_11, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_11);
+
+    FF_94: FD1P3DX
+        port map (D=>ifcount_12, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_12);
+
+    FF_93: FD1P3DX
+        port map (D=>ifcount_13, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_13);
+
+    FF_92: FD1P3DX
+        port map (D=>ifcount_14, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_14);
+
+    FF_91: FD1P3DX
+        port map (D=>ifcount_15, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_15);
+
+    FF_90: FD1S3BX
+        port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
+
+    FF_89: FD1S3DX
+        port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
+
+    FF_88: FD1P3BX
+        port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset, 
+            Q=>wcount_0);
+
+    FF_87: FD1P3DX
+        port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_1);
+
+    FF_86: FD1P3DX
+        port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_2);
+
+    FF_85: FD1P3DX
+        port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_3);
+
+    FF_84: FD1P3DX
+        port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_4);
+
+    FF_83: FD1P3DX
+        port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_5);
+
+    FF_82: FD1P3DX
+        port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_6);
+
+    FF_81: FD1P3DX
+        port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_7);
+
+    FF_80: FD1P3DX
+        port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_8);
+
+    FF_79: FD1P3DX
+        port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_9);
+
+    FF_78: FD1P3DX
+        port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_10);
+
+    FF_77: FD1P3DX
+        port map (D=>iwcount_11, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_11);
+
+    FF_76: FD1P3DX
+        port map (D=>iwcount_12, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_12);
+
+    FF_75: FD1P3DX
+        port map (D=>iwcount_13, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_13);
+
+    FF_74: FD1P3DX
+        port map (D=>iwcount_14, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_14);
+
+    FF_73: FD1P3DX
+        port map (D=>iwcount_15, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_15);
+
+    FF_72: FD1P3BX
+        port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset, 
+            Q=>rcount_0);
+
+    FF_71: FD1P3DX
+        port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_1);
+
+    FF_70: FD1P3DX
+        port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_2);
+
+    FF_69: FD1P3DX
+        port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_3);
+
+    FF_68: FD1P3DX
+        port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_4);
+
+    FF_67: FD1P3DX
+        port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_5);
+
+    FF_66: FD1P3DX
+        port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_6);
+
+    FF_65: FD1P3DX
+        port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_7);
+
+    FF_64: FD1P3DX
+        port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_8);
+
+    FF_63: FD1P3DX
+        port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_9);
+
+    FF_62: FD1P3DX
+        port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_10);
+
+    FF_61: FD1P3DX
+        port map (D=>ircount_11, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_11);
+
+    FF_60: FD1P3DX
+        port map (D=>ircount_12, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_12);
+
+    FF_59: FD1P3DX
+        port map (D=>ircount_13, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_13);
+
+    FF_58: FD1P3DX
+        port map (D=>ircount_14, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_14);
+
+    FF_57: FD1P3DX
+        port map (D=>ircount_15, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_15);
+
+    FF_56: FD1P3DX
+        port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_0);
+
+    FF_55: FD1P3DX
+        port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_1);
+
+    FF_54: FD1P3DX
+        port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_2);
+
+    FF_53: FD1P3DX
+        port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_3);
+
+    FF_52: FD1P3DX
+        port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_4);
+
+    FF_51: FD1P3DX
+        port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_5);
+
+    FF_50: FD1P3DX
+        port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_6);
+
+    FF_49: FD1P3DX
+        port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_7);
+
+    FF_48: FD1P3DX
+        port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_8);
+
+    FF_47: FD1P3DX
+        port map (D=>wcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_9);
+
+    FF_46: FD1P3DX
+        port map (D=>wcount_10, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_10);
+
+    FF_45: FD1P3DX
+        port map (D=>wcount_11, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_11);
+
+    FF_44: FD1P3DX
+        port map (D=>wcount_12, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_12);
+
+    FF_43: FD1P3DX
+        port map (D=>wcount_13, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_13);
+
+    FF_42: FD1P3DX
+        port map (D=>wcount_14, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_14);
+
+    FF_41: FD1P3DX
+        port map (D=>wcount_15, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_15);
+
+    FF_40: FD1P3DX
+        port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_0);
+
+    FF_39: FD1P3DX
+        port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_1);
+
+    FF_38: FD1P3DX
+        port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_2);
+
+    FF_37: FD1P3DX
+        port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_3);
+
+    FF_36: FD1P3DX
+        port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_4);
+
+    FF_35: FD1P3DX
+        port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_5);
+
+    FF_34: FD1P3DX
+        port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_6);
+
+    FF_33: FD1P3DX
+        port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_7);
+
+    FF_32: FD1P3DX
+        port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_8);
+
+    FF_31: FD1P3DX
+        port map (D=>rcount_9, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_9);
+
+    FF_30: FD1P3DX
+        port map (D=>rcount_10, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_10);
+
+    FF_29: FD1P3DX
+        port map (D=>rcount_11, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_11);
+
+    FF_28: FD1P3DX
+        port map (D=>rcount_12, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_12);
+
+    FF_27: FD1P3DX
+        port map (D=>rcount_13, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_13);
+
+    FF_26: FD1P3DX
+        port map (D=>rcount_14, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_14);
+
+    FF_25: FD1P3DX
+        port map (D=>rcount_15, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_15);
+
+    FF_24: FD1P3DX
+        port map (D=>rptr_11, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, 
+            Q=>rptr_11_ff);
+
+    FF_23: FD1P3DX
+        port map (D=>rptr_12, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, 
+            Q=>rptr_12_ff);
+
+    FF_22: FD1P3DX
+        port map (D=>rptr_13, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, 
+            Q=>rptr_13_ff);
+
+    FF_21: FD1P3DX
+        port map (D=>rptr_14, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, 
+            Q=>rptr_14_ff);
+
+    FF_20: FD1P3DX
+        port map (D=>rptr_11_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, 
+            Q=>rptr_11_ff2);
+
+    FF_19: FD1P3DX
+        port map (D=>rptr_12_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, 
+            Q=>rptr_12_ff2);
+
+    FF_18: FD1P3DX
+        port map (D=>rptr_13_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, 
+            Q=>rptr_13_ff2);
+
+    FF_17: FD1P3DX
+        port map (D=>rptr_14_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, 
+            Q=>rptr_14_ff2);
+
+    FF_16: FD1S3DX
+        port map (D=>wcnt_sub_0, CK=>Clock, CD=>Reset, Q=>wcnt_reg_0);
+
+    FF_15: FD1S3DX
+        port map (D=>wcnt_sub_1, CK=>Clock, CD=>Reset, Q=>wcnt_reg_1);
+
+    FF_14: FD1S3DX
+        port map (D=>wcnt_sub_2, CK=>Clock, CD=>Reset, Q=>wcnt_reg_2);
+
+    FF_13: FD1S3DX
+        port map (D=>wcnt_sub_3, CK=>Clock, CD=>Reset, Q=>wcnt_reg_3);
+
+    FF_12: FD1S3DX
+        port map (D=>wcnt_sub_4, CK=>Clock, CD=>Reset, Q=>wcnt_reg_4);
+
+    FF_11: FD1S3DX
+        port map (D=>wcnt_sub_5, CK=>Clock, CD=>Reset, Q=>wcnt_reg_5);
+
+    FF_10: FD1S3DX
+        port map (D=>wcnt_sub_6, CK=>Clock, CD=>Reset, Q=>wcnt_reg_6);
+
+    FF_9: FD1S3DX
+        port map (D=>wcnt_sub_7, CK=>Clock, CD=>Reset, Q=>wcnt_reg_7);
+
+    FF_8: FD1S3DX
+        port map (D=>wcnt_sub_8, CK=>Clock, CD=>Reset, Q=>wcnt_reg_8);
+
+    FF_7: FD1S3DX
+        port map (D=>wcnt_sub_9, CK=>Clock, CD=>Reset, Q=>wcnt_reg_9);
+
+    FF_6: FD1S3DX
+        port map (D=>wcnt_sub_10, CK=>Clock, CD=>Reset, Q=>wcnt_reg_10);
+
+    FF_5: FD1S3DX
+        port map (D=>wcnt_sub_11, CK=>Clock, CD=>Reset, Q=>wcnt_reg_11);
+
+    FF_4: FD1S3DX
+        port map (D=>wcnt_sub_12, CK=>Clock, CD=>Reset, Q=>wcnt_reg_12);
+
+    FF_3: FD1S3DX
+        port map (D=>wcnt_sub_13, CK=>Clock, CD=>Reset, Q=>wcnt_reg_13);
+
+    FF_2: FD1S3DX
+        port map (D=>wcnt_sub_14, CK=>Clock, CD=>Reset, Q=>wcnt_reg_14);
+
+    FF_1: FD1S3DX
+        port map (D=>wcnt_sub_15, CK=>Clock, CD=>Reset, Q=>wcnt_reg_15);
+
+    FF_0: FD1S3DX
+        port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull);
+
+    bdcnt_bctr_cia: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>'X', S0=>open, S1=>open, COUT=>bdcnt_bctr_ci);
+
+    bdcnt_bctr_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_0, A1=>fcount_1, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>bdcnt_bctr_ci, S0=>ifcount_0, S1=>ifcount_1, COUT=>co0);
+
+    bdcnt_bctr_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co0, S0=>ifcount_2, S1=>ifcount_3, COUT=>co1);
+
+    bdcnt_bctr_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_4, A1=>fcount_5, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co1, S0=>ifcount_4, S1=>ifcount_5, COUT=>co2);
+
+    bdcnt_bctr_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_6, A1=>fcount_7, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co2, S0=>ifcount_6, S1=>ifcount_7, COUT=>co3);
+
+    bdcnt_bctr_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_8, A1=>fcount_9, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co3, S0=>ifcount_8, S1=>ifcount_9, COUT=>co4);
+
+    bdcnt_bctr_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_10, A1=>fcount_11, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co4, S0=>ifcount_10, S1=>ifcount_11, COUT=>co5);
+
+    bdcnt_bctr_6: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_12, A1=>fcount_13, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co5, S0=>ifcount_12, S1=>ifcount_13, COUT=>co6);
+
+    bdcnt_bctr_7: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_14, A1=>fcount_15, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co6, S0=>ifcount_14, S1=>ifcount_15, COUT=>co7);
+
+    e_cmp_ci_a: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci);
+
+    e_cmp_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>rden_i, A1=>scuba_vlo, B0=>fcount_0, B1=>fcount_1, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>cmp_ci, S0=>open, S1=>open, COUT=>co0_1);
+
+    e_cmp_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_2, 
+            B1=>fcount_3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co0_1, S0=>open, S1=>open, COUT=>co1_1);
+
+    e_cmp_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_4, 
+            B1=>fcount_5, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co1_1, S0=>open, S1=>open, COUT=>co2_1);
+
+    e_cmp_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_6, 
+            B1=>fcount_7, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co2_1, S0=>open, S1=>open, COUT=>co3_1);
+
+    e_cmp_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_8, 
+            B1=>fcount_9, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co3_1, S0=>open, S1=>open, COUT=>co4_1);
+
+    e_cmp_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_10, 
+            B1=>fcount_11, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co4_1, S0=>open, S1=>open, COUT=>co5_1);
+
+    e_cmp_6: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_12, 
+            B1=>fcount_13, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co5_1, S0=>open, S1=>open, COUT=>co6_1);
+
+    e_cmp_7: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_14, 
+            B1=>fcount_15, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co6_1, S0=>open, S1=>open, 
+            COUT=>cmp_le_1_c);
+
+    a0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>cmp_le_1_c, S0=>cmp_le_1, S1=>open, 
+            COUT=>open);
+
+    g_cmp_ci_a: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_1);
+
+    g_cmp_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>cmp_ci_1, S0=>open, S1=>open, COUT=>co0_2);
+
+    g_cmp_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co0_2, S0=>open, S1=>open, COUT=>co1_2);
+
+    g_cmp_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co1_2, S0=>open, S1=>open, COUT=>co2_2);
+
+    g_cmp_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co2_2, S0=>open, S1=>open, COUT=>co3_2);
+
+    g_cmp_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co3_2, S0=>open, S1=>open, COUT=>co4_2);
+
+    g_cmp_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_10, A1=>fcount_11, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co4_2, S0=>open, S1=>open, COUT=>co5_2);
+
+    g_cmp_6: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_12, A1=>fcount_13, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co5_2, S0=>open, S1=>open, COUT=>co6_2);
+
+    g_cmp_7: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_14, A1=>fcount_15, B0=>wren_i, 
+            B1=>wren_i_inv, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co6_2, S0=>open, S1=>open, 
+            COUT=>cmp_ge_d1_c);
+
+    a1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>cmp_ge_d1_c, S0=>cmp_ge_d1, S1=>open, 
+            COUT=>open);
+
+    w_ctr_cia: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>w_ctr_ci);
+
+    w_ctr_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>w_ctr_ci, S0=>iwcount_0, S1=>iwcount_1, 
+            COUT=>co0_3);
+
+    w_ctr_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_2, A1=>wcount_3, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co0_3, S0=>iwcount_2, S1=>iwcount_3, 
+            COUT=>co1_3);
+
+    w_ctr_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_4, A1=>wcount_5, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co1_3, S0=>iwcount_4, S1=>iwcount_5, 
+            COUT=>co2_3);
+
+    w_ctr_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_6, A1=>wcount_7, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co2_3, S0=>iwcount_6, S1=>iwcount_7, 
+            COUT=>co3_3);
+
+    w_ctr_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_8, A1=>wcount_9, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co3_3, S0=>iwcount_8, S1=>iwcount_9, 
+            COUT=>co4_3);
+
+    w_ctr_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_10, A1=>wcount_11, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co4_3, S0=>iwcount_10, S1=>iwcount_11, 
+            COUT=>co5_3);
+
+    w_ctr_6: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_12, A1=>wcount_13, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co5_3, S0=>iwcount_12, S1=>iwcount_13, 
+            COUT=>co6_3);
+
+    w_ctr_7: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_14, A1=>wcount_15, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co6_3, S0=>iwcount_14, S1=>iwcount_15, 
+            COUT=>co7_1);
+
+    r_ctr_cia: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>r_ctr_ci);
+
+    r_ctr_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>r_ctr_ci, S0=>ircount_0, S1=>ircount_1, 
+            COUT=>co0_4);
+
+    r_ctr_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_2, A1=>rcount_3, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co0_4, S0=>ircount_2, S1=>ircount_3, 
+            COUT=>co1_4);
+
+    r_ctr_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_4, A1=>rcount_5, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co1_4, S0=>ircount_4, S1=>ircount_5, 
+            COUT=>co2_4);
+
+    r_ctr_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_6, A1=>rcount_7, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co2_4, S0=>ircount_6, S1=>ircount_7, 
+            COUT=>co3_4);
+
+    r_ctr_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_8, A1=>rcount_9, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co3_4, S0=>ircount_8, S1=>ircount_9, 
+            COUT=>co4_4);
+
+    r_ctr_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_10, A1=>rcount_11, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co4_4, S0=>ircount_10, S1=>ircount_11, 
+            COUT=>co5_4);
+
+    r_ctr_6: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_12, A1=>rcount_13, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co5_4, S0=>ircount_12, S1=>ircount_13, 
+            COUT=>co6_4);
+
+    r_ctr_7: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_14, A1=>rcount_15, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co6_4, S0=>ircount_14, S1=>ircount_15, 
+            COUT=>co7_2);
+
+    mux_35: MUX161
+        port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0, 
+            D3=>mdout1_3_0, D4=>mdout1_4_0, D5=>mdout1_5_0, 
+            D6=>mdout1_6_0, D7=>mdout1_7_0, D8=>mdout1_8_0, 
+            D9=>mdout1_9_0, D10=>mdout1_10_0, D11=>mdout1_11_0, 
+            D12=>mdout1_12_0, D13=>mdout1_13_0, D14=>mdout1_14_0, 
+            D15=>mdout1_15_0, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(0));
+
+    mux_34: MUX161
+        port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1, 
+            D3=>mdout1_3_1, D4=>mdout1_4_1, D5=>mdout1_5_1, 
+            D6=>mdout1_6_1, D7=>mdout1_7_1, D8=>mdout1_8_1, 
+            D9=>mdout1_9_1, D10=>mdout1_10_1, D11=>mdout1_11_1, 
+            D12=>mdout1_12_1, D13=>mdout1_13_1, D14=>mdout1_14_1, 
+            D15=>mdout1_15_1, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(1));
+
+    mux_33: MUX161
+        port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2, 
+            D3=>mdout1_3_2, D4=>mdout1_4_2, D5=>mdout1_5_2, 
+            D6=>mdout1_6_2, D7=>mdout1_7_2, D8=>mdout1_8_2, 
+            D9=>mdout1_9_2, D10=>mdout1_10_2, D11=>mdout1_11_2, 
+            D12=>mdout1_12_2, D13=>mdout1_13_2, D14=>mdout1_14_2, 
+            D15=>mdout1_15_2, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(2));
+
+    mux_32: MUX161
+        port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3, 
+            D3=>mdout1_3_3, D4=>mdout1_4_3, D5=>mdout1_5_3, 
+            D6=>mdout1_6_3, D7=>mdout1_7_3, D8=>mdout1_8_3, 
+            D9=>mdout1_9_3, D10=>mdout1_10_3, D11=>mdout1_11_3, 
+            D12=>mdout1_12_3, D13=>mdout1_13_3, D14=>mdout1_14_3, 
+            D15=>mdout1_15_3, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(3));
+
+    mux_31: MUX161
+        port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4, 
+            D3=>mdout1_3_4, D4=>mdout1_4_4, D5=>mdout1_5_4, 
+            D6=>mdout1_6_4, D7=>mdout1_7_4, D8=>mdout1_8_4, 
+            D9=>mdout1_9_4, D10=>mdout1_10_4, D11=>mdout1_11_4, 
+            D12=>mdout1_12_4, D13=>mdout1_13_4, D14=>mdout1_14_4, 
+            D15=>mdout1_15_4, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(4));
+
+    mux_30: MUX161
+        port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5, 
+            D3=>mdout1_3_5, D4=>mdout1_4_5, D5=>mdout1_5_5, 
+            D6=>mdout1_6_5, D7=>mdout1_7_5, D8=>mdout1_8_5, 
+            D9=>mdout1_9_5, D10=>mdout1_10_5, D11=>mdout1_11_5, 
+            D12=>mdout1_12_5, D13=>mdout1_13_5, D14=>mdout1_14_5, 
+            D15=>mdout1_15_5, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(5));
+
+    mux_29: MUX161
+        port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6, 
+            D3=>mdout1_3_6, D4=>mdout1_4_6, D5=>mdout1_5_6, 
+            D6=>mdout1_6_6, D7=>mdout1_7_6, D8=>mdout1_8_6, 
+            D9=>mdout1_9_6, D10=>mdout1_10_6, D11=>mdout1_11_6, 
+            D12=>mdout1_12_6, D13=>mdout1_13_6, D14=>mdout1_14_6, 
+            D15=>mdout1_15_6, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(6));
+
+    mux_28: MUX161
+        port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7, 
+            D3=>mdout1_3_7, D4=>mdout1_4_7, D5=>mdout1_5_7, 
+            D6=>mdout1_6_7, D7=>mdout1_7_7, D8=>mdout1_8_7, 
+            D9=>mdout1_9_7, D10=>mdout1_10_7, D11=>mdout1_11_7, 
+            D12=>mdout1_12_7, D13=>mdout1_13_7, D14=>mdout1_14_7, 
+            D15=>mdout1_15_7, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(7));
+
+    mux_27: MUX161
+        port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8, 
+            D3=>mdout1_3_8, D4=>mdout1_4_8, D5=>mdout1_5_8, 
+            D6=>mdout1_6_8, D7=>mdout1_7_8, D8=>mdout1_8_8, 
+            D9=>mdout1_9_8, D10=>mdout1_10_8, D11=>mdout1_11_8, 
+            D12=>mdout1_12_8, D13=>mdout1_13_8, D14=>mdout1_14_8, 
+            D15=>mdout1_15_8, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(8));
+
+    mux_26: MUX161
+        port map (D0=>mdout1_0_9, D1=>mdout1_1_9, D2=>mdout1_2_9, 
+            D3=>mdout1_3_9, D4=>mdout1_4_9, D5=>mdout1_5_9, 
+            D6=>mdout1_6_9, D7=>mdout1_7_9, D8=>mdout1_8_9, 
+            D9=>mdout1_9_9, D10=>mdout1_10_9, D11=>mdout1_11_9, 
+            D12=>mdout1_12_9, D13=>mdout1_13_9, D14=>mdout1_14_9, 
+            D15=>mdout1_15_9, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(9));
+
+    mux_25: MUX161
+        port map (D0=>mdout1_0_10, D1=>mdout1_1_10, D2=>mdout1_2_10, 
+            D3=>mdout1_3_10, D4=>mdout1_4_10, D5=>mdout1_5_10, 
+            D6=>mdout1_6_10, D7=>mdout1_7_10, D8=>mdout1_8_10, 
+            D9=>mdout1_9_10, D10=>mdout1_10_10, D11=>mdout1_11_10, 
+            D12=>mdout1_12_10, D13=>mdout1_13_10, D14=>mdout1_14_10, 
+            D15=>mdout1_15_10, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(10));
+
+    mux_24: MUX161
+        port map (D0=>mdout1_0_11, D1=>mdout1_1_11, D2=>mdout1_2_11, 
+            D3=>mdout1_3_11, D4=>mdout1_4_11, D5=>mdout1_5_11, 
+            D6=>mdout1_6_11, D7=>mdout1_7_11, D8=>mdout1_8_11, 
+            D9=>mdout1_9_11, D10=>mdout1_10_11, D11=>mdout1_11_11, 
+            D12=>mdout1_12_11, D13=>mdout1_13_11, D14=>mdout1_14_11, 
+            D15=>mdout1_15_11, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(11));
+
+    mux_23: MUX161
+        port map (D0=>mdout1_0_12, D1=>mdout1_1_12, D2=>mdout1_2_12, 
+            D3=>mdout1_3_12, D4=>mdout1_4_12, D5=>mdout1_5_12, 
+            D6=>mdout1_6_12, D7=>mdout1_7_12, D8=>mdout1_8_12, 
+            D9=>mdout1_9_12, D10=>mdout1_10_12, D11=>mdout1_11_12, 
+            D12=>mdout1_12_12, D13=>mdout1_13_12, D14=>mdout1_14_12, 
+            D15=>mdout1_15_12, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(12));
+
+    mux_22: MUX161
+        port map (D0=>mdout1_0_13, D1=>mdout1_1_13, D2=>mdout1_2_13, 
+            D3=>mdout1_3_13, D4=>mdout1_4_13, D5=>mdout1_5_13, 
+            D6=>mdout1_6_13, D7=>mdout1_7_13, D8=>mdout1_8_13, 
+            D9=>mdout1_9_13, D10=>mdout1_10_13, D11=>mdout1_11_13, 
+            D12=>mdout1_12_13, D13=>mdout1_13_13, D14=>mdout1_14_13, 
+            D15=>mdout1_15_13, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(13));
+
+    mux_21: MUX161
+        port map (D0=>mdout1_0_14, D1=>mdout1_1_14, D2=>mdout1_2_14, 
+            D3=>mdout1_3_14, D4=>mdout1_4_14, D5=>mdout1_5_14, 
+            D6=>mdout1_6_14, D7=>mdout1_7_14, D8=>mdout1_8_14, 
+            D9=>mdout1_9_14, D10=>mdout1_10_14, D11=>mdout1_11_14, 
+            D12=>mdout1_12_14, D13=>mdout1_13_14, D14=>mdout1_14_14, 
+            D15=>mdout1_15_14, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(14));
+
+    mux_20: MUX161
+        port map (D0=>mdout1_0_15, D1=>mdout1_1_15, D2=>mdout1_2_15, 
+            D3=>mdout1_3_15, D4=>mdout1_4_15, D5=>mdout1_5_15, 
+            D6=>mdout1_6_15, D7=>mdout1_7_15, D8=>mdout1_8_15, 
+            D9=>mdout1_9_15, D10=>mdout1_10_15, D11=>mdout1_11_15, 
+            D12=>mdout1_12_15, D13=>mdout1_13_15, D14=>mdout1_14_15, 
+            D15=>mdout1_15_15, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(15));
+
+    mux_19: MUX161
+        port map (D0=>mdout1_0_16, D1=>mdout1_1_16, D2=>mdout1_2_16, 
+            D3=>mdout1_3_16, D4=>mdout1_4_16, D5=>mdout1_5_16, 
+            D6=>mdout1_6_16, D7=>mdout1_7_16, D8=>mdout1_8_16, 
+            D9=>mdout1_9_16, D10=>mdout1_10_16, D11=>mdout1_11_16, 
+            D12=>mdout1_12_16, D13=>mdout1_13_16, D14=>mdout1_14_16, 
+            D15=>mdout1_15_16, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(16));
+
+    mux_18: MUX161
+        port map (D0=>mdout1_0_17, D1=>mdout1_1_17, D2=>mdout1_2_17, 
+            D3=>mdout1_3_17, D4=>mdout1_4_17, D5=>mdout1_5_17, 
+            D6=>mdout1_6_17, D7=>mdout1_7_17, D8=>mdout1_8_17, 
+            D9=>mdout1_9_17, D10=>mdout1_10_17, D11=>mdout1_11_17, 
+            D12=>mdout1_12_17, D13=>mdout1_13_17, D14=>mdout1_14_17, 
+            D15=>mdout1_15_17, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(17));
+
+    mux_17: MUX161
+        port map (D0=>mdout1_0_18, D1=>mdout1_1_18, D2=>mdout1_2_18, 
+            D3=>mdout1_3_18, D4=>mdout1_4_18, D5=>mdout1_5_18, 
+            D6=>mdout1_6_18, D7=>mdout1_7_18, D8=>mdout1_8_18, 
+            D9=>mdout1_9_18, D10=>mdout1_10_18, D11=>mdout1_11_18, 
+            D12=>mdout1_12_18, D13=>mdout1_13_18, D14=>mdout1_14_18, 
+            D15=>mdout1_15_18, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(18));
+
+    mux_16: MUX161
+        port map (D0=>mdout1_0_19, D1=>mdout1_1_19, D2=>mdout1_2_19, 
+            D3=>mdout1_3_19, D4=>mdout1_4_19, D5=>mdout1_5_19, 
+            D6=>mdout1_6_19, D7=>mdout1_7_19, D8=>mdout1_8_19, 
+            D9=>mdout1_9_19, D10=>mdout1_10_19, D11=>mdout1_11_19, 
+            D12=>mdout1_12_19, D13=>mdout1_13_19, D14=>mdout1_14_19, 
+            D15=>mdout1_15_19, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(19));
+
+    mux_15: MUX161
+        port map (D0=>mdout1_0_20, D1=>mdout1_1_20, D2=>mdout1_2_20, 
+            D3=>mdout1_3_20, D4=>mdout1_4_20, D5=>mdout1_5_20, 
+            D6=>mdout1_6_20, D7=>mdout1_7_20, D8=>mdout1_8_20, 
+            D9=>mdout1_9_20, D10=>mdout1_10_20, D11=>mdout1_11_20, 
+            D12=>mdout1_12_20, D13=>mdout1_13_20, D14=>mdout1_14_20, 
+            D15=>mdout1_15_20, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(20));
+
+    mux_14: MUX161
+        port map (D0=>mdout1_0_21, D1=>mdout1_1_21, D2=>mdout1_2_21, 
+            D3=>mdout1_3_21, D4=>mdout1_4_21, D5=>mdout1_5_21, 
+            D6=>mdout1_6_21, D7=>mdout1_7_21, D8=>mdout1_8_21, 
+            D9=>mdout1_9_21, D10=>mdout1_10_21, D11=>mdout1_11_21, 
+            D12=>mdout1_12_21, D13=>mdout1_13_21, D14=>mdout1_14_21, 
+            D15=>mdout1_15_21, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(21));
+
+    mux_13: MUX161
+        port map (D0=>mdout1_0_22, D1=>mdout1_1_22, D2=>mdout1_2_22, 
+            D3=>mdout1_3_22, D4=>mdout1_4_22, D5=>mdout1_5_22, 
+            D6=>mdout1_6_22, D7=>mdout1_7_22, D8=>mdout1_8_22, 
+            D9=>mdout1_9_22, D10=>mdout1_10_22, D11=>mdout1_11_22, 
+            D12=>mdout1_12_22, D13=>mdout1_13_22, D14=>mdout1_14_22, 
+            D15=>mdout1_15_22, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(22));
+
+    mux_12: MUX161
+        port map (D0=>mdout1_0_23, D1=>mdout1_1_23, D2=>mdout1_2_23, 
+            D3=>mdout1_3_23, D4=>mdout1_4_23, D5=>mdout1_5_23, 
+            D6=>mdout1_6_23, D7=>mdout1_7_23, D8=>mdout1_8_23, 
+            D9=>mdout1_9_23, D10=>mdout1_10_23, D11=>mdout1_11_23, 
+            D12=>mdout1_12_23, D13=>mdout1_13_23, D14=>mdout1_14_23, 
+            D15=>mdout1_15_23, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(23));
+
+    mux_11: MUX161
+        port map (D0=>mdout1_0_24, D1=>mdout1_1_24, D2=>mdout1_2_24, 
+            D3=>mdout1_3_24, D4=>mdout1_4_24, D5=>mdout1_5_24, 
+            D6=>mdout1_6_24, D7=>mdout1_7_24, D8=>mdout1_8_24, 
+            D9=>mdout1_9_24, D10=>mdout1_10_24, D11=>mdout1_11_24, 
+            D12=>mdout1_12_24, D13=>mdout1_13_24, D14=>mdout1_14_24, 
+            D15=>mdout1_15_24, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(24));
+
+    mux_10: MUX161
+        port map (D0=>mdout1_0_25, D1=>mdout1_1_25, D2=>mdout1_2_25, 
+            D3=>mdout1_3_25, D4=>mdout1_4_25, D5=>mdout1_5_25, 
+            D6=>mdout1_6_25, D7=>mdout1_7_25, D8=>mdout1_8_25, 
+            D9=>mdout1_9_25, D10=>mdout1_10_25, D11=>mdout1_11_25, 
+            D12=>mdout1_12_25, D13=>mdout1_13_25, D14=>mdout1_14_25, 
+            D15=>mdout1_15_25, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(25));
+
+    mux_9: MUX161
+        port map (D0=>mdout1_0_26, D1=>mdout1_1_26, D2=>mdout1_2_26, 
+            D3=>mdout1_3_26, D4=>mdout1_4_26, D5=>mdout1_5_26, 
+            D6=>mdout1_6_26, D7=>mdout1_7_26, D8=>mdout1_8_26, 
+            D9=>mdout1_9_26, D10=>mdout1_10_26, D11=>mdout1_11_26, 
+            D12=>mdout1_12_26, D13=>mdout1_13_26, D14=>mdout1_14_26, 
+            D15=>mdout1_15_26, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(26));
+
+    mux_8: MUX161
+        port map (D0=>mdout1_0_27, D1=>mdout1_1_27, D2=>mdout1_2_27, 
+            D3=>mdout1_3_27, D4=>mdout1_4_27, D5=>mdout1_5_27, 
+            D6=>mdout1_6_27, D7=>mdout1_7_27, D8=>mdout1_8_27, 
+            D9=>mdout1_9_27, D10=>mdout1_10_27, D11=>mdout1_11_27, 
+            D12=>mdout1_12_27, D13=>mdout1_13_27, D14=>mdout1_14_27, 
+            D15=>mdout1_15_27, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(27));
+
+    mux_7: MUX161
+        port map (D0=>mdout1_0_28, D1=>mdout1_1_28, D2=>mdout1_2_28, 
+            D3=>mdout1_3_28, D4=>mdout1_4_28, D5=>mdout1_5_28, 
+            D6=>mdout1_6_28, D7=>mdout1_7_28, D8=>mdout1_8_28, 
+            D9=>mdout1_9_28, D10=>mdout1_10_28, D11=>mdout1_11_28, 
+            D12=>mdout1_12_28, D13=>mdout1_13_28, D14=>mdout1_14_28, 
+            D15=>mdout1_15_28, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(28));
+
+    mux_6: MUX161
+        port map (D0=>mdout1_0_29, D1=>mdout1_1_29, D2=>mdout1_2_29, 
+            D3=>mdout1_3_29, D4=>mdout1_4_29, D5=>mdout1_5_29, 
+            D6=>mdout1_6_29, D7=>mdout1_7_29, D8=>mdout1_8_29, 
+            D9=>mdout1_9_29, D10=>mdout1_10_29, D11=>mdout1_11_29, 
+            D12=>mdout1_12_29, D13=>mdout1_13_29, D14=>mdout1_14_29, 
+            D15=>mdout1_15_29, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(29));
+
+    mux_5: MUX161
+        port map (D0=>mdout1_0_30, D1=>mdout1_1_30, D2=>mdout1_2_30, 
+            D3=>mdout1_3_30, D4=>mdout1_4_30, D5=>mdout1_5_30, 
+            D6=>mdout1_6_30, D7=>mdout1_7_30, D8=>mdout1_8_30, 
+            D9=>mdout1_9_30, D10=>mdout1_10_30, D11=>mdout1_11_30, 
+            D12=>mdout1_12_30, D13=>mdout1_13_30, D14=>mdout1_14_30, 
+            D15=>mdout1_15_30, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(30));
+
+    mux_4: MUX161
+        port map (D0=>mdout1_0_31, D1=>mdout1_1_31, D2=>mdout1_2_31, 
+            D3=>mdout1_3_31, D4=>mdout1_4_31, D5=>mdout1_5_31, 
+            D6=>mdout1_6_31, D7=>mdout1_7_31, D8=>mdout1_8_31, 
+            D9=>mdout1_9_31, D10=>mdout1_10_31, D11=>mdout1_11_31, 
+            D12=>mdout1_12_31, D13=>mdout1_13_31, D14=>mdout1_14_31, 
+            D15=>mdout1_15_31, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(31));
+
+    mux_3: MUX161
+        port map (D0=>mdout1_0_32, D1=>mdout1_1_32, D2=>mdout1_2_32, 
+            D3=>mdout1_3_32, D4=>mdout1_4_32, D5=>mdout1_5_32, 
+            D6=>mdout1_6_32, D7=>mdout1_7_32, D8=>mdout1_8_32, 
+            D9=>mdout1_9_32, D10=>mdout1_10_32, D11=>mdout1_11_32, 
+            D12=>mdout1_12_32, D13=>mdout1_13_32, D14=>mdout1_14_32, 
+            D15=>mdout1_15_32, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(32));
+
+    mux_2: MUX161
+        port map (D0=>mdout1_0_33, D1=>mdout1_1_33, D2=>mdout1_2_33, 
+            D3=>mdout1_3_33, D4=>mdout1_4_33, D5=>mdout1_5_33, 
+            D6=>mdout1_6_33, D7=>mdout1_7_33, D8=>mdout1_8_33, 
+            D9=>mdout1_9_33, D10=>mdout1_10_33, D11=>mdout1_11_33, 
+            D12=>mdout1_12_33, D13=>mdout1_13_33, D14=>mdout1_14_33, 
+            D15=>mdout1_15_33, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(33));
+
+    mux_1: MUX161
+        port map (D0=>mdout1_0_34, D1=>mdout1_1_34, D2=>mdout1_2_34, 
+            D3=>mdout1_3_34, D4=>mdout1_4_34, D5=>mdout1_5_34, 
+            D6=>mdout1_6_34, D7=>mdout1_7_34, D8=>mdout1_8_34, 
+            D9=>mdout1_9_34, D10=>mdout1_10_34, D11=>mdout1_11_34, 
+            D12=>mdout1_12_34, D13=>mdout1_13_34, D14=>mdout1_14_34, 
+            D15=>mdout1_15_34, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(34));
+
+    mux_0: MUX161
+        port map (D0=>mdout1_0_35, D1=>mdout1_1_35, D2=>mdout1_2_35, 
+            D3=>mdout1_3_35, D4=>mdout1_4_35, D5=>mdout1_5_35, 
+            D6=>mdout1_6_35, D7=>mdout1_7_35, D8=>mdout1_8_35, 
+            D9=>mdout1_9_35, D10=>mdout1_10_35, D11=>mdout1_11_35, 
+            D12=>mdout1_12_35, D13=>mdout1_13_35, D14=>mdout1_14_35, 
+            D15=>mdout1_15_35, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(35));
+
+    precin_inst1073: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"0000", 
+        INIT0=> X"0000")
+        port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>precin);
+
+    wcnt_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>cnt_con, A1=>wcount_0, B0=>cnt_con_inv, B1=>rptr_0, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>precin, S0=>open, S1=>wcnt_sub_0, COUT=>co0_5);
+
+    wcnt_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_1, A1=>wcount_2, B0=>rptr_1, B1=>rptr_2, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co0_5, S0=>wcnt_sub_1, S1=>wcnt_sub_2, COUT=>co1_5);
+
+    wcnt_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_3, A1=>wcount_4, B0=>rptr_3, B1=>rptr_4, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co1_5, S0=>wcnt_sub_3, S1=>wcnt_sub_4, COUT=>co2_5);
+
+    wcnt_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_5, A1=>wcount_6, B0=>rptr_5, B1=>rptr_6, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co2_5, S0=>wcnt_sub_5, S1=>wcnt_sub_6, COUT=>co3_5);
+
+    wcnt_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_7, A1=>wcount_8, B0=>rptr_7, B1=>rptr_8, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co3_5, S0=>wcnt_sub_7, S1=>wcnt_sub_8, COUT=>co4_5);
+
+    wcnt_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_9, A1=>wcount_10, B0=>rptr_9, B1=>rptr_10, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co4_5, S0=>wcnt_sub_9, S1=>wcnt_sub_10, COUT=>co5_5);
+
+    wcnt_6: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_11, A1=>wcount_12, B0=>rptr_11, B1=>rptr_12, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co5_5, S0=>wcnt_sub_11, S1=>wcnt_sub_12, COUT=>co6_5);
+
+    wcnt_7: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_13, A1=>wcount_14, B0=>rptr_13, B1=>rptr_14, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co6_5, S0=>wcnt_sub_13, S1=>wcnt_sub_14, COUT=>co7_3);
+
+    wcnt_8: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co7_3, S0=>wcnt_sub_15, S1=>open, 
+            COUT=>open);
+
+    af_set_cmp_ci_a: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_2);
+
+    af_set_cmp_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0), 
+            B1=>AmFullThresh(1), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>cmp_ci_2, S0=>open, 
+            S1=>open, COUT=>co0_6);
+
+    af_set_cmp_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2), 
+            B1=>AmFullThresh(3), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co0_6, S0=>open, S1=>open, 
+            COUT=>co1_6);
+
+    af_set_cmp_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4), 
+            B1=>AmFullThresh(5), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co1_6, S0=>open, S1=>open, 
+            COUT=>co2_6);
+
+    af_set_cmp_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6), 
+            B1=>AmFullThresh(7), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co2_6, S0=>open, S1=>open, 
+            COUT=>co3_6);
+
+    af_set_cmp_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8), 
+            B1=>AmFullThresh(9), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co3_6, S0=>open, S1=>open, 
+            COUT=>co4_6);
+
+    af_set_cmp_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_10, A1=>wcnt_reg_11, B0=>AmFullThresh(10), 
+            B1=>AmFullThresh(11), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co4_6, S0=>open, S1=>open, 
+            COUT=>co5_6);
+
+    af_set_cmp_6: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_12, A1=>wcnt_reg_13, B0=>AmFullThresh(12), 
+            B1=>AmFullThresh(13), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co5_6, S0=>open, S1=>open, 
+            COUT=>co6_6);
+
+    af_set_cmp_7: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_14, A1=>wcnt_reg_15, B0=>AmFullThresh(14), 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co6_6, S0=>open, S1=>open, 
+            COUT=>af_set_c);
+
+    scuba_vhi_inst: VHI
+        port map (Z=>scuba_vhi);
+
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    a2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>af_set_c, S0=>af_set, S1=>open, 
+            COUT=>open);
+
+    WCNT(0) <= fcount_0;
+    WCNT(1) <= fcount_1;
+    WCNT(2) <= fcount_2;
+    WCNT(3) <= fcount_3;
+    WCNT(4) <= fcount_4;
+    WCNT(5) <= fcount_5;
+    WCNT(6) <= fcount_6;
+    WCNT(7) <= fcount_7;
+    WCNT(8) <= fcount_8;
+    WCNT(9) <= fcount_9;
+    WCNT(10) <= fcount_10;
+    WCNT(11) <= fcount_11;
+    WCNT(12) <= fcount_12;
+    WCNT(13) <= fcount_13;
+    WCNT(14) <= fcount_14;
+    WCNT(15) <= fcount_15;
+    Empty <= empty_i;
+    Full <= full_i;
+end Structure;

diff --git a/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg_ngd.asd b/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg_ngd.asd
new file mode 100644 (file)
index 0000000..c265c78
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg_ngd.asd
@@ -0,0 +1 @@
+[ActiveSupport NGD]

diff --git a/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.cst b/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.cst
new file mode 100644 (file)
index 0000000..4204e1d
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.cst
@@ -0,0 +1,3 @@
+Date=03/18/2015
+Time=14:41:29
+

diff --git a/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.edn b/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.edn
new file mode 100644 (file)
index 0000000..8bd1ced
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.edn
@@ -0,0 +1,4721 @@
+(edif fifo_36x4k_oreg
+  (edifVersion 2 0 0)
+  (edifLevel 0)
+  (keywordMap (keywordLevel 0))
+  (status
+    (written
+      (timestamp 2015 3 18 14 41 31)
+      (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80"))))
+      (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x4k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 4096 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.fdc ")
+  (library ORCLIB
+    (edifLevel 0)
+    (technology
+      (numberDefinition))
+    (cell CCU2C
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A0
+            (direction INPUT))
+          (port A1
+            (direction INPUT))
+          (port B0
+            (direction INPUT))
+          (port B1
+            (direction INPUT))
+          (port C0
+            (direction INPUT))
+          (port C1
+            (direction INPUT))
+          (port D0
+            (direction INPUT))
+          (port D1
+            (direction INPUT))
+          (port CIN
+            (direction INPUT))
+          (port S0
+            (direction OUTPUT))
+          (port S1
+            (direction OUTPUT))
+          (port COUT
+            (direction OUTPUT)))))
+    (cell AND2
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A
+            (direction INPUT))
+          (port B
+            (direction INPUT))
+          (port Z
+            (direction OUTPUT)))))
+    (cell FD1P3BX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port SP
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port PD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell FD1P3DX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port SP
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port CD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell FD1S3BX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port PD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell FD1S3DX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port CD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell INV
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A
+            (direction INPUT))
+          (port Z
+            (direction OUTPUT)))))
+    (cell MUX21
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D0
+            (direction INPUT))
+          (port D1
+            (direction INPUT))
+          (port SD
+            (direction INPUT))
+          (port Z
+            (direction OUTPUT)))))
+    (cell ROM16X1A
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port AD3
+            (direction INPUT))
+          (port AD2
+            (direction INPUT))
+          (port AD1
+            (direction INPUT))
+          (port AD0
+            (direction INPUT))
+          (port DO0
+            (direction OUTPUT)))))
+    (cell VHI
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port Z
+            (direction OUTPUT)))))
+    (cell VLO
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port Z
+            (direction OUTPUT)))))
+    (cell XOR2
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A
+            (direction INPUT))
+          (port B
+            (direction INPUT))
+          (port Z
+            (direction OUTPUT)))))
+    (cell DP16KD
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port DIA17
+            (direction INPUT))
+          (port DIA16
+            (direction INPUT))
+          (port DIA15
+            (direction INPUT))
+          (port DIA14
+            (direction INPUT))
+          (port DIA13
+            (direction INPUT))
+          (port DIA12
+            (direction INPUT))
+          (port DIA11
+            (direction INPUT))
+          (port DIA10
+            (direction INPUT))
+          (port DIA9
+            (direction INPUT))
+          (port DIA8
+            (direction INPUT))
+          (port DIA7
+            (direction INPUT))
+          (port DIA6
+            (direction INPUT))
+          (port DIA5
+            (direction INPUT))
+          (port DIA4
+            (direction INPUT))
+          (port DIA3
+            (direction INPUT))
+          (port DIA2
+            (direction INPUT))
+          (port DIA1
+            (direction INPUT))
+          (port DIA0
+            (direction INPUT))
+          (port ADA13
+            (direction INPUT))
+          (port ADA12
+            (direction INPUT))
+          (port ADA11
+            (direction INPUT))
+          (port ADA10
+            (direction INPUT))
+          (port ADA9
+            (direction INPUT))
+          (port ADA8
+            (direction INPUT))
+          (port ADA7
+            (direction INPUT))
+          (port ADA6
+            (direction INPUT))
+          (port ADA5
+            (direction INPUT))
+          (port ADA4
+            (direction INPUT))
+          (port ADA3
+            (direction INPUT))
+          (port ADA2
+            (direction INPUT))
+          (port ADA1
+            (direction INPUT))
+          (port ADA0
+            (direction INPUT))
+          (port CEA
+            (direction INPUT))
+          (port OCEA
+            (direction INPUT))
+          (port CLKA
+            (direction INPUT))
+          (port WEA
+            (direction INPUT))
+          (port CSA2
+            (direction INPUT))
+          (port CSA1
+            (direction INPUT))
+          (port CSA0
+            (direction INPUT))
+          (port RSTA
+            (direction INPUT))
+          (port DIB17
+            (direction INPUT))
+          (port DIB16
+            (direction INPUT))
+          (port DIB15
+            (direction INPUT))
+          (port DIB14
+            (direction INPUT))
+          (port DIB13
+            (direction INPUT))
+          (port DIB12
+            (direction INPUT))
+          (port DIB11
+            (direction INPUT))
+          (port DIB10
+            (direction INPUT))
+          (port DIB9
+            (direction INPUT))
+          (port DIB8
+            (direction INPUT))
+          (port DIB7
+            (direction INPUT))
+          (port DIB6
+            (direction INPUT))
+          (port DIB5
+            (direction INPUT))
+          (port DIB4
+            (direction INPUT))
+          (port DIB3
+            (direction INPUT))
+          (port DIB2
+            (direction INPUT))
+          (port DIB1
+            (direction INPUT))
+          (port DIB0
+            (direction INPUT))
+          (port ADB13
+            (direction INPUT))
+          (port ADB12
+            (direction INPUT))
+          (port ADB11
+            (direction INPUT))
+          (port ADB10
+            (direction INPUT))
+          (port ADB9
+            (direction INPUT))
+          (port ADB8
+            (direction INPUT))
+          (port ADB7
+            (direction INPUT))
+          (port ADB6
+            (direction INPUT))
+          (port ADB5
+            (direction INPUT))
+          (port ADB4
+            (direction INPUT))
+          (port ADB3
+            (direction INPUT))
+          (port ADB2
+            (direction INPUT))
+          (port ADB1
+            (direction INPUT))
+          (port ADB0
+            (direction INPUT))
+          (port CEB
+            (direction INPUT))
+          (port OCEB
+            (direction INPUT))
+          (port CLKB
+            (direction INPUT))
+          (port WEB
+            (direction INPUT))
+          (port CSB2
+            (direction INPUT))
+          (port CSB1
+            (direction INPUT))
+          (port CSB0
+            (direction INPUT))
+          (port RSTB
+            (direction INPUT))
+          (port DOA17
+            (direction OUTPUT))
+          (port DOA16
+            (direction OUTPUT))
+          (port DOA15
+            (direction OUTPUT))
+          (port DOA14
+            (direction OUTPUT))
+          (port DOA13
+            (direction OUTPUT))
+          (port DOA12
+            (direction OUTPUT))
+          (port DOA11
+            (direction OUTPUT))
+          (port DOA10
+            (direction OUTPUT))
+          (port DOA9
+            (direction OUTPUT))
+          (port DOA8
+            (direction OUTPUT))
+          (port DOA7
+            (direction OUTPUT))
+          (port DOA6
+            (direction OUTPUT))
+          (port DOA5
+            (direction OUTPUT))
+          (port DOA4
+            (direction OUTPUT))
+          (port DOA3
+            (direction OUTPUT))
+          (port DOA2
+            (direction OUTPUT))
+          (port DOA1
+            (direction OUTPUT))
+          (port DOA0
+            (direction OUTPUT))
+          (port DOB17
+            (direction OUTPUT))
+          (port DOB16
+            (direction OUTPUT))
+          (port DOB15
+            (direction OUTPUT))
+          (port DOB14
+            (direction OUTPUT))
+          (port DOB13
+            (direction OUTPUT))
+          (port DOB12
+            (direction OUTPUT))
+          (port DOB11
+            (direction OUTPUT))
+          (port DOB10
+            (direction OUTPUT))
+          (port DOB9
+            (direction OUTPUT))
+          (port DOB8
+            (direction OUTPUT))
+          (port DOB7
+            (direction OUTPUT))
+          (port DOB6
+            (direction OUTPUT))
+          (port DOB5
+            (direction OUTPUT))
+          (port DOB4
+            (direction OUTPUT))
+          (port DOB3
+            (direction OUTPUT))
+          (port DOB2
+            (direction OUTPUT))
+          (port DOB1
+            (direction OUTPUT))
+          (port DOB0
+            (direction OUTPUT)))))
+    (cell fifo_36x4k_oreg
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port (array (rename Data "Data(35:0)") 36)
+            (direction INPUT))
+          (port Clock
+            (direction INPUT))
+          (port WrEn
+            (direction INPUT))
+          (port RdEn
+            (direction INPUT))
+          (port Reset
+            (direction INPUT))
+          (port (array (rename AmFullThresh "AmFullThresh(11:0)") 12)
+            (direction INPUT))
+          (port (array (rename Q "Q(35:0)") 36)
+            (direction OUTPUT))
+          (port (array (rename WCNT "WCNT(12:0)") 13)
+            (direction OUTPUT))
+          (port Empty
+            (direction OUTPUT))
+          (port Full
+            (direction OUTPUT))
+          (port AlmostFull
+            (direction OUTPUT)))
+        (property NGD_DRC_MASK (integer 1))
+        (contents
+          (instance AND2_t5
+            (viewRef view1 
+              (cellRef AND2)))
+          (instance INV_5
+            (viewRef view1 
+              (cellRef INV)))
+          (instance AND2_t4
+            (viewRef view1 
+              (cellRef AND2)))
+          (instance INV_4
+            (viewRef view1 
+              (cellRef INV)))
+          (instance AND2_t3
+            (viewRef view1 
+              (cellRef AND2)))
+          (instance XOR2_t2
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance INV_3
+            (viewRef view1 
+              (cellRef INV)))
+          (instance INV_2
+            (viewRef view1 
+              (cellRef INV)))
+          (instance LUT4_1
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x3232")))
+          (instance LUT4_0
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x3232")))
+          (instance AND2_t1
+            (viewRef view1 
+              (cellRef AND2)))
+          (instance INV_1
+            (viewRef view1 
+              (cellRef INV)))
+          (instance XOR2_t0
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance INV_0
+            (viewRef view1 
+              (cellRef INV)))
+          (instance pdp_ram_0_0_7
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x4k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b000"))
+            (property CSDECODE_A
+              (string "0b000"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_0_1_6
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x4k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b000"))
+            (property CSDECODE_A
+              (string "0b000"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_0_2_5
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x4k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b000"))
+            (property CSDECODE_A
+              (string "0b000"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_0_3_4
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x4k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b000"))
+            (property CSDECODE_A
+              (string "0b000"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_1_0_3
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x4k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_1_1_2
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x4k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_1_2_1
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x4k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_1_3_0
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x4k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance FF_82
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_81
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_80
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_79
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_78
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_77
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_76
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_75
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_74
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_73
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_72
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_71
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_70
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_69
+            (viewRef view1 
+              (cellRef FD1S3BX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_68
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_67
+            (viewRef view1 
+              (cellRef FD1P3BX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_66
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_65
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_64
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_63
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_62
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_61
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_60
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_59
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_58
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_57
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_56
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_55
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_54
+            (viewRef view1 
+              (cellRef FD1P3BX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_53
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_52
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_51
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_50
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_49
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_48
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_47
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_46
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_45
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_44
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_43
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_42
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_41
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_40
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_39
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_38
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_37
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_36
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_35
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_34
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_33
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_32
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_31
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_30
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_29
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_28
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_27
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_26
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_25
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_24
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_23
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_22
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_21
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_20
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_19
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_18
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_17
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_16
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_15
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_14
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_13
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_12
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_11
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_10
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_9
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_8
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_7
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_6
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_5
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_4
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_3
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_2
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_1
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_0
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance bdcnt_bctr_cia
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance bdcnt_bctr_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_6
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_ci_a
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance e_cmp_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_6
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance a0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance g_cmp_ci_a
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance g_cmp_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_6
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance a1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_cia
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_6
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_cia
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_6
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance mux_35
+            (viewRef view1 
+              (cellRef MUX21)))
+          (instance mux_34
+            (viewRef view1 
+              (cellRef MUX21)))
+          (instance mux_33
+            (viewRef view1 
+              (cellRef MUX21)))
+          (instance mux_32
+            (viewRef view1 
+              (cellRef MUX21)))
+          (instance mux_31
+            (viewRef view1 
+              (cellRef MUX21)))
+          (instance mux_30
+            (viewRef view1 
+              (cellRef MUX21)))
+          (instance mux_29
+            (viewRef view1 
+              (cellRef MUX21)))
+          (instance mux_28
+            (viewRef view1 
+              (cellRef MUX21)))
+          (instance mux_27
+            (viewRef view1 
+              (cellRef MUX21)))
+          (instance mux_26
+            (viewRef view1 
+              (cellRef MUX21)))
+          (instance mux_25
+            (viewRef view1 
+              (cellRef MUX21)))
+          (instance mux_24
+            (viewRef view1 
+              (cellRef MUX21)))
+          (instance mux_23
+            (viewRef view1 
+              (cellRef MUX21)))
+          (instance mux_22
+            (viewRef view1 
+              (cellRef MUX21)))
+          (instance mux_21
+            (viewRef view1 
+              (cellRef MUX21)))
+          (instance mux_20
+            (viewRef view1 
+              (cellRef MUX21)))
+          (instance mux_19
+            (viewRef view1 
+              (cellRef MUX21)))
+          (instance mux_18
+            (viewRef view1 
+              (cellRef MUX21)))
+          (instance mux_17
+            (viewRef view1 
+              (cellRef MUX21)))
+          (instance mux_16
+            (viewRef view1 
+              (cellRef MUX21)))
+          (instance mux_15
+            (viewRef view1 
+              (cellRef MUX21)))
+          (instance mux_14
+            (viewRef view1 
+              (cellRef MUX21)))
+          (instance mux_13
+            (viewRef view1 
+              (cellRef MUX21)))
+          (instance mux_12
+            (viewRef view1 
+              (cellRef MUX21)))
+          (instance mux_11
+            (viewRef view1 
+              (cellRef MUX21)))
+          (instance mux_10
+            (viewRef view1 
+              (cellRef MUX21)))
+          (instance mux_9
+            (viewRef view1 
+              (cellRef MUX21)))
+          (instance mux_8
+            (viewRef view1 
+              (cellRef MUX21)))
+          (instance mux_7
+            (viewRef view1 
+              (cellRef MUX21)))
+          (instance mux_6
+            (viewRef view1 
+              (cellRef MUX21)))
+          (instance mux_5
+            (viewRef view1 
+              (cellRef MUX21)))
+          (instance mux_4
+            (viewRef view1 
+              (cellRef MUX21)))
+          (instance mux_3
+            (viewRef view1 
+              (cellRef MUX21)))
+          (instance mux_2
+            (viewRef view1 
+              (cellRef MUX21)))
+          (instance mux_1
+            (viewRef view1 
+              (cellRef MUX21)))
+          (instance mux_0
+            (viewRef view1 
+              (cellRef MUX21)))
+          (instance precin_inst389
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x0000"))
+            (property INIT0
+              (string "0x0000")))
+          (instance wcnt_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_6
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcntd
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance af_set_cmp_ci_a
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance af_set_cmp_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_6
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance scuba_vhi_inst
+            (viewRef view1 
+              (cellRef VHI)))
+          (instance scuba_vlo_inst
+            (viewRef view1 
+              (cellRef VLO)))
+          (instance a2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (net invout_2
+            (joined
+              (portRef Z (instanceRef INV_5))
+              (portRef B (instanceRef AND2_t5))))
+          (net invout_1
+            (joined
+              (portRef Z (instanceRef INV_4))
+              (portRef B (instanceRef AND2_t4))))
+          (net rden_i_inv
+            (joined
+              (portRef Z (instanceRef INV_3))
+              (portRef B (instanceRef AND2_t3))))
+          (net invout_0
+            (joined
+              (portRef Z (instanceRef INV_1))
+              (portRef B (instanceRef AND2_t1))))
+          (net r_nw
+            (joined
+              (portRef Z (instanceRef AND2_t1))))
+          (net fcnt_en
+            (joined
+              (portRef SP (instanceRef FF_70))
+              (portRef Z (instanceRef XOR2_t2))
+              (portRef SP (instanceRef FF_82))
+              (portRef SP (instanceRef FF_81))
+              (portRef SP (instanceRef FF_80))
+              (portRef SP (instanceRef FF_79))
+              (portRef SP (instanceRef FF_78))
+              (portRef SP (instanceRef FF_77))
+              (portRef SP (instanceRef FF_76))
+              (portRef SP (instanceRef FF_75))
+              (portRef SP (instanceRef FF_74))
+              (portRef SP (instanceRef FF_73))
+              (portRef SP (instanceRef FF_72))
+              (portRef SP (instanceRef FF_71))))
+          (net empty_d
+            (joined
+              (portRef D (instanceRef FF_69))
+              (portRef DO0 (instanceRef LUT4_1))))
+          (net full_d
+            (joined
+              (portRef D (instanceRef FF_68))
+              (portRef DO0 (instanceRef LUT4_0))))
+          (net wptr_0
+            (joined
+              (portRef Q (instanceRef FF_41))
+              (portRef ADA3 (instanceRef pdp_ram_0_0_7))
+              (portRef ADA3 (instanceRef pdp_ram_0_1_6))
+              (portRef ADA3 (instanceRef pdp_ram_0_2_5))
+              (portRef ADA3 (instanceRef pdp_ram_0_3_4))
+              (portRef ADA3 (instanceRef pdp_ram_1_0_3))
+              (portRef ADA3 (instanceRef pdp_ram_1_1_2))
+              (portRef ADA3 (instanceRef pdp_ram_1_2_1))
+              (portRef ADA3 (instanceRef pdp_ram_1_3_0))))
+          (net wptr_1
+            (joined
+              (portRef Q (instanceRef FF_40))
+              (portRef ADA4 (instanceRef pdp_ram_0_0_7))
+              (portRef ADA4 (instanceRef pdp_ram_0_1_6))
+              (portRef ADA4 (instanceRef pdp_ram_0_2_5))
+              (portRef ADA4 (instanceRef pdp_ram_0_3_4))
+              (portRef ADA4 (instanceRef pdp_ram_1_0_3))
+              (portRef ADA4 (instanceRef pdp_ram_1_1_2))
+              (portRef ADA4 (instanceRef pdp_ram_1_2_1))
+              (portRef ADA4 (instanceRef pdp_ram_1_3_0))))
+          (net wptr_2
+            (joined
+              (portRef Q (instanceRef FF_39))
+              (portRef ADA5 (instanceRef pdp_ram_0_0_7))
+              (portRef ADA5 (instanceRef pdp_ram_0_1_6))
+              (portRef ADA5 (instanceRef pdp_ram_0_2_5))
+              (portRef ADA5 (instanceRef pdp_ram_0_3_4))
+              (portRef ADA5 (instanceRef pdp_ram_1_0_3))
+              (portRef ADA5 (instanceRef pdp_ram_1_1_2))
+              (portRef ADA5 (instanceRef pdp_ram_1_2_1))
+              (portRef ADA5 (instanceRef pdp_ram_1_3_0))))
+          (net wptr_3
+            (joined
+              (portRef Q (instanceRef FF_38))
+              (portRef ADA6 (instanceRef pdp_ram_0_0_7))
+              (portRef ADA6 (instanceRef pdp_ram_0_1_6))
+              (portRef ADA6 (instanceRef pdp_ram_0_2_5))
+              (portRef ADA6 (instanceRef pdp_ram_0_3_4))
+              (portRef ADA6 (instanceRef pdp_ram_1_0_3))
+              (portRef ADA6 (instanceRef pdp_ram_1_1_2))
+              (portRef ADA6 (instanceRef pdp_ram_1_2_1))
+              (portRef ADA6 (instanceRef pdp_ram_1_3_0))))
+          (net wptr_4
+            (joined
+              (portRef Q (instanceRef FF_37))
+              (portRef ADA7 (instanceRef pdp_ram_0_0_7))
+              (portRef ADA7 (instanceRef pdp_ram_0_1_6))
+              (portRef ADA7 (instanceRef pdp_ram_0_2_5))
+              (portRef ADA7 (instanceRef pdp_ram_0_3_4))
+              (portRef ADA7 (instanceRef pdp_ram_1_0_3))
+              (portRef ADA7 (instanceRef pdp_ram_1_1_2))
+              (portRef ADA7 (instanceRef pdp_ram_1_2_1))
+              (portRef ADA7 (instanceRef pdp_ram_1_3_0))))
+          (net wptr_5
+            (joined
+              (portRef Q (instanceRef FF_36))
+              (portRef ADA8 (instanceRef pdp_ram_0_0_7))
+              (portRef ADA8 (instanceRef pdp_ram_0_1_6))
+              (portRef ADA8 (instanceRef pdp_ram_0_2_5))
+              (portRef ADA8 (instanceRef pdp_ram_0_3_4))
+              (portRef ADA8 (instanceRef pdp_ram_1_0_3))
+              (portRef ADA8 (instanceRef pdp_ram_1_1_2))
+              (portRef ADA8 (instanceRef pdp_ram_1_2_1))
+              (portRef ADA8 (instanceRef pdp_ram_1_3_0))))
+          (net wptr_6
+            (joined
+              (portRef Q (instanceRef FF_35))
+              (portRef ADA9 (instanceRef pdp_ram_0_0_7))
+              (portRef ADA9 (instanceRef pdp_ram_0_1_6))
+              (portRef ADA9 (instanceRef pdp_ram_0_2_5))
+              (portRef ADA9 (instanceRef pdp_ram_0_3_4))
+              (portRef ADA9 (instanceRef pdp_ram_1_0_3))
+              (portRef ADA9 (instanceRef pdp_ram_1_1_2))
+              (portRef ADA9 (instanceRef pdp_ram_1_2_1))
+              (portRef ADA9 (instanceRef pdp_ram_1_3_0))))
+          (net wptr_7
+            (joined
+              (portRef Q (instanceRef FF_34))
+              (portRef ADA10 (instanceRef pdp_ram_0_0_7))
+              (portRef ADA10 (instanceRef pdp_ram_0_1_6))
+              (portRef ADA10 (instanceRef pdp_ram_0_2_5))
+              (portRef ADA10 (instanceRef pdp_ram_0_3_4))
+              (portRef ADA10 (instanceRef pdp_ram_1_0_3))
+              (portRef ADA10 (instanceRef pdp_ram_1_1_2))
+              (portRef ADA10 (instanceRef pdp_ram_1_2_1))
+              (portRef ADA10 (instanceRef pdp_ram_1_3_0))))
+          (net wptr_8
+            (joined
+              (portRef Q (instanceRef FF_33))
+              (portRef ADA11 (instanceRef pdp_ram_0_0_7))
+              (portRef ADA11 (instanceRef pdp_ram_0_1_6))
+              (portRef ADA11 (instanceRef pdp_ram_0_2_5))
+              (portRef ADA11 (instanceRef pdp_ram_0_3_4))
+              (portRef ADA11 (instanceRef pdp_ram_1_0_3))
+              (portRef ADA11 (instanceRef pdp_ram_1_1_2))
+              (portRef ADA11 (instanceRef pdp_ram_1_2_1))
+              (portRef ADA11 (instanceRef pdp_ram_1_3_0))))
+          (net wptr_9
+            (joined
+              (portRef Q (instanceRef FF_32))
+              (portRef ADA12 (instanceRef pdp_ram_0_0_7))
+              (portRef ADA12 (instanceRef pdp_ram_0_1_6))
+              (portRef ADA12 (instanceRef pdp_ram_0_2_5))
+              (portRef ADA12 (instanceRef pdp_ram_0_3_4))
+              (portRef ADA12 (instanceRef pdp_ram_1_0_3))
+              (portRef ADA12 (instanceRef pdp_ram_1_1_2))
+              (portRef ADA12 (instanceRef pdp_ram_1_2_1))
+              (portRef ADA12 (instanceRef pdp_ram_1_3_0))))
+          (net wptr_10
+            (joined
+              (portRef Q (instanceRef FF_31))
+              (portRef ADA13 (instanceRef pdp_ram_0_0_7))
+              (portRef ADA13 (instanceRef pdp_ram_0_1_6))
+              (portRef ADA13 (instanceRef pdp_ram_0_2_5))
+              (portRef ADA13 (instanceRef pdp_ram_0_3_4))
+              (portRef ADA13 (instanceRef pdp_ram_1_0_3))
+              (portRef ADA13 (instanceRef pdp_ram_1_1_2))
+              (portRef ADA13 (instanceRef pdp_ram_1_2_1))
+              (portRef ADA13 (instanceRef pdp_ram_1_3_0))))
+          (net wptr_11
+            (joined
+              (portRef Q (instanceRef FF_30))
+              (portRef CSA0 (instanceRef pdp_ram_0_0_7))
+              (portRef CSA0 (instanceRef pdp_ram_0_1_6))
+              (portRef CSA0 (instanceRef pdp_ram_0_2_5))
+              (portRef CSA0 (instanceRef pdp_ram_0_3_4))
+              (portRef CSA0 (instanceRef pdp_ram_1_0_3))
+              (portRef CSA0 (instanceRef pdp_ram_1_1_2))
+              (portRef CSA0 (instanceRef pdp_ram_1_2_1))
+              (portRef CSA0 (instanceRef pdp_ram_1_3_0))))
+          (net wptr_12
+            (joined
+              (portRef Q (instanceRef FF_29))))
+          (net rptr_12
+            (joined
+              (portRef Q (instanceRef FF_16))
+              (portRef B (instanceRef XOR2_t0))))
+          (net rptr_11_ff
+            (joined
+              (portRef D (instanceRef FF_14))
+              (portRef Q (instanceRef FF_15))))
+          (net ifcount_0
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_0))
+              (portRef D (instanceRef FF_82))))
+          (net ifcount_1
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_0))
+              (portRef D (instanceRef FF_81))))
+          (net bdcnt_bctr_ci
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_0))
+              (portRef COUT (instanceRef bdcnt_bctr_cia))))
+          (net ifcount_2
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_1))
+              (portRef D (instanceRef FF_80))))
+          (net ifcount_3
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_1))
+              (portRef D (instanceRef FF_79))))
+          (net co0
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_1))
+              (portRef COUT (instanceRef bdcnt_bctr_0))))
+          (net ifcount_4
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_2))
+              (portRef D (instanceRef FF_78))))
+          (net ifcount_5
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_2))
+              (portRef D (instanceRef FF_77))))
+          (net co1
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_2))
+              (portRef COUT (instanceRef bdcnt_bctr_1))))
+          (net ifcount_6
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_3))
+              (portRef D (instanceRef FF_76))))
+          (net ifcount_7
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_3))
+              (portRef D (instanceRef FF_75))))
+          (net co2
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_3))
+              (portRef COUT (instanceRef bdcnt_bctr_2))))
+          (net ifcount_8
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_4))
+              (portRef D (instanceRef FF_74))))
+          (net ifcount_9
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_4))
+              (portRef D (instanceRef FF_73))))
+          (net co3
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_4))
+              (portRef COUT (instanceRef bdcnt_bctr_3))))
+          (net ifcount_10
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_5))
+              (portRef D (instanceRef FF_72))))
+          (net ifcount_11
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_5))
+              (portRef D (instanceRef FF_71))))
+          (net co4
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_5))
+              (portRef COUT (instanceRef bdcnt_bctr_4))))
+          (net ifcount_12
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_6))
+              (portRef D (instanceRef FF_70))))
+          (net co6
+            (joined
+              (portRef COUT (instanceRef bdcnt_bctr_6))))
+          (net co5
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_6))
+              (portRef COUT (instanceRef bdcnt_bctr_5))))
+          (net cmp_ci
+            (joined
+              (portRef CIN (instanceRef e_cmp_0))
+              (portRef COUT (instanceRef e_cmp_ci_a))))
+          (net rden_i
+            (joined
+              (portRef A0 (instanceRef e_cmp_0))
+              (portRef Z (instanceRef AND2_t4))
+              (portRef B (instanceRef XOR2_t2))
+              (portRef A (instanceRef INV_3))
+              (portRef AD1 (instanceRef LUT4_0))
+              (portRef A (instanceRef AND2_t1))
+              (portRef CEB (instanceRef pdp_ram_0_0_7))
+              (portRef CEB (instanceRef pdp_ram_0_1_6))
+              (portRef CEB (instanceRef pdp_ram_0_2_5))
+              (portRef CEB (instanceRef pdp_ram_0_3_4))
+              (portRef CEB (instanceRef pdp_ram_1_0_3))
+              (portRef CEB (instanceRef pdp_ram_1_1_2))
+              (portRef CEB (instanceRef pdp_ram_1_2_1))
+              (portRef CEB (instanceRef pdp_ram_1_3_0))
+              (portRef SP (instanceRef FF_54))
+              (portRef SP (instanceRef FF_53))
+              (portRef SP (instanceRef FF_52))
+              (portRef SP (instanceRef FF_51))
+              (portRef SP (instanceRef FF_50))
+              (portRef SP (instanceRef FF_49))
+              (portRef SP (instanceRef FF_48))
+              (portRef SP (instanceRef FF_47))
+              (portRef SP (instanceRef FF_46))
+              (portRef SP (instanceRef FF_45))
+              (portRef SP (instanceRef FF_44))
+              (portRef SP (instanceRef FF_43))
+              (portRef SP (instanceRef FF_42))
+              (portRef SP (instanceRef FF_28))
+              (portRef SP (instanceRef FF_27))
+              (portRef SP (instanceRef FF_26))
+              (portRef SP (instanceRef FF_25))
+              (portRef SP (instanceRef FF_24))
+              (portRef SP (instanceRef FF_23))
+              (portRef SP (instanceRef FF_22))
+              (portRef SP (instanceRef FF_21))
+              (portRef SP (instanceRef FF_20))
+              (portRef SP (instanceRef FF_19))
+              (portRef SP (instanceRef FF_18))
+              (portRef SP (instanceRef FF_17))
+              (portRef SP (instanceRef FF_16))
+              (portRef SP (instanceRef FF_15))
+              (portRef SP (instanceRef FF_14))))
+          (net co0_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_1))
+              (portRef COUT (instanceRef e_cmp_0))))
+          (net co1_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_2))
+              (portRef COUT (instanceRef e_cmp_1))))
+          (net co2_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_3))
+              (portRef COUT (instanceRef e_cmp_2))))
+          (net co3_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_4))
+              (portRef COUT (instanceRef e_cmp_3))))
+          (net co4_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_5))
+              (portRef COUT (instanceRef e_cmp_4))))
+          (net co5_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_6))
+              (portRef COUT (instanceRef e_cmp_5))))
+          (net cmp_le_1
+            (joined
+              (portRef S0 (instanceRef a0))
+              (portRef AD2 (instanceRef LUT4_1))))
+          (net cmp_le_1_c
+            (joined
+              (portRef CIN (instanceRef a0))
+              (portRef COUT (instanceRef e_cmp_6))))
+          (net cmp_ci_1
+            (joined
+              (portRef CIN (instanceRef g_cmp_0))
+              (portRef COUT (instanceRef g_cmp_ci_a))))
+          (net co0_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_1))
+              (portRef COUT (instanceRef g_cmp_0))))
+          (net co1_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_2))
+              (portRef COUT (instanceRef g_cmp_1))))
+          (net co2_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_3))
+              (portRef COUT (instanceRef g_cmp_2))))
+          (net co3_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_4))
+              (portRef COUT (instanceRef g_cmp_3))))
+          (net co4_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_5))
+              (portRef COUT (instanceRef g_cmp_4))))
+          (net co5_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_6))
+              (portRef COUT (instanceRef g_cmp_5))))
+          (net wren_i_inv
+            (joined
+              (portRef B0 (instanceRef g_cmp_6))
+              (portRef Z (instanceRef INV_2))))
+          (net cmp_ge_d1
+            (joined
+              (portRef S0 (instanceRef a1))
+              (portRef AD2 (instanceRef LUT4_0))))
+          (net cmp_ge_d1_c
+            (joined
+              (portRef CIN (instanceRef a1))
+              (portRef COUT (instanceRef g_cmp_6))))
+          (net iwcount_0
+            (joined
+              (portRef S0 (instanceRef w_ctr_0))
+              (portRef D (instanceRef FF_67))))
+          (net iwcount_1
+            (joined
+              (portRef S1 (instanceRef w_ctr_0))
+              (portRef D (instanceRef FF_66))))
+          (net w_ctr_ci
+            (joined
+              (portRef CIN (instanceRef w_ctr_0))
+              (portRef COUT (instanceRef w_ctr_cia))))
+          (net iwcount_2
+            (joined
+              (portRef S0 (instanceRef w_ctr_1))
+              (portRef D (instanceRef FF_65))))
+          (net iwcount_3
+            (joined
+              (portRef S1 (instanceRef w_ctr_1))
+              (portRef D (instanceRef FF_64))))
+          (net co0_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_1))
+              (portRef COUT (instanceRef w_ctr_0))))
+          (net iwcount_4
+            (joined
+              (portRef S0 (instanceRef w_ctr_2))
+              (portRef D (instanceRef FF_63))))
+          (net iwcount_5
+            (joined
+              (portRef S1 (instanceRef w_ctr_2))
+              (portRef D (instanceRef FF_62))))
+          (net co1_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_2))
+              (portRef COUT (instanceRef w_ctr_1))))
+          (net iwcount_6
+            (joined
+              (portRef S0 (instanceRef w_ctr_3))
+              (portRef D (instanceRef FF_61))))
+          (net iwcount_7
+            (joined
+              (portRef S1 (instanceRef w_ctr_3))
+              (portRef D (instanceRef FF_60))))
+          (net co2_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_3))
+              (portRef COUT (instanceRef w_ctr_2))))
+          (net iwcount_8
+            (joined
+              (portRef S0 (instanceRef w_ctr_4))
+              (portRef D (instanceRef FF_59))))
+          (net iwcount_9
+            (joined
+              (portRef S1 (instanceRef w_ctr_4))
+              (portRef D (instanceRef FF_58))))
+          (net co3_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_4))
+              (portRef COUT (instanceRef w_ctr_3))))
+          (net iwcount_10
+            (joined
+              (portRef S0 (instanceRef w_ctr_5))
+              (portRef D (instanceRef FF_57))))
+          (net iwcount_11
+            (joined
+              (portRef S1 (instanceRef w_ctr_5))
+              (portRef D (instanceRef FF_56))))
+          (net co4_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_5))
+              (portRef COUT (instanceRef w_ctr_4))))
+          (net iwcount_12
+            (joined
+              (portRef S0 (instanceRef w_ctr_6))
+              (portRef D (instanceRef FF_55))))
+          (net co6_1
+            (joined
+              (portRef COUT (instanceRef w_ctr_6))))
+          (net co5_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_6))
+              (portRef COUT (instanceRef w_ctr_5))))
+          (net wcount_12
+            (joined
+              (portRef A0 (instanceRef w_ctr_6))
+              (portRef A (instanceRef XOR2_t0))
+              (portRef Q (instanceRef FF_55))
+              (portRef D (instanceRef FF_29))))
+          (net ircount_0
+            (joined
+              (portRef S0 (instanceRef r_ctr_0))
+              (portRef D (instanceRef FF_54))))
+          (net ircount_1
+            (joined
+              (portRef S1 (instanceRef r_ctr_0))
+              (portRef D (instanceRef FF_53))))
+          (net r_ctr_ci
+            (joined
+              (portRef CIN (instanceRef r_ctr_0))
+              (portRef COUT (instanceRef r_ctr_cia))))
+          (net rcount_0
+            (joined
+              (portRef A0 (instanceRef r_ctr_0))
+              (portRef Q (instanceRef FF_54))
+              (portRef D (instanceRef FF_28))))
+          (net rcount_1
+            (joined
+              (portRef A1 (instanceRef r_ctr_0))
+              (portRef Q (instanceRef FF_53))
+              (portRef D (instanceRef FF_27))))
+          (net ircount_2
+            (joined
+              (portRef S0 (instanceRef r_ctr_1))
+              (portRef D (instanceRef FF_52))))
+          (net ircount_3
+            (joined
+              (portRef S1 (instanceRef r_ctr_1))
+              (portRef D (instanceRef FF_51))))
+          (net co0_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_1))
+              (portRef COUT (instanceRef r_ctr_0))))
+          (net rcount_2
+            (joined
+              (portRef A0 (instanceRef r_ctr_1))
+              (portRef Q (instanceRef FF_52))
+              (portRef D (instanceRef FF_26))))
+          (net rcount_3
+            (joined
+              (portRef A1 (instanceRef r_ctr_1))
+              (portRef Q (instanceRef FF_51))
+              (portRef D (instanceRef FF_25))))
+          (net ircount_4
+            (joined
+              (portRef S0 (instanceRef r_ctr_2))
+              (portRef D (instanceRef FF_50))))
+          (net ircount_5
+            (joined
+              (portRef S1 (instanceRef r_ctr_2))
+              (portRef D (instanceRef FF_49))))
+          (net co1_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_2))
+              (portRef COUT (instanceRef r_ctr_1))))
+          (net rcount_4
+            (joined
+              (portRef A0 (instanceRef r_ctr_2))
+              (portRef Q (instanceRef FF_50))
+              (portRef D (instanceRef FF_24))))
+          (net rcount_5
+            (joined
+              (portRef A1 (instanceRef r_ctr_2))
+              (portRef Q (instanceRef FF_49))
+              (portRef D (instanceRef FF_23))))
+          (net ircount_6
+            (joined
+              (portRef S0 (instanceRef r_ctr_3))
+              (portRef D (instanceRef FF_48))))
+          (net ircount_7
+            (joined
+              (portRef S1 (instanceRef r_ctr_3))
+              (portRef D (instanceRef FF_47))))
+          (net co2_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_3))
+              (portRef COUT (instanceRef r_ctr_2))))
+          (net rcount_6
+            (joined
+              (portRef A0 (instanceRef r_ctr_3))
+              (portRef Q (instanceRef FF_48))
+              (portRef D (instanceRef FF_22))))
+          (net rcount_7
+            (joined
+              (portRef A1 (instanceRef r_ctr_3))
+              (portRef Q (instanceRef FF_47))
+              (portRef D (instanceRef FF_21))))
+          (net ircount_8
+            (joined
+              (portRef S0 (instanceRef r_ctr_4))
+              (portRef D (instanceRef FF_46))))
+          (net ircount_9
+            (joined
+              (portRef S1 (instanceRef r_ctr_4))
+              (portRef D (instanceRef FF_45))))
+          (net co3_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_4))
+              (portRef COUT (instanceRef r_ctr_3))))
+          (net rcount_8
+            (joined
+              (portRef A0 (instanceRef r_ctr_4))
+              (portRef Q (instanceRef FF_46))
+              (portRef D (instanceRef FF_20))))
+          (net rcount_9
+            (joined
+              (portRef A1 (instanceRef r_ctr_4))
+              (portRef Q (instanceRef FF_45))
+              (portRef D (instanceRef FF_19))))
+          (net ircount_10
+            (joined
+              (portRef S0 (instanceRef r_ctr_5))
+              (portRef D (instanceRef FF_44))))
+          (net ircount_11
+            (joined
+              (portRef S1 (instanceRef r_ctr_5))
+              (portRef D (instanceRef FF_43))))
+          (net co4_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_5))
+              (portRef COUT (instanceRef r_ctr_4))))
+          (net rcount_10
+            (joined
+              (portRef A0 (instanceRef r_ctr_5))
+              (portRef Q (instanceRef FF_44))
+              (portRef D (instanceRef FF_18))))
+          (net rcount_11
+            (joined
+              (portRef A1 (instanceRef r_ctr_5))
+              (portRef Q (instanceRef FF_43))
+              (portRef D (instanceRef FF_17))))
+          (net ircount_12
+            (joined
+              (portRef S0 (instanceRef r_ctr_6))
+              (portRef D (instanceRef FF_42))))
+          (net co6_2
+            (joined
+              (portRef COUT (instanceRef r_ctr_6))))
+          (net co5_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_6))
+              (portRef COUT (instanceRef r_ctr_5))))
+          (net rcount_12
+            (joined
+              (portRef A0 (instanceRef r_ctr_6))
+              (portRef Q (instanceRef FF_42))
+              (portRef D (instanceRef FF_16))))
+          (net mdout1_1_0
+            (joined
+              (portRef D1 (instanceRef mux_35))
+              (portRef DOB0 (instanceRef pdp_ram_1_0_3))))
+          (net mdout1_0_0
+            (joined
+              (portRef D0 (instanceRef mux_35))
+              (portRef DOB0 (instanceRef pdp_ram_0_0_7))))
+          (net mdout1_1_1
+            (joined
+              (portRef D1 (instanceRef mux_34))
+              (portRef DOB1 (instanceRef pdp_ram_1_0_3))))
+          (net mdout1_0_1
+            (joined
+              (portRef D0 (instanceRef mux_34))
+              (portRef DOB1 (instanceRef pdp_ram_0_0_7))))
+          (net mdout1_1_2
+            (joined
+              (portRef D1 (instanceRef mux_33))
+              (portRef DOB2 (instanceRef pdp_ram_1_0_3))))
+          (net mdout1_0_2
+            (joined
+              (portRef D0 (instanceRef mux_33))
+              (portRef DOB2 (instanceRef pdp_ram_0_0_7))))
+          (net mdout1_1_3
+            (joined
+              (portRef D1 (instanceRef mux_32))
+              (portRef DOB3 (instanceRef pdp_ram_1_0_3))))
+          (net mdout1_0_3
+            (joined
+              (portRef D0 (instanceRef mux_32))
+              (portRef DOB3 (instanceRef pdp_ram_0_0_7))))
+          (net mdout1_1_4
+            (joined
+              (portRef D1 (instanceRef mux_31))
+              (portRef DOB4 (instanceRef pdp_ram_1_0_3))))
+          (net mdout1_0_4
+            (joined
+              (portRef D0 (instanceRef mux_31))
+              (portRef DOB4 (instanceRef pdp_ram_0_0_7))))
+          (net mdout1_1_5
+            (joined
+              (portRef D1 (instanceRef mux_30))
+              (portRef DOB5 (instanceRef pdp_ram_1_0_3))))
+          (net mdout1_0_5
+            (joined
+              (portRef D0 (instanceRef mux_30))
+              (portRef DOB5 (instanceRef pdp_ram_0_0_7))))
+          (net mdout1_1_6
+            (joined
+              (portRef D1 (instanceRef mux_29))
+              (portRef DOB6 (instanceRef pdp_ram_1_0_3))))
+          (net mdout1_0_6
+            (joined
+              (portRef D0 (instanceRef mux_29))
+              (portRef DOB6 (instanceRef pdp_ram_0_0_7))))
+          (net mdout1_1_7
+            (joined
+              (portRef D1 (instanceRef mux_28))
+              (portRef DOB7 (instanceRef pdp_ram_1_0_3))))
+          (net mdout1_0_7
+            (joined
+              (portRef D0 (instanceRef mux_28))
+              (portRef DOB7 (instanceRef pdp_ram_0_0_7))))
+          (net mdout1_1_8
+            (joined
+              (portRef D1 (instanceRef mux_27))
+              (portRef DOB8 (instanceRef pdp_ram_1_0_3))))
+          (net mdout1_0_8
+            (joined
+              (portRef D0 (instanceRef mux_27))
+              (portRef DOB8 (instanceRef pdp_ram_0_0_7))))
+          (net mdout1_1_9
+            (joined
+              (portRef D1 (instanceRef mux_26))
+              (portRef DOB0 (instanceRef pdp_ram_1_1_2))))
+          (net mdout1_0_9
+            (joined
+              (portRef D0 (instanceRef mux_26))
+              (portRef DOB0 (instanceRef pdp_ram_0_1_6))))
+          (net mdout1_1_10
+            (joined
+              (portRef D1 (instanceRef mux_25))
+              (portRef DOB1 (instanceRef pdp_ram_1_1_2))))
+          (net mdout1_0_10
+            (joined
+              (portRef D0 (instanceRef mux_25))
+              (portRef DOB1 (instanceRef pdp_ram_0_1_6))))
+          (net mdout1_1_11
+            (joined
+              (portRef D1 (instanceRef mux_24))
+              (portRef DOB2 (instanceRef pdp_ram_1_1_2))))
+          (net mdout1_0_11
+            (joined
+              (portRef D0 (instanceRef mux_24))
+              (portRef DOB2 (instanceRef pdp_ram_0_1_6))))
+          (net mdout1_1_12
+            (joined
+              (portRef D1 (instanceRef mux_23))
+              (portRef DOB3 (instanceRef pdp_ram_1_1_2))))
+          (net mdout1_0_12
+            (joined
+              (portRef D0 (instanceRef mux_23))
+              (portRef DOB3 (instanceRef pdp_ram_0_1_6))))
+          (net mdout1_1_13
+            (joined
+              (portRef D1 (instanceRef mux_22))
+              (portRef DOB4 (instanceRef pdp_ram_1_1_2))))
+          (net mdout1_0_13
+            (joined
+              (portRef D0 (instanceRef mux_22))
+              (portRef DOB4 (instanceRef pdp_ram_0_1_6))))
+          (net mdout1_1_14
+            (joined
+              (portRef D1 (instanceRef mux_21))
+              (portRef DOB5 (instanceRef pdp_ram_1_1_2))))
+          (net mdout1_0_14
+            (joined
+              (portRef D0 (instanceRef mux_21))
+              (portRef DOB5 (instanceRef pdp_ram_0_1_6))))
+          (net mdout1_1_15
+            (joined
+              (portRef D1 (instanceRef mux_20))
+              (portRef DOB6 (instanceRef pdp_ram_1_1_2))))
+          (net mdout1_0_15
+            (joined
+              (portRef D0 (instanceRef mux_20))
+              (portRef DOB6 (instanceRef pdp_ram_0_1_6))))
+          (net mdout1_1_16
+            (joined
+              (portRef D1 (instanceRef mux_19))
+              (portRef DOB7 (instanceRef pdp_ram_1_1_2))))
+          (net mdout1_0_16
+            (joined
+              (portRef D0 (instanceRef mux_19))
+              (portRef DOB7 (instanceRef pdp_ram_0_1_6))))
+          (net mdout1_1_17
+            (joined
+              (portRef D1 (instanceRef mux_18))
+              (portRef DOB8 (instanceRef pdp_ram_1_1_2))))
+          (net mdout1_0_17
+            (joined
+              (portRef D0 (instanceRef mux_18))
+              (portRef DOB8 (instanceRef pdp_ram_0_1_6))))
+          (net mdout1_1_18
+            (joined
+              (portRef D1 (instanceRef mux_17))
+              (portRef DOB0 (instanceRef pdp_ram_1_2_1))))
+          (net mdout1_0_18
+            (joined
+              (portRef D0 (instanceRef mux_17))
+              (portRef DOB0 (instanceRef pdp_ram_0_2_5))))
+          (net mdout1_1_19
+            (joined
+              (portRef D1 (instanceRef mux_16))
+              (portRef DOB1 (instanceRef pdp_ram_1_2_1))))
+          (net mdout1_0_19
+            (joined
+              (portRef D0 (instanceRef mux_16))
+              (portRef DOB1 (instanceRef pdp_ram_0_2_5))))
+          (net mdout1_1_20
+            (joined
+              (portRef D1 (instanceRef mux_15))
+              (portRef DOB2 (instanceRef pdp_ram_1_2_1))))
+          (net mdout1_0_20
+            (joined
+              (portRef D0 (instanceRef mux_15))
+              (portRef DOB2 (instanceRef pdp_ram_0_2_5))))
+          (net mdout1_1_21
+            (joined
+              (portRef D1 (instanceRef mux_14))
+              (portRef DOB3 (instanceRef pdp_ram_1_2_1))))
+          (net mdout1_0_21
+            (joined
+              (portRef D0 (instanceRef mux_14))
+              (portRef DOB3 (instanceRef pdp_ram_0_2_5))))
+          (net mdout1_1_22
+            (joined
+              (portRef D1 (instanceRef mux_13))
+              (portRef DOB4 (instanceRef pdp_ram_1_2_1))))
+          (net mdout1_0_22
+            (joined
+              (portRef D0 (instanceRef mux_13))
+              (portRef DOB4 (instanceRef pdp_ram_0_2_5))))
+          (net mdout1_1_23
+            (joined
+              (portRef D1 (instanceRef mux_12))
+              (portRef DOB5 (instanceRef pdp_ram_1_2_1))))
+          (net mdout1_0_23
+            (joined
+              (portRef D0 (instanceRef mux_12))
+              (portRef DOB5 (instanceRef pdp_ram_0_2_5))))
+          (net mdout1_1_24
+            (joined
+              (portRef D1 (instanceRef mux_11))
+              (portRef DOB6 (instanceRef pdp_ram_1_2_1))))
+          (net mdout1_0_24
+            (joined
+              (portRef D0 (instanceRef mux_11))
+              (portRef DOB6 (instanceRef pdp_ram_0_2_5))))
+          (net mdout1_1_25
+            (joined
+              (portRef D1 (instanceRef mux_10))
+              (portRef DOB7 (instanceRef pdp_ram_1_2_1))))
+          (net mdout1_0_25
+            (joined
+              (portRef D0 (instanceRef mux_10))
+              (portRef DOB7 (instanceRef pdp_ram_0_2_5))))
+          (net mdout1_1_26
+            (joined
+              (portRef D1 (instanceRef mux_9))
+              (portRef DOB8 (instanceRef pdp_ram_1_2_1))))
+          (net mdout1_0_26
+            (joined
+              (portRef D0 (instanceRef mux_9))
+              (portRef DOB8 (instanceRef pdp_ram_0_2_5))))
+          (net mdout1_1_27
+            (joined
+              (portRef D1 (instanceRef mux_8))
+              (portRef DOB0 (instanceRef pdp_ram_1_3_0))))
+          (net mdout1_0_27
+            (joined
+              (portRef D0 (instanceRef mux_8))
+              (portRef DOB0 (instanceRef pdp_ram_0_3_4))))
+          (net mdout1_1_28
+            (joined
+              (portRef D1 (instanceRef mux_7))
+              (portRef DOB1 (instanceRef pdp_ram_1_3_0))))
+          (net mdout1_0_28
+            (joined
+              (portRef D0 (instanceRef mux_7))
+              (portRef DOB1 (instanceRef pdp_ram_0_3_4))))
+          (net mdout1_1_29
+            (joined
+              (portRef D1 (instanceRef mux_6))
+              (portRef DOB2 (instanceRef pdp_ram_1_3_0))))
+          (net mdout1_0_29
+            (joined
+              (portRef D0 (instanceRef mux_6))
+              (portRef DOB2 (instanceRef pdp_ram_0_3_4))))
+          (net mdout1_1_30
+            (joined
+              (portRef D1 (instanceRef mux_5))
+              (portRef DOB3 (instanceRef pdp_ram_1_3_0))))
+          (net mdout1_0_30
+            (joined
+              (portRef D0 (instanceRef mux_5))
+              (portRef DOB3 (instanceRef pdp_ram_0_3_4))))
+          (net mdout1_1_31
+            (joined
+              (portRef D1 (instanceRef mux_4))
+              (portRef DOB4 (instanceRef pdp_ram_1_3_0))))
+          (net mdout1_0_31
+            (joined
+              (portRef D0 (instanceRef mux_4))
+              (portRef DOB4 (instanceRef pdp_ram_0_3_4))))
+          (net mdout1_1_32
+            (joined
+              (portRef D1 (instanceRef mux_3))
+              (portRef DOB5 (instanceRef pdp_ram_1_3_0))))
+          (net mdout1_0_32
+            (joined
+              (portRef D0 (instanceRef mux_3))
+              (portRef DOB5 (instanceRef pdp_ram_0_3_4))))
+          (net mdout1_1_33
+            (joined
+              (portRef D1 (instanceRef mux_2))
+              (portRef DOB6 (instanceRef pdp_ram_1_3_0))))
+          (net mdout1_0_33
+            (joined
+              (portRef D0 (instanceRef mux_2))
+              (portRef DOB6 (instanceRef pdp_ram_0_3_4))))
+          (net mdout1_1_34
+            (joined
+              (portRef D1 (instanceRef mux_1))
+              (portRef DOB7 (instanceRef pdp_ram_1_3_0))))
+          (net mdout1_0_34
+            (joined
+              (portRef D0 (instanceRef mux_1))
+              (portRef DOB7 (instanceRef pdp_ram_0_3_4))))
+          (net rptr_11_ff2
+            (joined
+              (portRef SD (instanceRef mux_0))
+              (portRef Q (instanceRef FF_14))
+              (portRef SD (instanceRef mux_35))
+              (portRef SD (instanceRef mux_34))
+              (portRef SD (instanceRef mux_33))
+              (portRef SD (instanceRef mux_32))
+              (portRef SD (instanceRef mux_31))
+              (portRef SD (instanceRef mux_30))
+              (portRef SD (instanceRef mux_29))
+              (portRef SD (instanceRef mux_28))
+              (portRef SD (instanceRef mux_27))
+              (portRef SD (instanceRef mux_26))
+              (portRef SD (instanceRef mux_25))
+              (portRef SD (instanceRef mux_24))
+              (portRef SD (instanceRef mux_23))
+              (portRef SD (instanceRef mux_22))
+              (portRef SD (instanceRef mux_21))
+              (portRef SD (instanceRef mux_20))
+              (portRef SD (instanceRef mux_19))
+              (portRef SD (instanceRef mux_18))
+              (portRef SD (instanceRef mux_17))
+              (portRef SD (instanceRef mux_16))
+              (portRef SD (instanceRef mux_15))
+              (portRef SD (instanceRef mux_14))
+              (portRef SD (instanceRef mux_13))
+              (portRef SD (instanceRef mux_12))
+              (portRef SD (instanceRef mux_11))
+              (portRef SD (instanceRef mux_10))
+              (portRef SD (instanceRef mux_9))
+              (portRef SD (instanceRef mux_8))
+              (portRef SD (instanceRef mux_7))
+              (portRef SD (instanceRef mux_6))
+              (portRef SD (instanceRef mux_5))
+              (portRef SD (instanceRef mux_4))
+              (portRef SD (instanceRef mux_3))
+              (portRef SD (instanceRef mux_2))
+              (portRef SD (instanceRef mux_1))))
+          (net mdout1_1_35
+            (joined
+              (portRef D1 (instanceRef mux_0))
+              (portRef DOB8 (instanceRef pdp_ram_1_3_0))))
+          (net mdout1_0_35
+            (joined
+              (portRef D0 (instanceRef mux_0))
+              (portRef DOB8 (instanceRef pdp_ram_0_3_4))))
+          (net wcnt_sub_0
+            (joined
+              (portRef S1 (instanceRef wcnt_0))
+              (portRef D (instanceRef FF_13))))
+          (net rptr_0
+            (joined
+              (portRef B1 (instanceRef wcnt_0))
+              (portRef ADB3 (instanceRef pdp_ram_0_0_7))
+              (portRef ADB3 (instanceRef pdp_ram_0_1_6))
+              (portRef ADB3 (instanceRef pdp_ram_0_2_5))
+              (portRef ADB3 (instanceRef pdp_ram_0_3_4))
+              (portRef ADB3 (instanceRef pdp_ram_1_0_3))
+              (portRef ADB3 (instanceRef pdp_ram_1_1_2))
+              (portRef ADB3 (instanceRef pdp_ram_1_2_1))
+              (portRef ADB3 (instanceRef pdp_ram_1_3_0))
+              (portRef Q (instanceRef FF_28))))
+          (net cnt_con_inv
+            (joined
+              (portRef B0 (instanceRef wcnt_0))
+              (portRef Z (instanceRef INV_0))))
+          (net wcount_0
+            (joined
+              (portRef A1 (instanceRef wcnt_0))
+              (portRef Q (instanceRef FF_67))
+              (portRef D (instanceRef FF_41))
+              (portRef A0 (instanceRef w_ctr_0))))
+          (net cnt_con
+            (joined
+              (portRef A0 (instanceRef wcnt_0))
+              (portRef Z (instanceRef AND2_t3))
+              (portRef A (instanceRef INV_0))
+              (portRef B1 (instanceRef bdcnt_bctr_cia))
+              (portRef A1 (instanceRef bdcnt_bctr_cia))
+              (portRef B1 (instanceRef bdcnt_bctr_0))
+              (portRef B0 (instanceRef bdcnt_bctr_0))
+              (portRef B1 (instanceRef bdcnt_bctr_1))
+              (portRef B0 (instanceRef bdcnt_bctr_1))
+              (portRef B1 (instanceRef bdcnt_bctr_2))
+              (portRef B0 (instanceRef bdcnt_bctr_2))
+              (portRef B1 (instanceRef bdcnt_bctr_3))
+              (portRef B0 (instanceRef bdcnt_bctr_3))
+              (portRef B1 (instanceRef bdcnt_bctr_4))
+              (portRef B0 (instanceRef bdcnt_bctr_4))
+              (portRef B1 (instanceRef bdcnt_bctr_5))
+              (portRef B0 (instanceRef bdcnt_bctr_5))
+              (portRef B1 (instanceRef bdcnt_bctr_6))
+              (portRef B0 (instanceRef bdcnt_bctr_6))))
+          (net precin
+            (joined
+              (portRef CIN (instanceRef wcnt_0))
+              (portRef COUT (instanceRef precin_inst389))))
+          (net wcnt_sub_1
+            (joined
+              (portRef S0 (instanceRef wcnt_1))
+              (portRef D (instanceRef FF_12))))
+          (net wcnt_sub_2
+            (joined
+              (portRef S1 (instanceRef wcnt_1))
+              (portRef D (instanceRef FF_11))))
+          (net rptr_2
+            (joined
+              (portRef B1 (instanceRef wcnt_1))
+              (portRef ADB5 (instanceRef pdp_ram_0_0_7))
+              (portRef ADB5 (instanceRef pdp_ram_0_1_6))
+              (portRef ADB5 (instanceRef pdp_ram_0_2_5))
+              (portRef ADB5 (instanceRef pdp_ram_0_3_4))
+              (portRef ADB5 (instanceRef pdp_ram_1_0_3))
+              (portRef ADB5 (instanceRef pdp_ram_1_1_2))
+              (portRef ADB5 (instanceRef pdp_ram_1_2_1))
+              (portRef ADB5 (instanceRef pdp_ram_1_3_0))
+              (portRef Q (instanceRef FF_26))))
+          (net rptr_1
+            (joined
+              (portRef B0 (instanceRef wcnt_1))
+              (portRef ADB4 (instanceRef pdp_ram_0_0_7))
+              (portRef ADB4 (instanceRef pdp_ram_0_1_6))
+              (portRef ADB4 (instanceRef pdp_ram_0_2_5))
+              (portRef ADB4 (instanceRef pdp_ram_0_3_4))
+              (portRef ADB4 (instanceRef pdp_ram_1_0_3))
+              (portRef ADB4 (instanceRef pdp_ram_1_1_2))
+              (portRef ADB4 (instanceRef pdp_ram_1_2_1))
+              (portRef ADB4 (instanceRef pdp_ram_1_3_0))
+              (portRef Q (instanceRef FF_27))))
+          (net wcount_2
+            (joined
+              (portRef A1 (instanceRef wcnt_1))
+              (portRef Q (instanceRef FF_65))
+              (portRef D (instanceRef FF_39))
+              (portRef A0 (instanceRef w_ctr_1))))
+          (net wcount_1
+            (joined
+              (portRef A0 (instanceRef wcnt_1))
+              (portRef Q (instanceRef FF_66))
+              (portRef D (instanceRef FF_40))
+              (portRef A1 (instanceRef w_ctr_0))))
+          (net co0_5
+            (joined
+              (portRef CIN (instanceRef wcnt_1))
+              (portRef COUT (instanceRef wcnt_0))))
+          (net wcnt_sub_3
+            (joined
+              (portRef S0 (instanceRef wcnt_2))
+              (portRef D (instanceRef FF_10))))
+          (net wcnt_sub_4
+            (joined
+              (portRef S1 (instanceRef wcnt_2))
+              (portRef D (instanceRef FF_9))))
+          (net rptr_4
+            (joined
+              (portRef B1 (instanceRef wcnt_2))
+              (portRef ADB7 (instanceRef pdp_ram_0_0_7))
+              (portRef ADB7 (instanceRef pdp_ram_0_1_6))
+              (portRef ADB7 (instanceRef pdp_ram_0_2_5))
+              (portRef ADB7 (instanceRef pdp_ram_0_3_4))
+              (portRef ADB7 (instanceRef pdp_ram_1_0_3))
+              (portRef ADB7 (instanceRef pdp_ram_1_1_2))
+              (portRef ADB7 (instanceRef pdp_ram_1_2_1))
+              (portRef ADB7 (instanceRef pdp_ram_1_3_0))
+              (portRef Q (instanceRef FF_24))))
+          (net rptr_3
+            (joined
+              (portRef B0 (instanceRef wcnt_2))
+              (portRef ADB6 (instanceRef pdp_ram_0_0_7))
+              (portRef ADB6 (instanceRef pdp_ram_0_1_6))
+              (portRef ADB6 (instanceRef pdp_ram_0_2_5))
+              (portRef ADB6 (instanceRef pdp_ram_0_3_4))
+              (portRef ADB6 (instanceRef pdp_ram_1_0_3))
+              (portRef ADB6 (instanceRef pdp_ram_1_1_2))
+              (portRef ADB6 (instanceRef pdp_ram_1_2_1))
+              (portRef ADB6 (instanceRef pdp_ram_1_3_0))
+              (portRef Q (instanceRef FF_25))))
+          (net wcount_4
+            (joined
+              (portRef A1 (instanceRef wcnt_2))
+              (portRef Q (instanceRef FF_63))
+              (portRef D (instanceRef FF_37))
+              (portRef A0 (instanceRef w_ctr_2))))
+          (net wcount_3
+            (joined
+              (portRef A0 (instanceRef wcnt_2))
+              (portRef Q (instanceRef FF_64))
+              (portRef D (instanceRef FF_38))
+              (portRef A1 (instanceRef w_ctr_1))))
+          (net co1_5
+            (joined
+              (portRef CIN (instanceRef wcnt_2))
+              (portRef COUT (instanceRef wcnt_1))))
+          (net wcnt_sub_5
+            (joined
+              (portRef S0 (instanceRef wcnt_3))
+              (portRef D (instanceRef FF_8))))
+          (net wcnt_sub_6
+            (joined
+              (portRef S1 (instanceRef wcnt_3))
+              (portRef D (instanceRef FF_7))))
+          (net rptr_6
+            (joined
+              (portRef B1 (instanceRef wcnt_3))
+              (portRef ADB9 (instanceRef pdp_ram_0_0_7))
+              (portRef ADB9 (instanceRef pdp_ram_0_1_6))
+              (portRef ADB9 (instanceRef pdp_ram_0_2_5))
+              (portRef ADB9 (instanceRef pdp_ram_0_3_4))
+              (portRef ADB9 (instanceRef pdp_ram_1_0_3))
+              (portRef ADB9 (instanceRef pdp_ram_1_1_2))
+              (portRef ADB9 (instanceRef pdp_ram_1_2_1))
+              (portRef ADB9 (instanceRef pdp_ram_1_3_0))
+              (portRef Q (instanceRef FF_22))))
+          (net rptr_5
+            (joined
+              (portRef B0 (instanceRef wcnt_3))
+              (portRef ADB8 (instanceRef pdp_ram_0_0_7))
+              (portRef ADB8 (instanceRef pdp_ram_0_1_6))
+              (portRef ADB8 (instanceRef pdp_ram_0_2_5))
+              (portRef ADB8 (instanceRef pdp_ram_0_3_4))
+              (portRef ADB8 (instanceRef pdp_ram_1_0_3))
+              (portRef ADB8 (instanceRef pdp_ram_1_1_2))
+              (portRef ADB8 (instanceRef pdp_ram_1_2_1))
+              (portRef ADB8 (instanceRef pdp_ram_1_3_0))
+              (portRef Q (instanceRef FF_23))))
+          (net wcount_6
+            (joined
+              (portRef A1 (instanceRef wcnt_3))
+              (portRef Q (instanceRef FF_61))
+              (portRef D (instanceRef FF_35))
+              (portRef A0 (instanceRef w_ctr_3))))
+          (net wcount_5
+            (joined
+              (portRef A0 (instanceRef wcnt_3))
+              (portRef Q (instanceRef FF_62))
+              (portRef D (instanceRef FF_36))
+              (portRef A1 (instanceRef w_ctr_2))))
+          (net co2_5
+            (joined
+              (portRef CIN (instanceRef wcnt_3))
+              (portRef COUT (instanceRef wcnt_2))))
+          (net wcnt_sub_7
+            (joined
+              (portRef S0 (instanceRef wcnt_4))
+              (portRef D (instanceRef FF_6))))
+          (net wcnt_sub_8
+            (joined
+              (portRef S1 (instanceRef wcnt_4))
+              (portRef D (instanceRef FF_5))))
+          (net rptr_8
+            (joined
+              (portRef B1 (instanceRef wcnt_4))
+              (portRef ADB11 (instanceRef pdp_ram_0_0_7))
+              (portRef ADB11 (instanceRef pdp_ram_0_1_6))
+              (portRef ADB11 (instanceRef pdp_ram_0_2_5))
+              (portRef ADB11 (instanceRef pdp_ram_0_3_4))
+              (portRef ADB11 (instanceRef pdp_ram_1_0_3))
+              (portRef ADB11 (instanceRef pdp_ram_1_1_2))
+              (portRef ADB11 (instanceRef pdp_ram_1_2_1))
+              (portRef ADB11 (instanceRef pdp_ram_1_3_0))
+              (portRef Q (instanceRef FF_20))))
+          (net rptr_7
+            (joined
+              (portRef B0 (instanceRef wcnt_4))
+              (portRef ADB10 (instanceRef pdp_ram_0_0_7))
+              (portRef ADB10 (instanceRef pdp_ram_0_1_6))
+              (portRef ADB10 (instanceRef pdp_ram_0_2_5))
+              (portRef ADB10 (instanceRef pdp_ram_0_3_4))
+              (portRef ADB10 (instanceRef pdp_ram_1_0_3))
+              (portRef ADB10 (instanceRef pdp_ram_1_1_2))
+              (portRef ADB10 (instanceRef pdp_ram_1_2_1))
+              (portRef ADB10 (instanceRef pdp_ram_1_3_0))
+              (portRef Q (instanceRef FF_21))))
+          (net wcount_8
+            (joined
+              (portRef A1 (instanceRef wcnt_4))
+              (portRef Q (instanceRef FF_59))
+              (portRef D (instanceRef FF_33))
+              (portRef A0 (instanceRef w_ctr_4))))
+          (net wcount_7
+            (joined
+              (portRef A0 (instanceRef wcnt_4))
+              (portRef Q (instanceRef FF_60))
+              (portRef D (instanceRef FF_34))
+              (portRef A1 (instanceRef w_ctr_3))))
+          (net co3_5
+            (joined
+              (portRef CIN (instanceRef wcnt_4))
+              (portRef COUT (instanceRef wcnt_3))))
+          (net wcnt_sub_9
+            (joined
+              (portRef S0 (instanceRef wcnt_5))
+              (portRef D (instanceRef FF_4))))
+          (net wcnt_sub_10
+            (joined
+              (portRef S1 (instanceRef wcnt_5))
+              (portRef D (instanceRef FF_3))))
+          (net rptr_10
+            (joined
+              (portRef B1 (instanceRef wcnt_5))
+              (portRef ADB13 (instanceRef pdp_ram_0_0_7))
+              (portRef ADB13 (instanceRef pdp_ram_0_1_6))
+              (portRef ADB13 (instanceRef pdp_ram_0_2_5))
+              (portRef ADB13 (instanceRef pdp_ram_0_3_4))
+              (portRef ADB13 (instanceRef pdp_ram_1_0_3))
+              (portRef ADB13 (instanceRef pdp_ram_1_1_2))
+              (portRef ADB13 (instanceRef pdp_ram_1_2_1))
+              (portRef ADB13 (instanceRef pdp_ram_1_3_0))
+              (portRef Q (instanceRef FF_18))))
+          (net rptr_9
+            (joined
+              (portRef B0 (instanceRef wcnt_5))
+              (portRef ADB12 (instanceRef pdp_ram_0_0_7))
+              (portRef ADB12 (instanceRef pdp_ram_0_1_6))
+              (portRef ADB12 (instanceRef pdp_ram_0_2_5))
+              (portRef ADB12 (instanceRef pdp_ram_0_3_4))
+              (portRef ADB12 (instanceRef pdp_ram_1_0_3))
+              (portRef ADB12 (instanceRef pdp_ram_1_1_2))
+              (portRef ADB12 (instanceRef pdp_ram_1_2_1))
+              (portRef ADB12 (instanceRef pdp_ram_1_3_0))
+              (portRef Q (instanceRef FF_19))))
+          (net wcount_10
+            (joined
+              (portRef A1 (instanceRef wcnt_5))
+              (portRef Q (instanceRef FF_57))
+              (portRef D (instanceRef FF_31))
+              (portRef A0 (instanceRef w_ctr_5))))
+          (net wcount_9
+            (joined
+              (portRef A0 (instanceRef wcnt_5))
+              (portRef Q (instanceRef FF_58))
+              (portRef D (instanceRef FF_32))
+              (portRef A1 (instanceRef w_ctr_4))))
+          (net co4_5
+            (joined
+              (portRef CIN (instanceRef wcnt_5))
+              (portRef COUT (instanceRef wcnt_4))))
+          (net wcnt_sub_11
+            (joined
+              (portRef S0 (instanceRef wcnt_6))
+              (portRef D (instanceRef FF_2))))
+          (net wcnt_sub_12
+            (joined
+              (portRef S1 (instanceRef wcnt_6))
+              (portRef D (instanceRef FF_1))))
+          (net rptr_11
+            (joined
+              (portRef B0 (instanceRef wcnt_6))
+              (portRef CSB0 (instanceRef pdp_ram_0_0_7))
+              (portRef CSB0 (instanceRef pdp_ram_0_1_6))
+              (portRef CSB0 (instanceRef pdp_ram_0_2_5))
+              (portRef CSB0 (instanceRef pdp_ram_0_3_4))
+              (portRef CSB0 (instanceRef pdp_ram_1_0_3))
+              (portRef CSB0 (instanceRef pdp_ram_1_1_2))
+              (portRef CSB0 (instanceRef pdp_ram_1_2_1))
+              (portRef CSB0 (instanceRef pdp_ram_1_3_0))
+              (portRef Q (instanceRef FF_17))
+              (portRef D (instanceRef FF_15))))
+          (net wcnt_sub_msb
+            (joined
+              (portRef A1 (instanceRef wcnt_6))
+              (portRef Z (instanceRef XOR2_t0))))
+          (net wcount_11
+            (joined
+              (portRef A0 (instanceRef wcnt_6))
+              (portRef Q (instanceRef FF_56))
+              (portRef D (instanceRef FF_30))
+              (portRef A1 (instanceRef w_ctr_5))))
+          (net co5_5
+            (joined
+              (portRef CIN (instanceRef wcnt_6))
+              (portRef COUT (instanceRef wcnt_5))))
+          (net co6_3d
+            (joined
+              (portRef S0 (instanceRef wcntd))))
+          (net co6_3
+            (joined
+              (portRef CIN (instanceRef wcntd))
+              (portRef COUT (instanceRef wcnt_6))))
+          (net wren_i
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_ci_a))
+              (portRef Z (instanceRef AND2_t5))
+              (portRef A (instanceRef AND2_t3))
+              (portRef A (instanceRef XOR2_t2))
+              (portRef A (instanceRef INV_2))
+              (portRef AD1 (instanceRef LUT4_1))
+              (portRef A (instanceRef INV_1))
+              (portRef OCEA (instanceRef pdp_ram_0_0_7))
+              (portRef CEA (instanceRef pdp_ram_0_0_7))
+              (portRef OCEA (instanceRef pdp_ram_0_1_6))
+              (portRef CEA (instanceRef pdp_ram_0_1_6))
+              (portRef OCEA (instanceRef pdp_ram_0_2_5))
+              (portRef CEA (instanceRef pdp_ram_0_2_5))
+              (portRef OCEA (instanceRef pdp_ram_0_3_4))
+              (portRef CEA (instanceRef pdp_ram_0_3_4))
+              (portRef OCEA (instanceRef pdp_ram_1_0_3))
+              (portRef CEA (instanceRef pdp_ram_1_0_3))
+              (portRef OCEA (instanceRef pdp_ram_1_1_2))
+              (portRef CEA (instanceRef pdp_ram_1_1_2))
+              (portRef OCEA (instanceRef pdp_ram_1_2_1))
+              (portRef CEA (instanceRef pdp_ram_1_2_1))
+              (portRef OCEA (instanceRef pdp_ram_1_3_0))
+              (portRef CEA (instanceRef pdp_ram_1_3_0))
+              (portRef SP (instanceRef FF_67))
+              (portRef SP (instanceRef FF_66))
+              (portRef SP (instanceRef FF_65))
+              (portRef SP (instanceRef FF_64))
+              (portRef SP (instanceRef FF_63))
+              (portRef SP (instanceRef FF_62))
+              (portRef SP (instanceRef FF_61))
+              (portRef SP (instanceRef FF_60))
+              (portRef SP (instanceRef FF_59))
+              (portRef SP (instanceRef FF_58))
+              (portRef SP (instanceRef FF_57))
+              (portRef SP (instanceRef FF_56))
+              (portRef SP (instanceRef FF_55))
+              (portRef SP (instanceRef FF_41))
+              (portRef SP (instanceRef FF_40))
+              (portRef SP (instanceRef FF_39))
+              (portRef SP (instanceRef FF_38))
+              (portRef SP (instanceRef FF_37))
+              (portRef SP (instanceRef FF_36))
+              (portRef SP (instanceRef FF_35))
+              (portRef SP (instanceRef FF_34))
+              (portRef SP (instanceRef FF_33))
+              (portRef SP (instanceRef FF_32))
+              (portRef SP (instanceRef FF_31))
+              (portRef SP (instanceRef FF_30))
+              (portRef SP (instanceRef FF_29))
+              (portRef B0 (instanceRef g_cmp_0))
+              (portRef B1 (instanceRef g_cmp_0))
+              (portRef B0 (instanceRef g_cmp_1))
+              (portRef B1 (instanceRef g_cmp_1))
+              (portRef B0 (instanceRef g_cmp_2))
+              (portRef B1 (instanceRef g_cmp_2))
+              (portRef B0 (instanceRef g_cmp_3))
+              (portRef B1 (instanceRef g_cmp_3))
+              (portRef B0 (instanceRef g_cmp_4))
+              (portRef B1 (instanceRef g_cmp_4))
+              (portRef B0 (instanceRef g_cmp_5))
+              (portRef B1 (instanceRef g_cmp_5))
+              (portRef B1 (instanceRef af_set_cmp_ci_a))))
+          (net x
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_ci_a))
+              (portRef CIN (instanceRef bdcnt_bctr_cia))
+              (portRef CIN (instanceRef e_cmp_ci_a))
+              (portRef CIN (instanceRef g_cmp_ci_a))
+              (portRef CIN (instanceRef w_ctr_cia))
+              (portRef CIN (instanceRef r_ctr_cia))
+              (portRef CIN (instanceRef precin_inst389))))
+          (net cmp_ci_2
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_0))
+              (portRef COUT (instanceRef af_set_cmp_ci_a))))
+          (net wcnt_reg_0
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_0))
+              (portRef Q (instanceRef FF_13))))
+          (net wcnt_reg_1
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_0))
+              (portRef Q (instanceRef FF_12))))
+          (net co0_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_1))
+              (portRef COUT (instanceRef af_set_cmp_0))))
+          (net wcnt_reg_2
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_1))
+              (portRef Q (instanceRef FF_11))))
+          (net wcnt_reg_3
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_1))
+              (portRef Q (instanceRef FF_10))))
+          (net co1_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_2))
+              (portRef COUT (instanceRef af_set_cmp_1))))
+          (net wcnt_reg_4
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_2))
+              (portRef Q (instanceRef FF_9))))
+          (net wcnt_reg_5
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_2))
+              (portRef Q (instanceRef FF_8))))
+          (net co2_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_3))
+              (portRef COUT (instanceRef af_set_cmp_2))))
+          (net wcnt_reg_6
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_3))
+              (portRef Q (instanceRef FF_7))))
+          (net wcnt_reg_7
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_3))
+              (portRef Q (instanceRef FF_6))))
+          (net co3_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_4))
+              (portRef COUT (instanceRef af_set_cmp_3))))
+          (net wcnt_reg_8
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_4))
+              (portRef Q (instanceRef FF_5))))
+          (net wcnt_reg_9
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_4))
+              (portRef Q (instanceRef FF_4))))
+          (net co4_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_5))
+              (portRef COUT (instanceRef af_set_cmp_4))))
+          (net wcnt_reg_10
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_5))
+              (portRef Q (instanceRef FF_3))))
+          (net wcnt_reg_11
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_5))
+              (portRef Q (instanceRef FF_2))))
+          (net co5_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_6))
+              (portRef COUT (instanceRef af_set_cmp_5))))
+          (net wcnt_reg_12
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_6))
+              (portRef Q (instanceRef FF_1))))
+          (net af_set
+            (joined
+              (portRef S0 (instanceRef a2))
+              (portRef D (instanceRef FF_0))))
+          (net scuba_vhi
+            (joined
+              (portRef Z (instanceRef scuba_vhi_inst))
+              (portRef OCEB (instanceRef pdp_ram_0_0_7))
+              (portRef WEA (instanceRef pdp_ram_0_0_7))
+              (portRef OCEB (instanceRef pdp_ram_0_1_6))
+              (portRef WEA (instanceRef pdp_ram_0_1_6))
+              (portRef OCEB (instanceRef pdp_ram_0_2_5))
+              (portRef WEA (instanceRef pdp_ram_0_2_5))
+              (portRef OCEB (instanceRef pdp_ram_0_3_4))
+              (portRef WEA (instanceRef pdp_ram_0_3_4))
+              (portRef OCEB (instanceRef pdp_ram_1_0_3))
+              (portRef WEA (instanceRef pdp_ram_1_0_3))
+              (portRef OCEB (instanceRef pdp_ram_1_1_2))
+              (portRef WEA (instanceRef pdp_ram_1_1_2))
+              (portRef OCEB (instanceRef pdp_ram_1_2_1))
+              (portRef WEA (instanceRef pdp_ram_1_2_1))
+              (portRef OCEB (instanceRef pdp_ram_1_3_0))
+              (portRef WEA (instanceRef pdp_ram_1_3_0))
+              (portRef C1 (instanceRef bdcnt_bctr_cia))
+              (portRef C0 (instanceRef bdcnt_bctr_cia))
+              (portRef D1 (instanceRef bdcnt_bctr_cia))
+              (portRef D0 (instanceRef bdcnt_bctr_cia))
+              (portRef D1 (instanceRef bdcnt_bctr_0))
+              (portRef D0 (instanceRef bdcnt_bctr_0))
+              (portRef C1 (instanceRef bdcnt_bctr_0))
+              (portRef C0 (instanceRef bdcnt_bctr_0))
+              (portRef D1 (instanceRef bdcnt_bctr_1))
+              (portRef D0 (instanceRef bdcnt_bctr_1))
+              (portRef C1 (instanceRef bdcnt_bctr_1))
+              (portRef C0 (instanceRef bdcnt_bctr_1))
+              (portRef D1 (instanceRef bdcnt_bctr_2))
+              (portRef D0 (instanceRef bdcnt_bctr_2))
+              (portRef C1 (instanceRef bdcnt_bctr_2))
+              (portRef C0 (instanceRef bdcnt_bctr_2))
+              (portRef D1 (instanceRef bdcnt_bctr_3))
+              (portRef D0 (instanceRef bdcnt_bctr_3))
+              (portRef C1 (instanceRef bdcnt_bctr_3))
+              (portRef C0 (instanceRef bdcnt_bctr_3))
+              (portRef D1 (instanceRef bdcnt_bctr_4))
+              (portRef D0 (instanceRef bdcnt_bctr_4))
+              (portRef C1 (instanceRef bdcnt_bctr_4))
+              (portRef C0 (instanceRef bdcnt_bctr_4))
+              (portRef D1 (instanceRef bdcnt_bctr_5))
+              (portRef D0 (instanceRef bdcnt_bctr_5))
+              (portRef C1 (instanceRef bdcnt_bctr_5))
+              (portRef C0 (instanceRef bdcnt_bctr_5))
+              (portRef D1 (instanceRef bdcnt_bctr_6))
+              (portRef D0 (instanceRef bdcnt_bctr_6))
+              (portRef C1 (instanceRef bdcnt_bctr_6))
+              (portRef C0 (instanceRef bdcnt_bctr_6))
+              (portRef C1 (instanceRef e_cmp_ci_a))
+              (portRef C0 (instanceRef e_cmp_ci_a))
+              (portRef D1 (instanceRef e_cmp_ci_a))
+              (portRef D0 (instanceRef e_cmp_ci_a))
+              (portRef B1 (instanceRef e_cmp_ci_a))
+              (portRef B0 (instanceRef e_cmp_ci_a))
+              (portRef A1 (instanceRef e_cmp_ci_a))
+              (portRef A0 (instanceRef e_cmp_ci_a))
+              (portRef D1 (instanceRef e_cmp_0))
+              (portRef D0 (instanceRef e_cmp_0))
+              (portRef C1 (instanceRef e_cmp_0))
+              (portRef C0 (instanceRef e_cmp_0))
+              (portRef D1 (instanceRef e_cmp_1))
+              (portRef D0 (instanceRef e_cmp_1))
+              (portRef C1 (instanceRef e_cmp_1))
+              (portRef C0 (instanceRef e_cmp_1))
+              (portRef D1 (instanceRef e_cmp_2))
+              (portRef D0 (instanceRef e_cmp_2))
+              (portRef C1 (instanceRef e_cmp_2))
+              (portRef C0 (instanceRef e_cmp_2))
+              (portRef D1 (instanceRef e_cmp_3))
+              (portRef D0 (instanceRef e_cmp_3))
+              (portRef C1 (instanceRef e_cmp_3))
+              (portRef C0 (instanceRef e_cmp_3))
+              (portRef D1 (instanceRef e_cmp_4))
+              (portRef D0 (instanceRef e_cmp_4))
+              (portRef C1 (instanceRef e_cmp_4))
+              (portRef C0 (instanceRef e_cmp_4))
+              (portRef D1 (instanceRef e_cmp_5))
+              (portRef D0 (instanceRef e_cmp_5))
+              (portRef C1 (instanceRef e_cmp_5))
+              (portRef C0 (instanceRef e_cmp_5))
+              (portRef D1 (instanceRef e_cmp_6))
+              (portRef D0 (instanceRef e_cmp_6))
+              (portRef C1 (instanceRef e_cmp_6))
+              (portRef C0 (instanceRef e_cmp_6))
+              (portRef C1 (instanceRef a0))
+              (portRef C0 (instanceRef a0))
+              (portRef D1 (instanceRef a0))
+              (portRef D0 (instanceRef a0))
+              (portRef C1 (instanceRef g_cmp_ci_a))
+              (portRef C0 (instanceRef g_cmp_ci_a))
+              (portRef D1 (instanceRef g_cmp_ci_a))
+              (portRef D0 (instanceRef g_cmp_ci_a))
+              (portRef B1 (instanceRef g_cmp_ci_a))
+              (portRef B0 (instanceRef g_cmp_ci_a))
+              (portRef A1 (instanceRef g_cmp_ci_a))
+              (portRef A0 (instanceRef g_cmp_ci_a))
+              (portRef D1 (instanceRef g_cmp_0))
+              (portRef D0 (instanceRef g_cmp_0))
+              (portRef C1 (instanceRef g_cmp_0))
+              (portRef C0 (instanceRef g_cmp_0))
+              (portRef D1 (instanceRef g_cmp_1))
+              (portRef D0 (instanceRef g_cmp_1))
+              (portRef C1 (instanceRef g_cmp_1))
+              (portRef C0 (instanceRef g_cmp_1))
+              (portRef D1 (instanceRef g_cmp_2))
+              (portRef D0 (instanceRef g_cmp_2))
+              (portRef C1 (instanceRef g_cmp_2))
+              (portRef C0 (instanceRef g_cmp_2))
+              (portRef D1 (instanceRef g_cmp_3))
+              (portRef D0 (instanceRef g_cmp_3))
+              (portRef C1 (instanceRef g_cmp_3))
+              (portRef C0 (instanceRef g_cmp_3))
+              (portRef D1 (instanceRef g_cmp_4))
+              (portRef D0 (instanceRef g_cmp_4))
+              (portRef C1 (instanceRef g_cmp_4))
+              (portRef C0 (instanceRef g_cmp_4))
+              (portRef D1 (instanceRef g_cmp_5))
+              (portRef D0 (instanceRef g_cmp_5))
+              (portRef C1 (instanceRef g_cmp_5))
+              (portRef C0 (instanceRef g_cmp_5))
+              (portRef D1 (instanceRef g_cmp_6))
+              (portRef D0 (instanceRef g_cmp_6))
+              (portRef C1 (instanceRef g_cmp_6))
+              (portRef C0 (instanceRef g_cmp_6))
+              (portRef C1 (instanceRef a1))
+              (portRef C0 (instanceRef a1))
+              (portRef D1 (instanceRef a1))
+              (portRef D0 (instanceRef a1))
+              (portRef C1 (instanceRef w_ctr_cia))
+              (portRef C0 (instanceRef w_ctr_cia))
+              (portRef D1 (instanceRef w_ctr_cia))
+              (portRef D0 (instanceRef w_ctr_cia))
+              (portRef B1 (instanceRef w_ctr_cia))
+              (portRef A1 (instanceRef w_ctr_cia))
+              (portRef D1 (instanceRef w_ctr_0))
+              (portRef D0 (instanceRef w_ctr_0))
+              (portRef C1 (instanceRef w_ctr_0))
+              (portRef C0 (instanceRef w_ctr_0))
+              (portRef D1 (instanceRef w_ctr_1))
+              (portRef D0 (instanceRef w_ctr_1))
+              (portRef C1 (instanceRef w_ctr_1))
+              (portRef C0 (instanceRef w_ctr_1))
+              (portRef D1 (instanceRef w_ctr_2))
+              (portRef D0 (instanceRef w_ctr_2))
+              (portRef C1 (instanceRef w_ctr_2))
+              (portRef C0 (instanceRef w_ctr_2))
+              (portRef D1 (instanceRef w_ctr_3))
+              (portRef D0 (instanceRef w_ctr_3))
+              (portRef C1 (instanceRef w_ctr_3))
+              (portRef C0 (instanceRef w_ctr_3))
+              (portRef D1 (instanceRef w_ctr_4))
+              (portRef D0 (instanceRef w_ctr_4))
+              (portRef C1 (instanceRef w_ctr_4))
+              (portRef C0 (instanceRef w_ctr_4))
+              (portRef D1 (instanceRef w_ctr_5))
+              (portRef D0 (instanceRef w_ctr_5))
+              (portRef C1 (instanceRef w_ctr_5))
+              (portRef C0 (instanceRef w_ctr_5))
+              (portRef D1 (instanceRef w_ctr_6))
+              (portRef D0 (instanceRef w_ctr_6))
+              (portRef C1 (instanceRef w_ctr_6))
+              (portRef C0 (instanceRef w_ctr_6))
+              (portRef C1 (instanceRef r_ctr_cia))
+              (portRef C0 (instanceRef r_ctr_cia))
+              (portRef D1 (instanceRef r_ctr_cia))
+              (portRef D0 (instanceRef r_ctr_cia))
+              (portRef B1 (instanceRef r_ctr_cia))
+              (portRef A1 (instanceRef r_ctr_cia))
+              (portRef D1 (instanceRef r_ctr_0))
+              (portRef D0 (instanceRef r_ctr_0))
+              (portRef C1 (instanceRef r_ctr_0))
+              (portRef C0 (instanceRef r_ctr_0))
+              (portRef D1 (instanceRef r_ctr_1))
+              (portRef D0 (instanceRef r_ctr_1))
+              (portRef C1 (instanceRef r_ctr_1))
+              (portRef C0 (instanceRef r_ctr_1))
+              (portRef D1 (instanceRef r_ctr_2))
+              (portRef D0 (instanceRef r_ctr_2))
+              (portRef C1 (instanceRef r_ctr_2))
+              (portRef C0 (instanceRef r_ctr_2))
+              (portRef D1 (instanceRef r_ctr_3))
+              (portRef D0 (instanceRef r_ctr_3))
+              (portRef C1 (instanceRef r_ctr_3))
+              (portRef C0 (instanceRef r_ctr_3))
+              (portRef D1 (instanceRef r_ctr_4))
+              (portRef D0 (instanceRef r_ctr_4))
+              (portRef C1 (instanceRef r_ctr_4))
+              (portRef C0 (instanceRef r_ctr_4))
+              (portRef D1 (instanceRef r_ctr_5))
+              (portRef D0 (instanceRef r_ctr_5))
+              (portRef C1 (instanceRef r_ctr_5))
+              (portRef C0 (instanceRef r_ctr_5))
+              (portRef D1 (instanceRef r_ctr_6))
+              (portRef D0 (instanceRef r_ctr_6))
+              (portRef C1 (instanceRef r_ctr_6))
+              (portRef C0 (instanceRef r_ctr_6))
+              (portRef C1 (instanceRef precin_inst389))
+              (portRef C0 (instanceRef precin_inst389))
+              (portRef D1 (instanceRef precin_inst389))
+              (portRef D0 (instanceRef precin_inst389))
+              (portRef B1 (instanceRef precin_inst389))
+              (portRef B0 (instanceRef precin_inst389))
+              (portRef A1 (instanceRef precin_inst389))
+              (portRef A0 (instanceRef precin_inst389))
+              (portRef C1 (instanceRef wcnt_0))
+              (portRef C0 (instanceRef wcnt_0))
+              (portRef D1 (instanceRef wcnt_0))
+              (portRef D0 (instanceRef wcnt_0))
+              (portRef C1 (instanceRef wcnt_1))
+              (portRef C0 (instanceRef wcnt_1))
+              (portRef D1 (instanceRef wcnt_1))
+              (portRef D0 (instanceRef wcnt_1))
+              (portRef C1 (instanceRef wcnt_2))
+              (portRef C0 (instanceRef wcnt_2))
+              (portRef D1 (instanceRef wcnt_2))
+              (portRef D0 (instanceRef wcnt_2))
+              (portRef C1 (instanceRef wcnt_3))
+              (portRef C0 (instanceRef wcnt_3))
+              (portRef D1 (instanceRef wcnt_3))
+              (portRef D0 (instanceRef wcnt_3))
+              (portRef C1 (instanceRef wcnt_4))
+              (portRef C0 (instanceRef wcnt_4))
+              (portRef D1 (instanceRef wcnt_4))
+              (portRef D0 (instanceRef wcnt_4))
+              (portRef C1 (instanceRef wcnt_5))
+              (portRef C0 (instanceRef wcnt_5))
+              (portRef D1 (instanceRef wcnt_5))
+              (portRef D0 (instanceRef wcnt_5))
+              (portRef C1 (instanceRef wcnt_6))
+              (portRef C0 (instanceRef wcnt_6))
+              (portRef D1 (instanceRef wcnt_6))
+              (portRef D0 (instanceRef wcnt_6))
+              (portRef C1 (instanceRef wcntd))
+              (portRef C0 (instanceRef wcntd))
+              (portRef D1 (instanceRef wcntd))
+              (portRef D0 (instanceRef wcntd))
+              (portRef C1 (instanceRef af_set_cmp_ci_a))
+              (portRef C0 (instanceRef af_set_cmp_ci_a))
+              (portRef D1 (instanceRef af_set_cmp_ci_a))
+              (portRef D0 (instanceRef af_set_cmp_ci_a))
+              (portRef D1 (instanceRef af_set_cmp_0))
+              (portRef D0 (instanceRef af_set_cmp_0))
+              (portRef C1 (instanceRef af_set_cmp_0))
+              (portRef C0 (instanceRef af_set_cmp_0))
+              (portRef D1 (instanceRef af_set_cmp_1))
+              (portRef D0 (instanceRef af_set_cmp_1))
+              (portRef C1 (instanceRef af_set_cmp_1))
+              (portRef C0 (instanceRef af_set_cmp_1))
+              (portRef D1 (instanceRef af_set_cmp_2))
+              (portRef D0 (instanceRef af_set_cmp_2))
+              (portRef C1 (instanceRef af_set_cmp_2))
+              (portRef C0 (instanceRef af_set_cmp_2))
+              (portRef D1 (instanceRef af_set_cmp_3))
+              (portRef D0 (instanceRef af_set_cmp_3))
+              (portRef C1 (instanceRef af_set_cmp_3))
+              (portRef C0 (instanceRef af_set_cmp_3))
+              (portRef D1 (instanceRef af_set_cmp_4))
+              (portRef D0 (instanceRef af_set_cmp_4))
+              (portRef C1 (instanceRef af_set_cmp_4))
+              (portRef C0 (instanceRef af_set_cmp_4))
+              (portRef D1 (instanceRef af_set_cmp_5))
+              (portRef D0 (instanceRef af_set_cmp_5))
+              (portRef C1 (instanceRef af_set_cmp_5))
+              (portRef C0 (instanceRef af_set_cmp_5))
+              (portRef D1 (instanceRef af_set_cmp_6))
+              (portRef D0 (instanceRef af_set_cmp_6))
+              (portRef C1 (instanceRef af_set_cmp_6))
+              (portRef C0 (instanceRef af_set_cmp_6))
+              (portRef C1 (instanceRef a2))
+              (portRef C0 (instanceRef a2))
+              (portRef D1 (instanceRef a2))
+              (portRef D0 (instanceRef a2))))
+          (net scuba_vlo
+            (joined
+              (portRef Z (instanceRef scuba_vlo_inst))
+              (portRef AD3 (instanceRef LUT4_1))
+              (portRef AD3 (instanceRef LUT4_0))
+              (portRef CSB2 (instanceRef pdp_ram_0_0_7))
+              (portRef CSA2 (instanceRef pdp_ram_0_0_7))
+              (portRef CSB1 (instanceRef pdp_ram_0_0_7))
+              (portRef CSA1 (instanceRef pdp_ram_0_0_7))
+              (portRef WEB (instanceRef pdp_ram_0_0_7))
+              (portRef ADB2 (instanceRef pdp_ram_0_0_7))
+              (portRef ADA2 (instanceRef pdp_ram_0_0_7))
+              (portRef ADB1 (instanceRef pdp_ram_0_0_7))
+              (portRef ADA1 (instanceRef pdp_ram_0_0_7))
+              (portRef ADB0 (instanceRef pdp_ram_0_0_7))
+              (portRef ADA0 (instanceRef pdp_ram_0_0_7))
+              (portRef DIB17 (instanceRef pdp_ram_0_0_7))
+              (portRef DIA17 (instanceRef pdp_ram_0_0_7))
+              (portRef DIB16 (instanceRef pdp_ram_0_0_7))
+              (portRef DIA16 (instanceRef pdp_ram_0_0_7))
+              (portRef DIB15 (instanceRef pdp_ram_0_0_7))
+              (portRef DIA15 (instanceRef pdp_ram_0_0_7))
+              (portRef DIB14 (instanceRef pdp_ram_0_0_7))
+              (portRef DIA14 (instanceRef pdp_ram_0_0_7))
+              (portRef DIB13 (instanceRef pdp_ram_0_0_7))
+              (portRef DIA13 (instanceRef pdp_ram_0_0_7))
+              (portRef DIB12 (instanceRef pdp_ram_0_0_7))
+              (portRef DIA12 (instanceRef pdp_ram_0_0_7))
+              (portRef DIB11 (instanceRef pdp_ram_0_0_7))
+              (portRef DIA11 (instanceRef pdp_ram_0_0_7))
+              (portRef DIB10 (instanceRef pdp_ram_0_0_7))
+              (portRef DIA10 (instanceRef pdp_ram_0_0_7))
+              (portRef DIB9 (instanceRef pdp_ram_0_0_7))
+              (portRef DIA9 (instanceRef pdp_ram_0_0_7))
+              (portRef DIB8 (instanceRef pdp_ram_0_0_7))
+              (portRef DIB7 (instanceRef pdp_ram_0_0_7))
+              (portRef DIB6 (instanceRef pdp_ram_0_0_7))
+              (portRef DIB5 (instanceRef pdp_ram_0_0_7))
+              (portRef DIB4 (instanceRef pdp_ram_0_0_7))
+              (portRef DIB3 (instanceRef pdp_ram_0_0_7))
+              (portRef DIB2 (instanceRef pdp_ram_0_0_7))
+              (portRef DIB1 (instanceRef pdp_ram_0_0_7))
+              (portRef DIB0 (instanceRef pdp_ram_0_0_7))
+              (portRef CSB2 (instanceRef pdp_ram_0_1_6))
+              (portRef CSA2 (instanceRef pdp_ram_0_1_6))
+              (portRef CSB1 (instanceRef pdp_ram_0_1_6))
+              (portRef CSA1 (instanceRef pdp_ram_0_1_6))
+              (portRef WEB (instanceRef pdp_ram_0_1_6))
+              (portRef ADB2 (instanceRef pdp_ram_0_1_6))
+              (portRef ADA2 (instanceRef pdp_ram_0_1_6))
+              (portRef ADB1 (instanceRef pdp_ram_0_1_6))
+              (portRef ADA1 (instanceRef pdp_ram_0_1_6))
+              (portRef ADB0 (instanceRef pdp_ram_0_1_6))
+              (portRef ADA0 (instanceRef pdp_ram_0_1_6))
+              (portRef DIB17 (instanceRef pdp_ram_0_1_6))
+              (portRef DIA17 (instanceRef pdp_ram_0_1_6))
+              (portRef DIB16 (instanceRef pdp_ram_0_1_6))
+              (portRef DIA16 (instanceRef pdp_ram_0_1_6))
+              (portRef DIB15 (instanceRef pdp_ram_0_1_6))
+              (portRef DIA15 (instanceRef pdp_ram_0_1_6))
+              (portRef DIB14 (instanceRef pdp_ram_0_1_6))
+              (portRef DIA14 (instanceRef pdp_ram_0_1_6))
+              (portRef DIB13 (instanceRef pdp_ram_0_1_6))
+              (portRef DIA13 (instanceRef pdp_ram_0_1_6))
+              (portRef DIB12 (instanceRef pdp_ram_0_1_6))
+              (portRef DIA12 (instanceRef pdp_ram_0_1_6))
+              (portRef DIB11 (instanceRef pdp_ram_0_1_6))
+              (portRef DIA11 (instanceRef pdp_ram_0_1_6))
+              (portRef DIB10 (instanceRef pdp_ram_0_1_6))
+              (portRef DIA10 (instanceRef pdp_ram_0_1_6))
+              (portRef DIB9 (instanceRef pdp_ram_0_1_6))
+              (portRef DIA9 (instanceRef pdp_ram_0_1_6))
+              (portRef DIB8 (instanceRef pdp_ram_0_1_6))
+              (portRef DIB7 (instanceRef pdp_ram_0_1_6))
+              (portRef DIB6 (instanceRef pdp_ram_0_1_6))
+              (portRef DIB5 (instanceRef pdp_ram_0_1_6))
+              (portRef DIB4 (instanceRef pdp_ram_0_1_6))
+              (portRef DIB3 (instanceRef pdp_ram_0_1_6))
+              (portRef DIB2 (instanceRef pdp_ram_0_1_6))
+              (portRef DIB1 (instanceRef pdp_ram_0_1_6))
+              (portRef DIB0 (instanceRef pdp_ram_0_1_6))
+              (portRef CSB2 (instanceRef pdp_ram_0_2_5))
+              (portRef CSA2 (instanceRef pdp_ram_0_2_5))
+              (portRef CSB1 (instanceRef pdp_ram_0_2_5))
+              (portRef CSA1 (instanceRef pdp_ram_0_2_5))
+              (portRef WEB (instanceRef pdp_ram_0_2_5))
+              (portRef ADB2 (instanceRef pdp_ram_0_2_5))
+              (portRef ADA2 (instanceRef pdp_ram_0_2_5))
+              (portRef ADB1 (instanceRef pdp_ram_0_2_5))
+              (portRef ADA1 (instanceRef pdp_ram_0_2_5))
+              (portRef ADB0 (instanceRef pdp_ram_0_2_5))
+              (portRef ADA0 (instanceRef pdp_ram_0_2_5))
+              (portRef DIB17 (instanceRef pdp_ram_0_2_5))
+              (portRef DIA17 (instanceRef pdp_ram_0_2_5))
+              (portRef DIB16 (instanceRef pdp_ram_0_2_5))
+              (portRef DIA16 (instanceRef pdp_ram_0_2_5))
+              (portRef DIB15 (instanceRef pdp_ram_0_2_5))
+              (portRef DIA15 (instanceRef pdp_ram_0_2_5))
+              (portRef DIB14 (instanceRef pdp_ram_0_2_5))
+              (portRef DIA14 (instanceRef pdp_ram_0_2_5))
+              (portRef DIB13 (instanceRef pdp_ram_0_2_5))
+              (portRef DIA13 (instanceRef pdp_ram_0_2_5))
+              (portRef DIB12 (instanceRef pdp_ram_0_2_5))
+              (portRef DIA12 (instanceRef pdp_ram_0_2_5))
+              (portRef DIB11 (instanceRef pdp_ram_0_2_5))
+              (portRef DIA11 (instanceRef pdp_ram_0_2_5))
+              (portRef DIB10 (instanceRef pdp_ram_0_2_5))
+              (portRef DIA10 (instanceRef pdp_ram_0_2_5))
+              (portRef DIB9 (instanceRef pdp_ram_0_2_5))
+              (portRef DIA9 (instanceRef pdp_ram_0_2_5))
+              (portRef DIB8 (instanceRef pdp_ram_0_2_5))
+              (portRef DIB7 (instanceRef pdp_ram_0_2_5))
+              (portRef DIB6 (instanceRef pdp_ram_0_2_5))
+              (portRef DIB5 (instanceRef pdp_ram_0_2_5))
+              (portRef DIB4 (instanceRef pdp_ram_0_2_5))
+              (portRef DIB3 (instanceRef pdp_ram_0_2_5))
+              (portRef DIB2 (instanceRef pdp_ram_0_2_5))
+              (portRef DIB1 (instanceRef pdp_ram_0_2_5))
+              (portRef DIB0 (instanceRef pdp_ram_0_2_5))
+              (portRef CSB2 (instanceRef pdp_ram_0_3_4))
+              (portRef CSA2 (instanceRef pdp_ram_0_3_4))
+              (portRef CSB1 (instanceRef pdp_ram_0_3_4))
+              (portRef CSA1 (instanceRef pdp_ram_0_3_4))
+              (portRef WEB (instanceRef pdp_ram_0_3_4))
+              (portRef ADB2 (instanceRef pdp_ram_0_3_4))
+              (portRef ADA2 (instanceRef pdp_ram_0_3_4))
+              (portRef ADB1 (instanceRef pdp_ram_0_3_4))
+              (portRef ADA1 (instanceRef pdp_ram_0_3_4))
+              (portRef ADB0 (instanceRef pdp_ram_0_3_4))
+              (portRef ADA0 (instanceRef pdp_ram_0_3_4))
+              (portRef DIB17 (instanceRef pdp_ram_0_3_4))
+              (portRef DIA17 (instanceRef pdp_ram_0_3_4))
+              (portRef DIB16 (instanceRef pdp_ram_0_3_4))
+              (portRef DIA16 (instanceRef pdp_ram_0_3_4))
+              (portRef DIB15 (instanceRef pdp_ram_0_3_4))
+              (portRef DIA15 (instanceRef pdp_ram_0_3_4))
+              (portRef DIB14 (instanceRef pdp_ram_0_3_4))
+              (portRef DIA14 (instanceRef pdp_ram_0_3_4))
+              (portRef DIB13 (instanceRef pdp_ram_0_3_4))
+              (portRef DIA13 (instanceRef pdp_ram_0_3_4))
+              (portRef DIB12 (instanceRef pdp_ram_0_3_4))
+              (portRef DIA12 (instanceRef pdp_ram_0_3_4))
+              (portRef DIB11 (instanceRef pdp_ram_0_3_4))
+              (portRef DIA11 (instanceRef pdp_ram_0_3_4))
+              (portRef DIB10 (instanceRef pdp_ram_0_3_4))
+              (portRef DIA10 (instanceRef pdp_ram_0_3_4))
+              (portRef DIB9 (instanceRef pdp_ram_0_3_4))
+              (portRef DIA9 (instanceRef pdp_ram_0_3_4))
+              (portRef DIB8 (instanceRef pdp_ram_0_3_4))
+              (portRef DIB7 (instanceRef pdp_ram_0_3_4))
+              (portRef DIB6 (instanceRef pdp_ram_0_3_4))
+              (portRef DIB5 (instanceRef pdp_ram_0_3_4))
+              (portRef DIB4 (instanceRef pdp_ram_0_3_4))
+              (portRef DIB3 (instanceRef pdp_ram_0_3_4))
+              (portRef DIB2 (instanceRef pdp_ram_0_3_4))
+              (portRef DIB1 (instanceRef pdp_ram_0_3_4))
+              (portRef DIB0 (instanceRef pdp_ram_0_3_4))
+              (portRef CSB2 (instanceRef pdp_ram_1_0_3))
+              (portRef CSA2 (instanceRef pdp_ram_1_0_3))
+              (portRef CSB1 (instanceRef pdp_ram_1_0_3))
+              (portRef CSA1 (instanceRef pdp_ram_1_0_3))
+              (portRef WEB (instanceRef pdp_ram_1_0_3))
+              (portRef ADB2 (instanceRef pdp_ram_1_0_3))
+              (portRef ADA2 (instanceRef pdp_ram_1_0_3))
+              (portRef ADB1 (instanceRef pdp_ram_1_0_3))
+              (portRef ADA1 (instanceRef pdp_ram_1_0_3))
+              (portRef ADB0 (instanceRef pdp_ram_1_0_3))
+              (portRef ADA0 (instanceRef pdp_ram_1_0_3))
+              (portRef DIB17 (instanceRef pdp_ram_1_0_3))
+              (portRef DIA17 (instanceRef pdp_ram_1_0_3))
+              (portRef DIB16 (instanceRef pdp_ram_1_0_3))
+              (portRef DIA16 (instanceRef pdp_ram_1_0_3))
+              (portRef DIB15 (instanceRef pdp_ram_1_0_3))
+              (portRef DIA15 (instanceRef pdp_ram_1_0_3))
+              (portRef DIB14 (instanceRef pdp_ram_1_0_3))
+              (portRef DIA14 (instanceRef pdp_ram_1_0_3))
+              (portRef DIB13 (instanceRef pdp_ram_1_0_3))
+              (portRef DIA13 (instanceRef pdp_ram_1_0_3))
+              (portRef DIB12 (instanceRef pdp_ram_1_0_3))
+              (portRef DIA12 (instanceRef pdp_ram_1_0_3))
+              (portRef DIB11 (instanceRef pdp_ram_1_0_3))
+              (portRef DIA11 (instanceRef pdp_ram_1_0_3))
+              (portRef DIB10 (instanceRef pdp_ram_1_0_3))
+              (portRef DIA10 (instanceRef pdp_ram_1_0_3))
+              (portRef DIB9 (instanceRef pdp_ram_1_0_3))
+              (portRef DIA9 (instanceRef pdp_ram_1_0_3))
+              (portRef DIB8 (instanceRef pdp_ram_1_0_3))
+              (portRef DIB7 (instanceRef pdp_ram_1_0_3))
+              (portRef DIB6 (instanceRef pdp_ram_1_0_3))
+              (portRef DIB5 (instanceRef pdp_ram_1_0_3))
+              (portRef DIB4 (instanceRef pdp_ram_1_0_3))
+              (portRef DIB3 (instanceRef pdp_ram_1_0_3))
+              (portRef DIB2 (instanceRef pdp_ram_1_0_3))
+              (portRef DIB1 (instanceRef pdp_ram_1_0_3))
+              (portRef DIB0 (instanceRef pdp_ram_1_0_3))
+              (portRef CSB2 (instanceRef pdp_ram_1_1_2))
+              (portRef CSA2 (instanceRef pdp_ram_1_1_2))
+              (portRef CSB1 (instanceRef pdp_ram_1_1_2))
+              (portRef CSA1 (instanceRef pdp_ram_1_1_2))
+              (portRef WEB (instanceRef pdp_ram_1_1_2))
+              (portRef ADB2 (instanceRef pdp_ram_1_1_2))
+              (portRef ADA2 (instanceRef pdp_ram_1_1_2))
+              (portRef ADB1 (instanceRef pdp_ram_1_1_2))
+              (portRef ADA1 (instanceRef pdp_ram_1_1_2))
+              (portRef ADB0 (instanceRef pdp_ram_1_1_2))
+              (portRef ADA0 (instanceRef pdp_ram_1_1_2))
+              (portRef DIB17 (instanceRef pdp_ram_1_1_2))
+              (portRef DIA17 (instanceRef pdp_ram_1_1_2))
+              (portRef DIB16 (instanceRef pdp_ram_1_1_2))
+              (portRef DIA16 (instanceRef pdp_ram_1_1_2))
+              (portRef DIB15 (instanceRef pdp_ram_1_1_2))
+              (portRef DIA15 (instanceRef pdp_ram_1_1_2))
+              (portRef DIB14 (instanceRef pdp_ram_1_1_2))
+              (portRef DIA14 (instanceRef pdp_ram_1_1_2))
+              (portRef DIB13 (instanceRef pdp_ram_1_1_2))
+              (portRef DIA13 (instanceRef pdp_ram_1_1_2))
+              (portRef DIB12 (instanceRef pdp_ram_1_1_2))
+              (portRef DIA12 (instanceRef pdp_ram_1_1_2))
+              (portRef DIB11 (instanceRef pdp_ram_1_1_2))
+              (portRef DIA11 (instanceRef pdp_ram_1_1_2))
+              (portRef DIB10 (instanceRef pdp_ram_1_1_2))
+              (portRef DIA10 (instanceRef pdp_ram_1_1_2))
+              (portRef DIB9 (instanceRef pdp_ram_1_1_2))
+              (portRef DIA9 (instanceRef pdp_ram_1_1_2))
+              (portRef DIB8 (instanceRef pdp_ram_1_1_2))
+              (portRef DIB7 (instanceRef pdp_ram_1_1_2))
+              (portRef DIB6 (instanceRef pdp_ram_1_1_2))
+              (portRef DIB5 (instanceRef pdp_ram_1_1_2))
+              (portRef DIB4 (instanceRef pdp_ram_1_1_2))
+              (portRef DIB3 (instanceRef pdp_ram_1_1_2))
+              (portRef DIB2 (instanceRef pdp_ram_1_1_2))
+              (portRef DIB1 (instanceRef pdp_ram_1_1_2))
+              (portRef DIB0 (instanceRef pdp_ram_1_1_2))
+              (portRef CSB2 (instanceRef pdp_ram_1_2_1))
+              (portRef CSA2 (instanceRef pdp_ram_1_2_1))
+              (portRef CSB1 (instanceRef pdp_ram_1_2_1))
+              (portRef CSA1 (instanceRef pdp_ram_1_2_1))
+              (portRef WEB (instanceRef pdp_ram_1_2_1))
+              (portRef ADB2 (instanceRef pdp_ram_1_2_1))
+              (portRef ADA2 (instanceRef pdp_ram_1_2_1))
+              (portRef ADB1 (instanceRef pdp_ram_1_2_1))
+              (portRef ADA1 (instanceRef pdp_ram_1_2_1))
+              (portRef ADB0 (instanceRef pdp_ram_1_2_1))
+              (portRef ADA0 (instanceRef pdp_ram_1_2_1))
+              (portRef DIB17 (instanceRef pdp_ram_1_2_1))
+              (portRef DIA17 (instanceRef pdp_ram_1_2_1))
+              (portRef DIB16 (instanceRef pdp_ram_1_2_1))
+              (portRef DIA16 (instanceRef pdp_ram_1_2_1))
+              (portRef DIB15 (instanceRef pdp_ram_1_2_1))
+              (portRef DIA15 (instanceRef pdp_ram_1_2_1))
+              (portRef DIB14 (instanceRef pdp_ram_1_2_1))
+              (portRef DIA14 (instanceRef pdp_ram_1_2_1))
+              (portRef DIB13 (instanceRef pdp_ram_1_2_1))
+              (portRef DIA13 (instanceRef pdp_ram_1_2_1))
+              (portRef DIB12 (instanceRef pdp_ram_1_2_1))
+              (portRef DIA12 (instanceRef pdp_ram_1_2_1))
+              (portRef DIB11 (instanceRef pdp_ram_1_2_1))
+              (portRef DIA11 (instanceRef pdp_ram_1_2_1))
+              (portRef DIB10 (instanceRef pdp_ram_1_2_1))
+              (portRef DIA10 (instanceRef pdp_ram_1_2_1))
+              (portRef DIB9 (instanceRef pdp_ram_1_2_1))
+              (portRef DIA9 (instanceRef pdp_ram_1_2_1))
+              (portRef DIB8 (instanceRef pdp_ram_1_2_1))
+              (portRef DIB7 (instanceRef pdp_ram_1_2_1))
+              (portRef DIB6 (instanceRef pdp_ram_1_2_1))
+              (portRef DIB5 (instanceRef pdp_ram_1_2_1))
+              (portRef DIB4 (instanceRef pdp_ram_1_2_1))
+              (portRef DIB3 (instanceRef pdp_ram_1_2_1))
+              (portRef DIB2 (instanceRef pdp_ram_1_2_1))
+              (portRef DIB1 (instanceRef pdp_ram_1_2_1))
+              (portRef DIB0 (instanceRef pdp_ram_1_2_1))
+              (portRef CSB2 (instanceRef pdp_ram_1_3_0))
+              (portRef CSA2 (instanceRef pdp_ram_1_3_0))
+              (portRef CSB1 (instanceRef pdp_ram_1_3_0))
+              (portRef CSA1 (instanceRef pdp_ram_1_3_0))
+              (portRef WEB (instanceRef pdp_ram_1_3_0))
+              (portRef ADB2 (instanceRef pdp_ram_1_3_0))
+              (portRef ADA2 (instanceRef pdp_ram_1_3_0))
+              (portRef ADB1 (instanceRef pdp_ram_1_3_0))
+              (portRef ADA1 (instanceRef pdp_ram_1_3_0))
+              (portRef ADB0 (instanceRef pdp_ram_1_3_0))
+              (portRef ADA0 (instanceRef pdp_ram_1_3_0))
+              (portRef DIB17 (instanceRef pdp_ram_1_3_0))
+              (portRef DIA17 (instanceRef pdp_ram_1_3_0))
+              (portRef DIB16 (instanceRef pdp_ram_1_3_0))
+              (portRef DIA16 (instanceRef pdp_ram_1_3_0))
+              (portRef DIB15 (instanceRef pdp_ram_1_3_0))
+              (portRef DIA15 (instanceRef pdp_ram_1_3_0))
+              (portRef DIB14 (instanceRef pdp_ram_1_3_0))
+              (portRef DIA14 (instanceRef pdp_ram_1_3_0))
+              (portRef DIB13 (instanceRef pdp_ram_1_3_0))
+              (portRef DIA13 (instanceRef pdp_ram_1_3_0))
+              (portRef DIB12 (instanceRef pdp_ram_1_3_0))
+              (portRef DIA12 (instanceRef pdp_ram_1_3_0))
+              (portRef DIB11 (instanceRef pdp_ram_1_3_0))
+              (portRef DIA11 (instanceRef pdp_ram_1_3_0))
+              (portRef DIB10 (instanceRef pdp_ram_1_3_0))
+              (portRef DIA10 (instanceRef pdp_ram_1_3_0))
+              (portRef DIB9 (instanceRef pdp_ram_1_3_0))
+              (portRef DIA9 (instanceRef pdp_ram_1_3_0))
+              (portRef DIB8 (instanceRef pdp_ram_1_3_0))
+              (portRef DIB7 (instanceRef pdp_ram_1_3_0))
+              (portRef DIB6 (instanceRef pdp_ram_1_3_0))
+              (portRef DIB5 (instanceRef pdp_ram_1_3_0))
+              (portRef DIB4 (instanceRef pdp_ram_1_3_0))
+              (portRef DIB3 (instanceRef pdp_ram_1_3_0))
+              (portRef DIB2 (instanceRef pdp_ram_1_3_0))
+              (portRef DIB1 (instanceRef pdp_ram_1_3_0))
+              (portRef DIB0 (instanceRef pdp_ram_1_3_0))
+              (portRef CD (instanceRef FF_15))
+              (portRef CD (instanceRef FF_14))
+              (portRef B0 (instanceRef bdcnt_bctr_cia))
+              (portRef A0 (instanceRef bdcnt_bctr_cia))
+              (portRef A1 (instanceRef bdcnt_bctr_6))
+              (portRef A1 (instanceRef e_cmp_0))
+              (portRef A0 (instanceRef e_cmp_1))
+              (portRef A1 (instanceRef e_cmp_1))
+              (portRef A0 (instanceRef e_cmp_2))
+              (portRef A1 (instanceRef e_cmp_2))
+              (portRef A0 (instanceRef e_cmp_3))
+              (portRef A1 (instanceRef e_cmp_3))
+              (portRef A0 (instanceRef e_cmp_4))
+              (portRef A1 (instanceRef e_cmp_4))
+              (portRef A0 (instanceRef e_cmp_5))
+              (portRef A1 (instanceRef e_cmp_5))
+              (portRef A0 (instanceRef e_cmp_6))
+              (portRef A1 (instanceRef e_cmp_6))
+              (portRef B1 (instanceRef e_cmp_6))
+              (portRef B1 (instanceRef a0))
+              (portRef B0 (instanceRef a0))
+              (portRef A1 (instanceRef a0))
+              (portRef A0 (instanceRef a0))
+              (portRef B1 (instanceRef g_cmp_6))
+              (portRef A1 (instanceRef g_cmp_6))
+              (portRef B1 (instanceRef a1))
+              (portRef B0 (instanceRef a1))
+              (portRef A1 (instanceRef a1))
+              (portRef A0 (instanceRef a1))
+              (portRef B0 (instanceRef w_ctr_cia))
+              (portRef A0 (instanceRef w_ctr_cia))
+              (portRef B1 (instanceRef w_ctr_0))
+              (portRef B0 (instanceRef w_ctr_0))
+              (portRef B1 (instanceRef w_ctr_1))
+              (portRef B0 (instanceRef w_ctr_1))
+              (portRef B1 (instanceRef w_ctr_2))
+              (portRef B0 (instanceRef w_ctr_2))
+              (portRef B1 (instanceRef w_ctr_3))
+              (portRef B0 (instanceRef w_ctr_3))
+              (portRef B1 (instanceRef w_ctr_4))
+              (portRef B0 (instanceRef w_ctr_4))
+              (portRef B1 (instanceRef w_ctr_5))
+              (portRef B0 (instanceRef w_ctr_5))
+              (portRef B1 (instanceRef w_ctr_6))
+              (portRef B0 (instanceRef w_ctr_6))
+              (portRef A1 (instanceRef w_ctr_6))
+              (portRef B0 (instanceRef r_ctr_cia))
+              (portRef A0 (instanceRef r_ctr_cia))
+              (portRef B1 (instanceRef r_ctr_0))
+              (portRef B0 (instanceRef r_ctr_0))
+              (portRef B1 (instanceRef r_ctr_1))
+              (portRef B0 (instanceRef r_ctr_1))
+              (portRef B1 (instanceRef r_ctr_2))
+              (portRef B0 (instanceRef r_ctr_2))
+              (portRef B1 (instanceRef r_ctr_3))
+              (portRef B0 (instanceRef r_ctr_3))
+              (portRef B1 (instanceRef r_ctr_4))
+              (portRef B0 (instanceRef r_ctr_4))
+              (portRef B1 (instanceRef r_ctr_5))
+              (portRef B0 (instanceRef r_ctr_5))
+              (portRef B1 (instanceRef r_ctr_6))
+              (portRef B0 (instanceRef r_ctr_6))
+              (portRef A1 (instanceRef r_ctr_6))
+              (portRef B1 (instanceRef wcnt_6))
+              (portRef B1 (instanceRef wcntd))
+              (portRef B0 (instanceRef wcntd))
+              (portRef A1 (instanceRef wcntd))
+              (portRef A0 (instanceRef wcntd))
+              (portRef B0 (instanceRef af_set_cmp_ci_a))
+              (portRef A0 (instanceRef af_set_cmp_ci_a))
+              (portRef B0 (instanceRef af_set_cmp_6))
+              (portRef B1 (instanceRef af_set_cmp_6))
+              (portRef A1 (instanceRef af_set_cmp_6))
+              (portRef B1 (instanceRef a2))
+              (portRef B0 (instanceRef a2))
+              (portRef A1 (instanceRef a2))
+              (portRef A0 (instanceRef a2))))
+          (net af_set_c
+            (joined
+              (portRef CIN (instanceRef a2))
+              (portRef COUT (instanceRef af_set_cmp_6))))
+          (net partial_full
+            (joined
+              (portRef AlmostFull)
+              (portRef Q (instanceRef FF_0))))
+          (net Full
+            (joined
+              (portRef Full)
+              (portRef Q (instanceRef FF_68))
+              (portRef A (instanceRef INV_5))
+              (portRef AD0 (instanceRef LUT4_0))))
+          (net Empty
+            (joined
+              (portRef Empty)
+              (portRef Q (instanceRef FF_69))
+              (portRef A (instanceRef INV_4))
+              (portRef AD0 (instanceRef LUT4_1))))
+          (net WCNT12
+            (joined
+              (portRef (member WCNT 0))
+              (portRef A0 (instanceRef g_cmp_6))
+              (portRef Q (instanceRef FF_70))
+              (portRef A0 (instanceRef bdcnt_bctr_6))
+              (portRef B0 (instanceRef e_cmp_6))))
+          (net WCNT11
+            (joined
+              (portRef (member WCNT 1))
+              (portRef A1 (instanceRef g_cmp_5))
+              (portRef Q (instanceRef FF_71))
+              (portRef A1 (instanceRef bdcnt_bctr_5))
+              (portRef B1 (instanceRef e_cmp_5))))
+          (net WCNT10
+            (joined
+              (portRef (member WCNT 2))
+              (portRef A0 (instanceRef g_cmp_5))
+              (portRef Q (instanceRef FF_72))
+              (portRef A0 (instanceRef bdcnt_bctr_5))
+              (portRef B0 (instanceRef e_cmp_5))))
+          (net WCNT9
+            (joined
+              (portRef (member WCNT 3))
+              (portRef A1 (instanceRef g_cmp_4))
+              (portRef Q (instanceRef FF_73))
+              (portRef A1 (instanceRef bdcnt_bctr_4))
+              (portRef B1 (instanceRef e_cmp_4))))
+          (net WCNT8
+            (joined
+              (portRef (member WCNT 4))
+              (portRef A0 (instanceRef g_cmp_4))
+              (portRef Q (instanceRef FF_74))
+              (portRef A0 (instanceRef bdcnt_bctr_4))
+              (portRef B0 (instanceRef e_cmp_4))))
+          (net WCNT7
+            (joined
+              (portRef (member WCNT 5))
+              (portRef A1 (instanceRef g_cmp_3))
+              (portRef Q (instanceRef FF_75))
+              (portRef A1 (instanceRef bdcnt_bctr_3))
+              (portRef B1 (instanceRef e_cmp_3))))
+          (net WCNT6
+            (joined
+              (portRef (member WCNT 6))
+              (portRef A0 (instanceRef g_cmp_3))
+              (portRef Q (instanceRef FF_76))
+              (portRef A0 (instanceRef bdcnt_bctr_3))
+              (portRef B0 (instanceRef e_cmp_3))))
+          (net WCNT5
+            (joined
+              (portRef (member WCNT 7))
+              (portRef A1 (instanceRef g_cmp_2))
+              (portRef Q (instanceRef FF_77))
+              (portRef A1 (instanceRef bdcnt_bctr_2))
+              (portRef B1 (instanceRef e_cmp_2))))
+          (net WCNT4
+            (joined
+              (portRef (member WCNT 8))
+              (portRef A0 (instanceRef g_cmp_2))
+              (portRef Q (instanceRef FF_78))
+              (portRef A0 (instanceRef bdcnt_bctr_2))
+              (portRef B0 (instanceRef e_cmp_2))))
+          (net WCNT3
+            (joined
+              (portRef (member WCNT 9))
+              (portRef A1 (instanceRef g_cmp_1))
+              (portRef Q (instanceRef FF_79))
+              (portRef A1 (instanceRef bdcnt_bctr_1))
+              (portRef B1 (instanceRef e_cmp_1))))
+          (net WCNT2
+            (joined
+              (portRef (member WCNT 10))
+              (portRef A0 (instanceRef g_cmp_1))
+              (portRef Q (instanceRef FF_80))
+              (portRef A0 (instanceRef bdcnt_bctr_1))
+              (portRef B0 (instanceRef e_cmp_1))))
+          (net WCNT1
+            (joined
+              (portRef (member WCNT 11))
+              (portRef A1 (instanceRef g_cmp_0))
+              (portRef Q (instanceRef FF_81))
+              (portRef A1 (instanceRef bdcnt_bctr_0))
+              (portRef B1 (instanceRef e_cmp_0))))
+          (net WCNT0
+            (joined
+              (portRef (member WCNT 12))
+              (portRef A0 (instanceRef g_cmp_0))
+              (portRef Q (instanceRef FF_82))
+              (portRef A0 (instanceRef bdcnt_bctr_0))
+              (portRef B0 (instanceRef e_cmp_0))))
+          (net dataout35
+            (joined
+              (portRef (member Q 0))
+              (portRef Z (instanceRef mux_0))))
+          (net dataout34
+            (joined
+              (portRef (member Q 1))
+              (portRef Z (instanceRef mux_1))))
+          (net dataout33
+            (joined
+              (portRef (member Q 2))
+              (portRef Z (instanceRef mux_2))))
+          (net dataout32
+            (joined
+              (portRef (member Q 3))
+              (portRef Z (instanceRef mux_3))))
+          (net dataout31
+            (joined
+              (portRef (member Q 4))
+              (portRef Z (instanceRef mux_4))))
+          (net dataout30
+            (joined
+              (portRef (member Q 5))
+              (portRef Z (instanceRef mux_5))))
+          (net dataout29
+            (joined
+              (portRef (member Q 6))
+              (portRef Z (instanceRef mux_6))))
+          (net dataout28
+            (joined
+              (portRef (member Q 7))
+              (portRef Z (instanceRef mux_7))))
+          (net dataout27
+            (joined
+              (portRef (member Q 8))
+              (portRef Z (instanceRef mux_8))))
+          (net dataout26
+            (joined
+              (portRef (member Q 9))
+              (portRef Z (instanceRef mux_9))))
+          (net dataout25
+            (joined
+              (portRef (member Q 10))
+              (portRef Z (instanceRef mux_10))))
+          (net dataout24
+            (joined
+              (portRef (member Q 11))
+              (portRef Z (instanceRef mux_11))))
+          (net dataout23
+            (joined
+              (portRef (member Q 12))
+              (portRef Z (instanceRef mux_12))))
+          (net dataout22
+            (joined
+              (portRef (member Q 13))
+              (portRef Z (instanceRef mux_13))))
+          (net dataout21
+            (joined
+              (portRef (member Q 14))
+              (portRef Z (instanceRef mux_14))))
+          (net dataout20
+            (joined
+              (portRef (member Q 15))
+              (portRef Z (instanceRef mux_15))))
+          (net dataout19
+            (joined
+              (portRef (member Q 16))
+              (portRef Z (instanceRef mux_16))))
+          (net dataout18
+            (joined
+              (portRef (member Q 17))
+              (portRef Z (instanceRef mux_17))))
+          (net dataout17
+            (joined
+              (portRef (member Q 18))
+              (portRef Z (instanceRef mux_18))))
+          (net dataout16
+            (joined
+              (portRef (member Q 19))
+              (portRef Z (instanceRef mux_19))))
+          (net dataout15
+            (joined
+              (portRef (member Q 20))
+              (portRef Z (instanceRef mux_20))))
+          (net dataout14
+            (joined
+              (portRef (member Q 21))
+              (portRef Z (instanceRef mux_21))))
+          (net dataout13
+            (joined
+              (portRef (member Q 22))
+              (portRef Z (instanceRef mux_22))))
+          (net dataout12
+            (joined
+              (portRef (member Q 23))
+              (portRef Z (instanceRef mux_23))))
+          (net dataout11
+            (joined
+              (portRef (member Q 24))
+              (portRef Z (instanceRef mux_24))))
+          (net dataout10
+            (joined
+              (portRef (member Q 25))
+              (portRef Z (instanceRef mux_25))))
+          (net dataout9
+            (joined
+              (portRef (member Q 26))
+              (portRef Z (instanceRef mux_26))))
+          (net dataout8
+            (joined
+              (portRef (member Q 27))
+              (portRef Z (instanceRef mux_27))))
+          (net dataout7
+            (joined
+              (portRef (member Q 28))
+              (portRef Z (instanceRef mux_28))))
+          (net dataout6
+            (joined
+              (portRef (member Q 29))
+              (portRef Z (instanceRef mux_29))))
+          (net dataout5
+            (joined
+              (portRef (member Q 30))
+              (portRef Z (instanceRef mux_30))))
+          (net dataout4
+            (joined
+              (portRef (member Q 31))
+              (portRef Z (instanceRef mux_31))))
+          (net dataout3
+            (joined
+              (portRef (member Q 32))
+              (portRef Z (instanceRef mux_32))))
+          (net dataout2
+            (joined
+              (portRef (member Q 33))
+              (portRef Z (instanceRef mux_33))))
+          (net dataout1
+            (joined
+              (portRef (member Q 34))
+              (portRef Z (instanceRef mux_34))))
+          (net dataout0
+            (joined
+              (portRef (member Q 35))
+              (portRef Z (instanceRef mux_35))))
+          (net AmFullThresh11
+            (joined
+              (portRef (member AmFullThresh 0))
+              (portRef B1 (instanceRef af_set_cmp_5))))
+          (net AmFullThresh10
+            (joined
+              (portRef (member AmFullThresh 1))
+              (portRef B0 (instanceRef af_set_cmp_5))))
+          (net AmFullThresh9
+            (joined
+              (portRef (member AmFullThresh 2))
+              (portRef B1 (instanceRef af_set_cmp_4))))
+          (net AmFullThresh8
+            (joined
+              (portRef (member AmFullThresh 3))
+              (portRef B0 (instanceRef af_set_cmp_4))))
+          (net AmFullThresh7
+            (joined
+              (portRef (member AmFullThresh 4))
+              (portRef B1 (instanceRef af_set_cmp_3))))
+          (net AmFullThresh6
+            (joined
+              (portRef (member AmFullThresh 5))
+              (portRef B0 (instanceRef af_set_cmp_3))))
+          (net AmFullThresh5
+            (joined
+              (portRef (member AmFullThresh 6))
+              (portRef B1 (instanceRef af_set_cmp_2))))
+          (net AmFullThresh4
+            (joined
+              (portRef (member AmFullThresh 7))
+              (portRef B0 (instanceRef af_set_cmp_2))))
+          (net AmFullThresh3
+            (joined
+              (portRef (member AmFullThresh 8))
+              (portRef B1 (instanceRef af_set_cmp_1))))
+          (net AmFullThresh2
+            (joined
+              (portRef (member AmFullThresh 9))
+              (portRef B0 (instanceRef af_set_cmp_1))))
+          (net AmFullThresh1
+            (joined
+              (portRef (member AmFullThresh 10))
+              (portRef B1 (instanceRef af_set_cmp_0))))
+          (net AmFullThresh0
+            (joined
+              (portRef (member AmFullThresh 11))
+              (portRef B0 (instanceRef af_set_cmp_0))))
+          (net reset
+            (joined
+              (portRef Reset)
+              (portRef RSTB (instanceRef pdp_ram_0_0_7))
+              (portRef RSTA (instanceRef pdp_ram_0_0_7))
+              (portRef RSTB (instanceRef pdp_ram_0_1_6))
+              (portRef RSTA (instanceRef pdp_ram_0_1_6))
+              (portRef RSTB (instanceRef pdp_ram_0_2_5))
+              (portRef RSTA (instanceRef pdp_ram_0_2_5))
+              (portRef RSTB (instanceRef pdp_ram_0_3_4))
+              (portRef RSTA (instanceRef pdp_ram_0_3_4))
+              (portRef RSTB (instanceRef pdp_ram_1_0_3))
+              (portRef RSTA (instanceRef pdp_ram_1_0_3))
+              (portRef RSTB (instanceRef pdp_ram_1_1_2))
+              (portRef RSTA (instanceRef pdp_ram_1_1_2))
+              (portRef RSTB (instanceRef pdp_ram_1_2_1))
+              (portRef RSTA (instanceRef pdp_ram_1_2_1))
+              (portRef RSTB (instanceRef pdp_ram_1_3_0))
+              (portRef RSTA (instanceRef pdp_ram_1_3_0))
+              (portRef CD (instanceRef FF_82))
+              (portRef CD (instanceRef FF_81))
+              (portRef CD (instanceRef FF_80))
+              (portRef CD (instanceRef FF_79))
+              (portRef CD (instanceRef FF_78))
+              (portRef CD (instanceRef FF_77))
+              (portRef CD (instanceRef FF_76))
+              (portRef CD (instanceRef FF_75))
+              (portRef CD (instanceRef FF_74))
+              (portRef CD (instanceRef FF_73))
+              (portRef CD (instanceRef FF_72))
+              (portRef CD (instanceRef FF_71))
+              (portRef CD (instanceRef FF_70))
+              (portRef PD (instanceRef FF_69))
+              (portRef CD (instanceRef FF_68))
+              (portRef PD (instanceRef FF_67))
+              (portRef CD (instanceRef FF_66))
+              (portRef CD (instanceRef FF_65))
+              (portRef CD (instanceRef FF_64))
+              (portRef CD (instanceRef FF_63))
+              (portRef CD (instanceRef FF_62))
+              (portRef CD (instanceRef FF_61))
+              (portRef CD (instanceRef FF_60))
+              (portRef CD (instanceRef FF_59))
+              (portRef CD (instanceRef FF_58))
+              (portRef CD (instanceRef FF_57))
+              (portRef CD (instanceRef FF_56))
+              (portRef CD (instanceRef FF_55))
+              (portRef PD (instanceRef FF_54))
+              (portRef CD (instanceRef FF_53))
+              (portRef CD (instanceRef FF_52))
+              (portRef CD (instanceRef FF_51))
+              (portRef CD (instanceRef FF_50))
+              (portRef CD (instanceRef FF_49))
+              (portRef CD (instanceRef FF_48))
+              (portRef CD (instanceRef FF_47))
+              (portRef CD (instanceRef FF_46))
+              (portRef CD (instanceRef FF_45))
+              (portRef CD (instanceRef FF_44))
+              (portRef CD (instanceRef FF_43))
+              (portRef CD (instanceRef FF_42))
+              (portRef CD (instanceRef FF_41))
+              (portRef CD (instanceRef FF_40))
+              (portRef CD (instanceRef FF_39))
+              (portRef CD (instanceRef FF_38))
+              (portRef CD (instanceRef FF_37))
+              (portRef CD (instanceRef FF_36))
+              (portRef CD (instanceRef FF_35))
+              (portRef CD (instanceRef FF_34))
+              (portRef CD (instanceRef FF_33))
+              (portRef CD (instanceRef FF_32))
+              (portRef CD (instanceRef FF_31))
+              (portRef CD (instanceRef FF_30))
+              (portRef CD (instanceRef FF_29))
+              (portRef CD (instanceRef FF_28))
+              (portRef CD (instanceRef FF_27))
+              (portRef CD (instanceRef FF_26))
+              (portRef CD (instanceRef FF_25))
+              (portRef CD (instanceRef FF_24))
+              (portRef CD (instanceRef FF_23))
+              (portRef CD (instanceRef FF_22))
+              (portRef CD (instanceRef FF_21))
+              (portRef CD (instanceRef FF_20))
+              (portRef CD (instanceRef FF_19))
+              (portRef CD (instanceRef FF_18))
+              (portRef CD (instanceRef FF_17))
+              (portRef CD (instanceRef FF_16))
+              (portRef CD (instanceRef FF_13))
+              (portRef CD (instanceRef FF_12))
+              (portRef CD (instanceRef FF_11))
+              (portRef CD (instanceRef FF_10))
+              (portRef CD (instanceRef FF_9))
+              (portRef CD (instanceRef FF_8))
+              (portRef CD (instanceRef FF_7))
+              (portRef CD (instanceRef FF_6))
+              (portRef CD (instanceRef FF_5))
+              (portRef CD (instanceRef FF_4))
+              (portRef CD (instanceRef FF_3))
+              (portRef CD (instanceRef FF_2))
+              (portRef CD (instanceRef FF_1))
+              (portRef CD (instanceRef FF_0))))
+          (net rden
+            (joined
+              (portRef RdEn)
+              (portRef A (instanceRef AND2_t4))))
+          (net wren
+            (joined
+              (portRef WrEn)
+              (portRef A (instanceRef AND2_t5))))
+          (net clk
+            (joined
+              (portRef Clock)
+              (portRef CLKB (instanceRef pdp_ram_0_0_7))
+              (portRef CLKA (instanceRef pdp_ram_0_0_7))
+              (portRef CLKB (instanceRef pdp_ram_0_1_6))
+              (portRef CLKA (instanceRef pdp_ram_0_1_6))
+              (portRef CLKB (instanceRef pdp_ram_0_2_5))
+              (portRef CLKA (instanceRef pdp_ram_0_2_5))
+              (portRef CLKB (instanceRef pdp_ram_0_3_4))
+              (portRef CLKA (instanceRef pdp_ram_0_3_4))
+              (portRef CLKB (instanceRef pdp_ram_1_0_3))
+              (portRef CLKA (instanceRef pdp_ram_1_0_3))
+              (portRef CLKB (instanceRef pdp_ram_1_1_2))
+              (portRef CLKA (instanceRef pdp_ram_1_1_2))
+              (portRef CLKB (instanceRef pdp_ram_1_2_1))
+              (portRef CLKA (instanceRef pdp_ram_1_2_1))
+              (portRef CLKB (instanceRef pdp_ram_1_3_0))
+              (portRef CLKA (instanceRef pdp_ram_1_3_0))
+              (portRef CK (instanceRef FF_82))
+              (portRef CK (instanceRef FF_81))
+              (portRef CK (instanceRef FF_80))
+              (portRef CK (instanceRef FF_79))
+              (portRef CK (instanceRef FF_78))
+              (portRef CK (instanceRef FF_77))
+              (portRef CK (instanceRef FF_76))
+              (portRef CK (instanceRef FF_75))
+              (portRef CK (instanceRef FF_74))
+              (portRef CK (instanceRef FF_73))
+              (portRef CK (instanceRef FF_72))
+              (portRef CK (instanceRef FF_71))
+              (portRef CK (instanceRef FF_70))
+              (portRef CK (instanceRef FF_69))
+              (portRef CK (instanceRef FF_68))
+              (portRef CK (instanceRef FF_67))
+              (portRef CK (instanceRef FF_66))
+              (portRef CK (instanceRef FF_65))
+              (portRef CK (instanceRef FF_64))
+              (portRef CK (instanceRef FF_63))
+              (portRef CK (instanceRef FF_62))
+              (portRef CK (instanceRef FF_61))
+              (portRef CK (instanceRef FF_60))
+              (portRef CK (instanceRef FF_59))
+              (portRef CK (instanceRef FF_58))
+              (portRef CK (instanceRef FF_57))
+              (portRef CK (instanceRef FF_56))
+              (portRef CK (instanceRef FF_55))
+              (portRef CK (instanceRef FF_54))
+              (portRef CK (instanceRef FF_53))
+              (portRef CK (instanceRef FF_52))
+              (portRef CK (instanceRef FF_51))
+              (portRef CK (instanceRef FF_50))
+              (portRef CK (instanceRef FF_49))
+              (portRef CK (instanceRef FF_48))
+              (portRef CK (instanceRef FF_47))
+              (portRef CK (instanceRef FF_46))
+              (portRef CK (instanceRef FF_45))
+              (portRef CK (instanceRef FF_44))
+              (portRef CK (instanceRef FF_43))
+              (portRef CK (instanceRef FF_42))
+              (portRef CK (instanceRef FF_41))
+              (portRef CK (instanceRef FF_40))
+              (portRef CK (instanceRef FF_39))
+              (portRef CK (instanceRef FF_38))
+              (portRef CK (instanceRef FF_37))
+              (portRef CK (instanceRef FF_36))
+              (portRef CK (instanceRef FF_35))
+              (portRef CK (instanceRef FF_34))
+              (portRef CK (instanceRef FF_33))
+              (portRef CK (instanceRef FF_32))
+              (portRef CK (instanceRef FF_31))
+              (portRef CK (instanceRef FF_30))
+              (portRef CK (instanceRef FF_29))
+              (portRef CK (instanceRef FF_28))
+              (portRef CK (instanceRef FF_27))
+              (portRef CK (instanceRef FF_26))
+              (portRef CK (instanceRef FF_25))
+              (portRef CK (instanceRef FF_24))
+              (portRef CK (instanceRef FF_23))
+              (portRef CK (instanceRef FF_22))
+              (portRef CK (instanceRef FF_21))
+              (portRef CK (instanceRef FF_20))
+              (portRef CK (instanceRef FF_19))
+              (portRef CK (instanceRef FF_18))
+              (portRef CK (instanceRef FF_17))
+              (portRef CK (instanceRef FF_16))
+              (portRef CK (instanceRef FF_15))
+              (portRef CK (instanceRef FF_14))
+              (portRef CK (instanceRef FF_13))
+              (portRef CK (instanceRef FF_12))
+              (portRef CK (instanceRef FF_11))
+              (portRef CK (instanceRef FF_10))
+              (portRef CK (instanceRef FF_9))
+              (portRef CK (instanceRef FF_8))
+              (portRef CK (instanceRef FF_7))
+              (portRef CK (instanceRef FF_6))
+              (portRef CK (instanceRef FF_5))
+              (portRef CK (instanceRef FF_4))
+              (portRef CK (instanceRef FF_3))
+              (portRef CK (instanceRef FF_2))
+              (portRef CK (instanceRef FF_1))
+              (portRef CK (instanceRef FF_0))))
+          (net datain35
+            (joined
+              (portRef (member Data 0))
+              (portRef DIA8 (instanceRef pdp_ram_0_3_4))
+              (portRef DIA8 (instanceRef pdp_ram_1_3_0))))
+          (net datain34
+            (joined
+              (portRef (member Data 1))
+              (portRef DIA7 (instanceRef pdp_ram_0_3_4))
+              (portRef DIA7 (instanceRef pdp_ram_1_3_0))))
+          (net datain33
+            (joined
+              (portRef (member Data 2))
+              (portRef DIA6 (instanceRef pdp_ram_0_3_4))
+              (portRef DIA6 (instanceRef pdp_ram_1_3_0))))
+          (net datain32
+            (joined
+              (portRef (member Data 3))
+              (portRef DIA5 (instanceRef pdp_ram_0_3_4))
+              (portRef DIA5 (instanceRef pdp_ram_1_3_0))))
+          (net datain31
+            (joined
+              (portRef (member Data 4))
+              (portRef DIA4 (instanceRef pdp_ram_0_3_4))
+              (portRef DIA4 (instanceRef pdp_ram_1_3_0))))
+          (net datain30
+            (joined
+              (portRef (member Data 5))
+              (portRef DIA3 (instanceRef pdp_ram_0_3_4))
+              (portRef DIA3 (instanceRef pdp_ram_1_3_0))))
+          (net datain29
+            (joined
+              (portRef (member Data 6))
+              (portRef DIA2 (instanceRef pdp_ram_0_3_4))
+              (portRef DIA2 (instanceRef pdp_ram_1_3_0))))
+          (net datain28
+            (joined
+              (portRef (member Data 7))
+              (portRef DIA1 (instanceRef pdp_ram_0_3_4))
+              (portRef DIA1 (instanceRef pdp_ram_1_3_0))))
+          (net datain27
+            (joined
+              (portRef (member Data 8))
+              (portRef DIA0 (instanceRef pdp_ram_0_3_4))
+              (portRef DIA0 (instanceRef pdp_ram_1_3_0))))
+          (net datain26
+            (joined
+              (portRef (member Data 9))
+              (portRef DIA8 (instanceRef pdp_ram_0_2_5))
+              (portRef DIA8 (instanceRef pdp_ram_1_2_1))))
+          (net datain25
+            (joined
+              (portRef (member Data 10))
+              (portRef DIA7 (instanceRef pdp_ram_0_2_5))
+              (portRef DIA7 (instanceRef pdp_ram_1_2_1))))
+          (net datain24
+            (joined
+              (portRef (member Data 11))
+              (portRef DIA6 (instanceRef pdp_ram_0_2_5))
+              (portRef DIA6 (instanceRef pdp_ram_1_2_1))))
+          (net datain23
+            (joined
+              (portRef (member Data 12))
+              (portRef DIA5 (instanceRef pdp_ram_0_2_5))
+              (portRef DIA5 (instanceRef pdp_ram_1_2_1))))
+          (net datain22
+            (joined
+              (portRef (member Data 13))
+              (portRef DIA4 (instanceRef pdp_ram_0_2_5))
+              (portRef DIA4 (instanceRef pdp_ram_1_2_1))))
+          (net datain21
+            (joined
+              (portRef (member Data 14))
+              (portRef DIA3 (instanceRef pdp_ram_0_2_5))
+              (portRef DIA3 (instanceRef pdp_ram_1_2_1))))
+          (net datain20
+            (joined
+              (portRef (member Data 15))
+              (portRef DIA2 (instanceRef pdp_ram_0_2_5))
+              (portRef DIA2 (instanceRef pdp_ram_1_2_1))))
+          (net datain19
+            (joined
+              (portRef (member Data 16))
+              (portRef DIA1 (instanceRef pdp_ram_0_2_5))
+              (portRef DIA1 (instanceRef pdp_ram_1_2_1))))
+          (net datain18
+            (joined
+              (portRef (member Data 17))
+              (portRef DIA0 (instanceRef pdp_ram_0_2_5))
+              (portRef DIA0 (instanceRef pdp_ram_1_2_1))))
+          (net datain17
+            (joined
+              (portRef (member Data 18))
+              (portRef DIA8 (instanceRef pdp_ram_0_1_6))
+              (portRef DIA8 (instanceRef pdp_ram_1_1_2))))
+          (net datain16
+            (joined
+              (portRef (member Data 19))
+              (portRef DIA7 (instanceRef pdp_ram_0_1_6))
+              (portRef DIA7 (instanceRef pdp_ram_1_1_2))))
+          (net datain15
+            (joined
+              (portRef (member Data 20))
+              (portRef DIA6 (instanceRef pdp_ram_0_1_6))
+              (portRef DIA6 (instanceRef pdp_ram_1_1_2))))
+          (net datain14
+            (joined
+              (portRef (member Data 21))
+              (portRef DIA5 (instanceRef pdp_ram_0_1_6))
+              (portRef DIA5 (instanceRef pdp_ram_1_1_2))))
+          (net datain13
+            (joined
+              (portRef (member Data 22))
+              (portRef DIA4 (instanceRef pdp_ram_0_1_6))
+              (portRef DIA4 (instanceRef pdp_ram_1_1_2))))
+          (net datain12
+            (joined
+              (portRef (member Data 23))
+              (portRef DIA3 (instanceRef pdp_ram_0_1_6))
+              (portRef DIA3 (instanceRef pdp_ram_1_1_2))))
+          (net datain11
+            (joined
+              (portRef (member Data 24))
+              (portRef DIA2 (instanceRef pdp_ram_0_1_6))
+              (portRef DIA2 (instanceRef pdp_ram_1_1_2))))
+          (net datain10
+            (joined
+              (portRef (member Data 25))
+              (portRef DIA1 (instanceRef pdp_ram_0_1_6))
+              (portRef DIA1 (instanceRef pdp_ram_1_1_2))))
+          (net datain9
+            (joined
+              (portRef (member Data 26))
+              (portRef DIA0 (instanceRef pdp_ram_0_1_6))
+              (portRef DIA0 (instanceRef pdp_ram_1_1_2))))
+          (net datain8
+            (joined
+              (portRef (member Data 27))
+              (portRef DIA8 (instanceRef pdp_ram_0_0_7))
+              (portRef DIA8 (instanceRef pdp_ram_1_0_3))))
+          (net datain7
+            (joined
+              (portRef (member Data 28))
+              (portRef DIA7 (instanceRef pdp_ram_0_0_7))
+              (portRef DIA7 (instanceRef pdp_ram_1_0_3))))
+          (net datain6
+            (joined
+              (portRef (member Data 29))
+              (portRef DIA6 (instanceRef pdp_ram_0_0_7))
+              (portRef DIA6 (instanceRef pdp_ram_1_0_3))))
+          (net datain5
+            (joined
+              (portRef (member Data 30))
+              (portRef DIA5 (instanceRef pdp_ram_0_0_7))
+              (portRef DIA5 (instanceRef pdp_ram_1_0_3))))
+          (net datain4
+            (joined
+              (portRef (member Data 31))
+              (portRef DIA4 (instanceRef pdp_ram_0_0_7))
+              (portRef DIA4 (instanceRef pdp_ram_1_0_3))))
+          (net datain3
+            (joined
+              (portRef (member Data 32))
+              (portRef DIA3 (instanceRef pdp_ram_0_0_7))
+              (portRef DIA3 (instanceRef pdp_ram_1_0_3))))
+          (net datain2
+            (joined
+              (portRef (member Data 33))
+              (portRef DIA2 (instanceRef pdp_ram_0_0_7))
+              (portRef DIA2 (instanceRef pdp_ram_1_0_3))))
+          (net datain1
+            (joined
+              (portRef (member Data 34))
+              (portRef DIA1 (instanceRef pdp_ram_0_0_7))
+              (portRef DIA1 (instanceRef pdp_ram_1_0_3))))
+          (net datain0
+            (joined
+              (portRef (member Data 35))
+              (portRef DIA0 (instanceRef pdp_ram_0_0_7))
+              (portRef DIA0 (instanceRef pdp_ram_1_0_3))))))))
+  (design fifo_36x4k_oreg
+    (cellRef fifo_36x4k_oreg
+      (libraryRef ORCLIB)))
+)

diff --git a/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.fdc b/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.fdc
new file mode 100644 (file)
index 0000000..6fbcac9
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.fdc
@@ -0,0 +1,2 @@
+###==== Start Configuration
+

diff --git a/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.lpc b/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.lpc
new file mode 100644 (file)
index 0000000..86d40cd
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.lpc
@@ -0,0 +1,50 @@
+[Device]
+Family=ecp5um
+PartType=LFE5UM-85F
+PartName=LFE5UM-85F-8MG285C
+SpeedGrade=8
+Package=CSFBGA285
+OperatingCondition=COM
+Status=C
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO
+CoreRevision=5.0
+ModuleName=fifo_36x4k_oreg
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=03/18/2015
+Time=14:41:29
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=4096
+Width=36
+regout=1
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=1
+PfMode=Dynamic - Single Threshold
+PfAssert=508
+PfDeassert=506
+Reset=Async
+Reset1=Sync
+RDataCount=1
+EnECC=0
+EnFWFT=0
+
+[Command]
+cmd_line= -w -n fifo_36x4k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 4096 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill

diff --git a/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.ngd b/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.ngd
new file mode 100644 (file)
index 0000000..0d6ed61
Binary files /dev/null and b/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.ngd differ

diff --git a/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.ngo b/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.ngo
new file mode 100644 (file)
index 0000000..6df561d
Binary files /dev/null and b/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.ngo differ

diff --git a/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.vhd b/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.vhd
new file mode 100644 (file)
index 0000000..bbb25a5
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.vhd
@@ -0,0 +1,1721 @@
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80
+-- Module  Version: 5.0
+--/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x4k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 4096 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.fdc 
+
+-- Wed Mar 18 14:41:31 2015
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity fifo_36x4k_oreg is
+    port (
+        Data: in  std_logic_vector(35 downto 0); 
+        Clock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        AmFullThresh: in  std_logic_vector(11 downto 0); 
+        Q: out  std_logic_vector(35 downto 0); 
+        WCNT: out  std_logic_vector(12 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic; 
+        AlmostFull: out  std_logic);
+end fifo_36x4k_oreg;
+
+architecture Structure of fifo_36x4k_oreg is
+
+    -- internal signal declarations
+    signal invout_2: std_logic;
+    signal invout_1: std_logic;
+    signal rden_i_inv: std_logic;
+    signal invout_0: std_logic;
+    signal r_nw: std_logic;
+    signal fcnt_en: std_logic;
+    signal empty_i: std_logic;
+    signal empty_d: std_logic;
+    signal full_i: std_logic;
+    signal full_d: std_logic;
+    signal wptr_0: std_logic;
+    signal wptr_1: std_logic;
+    signal wptr_2: std_logic;
+    signal wptr_3: std_logic;
+    signal wptr_4: std_logic;
+    signal wptr_5: std_logic;
+    signal wptr_6: std_logic;
+    signal wptr_7: std_logic;
+    signal wptr_8: std_logic;
+    signal wptr_9: std_logic;
+    signal wptr_10: std_logic;
+    signal wptr_11: std_logic;
+    signal wptr_12: std_logic;
+    signal rptr_12: std_logic;
+    signal rptr_11_ff: std_logic;
+    signal ifcount_0: std_logic;
+    signal ifcount_1: std_logic;
+    signal bdcnt_bctr_ci: std_logic;
+    signal ifcount_2: std_logic;
+    signal ifcount_3: std_logic;
+    signal co0: std_logic;
+    signal ifcount_4: std_logic;
+    signal ifcount_5: std_logic;
+    signal co1: std_logic;
+    signal ifcount_6: std_logic;
+    signal ifcount_7: std_logic;
+    signal co2: std_logic;
+    signal ifcount_8: std_logic;
+    signal ifcount_9: std_logic;
+    signal co3: std_logic;
+    signal ifcount_10: std_logic;
+    signal ifcount_11: std_logic;
+    signal co4: std_logic;
+    signal ifcount_12: std_logic;
+    signal co6: std_logic;
+    signal co5: std_logic;
+    signal cmp_ci: std_logic;
+    signal rden_i: std_logic;
+    signal co0_1: std_logic;
+    signal co1_1: std_logic;
+    signal co2_1: std_logic;
+    signal co3_1: std_logic;
+    signal co4_1: std_logic;
+    signal co5_1: std_logic;
+    signal cmp_le_1: std_logic;
+    signal cmp_le_1_c: std_logic;
+    signal cmp_ci_1: std_logic;
+    signal fcount_0: std_logic;
+    signal fcount_1: std_logic;
+    signal co0_2: std_logic;
+    signal fcount_2: std_logic;
+    signal fcount_3: std_logic;
+    signal co1_2: std_logic;
+    signal fcount_4: std_logic;
+    signal fcount_5: std_logic;
+    signal co2_2: std_logic;
+    signal fcount_6: std_logic;
+    signal fcount_7: std_logic;
+    signal co3_2: std_logic;
+    signal fcount_8: std_logic;
+    signal fcount_9: std_logic;
+    signal co4_2: std_logic;
+    signal fcount_10: std_logic;
+    signal fcount_11: std_logic;
+    signal co5_2: std_logic;
+    signal wren_i_inv: std_logic;
+    signal fcount_12: std_logic;
+    signal cmp_ge_d1: std_logic;
+    signal cmp_ge_d1_c: std_logic;
+    signal iwcount_0: std_logic;
+    signal iwcount_1: std_logic;
+    signal w_ctr_ci: std_logic;
+    signal iwcount_2: std_logic;
+    signal iwcount_3: std_logic;
+    signal co0_3: std_logic;
+    signal iwcount_4: std_logic;
+    signal iwcount_5: std_logic;
+    signal co1_3: std_logic;
+    signal iwcount_6: std_logic;
+    signal iwcount_7: std_logic;
+    signal co2_3: std_logic;
+    signal iwcount_8: std_logic;
+    signal iwcount_9: std_logic;
+    signal co3_3: std_logic;
+    signal iwcount_10: std_logic;
+    signal iwcount_11: std_logic;
+    signal co4_3: std_logic;
+    signal iwcount_12: std_logic;
+    signal co6_1: std_logic;
+    signal co5_3: std_logic;
+    signal wcount_12: std_logic;
+    signal ircount_0: std_logic;
+    signal ircount_1: std_logic;
+    signal r_ctr_ci: std_logic;
+    signal rcount_0: std_logic;
+    signal rcount_1: std_logic;
+    signal ircount_2: std_logic;
+    signal ircount_3: std_logic;
+    signal co0_4: std_logic;
+    signal rcount_2: std_logic;
+    signal rcount_3: std_logic;
+    signal ircount_4: std_logic;
+    signal ircount_5: std_logic;
+    signal co1_4: std_logic;
+    signal rcount_4: std_logic;
+    signal rcount_5: std_logic;
+    signal ircount_6: std_logic;
+    signal ircount_7: std_logic;
+    signal co2_4: std_logic;
+    signal rcount_6: std_logic;
+    signal rcount_7: std_logic;
+    signal ircount_8: std_logic;
+    signal ircount_9: std_logic;
+    signal co3_4: std_logic;
+    signal rcount_8: std_logic;
+    signal rcount_9: std_logic;
+    signal ircount_10: std_logic;
+    signal ircount_11: std_logic;
+    signal co4_4: std_logic;
+    signal rcount_10: std_logic;
+    signal rcount_11: std_logic;
+    signal ircount_12: std_logic;
+    signal co6_2: std_logic;
+    signal co5_4: std_logic;
+    signal rcount_12: std_logic;
+    signal mdout1_1_0: std_logic;
+    signal mdout1_0_0: std_logic;
+    signal mdout1_1_1: std_logic;
+    signal mdout1_0_1: std_logic;
+    signal mdout1_1_2: std_logic;
+    signal mdout1_0_2: std_logic;
+    signal mdout1_1_3: std_logic;
+    signal mdout1_0_3: std_logic;
+    signal mdout1_1_4: std_logic;
+    signal mdout1_0_4: std_logic;
+    signal mdout1_1_5: std_logic;
+    signal mdout1_0_5: std_logic;
+    signal mdout1_1_6: std_logic;
+    signal mdout1_0_6: std_logic;
+    signal mdout1_1_7: std_logic;
+    signal mdout1_0_7: std_logic;
+    signal mdout1_1_8: std_logic;
+    signal mdout1_0_8: std_logic;
+    signal mdout1_1_9: std_logic;
+    signal mdout1_0_9: std_logic;
+    signal mdout1_1_10: std_logic;
+    signal mdout1_0_10: std_logic;
+    signal mdout1_1_11: std_logic;
+    signal mdout1_0_11: std_logic;
+    signal mdout1_1_12: std_logic;
+    signal mdout1_0_12: std_logic;
+    signal mdout1_1_13: std_logic;
+    signal mdout1_0_13: std_logic;
+    signal mdout1_1_14: std_logic;
+    signal mdout1_0_14: std_logic;
+    signal mdout1_1_15: std_logic;
+    signal mdout1_0_15: std_logic;
+    signal mdout1_1_16: std_logic;
+    signal mdout1_0_16: std_logic;
+    signal mdout1_1_17: std_logic;
+    signal mdout1_0_17: std_logic;
+    signal mdout1_1_18: std_logic;
+    signal mdout1_0_18: std_logic;
+    signal mdout1_1_19: std_logic;
+    signal mdout1_0_19: std_logic;
+    signal mdout1_1_20: std_logic;
+    signal mdout1_0_20: std_logic;
+    signal mdout1_1_21: std_logic;
+    signal mdout1_0_21: std_logic;
+    signal mdout1_1_22: std_logic;
+    signal mdout1_0_22: std_logic;
+    signal mdout1_1_23: std_logic;
+    signal mdout1_0_23: std_logic;
+    signal mdout1_1_24: std_logic;
+    signal mdout1_0_24: std_logic;
+    signal mdout1_1_25: std_logic;
+    signal mdout1_0_25: std_logic;
+    signal mdout1_1_26: std_logic;
+    signal mdout1_0_26: std_logic;
+    signal mdout1_1_27: std_logic;
+    signal mdout1_0_27: std_logic;
+    signal mdout1_1_28: std_logic;
+    signal mdout1_0_28: std_logic;
+    signal mdout1_1_29: std_logic;
+    signal mdout1_0_29: std_logic;
+    signal mdout1_1_30: std_logic;
+    signal mdout1_0_30: std_logic;
+    signal mdout1_1_31: std_logic;
+    signal mdout1_0_31: std_logic;
+    signal mdout1_1_32: std_logic;
+    signal mdout1_0_32: std_logic;
+    signal mdout1_1_33: std_logic;
+    signal mdout1_0_33: std_logic;
+    signal mdout1_1_34: std_logic;
+    signal mdout1_0_34: std_logic;
+    signal rptr_11_ff2: std_logic;
+    signal mdout1_1_35: std_logic;
+    signal mdout1_0_35: std_logic;
+    signal wcnt_sub_0: std_logic;
+    signal rptr_0: std_logic;
+    signal cnt_con_inv: std_logic;
+    signal wcount_0: std_logic;
+    signal cnt_con: std_logic;
+    signal precin: std_logic;
+    signal wcnt_sub_1: std_logic;
+    signal wcnt_sub_2: std_logic;
+    signal rptr_2: std_logic;
+    signal rptr_1: std_logic;
+    signal wcount_2: std_logic;
+    signal wcount_1: std_logic;
+    signal co0_5: std_logic;
+    signal wcnt_sub_3: std_logic;
+    signal wcnt_sub_4: std_logic;
+    signal rptr_4: std_logic;
+    signal rptr_3: std_logic;
+    signal wcount_4: std_logic;
+    signal wcount_3: std_logic;
+    signal co1_5: std_logic;
+    signal wcnt_sub_5: std_logic;
+    signal wcnt_sub_6: std_logic;
+    signal rptr_6: std_logic;
+    signal rptr_5: std_logic;
+    signal wcount_6: std_logic;
+    signal wcount_5: std_logic;
+    signal co2_5: std_logic;
+    signal wcnt_sub_7: std_logic;
+    signal wcnt_sub_8: std_logic;
+    signal rptr_8: std_logic;
+    signal rptr_7: std_logic;
+    signal wcount_8: std_logic;
+    signal wcount_7: std_logic;
+    signal co3_5: std_logic;
+    signal wcnt_sub_9: std_logic;
+    signal wcnt_sub_10: std_logic;
+    signal rptr_10: std_logic;
+    signal rptr_9: std_logic;
+    signal wcount_10: std_logic;
+    signal wcount_9: std_logic;
+    signal co4_5: std_logic;
+    signal wcnt_sub_11: std_logic;
+    signal wcnt_sub_12: std_logic;
+    signal rptr_11: std_logic;
+    signal wcnt_sub_msb: std_logic;
+    signal wcount_11: std_logic;
+    signal co5_5: std_logic;
+    signal co6_3d: std_logic;
+    signal co6_3: std_logic;
+    signal wren_i: std_logic;
+    signal cmp_ci_2: std_logic;
+    signal wcnt_reg_0: std_logic;
+    signal wcnt_reg_1: std_logic;
+    signal co0_6: std_logic;
+    signal wcnt_reg_2: std_logic;
+    signal wcnt_reg_3: std_logic;
+    signal co1_6: std_logic;
+    signal wcnt_reg_4: std_logic;
+    signal wcnt_reg_5: std_logic;
+    signal co2_6: std_logic;
+    signal wcnt_reg_6: std_logic;
+    signal wcnt_reg_7: std_logic;
+    signal co3_6: std_logic;
+    signal wcnt_reg_8: std_logic;
+    signal wcnt_reg_9: std_logic;
+    signal co4_6: std_logic;
+    signal wcnt_reg_10: std_logic;
+    signal wcnt_reg_11: std_logic;
+    signal co5_6: std_logic;
+    signal wcnt_reg_12: std_logic;
+    signal af_set: std_logic;
+    signal scuba_vhi: std_logic;
+    signal scuba_vlo: std_logic;
+    signal af_set_c: std_logic;
+
+    attribute MEM_LPC_FILE : string; 
+    attribute MEM_INIT_FILE : string; 
+    attribute GSR : string; 
+    attribute MEM_LPC_FILE of pdp_ram_0_0_7 : label is "fifo_36x4k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_0_7 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_0_1_6 : label is "fifo_36x4k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_1_6 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_0_2_5 : label is "fifo_36x4k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_2_5 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_0_3_4 : label is "fifo_36x4k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_3_4 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_1_0_3 : label is "fifo_36x4k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_1_0_3 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_1_1_2 : label is "fifo_36x4k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_1_1_2 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_1_2_1 : label is "fifo_36x4k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_1_2_1 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_1_3_0 : label is "fifo_36x4k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_1_3_0 : label is "";
+    attribute GSR of FF_82 : label is "ENABLED";
+    attribute GSR of FF_81 : label is "ENABLED";
+    attribute GSR of FF_80 : label is "ENABLED";
+    attribute GSR of FF_79 : label is "ENABLED";
+    attribute GSR of FF_78 : label is "ENABLED";
+    attribute GSR of FF_77 : label is "ENABLED";
+    attribute GSR of FF_76 : label is "ENABLED";
+    attribute GSR of FF_75 : label is "ENABLED";
+    attribute GSR of FF_74 : label is "ENABLED";
+    attribute GSR of FF_73 : label is "ENABLED";
+    attribute GSR of FF_72 : label is "ENABLED";
+    attribute GSR of FF_71 : label is "ENABLED";
+    attribute GSR of FF_70 : label is "ENABLED";
+    attribute GSR of FF_69 : label is "ENABLED";
+    attribute GSR of FF_68 : label is "ENABLED";
+    attribute GSR of FF_67 : label is "ENABLED";
+    attribute GSR of FF_66 : label is "ENABLED";
+    attribute GSR of FF_65 : label is "ENABLED";
+    attribute GSR of FF_64 : label is "ENABLED";
+    attribute GSR of FF_63 : label is "ENABLED";
+    attribute GSR of FF_62 : label is "ENABLED";
+    attribute GSR of FF_61 : label is "ENABLED";
+    attribute GSR of FF_60 : label is "ENABLED";
+    attribute GSR of FF_59 : label is "ENABLED";
+    attribute GSR of FF_58 : label is "ENABLED";
+    attribute GSR of FF_57 : label is "ENABLED";
+    attribute GSR of FF_56 : label is "ENABLED";
+    attribute GSR of FF_55 : label is "ENABLED";
+    attribute GSR of FF_54 : label is "ENABLED";
+    attribute GSR of FF_53 : label is "ENABLED";
+    attribute GSR of FF_52 : label is "ENABLED";
+    attribute GSR of FF_51 : label is "ENABLED";
+    attribute GSR of FF_50 : label is "ENABLED";
+    attribute GSR of FF_49 : label is "ENABLED";
+    attribute GSR of FF_48 : label is "ENABLED";
+    attribute GSR of FF_47 : label is "ENABLED";
+    attribute GSR of FF_46 : label is "ENABLED";
+    attribute GSR of FF_45 : label is "ENABLED";
+    attribute GSR of FF_44 : label is "ENABLED";
+    attribute GSR of FF_43 : label is "ENABLED";
+    attribute GSR of FF_42 : label is "ENABLED";
+    attribute GSR of FF_41 : label is "ENABLED";
+    attribute GSR of FF_40 : label is "ENABLED";
+    attribute GSR of FF_39 : label is "ENABLED";
+    attribute GSR of FF_38 : label is "ENABLED";
+    attribute GSR of FF_37 : label is "ENABLED";
+    attribute GSR of FF_36 : label is "ENABLED";
+    attribute GSR of FF_35 : label is "ENABLED";
+    attribute GSR of FF_34 : label is "ENABLED";
+    attribute GSR of FF_33 : label is "ENABLED";
+    attribute GSR of FF_32 : label is "ENABLED";
+    attribute GSR of FF_31 : label is "ENABLED";
+    attribute GSR of FF_30 : label is "ENABLED";
+    attribute GSR of FF_29 : label is "ENABLED";
+    attribute GSR of FF_28 : label is "ENABLED";
+    attribute GSR of FF_27 : label is "ENABLED";
+    attribute GSR of FF_26 : label is "ENABLED";
+    attribute GSR of FF_25 : label is "ENABLED";
+    attribute GSR of FF_24 : label is "ENABLED";
+    attribute GSR of FF_23 : label is "ENABLED";
+    attribute GSR of FF_22 : label is "ENABLED";
+    attribute GSR of FF_21 : label is "ENABLED";
+    attribute GSR of FF_20 : label is "ENABLED";
+    attribute GSR of FF_19 : label is "ENABLED";
+    attribute GSR of FF_18 : label is "ENABLED";
+    attribute GSR of FF_17 : label is "ENABLED";
+    attribute GSR of FF_16 : label is "ENABLED";
+    attribute GSR of FF_15 : label is "ENABLED";
+    attribute GSR of FF_14 : label is "ENABLED";
+    attribute GSR of FF_13 : label is "ENABLED";
+    attribute GSR of FF_12 : label is "ENABLED";
+    attribute GSR of FF_11 : label is "ENABLED";
+    attribute GSR of FF_10 : label is "ENABLED";
+    attribute GSR of FF_9 : label is "ENABLED";
+    attribute GSR of FF_8 : label is "ENABLED";
+    attribute GSR of FF_7 : label is "ENABLED";
+    attribute GSR of FF_6 : label is "ENABLED";
+    attribute GSR of FF_5 : label is "ENABLED";
+    attribute GSR of FF_4 : label is "ENABLED";
+    attribute GSR of FF_3 : label is "ENABLED";
+    attribute GSR of FF_2 : label is "ENABLED";
+    attribute GSR of FF_1 : label is "ENABLED";
+    attribute GSR of FF_0 : label is "ENABLED";
+    attribute syn_keep : boolean;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    AND2_t5: AND2
+        port map (A=>WrEn, B=>invout_2, Z=>wren_i);
+
+    INV_5: INV
+        port map (A=>full_i, Z=>invout_2);
+
+    AND2_t4: AND2
+        port map (A=>RdEn, B=>invout_1, Z=>rden_i);
+
+    INV_4: INV
+        port map (A=>empty_i, Z=>invout_1);
+
+    AND2_t3: AND2
+        port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
+
+    XOR2_t2: XOR2
+        port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
+
+    INV_3: INV
+        port map (A=>rden_i, Z=>rden_i_inv);
+
+    INV_2: INV
+        port map (A=>wren_i, Z=>wren_i_inv);
+
+    LUT4_1: ROM16X1A
+        generic map (initval=> X"3232")
+        port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, 
+            AD0=>empty_i, DO0=>empty_d);
+
+    LUT4_0: ROM16X1A
+        generic map (initval=> X"3232")
+        port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, 
+            AD0=>full_i, DO0=>full_d);
+
+    AND2_t1: AND2
+        port map (A=>rden_i, B=>invout_0, Z=>r_nw);
+
+    INV_1: INV
+        port map (A=>wren_i, Z=>invout_0);
+
+    XOR2_t0: XOR2
+        port map (A=>wcount_12, B=>rptr_12, Z=>wcnt_sub_msb);
+
+    INV_0: INV
+        port map (A=>cnt_con, Z=>cnt_con_inv);
+
+    pdp_ram_0_0_7: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), 
+            DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), 
+            DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, 
+            ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, 
+            ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, 
+            ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, 
+            CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, 
+            CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>wptr_11, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>rptr_11, RSTB=>Reset, 
+            DOA17=>open, DOA16=>open, DOA15=>open, DOA14=>open, 
+            DOA13=>open, DOA12=>open, DOA11=>open, DOA10=>open, 
+            DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open, 
+            DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open, 
+            DOB17=>open, DOB16=>open, DOB15=>open, DOB14=>open, 
+            DOB13=>open, DOB12=>open, DOB11=>open, DOB10=>open, 
+            DOB9=>open, DOB8=>mdout1_0_8, DOB7=>mdout1_0_7, 
+            DOB6=>mdout1_0_6, DOB5=>mdout1_0_5, DOB4=>mdout1_0_4, 
+            DOB3=>mdout1_0_3, DOB2=>mdout1_0_2, DOB1=>mdout1_0_1, 
+            DOB0=>mdout1_0_0);
+
+    pdp_ram_0_1_6: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), 
+            DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), 
+            DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>wptr_11, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>rptr_11, RSTB=>Reset, 
+            DOA17=>open, DOA16=>open, DOA15=>open, DOA14=>open, 
+            DOA13=>open, DOA12=>open, DOA11=>open, DOA10=>open, 
+            DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open, 
+            DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open, 
+            DOB17=>open, DOB16=>open, DOB15=>open, DOB14=>open, 
+            DOB13=>open, DOB12=>open, DOB11=>open, DOB10=>open, 
+            DOB9=>open, DOB8=>mdout1_0_17, DOB7=>mdout1_0_16, 
+            DOB6=>mdout1_0_15, DOB5=>mdout1_0_14, DOB4=>mdout1_0_13, 
+            DOB3=>mdout1_0_12, DOB2=>mdout1_0_11, DOB1=>mdout1_0_10, 
+            DOB0=>mdout1_0_9);
+
+    pdp_ram_0_2_5: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), 
+            DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), 
+            DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>wptr_11, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>rptr_11, RSTB=>Reset, 
+            DOA17=>open, DOA16=>open, DOA15=>open, DOA14=>open, 
+            DOA13=>open, DOA12=>open, DOA11=>open, DOA10=>open, 
+            DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open, 
+            DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open, 
+            DOB17=>open, DOB16=>open, DOB15=>open, DOB14=>open, 
+            DOB13=>open, DOB12=>open, DOB11=>open, DOB10=>open, 
+            DOB9=>open, DOB8=>mdout1_0_26, DOB7=>mdout1_0_25, 
+            DOB6=>mdout1_0_24, DOB5=>mdout1_0_23, DOB4=>mdout1_0_22, 
+            DOB3=>mdout1_0_21, DOB2=>mdout1_0_20, DOB1=>mdout1_0_19, 
+            DOB0=>mdout1_0_18);
+
+    pdp_ram_0_3_4: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), 
+            DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), 
+            DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>wptr_11, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>rptr_11, RSTB=>Reset, 
+            DOA17=>open, DOA16=>open, DOA15=>open, DOA14=>open, 
+            DOA13=>open, DOA12=>open, DOA11=>open, DOA10=>open, 
+            DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open, 
+            DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open, 
+            DOB17=>open, DOB16=>open, DOB15=>open, DOB14=>open, 
+            DOB13=>open, DOB12=>open, DOB11=>open, DOB10=>open, 
+            DOB9=>open, DOB8=>mdout1_0_35, DOB7=>mdout1_0_34, 
+            DOB6=>mdout1_0_33, DOB5=>mdout1_0_32, DOB4=>mdout1_0_31, 
+            DOB3=>mdout1_0_30, DOB2=>mdout1_0_29, DOB1=>mdout1_0_28, 
+            DOB0=>mdout1_0_27);
+
+    pdp_ram_1_0_3: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), 
+            DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), 
+            DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, 
+            ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, 
+            ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, 
+            ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, 
+            CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, 
+            CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>wptr_11, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>rptr_11, RSTB=>Reset, 
+            DOA17=>open, DOA16=>open, DOA15=>open, DOA14=>open, 
+            DOA13=>open, DOA12=>open, DOA11=>open, DOA10=>open, 
+            DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open, 
+            DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open, 
+            DOB17=>open, DOB16=>open, DOB15=>open, DOB14=>open, 
+            DOB13=>open, DOB12=>open, DOB11=>open, DOB10=>open, 
+            DOB9=>open, DOB8=>mdout1_1_8, DOB7=>mdout1_1_7, 
+            DOB6=>mdout1_1_6, DOB5=>mdout1_1_5, DOB4=>mdout1_1_4, 
+            DOB3=>mdout1_1_3, DOB2=>mdout1_1_2, DOB1=>mdout1_1_1, 
+            DOB0=>mdout1_1_0);
+
+    pdp_ram_1_1_2: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), 
+            DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), 
+            DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>wptr_11, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>rptr_11, RSTB=>Reset, 
+            DOA17=>open, DOA16=>open, DOA15=>open, DOA14=>open, 
+            DOA13=>open, DOA12=>open, DOA11=>open, DOA10=>open, 
+            DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open, 
+            DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open, 
+            DOB17=>open, DOB16=>open, DOB15=>open, DOB14=>open, 
+            DOB13=>open, DOB12=>open, DOB11=>open, DOB10=>open, 
+            DOB9=>open, DOB8=>mdout1_1_17, DOB7=>mdout1_1_16, 
+            DOB6=>mdout1_1_15, DOB5=>mdout1_1_14, DOB4=>mdout1_1_13, 
+            DOB3=>mdout1_1_12, DOB2=>mdout1_1_11, DOB1=>mdout1_1_10, 
+            DOB0=>mdout1_1_9);
+
+    pdp_ram_1_2_1: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), 
+            DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), 
+            DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>wptr_11, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>rptr_11, RSTB=>Reset, 
+            DOA17=>open, DOA16=>open, DOA15=>open, DOA14=>open, 
+            DOA13=>open, DOA12=>open, DOA11=>open, DOA10=>open, 
+            DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open, 
+            DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open, 
+            DOB17=>open, DOB16=>open, DOB15=>open, DOB14=>open, 
+            DOB13=>open, DOB12=>open, DOB11=>open, DOB10=>open, 
+            DOB9=>open, DOB8=>mdout1_1_26, DOB7=>mdout1_1_25, 
+            DOB6=>mdout1_1_24, DOB5=>mdout1_1_23, DOB4=>mdout1_1_22, 
+            DOB3=>mdout1_1_21, DOB2=>mdout1_1_20, DOB1=>mdout1_1_19, 
+            DOB0=>mdout1_1_18);
+
+    pdp_ram_1_3_0: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), 
+            DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), 
+            DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA0=>wptr_11, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>rptr_11, RSTB=>Reset, 
+            DOA17=>open, DOA16=>open, DOA15=>open, DOA14=>open, 
+            DOA13=>open, DOA12=>open, DOA11=>open, DOA10=>open, 
+            DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open, 
+            DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open, 
+            DOB17=>open, DOB16=>open, DOB15=>open, DOB14=>open, 
+            DOB13=>open, DOB12=>open, DOB11=>open, DOB10=>open, 
+            DOB9=>open, DOB8=>mdout1_1_35, DOB7=>mdout1_1_34, 
+            DOB6=>mdout1_1_33, DOB5=>mdout1_1_32, DOB4=>mdout1_1_31, 
+            DOB3=>mdout1_1_30, DOB2=>mdout1_1_29, DOB1=>mdout1_1_28, 
+            DOB0=>mdout1_1_27);
+
+    FF_82: FD1P3DX
+        port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_0);
+
+    FF_81: FD1P3DX
+        port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_1);
+
+    FF_80: FD1P3DX
+        port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_2);
+
+    FF_79: FD1P3DX
+        port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_3);
+
+    FF_78: FD1P3DX
+        port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_4);
+
+    FF_77: FD1P3DX
+        port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_5);
+
+    FF_76: FD1P3DX
+        port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_6);
+
+    FF_75: FD1P3DX
+        port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_7);
+
+    FF_74: FD1P3DX
+        port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_8);
+
+    FF_73: FD1P3DX
+        port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_9);
+
+    FF_72: FD1P3DX
+        port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_10);
+
+    FF_71: FD1P3DX
+        port map (D=>ifcount_11, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_11);
+
+    FF_70: FD1P3DX
+        port map (D=>ifcount_12, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_12);
+
+    FF_69: FD1S3BX
+        port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
+
+    FF_68: FD1S3DX
+        port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
+
+    FF_67: FD1P3BX
+        port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset, 
+            Q=>wcount_0);
+
+    FF_66: FD1P3DX
+        port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_1);
+
+    FF_65: FD1P3DX
+        port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_2);
+
+    FF_64: FD1P3DX
+        port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_3);
+
+    FF_63: FD1P3DX
+        port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_4);
+
+    FF_62: FD1P3DX
+        port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_5);
+
+    FF_61: FD1P3DX
+        port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_6);
+
+    FF_60: FD1P3DX
+        port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_7);
+
+    FF_59: FD1P3DX
+        port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_8);
+
+    FF_58: FD1P3DX
+        port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_9);
+
+    FF_57: FD1P3DX
+        port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_10);
+
+    FF_56: FD1P3DX
+        port map (D=>iwcount_11, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_11);
+
+    FF_55: FD1P3DX
+        port map (D=>iwcount_12, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_12);
+
+    FF_54: FD1P3BX
+        port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset, 
+            Q=>rcount_0);
+
+    FF_53: FD1P3DX
+        port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_1);
+
+    FF_52: FD1P3DX
+        port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_2);
+
+    FF_51: FD1P3DX
+        port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_3);
+
+    FF_50: FD1P3DX
+        port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_4);
+
+    FF_49: FD1P3DX
+        port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_5);
+
+    FF_48: FD1P3DX
+        port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_6);
+
+    FF_47: FD1P3DX
+        port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_7);
+
+    FF_46: FD1P3DX
+        port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_8);
+
+    FF_45: FD1P3DX
+        port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_9);
+
+    FF_44: FD1P3DX
+        port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_10);
+
+    FF_43: FD1P3DX
+        port map (D=>ircount_11, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_11);
+
+    FF_42: FD1P3DX
+        port map (D=>ircount_12, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_12);
+
+    FF_41: FD1P3DX
+        port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_0);
+
+    FF_40: FD1P3DX
+        port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_1);
+
+    FF_39: FD1P3DX
+        port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_2);
+
+    FF_38: FD1P3DX
+        port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_3);
+
+    FF_37: FD1P3DX
+        port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_4);
+
+    FF_36: FD1P3DX
+        port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_5);
+
+    FF_35: FD1P3DX
+        port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_6);
+
+    FF_34: FD1P3DX
+        port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_7);
+
+    FF_33: FD1P3DX
+        port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_8);
+
+    FF_32: FD1P3DX
+        port map (D=>wcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_9);
+
+    FF_31: FD1P3DX
+        port map (D=>wcount_10, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_10);
+
+    FF_30: FD1P3DX
+        port map (D=>wcount_11, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_11);
+
+    FF_29: FD1P3DX
+        port map (D=>wcount_12, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_12);
+
+    FF_28: FD1P3DX
+        port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_0);
+
+    FF_27: FD1P3DX
+        port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_1);
+
+    FF_26: FD1P3DX
+        port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_2);
+
+    FF_25: FD1P3DX
+        port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_3);
+
+    FF_24: FD1P3DX
+        port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_4);
+
+    FF_23: FD1P3DX
+        port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_5);
+
+    FF_22: FD1P3DX
+        port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_6);
+
+    FF_21: FD1P3DX
+        port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_7);
+
+    FF_20: FD1P3DX
+        port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_8);
+
+    FF_19: FD1P3DX
+        port map (D=>rcount_9, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_9);
+
+    FF_18: FD1P3DX
+        port map (D=>rcount_10, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_10);
+
+    FF_17: FD1P3DX
+        port map (D=>rcount_11, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_11);
+
+    FF_16: FD1P3DX
+        port map (D=>rcount_12, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_12);
+
+    FF_15: FD1P3DX
+        port map (D=>rptr_11, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, 
+            Q=>rptr_11_ff);
+
+    FF_14: FD1P3DX
+        port map (D=>rptr_11_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, 
+            Q=>rptr_11_ff2);
+
+    FF_13: FD1S3DX
+        port map (D=>wcnt_sub_0, CK=>Clock, CD=>Reset, Q=>wcnt_reg_0);
+
+    FF_12: FD1S3DX
+        port map (D=>wcnt_sub_1, CK=>Clock, CD=>Reset, Q=>wcnt_reg_1);
+
+    FF_11: FD1S3DX
+        port map (D=>wcnt_sub_2, CK=>Clock, CD=>Reset, Q=>wcnt_reg_2);
+
+    FF_10: FD1S3DX
+        port map (D=>wcnt_sub_3, CK=>Clock, CD=>Reset, Q=>wcnt_reg_3);
+
+    FF_9: FD1S3DX
+        port map (D=>wcnt_sub_4, CK=>Clock, CD=>Reset, Q=>wcnt_reg_4);
+
+    FF_8: FD1S3DX
+        port map (D=>wcnt_sub_5, CK=>Clock, CD=>Reset, Q=>wcnt_reg_5);
+
+    FF_7: FD1S3DX
+        port map (D=>wcnt_sub_6, CK=>Clock, CD=>Reset, Q=>wcnt_reg_6);
+
+    FF_6: FD1S3DX
+        port map (D=>wcnt_sub_7, CK=>Clock, CD=>Reset, Q=>wcnt_reg_7);
+
+    FF_5: FD1S3DX
+        port map (D=>wcnt_sub_8, CK=>Clock, CD=>Reset, Q=>wcnt_reg_8);
+
+    FF_4: FD1S3DX
+        port map (D=>wcnt_sub_9, CK=>Clock, CD=>Reset, Q=>wcnt_reg_9);
+
+    FF_3: FD1S3DX
+        port map (D=>wcnt_sub_10, CK=>Clock, CD=>Reset, Q=>wcnt_reg_10);
+
+    FF_2: FD1S3DX
+        port map (D=>wcnt_sub_11, CK=>Clock, CD=>Reset, Q=>wcnt_reg_11);
+
+    FF_1: FD1S3DX
+        port map (D=>wcnt_sub_12, CK=>Clock, CD=>Reset, Q=>wcnt_reg_12);
+
+    FF_0: FD1S3DX
+        port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull);
+
+    bdcnt_bctr_cia: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>'X', S0=>open, S1=>open, COUT=>bdcnt_bctr_ci);
+
+    bdcnt_bctr_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_0, A1=>fcount_1, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>bdcnt_bctr_ci, S0=>ifcount_0, S1=>ifcount_1, COUT=>co0);
+
+    bdcnt_bctr_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co0, S0=>ifcount_2, S1=>ifcount_3, COUT=>co1);
+
+    bdcnt_bctr_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_4, A1=>fcount_5, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co1, S0=>ifcount_4, S1=>ifcount_5, COUT=>co2);
+
+    bdcnt_bctr_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_6, A1=>fcount_7, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co2, S0=>ifcount_6, S1=>ifcount_7, COUT=>co3);
+
+    bdcnt_bctr_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_8, A1=>fcount_9, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co3, S0=>ifcount_8, S1=>ifcount_9, COUT=>co4);
+
+    bdcnt_bctr_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_10, A1=>fcount_11, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co4, S0=>ifcount_10, S1=>ifcount_11, COUT=>co5);
+
+    bdcnt_bctr_6: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_12, A1=>scuba_vlo, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co5, S0=>ifcount_12, S1=>open, COUT=>co6);
+
+    e_cmp_ci_a: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci);
+
+    e_cmp_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>rden_i, A1=>scuba_vlo, B0=>fcount_0, B1=>fcount_1, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>cmp_ci, S0=>open, S1=>open, COUT=>co0_1);
+
+    e_cmp_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_2, 
+            B1=>fcount_3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co0_1, S0=>open, S1=>open, COUT=>co1_1);
+
+    e_cmp_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_4, 
+            B1=>fcount_5, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co1_1, S0=>open, S1=>open, COUT=>co2_1);
+
+    e_cmp_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_6, 
+            B1=>fcount_7, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co2_1, S0=>open, S1=>open, COUT=>co3_1);
+
+    e_cmp_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_8, 
+            B1=>fcount_9, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co3_1, S0=>open, S1=>open, COUT=>co4_1);
+
+    e_cmp_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_10, 
+            B1=>fcount_11, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co4_1, S0=>open, S1=>open, COUT=>co5_1);
+
+    e_cmp_6: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_12, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co5_1, S0=>open, S1=>open, 
+            COUT=>cmp_le_1_c);
+
+    a0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>cmp_le_1_c, S0=>cmp_le_1, S1=>open, 
+            COUT=>open);
+
+    g_cmp_ci_a: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_1);
+
+    g_cmp_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>cmp_ci_1, S0=>open, S1=>open, COUT=>co0_2);
+
+    g_cmp_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co0_2, S0=>open, S1=>open, COUT=>co1_2);
+
+    g_cmp_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co1_2, S0=>open, S1=>open, COUT=>co2_2);
+
+    g_cmp_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co2_2, S0=>open, S1=>open, COUT=>co3_2);
+
+    g_cmp_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co3_2, S0=>open, S1=>open, COUT=>co4_2);
+
+    g_cmp_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_10, A1=>fcount_11, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co4_2, S0=>open, S1=>open, COUT=>co5_2);
+
+    g_cmp_6: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_12, A1=>scuba_vlo, B0=>wren_i_inv, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co5_2, S0=>open, S1=>open, 
+            COUT=>cmp_ge_d1_c);
+
+    a1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>cmp_ge_d1_c, S0=>cmp_ge_d1, S1=>open, 
+            COUT=>open);
+
+    w_ctr_cia: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>w_ctr_ci);
+
+    w_ctr_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>w_ctr_ci, S0=>iwcount_0, S1=>iwcount_1, 
+            COUT=>co0_3);
+
+    w_ctr_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_2, A1=>wcount_3, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co0_3, S0=>iwcount_2, S1=>iwcount_3, 
+            COUT=>co1_3);
+
+    w_ctr_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_4, A1=>wcount_5, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co1_3, S0=>iwcount_4, S1=>iwcount_5, 
+            COUT=>co2_3);
+
+    w_ctr_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_6, A1=>wcount_7, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co2_3, S0=>iwcount_6, S1=>iwcount_7, 
+            COUT=>co3_3);
+
+    w_ctr_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_8, A1=>wcount_9, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co3_3, S0=>iwcount_8, S1=>iwcount_9, 
+            COUT=>co4_3);
+
+    w_ctr_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_10, A1=>wcount_11, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co4_3, S0=>iwcount_10, S1=>iwcount_11, 
+            COUT=>co5_3);
+
+    w_ctr_6: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_12, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co5_3, S0=>iwcount_12, S1=>open, 
+            COUT=>co6_1);
+
+    r_ctr_cia: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>r_ctr_ci);
+
+    r_ctr_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>r_ctr_ci, S0=>ircount_0, S1=>ircount_1, 
+            COUT=>co0_4);
+
+    r_ctr_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_2, A1=>rcount_3, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co0_4, S0=>ircount_2, S1=>ircount_3, 
+            COUT=>co1_4);
+
+    r_ctr_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_4, A1=>rcount_5, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co1_4, S0=>ircount_4, S1=>ircount_5, 
+            COUT=>co2_4);
+
+    r_ctr_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_6, A1=>rcount_7, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co2_4, S0=>ircount_6, S1=>ircount_7, 
+            COUT=>co3_4);
+
+    r_ctr_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_8, A1=>rcount_9, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co3_4, S0=>ircount_8, S1=>ircount_9, 
+            COUT=>co4_4);
+
+    r_ctr_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_10, A1=>rcount_11, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co4_4, S0=>ircount_10, S1=>ircount_11, 
+            COUT=>co5_4);
+
+    r_ctr_6: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_12, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co5_4, S0=>ircount_12, S1=>open, 
+            COUT=>co6_2);
+
+    mux_35: MUX21
+        port map (D0=>mdout1_0_0, D1=>mdout1_1_0, SD=>rptr_11_ff2, 
+            Z=>Q(0));
+
+    mux_34: MUX21
+        port map (D0=>mdout1_0_1, D1=>mdout1_1_1, SD=>rptr_11_ff2, 
+            Z=>Q(1));
+
+    mux_33: MUX21
+        port map (D0=>mdout1_0_2, D1=>mdout1_1_2, SD=>rptr_11_ff2, 
+            Z=>Q(2));
+
+    mux_32: MUX21
+        port map (D0=>mdout1_0_3, D1=>mdout1_1_3, SD=>rptr_11_ff2, 
+            Z=>Q(3));
+
+    mux_31: MUX21
+        port map (D0=>mdout1_0_4, D1=>mdout1_1_4, SD=>rptr_11_ff2, 
+            Z=>Q(4));
+
+    mux_30: MUX21
+        port map (D0=>mdout1_0_5, D1=>mdout1_1_5, SD=>rptr_11_ff2, 
+            Z=>Q(5));
+
+    mux_29: MUX21
+        port map (D0=>mdout1_0_6, D1=>mdout1_1_6, SD=>rptr_11_ff2, 
+            Z=>Q(6));
+
+    mux_28: MUX21
+        port map (D0=>mdout1_0_7, D1=>mdout1_1_7, SD=>rptr_11_ff2, 
+            Z=>Q(7));
+
+    mux_27: MUX21
+        port map (D0=>mdout1_0_8, D1=>mdout1_1_8, SD=>rptr_11_ff2, 
+            Z=>Q(8));
+
+    mux_26: MUX21
+        port map (D0=>mdout1_0_9, D1=>mdout1_1_9, SD=>rptr_11_ff2, 
+            Z=>Q(9));
+
+    mux_25: MUX21
+        port map (D0=>mdout1_0_10, D1=>mdout1_1_10, SD=>rptr_11_ff2, 
+            Z=>Q(10));
+
+    mux_24: MUX21
+        port map (D0=>mdout1_0_11, D1=>mdout1_1_11, SD=>rptr_11_ff2, 
+            Z=>Q(11));
+
+    mux_23: MUX21
+        port map (D0=>mdout1_0_12, D1=>mdout1_1_12, SD=>rptr_11_ff2, 
+            Z=>Q(12));
+
+    mux_22: MUX21
+        port map (D0=>mdout1_0_13, D1=>mdout1_1_13, SD=>rptr_11_ff2, 
+            Z=>Q(13));
+
+    mux_21: MUX21
+        port map (D0=>mdout1_0_14, D1=>mdout1_1_14, SD=>rptr_11_ff2, 
+            Z=>Q(14));
+
+    mux_20: MUX21
+        port map (D0=>mdout1_0_15, D1=>mdout1_1_15, SD=>rptr_11_ff2, 
+            Z=>Q(15));
+
+    mux_19: MUX21
+        port map (D0=>mdout1_0_16, D1=>mdout1_1_16, SD=>rptr_11_ff2, 
+            Z=>Q(16));
+
+    mux_18: MUX21
+        port map (D0=>mdout1_0_17, D1=>mdout1_1_17, SD=>rptr_11_ff2, 
+            Z=>Q(17));
+
+    mux_17: MUX21
+        port map (D0=>mdout1_0_18, D1=>mdout1_1_18, SD=>rptr_11_ff2, 
+            Z=>Q(18));
+
+    mux_16: MUX21
+        port map (D0=>mdout1_0_19, D1=>mdout1_1_19, SD=>rptr_11_ff2, 
+            Z=>Q(19));
+
+    mux_15: MUX21
+        port map (D0=>mdout1_0_20, D1=>mdout1_1_20, SD=>rptr_11_ff2, 
+            Z=>Q(20));
+
+    mux_14: MUX21
+        port map (D0=>mdout1_0_21, D1=>mdout1_1_21, SD=>rptr_11_ff2, 
+            Z=>Q(21));
+
+    mux_13: MUX21
+        port map (D0=>mdout1_0_22, D1=>mdout1_1_22, SD=>rptr_11_ff2, 
+            Z=>Q(22));
+
+    mux_12: MUX21
+        port map (D0=>mdout1_0_23, D1=>mdout1_1_23, SD=>rptr_11_ff2, 
+            Z=>Q(23));
+
+    mux_11: MUX21
+        port map (D0=>mdout1_0_24, D1=>mdout1_1_24, SD=>rptr_11_ff2, 
+            Z=>Q(24));
+
+    mux_10: MUX21
+        port map (D0=>mdout1_0_25, D1=>mdout1_1_25, SD=>rptr_11_ff2, 
+            Z=>Q(25));
+
+    mux_9: MUX21
+        port map (D0=>mdout1_0_26, D1=>mdout1_1_26, SD=>rptr_11_ff2, 
+            Z=>Q(26));
+
+    mux_8: MUX21
+        port map (D0=>mdout1_0_27, D1=>mdout1_1_27, SD=>rptr_11_ff2, 
+            Z=>Q(27));
+
+    mux_7: MUX21
+        port map (D0=>mdout1_0_28, D1=>mdout1_1_28, SD=>rptr_11_ff2, 
+            Z=>Q(28));
+
+    mux_6: MUX21
+        port map (D0=>mdout1_0_29, D1=>mdout1_1_29, SD=>rptr_11_ff2, 
+            Z=>Q(29));
+
+    mux_5: MUX21
+        port map (D0=>mdout1_0_30, D1=>mdout1_1_30, SD=>rptr_11_ff2, 
+            Z=>Q(30));
+
+    mux_4: MUX21
+        port map (D0=>mdout1_0_31, D1=>mdout1_1_31, SD=>rptr_11_ff2, 
+            Z=>Q(31));
+
+    mux_3: MUX21
+        port map (D0=>mdout1_0_32, D1=>mdout1_1_32, SD=>rptr_11_ff2, 
+            Z=>Q(32));
+
+    mux_2: MUX21
+        port map (D0=>mdout1_0_33, D1=>mdout1_1_33, SD=>rptr_11_ff2, 
+            Z=>Q(33));
+
+    mux_1: MUX21
+        port map (D0=>mdout1_0_34, D1=>mdout1_1_34, SD=>rptr_11_ff2, 
+            Z=>Q(34));
+
+    mux_0: MUX21
+        port map (D0=>mdout1_0_35, D1=>mdout1_1_35, SD=>rptr_11_ff2, 
+            Z=>Q(35));
+
+    precin_inst389: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"0000", 
+        INIT0=> X"0000")
+        port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>precin);
+
+    wcnt_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>cnt_con, A1=>wcount_0, B0=>cnt_con_inv, B1=>rptr_0, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>precin, S0=>open, S1=>wcnt_sub_0, COUT=>co0_5);
+
+    wcnt_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_1, A1=>wcount_2, B0=>rptr_1, B1=>rptr_2, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co0_5, S0=>wcnt_sub_1, S1=>wcnt_sub_2, COUT=>co1_5);
+
+    wcnt_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_3, A1=>wcount_4, B0=>rptr_3, B1=>rptr_4, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co1_5, S0=>wcnt_sub_3, S1=>wcnt_sub_4, COUT=>co2_5);
+
+    wcnt_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_5, A1=>wcount_6, B0=>rptr_5, B1=>rptr_6, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co2_5, S0=>wcnt_sub_5, S1=>wcnt_sub_6, COUT=>co3_5);
+
+    wcnt_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_7, A1=>wcount_8, B0=>rptr_7, B1=>rptr_8, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co3_5, S0=>wcnt_sub_7, S1=>wcnt_sub_8, COUT=>co4_5);
+
+    wcnt_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_9, A1=>wcount_10, B0=>rptr_9, B1=>rptr_10, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co4_5, S0=>wcnt_sub_9, S1=>wcnt_sub_10, COUT=>co5_5);
+
+    wcnt_6: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_11, A1=>wcnt_sub_msb, B0=>rptr_11, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co5_5, S0=>wcnt_sub_11, S1=>wcnt_sub_12, 
+            COUT=>co6_3);
+
+    wcntd: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co6_3, S0=>co6_3d, S1=>open, COUT=>open);
+
+    af_set_cmp_ci_a: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_2);
+
+    af_set_cmp_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0), 
+            B1=>AmFullThresh(1), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>cmp_ci_2, S0=>open, 
+            S1=>open, COUT=>co0_6);
+
+    af_set_cmp_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2), 
+            B1=>AmFullThresh(3), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co0_6, S0=>open, S1=>open, 
+            COUT=>co1_6);
+
+    af_set_cmp_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4), 
+            B1=>AmFullThresh(5), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co1_6, S0=>open, S1=>open, 
+            COUT=>co2_6);
+
+    af_set_cmp_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6), 
+            B1=>AmFullThresh(7), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co2_6, S0=>open, S1=>open, 
+            COUT=>co3_6);
+
+    af_set_cmp_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8), 
+            B1=>AmFullThresh(9), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co3_6, S0=>open, S1=>open, 
+            COUT=>co4_6);
+
+    af_set_cmp_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_10, A1=>wcnt_reg_11, B0=>AmFullThresh(10), 
+            B1=>AmFullThresh(11), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co4_6, S0=>open, S1=>open, 
+            COUT=>co5_6);
+
+    af_set_cmp_6: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_12, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co5_6, S0=>open, S1=>open, 
+            COUT=>af_set_c);
+
+    scuba_vhi_inst: VHI
+        port map (Z=>scuba_vhi);
+
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    a2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>af_set_c, S0=>af_set, S1=>open, 
+            COUT=>open);
+
+    WCNT(0) <= fcount_0;
+    WCNT(1) <= fcount_1;
+    WCNT(2) <= fcount_2;
+    WCNT(3) <= fcount_3;
+    WCNT(4) <= fcount_4;
+    WCNT(5) <= fcount_5;
+    WCNT(6) <= fcount_6;
+    WCNT(7) <= fcount_7;
+    WCNT(8) <= fcount_8;
+    WCNT(9) <= fcount_9;
+    WCNT(10) <= fcount_10;
+    WCNT(11) <= fcount_11;
+    WCNT(12) <= fcount_12;
+    Empty <= empty_i;
+    Full <= full_i;
+end Structure;

diff --git a/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg_ngd.asd b/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg_ngd.asd
new file mode 100644 (file)
index 0000000..c265c78
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg_ngd.asd
@@ -0,0 +1 @@
+[ActiveSupport NGD]

diff --git a/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.cst b/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.cst
new file mode 100644 (file)
index 0000000..5adc24e
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.cst
@@ -0,0 +1,3 @@
+Date=03/18/2015
+Time=14:40:02
+

diff --git a/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.edn b/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.edn
new file mode 100644 (file)
index 0000000..f005697
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.edn
@@ -0,0 +1,2868 @@
+(edif fifo_36x512_oreg
+  (edifVersion 2 0 0)
+  (edifLevel 0)
+  (keywordMap (keywordLevel 0))
+  (status
+    (written
+      (timestamp 2015 3 18 14 40 4)
+      (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80"))))
+      (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x512_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 512 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.fdc ")
+  (library ORCLIB
+    (edifLevel 0)
+    (technology
+      (numberDefinition))
+    (cell CCU2C
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A0
+            (direction INPUT))
+          (port A1
+            (direction INPUT))
+          (port B0
+            (direction INPUT))
+          (port B1
+            (direction INPUT))
+          (port C0
+            (direction INPUT))
+          (port C1
+            (direction INPUT))
+          (port D0
+            (direction INPUT))
+          (port D1
+            (direction INPUT))
+          (port CIN
+            (direction INPUT))
+          (port S0
+            (direction OUTPUT))
+          (port S1
+            (direction OUTPUT))
+          (port COUT
+            (direction OUTPUT)))))
+    (cell AND2
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A
+            (direction INPUT))
+          (port B
+            (direction INPUT))
+          (port Z
+            (direction OUTPUT)))))
+    (cell FD1P3BX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port SP
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port PD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell FD1P3DX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port SP
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port CD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell FD1S3BX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port PD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell FD1S3DX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port CD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell INV
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A
+            (direction INPUT))
+          (port Z
+            (direction OUTPUT)))))
+    (cell ROM16X1A
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port AD3
+            (direction INPUT))
+          (port AD2
+            (direction INPUT))
+          (port AD1
+            (direction INPUT))
+          (port AD0
+            (direction INPUT))
+          (port DO0
+            (direction OUTPUT)))))
+    (cell VHI
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port Z
+            (direction OUTPUT)))))
+    (cell VLO
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port Z
+            (direction OUTPUT)))))
+    (cell XOR2
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A
+            (direction INPUT))
+          (port B
+            (direction INPUT))
+          (port Z
+            (direction OUTPUT)))))
+    (cell PDPW16KD
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port DI35
+            (direction INPUT))
+          (port DI34
+            (direction INPUT))
+          (port DI33
+            (direction INPUT))
+          (port DI32
+            (direction INPUT))
+          (port DI31
+            (direction INPUT))
+          (port DI30
+            (direction INPUT))
+          (port DI29
+            (direction INPUT))
+          (port DI28
+            (direction INPUT))
+          (port DI27
+            (direction INPUT))
+          (port DI26
+            (direction INPUT))
+          (port DI25
+            (direction INPUT))
+          (port DI24
+            (direction INPUT))
+          (port DI23
+            (direction INPUT))
+          (port DI22
+            (direction INPUT))
+          (port DI21
+            (direction INPUT))
+          (port DI20
+            (direction INPUT))
+          (port DI19
+            (direction INPUT))
+          (port DI18
+            (direction INPUT))
+          (port DI17
+            (direction INPUT))
+          (port DI16
+            (direction INPUT))
+          (port DI15
+            (direction INPUT))
+          (port DI14
+            (direction INPUT))
+          (port DI13
+            (direction INPUT))
+          (port DI12
+            (direction INPUT))
+          (port DI11
+            (direction INPUT))
+          (port DI10
+            (direction INPUT))
+          (port DI9
+            (direction INPUT))
+          (port DI8
+            (direction INPUT))
+          (port DI7
+            (direction INPUT))
+          (port DI6
+            (direction INPUT))
+          (port DI5
+            (direction INPUT))
+          (port DI4
+            (direction INPUT))
+          (port DI3
+            (direction INPUT))
+          (port DI2
+            (direction INPUT))
+          (port DI1
+            (direction INPUT))
+          (port DI0
+            (direction INPUT))
+          (port ADW8
+            (direction INPUT))
+          (port ADW7
+            (direction INPUT))
+          (port ADW6
+            (direction INPUT))
+          (port ADW5
+            (direction INPUT))
+          (port ADW4
+            (direction INPUT))
+          (port ADW3
+            (direction INPUT))
+          (port ADW2
+            (direction INPUT))
+          (port ADW1
+            (direction INPUT))
+          (port ADW0
+            (direction INPUT))
+          (port BE3
+            (direction INPUT))
+          (port BE2
+            (direction INPUT))
+          (port BE1
+            (direction INPUT))
+          (port BE0
+            (direction INPUT))
+          (port CEW
+            (direction INPUT))
+          (port CLKW
+            (direction INPUT))
+          (port CSW2
+            (direction INPUT))
+          (port CSW1
+            (direction INPUT))
+          (port CSW0
+            (direction INPUT))
+          (port ADR13
+            (direction INPUT))
+          (port ADR12
+            (direction INPUT))
+          (port ADR11
+            (direction INPUT))
+          (port ADR10
+            (direction INPUT))
+          (port ADR9
+            (direction INPUT))
+          (port ADR8
+            (direction INPUT))
+          (port ADR7
+            (direction INPUT))
+          (port ADR6
+            (direction INPUT))
+          (port ADR5
+            (direction INPUT))
+          (port ADR4
+            (direction INPUT))
+          (port ADR3
+            (direction INPUT))
+          (port ADR2
+            (direction INPUT))
+          (port ADR1
+            (direction INPUT))
+          (port ADR0
+            (direction INPUT))
+          (port CER
+            (direction INPUT))
+          (port OCER
+            (direction INPUT))
+          (port CLKR
+            (direction INPUT))
+          (port CSR2
+            (direction INPUT))
+          (port CSR1
+            (direction INPUT))
+          (port CSR0
+            (direction INPUT))
+          (port RST
+            (direction INPUT))
+          (port DO35
+            (direction OUTPUT))
+          (port DO34
+            (direction OUTPUT))
+          (port DO33
+            (direction OUTPUT))
+          (port DO32
+            (direction OUTPUT))
+          (port DO31
+            (direction OUTPUT))
+          (port DO30
+            (direction OUTPUT))
+          (port DO29
+            (direction OUTPUT))
+          (port DO28
+            (direction OUTPUT))
+          (port DO27
+            (direction OUTPUT))
+          (port DO26
+            (direction OUTPUT))
+          (port DO25
+            (direction OUTPUT))
+          (port DO24
+            (direction OUTPUT))
+          (port DO23
+            (direction OUTPUT))
+          (port DO22
+            (direction OUTPUT))
+          (port DO21
+            (direction OUTPUT))
+          (port DO20
+            (direction OUTPUT))
+          (port DO19
+            (direction OUTPUT))
+          (port DO18
+            (direction OUTPUT))
+          (port DO17
+            (direction OUTPUT))
+          (port DO16
+            (direction OUTPUT))
+          (port DO15
+            (direction OUTPUT))
+          (port DO14
+            (direction OUTPUT))
+          (port DO13
+            (direction OUTPUT))
+          (port DO12
+            (direction OUTPUT))
+          (port DO11
+            (direction OUTPUT))
+          (port DO10
+            (direction OUTPUT))
+          (port DO9
+            (direction OUTPUT))
+          (port DO8
+            (direction OUTPUT))
+          (port DO7
+            (direction OUTPUT))
+          (port DO6
+            (direction OUTPUT))
+          (port DO5
+            (direction OUTPUT))
+          (port DO4
+            (direction OUTPUT))
+          (port DO3
+            (direction OUTPUT))
+          (port DO2
+            (direction OUTPUT))
+          (port DO1
+            (direction OUTPUT))
+          (port DO0
+            (direction OUTPUT)))))
+    (cell fifo_36x512_oreg
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port (array (rename Data "Data(35:0)") 36)
+            (direction INPUT))
+          (port Clock
+            (direction INPUT))
+          (port WrEn
+            (direction INPUT))
+          (port RdEn
+            (direction INPUT))
+          (port Reset
+            (direction INPUT))
+          (port (array (rename AmFullThresh "AmFullThresh(8:0)") 9)
+            (direction INPUT))
+          (port (array (rename Q "Q(35:0)") 36)
+            (direction OUTPUT))
+          (port (array (rename WCNT "WCNT(9:0)") 10)
+            (direction OUTPUT))
+          (port Empty
+            (direction OUTPUT))
+          (port Full
+            (direction OUTPUT))
+          (port AlmostFull
+            (direction OUTPUT)))
+        (property NGD_DRC_MASK (integer 1))
+        (contents
+          (instance AND2_t5
+            (viewRef view1 
+              (cellRef AND2)))
+          (instance INV_5
+            (viewRef view1 
+              (cellRef INV)))
+          (instance AND2_t4
+            (viewRef view1 
+              (cellRef AND2)))
+          (instance INV_4
+            (viewRef view1 
+              (cellRef INV)))
+          (instance AND2_t3
+            (viewRef view1 
+              (cellRef AND2)))
+          (instance XOR2_t2
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance INV_3
+            (viewRef view1 
+              (cellRef INV)))
+          (instance INV_2
+            (viewRef view1 
+              (cellRef INV)))
+          (instance LUT4_1
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x3232")))
+          (instance LUT4_0
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x3232")))
+          (instance AND2_t1
+            (viewRef view1 
+              (cellRef AND2)))
+          (instance INV_1
+            (viewRef view1 
+              (cellRef INV)))
+          (instance XOR2_t0
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance INV_0
+            (viewRef view1 
+              (cellRef INV)))
+          (instance pdp_ram_0_0_0
+            (viewRef view1 
+              (cellRef PDPW16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x512_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_R
+              (string "0b001"))
+            (property CSDECODE_W
+              (string "0b001"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE
+              (string "OUTREG"))
+            (property DATA_WIDTH_R
+              (string "36"))
+            (property DATA_WIDTH_W
+              (string "36")))
+          (instance FF_62
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_61
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_60
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_59
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_58
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_57
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_56
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_55
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_54
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_53
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_52
+            (viewRef view1 
+              (cellRef FD1S3BX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_51
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_50
+            (viewRef view1 
+              (cellRef FD1P3BX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_49
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_48
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_47
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_46
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_45
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_44
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_43
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_42
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_41
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_40
+            (viewRef view1 
+              (cellRef FD1P3BX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_39
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_38
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_37
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_36
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_35
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_34
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_33
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_32
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_31
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_30
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_29
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_28
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_27
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_26
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_25
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_24
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_23
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_22
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_21
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_20
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_19
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_18
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_17
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_16
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_15
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_14
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_13
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_12
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_11
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_10
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_9
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_8
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_7
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_6
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_5
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_4
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_3
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_2
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_1
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_0
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance bdcnt_bctr_cia
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance bdcnt_bctr_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_ci_a
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance e_cmp_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance a0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance g_cmp_ci_a
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance g_cmp_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance a1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_cia
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_cia
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance precin_inst272
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x0000"))
+            (property INIT0
+              (string "0x0000")))
+          (instance wcnt_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_ci_a
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance af_set_cmp_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance scuba_vhi_inst
+            (viewRef view1 
+              (cellRef VHI)))
+          (instance scuba_vlo_inst
+            (viewRef view1 
+              (cellRef VLO)))
+          (instance a2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (net invout_2
+            (joined
+              (portRef Z (instanceRef INV_5))
+              (portRef B (instanceRef AND2_t5))))
+          (net invout_1
+            (joined
+              (portRef Z (instanceRef INV_4))
+              (portRef B (instanceRef AND2_t4))))
+          (net rden_i_inv
+            (joined
+              (portRef Z (instanceRef INV_3))
+              (portRef B (instanceRef AND2_t3))))
+          (net invout_0
+            (joined
+              (portRef Z (instanceRef INV_1))
+              (portRef B (instanceRef AND2_t1))))
+          (net r_nw
+            (joined
+              (portRef Z (instanceRef AND2_t1))))
+          (net fcnt_en
+            (joined
+              (portRef SP (instanceRef FF_53))
+              (portRef Z (instanceRef XOR2_t2))
+              (portRef SP (instanceRef FF_62))
+              (portRef SP (instanceRef FF_61))
+              (portRef SP (instanceRef FF_60))
+              (portRef SP (instanceRef FF_59))
+              (portRef SP (instanceRef FF_58))
+              (portRef SP (instanceRef FF_57))
+              (portRef SP (instanceRef FF_56))
+              (portRef SP (instanceRef FF_55))
+              (portRef SP (instanceRef FF_54))))
+          (net empty_d
+            (joined
+              (portRef D (instanceRef FF_52))
+              (portRef DO0 (instanceRef LUT4_1))))
+          (net full_d
+            (joined
+              (portRef D (instanceRef FF_51))
+              (portRef DO0 (instanceRef LUT4_0))))
+          (net wptr_0
+            (joined
+              (portRef Q (instanceRef FF_30))
+              (portRef ADW0 (instanceRef pdp_ram_0_0_0))))
+          (net wptr_1
+            (joined
+              (portRef Q (instanceRef FF_29))
+              (portRef ADW1 (instanceRef pdp_ram_0_0_0))))
+          (net wptr_2
+            (joined
+              (portRef Q (instanceRef FF_28))
+              (portRef ADW2 (instanceRef pdp_ram_0_0_0))))
+          (net wptr_3
+            (joined
+              (portRef Q (instanceRef FF_27))
+              (portRef ADW3 (instanceRef pdp_ram_0_0_0))))
+          (net wptr_4
+            (joined
+              (portRef Q (instanceRef FF_26))
+              (portRef ADW4 (instanceRef pdp_ram_0_0_0))))
+          (net wptr_5
+            (joined
+              (portRef Q (instanceRef FF_25))
+              (portRef ADW5 (instanceRef pdp_ram_0_0_0))))
+          (net wptr_6
+            (joined
+              (portRef Q (instanceRef FF_24))
+              (portRef ADW6 (instanceRef pdp_ram_0_0_0))))
+          (net wptr_7
+            (joined
+              (portRef Q (instanceRef FF_23))
+              (portRef ADW7 (instanceRef pdp_ram_0_0_0))))
+          (net wptr_8
+            (joined
+              (portRef Q (instanceRef FF_22))
+              (portRef ADW8 (instanceRef pdp_ram_0_0_0))))
+          (net wptr_9
+            (joined
+              (portRef Q (instanceRef FF_21))))
+          (net rptr_9
+            (joined
+              (portRef Q (instanceRef FF_11))
+              (portRef B (instanceRef XOR2_t0))))
+          (net ifcount_0
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_0))
+              (portRef D (instanceRef FF_62))))
+          (net ifcount_1
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_0))
+              (portRef D (instanceRef FF_61))))
+          (net bdcnt_bctr_ci
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_0))
+              (portRef COUT (instanceRef bdcnt_bctr_cia))))
+          (net ifcount_2
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_1))
+              (portRef D (instanceRef FF_60))))
+          (net ifcount_3
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_1))
+              (portRef D (instanceRef FF_59))))
+          (net co0
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_1))
+              (portRef COUT (instanceRef bdcnt_bctr_0))))
+          (net ifcount_4
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_2))
+              (portRef D (instanceRef FF_58))))
+          (net ifcount_5
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_2))
+              (portRef D (instanceRef FF_57))))
+          (net co1
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_2))
+              (portRef COUT (instanceRef bdcnt_bctr_1))))
+          (net ifcount_6
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_3))
+              (portRef D (instanceRef FF_56))))
+          (net ifcount_7
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_3))
+              (portRef D (instanceRef FF_55))))
+          (net co2
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_3))
+              (portRef COUT (instanceRef bdcnt_bctr_2))))
+          (net ifcount_8
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_4))
+              (portRef D (instanceRef FF_54))))
+          (net ifcount_9
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_4))
+              (portRef D (instanceRef FF_53))))
+          (net co4
+            (joined
+              (portRef COUT (instanceRef bdcnt_bctr_4))))
+          (net co3
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_4))
+              (portRef COUT (instanceRef bdcnt_bctr_3))))
+          (net cmp_ci
+            (joined
+              (portRef CIN (instanceRef e_cmp_0))
+              (portRef COUT (instanceRef e_cmp_ci_a))))
+          (net rden_i
+            (joined
+              (portRef A0 (instanceRef e_cmp_0))
+              (portRef Z (instanceRef AND2_t4))
+              (portRef B (instanceRef XOR2_t2))
+              (portRef A (instanceRef INV_3))
+              (portRef AD1 (instanceRef LUT4_0))
+              (portRef A (instanceRef AND2_t1))
+              (portRef CSR0 (instanceRef pdp_ram_0_0_0))
+              (portRef SP (instanceRef FF_40))
+              (portRef SP (instanceRef FF_39))
+              (portRef SP (instanceRef FF_38))
+              (portRef SP (instanceRef FF_37))
+              (portRef SP (instanceRef FF_36))
+              (portRef SP (instanceRef FF_35))
+              (portRef SP (instanceRef FF_34))
+              (portRef SP (instanceRef FF_33))
+              (portRef SP (instanceRef FF_32))
+              (portRef SP (instanceRef FF_31))
+              (portRef SP (instanceRef FF_20))
+              (portRef SP (instanceRef FF_19))
+              (portRef SP (instanceRef FF_18))
+              (portRef SP (instanceRef FF_17))
+              (portRef SP (instanceRef FF_16))
+              (portRef SP (instanceRef FF_15))
+              (portRef SP (instanceRef FF_14))
+              (portRef SP (instanceRef FF_13))
+              (portRef SP (instanceRef FF_12))
+              (portRef SP (instanceRef FF_11))))
+          (net co0_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_1))
+              (portRef COUT (instanceRef e_cmp_0))))
+          (net co1_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_2))
+              (portRef COUT (instanceRef e_cmp_1))))
+          (net co2_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_3))
+              (portRef COUT (instanceRef e_cmp_2))))
+          (net co3_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_4))
+              (portRef COUT (instanceRef e_cmp_3))))
+          (net cmp_le_1
+            (joined
+              (portRef S0 (instanceRef a0))
+              (portRef AD2 (instanceRef LUT4_1))))
+          (net cmp_le_1_c
+            (joined
+              (portRef CIN (instanceRef a0))
+              (portRef COUT (instanceRef e_cmp_4))))
+          (net cmp_ci_1
+            (joined
+              (portRef CIN (instanceRef g_cmp_0))
+              (portRef COUT (instanceRef g_cmp_ci_a))))
+          (net co0_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_1))
+              (portRef COUT (instanceRef g_cmp_0))))
+          (net co1_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_2))
+              (portRef COUT (instanceRef g_cmp_1))))
+          (net co2_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_3))
+              (portRef COUT (instanceRef g_cmp_2))))
+          (net co3_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_4))
+              (portRef COUT (instanceRef g_cmp_3))))
+          (net wren_i_inv
+            (joined
+              (portRef B1 (instanceRef g_cmp_4))
+              (portRef Z (instanceRef INV_2))))
+          (net cmp_ge_d1
+            (joined
+              (portRef S0 (instanceRef a1))
+              (portRef AD2 (instanceRef LUT4_0))))
+          (net cmp_ge_d1_c
+            (joined
+              (portRef CIN (instanceRef a1))
+              (portRef COUT (instanceRef g_cmp_4))))
+          (net iwcount_0
+            (joined
+              (portRef S0 (instanceRef w_ctr_0))
+              (portRef D (instanceRef FF_50))))
+          (net iwcount_1
+            (joined
+              (portRef S1 (instanceRef w_ctr_0))
+              (portRef D (instanceRef FF_49))))
+          (net w_ctr_ci
+            (joined
+              (portRef CIN (instanceRef w_ctr_0))
+              (portRef COUT (instanceRef w_ctr_cia))))
+          (net iwcount_2
+            (joined
+              (portRef S0 (instanceRef w_ctr_1))
+              (portRef D (instanceRef FF_48))))
+          (net iwcount_3
+            (joined
+              (portRef S1 (instanceRef w_ctr_1))
+              (portRef D (instanceRef FF_47))))
+          (net co0_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_1))
+              (portRef COUT (instanceRef w_ctr_0))))
+          (net iwcount_4
+            (joined
+              (portRef S0 (instanceRef w_ctr_2))
+              (portRef D (instanceRef FF_46))))
+          (net iwcount_5
+            (joined
+              (portRef S1 (instanceRef w_ctr_2))
+              (portRef D (instanceRef FF_45))))
+          (net co1_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_2))
+              (portRef COUT (instanceRef w_ctr_1))))
+          (net iwcount_6
+            (joined
+              (portRef S0 (instanceRef w_ctr_3))
+              (portRef D (instanceRef FF_44))))
+          (net iwcount_7
+            (joined
+              (portRef S1 (instanceRef w_ctr_3))
+              (portRef D (instanceRef FF_43))))
+          (net co2_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_3))
+              (portRef COUT (instanceRef w_ctr_2))))
+          (net iwcount_8
+            (joined
+              (portRef S0 (instanceRef w_ctr_4))
+              (portRef D (instanceRef FF_42))))
+          (net iwcount_9
+            (joined
+              (portRef S1 (instanceRef w_ctr_4))
+              (portRef D (instanceRef FF_41))))
+          (net co4_1
+            (joined
+              (portRef COUT (instanceRef w_ctr_4))))
+          (net co3_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_4))
+              (portRef COUT (instanceRef w_ctr_3))))
+          (net wcount_9
+            (joined
+              (portRef A1 (instanceRef w_ctr_4))
+              (portRef A (instanceRef XOR2_t0))
+              (portRef Q (instanceRef FF_41))
+              (portRef D (instanceRef FF_21))))
+          (net ircount_0
+            (joined
+              (portRef S0 (instanceRef r_ctr_0))
+              (portRef D (instanceRef FF_40))))
+          (net ircount_1
+            (joined
+              (portRef S1 (instanceRef r_ctr_0))
+              (portRef D (instanceRef FF_39))))
+          (net r_ctr_ci
+            (joined
+              (portRef CIN (instanceRef r_ctr_0))
+              (portRef COUT (instanceRef r_ctr_cia))))
+          (net rcount_0
+            (joined
+              (portRef A0 (instanceRef r_ctr_0))
+              (portRef Q (instanceRef FF_40))
+              (portRef D (instanceRef FF_20))))
+          (net rcount_1
+            (joined
+              (portRef A1 (instanceRef r_ctr_0))
+              (portRef Q (instanceRef FF_39))
+              (portRef D (instanceRef FF_19))))
+          (net ircount_2
+            (joined
+              (portRef S0 (instanceRef r_ctr_1))
+              (portRef D (instanceRef FF_38))))
+          (net ircount_3
+            (joined
+              (portRef S1 (instanceRef r_ctr_1))
+              (portRef D (instanceRef FF_37))))
+          (net co0_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_1))
+              (portRef COUT (instanceRef r_ctr_0))))
+          (net rcount_2
+            (joined
+              (portRef A0 (instanceRef r_ctr_1))
+              (portRef Q (instanceRef FF_38))
+              (portRef D (instanceRef FF_18))))
+          (net rcount_3
+            (joined
+              (portRef A1 (instanceRef r_ctr_1))
+              (portRef Q (instanceRef FF_37))
+              (portRef D (instanceRef FF_17))))
+          (net ircount_4
+            (joined
+              (portRef S0 (instanceRef r_ctr_2))
+              (portRef D (instanceRef FF_36))))
+          (net ircount_5
+            (joined
+              (portRef S1 (instanceRef r_ctr_2))
+              (portRef D (instanceRef FF_35))))
+          (net co1_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_2))
+              (portRef COUT (instanceRef r_ctr_1))))
+          (net rcount_4
+            (joined
+              (portRef A0 (instanceRef r_ctr_2))
+              (portRef Q (instanceRef FF_36))
+              (portRef D (instanceRef FF_16))))
+          (net rcount_5
+            (joined
+              (portRef A1 (instanceRef r_ctr_2))
+              (portRef Q (instanceRef FF_35))
+              (portRef D (instanceRef FF_15))))
+          (net ircount_6
+            (joined
+              (portRef S0 (instanceRef r_ctr_3))
+              (portRef D (instanceRef FF_34))))
+          (net ircount_7
+            (joined
+              (portRef S1 (instanceRef r_ctr_3))
+              (portRef D (instanceRef FF_33))))
+          (net co2_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_3))
+              (portRef COUT (instanceRef r_ctr_2))))
+          (net rcount_6
+            (joined
+              (portRef A0 (instanceRef r_ctr_3))
+              (portRef Q (instanceRef FF_34))
+              (portRef D (instanceRef FF_14))))
+          (net rcount_7
+            (joined
+              (portRef A1 (instanceRef r_ctr_3))
+              (portRef Q (instanceRef FF_33))
+              (portRef D (instanceRef FF_13))))
+          (net ircount_8
+            (joined
+              (portRef S0 (instanceRef r_ctr_4))
+              (portRef D (instanceRef FF_32))))
+          (net ircount_9
+            (joined
+              (portRef S1 (instanceRef r_ctr_4))
+              (portRef D (instanceRef FF_31))))
+          (net co4_2
+            (joined
+              (portRef COUT (instanceRef r_ctr_4))))
+          (net co3_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_4))
+              (portRef COUT (instanceRef r_ctr_3))))
+          (net rcount_8
+            (joined
+              (portRef A0 (instanceRef r_ctr_4))
+              (portRef Q (instanceRef FF_32))
+              (portRef D (instanceRef FF_12))))
+          (net rcount_9
+            (joined
+              (portRef A1 (instanceRef r_ctr_4))
+              (portRef Q (instanceRef FF_31))
+              (portRef D (instanceRef FF_11))))
+          (net wcnt_sub_0
+            (joined
+              (portRef S1 (instanceRef wcnt_0))
+              (portRef D (instanceRef FF_10))))
+          (net rptr_0
+            (joined
+              (portRef B1 (instanceRef wcnt_0))
+              (portRef ADR5 (instanceRef pdp_ram_0_0_0))
+              (portRef Q (instanceRef FF_20))))
+          (net cnt_con_inv
+            (joined
+              (portRef B0 (instanceRef wcnt_0))
+              (portRef Z (instanceRef INV_0))))
+          (net wcount_0
+            (joined
+              (portRef A1 (instanceRef wcnt_0))
+              (portRef Q (instanceRef FF_50))
+              (portRef D (instanceRef FF_30))
+              (portRef A0 (instanceRef w_ctr_0))))
+          (net cnt_con
+            (joined
+              (portRef A0 (instanceRef wcnt_0))
+              (portRef Z (instanceRef AND2_t3))
+              (portRef A (instanceRef INV_0))
+              (portRef B1 (instanceRef bdcnt_bctr_cia))
+              (portRef A1 (instanceRef bdcnt_bctr_cia))
+              (portRef B1 (instanceRef bdcnt_bctr_0))
+              (portRef B0 (instanceRef bdcnt_bctr_0))
+              (portRef B1 (instanceRef bdcnt_bctr_1))
+              (portRef B0 (instanceRef bdcnt_bctr_1))
+              (portRef B1 (instanceRef bdcnt_bctr_2))
+              (portRef B0 (instanceRef bdcnt_bctr_2))
+              (portRef B1 (instanceRef bdcnt_bctr_3))
+              (portRef B0 (instanceRef bdcnt_bctr_3))
+              (portRef B1 (instanceRef bdcnt_bctr_4))
+              (portRef B0 (instanceRef bdcnt_bctr_4))))
+          (net precin
+            (joined
+              (portRef CIN (instanceRef wcnt_0))
+              (portRef COUT (instanceRef precin_inst272))))
+          (net wcnt_sub_1
+            (joined
+              (portRef S0 (instanceRef wcnt_1))
+              (portRef D (instanceRef FF_9))))
+          (net wcnt_sub_2
+            (joined
+              (portRef S1 (instanceRef wcnt_1))
+              (portRef D (instanceRef FF_8))))
+          (net rptr_2
+            (joined
+              (portRef B1 (instanceRef wcnt_1))
+              (portRef ADR7 (instanceRef pdp_ram_0_0_0))
+              (portRef Q (instanceRef FF_18))))
+          (net rptr_1
+            (joined
+              (portRef B0 (instanceRef wcnt_1))
+              (portRef ADR6 (instanceRef pdp_ram_0_0_0))
+              (portRef Q (instanceRef FF_19))))
+          (net wcount_2
+            (joined
+              (portRef A1 (instanceRef wcnt_1))
+              (portRef Q (instanceRef FF_48))
+              (portRef D (instanceRef FF_28))
+              (portRef A0 (instanceRef w_ctr_1))))
+          (net wcount_1
+            (joined
+              (portRef A0 (instanceRef wcnt_1))
+              (portRef Q (instanceRef FF_49))
+              (portRef D (instanceRef FF_29))
+              (portRef A1 (instanceRef w_ctr_0))))
+          (net co0_5
+            (joined
+              (portRef CIN (instanceRef wcnt_1))
+              (portRef COUT (instanceRef wcnt_0))))
+          (net wcnt_sub_3
+            (joined
+              (portRef S0 (instanceRef wcnt_2))
+              (portRef D (instanceRef FF_7))))
+          (net wcnt_sub_4
+            (joined
+              (portRef S1 (instanceRef wcnt_2))
+              (portRef D (instanceRef FF_6))))
+          (net rptr_4
+            (joined
+              (portRef B1 (instanceRef wcnt_2))
+              (portRef ADR9 (instanceRef pdp_ram_0_0_0))
+              (portRef Q (instanceRef FF_16))))
+          (net rptr_3
+            (joined
+              (portRef B0 (instanceRef wcnt_2))
+              (portRef ADR8 (instanceRef pdp_ram_0_0_0))
+              (portRef Q (instanceRef FF_17))))
+          (net wcount_4
+            (joined
+              (portRef A1 (instanceRef wcnt_2))
+              (portRef Q (instanceRef FF_46))
+              (portRef D (instanceRef FF_26))
+              (portRef A0 (instanceRef w_ctr_2))))
+          (net wcount_3
+            (joined
+              (portRef A0 (instanceRef wcnt_2))
+              (portRef Q (instanceRef FF_47))
+              (portRef D (instanceRef FF_27))
+              (portRef A1 (instanceRef w_ctr_1))))
+          (net co1_5
+            (joined
+              (portRef CIN (instanceRef wcnt_2))
+              (portRef COUT (instanceRef wcnt_1))))
+          (net wcnt_sub_5
+            (joined
+              (portRef S0 (instanceRef wcnt_3))
+              (portRef D (instanceRef FF_5))))
+          (net wcnt_sub_6
+            (joined
+              (portRef S1 (instanceRef wcnt_3))
+              (portRef D (instanceRef FF_4))))
+          (net rptr_6
+            (joined
+              (portRef B1 (instanceRef wcnt_3))
+              (portRef ADR11 (instanceRef pdp_ram_0_0_0))
+              (portRef Q (instanceRef FF_14))))
+          (net rptr_5
+            (joined
+              (portRef B0 (instanceRef wcnt_3))
+              (portRef ADR10 (instanceRef pdp_ram_0_0_0))
+              (portRef Q (instanceRef FF_15))))
+          (net wcount_6
+            (joined
+              (portRef A1 (instanceRef wcnt_3))
+              (portRef Q (instanceRef FF_44))
+              (portRef D (instanceRef FF_24))
+              (portRef A0 (instanceRef w_ctr_3))))
+          (net wcount_5
+            (joined
+              (portRef A0 (instanceRef wcnt_3))
+              (portRef Q (instanceRef FF_45))
+              (portRef D (instanceRef FF_25))
+              (portRef A1 (instanceRef w_ctr_2))))
+          (net co2_5
+            (joined
+              (portRef CIN (instanceRef wcnt_3))
+              (portRef COUT (instanceRef wcnt_2))))
+          (net wcnt_sub_7
+            (joined
+              (portRef S0 (instanceRef wcnt_4))
+              (portRef D (instanceRef FF_3))))
+          (net wcnt_sub_8
+            (joined
+              (portRef S1 (instanceRef wcnt_4))
+              (portRef D (instanceRef FF_2))))
+          (net rptr_8
+            (joined
+              (portRef B1 (instanceRef wcnt_4))
+              (portRef ADR13 (instanceRef pdp_ram_0_0_0))
+              (portRef Q (instanceRef FF_12))))
+          (net rptr_7
+            (joined
+              (portRef B0 (instanceRef wcnt_4))
+              (portRef ADR12 (instanceRef pdp_ram_0_0_0))
+              (portRef Q (instanceRef FF_13))))
+          (net wcount_8
+            (joined
+              (portRef A1 (instanceRef wcnt_4))
+              (portRef Q (instanceRef FF_42))
+              (portRef D (instanceRef FF_22))
+              (portRef A0 (instanceRef w_ctr_4))))
+          (net wcount_7
+            (joined
+              (portRef A0 (instanceRef wcnt_4))
+              (portRef Q (instanceRef FF_43))
+              (portRef D (instanceRef FF_23))
+              (portRef A1 (instanceRef w_ctr_3))))
+          (net co3_5
+            (joined
+              (portRef CIN (instanceRef wcnt_4))
+              (portRef COUT (instanceRef wcnt_3))))
+          (net wcnt_sub_9
+            (joined
+              (portRef S0 (instanceRef wcnt_5))
+              (portRef D (instanceRef FF_1))))
+          (net wcnt_sub_msb
+            (joined
+              (portRef A0 (instanceRef wcnt_5))
+              (portRef Z (instanceRef XOR2_t0))))
+          (net co4_3
+            (joined
+              (portRef CIN (instanceRef wcnt_5))
+              (portRef COUT (instanceRef wcnt_4))))
+          (net wren_i
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_ci_a))
+              (portRef Z (instanceRef AND2_t5))
+              (portRef A (instanceRef AND2_t3))
+              (portRef A (instanceRef XOR2_t2))
+              (portRef A (instanceRef INV_2))
+              (portRef AD1 (instanceRef LUT4_1))
+              (portRef A (instanceRef INV_1))
+              (portRef CEW (instanceRef pdp_ram_0_0_0))
+              (portRef SP (instanceRef FF_50))
+              (portRef SP (instanceRef FF_49))
+              (portRef SP (instanceRef FF_48))
+              (portRef SP (instanceRef FF_47))
+              (portRef SP (instanceRef FF_46))
+              (portRef SP (instanceRef FF_45))
+              (portRef SP (instanceRef FF_44))
+              (portRef SP (instanceRef FF_43))
+              (portRef SP (instanceRef FF_42))
+              (portRef SP (instanceRef FF_41))
+              (portRef SP (instanceRef FF_30))
+              (portRef SP (instanceRef FF_29))
+              (portRef SP (instanceRef FF_28))
+              (portRef SP (instanceRef FF_27))
+              (portRef SP (instanceRef FF_26))
+              (portRef SP (instanceRef FF_25))
+              (portRef SP (instanceRef FF_24))
+              (portRef SP (instanceRef FF_23))
+              (portRef SP (instanceRef FF_22))
+              (portRef SP (instanceRef FF_21))
+              (portRef B0 (instanceRef g_cmp_0))
+              (portRef B1 (instanceRef g_cmp_0))
+              (portRef B0 (instanceRef g_cmp_1))
+              (portRef B1 (instanceRef g_cmp_1))
+              (portRef B0 (instanceRef g_cmp_2))
+              (portRef B1 (instanceRef g_cmp_2))
+              (portRef B0 (instanceRef g_cmp_3))
+              (portRef B1 (instanceRef g_cmp_3))
+              (portRef B0 (instanceRef g_cmp_4))
+              (portRef B1 (instanceRef af_set_cmp_ci_a))))
+          (net x
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_ci_a))
+              (portRef CIN (instanceRef bdcnt_bctr_cia))
+              (portRef CIN (instanceRef e_cmp_ci_a))
+              (portRef CIN (instanceRef g_cmp_ci_a))
+              (portRef CIN (instanceRef w_ctr_cia))
+              (portRef CIN (instanceRef r_ctr_cia))
+              (portRef CIN (instanceRef precin_inst272))))
+          (net cmp_ci_2
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_0))
+              (portRef COUT (instanceRef af_set_cmp_ci_a))))
+          (net wcnt_reg_0
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_0))
+              (portRef Q (instanceRef FF_10))))
+          (net wcnt_reg_1
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_0))
+              (portRef Q (instanceRef FF_9))))
+          (net co0_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_1))
+              (portRef COUT (instanceRef af_set_cmp_0))))
+          (net wcnt_reg_2
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_1))
+              (portRef Q (instanceRef FF_8))))
+          (net wcnt_reg_3
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_1))
+              (portRef Q (instanceRef FF_7))))
+          (net co1_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_2))
+              (portRef COUT (instanceRef af_set_cmp_1))))
+          (net wcnt_reg_4
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_2))
+              (portRef Q (instanceRef FF_6))))
+          (net wcnt_reg_5
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_2))
+              (portRef Q (instanceRef FF_5))))
+          (net co2_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_3))
+              (portRef COUT (instanceRef af_set_cmp_2))))
+          (net wcnt_reg_6
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_3))
+              (portRef Q (instanceRef FF_4))))
+          (net wcnt_reg_7
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_3))
+              (portRef Q (instanceRef FF_3))))
+          (net co3_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_4))
+              (portRef COUT (instanceRef af_set_cmp_3))))
+          (net wcnt_reg_8
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_4))
+              (portRef Q (instanceRef FF_2))))
+          (net wcnt_reg_9
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_4))
+              (portRef Q (instanceRef FF_1))))
+          (net af_set
+            (joined
+              (portRef S0 (instanceRef a2))
+              (portRef D (instanceRef FF_0))))
+          (net scuba_vhi
+            (joined
+              (portRef Z (instanceRef scuba_vhi_inst))
+              (portRef CSW0 (instanceRef pdp_ram_0_0_0))
+              (portRef BE3 (instanceRef pdp_ram_0_0_0))
+              (portRef BE2 (instanceRef pdp_ram_0_0_0))
+              (portRef BE1 (instanceRef pdp_ram_0_0_0))
+              (portRef BE0 (instanceRef pdp_ram_0_0_0))
+              (portRef OCER (instanceRef pdp_ram_0_0_0))
+              (portRef CER (instanceRef pdp_ram_0_0_0))
+              (portRef C1 (instanceRef bdcnt_bctr_cia))
+              (portRef C0 (instanceRef bdcnt_bctr_cia))
+              (portRef D1 (instanceRef bdcnt_bctr_cia))
+              (portRef D0 (instanceRef bdcnt_bctr_cia))
+              (portRef D1 (instanceRef bdcnt_bctr_0))
+              (portRef D0 (instanceRef bdcnt_bctr_0))
+              (portRef C1 (instanceRef bdcnt_bctr_0))
+              (portRef C0 (instanceRef bdcnt_bctr_0))
+              (portRef D1 (instanceRef bdcnt_bctr_1))
+              (portRef D0 (instanceRef bdcnt_bctr_1))
+              (portRef C1 (instanceRef bdcnt_bctr_1))
+              (portRef C0 (instanceRef bdcnt_bctr_1))
+              (portRef D1 (instanceRef bdcnt_bctr_2))
+              (portRef D0 (instanceRef bdcnt_bctr_2))
+              (portRef C1 (instanceRef bdcnt_bctr_2))
+              (portRef C0 (instanceRef bdcnt_bctr_2))
+              (portRef D1 (instanceRef bdcnt_bctr_3))
+              (portRef D0 (instanceRef bdcnt_bctr_3))
+              (portRef C1 (instanceRef bdcnt_bctr_3))
+              (portRef C0 (instanceRef bdcnt_bctr_3))
+              (portRef D1 (instanceRef bdcnt_bctr_4))
+              (portRef D0 (instanceRef bdcnt_bctr_4))
+              (portRef C1 (instanceRef bdcnt_bctr_4))
+              (portRef C0 (instanceRef bdcnt_bctr_4))
+              (portRef C1 (instanceRef e_cmp_ci_a))
+              (portRef C0 (instanceRef e_cmp_ci_a))
+              (portRef D1 (instanceRef e_cmp_ci_a))
+              (portRef D0 (instanceRef e_cmp_ci_a))
+              (portRef B1 (instanceRef e_cmp_ci_a))
+              (portRef B0 (instanceRef e_cmp_ci_a))
+              (portRef A1 (instanceRef e_cmp_ci_a))
+              (portRef A0 (instanceRef e_cmp_ci_a))
+              (portRef D1 (instanceRef e_cmp_0))
+              (portRef D0 (instanceRef e_cmp_0))
+              (portRef C1 (instanceRef e_cmp_0))
+              (portRef C0 (instanceRef e_cmp_0))
+              (portRef D1 (instanceRef e_cmp_1))
+              (portRef D0 (instanceRef e_cmp_1))
+              (portRef C1 (instanceRef e_cmp_1))
+              (portRef C0 (instanceRef e_cmp_1))
+              (portRef D1 (instanceRef e_cmp_2))
+              (portRef D0 (instanceRef e_cmp_2))
+              (portRef C1 (instanceRef e_cmp_2))
+              (portRef C0 (instanceRef e_cmp_2))
+              (portRef D1 (instanceRef e_cmp_3))
+              (portRef D0 (instanceRef e_cmp_3))
+              (portRef C1 (instanceRef e_cmp_3))
+              (portRef C0 (instanceRef e_cmp_3))
+              (portRef D1 (instanceRef e_cmp_4))
+              (portRef D0 (instanceRef e_cmp_4))
+              (portRef C1 (instanceRef e_cmp_4))
+              (portRef C0 (instanceRef e_cmp_4))
+              (portRef C1 (instanceRef a0))
+              (portRef C0 (instanceRef a0))
+              (portRef D1 (instanceRef a0))
+              (portRef D0 (instanceRef a0))
+              (portRef C1 (instanceRef g_cmp_ci_a))
+              (portRef C0 (instanceRef g_cmp_ci_a))
+              (portRef D1 (instanceRef g_cmp_ci_a))
+              (portRef D0 (instanceRef g_cmp_ci_a))
+              (portRef B1 (instanceRef g_cmp_ci_a))
+              (portRef B0 (instanceRef g_cmp_ci_a))
+              (portRef A1 (instanceRef g_cmp_ci_a))
+              (portRef A0 (instanceRef g_cmp_ci_a))
+              (portRef D1 (instanceRef g_cmp_0))
+              (portRef D0 (instanceRef g_cmp_0))
+              (portRef C1 (instanceRef g_cmp_0))
+              (portRef C0 (instanceRef g_cmp_0))
+              (portRef D1 (instanceRef g_cmp_1))
+              (portRef D0 (instanceRef g_cmp_1))
+              (portRef C1 (instanceRef g_cmp_1))
+              (portRef C0 (instanceRef g_cmp_1))
+              (portRef D1 (instanceRef g_cmp_2))
+              (portRef D0 (instanceRef g_cmp_2))
+              (portRef C1 (instanceRef g_cmp_2))
+              (portRef C0 (instanceRef g_cmp_2))
+              (portRef D1 (instanceRef g_cmp_3))
+              (portRef D0 (instanceRef g_cmp_3))
+              (portRef C1 (instanceRef g_cmp_3))
+              (portRef C0 (instanceRef g_cmp_3))
+              (portRef D1 (instanceRef g_cmp_4))
+              (portRef D0 (instanceRef g_cmp_4))
+              (portRef C1 (instanceRef g_cmp_4))
+              (portRef C0 (instanceRef g_cmp_4))
+              (portRef C1 (instanceRef a1))
+              (portRef C0 (instanceRef a1))
+              (portRef D1 (instanceRef a1))
+              (portRef D0 (instanceRef a1))
+              (portRef C1 (instanceRef w_ctr_cia))
+              (portRef C0 (instanceRef w_ctr_cia))
+              (portRef D1 (instanceRef w_ctr_cia))
+              (portRef D0 (instanceRef w_ctr_cia))
+              (portRef B1 (instanceRef w_ctr_cia))
+              (portRef A1 (instanceRef w_ctr_cia))
+              (portRef D1 (instanceRef w_ctr_0))
+              (portRef D0 (instanceRef w_ctr_0))
+              (portRef C1 (instanceRef w_ctr_0))
+              (portRef C0 (instanceRef w_ctr_0))
+              (portRef D1 (instanceRef w_ctr_1))
+              (portRef D0 (instanceRef w_ctr_1))
+              (portRef C1 (instanceRef w_ctr_1))
+              (portRef C0 (instanceRef w_ctr_1))
+              (portRef D1 (instanceRef w_ctr_2))
+              (portRef D0 (instanceRef w_ctr_2))
+              (portRef C1 (instanceRef w_ctr_2))
+              (portRef C0 (instanceRef w_ctr_2))
+              (portRef D1 (instanceRef w_ctr_3))
+              (portRef D0 (instanceRef w_ctr_3))
+              (portRef C1 (instanceRef w_ctr_3))
+              (portRef C0 (instanceRef w_ctr_3))
+              (portRef D1 (instanceRef w_ctr_4))
+              (portRef D0 (instanceRef w_ctr_4))
+              (portRef C1 (instanceRef w_ctr_4))
+              (portRef C0 (instanceRef w_ctr_4))
+              (portRef C1 (instanceRef r_ctr_cia))
+              (portRef C0 (instanceRef r_ctr_cia))
+              (portRef D1 (instanceRef r_ctr_cia))
+              (portRef D0 (instanceRef r_ctr_cia))
+              (portRef B1 (instanceRef r_ctr_cia))
+              (portRef A1 (instanceRef r_ctr_cia))
+              (portRef D1 (instanceRef r_ctr_0))
+              (portRef D0 (instanceRef r_ctr_0))
+              (portRef C1 (instanceRef r_ctr_0))
+              (portRef C0 (instanceRef r_ctr_0))
+              (portRef D1 (instanceRef r_ctr_1))
+              (portRef D0 (instanceRef r_ctr_1))
+              (portRef C1 (instanceRef r_ctr_1))
+              (portRef C0 (instanceRef r_ctr_1))
+              (portRef D1 (instanceRef r_ctr_2))
+              (portRef D0 (instanceRef r_ctr_2))
+              (portRef C1 (instanceRef r_ctr_2))
+              (portRef C0 (instanceRef r_ctr_2))
+              (portRef D1 (instanceRef r_ctr_3))
+              (portRef D0 (instanceRef r_ctr_3))
+              (portRef C1 (instanceRef r_ctr_3))
+              (portRef C0 (instanceRef r_ctr_3))
+              (portRef D1 (instanceRef r_ctr_4))
+              (portRef D0 (instanceRef r_ctr_4))
+              (portRef C1 (instanceRef r_ctr_4))
+              (portRef C0 (instanceRef r_ctr_4))
+              (portRef C1 (instanceRef precin_inst272))
+              (portRef C0 (instanceRef precin_inst272))
+              (portRef D1 (instanceRef precin_inst272))
+              (portRef D0 (instanceRef precin_inst272))
+              (portRef B1 (instanceRef precin_inst272))
+              (portRef B0 (instanceRef precin_inst272))
+              (portRef A1 (instanceRef precin_inst272))
+              (portRef A0 (instanceRef precin_inst272))
+              (portRef C1 (instanceRef wcnt_0))
+              (portRef C0 (instanceRef wcnt_0))
+              (portRef D1 (instanceRef wcnt_0))
+              (portRef D0 (instanceRef wcnt_0))
+              (portRef C1 (instanceRef wcnt_1))
+              (portRef C0 (instanceRef wcnt_1))
+              (portRef D1 (instanceRef wcnt_1))
+              (portRef D0 (instanceRef wcnt_1))
+              (portRef C1 (instanceRef wcnt_2))
+              (portRef C0 (instanceRef wcnt_2))
+              (portRef D1 (instanceRef wcnt_2))
+              (portRef D0 (instanceRef wcnt_2))
+              (portRef C1 (instanceRef wcnt_3))
+              (portRef C0 (instanceRef wcnt_3))
+              (portRef D1 (instanceRef wcnt_3))
+              (portRef D0 (instanceRef wcnt_3))
+              (portRef C1 (instanceRef wcnt_4))
+              (portRef C0 (instanceRef wcnt_4))
+              (portRef D1 (instanceRef wcnt_4))
+              (portRef D0 (instanceRef wcnt_4))
+              (portRef C1 (instanceRef wcnt_5))
+              (portRef C0 (instanceRef wcnt_5))
+              (portRef D1 (instanceRef wcnt_5))
+              (portRef D0 (instanceRef wcnt_5))
+              (portRef C1 (instanceRef af_set_cmp_ci_a))
+              (portRef C0 (instanceRef af_set_cmp_ci_a))
+              (portRef D1 (instanceRef af_set_cmp_ci_a))
+              (portRef D0 (instanceRef af_set_cmp_ci_a))
+              (portRef D1 (instanceRef af_set_cmp_0))
+              (portRef D0 (instanceRef af_set_cmp_0))
+              (portRef C1 (instanceRef af_set_cmp_0))
+              (portRef C0 (instanceRef af_set_cmp_0))
+              (portRef D1 (instanceRef af_set_cmp_1))
+              (portRef D0 (instanceRef af_set_cmp_1))
+              (portRef C1 (instanceRef af_set_cmp_1))
+              (portRef C0 (instanceRef af_set_cmp_1))
+              (portRef D1 (instanceRef af_set_cmp_2))
+              (portRef D0 (instanceRef af_set_cmp_2))
+              (portRef C1 (instanceRef af_set_cmp_2))
+              (portRef C0 (instanceRef af_set_cmp_2))
+              (portRef D1 (instanceRef af_set_cmp_3))
+              (portRef D0 (instanceRef af_set_cmp_3))
+              (portRef C1 (instanceRef af_set_cmp_3))
+              (portRef C0 (instanceRef af_set_cmp_3))
+              (portRef D1 (instanceRef af_set_cmp_4))
+              (portRef D0 (instanceRef af_set_cmp_4))
+              (portRef C1 (instanceRef af_set_cmp_4))
+              (portRef C0 (instanceRef af_set_cmp_4))
+              (portRef C1 (instanceRef a2))
+              (portRef C0 (instanceRef a2))
+              (portRef D1 (instanceRef a2))
+              (portRef D0 (instanceRef a2))))
+          (net scuba_vlo
+            (joined
+              (portRef Z (instanceRef scuba_vlo_inst))
+              (portRef AD3 (instanceRef LUT4_1))
+              (portRef AD3 (instanceRef LUT4_0))
+              (portRef CSR2 (instanceRef pdp_ram_0_0_0))
+              (portRef CSW2 (instanceRef pdp_ram_0_0_0))
+              (portRef CSR1 (instanceRef pdp_ram_0_0_0))
+              (portRef CSW1 (instanceRef pdp_ram_0_0_0))
+              (portRef ADR4 (instanceRef pdp_ram_0_0_0))
+              (portRef ADR3 (instanceRef pdp_ram_0_0_0))
+              (portRef ADR2 (instanceRef pdp_ram_0_0_0))
+              (portRef ADR1 (instanceRef pdp_ram_0_0_0))
+              (portRef ADR0 (instanceRef pdp_ram_0_0_0))
+              (portRef B0 (instanceRef bdcnt_bctr_cia))
+              (portRef A0 (instanceRef bdcnt_bctr_cia))
+              (portRef A1 (instanceRef e_cmp_0))
+              (portRef A0 (instanceRef e_cmp_1))
+              (portRef A1 (instanceRef e_cmp_1))
+              (portRef A0 (instanceRef e_cmp_2))
+              (portRef A1 (instanceRef e_cmp_2))
+              (portRef A0 (instanceRef e_cmp_3))
+              (portRef A1 (instanceRef e_cmp_3))
+              (portRef A0 (instanceRef e_cmp_4))
+              (portRef A1 (instanceRef e_cmp_4))
+              (portRef B1 (instanceRef a0))
+              (portRef B0 (instanceRef a0))
+              (portRef A1 (instanceRef a0))
+              (portRef A0 (instanceRef a0))
+              (portRef B1 (instanceRef a1))
+              (portRef B0 (instanceRef a1))
+              (portRef A1 (instanceRef a1))
+              (portRef A0 (instanceRef a1))
+              (portRef B0 (instanceRef w_ctr_cia))
+              (portRef A0 (instanceRef w_ctr_cia))
+              (portRef B1 (instanceRef w_ctr_0))
+              (portRef B0 (instanceRef w_ctr_0))
+              (portRef B1 (instanceRef w_ctr_1))
+              (portRef B0 (instanceRef w_ctr_1))
+              (portRef B1 (instanceRef w_ctr_2))
+              (portRef B0 (instanceRef w_ctr_2))
+              (portRef B1 (instanceRef w_ctr_3))
+              (portRef B0 (instanceRef w_ctr_3))
+              (portRef B1 (instanceRef w_ctr_4))
+              (portRef B0 (instanceRef w_ctr_4))
+              (portRef B0 (instanceRef r_ctr_cia))
+              (portRef A0 (instanceRef r_ctr_cia))
+              (portRef B1 (instanceRef r_ctr_0))
+              (portRef B0 (instanceRef r_ctr_0))
+              (portRef B1 (instanceRef r_ctr_1))
+              (portRef B0 (instanceRef r_ctr_1))
+              (portRef B1 (instanceRef r_ctr_2))
+              (portRef B0 (instanceRef r_ctr_2))
+              (portRef B1 (instanceRef r_ctr_3))
+              (portRef B0 (instanceRef r_ctr_3))
+              (portRef B1 (instanceRef r_ctr_4))
+              (portRef B0 (instanceRef r_ctr_4))
+              (portRef B1 (instanceRef wcnt_5))
+              (portRef B0 (instanceRef wcnt_5))
+              (portRef A1 (instanceRef wcnt_5))
+              (portRef B0 (instanceRef af_set_cmp_ci_a))
+              (portRef A0 (instanceRef af_set_cmp_ci_a))
+              (portRef B1 (instanceRef af_set_cmp_4))
+              (portRef B1 (instanceRef a2))
+              (portRef B0 (instanceRef a2))
+              (portRef A1 (instanceRef a2))
+              (portRef A0 (instanceRef a2))))
+          (net af_set_c
+            (joined
+              (portRef CIN (instanceRef a2))
+              (portRef COUT (instanceRef af_set_cmp_4))))
+          (net partial_full
+            (joined
+              (portRef AlmostFull)
+              (portRef Q (instanceRef FF_0))))
+          (net Full
+            (joined
+              (portRef Full)
+              (portRef Q (instanceRef FF_51))
+              (portRef A (instanceRef INV_5))
+              (portRef AD0 (instanceRef LUT4_0))))
+          (net Empty
+            (joined
+              (portRef Empty)
+              (portRef Q (instanceRef FF_52))
+              (portRef A (instanceRef INV_4))
+              (portRef AD0 (instanceRef LUT4_1))))
+          (net WCNT9
+            (joined
+              (portRef (member WCNT 0))
+              (portRef A1 (instanceRef g_cmp_4))
+              (portRef Q (instanceRef FF_53))
+              (portRef A1 (instanceRef bdcnt_bctr_4))
+              (portRef B1 (instanceRef e_cmp_4))))
+          (net WCNT8
+            (joined
+              (portRef (member WCNT 1))
+              (portRef A0 (instanceRef g_cmp_4))
+              (portRef Q (instanceRef FF_54))
+              (portRef A0 (instanceRef bdcnt_bctr_4))
+              (portRef B0 (instanceRef e_cmp_4))))
+          (net WCNT7
+            (joined
+              (portRef (member WCNT 2))
+              (portRef A1 (instanceRef g_cmp_3))
+              (portRef Q (instanceRef FF_55))
+              (portRef A1 (instanceRef bdcnt_bctr_3))
+              (portRef B1 (instanceRef e_cmp_3))))
+          (net WCNT6
+            (joined
+              (portRef (member WCNT 3))
+              (portRef A0 (instanceRef g_cmp_3))
+              (portRef Q (instanceRef FF_56))
+              (portRef A0 (instanceRef bdcnt_bctr_3))
+              (portRef B0 (instanceRef e_cmp_3))))
+          (net WCNT5
+            (joined
+              (portRef (member WCNT 4))
+              (portRef A1 (instanceRef g_cmp_2))
+              (portRef Q (instanceRef FF_57))
+              (portRef A1 (instanceRef bdcnt_bctr_2))
+              (portRef B1 (instanceRef e_cmp_2))))
+          (net WCNT4
+            (joined
+              (portRef (member WCNT 5))
+              (portRef A0 (instanceRef g_cmp_2))
+              (portRef Q (instanceRef FF_58))
+              (portRef A0 (instanceRef bdcnt_bctr_2))
+              (portRef B0 (instanceRef e_cmp_2))))
+          (net WCNT3
+            (joined
+              (portRef (member WCNT 6))
+              (portRef A1 (instanceRef g_cmp_1))
+              (portRef Q (instanceRef FF_59))
+              (portRef A1 (instanceRef bdcnt_bctr_1))
+              (portRef B1 (instanceRef e_cmp_1))))
+          (net WCNT2
+            (joined
+              (portRef (member WCNT 7))
+              (portRef A0 (instanceRef g_cmp_1))
+              (portRef Q (instanceRef FF_60))
+              (portRef A0 (instanceRef bdcnt_bctr_1))
+              (portRef B0 (instanceRef e_cmp_1))))
+          (net WCNT1
+            (joined
+              (portRef (member WCNT 8))
+              (portRef A1 (instanceRef g_cmp_0))
+              (portRef Q (instanceRef FF_61))
+              (portRef A1 (instanceRef bdcnt_bctr_0))
+              (portRef B1 (instanceRef e_cmp_0))))
+          (net WCNT0
+            (joined
+              (portRef (member WCNT 9))
+              (portRef A0 (instanceRef g_cmp_0))
+              (portRef Q (instanceRef FF_62))
+              (portRef A0 (instanceRef bdcnt_bctr_0))
+              (portRef B0 (instanceRef e_cmp_0))))
+          (net dataout35
+            (joined
+              (portRef (member Q 0))
+              (portRef DO17 (instanceRef pdp_ram_0_0_0))))
+          (net dataout34
+            (joined
+              (portRef (member Q 1))
+              (portRef DO16 (instanceRef pdp_ram_0_0_0))))
+          (net dataout33
+            (joined
+              (portRef (member Q 2))
+              (portRef DO15 (instanceRef pdp_ram_0_0_0))))
+          (net dataout32
+            (joined
+              (portRef (member Q 3))
+              (portRef DO14 (instanceRef pdp_ram_0_0_0))))
+          (net dataout31
+            (joined
+              (portRef (member Q 4))
+              (portRef DO13 (instanceRef pdp_ram_0_0_0))))
+          (net dataout30
+            (joined
+              (portRef (member Q 5))
+              (portRef DO12 (instanceRef pdp_ram_0_0_0))))
+          (net dataout29
+            (joined
+              (portRef (member Q 6))
+              (portRef DO11 (instanceRef pdp_ram_0_0_0))))
+          (net dataout28
+            (joined
+              (portRef (member Q 7))
+              (portRef DO10 (instanceRef pdp_ram_0_0_0))))
+          (net dataout27
+            (joined
+              (portRef (member Q 8))
+              (portRef DO9 (instanceRef pdp_ram_0_0_0))))
+          (net dataout26
+            (joined
+              (portRef (member Q 9))
+              (portRef DO8 (instanceRef pdp_ram_0_0_0))))
+          (net dataout25
+            (joined
+              (portRef (member Q 10))
+              (portRef DO7 (instanceRef pdp_ram_0_0_0))))
+          (net dataout24
+            (joined
+              (portRef (member Q 11))
+              (portRef DO6 (instanceRef pdp_ram_0_0_0))))
+          (net dataout23
+            (joined
+              (portRef (member Q 12))
+              (portRef DO5 (instanceRef pdp_ram_0_0_0))))
+          (net dataout22
+            (joined
+              (portRef (member Q 13))
+              (portRef DO4 (instanceRef pdp_ram_0_0_0))))
+          (net dataout21
+            (joined
+              (portRef (member Q 14))
+              (portRef DO3 (instanceRef pdp_ram_0_0_0))))
+          (net dataout20
+            (joined
+              (portRef (member Q 15))
+              (portRef DO2 (instanceRef pdp_ram_0_0_0))))
+          (net dataout19
+            (joined
+              (portRef (member Q 16))
+              (portRef DO1 (instanceRef pdp_ram_0_0_0))))
+          (net dataout18
+            (joined
+              (portRef (member Q 17))
+              (portRef DO0 (instanceRef pdp_ram_0_0_0))))
+          (net dataout17
+            (joined
+              (portRef (member Q 18))
+              (portRef DO35 (instanceRef pdp_ram_0_0_0))))
+          (net dataout16
+            (joined
+              (portRef (member Q 19))
+              (portRef DO34 (instanceRef pdp_ram_0_0_0))))
+          (net dataout15
+            (joined
+              (portRef (member Q 20))
+              (portRef DO33 (instanceRef pdp_ram_0_0_0))))
+          (net dataout14
+            (joined
+              (portRef (member Q 21))
+              (portRef DO32 (instanceRef pdp_ram_0_0_0))))
+          (net dataout13
+            (joined
+              (portRef (member Q 22))
+              (portRef DO31 (instanceRef pdp_ram_0_0_0))))
+          (net dataout12
+            (joined
+              (portRef (member Q 23))
+              (portRef DO30 (instanceRef pdp_ram_0_0_0))))
+          (net dataout11
+            (joined
+              (portRef (member Q 24))
+              (portRef DO29 (instanceRef pdp_ram_0_0_0))))
+          (net dataout10
+            (joined
+              (portRef (member Q 25))
+              (portRef DO28 (instanceRef pdp_ram_0_0_0))))
+          (net dataout9
+            (joined
+              (portRef (member Q 26))
+              (portRef DO27 (instanceRef pdp_ram_0_0_0))))
+          (net dataout8
+            (joined
+              (portRef (member Q 27))
+              (portRef DO26 (instanceRef pdp_ram_0_0_0))))
+          (net dataout7
+            (joined
+              (portRef (member Q 28))
+              (portRef DO25 (instanceRef pdp_ram_0_0_0))))
+          (net dataout6
+            (joined
+              (portRef (member Q 29))
+              (portRef DO24 (instanceRef pdp_ram_0_0_0))))
+          (net dataout5
+            (joined
+              (portRef (member Q 30))
+              (portRef DO23 (instanceRef pdp_ram_0_0_0))))
+          (net dataout4
+            (joined
+              (portRef (member Q 31))
+              (portRef DO22 (instanceRef pdp_ram_0_0_0))))
+          (net dataout3
+            (joined
+              (portRef (member Q 32))
+              (portRef DO21 (instanceRef pdp_ram_0_0_0))))
+          (net dataout2
+            (joined
+              (portRef (member Q 33))
+              (portRef DO20 (instanceRef pdp_ram_0_0_0))))
+          (net dataout1
+            (joined
+              (portRef (member Q 34))
+              (portRef DO19 (instanceRef pdp_ram_0_0_0))))
+          (net dataout0
+            (joined
+              (portRef (member Q 35))
+              (portRef DO18 (instanceRef pdp_ram_0_0_0))))
+          (net AmFullThresh8
+            (joined
+              (portRef (member AmFullThresh 0))
+              (portRef B0 (instanceRef af_set_cmp_4))))
+          (net AmFullThresh7
+            (joined
+              (portRef (member AmFullThresh 1))
+              (portRef B1 (instanceRef af_set_cmp_3))))
+          (net AmFullThresh6
+            (joined
+              (portRef (member AmFullThresh 2))
+              (portRef B0 (instanceRef af_set_cmp_3))))
+          (net AmFullThresh5
+            (joined
+              (portRef (member AmFullThresh 3))
+              (portRef B1 (instanceRef af_set_cmp_2))))
+          (net AmFullThresh4
+            (joined
+              (portRef (member AmFullThresh 4))
+              (portRef B0 (instanceRef af_set_cmp_2))))
+          (net AmFullThresh3
+            (joined
+              (portRef (member AmFullThresh 5))
+              (portRef B1 (instanceRef af_set_cmp_1))))
+          (net AmFullThresh2
+            (joined
+              (portRef (member AmFullThresh 6))
+              (portRef B0 (instanceRef af_set_cmp_1))))
+          (net AmFullThresh1
+            (joined
+              (portRef (member AmFullThresh 7))
+              (portRef B1 (instanceRef af_set_cmp_0))))
+          (net AmFullThresh0
+            (joined
+              (portRef (member AmFullThresh 8))
+              (portRef B0 (instanceRef af_set_cmp_0))))
+          (net reset
+            (joined
+              (portRef Reset)
+              (portRef RST (instanceRef pdp_ram_0_0_0))
+              (portRef CD (instanceRef FF_62))
+              (portRef CD (instanceRef FF_61))
+              (portRef CD (instanceRef FF_60))
+              (portRef CD (instanceRef FF_59))
+              (portRef CD (instanceRef FF_58))
+              (portRef CD (instanceRef FF_57))
+              (portRef CD (instanceRef FF_56))
+              (portRef CD (instanceRef FF_55))
+              (portRef CD (instanceRef FF_54))
+              (portRef CD (instanceRef FF_53))
+              (portRef PD (instanceRef FF_52))
+              (portRef CD (instanceRef FF_51))
+              (portRef PD (instanceRef FF_50))
+              (portRef CD (instanceRef FF_49))
+              (portRef CD (instanceRef FF_48))
+              (portRef CD (instanceRef FF_47))
+              (portRef CD (instanceRef FF_46))
+              (portRef CD (instanceRef FF_45))
+              (portRef CD (instanceRef FF_44))
+              (portRef CD (instanceRef FF_43))
+              (portRef CD (instanceRef FF_42))
+              (portRef CD (instanceRef FF_41))
+              (portRef PD (instanceRef FF_40))
+              (portRef CD (instanceRef FF_39))
+              (portRef CD (instanceRef FF_38))
+              (portRef CD (instanceRef FF_37))
+              (portRef CD (instanceRef FF_36))
+              (portRef CD (instanceRef FF_35))
+              (portRef CD (instanceRef FF_34))
+              (portRef CD (instanceRef FF_33))
+              (portRef CD (instanceRef FF_32))
+              (portRef CD (instanceRef FF_31))
+              (portRef CD (instanceRef FF_30))
+              (portRef CD (instanceRef FF_29))
+              (portRef CD (instanceRef FF_28))
+              (portRef CD (instanceRef FF_27))
+              (portRef CD (instanceRef FF_26))
+              (portRef CD (instanceRef FF_25))
+              (portRef CD (instanceRef FF_24))
+              (portRef CD (instanceRef FF_23))
+              (portRef CD (instanceRef FF_22))
+              (portRef CD (instanceRef FF_21))
+              (portRef CD (instanceRef FF_20))
+              (portRef CD (instanceRef FF_19))
+              (portRef CD (instanceRef FF_18))
+              (portRef CD (instanceRef FF_17))
+              (portRef CD (instanceRef FF_16))
+              (portRef CD (instanceRef FF_15))
+              (portRef CD (instanceRef FF_14))
+              (portRef CD (instanceRef FF_13))
+              (portRef CD (instanceRef FF_12))
+              (portRef CD (instanceRef FF_11))
+              (portRef CD (instanceRef FF_10))
+              (portRef CD (instanceRef FF_9))
+              (portRef CD (instanceRef FF_8))
+              (portRef CD (instanceRef FF_7))
+              (portRef CD (instanceRef FF_6))
+              (portRef CD (instanceRef FF_5))
+              (portRef CD (instanceRef FF_4))
+              (portRef CD (instanceRef FF_3))
+              (portRef CD (instanceRef FF_2))
+              (portRef CD (instanceRef FF_1))
+              (portRef CD (instanceRef FF_0))))
+          (net rden
+            (joined
+              (portRef RdEn)
+              (portRef A (instanceRef AND2_t4))))
+          (net wren
+            (joined
+              (portRef WrEn)
+              (portRef A (instanceRef AND2_t5))))
+          (net clk
+            (joined
+              (portRef Clock)
+              (portRef CLKR (instanceRef pdp_ram_0_0_0))
+              (portRef CLKW (instanceRef pdp_ram_0_0_0))
+              (portRef CK (instanceRef FF_62))
+              (portRef CK (instanceRef FF_61))
+              (portRef CK (instanceRef FF_60))
+              (portRef CK (instanceRef FF_59))
+              (portRef CK (instanceRef FF_58))
+              (portRef CK (instanceRef FF_57))
+              (portRef CK (instanceRef FF_56))
+              (portRef CK (instanceRef FF_55))
+              (portRef CK (instanceRef FF_54))
+              (portRef CK (instanceRef FF_53))
+              (portRef CK (instanceRef FF_52))
+              (portRef CK (instanceRef FF_51))
+              (portRef CK (instanceRef FF_50))
+              (portRef CK (instanceRef FF_49))
+              (portRef CK (instanceRef FF_48))
+              (portRef CK (instanceRef FF_47))
+              (portRef CK (instanceRef FF_46))
+              (portRef CK (instanceRef FF_45))
+              (portRef CK (instanceRef FF_44))
+              (portRef CK (instanceRef FF_43))
+              (portRef CK (instanceRef FF_42))
+              (portRef CK (instanceRef FF_41))
+              (portRef CK (instanceRef FF_40))
+              (portRef CK (instanceRef FF_39))
+              (portRef CK (instanceRef FF_38))
+              (portRef CK (instanceRef FF_37))
+              (portRef CK (instanceRef FF_36))
+              (portRef CK (instanceRef FF_35))
+              (portRef CK (instanceRef FF_34))
+              (portRef CK (instanceRef FF_33))
+              (portRef CK (instanceRef FF_32))
+              (portRef CK (instanceRef FF_31))
+              (portRef CK (instanceRef FF_30))
+              (portRef CK (instanceRef FF_29))
+              (portRef CK (instanceRef FF_28))
+              (portRef CK (instanceRef FF_27))
+              (portRef CK (instanceRef FF_26))
+              (portRef CK (instanceRef FF_25))
+              (portRef CK (instanceRef FF_24))
+              (portRef CK (instanceRef FF_23))
+              (portRef CK (instanceRef FF_22))
+              (portRef CK (instanceRef FF_21))
+              (portRef CK (instanceRef FF_20))
+              (portRef CK (instanceRef FF_19))
+              (portRef CK (instanceRef FF_18))
+              (portRef CK (instanceRef FF_17))
+              (portRef CK (instanceRef FF_16))
+              (portRef CK (instanceRef FF_15))
+              (portRef CK (instanceRef FF_14))
+              (portRef CK (instanceRef FF_13))
+              (portRef CK (instanceRef FF_12))
+              (portRef CK (instanceRef FF_11))
+              (portRef CK (instanceRef FF_10))
+              (portRef CK (instanceRef FF_9))
+              (portRef CK (instanceRef FF_8))
+              (portRef CK (instanceRef FF_7))
+              (portRef CK (instanceRef FF_6))
+              (portRef CK (instanceRef FF_5))
+              (portRef CK (instanceRef FF_4))
+              (portRef CK (instanceRef FF_3))
+              (portRef CK (instanceRef FF_2))
+              (portRef CK (instanceRef FF_1))
+              (portRef CK (instanceRef FF_0))))
+          (net datain35
+            (joined
+              (portRef (member Data 0))
+              (portRef DI35 (instanceRef pdp_ram_0_0_0))))
+          (net datain34
+            (joined
+              (portRef (member Data 1))
+              (portRef DI34 (instanceRef pdp_ram_0_0_0))))
+          (net datain33
+            (joined
+              (portRef (member Data 2))
+              (portRef DI33 (instanceRef pdp_ram_0_0_0))))
+          (net datain32
+            (joined
+              (portRef (member Data 3))
+              (portRef DI32 (instanceRef pdp_ram_0_0_0))))
+          (net datain31
+            (joined
+              (portRef (member Data 4))
+              (portRef DI31 (instanceRef pdp_ram_0_0_0))))
+          (net datain30
+            (joined
+              (portRef (member Data 5))
+              (portRef DI30 (instanceRef pdp_ram_0_0_0))))
+          (net datain29
+            (joined
+              (portRef (member Data 6))
+              (portRef DI29 (instanceRef pdp_ram_0_0_0))))
+          (net datain28
+            (joined
+              (portRef (member Data 7))
+              (portRef DI28 (instanceRef pdp_ram_0_0_0))))
+          (net datain27
+            (joined
+              (portRef (member Data 8))
+              (portRef DI27 (instanceRef pdp_ram_0_0_0))))
+          (net datain26
+            (joined
+              (portRef (member Data 9))
+              (portRef DI26 (instanceRef pdp_ram_0_0_0))))
+          (net datain25
+            (joined
+              (portRef (member Data 10))
+              (portRef DI25 (instanceRef pdp_ram_0_0_0))))
+          (net datain24
+            (joined
+              (portRef (member Data 11))
+              (portRef DI24 (instanceRef pdp_ram_0_0_0))))
+          (net datain23
+            (joined
+              (portRef (member Data 12))
+              (portRef DI23 (instanceRef pdp_ram_0_0_0))))
+          (net datain22
+            (joined
+              (portRef (member Data 13))
+              (portRef DI22 (instanceRef pdp_ram_0_0_0))))
+          (net datain21
+            (joined
+              (portRef (member Data 14))
+              (portRef DI21 (instanceRef pdp_ram_0_0_0))))
+          (net datain20
+            (joined
+              (portRef (member Data 15))
+              (portRef DI20 (instanceRef pdp_ram_0_0_0))))
+          (net datain19
+            (joined
+              (portRef (member Data 16))
+              (portRef DI19 (instanceRef pdp_ram_0_0_0))))
+          (net datain18
+            (joined
+              (portRef (member Data 17))
+              (portRef DI18 (instanceRef pdp_ram_0_0_0))))
+          (net datain17
+            (joined
+              (portRef (member Data 18))
+              (portRef DI17 (instanceRef pdp_ram_0_0_0))))
+          (net datain16
+            (joined
+              (portRef (member Data 19))
+              (portRef DI16 (instanceRef pdp_ram_0_0_0))))
+          (net datain15
+            (joined
+              (portRef (member Data 20))
+              (portRef DI15 (instanceRef pdp_ram_0_0_0))))
+          (net datain14
+            (joined
+              (portRef (member Data 21))
+              (portRef DI14 (instanceRef pdp_ram_0_0_0))))
+          (net datain13
+            (joined
+              (portRef (member Data 22))
+              (portRef DI13 (instanceRef pdp_ram_0_0_0))))
+          (net datain12
+            (joined
+              (portRef (member Data 23))
+              (portRef DI12 (instanceRef pdp_ram_0_0_0))))
+          (net datain11
+            (joined
+              (portRef (member Data 24))
+              (portRef DI11 (instanceRef pdp_ram_0_0_0))))
+          (net datain10
+            (joined
+              (portRef (member Data 25))
+              (portRef DI10 (instanceRef pdp_ram_0_0_0))))
+          (net datain9
+            (joined
+              (portRef (member Data 26))
+              (portRef DI9 (instanceRef pdp_ram_0_0_0))))
+          (net datain8
+            (joined
+              (portRef (member Data 27))
+              (portRef DI8 (instanceRef pdp_ram_0_0_0))))
+          (net datain7
+            (joined
+              (portRef (member Data 28))
+              (portRef DI7 (instanceRef pdp_ram_0_0_0))))
+          (net datain6
+            (joined
+              (portRef (member Data 29))
+              (portRef DI6 (instanceRef pdp_ram_0_0_0))))
+          (net datain5
+            (joined
+              (portRef (member Data 30))
+              (portRef DI5 (instanceRef pdp_ram_0_0_0))))
+          (net datain4
+            (joined
+              (portRef (member Data 31))
+              (portRef DI4 (instanceRef pdp_ram_0_0_0))))
+          (net datain3
+            (joined
+              (portRef (member Data 32))
+              (portRef DI3 (instanceRef pdp_ram_0_0_0))))
+          (net datain2
+            (joined
+              (portRef (member Data 33))
+              (portRef DI2 (instanceRef pdp_ram_0_0_0))))
+          (net datain1
+            (joined
+              (portRef (member Data 34))
+              (portRef DI1 (instanceRef pdp_ram_0_0_0))))
+          (net datain0
+            (joined
+              (portRef (member Data 35))
+              (portRef DI0 (instanceRef pdp_ram_0_0_0))))))))
+  (design fifo_36x512_oreg
+    (cellRef fifo_36x512_oreg
+      (libraryRef ORCLIB)))
+)

diff --git a/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.fdc b/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.fdc
new file mode 100644 (file)
index 0000000..6fbcac9
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.fdc
@@ -0,0 +1,2 @@
+###==== Start Configuration
+

diff --git a/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.lpc b/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.lpc
new file mode 100644 (file)
index 0000000..c0b44aa
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.lpc
@@ -0,0 +1,50 @@
+[Device]
+Family=ecp5um
+PartType=LFE5UM-85F
+PartName=LFE5UM-85F-8MG285C
+SpeedGrade=8
+Package=CSFBGA285
+OperatingCondition=COM
+Status=C
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO
+CoreRevision=5.0
+ModuleName=fifo_36x512_oreg
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=03/18/2015
+Time=14:40:02
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=512
+Width=36
+regout=1
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=1
+PfMode=Dynamic - Single Threshold
+PfAssert=508
+PfDeassert=506
+Reset=Async
+Reset1=Sync
+RDataCount=1
+EnECC=0
+EnFWFT=0
+
+[Command]
+cmd_line= -w -n fifo_36x512_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 512 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill

diff --git a/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.ngd b/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.ngd
new file mode 100644 (file)
index 0000000..22ea4f0
Binary files /dev/null and b/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.ngd differ

diff --git a/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.ngo b/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.ngo
new file mode 100644 (file)
index 0000000..5360acc
Binary files /dev/null and b/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.ngo differ

diff --git a/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.vhd b/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.vhd
new file mode 100644 (file)
index 0000000..c76aa9d
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.vhd
@@ -0,0 +1,949 @@
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80
+-- Module  Version: 5.0
+--/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x512_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 512 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.fdc 
+
+-- Wed Mar 18 14:40:04 2015
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity fifo_36x512_oreg is
+    port (
+        Data: in  std_logic_vector(35 downto 0); 
+        Clock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        AmFullThresh: in  std_logic_vector(8 downto 0); 
+        Q: out  std_logic_vector(35 downto 0); 
+        WCNT: out  std_logic_vector(9 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic; 
+        AlmostFull: out  std_logic);
+end fifo_36x512_oreg;
+
+architecture Structure of fifo_36x512_oreg is
+
+    -- internal signal declarations
+    signal invout_2: std_logic;
+    signal invout_1: std_logic;
+    signal rden_i_inv: std_logic;
+    signal invout_0: std_logic;
+    signal r_nw: std_logic;
+    signal fcnt_en: std_logic;
+    signal empty_i: std_logic;
+    signal empty_d: std_logic;
+    signal full_i: std_logic;
+    signal full_d: std_logic;
+    signal wptr_0: std_logic;
+    signal wptr_1: std_logic;
+    signal wptr_2: std_logic;
+    signal wptr_3: std_logic;
+    signal wptr_4: std_logic;
+    signal wptr_5: std_logic;
+    signal wptr_6: std_logic;
+    signal wptr_7: std_logic;
+    signal wptr_8: std_logic;
+    signal wptr_9: std_logic;
+    signal rptr_9: std_logic;
+    signal ifcount_0: std_logic;
+    signal ifcount_1: std_logic;
+    signal bdcnt_bctr_ci: std_logic;
+    signal ifcount_2: std_logic;
+    signal ifcount_3: std_logic;
+    signal co0: std_logic;
+    signal ifcount_4: std_logic;
+    signal ifcount_5: std_logic;
+    signal co1: std_logic;
+    signal ifcount_6: std_logic;
+    signal ifcount_7: std_logic;
+    signal co2: std_logic;
+    signal ifcount_8: std_logic;
+    signal ifcount_9: std_logic;
+    signal co4: std_logic;
+    signal co3: std_logic;
+    signal cmp_ci: std_logic;
+    signal rden_i: std_logic;
+    signal co0_1: std_logic;
+    signal co1_1: std_logic;
+    signal co2_1: std_logic;
+    signal co3_1: std_logic;
+    signal cmp_le_1: std_logic;
+    signal cmp_le_1_c: std_logic;
+    signal cmp_ci_1: std_logic;
+    signal fcount_0: std_logic;
+    signal fcount_1: std_logic;
+    signal co0_2: std_logic;
+    signal fcount_2: std_logic;
+    signal fcount_3: std_logic;
+    signal co1_2: std_logic;
+    signal fcount_4: std_logic;
+    signal fcount_5: std_logic;
+    signal co2_2: std_logic;
+    signal fcount_6: std_logic;
+    signal fcount_7: std_logic;
+    signal co3_2: std_logic;
+    signal wren_i_inv: std_logic;
+    signal fcount_8: std_logic;
+    signal fcount_9: std_logic;
+    signal cmp_ge_d1: std_logic;
+    signal cmp_ge_d1_c: std_logic;
+    signal iwcount_0: std_logic;
+    signal iwcount_1: std_logic;
+    signal w_ctr_ci: std_logic;
+    signal iwcount_2: std_logic;
+    signal iwcount_3: std_logic;
+    signal co0_3: std_logic;
+    signal iwcount_4: std_logic;
+    signal iwcount_5: std_logic;
+    signal co1_3: std_logic;
+    signal iwcount_6: std_logic;
+    signal iwcount_7: std_logic;
+    signal co2_3: std_logic;
+    signal iwcount_8: std_logic;
+    signal iwcount_9: std_logic;
+    signal co4_1: std_logic;
+    signal co3_3: std_logic;
+    signal wcount_9: std_logic;
+    signal ircount_0: std_logic;
+    signal ircount_1: std_logic;
+    signal r_ctr_ci: std_logic;
+    signal rcount_0: std_logic;
+    signal rcount_1: std_logic;
+    signal ircount_2: std_logic;
+    signal ircount_3: std_logic;
+    signal co0_4: std_logic;
+    signal rcount_2: std_logic;
+    signal rcount_3: std_logic;
+    signal ircount_4: std_logic;
+    signal ircount_5: std_logic;
+    signal co1_4: std_logic;
+    signal rcount_4: std_logic;
+    signal rcount_5: std_logic;
+    signal ircount_6: std_logic;
+    signal ircount_7: std_logic;
+    signal co2_4: std_logic;
+    signal rcount_6: std_logic;
+    signal rcount_7: std_logic;
+    signal ircount_8: std_logic;
+    signal ircount_9: std_logic;
+    signal co4_2: std_logic;
+    signal co3_4: std_logic;
+    signal rcount_8: std_logic;
+    signal rcount_9: std_logic;
+    signal wcnt_sub_0: std_logic;
+    signal rptr_0: std_logic;
+    signal cnt_con_inv: std_logic;
+    signal wcount_0: std_logic;
+    signal cnt_con: std_logic;
+    signal precin: std_logic;
+    signal wcnt_sub_1: std_logic;
+    signal wcnt_sub_2: std_logic;
+    signal rptr_2: std_logic;
+    signal rptr_1: std_logic;
+    signal wcount_2: std_logic;
+    signal wcount_1: std_logic;
+    signal co0_5: std_logic;
+    signal wcnt_sub_3: std_logic;
+    signal wcnt_sub_4: std_logic;
+    signal rptr_4: std_logic;
+    signal rptr_3: std_logic;
+    signal wcount_4: std_logic;
+    signal wcount_3: std_logic;
+    signal co1_5: std_logic;
+    signal wcnt_sub_5: std_logic;
+    signal wcnt_sub_6: std_logic;
+    signal rptr_6: std_logic;
+    signal rptr_5: std_logic;
+    signal wcount_6: std_logic;
+    signal wcount_5: std_logic;
+    signal co2_5: std_logic;
+    signal wcnt_sub_7: std_logic;
+    signal wcnt_sub_8: std_logic;
+    signal rptr_8: std_logic;
+    signal rptr_7: std_logic;
+    signal wcount_8: std_logic;
+    signal wcount_7: std_logic;
+    signal co3_5: std_logic;
+    signal wcnt_sub_9: std_logic;
+    signal wcnt_sub_msb: std_logic;
+    signal co4_3: std_logic;
+    signal wren_i: std_logic;
+    signal cmp_ci_2: std_logic;
+    signal wcnt_reg_0: std_logic;
+    signal wcnt_reg_1: std_logic;
+    signal co0_6: std_logic;
+    signal wcnt_reg_2: std_logic;
+    signal wcnt_reg_3: std_logic;
+    signal co1_6: std_logic;
+    signal wcnt_reg_4: std_logic;
+    signal wcnt_reg_5: std_logic;
+    signal co2_6: std_logic;
+    signal wcnt_reg_6: std_logic;
+    signal wcnt_reg_7: std_logic;
+    signal co3_6: std_logic;
+    signal wcnt_reg_8: std_logic;
+    signal wcnt_reg_9: std_logic;
+    signal af_set: std_logic;
+    signal scuba_vhi: std_logic;
+    signal scuba_vlo: std_logic;
+    signal af_set_c: std_logic;
+
+    attribute MEM_LPC_FILE : string; 
+    attribute MEM_INIT_FILE : string; 
+    attribute GSR : string; 
+    attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_36x512_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
+    attribute GSR of FF_62 : label is "ENABLED";
+    attribute GSR of FF_61 : label is "ENABLED";
+    attribute GSR of FF_60 : label is "ENABLED";
+    attribute GSR of FF_59 : label is "ENABLED";
+    attribute GSR of FF_58 : label is "ENABLED";
+    attribute GSR of FF_57 : label is "ENABLED";
+    attribute GSR of FF_56 : label is "ENABLED";
+    attribute GSR of FF_55 : label is "ENABLED";
+    attribute GSR of FF_54 : label is "ENABLED";
+    attribute GSR of FF_53 : label is "ENABLED";
+    attribute GSR of FF_52 : label is "ENABLED";
+    attribute GSR of FF_51 : label is "ENABLED";
+    attribute GSR of FF_50 : label is "ENABLED";
+    attribute GSR of FF_49 : label is "ENABLED";
+    attribute GSR of FF_48 : label is "ENABLED";
+    attribute GSR of FF_47 : label is "ENABLED";
+    attribute GSR of FF_46 : label is "ENABLED";
+    attribute GSR of FF_45 : label is "ENABLED";
+    attribute GSR of FF_44 : label is "ENABLED";
+    attribute GSR of FF_43 : label is "ENABLED";
+    attribute GSR of FF_42 : label is "ENABLED";
+    attribute GSR of FF_41 : label is "ENABLED";
+    attribute GSR of FF_40 : label is "ENABLED";
+    attribute GSR of FF_39 : label is "ENABLED";
+    attribute GSR of FF_38 : label is "ENABLED";
+    attribute GSR of FF_37 : label is "ENABLED";
+    attribute GSR of FF_36 : label is "ENABLED";
+    attribute GSR of FF_35 : label is "ENABLED";
+    attribute GSR of FF_34 : label is "ENABLED";
+    attribute GSR of FF_33 : label is "ENABLED";
+    attribute GSR of FF_32 : label is "ENABLED";
+    attribute GSR of FF_31 : label is "ENABLED";
+    attribute GSR of FF_30 : label is "ENABLED";
+    attribute GSR of FF_29 : label is "ENABLED";
+    attribute GSR of FF_28 : label is "ENABLED";
+    attribute GSR of FF_27 : label is "ENABLED";
+    attribute GSR of FF_26 : label is "ENABLED";
+    attribute GSR of FF_25 : label is "ENABLED";
+    attribute GSR of FF_24 : label is "ENABLED";
+    attribute GSR of FF_23 : label is "ENABLED";
+    attribute GSR of FF_22 : label is "ENABLED";
+    attribute GSR of FF_21 : label is "ENABLED";
+    attribute GSR of FF_20 : label is "ENABLED";
+    attribute GSR of FF_19 : label is "ENABLED";
+    attribute GSR of FF_18 : label is "ENABLED";
+    attribute GSR of FF_17 : label is "ENABLED";
+    attribute GSR of FF_16 : label is "ENABLED";
+    attribute GSR of FF_15 : label is "ENABLED";
+    attribute GSR of FF_14 : label is "ENABLED";
+    attribute GSR of FF_13 : label is "ENABLED";
+    attribute GSR of FF_12 : label is "ENABLED";
+    attribute GSR of FF_11 : label is "ENABLED";
+    attribute GSR of FF_10 : label is "ENABLED";
+    attribute GSR of FF_9 : label is "ENABLED";
+    attribute GSR of FF_8 : label is "ENABLED";
+    attribute GSR of FF_7 : label is "ENABLED";
+    attribute GSR of FF_6 : label is "ENABLED";
+    attribute GSR of FF_5 : label is "ENABLED";
+    attribute GSR of FF_4 : label is "ENABLED";
+    attribute GSR of FF_3 : label is "ENABLED";
+    attribute GSR of FF_2 : label is "ENABLED";
+    attribute GSR of FF_1 : label is "ENABLED";
+    attribute GSR of FF_0 : label is "ENABLED";
+    attribute syn_keep : boolean;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    AND2_t5: AND2
+        port map (A=>WrEn, B=>invout_2, Z=>wren_i);
+
+    INV_5: INV
+        port map (A=>full_i, Z=>invout_2);
+
+    AND2_t4: AND2
+        port map (A=>RdEn, B=>invout_1, Z=>rden_i);
+
+    INV_4: INV
+        port map (A=>empty_i, Z=>invout_1);
+
+    AND2_t3: AND2
+        port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
+
+    XOR2_t2: XOR2
+        port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
+
+    INV_3: INV
+        port map (A=>rden_i, Z=>rden_i_inv);
+
+    INV_2: INV
+        port map (A=>wren_i, Z=>wren_i_inv);
+
+    LUT4_1: ROM16X1A
+        generic map (initval=> X"3232")
+        port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, 
+            AD0=>empty_i, DO0=>empty_d);
+
+    LUT4_0: ROM16X1A
+        generic map (initval=> X"3232")
+        port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, 
+            AD0=>full_i, DO0=>full_d);
+
+    AND2_t1: AND2
+        port map (A=>rden_i, B=>invout_0, Z=>r_nw);
+
+    INV_1: INV
+        port map (A=>wren_i, Z=>invout_0);
+
+    XOR2_t0: XOR2
+        port map (A=>wcount_9, B=>rptr_9, Z=>wcnt_sub_msb);
+
+    INV_0: INV
+        port map (A=>cnt_con, Z=>cnt_con_inv);
+
+    pdp_ram_0_0_0: PDPW16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "ENABLED", 
+        RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=>  36, 
+        DATA_WIDTH_W=>  36)
+        port map (DI35=>Data(35), DI34=>Data(34), DI33=>Data(33), 
+            DI32=>Data(32), DI31=>Data(31), DI30=>Data(30), 
+            DI29=>Data(29), DI28=>Data(28), DI27=>Data(27), 
+            DI26=>Data(26), DI25=>Data(25), DI24=>Data(24), 
+            DI23=>Data(23), DI22=>Data(22), DI21=>Data(21), 
+            DI20=>Data(20), DI19=>Data(19), DI18=>Data(18), 
+            DI17=>Data(17), DI16=>Data(16), DI15=>Data(15), 
+            DI14=>Data(14), DI13=>Data(13), DI12=>Data(12), 
+            DI11=>Data(11), DI10=>Data(10), DI9=>Data(9), DI8=>Data(8), 
+            DI7=>Data(7), DI6=>Data(6), DI5=>Data(5), DI4=>Data(4), 
+            DI3=>Data(3), DI2=>Data(2), DI1=>Data(1), DI0=>Data(0), 
+            ADW8=>wptr_8, ADW7=>wptr_7, ADW6=>wptr_6, ADW5=>wptr_5, 
+            ADW4=>wptr_4, ADW3=>wptr_3, ADW2=>wptr_2, ADW1=>wptr_1, 
+            ADW0=>wptr_0, BE3=>scuba_vhi, BE2=>scuba_vhi, BE1=>scuba_vhi, 
+            BE0=>scuba_vhi, CEW=>wren_i, CLKW=>Clock, CSW2=>scuba_vlo, 
+            CSW1=>scuba_vlo, CSW0=>scuba_vhi, ADR13=>rptr_8, 
+            ADR12=>rptr_7, ADR11=>rptr_6, ADR10=>rptr_5, ADR9=>rptr_4, 
+            ADR8=>rptr_3, ADR7=>rptr_2, ADR6=>rptr_1, ADR5=>rptr_0, 
+            ADR4=>scuba_vlo, ADR3=>scuba_vlo, ADR2=>scuba_vlo, 
+            ADR1=>scuba_vlo, ADR0=>scuba_vlo, CER=>scuba_vhi, 
+            OCER=>scuba_vhi, CLKR=>Clock, CSR2=>scuba_vlo, 
+            CSR1=>scuba_vlo, CSR0=>rden_i, RST=>Reset, DO35=>Q(17), 
+            DO34=>Q(16), DO33=>Q(15), DO32=>Q(14), DO31=>Q(13), 
+            DO30=>Q(12), DO29=>Q(11), DO28=>Q(10), DO27=>Q(9), 
+            DO26=>Q(8), DO25=>Q(7), DO24=>Q(6), DO23=>Q(5), DO22=>Q(4), 
+            DO21=>Q(3), DO20=>Q(2), DO19=>Q(1), DO18=>Q(0), DO17=>Q(35), 
+            DO16=>Q(34), DO15=>Q(33), DO14=>Q(32), DO13=>Q(31), 
+            DO12=>Q(30), DO11=>Q(29), DO10=>Q(28), DO9=>Q(27), 
+            DO8=>Q(26), DO7=>Q(25), DO6=>Q(24), DO5=>Q(23), DO4=>Q(22), 
+            DO3=>Q(21), DO2=>Q(20), DO1=>Q(19), DO0=>Q(18));
+
+    FF_62: FD1P3DX
+        port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_0);
+
+    FF_61: FD1P3DX
+        port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_1);
+
+    FF_60: FD1P3DX
+        port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_2);
+
+    FF_59: FD1P3DX
+        port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_3);
+
+    FF_58: FD1P3DX
+        port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_4);
+
+    FF_57: FD1P3DX
+        port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_5);
+
+    FF_56: FD1P3DX
+        port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_6);
+
+    FF_55: FD1P3DX
+        port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_7);
+
+    FF_54: FD1P3DX
+        port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_8);
+
+    FF_53: FD1P3DX
+        port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_9);
+
+    FF_52: FD1S3BX
+        port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
+
+    FF_51: FD1S3DX
+        port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
+
+    FF_50: FD1P3BX
+        port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset, 
+            Q=>wcount_0);
+
+    FF_49: FD1P3DX
+        port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_1);
+
+    FF_48: FD1P3DX
+        port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_2);
+
+    FF_47: FD1P3DX
+        port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_3);
+
+    FF_46: FD1P3DX
+        port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_4);
+
+    FF_45: FD1P3DX
+        port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_5);
+
+    FF_44: FD1P3DX
+        port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_6);
+
+    FF_43: FD1P3DX
+        port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_7);
+
+    FF_42: FD1P3DX
+        port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_8);
+
+    FF_41: FD1P3DX
+        port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_9);
+
+    FF_40: FD1P3BX
+        port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset, 
+            Q=>rcount_0);
+
+    FF_39: FD1P3DX
+        port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_1);
+
+    FF_38: FD1P3DX
+        port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_2);
+
+    FF_37: FD1P3DX
+        port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_3);
+
+    FF_36: FD1P3DX
+        port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_4);
+
+    FF_35: FD1P3DX
+        port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_5);
+
+    FF_34: FD1P3DX
+        port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_6);
+
+    FF_33: FD1P3DX
+        port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_7);
+
+    FF_32: FD1P3DX
+        port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_8);
+
+    FF_31: FD1P3DX
+        port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_9);
+
+    FF_30: FD1P3DX
+        port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_0);
+
+    FF_29: FD1P3DX
+        port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_1);
+
+    FF_28: FD1P3DX
+        port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_2);
+
+    FF_27: FD1P3DX
+        port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_3);
+
+    FF_26: FD1P3DX
+        port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_4);
+
+    FF_25: FD1P3DX
+        port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_5);
+
+    FF_24: FD1P3DX
+        port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_6);
+
+    FF_23: FD1P3DX
+        port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_7);
+
+    FF_22: FD1P3DX
+        port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_8);
+
+    FF_21: FD1P3DX
+        port map (D=>wcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_9);
+
+    FF_20: FD1P3DX
+        port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_0);
+
+    FF_19: FD1P3DX
+        port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_1);
+
+    FF_18: FD1P3DX
+        port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_2);
+
+    FF_17: FD1P3DX
+        port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_3);
+
+    FF_16: FD1P3DX
+        port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_4);
+
+    FF_15: FD1P3DX
+        port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_5);
+
+    FF_14: FD1P3DX
+        port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_6);
+
+    FF_13: FD1P3DX
+        port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_7);
+
+    FF_12: FD1P3DX
+        port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_8);
+
+    FF_11: FD1P3DX
+        port map (D=>rcount_9, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_9);
+
+    FF_10: FD1S3DX
+        port map (D=>wcnt_sub_0, CK=>Clock, CD=>Reset, Q=>wcnt_reg_0);
+
+    FF_9: FD1S3DX
+        port map (D=>wcnt_sub_1, CK=>Clock, CD=>Reset, Q=>wcnt_reg_1);
+
+    FF_8: FD1S3DX
+        port map (D=>wcnt_sub_2, CK=>Clock, CD=>Reset, Q=>wcnt_reg_2);
+
+    FF_7: FD1S3DX
+        port map (D=>wcnt_sub_3, CK=>Clock, CD=>Reset, Q=>wcnt_reg_3);
+
+    FF_6: FD1S3DX
+        port map (D=>wcnt_sub_4, CK=>Clock, CD=>Reset, Q=>wcnt_reg_4);
+
+    FF_5: FD1S3DX
+        port map (D=>wcnt_sub_5, CK=>Clock, CD=>Reset, Q=>wcnt_reg_5);
+
+    FF_4: FD1S3DX
+        port map (D=>wcnt_sub_6, CK=>Clock, CD=>Reset, Q=>wcnt_reg_6);
+
+    FF_3: FD1S3DX
+        port map (D=>wcnt_sub_7, CK=>Clock, CD=>Reset, Q=>wcnt_reg_7);
+
+    FF_2: FD1S3DX
+        port map (D=>wcnt_sub_8, CK=>Clock, CD=>Reset, Q=>wcnt_reg_8);
+
+    FF_1: FD1S3DX
+        port map (D=>wcnt_sub_9, CK=>Clock, CD=>Reset, Q=>wcnt_reg_9);
+
+    FF_0: FD1S3DX
+        port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull);
+
+    bdcnt_bctr_cia: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>'X', S0=>open, S1=>open, COUT=>bdcnt_bctr_ci);
+
+    bdcnt_bctr_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_0, A1=>fcount_1, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>bdcnt_bctr_ci, S0=>ifcount_0, S1=>ifcount_1, COUT=>co0);
+
+    bdcnt_bctr_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co0, S0=>ifcount_2, S1=>ifcount_3, COUT=>co1);
+
+    bdcnt_bctr_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_4, A1=>fcount_5, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co1, S0=>ifcount_4, S1=>ifcount_5, COUT=>co2);
+
+    bdcnt_bctr_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_6, A1=>fcount_7, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co2, S0=>ifcount_6, S1=>ifcount_7, COUT=>co3);
+
+    bdcnt_bctr_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_8, A1=>fcount_9, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co3, S0=>ifcount_8, S1=>ifcount_9, COUT=>co4);
+
+    e_cmp_ci_a: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci);
+
+    e_cmp_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>rden_i, A1=>scuba_vlo, B0=>fcount_0, B1=>fcount_1, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>cmp_ci, S0=>open, S1=>open, COUT=>co0_1);
+
+    e_cmp_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_2, 
+            B1=>fcount_3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co0_1, S0=>open, S1=>open, COUT=>co1_1);
+
+    e_cmp_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_4, 
+            B1=>fcount_5, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co1_1, S0=>open, S1=>open, COUT=>co2_1);
+
+    e_cmp_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_6, 
+            B1=>fcount_7, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co2_1, S0=>open, S1=>open, COUT=>co3_1);
+
+    e_cmp_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_8, 
+            B1=>fcount_9, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co3_1, S0=>open, S1=>open, 
+            COUT=>cmp_le_1_c);
+
+    a0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>cmp_le_1_c, S0=>cmp_le_1, S1=>open, 
+            COUT=>open);
+
+    g_cmp_ci_a: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_1);
+
+    g_cmp_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>cmp_ci_1, S0=>open, S1=>open, COUT=>co0_2);
+
+    g_cmp_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co0_2, S0=>open, S1=>open, COUT=>co1_2);
+
+    g_cmp_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co1_2, S0=>open, S1=>open, COUT=>co2_2);
+
+    g_cmp_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co2_2, S0=>open, S1=>open, COUT=>co3_2);
+
+    g_cmp_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i_inv, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co3_2, S0=>open, S1=>open, COUT=>cmp_ge_d1_c);
+
+    a1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>cmp_ge_d1_c, S0=>cmp_ge_d1, S1=>open, 
+            COUT=>open);
+
+    w_ctr_cia: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>w_ctr_ci);
+
+    w_ctr_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>w_ctr_ci, S0=>iwcount_0, S1=>iwcount_1, 
+            COUT=>co0_3);
+
+    w_ctr_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_2, A1=>wcount_3, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co0_3, S0=>iwcount_2, S1=>iwcount_3, 
+            COUT=>co1_3);
+
+    w_ctr_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_4, A1=>wcount_5, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co1_3, S0=>iwcount_4, S1=>iwcount_5, 
+            COUT=>co2_3);
+
+    w_ctr_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_6, A1=>wcount_7, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co2_3, S0=>iwcount_6, S1=>iwcount_7, 
+            COUT=>co3_3);
+
+    w_ctr_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_8, A1=>wcount_9, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co3_3, S0=>iwcount_8, S1=>iwcount_9, 
+            COUT=>co4_1);
+
+    r_ctr_cia: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>r_ctr_ci);
+
+    r_ctr_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>r_ctr_ci, S0=>ircount_0, S1=>ircount_1, 
+            COUT=>co0_4);
+
+    r_ctr_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_2, A1=>rcount_3, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co0_4, S0=>ircount_2, S1=>ircount_3, 
+            COUT=>co1_4);
+
+    r_ctr_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_4, A1=>rcount_5, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co1_4, S0=>ircount_4, S1=>ircount_5, 
+            COUT=>co2_4);
+
+    r_ctr_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_6, A1=>rcount_7, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co2_4, S0=>ircount_6, S1=>ircount_7, 
+            COUT=>co3_4);
+
+    r_ctr_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_8, A1=>rcount_9, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co3_4, S0=>ircount_8, S1=>ircount_9, 
+            COUT=>co4_2);
+
+    precin_inst272: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"0000", 
+        INIT0=> X"0000")
+        port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>precin);
+
+    wcnt_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>cnt_con, A1=>wcount_0, B0=>cnt_con_inv, B1=>rptr_0, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>precin, S0=>open, S1=>wcnt_sub_0, COUT=>co0_5);
+
+    wcnt_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_1, A1=>wcount_2, B0=>rptr_1, B1=>rptr_2, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co0_5, S0=>wcnt_sub_1, S1=>wcnt_sub_2, COUT=>co1_5);
+
+    wcnt_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_3, A1=>wcount_4, B0=>rptr_3, B1=>rptr_4, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co1_5, S0=>wcnt_sub_3, S1=>wcnt_sub_4, COUT=>co2_5);
+
+    wcnt_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_5, A1=>wcount_6, B0=>rptr_5, B1=>rptr_6, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co2_5, S0=>wcnt_sub_5, S1=>wcnt_sub_6, COUT=>co3_5);
+
+    wcnt_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_7, A1=>wcount_8, B0=>rptr_7, B1=>rptr_8, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co3_5, S0=>wcnt_sub_7, S1=>wcnt_sub_8, COUT=>co4_3);
+
+    wcnt_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co4_3, S0=>wcnt_sub_9, S1=>open, 
+            COUT=>open);
+
+    af_set_cmp_ci_a: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_2);
+
+    af_set_cmp_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0), 
+            B1=>AmFullThresh(1), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>cmp_ci_2, S0=>open, 
+            S1=>open, COUT=>co0_6);
+
+    af_set_cmp_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2), 
+            B1=>AmFullThresh(3), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co0_6, S0=>open, S1=>open, 
+            COUT=>co1_6);
+
+    af_set_cmp_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4), 
+            B1=>AmFullThresh(5), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co1_6, S0=>open, S1=>open, 
+            COUT=>co2_6);
+
+    af_set_cmp_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6), 
+            B1=>AmFullThresh(7), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co2_6, S0=>open, S1=>open, 
+            COUT=>co3_6);
+
+    af_set_cmp_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8), 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co3_6, S0=>open, S1=>open, 
+            COUT=>af_set_c);
+
+    scuba_vhi_inst: VHI
+        port map (Z=>scuba_vhi);
+
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    a2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>af_set_c, S0=>af_set, S1=>open, 
+            COUT=>open);
+
+    WCNT(0) <= fcount_0;
+    WCNT(1) <= fcount_1;
+    WCNT(2) <= fcount_2;
+    WCNT(3) <= fcount_3;
+    WCNT(4) <= fcount_4;
+    WCNT(5) <= fcount_5;
+    WCNT(6) <= fcount_6;
+    WCNT(7) <= fcount_7;
+    WCNT(8) <= fcount_8;
+    WCNT(9) <= fcount_9;
+    Empty <= empty_i;
+    Full <= full_i;
+end Structure;

diff --git a/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg_ngd.asd b/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg_ngd.asd
new file mode 100644 (file)
index 0000000..c265c78
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg_ngd.asd
@@ -0,0 +1 @@
+[ActiveSupport NGD]

diff --git a/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.cst b/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.cst
new file mode 100644 (file)
index 0000000..a9a39ca
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.cst
@@ -0,0 +1,3 @@
+Date=03/18/2015
+Time=14:41:45
+

diff --git a/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.edn b/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.edn
new file mode 100644 (file)
index 0000000..9a9857b
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.edn
@@ -0,0 +1,6047 @@
+(edif fifo_36x8k_oreg
+  (edifVersion 2 0 0)
+  (edifLevel 0)
+  (keywordMap (keywordLevel 0))
+  (status
+    (written
+      (timestamp 2015 3 18 14 41 46)
+      (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80"))))
+      (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x8k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 8192 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.fdc ")
+  (library ORCLIB
+    (edifLevel 0)
+    (technology
+      (numberDefinition))
+    (cell CCU2C
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A0
+            (direction INPUT))
+          (port A1
+            (direction INPUT))
+          (port B0
+            (direction INPUT))
+          (port B1
+            (direction INPUT))
+          (port C0
+            (direction INPUT))
+          (port C1
+            (direction INPUT))
+          (port D0
+            (direction INPUT))
+          (port D1
+            (direction INPUT))
+          (port CIN
+            (direction INPUT))
+          (port S0
+            (direction OUTPUT))
+          (port S1
+            (direction OUTPUT))
+          (port COUT
+            (direction OUTPUT)))))
+    (cell AND2
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A
+            (direction INPUT))
+          (port B
+            (direction INPUT))
+          (port Z
+            (direction OUTPUT)))))
+    (cell FD1P3BX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port SP
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port PD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell FD1P3DX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port SP
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port CD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell FD1S3BX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port PD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell FD1S3DX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port CD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell INV
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A
+            (direction INPUT))
+          (port Z
+            (direction OUTPUT)))))
+    (cell MUX41
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D0
+            (direction INPUT))
+          (port D1
+            (direction INPUT))
+          (port D2
+            (direction INPUT))
+          (port D3
+            (direction INPUT))
+          (port SD1
+            (direction INPUT))
+          (port SD2
+            (direction INPUT))
+          (port Z
+            (direction OUTPUT)))))
+    (cell ROM16X1A
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port AD3
+            (direction INPUT))
+          (port AD2
+            (direction INPUT))
+          (port AD1
+            (direction INPUT))
+          (port AD0
+            (direction INPUT))
+          (port DO0
+            (direction OUTPUT)))))
+    (cell VHI
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port Z
+            (direction OUTPUT)))))
+    (cell VLO
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port Z
+            (direction OUTPUT)))))
+    (cell XOR2
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A
+            (direction INPUT))
+          (port B
+            (direction INPUT))
+          (port Z
+            (direction OUTPUT)))))
+    (cell DP16KD
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port DIA17
+            (direction INPUT))
+          (port DIA16
+            (direction INPUT))
+          (port DIA15
+            (direction INPUT))
+          (port DIA14
+            (direction INPUT))
+          (port DIA13
+            (direction INPUT))
+          (port DIA12
+            (direction INPUT))
+          (port DIA11
+            (direction INPUT))
+          (port DIA10
+            (direction INPUT))
+          (port DIA9
+            (direction INPUT))
+          (port DIA8
+            (direction INPUT))
+          (port DIA7
+            (direction INPUT))
+          (port DIA6
+            (direction INPUT))
+          (port DIA5
+            (direction INPUT))
+          (port DIA4
+            (direction INPUT))
+          (port DIA3
+            (direction INPUT))
+          (port DIA2
+            (direction INPUT))
+          (port DIA1
+            (direction INPUT))
+          (port DIA0
+            (direction INPUT))
+          (port ADA13
+            (direction INPUT))
+          (port ADA12
+            (direction INPUT))
+          (port ADA11
+            (direction INPUT))
+          (port ADA10
+            (direction INPUT))
+          (port ADA9
+            (direction INPUT))
+          (port ADA8
+            (direction INPUT))
+          (port ADA7
+            (direction INPUT))
+          (port ADA6
+            (direction INPUT))
+          (port ADA5
+            (direction INPUT))
+          (port ADA4
+            (direction INPUT))
+          (port ADA3
+            (direction INPUT))
+          (port ADA2
+            (direction INPUT))
+          (port ADA1
+            (direction INPUT))
+          (port ADA0
+            (direction INPUT))
+          (port CEA
+            (direction INPUT))
+          (port OCEA
+            (direction INPUT))
+          (port CLKA
+            (direction INPUT))
+          (port WEA
+            (direction INPUT))
+          (port CSA2
+            (direction INPUT))
+          (port CSA1
+            (direction INPUT))
+          (port CSA0
+            (direction INPUT))
+          (port RSTA
+            (direction INPUT))
+          (port DIB17
+            (direction INPUT))
+          (port DIB16
+            (direction INPUT))
+          (port DIB15
+            (direction INPUT))
+          (port DIB14
+            (direction INPUT))
+          (port DIB13
+            (direction INPUT))
+          (port DIB12
+            (direction INPUT))
+          (port DIB11
+            (direction INPUT))
+          (port DIB10
+            (direction INPUT))
+          (port DIB9
+            (direction INPUT))
+          (port DIB8
+            (direction INPUT))
+          (port DIB7
+            (direction INPUT))
+          (port DIB6
+            (direction INPUT))
+          (port DIB5
+            (direction INPUT))
+          (port DIB4
+            (direction INPUT))
+          (port DIB3
+            (direction INPUT))
+          (port DIB2
+            (direction INPUT))
+          (port DIB1
+            (direction INPUT))
+          (port DIB0
+            (direction INPUT))
+          (port ADB13
+            (direction INPUT))
+          (port ADB12
+            (direction INPUT))
+          (port ADB11
+            (direction INPUT))
+          (port ADB10
+            (direction INPUT))
+          (port ADB9
+            (direction INPUT))
+          (port ADB8
+            (direction INPUT))
+          (port ADB7
+            (direction INPUT))
+          (port ADB6
+            (direction INPUT))
+          (port ADB5
+            (direction INPUT))
+          (port ADB4
+            (direction INPUT))
+          (port ADB3
+            (direction INPUT))
+          (port ADB2
+            (direction INPUT))
+          (port ADB1
+            (direction INPUT))
+          (port ADB0
+            (direction INPUT))
+          (port CEB
+            (direction INPUT))
+          (port OCEB
+            (direction INPUT))
+          (port CLKB
+            (direction INPUT))
+          (port WEB
+            (direction INPUT))
+          (port CSB2
+            (direction INPUT))
+          (port CSB1
+            (direction INPUT))
+          (port CSB0
+            (direction INPUT))
+          (port RSTB
+            (direction INPUT))
+          (port DOA17
+            (direction OUTPUT))
+          (port DOA16
+            (direction OUTPUT))
+          (port DOA15
+            (direction OUTPUT))
+          (port DOA14
+            (direction OUTPUT))
+          (port DOA13
+            (direction OUTPUT))
+          (port DOA12
+            (direction OUTPUT))
+          (port DOA11
+            (direction OUTPUT))
+          (port DOA10
+            (direction OUTPUT))
+          (port DOA9
+            (direction OUTPUT))
+          (port DOA8
+            (direction OUTPUT))
+          (port DOA7
+            (direction OUTPUT))
+          (port DOA6
+            (direction OUTPUT))
+          (port DOA5
+            (direction OUTPUT))
+          (port DOA4
+            (direction OUTPUT))
+          (port DOA3
+            (direction OUTPUT))
+          (port DOA2
+            (direction OUTPUT))
+          (port DOA1
+            (direction OUTPUT))
+          (port DOA0
+            (direction OUTPUT))
+          (port DOB17
+            (direction OUTPUT))
+          (port DOB16
+            (direction OUTPUT))
+          (port DOB15
+            (direction OUTPUT))
+          (port DOB14
+            (direction OUTPUT))
+          (port DOB13
+            (direction OUTPUT))
+          (port DOB12
+            (direction OUTPUT))
+          (port DOB11
+            (direction OUTPUT))
+          (port DOB10
+            (direction OUTPUT))
+          (port DOB9
+            (direction OUTPUT))
+          (port DOB8
+            (direction OUTPUT))
+          (port DOB7
+            (direction OUTPUT))
+          (port DOB6
+            (direction OUTPUT))
+          (port DOB5
+            (direction OUTPUT))
+          (port DOB4
+            (direction OUTPUT))
+          (port DOB3
+            (direction OUTPUT))
+          (port DOB2
+            (direction OUTPUT))
+          (port DOB1
+            (direction OUTPUT))
+          (port DOB0
+            (direction OUTPUT)))))
+    (cell fifo_36x8k_oreg
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port (array (rename Data "Data(35:0)") 36)
+            (direction INPUT))
+          (port Clock
+            (direction INPUT))
+          (port WrEn
+            (direction INPUT))
+          (port RdEn
+            (direction INPUT))
+          (port Reset
+            (direction INPUT))
+          (port (array (rename AmFullThresh "AmFullThresh(12:0)") 13)
+            (direction INPUT))
+          (port (array (rename Q "Q(35:0)") 36)
+            (direction OUTPUT))
+          (port (array (rename WCNT "WCNT(13:0)") 14)
+            (direction OUTPUT))
+          (port Empty
+            (direction OUTPUT))
+          (port Full
+            (direction OUTPUT))
+          (port AlmostFull
+            (direction OUTPUT)))
+        (property NGD_DRC_MASK (integer 1))
+        (contents
+          (instance AND2_t5
+            (viewRef view1 
+              (cellRef AND2)))
+          (instance INV_5
+            (viewRef view1 
+              (cellRef INV)))
+          (instance AND2_t4
+            (viewRef view1 
+              (cellRef AND2)))
+          (instance INV_4
+            (viewRef view1 
+              (cellRef INV)))
+          (instance AND2_t3
+            (viewRef view1 
+              (cellRef AND2)))
+          (instance XOR2_t2
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance INV_3
+            (viewRef view1 
+              (cellRef INV)))
+          (instance INV_2
+            (viewRef view1 
+              (cellRef INV)))
+          (instance LUT4_1
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x3232")))
+          (instance LUT4_0
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x3232")))
+          (instance AND2_t1
+            (viewRef view1 
+              (cellRef AND2)))
+          (instance INV_1
+            (viewRef view1 
+              (cellRef INV)))
+          (instance XOR2_t0
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance INV_0
+            (viewRef view1 
+              (cellRef INV)))
+          (instance pdp_ram_0_0_15
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x8k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b000"))
+            (property CSDECODE_A
+              (string "0b000"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_0_1_14
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x8k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b000"))
+            (property CSDECODE_A
+              (string "0b000"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_0_2_13
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x8k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b000"))
+            (property CSDECODE_A
+              (string "0b000"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_0_3_12
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x8k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b000"))
+            (property CSDECODE_A
+              (string "0b000"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_1_0_11
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x8k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_1_1_10
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x8k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_1_2_9
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x8k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_1_3_8
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x8k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b001"))
+            (property CSDECODE_A
+              (string "0b001"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_2_0_7
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x8k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b010"))
+            (property CSDECODE_A
+              (string "0b010"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_2_1_6
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x8k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b010"))
+            (property CSDECODE_A
+              (string "0b010"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_2_2_5
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x8k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b010"))
+            (property CSDECODE_A
+              (string "0b010"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_2_3_4
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x8k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b010"))
+            (property CSDECODE_A
+              (string "0b010"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_3_0_3
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x8k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b011"))
+            (property CSDECODE_A
+              (string "0b011"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_3_1_2
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x8k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b011"))
+            (property CSDECODE_A
+              (string "0b011"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_3_2_1
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x8k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b011"))
+            (property CSDECODE_A
+              (string "0b011"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance pdp_ram_3_3_0
+            (viewRef view1 
+              (cellRef DP16KD))
+            (property INIT_DATA
+              (string "STATIC"))
+            (property ASYNC_RESET_RELEASE
+              (string "SYNC"))
+            (property MEM_LPC_FILE
+              (string "fifo_36x8k_oreg.lpc"))
+            (property MEM_INIT_FILE
+              (string ""))
+            (property CSDECODE_B
+              (string "0b011"))
+            (property CSDECODE_A
+              (string "0b011"))
+            (property WRITEMODE_B
+              (string "NORMAL"))
+            (property WRITEMODE_A
+              (string "NORMAL"))
+            (property GSR
+              (string "ENABLED"))
+            (property RESETMODE
+              (string "ASYNC"))
+            (property REGMODE_B
+              (string "OUTREG"))
+            (property REGMODE_A
+              (string "OUTREG"))
+            (property DATA_WIDTH_B
+              (string "9"))
+            (property DATA_WIDTH_A
+              (string "9")))
+          (instance FF_90
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_89
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_88
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_87
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_86
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_85
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_84
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_83
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_82
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_81
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_80
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_79
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_78
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_77
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_76
+            (viewRef view1 
+              (cellRef FD1S3BX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_75
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_74
+            (viewRef view1 
+              (cellRef FD1P3BX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_73
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_72
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_71
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_70
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_69
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_68
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_67
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_66
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_65
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_64
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_63
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_62
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_61
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_60
+            (viewRef view1 
+              (cellRef FD1P3BX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_59
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_58
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_57
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_56
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_55
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_54
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_53
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_52
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_51
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_50
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_49
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_48
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_47
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_46
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_45
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_44
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_43
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_42
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_41
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_40
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_39
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_38
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_37
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_36
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_35
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_34
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_33
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_32
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_31
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_30
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_29
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_28
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_27
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_26
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_25
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_24
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_23
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_22
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_21
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_20
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_19
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_18
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_17
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_16
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_15
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_14
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_13
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_12
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_11
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_10
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_9
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_8
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_7
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_6
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_5
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_4
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_3
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_2
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_1
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_0
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance bdcnt_bctr_cia
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance bdcnt_bctr_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance bdcnt_bctr_6
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_ci_a
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance e_cmp_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance e_cmp_6
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance a0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance g_cmp_ci_a
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance g_cmp_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance g_cmp_6
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance a1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_cia
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance w_ctr_6
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_cia
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance r_ctr_6
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance mux_35
+            (viewRef view1 
+              (cellRef MUX41)))
+          (instance mux_34
+            (viewRef view1 
+              (cellRef MUX41)))
+          (instance mux_33
+            (viewRef view1 
+              (cellRef MUX41)))
+          (instance mux_32
+            (viewRef view1 
+              (cellRef MUX41)))
+          (instance mux_31
+            (viewRef view1 
+              (cellRef MUX41)))
+          (instance mux_30
+            (viewRef view1 
+              (cellRef MUX41)))
+          (instance mux_29
+            (viewRef view1 
+              (cellRef MUX41)))
+          (instance mux_28
+            (viewRef view1 
+              (cellRef MUX41)))
+          (instance mux_27
+            (viewRef view1 
+              (cellRef MUX41)))
+          (instance mux_26
+            (viewRef view1 
+              (cellRef MUX41)))
+          (instance mux_25
+            (viewRef view1 
+              (cellRef MUX41)))
+          (instance mux_24
+            (viewRef view1 
+              (cellRef MUX41)))
+          (instance mux_23
+            (viewRef view1 
+              (cellRef MUX41)))
+          (instance mux_22
+            (viewRef view1 
+              (cellRef MUX41)))
+          (instance mux_21
+            (viewRef view1 
+              (cellRef MUX41)))
+          (instance mux_20
+            (viewRef view1 
+              (cellRef MUX41)))
+          (instance mux_19
+            (viewRef view1 
+              (cellRef MUX41)))
+          (instance mux_18
+            (viewRef view1 
+              (cellRef MUX41)))
+          (instance mux_17
+            (viewRef view1 
+              (cellRef MUX41)))
+          (instance mux_16
+            (viewRef view1 
+              (cellRef MUX41)))
+          (instance mux_15
+            (viewRef view1 
+              (cellRef MUX41)))
+          (instance mux_14
+            (viewRef view1 
+              (cellRef MUX41)))
+          (instance mux_13
+            (viewRef view1 
+              (cellRef MUX41)))
+          (instance mux_12
+            (viewRef view1 
+              (cellRef MUX41)))
+          (instance mux_11
+            (viewRef view1 
+              (cellRef MUX41)))
+          (instance mux_10
+            (viewRef view1 
+              (cellRef MUX41)))
+          (instance mux_9
+            (viewRef view1 
+              (cellRef MUX41)))
+          (instance mux_8
+            (viewRef view1 
+              (cellRef MUX41)))
+          (instance mux_7
+            (viewRef view1 
+              (cellRef MUX41)))
+          (instance mux_6
+            (viewRef view1 
+              (cellRef MUX41)))
+          (instance mux_5
+            (viewRef view1 
+              (cellRef MUX41)))
+          (instance mux_4
+            (viewRef view1 
+              (cellRef MUX41)))
+          (instance mux_3
+            (viewRef view1 
+              (cellRef MUX41)))
+          (instance mux_2
+            (viewRef view1 
+              (cellRef MUX41)))
+          (instance mux_1
+            (viewRef view1 
+              (cellRef MUX41)))
+          (instance mux_0
+            (viewRef view1 
+              (cellRef MUX41)))
+          (instance precin_inst474
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x0000"))
+            (property INIT0
+              (string "0x0000")))
+          (instance wcnt_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_6
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance wcnt_7
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_ci_a
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (instance af_set_cmp_0
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_1
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_3
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_4
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_5
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance af_set_cmp_6
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x99AA"))
+            (property INIT0
+              (string "0x99AA")))
+          (instance scuba_vhi_inst
+            (viewRef view1 
+              (cellRef VHI)))
+          (instance scuba_vlo_inst
+            (viewRef view1 
+              (cellRef VLO)))
+          (instance a2
+            (viewRef view1 
+              (cellRef CCU2C))
+            (property INJECT1_1
+              (string "NO"))
+            (property INJECT1_0
+              (string "NO"))
+            (property INIT1
+              (string "0x66AA"))
+            (property INIT0
+              (string "0x66AA")))
+          (net invout_2
+            (joined
+              (portRef Z (instanceRef INV_5))
+              (portRef B (instanceRef AND2_t5))))
+          (net invout_1
+            (joined
+              (portRef Z (instanceRef INV_4))
+              (portRef B (instanceRef AND2_t4))))
+          (net rden_i_inv
+            (joined
+              (portRef Z (instanceRef INV_3))
+              (portRef B (instanceRef AND2_t3))))
+          (net invout_0
+            (joined
+              (portRef Z (instanceRef INV_1))
+              (portRef B (instanceRef AND2_t1))))
+          (net r_nw
+            (joined
+              (portRef Z (instanceRef AND2_t1))))
+          (net fcnt_en
+            (joined
+              (portRef SP (instanceRef FF_77))
+              (portRef Z (instanceRef XOR2_t2))
+              (portRef SP (instanceRef FF_90))
+              (portRef SP (instanceRef FF_89))
+              (portRef SP (instanceRef FF_88))
+              (portRef SP (instanceRef FF_87))
+              (portRef SP (instanceRef FF_86))
+              (portRef SP (instanceRef FF_85))
+              (portRef SP (instanceRef FF_84))
+              (portRef SP (instanceRef FF_83))
+              (portRef SP (instanceRef FF_82))
+              (portRef SP (instanceRef FF_81))
+              (portRef SP (instanceRef FF_80))
+              (portRef SP (instanceRef FF_79))
+              (portRef SP (instanceRef FF_78))))
+          (net empty_d
+            (joined
+              (portRef D (instanceRef FF_76))
+              (portRef DO0 (instanceRef LUT4_1))))
+          (net full_d
+            (joined
+              (portRef D (instanceRef FF_75))
+              (portRef DO0 (instanceRef LUT4_0))))
+          (net wptr_0
+            (joined
+              (portRef Q (instanceRef FF_46))
+              (portRef ADA3 (instanceRef pdp_ram_0_0_15))
+              (portRef ADA3 (instanceRef pdp_ram_0_1_14))
+              (portRef ADA3 (instanceRef pdp_ram_0_2_13))
+              (portRef ADA3 (instanceRef pdp_ram_0_3_12))
+              (portRef ADA3 (instanceRef pdp_ram_1_0_11))
+              (portRef ADA3 (instanceRef pdp_ram_1_1_10))
+              (portRef ADA3 (instanceRef pdp_ram_1_2_9))
+              (portRef ADA3 (instanceRef pdp_ram_1_3_8))
+              (portRef ADA3 (instanceRef pdp_ram_2_0_7))
+              (portRef ADA3 (instanceRef pdp_ram_2_1_6))
+              (portRef ADA3 (instanceRef pdp_ram_2_2_5))
+              (portRef ADA3 (instanceRef pdp_ram_2_3_4))
+              (portRef ADA3 (instanceRef pdp_ram_3_0_3))
+              (portRef ADA3 (instanceRef pdp_ram_3_1_2))
+              (portRef ADA3 (instanceRef pdp_ram_3_2_1))
+              (portRef ADA3 (instanceRef pdp_ram_3_3_0))))
+          (net wptr_1
+            (joined
+              (portRef Q (instanceRef FF_45))
+              (portRef ADA4 (instanceRef pdp_ram_0_0_15))
+              (portRef ADA4 (instanceRef pdp_ram_0_1_14))
+              (portRef ADA4 (instanceRef pdp_ram_0_2_13))
+              (portRef ADA4 (instanceRef pdp_ram_0_3_12))
+              (portRef ADA4 (instanceRef pdp_ram_1_0_11))
+              (portRef ADA4 (instanceRef pdp_ram_1_1_10))
+              (portRef ADA4 (instanceRef pdp_ram_1_2_9))
+              (portRef ADA4 (instanceRef pdp_ram_1_3_8))
+              (portRef ADA4 (instanceRef pdp_ram_2_0_7))
+              (portRef ADA4 (instanceRef pdp_ram_2_1_6))
+              (portRef ADA4 (instanceRef pdp_ram_2_2_5))
+              (portRef ADA4 (instanceRef pdp_ram_2_3_4))
+              (portRef ADA4 (instanceRef pdp_ram_3_0_3))
+              (portRef ADA4 (instanceRef pdp_ram_3_1_2))
+              (portRef ADA4 (instanceRef pdp_ram_3_2_1))
+              (portRef ADA4 (instanceRef pdp_ram_3_3_0))))
+          (net wptr_2
+            (joined
+              (portRef Q (instanceRef FF_44))
+              (portRef ADA5 (instanceRef pdp_ram_0_0_15))
+              (portRef ADA5 (instanceRef pdp_ram_0_1_14))
+              (portRef ADA5 (instanceRef pdp_ram_0_2_13))
+              (portRef ADA5 (instanceRef pdp_ram_0_3_12))
+              (portRef ADA5 (instanceRef pdp_ram_1_0_11))
+              (portRef ADA5 (instanceRef pdp_ram_1_1_10))
+              (portRef ADA5 (instanceRef pdp_ram_1_2_9))
+              (portRef ADA5 (instanceRef pdp_ram_1_3_8))
+              (portRef ADA5 (instanceRef pdp_ram_2_0_7))
+              (portRef ADA5 (instanceRef pdp_ram_2_1_6))
+              (portRef ADA5 (instanceRef pdp_ram_2_2_5))
+              (portRef ADA5 (instanceRef pdp_ram_2_3_4))
+              (portRef ADA5 (instanceRef pdp_ram_3_0_3))
+              (portRef ADA5 (instanceRef pdp_ram_3_1_2))
+              (portRef ADA5 (instanceRef pdp_ram_3_2_1))
+              (portRef ADA5 (instanceRef pdp_ram_3_3_0))))
+          (net wptr_3
+            (joined
+              (portRef Q (instanceRef FF_43))
+              (portRef ADA6 (instanceRef pdp_ram_0_0_15))
+              (portRef ADA6 (instanceRef pdp_ram_0_1_14))
+              (portRef ADA6 (instanceRef pdp_ram_0_2_13))
+              (portRef ADA6 (instanceRef pdp_ram_0_3_12))
+              (portRef ADA6 (instanceRef pdp_ram_1_0_11))
+              (portRef ADA6 (instanceRef pdp_ram_1_1_10))
+              (portRef ADA6 (instanceRef pdp_ram_1_2_9))
+              (portRef ADA6 (instanceRef pdp_ram_1_3_8))
+              (portRef ADA6 (instanceRef pdp_ram_2_0_7))
+              (portRef ADA6 (instanceRef pdp_ram_2_1_6))
+              (portRef ADA6 (instanceRef pdp_ram_2_2_5))
+              (portRef ADA6 (instanceRef pdp_ram_2_3_4))
+              (portRef ADA6 (instanceRef pdp_ram_3_0_3))
+              (portRef ADA6 (instanceRef pdp_ram_3_1_2))
+              (portRef ADA6 (instanceRef pdp_ram_3_2_1))
+              (portRef ADA6 (instanceRef pdp_ram_3_3_0))))
+          (net wptr_4
+            (joined
+              (portRef Q (instanceRef FF_42))
+              (portRef ADA7 (instanceRef pdp_ram_0_0_15))
+              (portRef ADA7 (instanceRef pdp_ram_0_1_14))
+              (portRef ADA7 (instanceRef pdp_ram_0_2_13))
+              (portRef ADA7 (instanceRef pdp_ram_0_3_12))
+              (portRef ADA7 (instanceRef pdp_ram_1_0_11))
+              (portRef ADA7 (instanceRef pdp_ram_1_1_10))
+              (portRef ADA7 (instanceRef pdp_ram_1_2_9))
+              (portRef ADA7 (instanceRef pdp_ram_1_3_8))
+              (portRef ADA7 (instanceRef pdp_ram_2_0_7))
+              (portRef ADA7 (instanceRef pdp_ram_2_1_6))
+              (portRef ADA7 (instanceRef pdp_ram_2_2_5))
+              (portRef ADA7 (instanceRef pdp_ram_2_3_4))
+              (portRef ADA7 (instanceRef pdp_ram_3_0_3))
+              (portRef ADA7 (instanceRef pdp_ram_3_1_2))
+              (portRef ADA7 (instanceRef pdp_ram_3_2_1))
+              (portRef ADA7 (instanceRef pdp_ram_3_3_0))))
+          (net wptr_5
+            (joined
+              (portRef Q (instanceRef FF_41))
+              (portRef ADA8 (instanceRef pdp_ram_0_0_15))
+              (portRef ADA8 (instanceRef pdp_ram_0_1_14))
+              (portRef ADA8 (instanceRef pdp_ram_0_2_13))
+              (portRef ADA8 (instanceRef pdp_ram_0_3_12))
+              (portRef ADA8 (instanceRef pdp_ram_1_0_11))
+              (portRef ADA8 (instanceRef pdp_ram_1_1_10))
+              (portRef ADA8 (instanceRef pdp_ram_1_2_9))
+              (portRef ADA8 (instanceRef pdp_ram_1_3_8))
+              (portRef ADA8 (instanceRef pdp_ram_2_0_7))
+              (portRef ADA8 (instanceRef pdp_ram_2_1_6))
+              (portRef ADA8 (instanceRef pdp_ram_2_2_5))
+              (portRef ADA8 (instanceRef pdp_ram_2_3_4))
+              (portRef ADA8 (instanceRef pdp_ram_3_0_3))
+              (portRef ADA8 (instanceRef pdp_ram_3_1_2))
+              (portRef ADA8 (instanceRef pdp_ram_3_2_1))
+              (portRef ADA8 (instanceRef pdp_ram_3_3_0))))
+          (net wptr_6
+            (joined
+              (portRef Q (instanceRef FF_40))
+              (portRef ADA9 (instanceRef pdp_ram_0_0_15))
+              (portRef ADA9 (instanceRef pdp_ram_0_1_14))
+              (portRef ADA9 (instanceRef pdp_ram_0_2_13))
+              (portRef ADA9 (instanceRef pdp_ram_0_3_12))
+              (portRef ADA9 (instanceRef pdp_ram_1_0_11))
+              (portRef ADA9 (instanceRef pdp_ram_1_1_10))
+              (portRef ADA9 (instanceRef pdp_ram_1_2_9))
+              (portRef ADA9 (instanceRef pdp_ram_1_3_8))
+              (portRef ADA9 (instanceRef pdp_ram_2_0_7))
+              (portRef ADA9 (instanceRef pdp_ram_2_1_6))
+              (portRef ADA9 (instanceRef pdp_ram_2_2_5))
+              (portRef ADA9 (instanceRef pdp_ram_2_3_4))
+              (portRef ADA9 (instanceRef pdp_ram_3_0_3))
+              (portRef ADA9 (instanceRef pdp_ram_3_1_2))
+              (portRef ADA9 (instanceRef pdp_ram_3_2_1))
+              (portRef ADA9 (instanceRef pdp_ram_3_3_0))))
+          (net wptr_7
+            (joined
+              (portRef Q (instanceRef FF_39))
+              (portRef ADA10 (instanceRef pdp_ram_0_0_15))
+              (portRef ADA10 (instanceRef pdp_ram_0_1_14))
+              (portRef ADA10 (instanceRef pdp_ram_0_2_13))
+              (portRef ADA10 (instanceRef pdp_ram_0_3_12))
+              (portRef ADA10 (instanceRef pdp_ram_1_0_11))
+              (portRef ADA10 (instanceRef pdp_ram_1_1_10))
+              (portRef ADA10 (instanceRef pdp_ram_1_2_9))
+              (portRef ADA10 (instanceRef pdp_ram_1_3_8))
+              (portRef ADA10 (instanceRef pdp_ram_2_0_7))
+              (portRef ADA10 (instanceRef pdp_ram_2_1_6))
+              (portRef ADA10 (instanceRef pdp_ram_2_2_5))
+              (portRef ADA10 (instanceRef pdp_ram_2_3_4))
+              (portRef ADA10 (instanceRef pdp_ram_3_0_3))
+              (portRef ADA10 (instanceRef pdp_ram_3_1_2))
+              (portRef ADA10 (instanceRef pdp_ram_3_2_1))
+              (portRef ADA10 (instanceRef pdp_ram_3_3_0))))
+          (net wptr_8
+            (joined
+              (portRef Q (instanceRef FF_38))
+              (portRef ADA11 (instanceRef pdp_ram_0_0_15))
+              (portRef ADA11 (instanceRef pdp_ram_0_1_14))
+              (portRef ADA11 (instanceRef pdp_ram_0_2_13))
+              (portRef ADA11 (instanceRef pdp_ram_0_3_12))
+              (portRef ADA11 (instanceRef pdp_ram_1_0_11))
+              (portRef ADA11 (instanceRef pdp_ram_1_1_10))
+              (portRef ADA11 (instanceRef pdp_ram_1_2_9))
+              (portRef ADA11 (instanceRef pdp_ram_1_3_8))
+              (portRef ADA11 (instanceRef pdp_ram_2_0_7))
+              (portRef ADA11 (instanceRef pdp_ram_2_1_6))
+              (portRef ADA11 (instanceRef pdp_ram_2_2_5))
+              (portRef ADA11 (instanceRef pdp_ram_2_3_4))
+              (portRef ADA11 (instanceRef pdp_ram_3_0_3))
+              (portRef ADA11 (instanceRef pdp_ram_3_1_2))
+              (portRef ADA11 (instanceRef pdp_ram_3_2_1))
+              (portRef ADA11 (instanceRef pdp_ram_3_3_0))))
+          (net wptr_9
+            (joined
+              (portRef Q (instanceRef FF_37))
+              (portRef ADA12 (instanceRef pdp_ram_0_0_15))
+              (portRef ADA12 (instanceRef pdp_ram_0_1_14))
+              (portRef ADA12 (instanceRef pdp_ram_0_2_13))
+              (portRef ADA12 (instanceRef pdp_ram_0_3_12))
+              (portRef ADA12 (instanceRef pdp_ram_1_0_11))
+              (portRef ADA12 (instanceRef pdp_ram_1_1_10))
+              (portRef ADA12 (instanceRef pdp_ram_1_2_9))
+              (portRef ADA12 (instanceRef pdp_ram_1_3_8))
+              (portRef ADA12 (instanceRef pdp_ram_2_0_7))
+              (portRef ADA12 (instanceRef pdp_ram_2_1_6))
+              (portRef ADA12 (instanceRef pdp_ram_2_2_5))
+              (portRef ADA12 (instanceRef pdp_ram_2_3_4))
+              (portRef ADA12 (instanceRef pdp_ram_3_0_3))
+              (portRef ADA12 (instanceRef pdp_ram_3_1_2))
+              (portRef ADA12 (instanceRef pdp_ram_3_2_1))
+              (portRef ADA12 (instanceRef pdp_ram_3_3_0))))
+          (net wptr_10
+            (joined
+              (portRef Q (instanceRef FF_36))
+              (portRef ADA13 (instanceRef pdp_ram_0_0_15))
+              (portRef ADA13 (instanceRef pdp_ram_0_1_14))
+              (portRef ADA13 (instanceRef pdp_ram_0_2_13))
+              (portRef ADA13 (instanceRef pdp_ram_0_3_12))
+              (portRef ADA13 (instanceRef pdp_ram_1_0_11))
+              (portRef ADA13 (instanceRef pdp_ram_1_1_10))
+              (portRef ADA13 (instanceRef pdp_ram_1_2_9))
+              (portRef ADA13 (instanceRef pdp_ram_1_3_8))
+              (portRef ADA13 (instanceRef pdp_ram_2_0_7))
+              (portRef ADA13 (instanceRef pdp_ram_2_1_6))
+              (portRef ADA13 (instanceRef pdp_ram_2_2_5))
+              (portRef ADA13 (instanceRef pdp_ram_2_3_4))
+              (portRef ADA13 (instanceRef pdp_ram_3_0_3))
+              (portRef ADA13 (instanceRef pdp_ram_3_1_2))
+              (portRef ADA13 (instanceRef pdp_ram_3_2_1))
+              (portRef ADA13 (instanceRef pdp_ram_3_3_0))))
+          (net wptr_11
+            (joined
+              (portRef Q (instanceRef FF_35))
+              (portRef CSA0 (instanceRef pdp_ram_0_0_15))
+              (portRef CSA0 (instanceRef pdp_ram_0_1_14))
+              (portRef CSA0 (instanceRef pdp_ram_0_2_13))
+              (portRef CSA0 (instanceRef pdp_ram_0_3_12))
+              (portRef CSA0 (instanceRef pdp_ram_1_0_11))
+              (portRef CSA0 (instanceRef pdp_ram_1_1_10))
+              (portRef CSA0 (instanceRef pdp_ram_1_2_9))
+              (portRef CSA0 (instanceRef pdp_ram_1_3_8))
+              (portRef CSA0 (instanceRef pdp_ram_2_0_7))
+              (portRef CSA0 (instanceRef pdp_ram_2_1_6))
+              (portRef CSA0 (instanceRef pdp_ram_2_2_5))
+              (portRef CSA0 (instanceRef pdp_ram_2_3_4))
+              (portRef CSA0 (instanceRef pdp_ram_3_0_3))
+              (portRef CSA0 (instanceRef pdp_ram_3_1_2))
+              (portRef CSA0 (instanceRef pdp_ram_3_2_1))
+              (portRef CSA0 (instanceRef pdp_ram_3_3_0))))
+          (net wptr_12
+            (joined
+              (portRef Q (instanceRef FF_34))
+              (portRef CSA1 (instanceRef pdp_ram_0_0_15))
+              (portRef CSA1 (instanceRef pdp_ram_0_1_14))
+              (portRef CSA1 (instanceRef pdp_ram_0_2_13))
+              (portRef CSA1 (instanceRef pdp_ram_0_3_12))
+              (portRef CSA1 (instanceRef pdp_ram_1_0_11))
+              (portRef CSA1 (instanceRef pdp_ram_1_1_10))
+              (portRef CSA1 (instanceRef pdp_ram_1_2_9))
+              (portRef CSA1 (instanceRef pdp_ram_1_3_8))
+              (portRef CSA1 (instanceRef pdp_ram_2_0_7))
+              (portRef CSA1 (instanceRef pdp_ram_2_1_6))
+              (portRef CSA1 (instanceRef pdp_ram_2_2_5))
+              (portRef CSA1 (instanceRef pdp_ram_2_3_4))
+              (portRef CSA1 (instanceRef pdp_ram_3_0_3))
+              (portRef CSA1 (instanceRef pdp_ram_3_1_2))
+              (portRef CSA1 (instanceRef pdp_ram_3_2_1))
+              (portRef CSA1 (instanceRef pdp_ram_3_3_0))))
+          (net wptr_13
+            (joined
+              (portRef Q (instanceRef FF_33))))
+          (net rptr_13
+            (joined
+              (portRef Q (instanceRef FF_19))
+              (portRef B (instanceRef XOR2_t0))))
+          (net rptr_11_ff
+            (joined
+              (portRef D (instanceRef FF_16))
+              (portRef Q (instanceRef FF_18))))
+          (net rptr_12_ff
+            (joined
+              (portRef D (instanceRef FF_15))
+              (portRef Q (instanceRef FF_17))))
+          (net ifcount_0
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_0))
+              (portRef D (instanceRef FF_90))))
+          (net ifcount_1
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_0))
+              (portRef D (instanceRef FF_89))))
+          (net bdcnt_bctr_ci
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_0))
+              (portRef COUT (instanceRef bdcnt_bctr_cia))))
+          (net ifcount_2
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_1))
+              (portRef D (instanceRef FF_88))))
+          (net ifcount_3
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_1))
+              (portRef D (instanceRef FF_87))))
+          (net co0
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_1))
+              (portRef COUT (instanceRef bdcnt_bctr_0))))
+          (net ifcount_4
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_2))
+              (portRef D (instanceRef FF_86))))
+          (net ifcount_5
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_2))
+              (portRef D (instanceRef FF_85))))
+          (net co1
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_2))
+              (portRef COUT (instanceRef bdcnt_bctr_1))))
+          (net ifcount_6
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_3))
+              (portRef D (instanceRef FF_84))))
+          (net ifcount_7
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_3))
+              (portRef D (instanceRef FF_83))))
+          (net co2
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_3))
+              (portRef COUT (instanceRef bdcnt_bctr_2))))
+          (net ifcount_8
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_4))
+              (portRef D (instanceRef FF_82))))
+          (net ifcount_9
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_4))
+              (portRef D (instanceRef FF_81))))
+          (net co3
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_4))
+              (portRef COUT (instanceRef bdcnt_bctr_3))))
+          (net ifcount_10
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_5))
+              (portRef D (instanceRef FF_80))))
+          (net ifcount_11
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_5))
+              (portRef D (instanceRef FF_79))))
+          (net co4
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_5))
+              (portRef COUT (instanceRef bdcnt_bctr_4))))
+          (net ifcount_12
+            (joined
+              (portRef S0 (instanceRef bdcnt_bctr_6))
+              (portRef D (instanceRef FF_78))))
+          (net ifcount_13
+            (joined
+              (portRef S1 (instanceRef bdcnt_bctr_6))
+              (portRef D (instanceRef FF_77))))
+          (net co6
+            (joined
+              (portRef COUT (instanceRef bdcnt_bctr_6))))
+          (net co5
+            (joined
+              (portRef CIN (instanceRef bdcnt_bctr_6))
+              (portRef COUT (instanceRef bdcnt_bctr_5))))
+          (net cmp_ci
+            (joined
+              (portRef CIN (instanceRef e_cmp_0))
+              (portRef COUT (instanceRef e_cmp_ci_a))))
+          (net rden_i
+            (joined
+              (portRef A0 (instanceRef e_cmp_0))
+              (portRef Z (instanceRef AND2_t4))
+              (portRef B (instanceRef XOR2_t2))
+              (portRef A (instanceRef INV_3))
+              (portRef AD1 (instanceRef LUT4_0))
+              (portRef A (instanceRef AND2_t1))
+              (portRef CEB (instanceRef pdp_ram_0_0_15))
+              (portRef CEB (instanceRef pdp_ram_0_1_14))
+              (portRef CEB (instanceRef pdp_ram_0_2_13))
+              (portRef CEB (instanceRef pdp_ram_0_3_12))
+              (portRef CEB (instanceRef pdp_ram_1_0_11))
+              (portRef CEB (instanceRef pdp_ram_1_1_10))
+              (portRef CEB (instanceRef pdp_ram_1_2_9))
+              (portRef CEB (instanceRef pdp_ram_1_3_8))
+              (portRef CEB (instanceRef pdp_ram_2_0_7))
+              (portRef CEB (instanceRef pdp_ram_2_1_6))
+              (portRef CEB (instanceRef pdp_ram_2_2_5))
+              (portRef CEB (instanceRef pdp_ram_2_3_4))
+              (portRef CEB (instanceRef pdp_ram_3_0_3))
+              (portRef CEB (instanceRef pdp_ram_3_1_2))
+              (portRef CEB (instanceRef pdp_ram_3_2_1))
+              (portRef CEB (instanceRef pdp_ram_3_3_0))
+              (portRef SP (instanceRef FF_60))
+              (portRef SP (instanceRef FF_59))
+              (portRef SP (instanceRef FF_58))
+              (portRef SP (instanceRef FF_57))
+              (portRef SP (instanceRef FF_56))
+              (portRef SP (instanceRef FF_55))
+              (portRef SP (instanceRef FF_54))
+              (portRef SP (instanceRef FF_53))
+              (portRef SP (instanceRef FF_52))
+              (portRef SP (instanceRef FF_51))
+              (portRef SP (instanceRef FF_50))
+              (portRef SP (instanceRef FF_49))
+              (portRef SP (instanceRef FF_48))
+              (portRef SP (instanceRef FF_47))
+              (portRef SP (instanceRef FF_32))
+              (portRef SP (instanceRef FF_31))
+              (portRef SP (instanceRef FF_30))
+              (portRef SP (instanceRef FF_29))
+              (portRef SP (instanceRef FF_28))
+              (portRef SP (instanceRef FF_27))
+              (portRef SP (instanceRef FF_26))
+              (portRef SP (instanceRef FF_25))
+              (portRef SP (instanceRef FF_24))
+              (portRef SP (instanceRef FF_23))
+              (portRef SP (instanceRef FF_22))
+              (portRef SP (instanceRef FF_21))
+              (portRef SP (instanceRef FF_20))
+              (portRef SP (instanceRef FF_19))
+              (portRef SP (instanceRef FF_18))
+              (portRef SP (instanceRef FF_17))
+              (portRef SP (instanceRef FF_16))
+              (portRef SP (instanceRef FF_15))))
+          (net co0_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_1))
+              (portRef COUT (instanceRef e_cmp_0))))
+          (net co1_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_2))
+              (portRef COUT (instanceRef e_cmp_1))))
+          (net co2_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_3))
+              (portRef COUT (instanceRef e_cmp_2))))
+          (net co3_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_4))
+              (portRef COUT (instanceRef e_cmp_3))))
+          (net co4_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_5))
+              (portRef COUT (instanceRef e_cmp_4))))
+          (net co5_1
+            (joined
+              (portRef CIN (instanceRef e_cmp_6))
+              (portRef COUT (instanceRef e_cmp_5))))
+          (net cmp_le_1
+            (joined
+              (portRef S0 (instanceRef a0))
+              (portRef AD2 (instanceRef LUT4_1))))
+          (net cmp_le_1_c
+            (joined
+              (portRef CIN (instanceRef a0))
+              (portRef COUT (instanceRef e_cmp_6))))
+          (net cmp_ci_1
+            (joined
+              (portRef CIN (instanceRef g_cmp_0))
+              (portRef COUT (instanceRef g_cmp_ci_a))))
+          (net co0_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_1))
+              (portRef COUT (instanceRef g_cmp_0))))
+          (net co1_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_2))
+              (portRef COUT (instanceRef g_cmp_1))))
+          (net co2_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_3))
+              (portRef COUT (instanceRef g_cmp_2))))
+          (net co3_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_4))
+              (portRef COUT (instanceRef g_cmp_3))))
+          (net co4_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_5))
+              (portRef COUT (instanceRef g_cmp_4))))
+          (net co5_2
+            (joined
+              (portRef CIN (instanceRef g_cmp_6))
+              (portRef COUT (instanceRef g_cmp_5))))
+          (net wren_i_inv
+            (joined
+              (portRef B1 (instanceRef g_cmp_6))
+              (portRef Z (instanceRef INV_2))))
+          (net cmp_ge_d1
+            (joined
+              (portRef S0 (instanceRef a1))
+              (portRef AD2 (instanceRef LUT4_0))))
+          (net cmp_ge_d1_c
+            (joined
+              (portRef CIN (instanceRef a1))
+              (portRef COUT (instanceRef g_cmp_6))))
+          (net iwcount_0
+            (joined
+              (portRef S0 (instanceRef w_ctr_0))
+              (portRef D (instanceRef FF_74))))
+          (net iwcount_1
+            (joined
+              (portRef S1 (instanceRef w_ctr_0))
+              (portRef D (instanceRef FF_73))))
+          (net w_ctr_ci
+            (joined
+              (portRef CIN (instanceRef w_ctr_0))
+              (portRef COUT (instanceRef w_ctr_cia))))
+          (net iwcount_2
+            (joined
+              (portRef S0 (instanceRef w_ctr_1))
+              (portRef D (instanceRef FF_72))))
+          (net iwcount_3
+            (joined
+              (portRef S1 (instanceRef w_ctr_1))
+              (portRef D (instanceRef FF_71))))
+          (net co0_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_1))
+              (portRef COUT (instanceRef w_ctr_0))))
+          (net iwcount_4
+            (joined
+              (portRef S0 (instanceRef w_ctr_2))
+              (portRef D (instanceRef FF_70))))
+          (net iwcount_5
+            (joined
+              (portRef S1 (instanceRef w_ctr_2))
+              (portRef D (instanceRef FF_69))))
+          (net co1_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_2))
+              (portRef COUT (instanceRef w_ctr_1))))
+          (net iwcount_6
+            (joined
+              (portRef S0 (instanceRef w_ctr_3))
+              (portRef D (instanceRef FF_68))))
+          (net iwcount_7
+            (joined
+              (portRef S1 (instanceRef w_ctr_3))
+              (portRef D (instanceRef FF_67))))
+          (net co2_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_3))
+              (portRef COUT (instanceRef w_ctr_2))))
+          (net iwcount_8
+            (joined
+              (portRef S0 (instanceRef w_ctr_4))
+              (portRef D (instanceRef FF_66))))
+          (net iwcount_9
+            (joined
+              (portRef S1 (instanceRef w_ctr_4))
+              (portRef D (instanceRef FF_65))))
+          (net co3_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_4))
+              (portRef COUT (instanceRef w_ctr_3))))
+          (net iwcount_10
+            (joined
+              (portRef S0 (instanceRef w_ctr_5))
+              (portRef D (instanceRef FF_64))))
+          (net iwcount_11
+            (joined
+              (portRef S1 (instanceRef w_ctr_5))
+              (portRef D (instanceRef FF_63))))
+          (net co4_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_5))
+              (portRef COUT (instanceRef w_ctr_4))))
+          (net iwcount_12
+            (joined
+              (portRef S0 (instanceRef w_ctr_6))
+              (portRef D (instanceRef FF_62))))
+          (net iwcount_13
+            (joined
+              (portRef S1 (instanceRef w_ctr_6))
+              (portRef D (instanceRef FF_61))))
+          (net co6_1
+            (joined
+              (portRef COUT (instanceRef w_ctr_6))))
+          (net co5_3
+            (joined
+              (portRef CIN (instanceRef w_ctr_6))
+              (portRef COUT (instanceRef w_ctr_5))))
+          (net wcount_13
+            (joined
+              (portRef A1 (instanceRef w_ctr_6))
+              (portRef A (instanceRef XOR2_t0))
+              (portRef Q (instanceRef FF_61))
+              (portRef D (instanceRef FF_33))))
+          (net ircount_0
+            (joined
+              (portRef S0 (instanceRef r_ctr_0))
+              (portRef D (instanceRef FF_60))))
+          (net ircount_1
+            (joined
+              (portRef S1 (instanceRef r_ctr_0))
+              (portRef D (instanceRef FF_59))))
+          (net r_ctr_ci
+            (joined
+              (portRef CIN (instanceRef r_ctr_0))
+              (portRef COUT (instanceRef r_ctr_cia))))
+          (net rcount_0
+            (joined
+              (portRef A0 (instanceRef r_ctr_0))
+              (portRef Q (instanceRef FF_60))
+              (portRef D (instanceRef FF_32))))
+          (net rcount_1
+            (joined
+              (portRef A1 (instanceRef r_ctr_0))
+              (portRef Q (instanceRef FF_59))
+              (portRef D (instanceRef FF_31))))
+          (net ircount_2
+            (joined
+              (portRef S0 (instanceRef r_ctr_1))
+              (portRef D (instanceRef FF_58))))
+          (net ircount_3
+            (joined
+              (portRef S1 (instanceRef r_ctr_1))
+              (portRef D (instanceRef FF_57))))
+          (net co0_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_1))
+              (portRef COUT (instanceRef r_ctr_0))))
+          (net rcount_2
+            (joined
+              (portRef A0 (instanceRef r_ctr_1))
+              (portRef Q (instanceRef FF_58))
+              (portRef D (instanceRef FF_30))))
+          (net rcount_3
+            (joined
+              (portRef A1 (instanceRef r_ctr_1))
+              (portRef Q (instanceRef FF_57))
+              (portRef D (instanceRef FF_29))))
+          (net ircount_4
+            (joined
+              (portRef S0 (instanceRef r_ctr_2))
+              (portRef D (instanceRef FF_56))))
+          (net ircount_5
+            (joined
+              (portRef S1 (instanceRef r_ctr_2))
+              (portRef D (instanceRef FF_55))))
+          (net co1_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_2))
+              (portRef COUT (instanceRef r_ctr_1))))
+          (net rcount_4
+            (joined
+              (portRef A0 (instanceRef r_ctr_2))
+              (portRef Q (instanceRef FF_56))
+              (portRef D (instanceRef FF_28))))
+          (net rcount_5
+            (joined
+              (portRef A1 (instanceRef r_ctr_2))
+              (portRef Q (instanceRef FF_55))
+              (portRef D (instanceRef FF_27))))
+          (net ircount_6
+            (joined
+              (portRef S0 (instanceRef r_ctr_3))
+              (portRef D (instanceRef FF_54))))
+          (net ircount_7
+            (joined
+              (portRef S1 (instanceRef r_ctr_3))
+              (portRef D (instanceRef FF_53))))
+          (net co2_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_3))
+              (portRef COUT (instanceRef r_ctr_2))))
+          (net rcount_6
+            (joined
+              (portRef A0 (instanceRef r_ctr_3))
+              (portRef Q (instanceRef FF_54))
+              (portRef D (instanceRef FF_26))))
+          (net rcount_7
+            (joined
+              (portRef A1 (instanceRef r_ctr_3))
+              (portRef Q (instanceRef FF_53))
+              (portRef D (instanceRef FF_25))))
+          (net ircount_8
+            (joined
+              (portRef S0 (instanceRef r_ctr_4))
+              (portRef D (instanceRef FF_52))))
+          (net ircount_9
+            (joined
+              (portRef S1 (instanceRef r_ctr_4))
+              (portRef D (instanceRef FF_51))))
+          (net co3_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_4))
+              (portRef COUT (instanceRef r_ctr_3))))
+          (net rcount_8
+            (joined
+              (portRef A0 (instanceRef r_ctr_4))
+              (portRef Q (instanceRef FF_52))
+              (portRef D (instanceRef FF_24))))
+          (net rcount_9
+            (joined
+              (portRef A1 (instanceRef r_ctr_4))
+              (portRef Q (instanceRef FF_51))
+              (portRef D (instanceRef FF_23))))
+          (net ircount_10
+            (joined
+              (portRef S0 (instanceRef r_ctr_5))
+              (portRef D (instanceRef FF_50))))
+          (net ircount_11
+            (joined
+              (portRef S1 (instanceRef r_ctr_5))
+              (portRef D (instanceRef FF_49))))
+          (net co4_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_5))
+              (portRef COUT (instanceRef r_ctr_4))))
+          (net rcount_10
+            (joined
+              (portRef A0 (instanceRef r_ctr_5))
+              (portRef Q (instanceRef FF_50))
+              (portRef D (instanceRef FF_22))))
+          (net rcount_11
+            (joined
+              (portRef A1 (instanceRef r_ctr_5))
+              (portRef Q (instanceRef FF_49))
+              (portRef D (instanceRef FF_21))))
+          (net ircount_12
+            (joined
+              (portRef S0 (instanceRef r_ctr_6))
+              (portRef D (instanceRef FF_48))))
+          (net ircount_13
+            (joined
+              (portRef S1 (instanceRef r_ctr_6))
+              (portRef D (instanceRef FF_47))))
+          (net co6_2
+            (joined
+              (portRef COUT (instanceRef r_ctr_6))))
+          (net co5_4
+            (joined
+              (portRef CIN (instanceRef r_ctr_6))
+              (portRef COUT (instanceRef r_ctr_5))))
+          (net rcount_12
+            (joined
+              (portRef A0 (instanceRef r_ctr_6))
+              (portRef Q (instanceRef FF_48))
+              (portRef D (instanceRef FF_20))))
+          (net rcount_13
+            (joined
+              (portRef A1 (instanceRef r_ctr_6))
+              (portRef Q (instanceRef FF_47))
+              (portRef D (instanceRef FF_19))))
+          (net mdout1_3_0
+            (joined
+              (portRef D3 (instanceRef mux_35))
+              (portRef DOB0 (instanceRef pdp_ram_3_0_3))))
+          (net mdout1_2_0
+            (joined
+              (portRef D2 (instanceRef mux_35))
+              (portRef DOB0 (instanceRef pdp_ram_2_0_7))))
+          (net mdout1_1_0
+            (joined
+              (portRef D1 (instanceRef mux_35))
+              (portRef DOB0 (instanceRef pdp_ram_1_0_11))))
+          (net mdout1_0_0
+            (joined
+              (portRef D0 (instanceRef mux_35))
+              (portRef DOB0 (instanceRef pdp_ram_0_0_15))))
+          (net mdout1_3_1
+            (joined
+              (portRef D3 (instanceRef mux_34))
+              (portRef DOB1 (instanceRef pdp_ram_3_0_3))))
+          (net mdout1_2_1
+            (joined
+              (portRef D2 (instanceRef mux_34))
+              (portRef DOB1 (instanceRef pdp_ram_2_0_7))))
+          (net mdout1_1_1
+            (joined
+              (portRef D1 (instanceRef mux_34))
+              (portRef DOB1 (instanceRef pdp_ram_1_0_11))))
+          (net mdout1_0_1
+            (joined
+              (portRef D0 (instanceRef mux_34))
+              (portRef DOB1 (instanceRef pdp_ram_0_0_15))))
+          (net mdout1_3_2
+            (joined
+              (portRef D3 (instanceRef mux_33))
+              (portRef DOB2 (instanceRef pdp_ram_3_0_3))))
+          (net mdout1_2_2
+            (joined
+              (portRef D2 (instanceRef mux_33))
+              (portRef DOB2 (instanceRef pdp_ram_2_0_7))))
+          (net mdout1_1_2
+            (joined
+              (portRef D1 (instanceRef mux_33))
+              (portRef DOB2 (instanceRef pdp_ram_1_0_11))))
+          (net mdout1_0_2
+            (joined
+              (portRef D0 (instanceRef mux_33))
+              (portRef DOB2 (instanceRef pdp_ram_0_0_15))))
+          (net mdout1_3_3
+            (joined
+              (portRef D3 (instanceRef mux_32))
+              (portRef DOB3 (instanceRef pdp_ram_3_0_3))))
+          (net mdout1_2_3
+            (joined
+              (portRef D2 (instanceRef mux_32))
+              (portRef DOB3 (instanceRef pdp_ram_2_0_7))))
+          (net mdout1_1_3
+            (joined
+              (portRef D1 (instanceRef mux_32))
+              (portRef DOB3 (instanceRef pdp_ram_1_0_11))))
+          (net mdout1_0_3
+            (joined
+              (portRef D0 (instanceRef mux_32))
+              (portRef DOB3 (instanceRef pdp_ram_0_0_15))))
+          (net mdout1_3_4
+            (joined
+              (portRef D3 (instanceRef mux_31))
+              (portRef DOB4 (instanceRef pdp_ram_3_0_3))))
+          (net mdout1_2_4
+            (joined
+              (portRef D2 (instanceRef mux_31))
+              (portRef DOB4 (instanceRef pdp_ram_2_0_7))))
+          (net mdout1_1_4
+            (joined
+              (portRef D1 (instanceRef mux_31))
+              (portRef DOB4 (instanceRef pdp_ram_1_0_11))))
+          (net mdout1_0_4
+            (joined
+              (portRef D0 (instanceRef mux_31))
+              (portRef DOB4 (instanceRef pdp_ram_0_0_15))))
+          (net mdout1_3_5
+            (joined
+              (portRef D3 (instanceRef mux_30))
+              (portRef DOB5 (instanceRef pdp_ram_3_0_3))))
+          (net mdout1_2_5
+            (joined
+              (portRef D2 (instanceRef mux_30))
+              (portRef DOB5 (instanceRef pdp_ram_2_0_7))))
+          (net mdout1_1_5
+            (joined
+              (portRef D1 (instanceRef mux_30))
+              (portRef DOB5 (instanceRef pdp_ram_1_0_11))))
+          (net mdout1_0_5
+            (joined
+              (portRef D0 (instanceRef mux_30))
+              (portRef DOB5 (instanceRef pdp_ram_0_0_15))))
+          (net mdout1_3_6
+            (joined
+              (portRef D3 (instanceRef mux_29))
+              (portRef DOB6 (instanceRef pdp_ram_3_0_3))))
+          (net mdout1_2_6
+            (joined
+              (portRef D2 (instanceRef mux_29))
+              (portRef DOB6 (instanceRef pdp_ram_2_0_7))))
+          (net mdout1_1_6
+            (joined
+              (portRef D1 (instanceRef mux_29))
+              (portRef DOB6 (instanceRef pdp_ram_1_0_11))))
+          (net mdout1_0_6
+            (joined
+              (portRef D0 (instanceRef mux_29))
+              (portRef DOB6 (instanceRef pdp_ram_0_0_15))))
+          (net mdout1_3_7
+            (joined
+              (portRef D3 (instanceRef mux_28))
+              (portRef DOB7 (instanceRef pdp_ram_3_0_3))))
+          (net mdout1_2_7
+            (joined
+              (portRef D2 (instanceRef mux_28))
+              (portRef DOB7 (instanceRef pdp_ram_2_0_7))))
+          (net mdout1_1_7
+            (joined
+              (portRef D1 (instanceRef mux_28))
+              (portRef DOB7 (instanceRef pdp_ram_1_0_11))))
+          (net mdout1_0_7
+            (joined
+              (portRef D0 (instanceRef mux_28))
+              (portRef DOB7 (instanceRef pdp_ram_0_0_15))))
+          (net mdout1_3_8
+            (joined
+              (portRef D3 (instanceRef mux_27))
+              (portRef DOB8 (instanceRef pdp_ram_3_0_3))))
+          (net mdout1_2_8
+            (joined
+              (portRef D2 (instanceRef mux_27))
+              (portRef DOB8 (instanceRef pdp_ram_2_0_7))))
+          (net mdout1_1_8
+            (joined
+              (portRef D1 (instanceRef mux_27))
+              (portRef DOB8 (instanceRef pdp_ram_1_0_11))))
+          (net mdout1_0_8
+            (joined
+              (portRef D0 (instanceRef mux_27))
+              (portRef DOB8 (instanceRef pdp_ram_0_0_15))))
+          (net mdout1_3_9
+            (joined
+              (portRef D3 (instanceRef mux_26))
+              (portRef DOB0 (instanceRef pdp_ram_3_1_2))))
+          (net mdout1_2_9
+            (joined
+              (portRef D2 (instanceRef mux_26))
+              (portRef DOB0 (instanceRef pdp_ram_2_1_6))))
+          (net mdout1_1_9
+            (joined
+              (portRef D1 (instanceRef mux_26))
+              (portRef DOB0 (instanceRef pdp_ram_1_1_10))))
+          (net mdout1_0_9
+            (joined
+              (portRef D0 (instanceRef mux_26))
+              (portRef DOB0 (instanceRef pdp_ram_0_1_14))))
+          (net mdout1_3_10
+            (joined
+              (portRef D3 (instanceRef mux_25))
+              (portRef DOB1 (instanceRef pdp_ram_3_1_2))))
+          (net mdout1_2_10
+            (joined
+              (portRef D2 (instanceRef mux_25))
+              (portRef DOB1 (instanceRef pdp_ram_2_1_6))))
+          (net mdout1_1_10
+            (joined
+              (portRef D1 (instanceRef mux_25))
+              (portRef DOB1 (instanceRef pdp_ram_1_1_10))))
+          (net mdout1_0_10
+            (joined
+              (portRef D0 (instanceRef mux_25))
+              (portRef DOB1 (instanceRef pdp_ram_0_1_14))))
+          (net mdout1_3_11
+            (joined
+              (portRef D3 (instanceRef mux_24))
+              (portRef DOB2 (instanceRef pdp_ram_3_1_2))))
+          (net mdout1_2_11
+            (joined
+              (portRef D2 (instanceRef mux_24))
+              (portRef DOB2 (instanceRef pdp_ram_2_1_6))))
+          (net mdout1_1_11
+            (joined
+              (portRef D1 (instanceRef mux_24))
+              (portRef DOB2 (instanceRef pdp_ram_1_1_10))))
+          (net mdout1_0_11
+            (joined
+              (portRef D0 (instanceRef mux_24))
+              (portRef DOB2 (instanceRef pdp_ram_0_1_14))))
+          (net mdout1_3_12
+            (joined
+              (portRef D3 (instanceRef mux_23))
+              (portRef DOB3 (instanceRef pdp_ram_3_1_2))))
+          (net mdout1_2_12
+            (joined
+              (portRef D2 (instanceRef mux_23))
+              (portRef DOB3 (instanceRef pdp_ram_2_1_6))))
+          (net mdout1_1_12
+            (joined
+              (portRef D1 (instanceRef mux_23))
+              (portRef DOB3 (instanceRef pdp_ram_1_1_10))))
+          (net mdout1_0_12
+            (joined
+              (portRef D0 (instanceRef mux_23))
+              (portRef DOB3 (instanceRef pdp_ram_0_1_14))))
+          (net mdout1_3_13
+            (joined
+              (portRef D3 (instanceRef mux_22))
+              (portRef DOB4 (instanceRef pdp_ram_3_1_2))))
+          (net mdout1_2_13
+            (joined
+              (portRef D2 (instanceRef mux_22))
+              (portRef DOB4 (instanceRef pdp_ram_2_1_6))))
+          (net mdout1_1_13
+            (joined
+              (portRef D1 (instanceRef mux_22))
+              (portRef DOB4 (instanceRef pdp_ram_1_1_10))))
+          (net mdout1_0_13
+            (joined
+              (portRef D0 (instanceRef mux_22))
+              (portRef DOB4 (instanceRef pdp_ram_0_1_14))))
+          (net mdout1_3_14
+            (joined
+              (portRef D3 (instanceRef mux_21))
+              (portRef DOB5 (instanceRef pdp_ram_3_1_2))))
+          (net mdout1_2_14
+            (joined
+              (portRef D2 (instanceRef mux_21))
+              (portRef DOB5 (instanceRef pdp_ram_2_1_6))))
+          (net mdout1_1_14
+            (joined
+              (portRef D1 (instanceRef mux_21))
+              (portRef DOB5 (instanceRef pdp_ram_1_1_10))))
+          (net mdout1_0_14
+            (joined
+              (portRef D0 (instanceRef mux_21))
+              (portRef DOB5 (instanceRef pdp_ram_0_1_14))))
+          (net mdout1_3_15
+            (joined
+              (portRef D3 (instanceRef mux_20))
+              (portRef DOB6 (instanceRef pdp_ram_3_1_2))))
+          (net mdout1_2_15
+            (joined
+              (portRef D2 (instanceRef mux_20))
+              (portRef DOB6 (instanceRef pdp_ram_2_1_6))))
+          (net mdout1_1_15
+            (joined
+              (portRef D1 (instanceRef mux_20))
+              (portRef DOB6 (instanceRef pdp_ram_1_1_10))))
+          (net mdout1_0_15
+            (joined
+              (portRef D0 (instanceRef mux_20))
+              (portRef DOB6 (instanceRef pdp_ram_0_1_14))))
+          (net mdout1_3_16
+            (joined
+              (portRef D3 (instanceRef mux_19))
+              (portRef DOB7 (instanceRef pdp_ram_3_1_2))))
+          (net mdout1_2_16
+            (joined
+              (portRef D2 (instanceRef mux_19))
+              (portRef DOB7 (instanceRef pdp_ram_2_1_6))))
+          (net mdout1_1_16
+            (joined
+              (portRef D1 (instanceRef mux_19))
+              (portRef DOB7 (instanceRef pdp_ram_1_1_10))))
+          (net mdout1_0_16
+            (joined
+              (portRef D0 (instanceRef mux_19))
+              (portRef DOB7 (instanceRef pdp_ram_0_1_14))))
+          (net mdout1_3_17
+            (joined
+              (portRef D3 (instanceRef mux_18))
+              (portRef DOB8 (instanceRef pdp_ram_3_1_2))))
+          (net mdout1_2_17
+            (joined
+              (portRef D2 (instanceRef mux_18))
+              (portRef DOB8 (instanceRef pdp_ram_2_1_6))))
+          (net mdout1_1_17
+            (joined
+              (portRef D1 (instanceRef mux_18))
+              (portRef DOB8 (instanceRef pdp_ram_1_1_10))))
+          (net mdout1_0_17
+            (joined
+              (portRef D0 (instanceRef mux_18))
+              (portRef DOB8 (instanceRef pdp_ram_0_1_14))))
+          (net mdout1_3_18
+            (joined
+              (portRef D3 (instanceRef mux_17))
+              (portRef DOB0 (instanceRef pdp_ram_3_2_1))))
+          (net mdout1_2_18
+            (joined
+              (portRef D2 (instanceRef mux_17))
+              (portRef DOB0 (instanceRef pdp_ram_2_2_5))))
+          (net mdout1_1_18
+            (joined
+              (portRef D1 (instanceRef mux_17))
+              (portRef DOB0 (instanceRef pdp_ram_1_2_9))))
+          (net mdout1_0_18
+            (joined
+              (portRef D0 (instanceRef mux_17))
+              (portRef DOB0 (instanceRef pdp_ram_0_2_13))))
+          (net mdout1_3_19
+            (joined
+              (portRef D3 (instanceRef mux_16))
+              (portRef DOB1 (instanceRef pdp_ram_3_2_1))))
+          (net mdout1_2_19
+            (joined
+              (portRef D2 (instanceRef mux_16))
+              (portRef DOB1 (instanceRef pdp_ram_2_2_5))))
+          (net mdout1_1_19
+            (joined
+              (portRef D1 (instanceRef mux_16))
+              (portRef DOB1 (instanceRef pdp_ram_1_2_9))))
+          (net mdout1_0_19
+            (joined
+              (portRef D0 (instanceRef mux_16))
+              (portRef DOB1 (instanceRef pdp_ram_0_2_13))))
+          (net mdout1_3_20
+            (joined
+              (portRef D3 (instanceRef mux_15))
+              (portRef DOB2 (instanceRef pdp_ram_3_2_1))))
+          (net mdout1_2_20
+            (joined
+              (portRef D2 (instanceRef mux_15))
+              (portRef DOB2 (instanceRef pdp_ram_2_2_5))))
+          (net mdout1_1_20
+            (joined
+              (portRef D1 (instanceRef mux_15))
+              (portRef DOB2 (instanceRef pdp_ram_1_2_9))))
+          (net mdout1_0_20
+            (joined
+              (portRef D0 (instanceRef mux_15))
+              (portRef DOB2 (instanceRef pdp_ram_0_2_13))))
+          (net mdout1_3_21
+            (joined
+              (portRef D3 (instanceRef mux_14))
+              (portRef DOB3 (instanceRef pdp_ram_3_2_1))))
+          (net mdout1_2_21
+            (joined
+              (portRef D2 (instanceRef mux_14))
+              (portRef DOB3 (instanceRef pdp_ram_2_2_5))))
+          (net mdout1_1_21
+            (joined
+              (portRef D1 (instanceRef mux_14))
+              (portRef DOB3 (instanceRef pdp_ram_1_2_9))))
+          (net mdout1_0_21
+            (joined
+              (portRef D0 (instanceRef mux_14))
+              (portRef DOB3 (instanceRef pdp_ram_0_2_13))))
+          (net mdout1_3_22
+            (joined
+              (portRef D3 (instanceRef mux_13))
+              (portRef DOB4 (instanceRef pdp_ram_3_2_1))))
+          (net mdout1_2_22
+            (joined
+              (portRef D2 (instanceRef mux_13))
+              (portRef DOB4 (instanceRef pdp_ram_2_2_5))))
+          (net mdout1_1_22
+            (joined
+              (portRef D1 (instanceRef mux_13))
+              (portRef DOB4 (instanceRef pdp_ram_1_2_9))))
+          (net mdout1_0_22
+            (joined
+              (portRef D0 (instanceRef mux_13))
+              (portRef DOB4 (instanceRef pdp_ram_0_2_13))))
+          (net mdout1_3_23
+            (joined
+              (portRef D3 (instanceRef mux_12))
+              (portRef DOB5 (instanceRef pdp_ram_3_2_1))))
+          (net mdout1_2_23
+            (joined
+              (portRef D2 (instanceRef mux_12))
+              (portRef DOB5 (instanceRef pdp_ram_2_2_5))))
+          (net mdout1_1_23
+            (joined
+              (portRef D1 (instanceRef mux_12))
+              (portRef DOB5 (instanceRef pdp_ram_1_2_9))))
+          (net mdout1_0_23
+            (joined
+              (portRef D0 (instanceRef mux_12))
+              (portRef DOB5 (instanceRef pdp_ram_0_2_13))))
+          (net mdout1_3_24
+            (joined
+              (portRef D3 (instanceRef mux_11))
+              (portRef DOB6 (instanceRef pdp_ram_3_2_1))))
+          (net mdout1_2_24
+            (joined
+              (portRef D2 (instanceRef mux_11))
+              (portRef DOB6 (instanceRef pdp_ram_2_2_5))))
+          (net mdout1_1_24
+            (joined
+              (portRef D1 (instanceRef mux_11))
+              (portRef DOB6 (instanceRef pdp_ram_1_2_9))))
+          (net mdout1_0_24
+            (joined
+              (portRef D0 (instanceRef mux_11))
+              (portRef DOB6 (instanceRef pdp_ram_0_2_13))))
+          (net mdout1_3_25
+            (joined
+              (portRef D3 (instanceRef mux_10))
+              (portRef DOB7 (instanceRef pdp_ram_3_2_1))))
+          (net mdout1_2_25
+            (joined
+              (portRef D2 (instanceRef mux_10))
+              (portRef DOB7 (instanceRef pdp_ram_2_2_5))))
+          (net mdout1_1_25
+            (joined
+              (portRef D1 (instanceRef mux_10))
+              (portRef DOB7 (instanceRef pdp_ram_1_2_9))))
+          (net mdout1_0_25
+            (joined
+              (portRef D0 (instanceRef mux_10))
+              (portRef DOB7 (instanceRef pdp_ram_0_2_13))))
+          (net mdout1_3_26
+            (joined
+              (portRef D3 (instanceRef mux_9))
+              (portRef DOB8 (instanceRef pdp_ram_3_2_1))))
+          (net mdout1_2_26
+            (joined
+              (portRef D2 (instanceRef mux_9))
+              (portRef DOB8 (instanceRef pdp_ram_2_2_5))))
+          (net mdout1_1_26
+            (joined
+              (portRef D1 (instanceRef mux_9))
+              (portRef DOB8 (instanceRef pdp_ram_1_2_9))))
+          (net mdout1_0_26
+            (joined
+              (portRef D0 (instanceRef mux_9))
+              (portRef DOB8 (instanceRef pdp_ram_0_2_13))))
+          (net mdout1_3_27
+            (joined
+              (portRef D3 (instanceRef mux_8))
+              (portRef DOB0 (instanceRef pdp_ram_3_3_0))))
+          (net mdout1_2_27
+            (joined
+              (portRef D2 (instanceRef mux_8))
+              (portRef DOB0 (instanceRef pdp_ram_2_3_4))))
+          (net mdout1_1_27
+            (joined
+              (portRef D1 (instanceRef mux_8))
+              (portRef DOB0 (instanceRef pdp_ram_1_3_8))))
+          (net mdout1_0_27
+            (joined
+              (portRef D0 (instanceRef mux_8))
+              (portRef DOB0 (instanceRef pdp_ram_0_3_12))))
+          (net mdout1_3_28
+            (joined
+              (portRef D3 (instanceRef mux_7))
+              (portRef DOB1 (instanceRef pdp_ram_3_3_0))))
+          (net mdout1_2_28
+            (joined
+              (portRef D2 (instanceRef mux_7))
+              (portRef DOB1 (instanceRef pdp_ram_2_3_4))))
+          (net mdout1_1_28
+            (joined
+              (portRef D1 (instanceRef mux_7))
+              (portRef DOB1 (instanceRef pdp_ram_1_3_8))))
+          (net mdout1_0_28
+            (joined
+              (portRef D0 (instanceRef mux_7))
+              (portRef DOB1 (instanceRef pdp_ram_0_3_12))))
+          (net mdout1_3_29
+            (joined
+              (portRef D3 (instanceRef mux_6))
+              (portRef DOB2 (instanceRef pdp_ram_3_3_0))))
+          (net mdout1_2_29
+            (joined
+              (portRef D2 (instanceRef mux_6))
+              (portRef DOB2 (instanceRef pdp_ram_2_3_4))))
+          (net mdout1_1_29
+            (joined
+              (portRef D1 (instanceRef mux_6))
+              (portRef DOB2 (instanceRef pdp_ram_1_3_8))))
+          (net mdout1_0_29
+            (joined
+              (portRef D0 (instanceRef mux_6))
+              (portRef DOB2 (instanceRef pdp_ram_0_3_12))))
+          (net mdout1_3_30
+            (joined
+              (portRef D3 (instanceRef mux_5))
+              (portRef DOB3 (instanceRef pdp_ram_3_3_0))))
+          (net mdout1_2_30
+            (joined
+              (portRef D2 (instanceRef mux_5))
+              (portRef DOB3 (instanceRef pdp_ram_2_3_4))))
+          (net mdout1_1_30
+            (joined
+              (portRef D1 (instanceRef mux_5))
+              (portRef DOB3 (instanceRef pdp_ram_1_3_8))))
+          (net mdout1_0_30
+            (joined
+              (portRef D0 (instanceRef mux_5))
+              (portRef DOB3 (instanceRef pdp_ram_0_3_12))))
+          (net mdout1_3_31
+            (joined
+              (portRef D3 (instanceRef mux_4))
+              (portRef DOB4 (instanceRef pdp_ram_3_3_0))))
+          (net mdout1_2_31
+            (joined
+              (portRef D2 (instanceRef mux_4))
+              (portRef DOB4 (instanceRef pdp_ram_2_3_4))))
+          (net mdout1_1_31
+            (joined
+              (portRef D1 (instanceRef mux_4))
+              (portRef DOB4 (instanceRef pdp_ram_1_3_8))))
+          (net mdout1_0_31
+            (joined
+              (portRef D0 (instanceRef mux_4))
+              (portRef DOB4 (instanceRef pdp_ram_0_3_12))))
+          (net mdout1_3_32
+            (joined
+              (portRef D3 (instanceRef mux_3))
+              (portRef DOB5 (instanceRef pdp_ram_3_3_0))))
+          (net mdout1_2_32
+            (joined
+              (portRef D2 (instanceRef mux_3))
+              (portRef DOB5 (instanceRef pdp_ram_2_3_4))))
+          (net mdout1_1_32
+            (joined
+              (portRef D1 (instanceRef mux_3))
+              (portRef DOB5 (instanceRef pdp_ram_1_3_8))))
+          (net mdout1_0_32
+            (joined
+              (portRef D0 (instanceRef mux_3))
+              (portRef DOB5 (instanceRef pdp_ram_0_3_12))))
+          (net mdout1_3_33
+            (joined
+              (portRef D3 (instanceRef mux_2))
+              (portRef DOB6 (instanceRef pdp_ram_3_3_0))))
+          (net mdout1_2_33
+            (joined
+              (portRef D2 (instanceRef mux_2))
+              (portRef DOB6 (instanceRef pdp_ram_2_3_4))))
+          (net mdout1_1_33
+            (joined
+              (portRef D1 (instanceRef mux_2))
+              (portRef DOB6 (instanceRef pdp_ram_1_3_8))))
+          (net mdout1_0_33
+            (joined
+              (portRef D0 (instanceRef mux_2))
+              (portRef DOB6 (instanceRef pdp_ram_0_3_12))))
+          (net mdout1_3_34
+            (joined
+              (portRef D3 (instanceRef mux_1))
+              (portRef DOB7 (instanceRef pdp_ram_3_3_0))))
+          (net mdout1_2_34
+            (joined
+              (portRef D2 (instanceRef mux_1))
+              (portRef DOB7 (instanceRef pdp_ram_2_3_4))))
+          (net mdout1_1_34
+            (joined
+              (portRef D1 (instanceRef mux_1))
+              (portRef DOB7 (instanceRef pdp_ram_1_3_8))))
+          (net mdout1_0_34
+            (joined
+              (portRef D0 (instanceRef mux_1))
+              (portRef DOB7 (instanceRef pdp_ram_0_3_12))))
+          (net rptr_12_ff2
+            (joined
+              (portRef SD2 (instanceRef mux_0))
+              (portRef Q (instanceRef FF_15))
+              (portRef SD2 (instanceRef mux_35))
+              (portRef SD2 (instanceRef mux_34))
+              (portRef SD2 (instanceRef mux_33))
+              (portRef SD2 (instanceRef mux_32))
+              (portRef SD2 (instanceRef mux_31))
+              (portRef SD2 (instanceRef mux_30))
+              (portRef SD2 (instanceRef mux_29))
+              (portRef SD2 (instanceRef mux_28))
+              (portRef SD2 (instanceRef mux_27))
+              (portRef SD2 (instanceRef mux_26))
+              (portRef SD2 (instanceRef mux_25))
+              (portRef SD2 (instanceRef mux_24))
+              (portRef SD2 (instanceRef mux_23))
+              (portRef SD2 (instanceRef mux_22))
+              (portRef SD2 (instanceRef mux_21))
+              (portRef SD2 (instanceRef mux_20))
+              (portRef SD2 (instanceRef mux_19))
+              (portRef SD2 (instanceRef mux_18))
+              (portRef SD2 (instanceRef mux_17))
+              (portRef SD2 (instanceRef mux_16))
+              (portRef SD2 (instanceRef mux_15))
+              (portRef SD2 (instanceRef mux_14))
+              (portRef SD2 (instanceRef mux_13))
+              (portRef SD2 (instanceRef mux_12))
+              (portRef SD2 (instanceRef mux_11))
+              (portRef SD2 (instanceRef mux_10))
+              (portRef SD2 (instanceRef mux_9))
+              (portRef SD2 (instanceRef mux_8))
+              (portRef SD2 (instanceRef mux_7))
+              (portRef SD2 (instanceRef mux_6))
+              (portRef SD2 (instanceRef mux_5))
+              (portRef SD2 (instanceRef mux_4))
+              (portRef SD2 (instanceRef mux_3))
+              (portRef SD2 (instanceRef mux_2))
+              (portRef SD2 (instanceRef mux_1))))
+          (net rptr_11_ff2
+            (joined
+              (portRef SD1 (instanceRef mux_0))
+              (portRef Q (instanceRef FF_16))
+              (portRef SD1 (instanceRef mux_35))
+              (portRef SD1 (instanceRef mux_34))
+              (portRef SD1 (instanceRef mux_33))
+              (portRef SD1 (instanceRef mux_32))
+              (portRef SD1 (instanceRef mux_31))
+              (portRef SD1 (instanceRef mux_30))
+              (portRef SD1 (instanceRef mux_29))
+              (portRef SD1 (instanceRef mux_28))
+              (portRef SD1 (instanceRef mux_27))
+              (portRef SD1 (instanceRef mux_26))
+              (portRef SD1 (instanceRef mux_25))
+              (portRef SD1 (instanceRef mux_24))
+              (portRef SD1 (instanceRef mux_23))
+              (portRef SD1 (instanceRef mux_22))
+              (portRef SD1 (instanceRef mux_21))
+              (portRef SD1 (instanceRef mux_20))
+              (portRef SD1 (instanceRef mux_19))
+              (portRef SD1 (instanceRef mux_18))
+              (portRef SD1 (instanceRef mux_17))
+              (portRef SD1 (instanceRef mux_16))
+              (portRef SD1 (instanceRef mux_15))
+              (portRef SD1 (instanceRef mux_14))
+              (portRef SD1 (instanceRef mux_13))
+              (portRef SD1 (instanceRef mux_12))
+              (portRef SD1 (instanceRef mux_11))
+              (portRef SD1 (instanceRef mux_10))
+              (portRef SD1 (instanceRef mux_9))
+              (portRef SD1 (instanceRef mux_8))
+              (portRef SD1 (instanceRef mux_7))
+              (portRef SD1 (instanceRef mux_6))
+              (portRef SD1 (instanceRef mux_5))
+              (portRef SD1 (instanceRef mux_4))
+              (portRef SD1 (instanceRef mux_3))
+              (portRef SD1 (instanceRef mux_2))
+              (portRef SD1 (instanceRef mux_1))))
+          (net mdout1_3_35
+            (joined
+              (portRef D3 (instanceRef mux_0))
+              (portRef DOB8 (instanceRef pdp_ram_3_3_0))))
+          (net mdout1_2_35
+            (joined
+              (portRef D2 (instanceRef mux_0))
+              (portRef DOB8 (instanceRef pdp_ram_2_3_4))))
+          (net mdout1_1_35
+            (joined
+              (portRef D1 (instanceRef mux_0))
+              (portRef DOB8 (instanceRef pdp_ram_1_3_8))))
+          (net mdout1_0_35
+            (joined
+              (portRef D0 (instanceRef mux_0))
+              (portRef DOB8 (instanceRef pdp_ram_0_3_12))))
+          (net wcnt_sub_0
+            (joined
+              (portRef S1 (instanceRef wcnt_0))
+              (portRef D (instanceRef FF_14))))
+          (net rptr_0
+            (joined
+              (portRef B1 (instanceRef wcnt_0))
+              (portRef ADB3 (instanceRef pdp_ram_0_0_15))
+              (portRef ADB3 (instanceRef pdp_ram_0_1_14))
+              (portRef ADB3 (instanceRef pdp_ram_0_2_13))
+              (portRef ADB3 (instanceRef pdp_ram_0_3_12))
+              (portRef ADB3 (instanceRef pdp_ram_1_0_11))
+              (portRef ADB3 (instanceRef pdp_ram_1_1_10))
+              (portRef ADB3 (instanceRef pdp_ram_1_2_9))
+              (portRef ADB3 (instanceRef pdp_ram_1_3_8))
+              (portRef ADB3 (instanceRef pdp_ram_2_0_7))
+              (portRef ADB3 (instanceRef pdp_ram_2_1_6))
+              (portRef ADB3 (instanceRef pdp_ram_2_2_5))
+              (portRef ADB3 (instanceRef pdp_ram_2_3_4))
+              (portRef ADB3 (instanceRef pdp_ram_3_0_3))
+              (portRef ADB3 (instanceRef pdp_ram_3_1_2))
+              (portRef ADB3 (instanceRef pdp_ram_3_2_1))
+              (portRef ADB3 (instanceRef pdp_ram_3_3_0))
+              (portRef Q (instanceRef FF_32))))
+          (net cnt_con_inv
+            (joined
+              (portRef B0 (instanceRef wcnt_0))
+              (portRef Z (instanceRef INV_0))))
+          (net wcount_0
+            (joined
+              (portRef A1 (instanceRef wcnt_0))
+              (portRef Q (instanceRef FF_74))
+              (portRef D (instanceRef FF_46))
+              (portRef A0 (instanceRef w_ctr_0))))
+          (net cnt_con
+            (joined
+              (portRef A0 (instanceRef wcnt_0))
+              (portRef Z (instanceRef AND2_t3))
+              (portRef A (instanceRef INV_0))
+              (portRef B1 (instanceRef bdcnt_bctr_cia))
+              (portRef A1 (instanceRef bdcnt_bctr_cia))
+              (portRef B1 (instanceRef bdcnt_bctr_0))
+              (portRef B0 (instanceRef bdcnt_bctr_0))
+              (portRef B1 (instanceRef bdcnt_bctr_1))
+              (portRef B0 (instanceRef bdcnt_bctr_1))
+              (portRef B1 (instanceRef bdcnt_bctr_2))
+              (portRef B0 (instanceRef bdcnt_bctr_2))
+              (portRef B1 (instanceRef bdcnt_bctr_3))
+              (portRef B0 (instanceRef bdcnt_bctr_3))
+              (portRef B1 (instanceRef bdcnt_bctr_4))
+              (portRef B0 (instanceRef bdcnt_bctr_4))
+              (portRef B1 (instanceRef bdcnt_bctr_5))
+              (portRef B0 (instanceRef bdcnt_bctr_5))
+              (portRef B1 (instanceRef bdcnt_bctr_6))
+              (portRef B0 (instanceRef bdcnt_bctr_6))))
+          (net precin
+            (joined
+              (portRef CIN (instanceRef wcnt_0))
+              (portRef COUT (instanceRef precin_inst474))))
+          (net wcnt_sub_1
+            (joined
+              (portRef S0 (instanceRef wcnt_1))
+              (portRef D (instanceRef FF_13))))
+          (net wcnt_sub_2
+            (joined
+              (portRef S1 (instanceRef wcnt_1))
+              (portRef D (instanceRef FF_12))))
+          (net rptr_2
+            (joined
+              (portRef B1 (instanceRef wcnt_1))
+              (portRef ADB5 (instanceRef pdp_ram_0_0_15))
+              (portRef ADB5 (instanceRef pdp_ram_0_1_14))
+              (portRef ADB5 (instanceRef pdp_ram_0_2_13))
+              (portRef ADB5 (instanceRef pdp_ram_0_3_12))
+              (portRef ADB5 (instanceRef pdp_ram_1_0_11))
+              (portRef ADB5 (instanceRef pdp_ram_1_1_10))
+              (portRef ADB5 (instanceRef pdp_ram_1_2_9))
+              (portRef ADB5 (instanceRef pdp_ram_1_3_8))
+              (portRef ADB5 (instanceRef pdp_ram_2_0_7))
+              (portRef ADB5 (instanceRef pdp_ram_2_1_6))
+              (portRef ADB5 (instanceRef pdp_ram_2_2_5))
+              (portRef ADB5 (instanceRef pdp_ram_2_3_4))
+              (portRef ADB5 (instanceRef pdp_ram_3_0_3))
+              (portRef ADB5 (instanceRef pdp_ram_3_1_2))
+              (portRef ADB5 (instanceRef pdp_ram_3_2_1))
+              (portRef ADB5 (instanceRef pdp_ram_3_3_0))
+              (portRef Q (instanceRef FF_30))))
+          (net rptr_1
+            (joined
+              (portRef B0 (instanceRef wcnt_1))
+              (portRef ADB4 (instanceRef pdp_ram_0_0_15))
+              (portRef ADB4 (instanceRef pdp_ram_0_1_14))
+              (portRef ADB4 (instanceRef pdp_ram_0_2_13))
+              (portRef ADB4 (instanceRef pdp_ram_0_3_12))
+              (portRef ADB4 (instanceRef pdp_ram_1_0_11))
+              (portRef ADB4 (instanceRef pdp_ram_1_1_10))
+              (portRef ADB4 (instanceRef pdp_ram_1_2_9))
+              (portRef ADB4 (instanceRef pdp_ram_1_3_8))
+              (portRef ADB4 (instanceRef pdp_ram_2_0_7))
+              (portRef ADB4 (instanceRef pdp_ram_2_1_6))
+              (portRef ADB4 (instanceRef pdp_ram_2_2_5))
+              (portRef ADB4 (instanceRef pdp_ram_2_3_4))
+              (portRef ADB4 (instanceRef pdp_ram_3_0_3))
+              (portRef ADB4 (instanceRef pdp_ram_3_1_2))
+              (portRef ADB4 (instanceRef pdp_ram_3_2_1))
+              (portRef ADB4 (instanceRef pdp_ram_3_3_0))
+              (portRef Q (instanceRef FF_31))))
+          (net wcount_2
+            (joined
+              (portRef A1 (instanceRef wcnt_1))
+              (portRef Q (instanceRef FF_72))
+              (portRef D (instanceRef FF_44))
+              (portRef A0 (instanceRef w_ctr_1))))
+          (net wcount_1
+            (joined
+              (portRef A0 (instanceRef wcnt_1))
+              (portRef Q (instanceRef FF_73))
+              (portRef D (instanceRef FF_45))
+              (portRef A1 (instanceRef w_ctr_0))))
+          (net co0_5
+            (joined
+              (portRef CIN (instanceRef wcnt_1))
+              (portRef COUT (instanceRef wcnt_0))))
+          (net wcnt_sub_3
+            (joined
+              (portRef S0 (instanceRef wcnt_2))
+              (portRef D (instanceRef FF_11))))
+          (net wcnt_sub_4
+            (joined
+              (portRef S1 (instanceRef wcnt_2))
+              (portRef D (instanceRef FF_10))))
+          (net rptr_4
+            (joined
+              (portRef B1 (instanceRef wcnt_2))
+              (portRef ADB7 (instanceRef pdp_ram_0_0_15))
+              (portRef ADB7 (instanceRef pdp_ram_0_1_14))
+              (portRef ADB7 (instanceRef pdp_ram_0_2_13))
+              (portRef ADB7 (instanceRef pdp_ram_0_3_12))
+              (portRef ADB7 (instanceRef pdp_ram_1_0_11))
+              (portRef ADB7 (instanceRef pdp_ram_1_1_10))
+              (portRef ADB7 (instanceRef pdp_ram_1_2_9))
+              (portRef ADB7 (instanceRef pdp_ram_1_3_8))
+              (portRef ADB7 (instanceRef pdp_ram_2_0_7))
+              (portRef ADB7 (instanceRef pdp_ram_2_1_6))
+              (portRef ADB7 (instanceRef pdp_ram_2_2_5))
+              (portRef ADB7 (instanceRef pdp_ram_2_3_4))
+              (portRef ADB7 (instanceRef pdp_ram_3_0_3))
+              (portRef ADB7 (instanceRef pdp_ram_3_1_2))
+              (portRef ADB7 (instanceRef pdp_ram_3_2_1))
+              (portRef ADB7 (instanceRef pdp_ram_3_3_0))
+              (portRef Q (instanceRef FF_28))))
+          (net rptr_3
+            (joined
+              (portRef B0 (instanceRef wcnt_2))
+              (portRef ADB6 (instanceRef pdp_ram_0_0_15))
+              (portRef ADB6 (instanceRef pdp_ram_0_1_14))
+              (portRef ADB6 (instanceRef pdp_ram_0_2_13))
+              (portRef ADB6 (instanceRef pdp_ram_0_3_12))
+              (portRef ADB6 (instanceRef pdp_ram_1_0_11))
+              (portRef ADB6 (instanceRef pdp_ram_1_1_10))
+              (portRef ADB6 (instanceRef pdp_ram_1_2_9))
+              (portRef ADB6 (instanceRef pdp_ram_1_3_8))
+              (portRef ADB6 (instanceRef pdp_ram_2_0_7))
+              (portRef ADB6 (instanceRef pdp_ram_2_1_6))
+              (portRef ADB6 (instanceRef pdp_ram_2_2_5))
+              (portRef ADB6 (instanceRef pdp_ram_2_3_4))
+              (portRef ADB6 (instanceRef pdp_ram_3_0_3))
+              (portRef ADB6 (instanceRef pdp_ram_3_1_2))
+              (portRef ADB6 (instanceRef pdp_ram_3_2_1))
+              (portRef ADB6 (instanceRef pdp_ram_3_3_0))
+              (portRef Q (instanceRef FF_29))))
+          (net wcount_4
+            (joined
+              (portRef A1 (instanceRef wcnt_2))
+              (portRef Q (instanceRef FF_70))
+              (portRef D (instanceRef FF_42))
+              (portRef A0 (instanceRef w_ctr_2))))
+          (net wcount_3
+            (joined
+              (portRef A0 (instanceRef wcnt_2))
+              (portRef Q (instanceRef FF_71))
+              (portRef D (instanceRef FF_43))
+              (portRef A1 (instanceRef w_ctr_1))))
+          (net co1_5
+            (joined
+              (portRef CIN (instanceRef wcnt_2))
+              (portRef COUT (instanceRef wcnt_1))))
+          (net wcnt_sub_5
+            (joined
+              (portRef S0 (instanceRef wcnt_3))
+              (portRef D (instanceRef FF_9))))
+          (net wcnt_sub_6
+            (joined
+              (portRef S1 (instanceRef wcnt_3))
+              (portRef D (instanceRef FF_8))))
+          (net rptr_6
+            (joined
+              (portRef B1 (instanceRef wcnt_3))
+              (portRef ADB9 (instanceRef pdp_ram_0_0_15))
+              (portRef ADB9 (instanceRef pdp_ram_0_1_14))
+              (portRef ADB9 (instanceRef pdp_ram_0_2_13))
+              (portRef ADB9 (instanceRef pdp_ram_0_3_12))
+              (portRef ADB9 (instanceRef pdp_ram_1_0_11))
+              (portRef ADB9 (instanceRef pdp_ram_1_1_10))
+              (portRef ADB9 (instanceRef pdp_ram_1_2_9))
+              (portRef ADB9 (instanceRef pdp_ram_1_3_8))
+              (portRef ADB9 (instanceRef pdp_ram_2_0_7))
+              (portRef ADB9 (instanceRef pdp_ram_2_1_6))
+              (portRef ADB9 (instanceRef pdp_ram_2_2_5))
+              (portRef ADB9 (instanceRef pdp_ram_2_3_4))
+              (portRef ADB9 (instanceRef pdp_ram_3_0_3))
+              (portRef ADB9 (instanceRef pdp_ram_3_1_2))
+              (portRef ADB9 (instanceRef pdp_ram_3_2_1))
+              (portRef ADB9 (instanceRef pdp_ram_3_3_0))
+              (portRef Q (instanceRef FF_26))))
+          (net rptr_5
+            (joined
+              (portRef B0 (instanceRef wcnt_3))
+              (portRef ADB8 (instanceRef pdp_ram_0_0_15))
+              (portRef ADB8 (instanceRef pdp_ram_0_1_14))
+              (portRef ADB8 (instanceRef pdp_ram_0_2_13))
+              (portRef ADB8 (instanceRef pdp_ram_0_3_12))
+              (portRef ADB8 (instanceRef pdp_ram_1_0_11))
+              (portRef ADB8 (instanceRef pdp_ram_1_1_10))
+              (portRef ADB8 (instanceRef pdp_ram_1_2_9))
+              (portRef ADB8 (instanceRef pdp_ram_1_3_8))
+              (portRef ADB8 (instanceRef pdp_ram_2_0_7))
+              (portRef ADB8 (instanceRef pdp_ram_2_1_6))
+              (portRef ADB8 (instanceRef pdp_ram_2_2_5))
+              (portRef ADB8 (instanceRef pdp_ram_2_3_4))
+              (portRef ADB8 (instanceRef pdp_ram_3_0_3))
+              (portRef ADB8 (instanceRef pdp_ram_3_1_2))
+              (portRef ADB8 (instanceRef pdp_ram_3_2_1))
+              (portRef ADB8 (instanceRef pdp_ram_3_3_0))
+              (portRef Q (instanceRef FF_27))))
+          (net wcount_6
+            (joined
+              (portRef A1 (instanceRef wcnt_3))
+              (portRef Q (instanceRef FF_68))
+              (portRef D (instanceRef FF_40))
+              (portRef A0 (instanceRef w_ctr_3))))
+          (net wcount_5
+            (joined
+              (portRef A0 (instanceRef wcnt_3))
+              (portRef Q (instanceRef FF_69))
+              (portRef D (instanceRef FF_41))
+              (portRef A1 (instanceRef w_ctr_2))))
+          (net co2_5
+            (joined
+              (portRef CIN (instanceRef wcnt_3))
+              (portRef COUT (instanceRef wcnt_2))))
+          (net wcnt_sub_7
+            (joined
+              (portRef S0 (instanceRef wcnt_4))
+              (portRef D (instanceRef FF_7))))
+          (net wcnt_sub_8
+            (joined
+              (portRef S1 (instanceRef wcnt_4))
+              (portRef D (instanceRef FF_6))))
+          (net rptr_8
+            (joined
+              (portRef B1 (instanceRef wcnt_4))
+              (portRef ADB11 (instanceRef pdp_ram_0_0_15))
+              (portRef ADB11 (instanceRef pdp_ram_0_1_14))
+              (portRef ADB11 (instanceRef pdp_ram_0_2_13))
+              (portRef ADB11 (instanceRef pdp_ram_0_3_12))
+              (portRef ADB11 (instanceRef pdp_ram_1_0_11))
+              (portRef ADB11 (instanceRef pdp_ram_1_1_10))
+              (portRef ADB11 (instanceRef pdp_ram_1_2_9))
+              (portRef ADB11 (instanceRef pdp_ram_1_3_8))
+              (portRef ADB11 (instanceRef pdp_ram_2_0_7))
+              (portRef ADB11 (instanceRef pdp_ram_2_1_6))
+              (portRef ADB11 (instanceRef pdp_ram_2_2_5))
+              (portRef ADB11 (instanceRef pdp_ram_2_3_4))
+              (portRef ADB11 (instanceRef pdp_ram_3_0_3))
+              (portRef ADB11 (instanceRef pdp_ram_3_1_2))
+              (portRef ADB11 (instanceRef pdp_ram_3_2_1))
+              (portRef ADB11 (instanceRef pdp_ram_3_3_0))
+              (portRef Q (instanceRef FF_24))))
+          (net rptr_7
+            (joined
+              (portRef B0 (instanceRef wcnt_4))
+              (portRef ADB10 (instanceRef pdp_ram_0_0_15))
+              (portRef ADB10 (instanceRef pdp_ram_0_1_14))
+              (portRef ADB10 (instanceRef pdp_ram_0_2_13))
+              (portRef ADB10 (instanceRef pdp_ram_0_3_12))
+              (portRef ADB10 (instanceRef pdp_ram_1_0_11))
+              (portRef ADB10 (instanceRef pdp_ram_1_1_10))
+              (portRef ADB10 (instanceRef pdp_ram_1_2_9))
+              (portRef ADB10 (instanceRef pdp_ram_1_3_8))
+              (portRef ADB10 (instanceRef pdp_ram_2_0_7))
+              (portRef ADB10 (instanceRef pdp_ram_2_1_6))
+              (portRef ADB10 (instanceRef pdp_ram_2_2_5))
+              (portRef ADB10 (instanceRef pdp_ram_2_3_4))
+              (portRef ADB10 (instanceRef pdp_ram_3_0_3))
+              (portRef ADB10 (instanceRef pdp_ram_3_1_2))
+              (portRef ADB10 (instanceRef pdp_ram_3_2_1))
+              (portRef ADB10 (instanceRef pdp_ram_3_3_0))
+              (portRef Q (instanceRef FF_25))))
+          (net wcount_8
+            (joined
+              (portRef A1 (instanceRef wcnt_4))
+              (portRef Q (instanceRef FF_66))
+              (portRef D (instanceRef FF_38))
+              (portRef A0 (instanceRef w_ctr_4))))
+          (net wcount_7
+            (joined
+              (portRef A0 (instanceRef wcnt_4))
+              (portRef Q (instanceRef FF_67))
+              (portRef D (instanceRef FF_39))
+              (portRef A1 (instanceRef w_ctr_3))))
+          (net co3_5
+            (joined
+              (portRef CIN (instanceRef wcnt_4))
+              (portRef COUT (instanceRef wcnt_3))))
+          (net wcnt_sub_9
+            (joined
+              (portRef S0 (instanceRef wcnt_5))
+              (portRef D (instanceRef FF_5))))
+          (net wcnt_sub_10
+            (joined
+              (portRef S1 (instanceRef wcnt_5))
+              (portRef D (instanceRef FF_4))))
+          (net rptr_10
+            (joined
+              (portRef B1 (instanceRef wcnt_5))
+              (portRef ADB13 (instanceRef pdp_ram_0_0_15))
+              (portRef ADB13 (instanceRef pdp_ram_0_1_14))
+              (portRef ADB13 (instanceRef pdp_ram_0_2_13))
+              (portRef ADB13 (instanceRef pdp_ram_0_3_12))
+              (portRef ADB13 (instanceRef pdp_ram_1_0_11))
+              (portRef ADB13 (instanceRef pdp_ram_1_1_10))
+              (portRef ADB13 (instanceRef pdp_ram_1_2_9))
+              (portRef ADB13 (instanceRef pdp_ram_1_3_8))
+              (portRef ADB13 (instanceRef pdp_ram_2_0_7))
+              (portRef ADB13 (instanceRef pdp_ram_2_1_6))
+              (portRef ADB13 (instanceRef pdp_ram_2_2_5))
+              (portRef ADB13 (instanceRef pdp_ram_2_3_4))
+              (portRef ADB13 (instanceRef pdp_ram_3_0_3))
+              (portRef ADB13 (instanceRef pdp_ram_3_1_2))
+              (portRef ADB13 (instanceRef pdp_ram_3_2_1))
+              (portRef ADB13 (instanceRef pdp_ram_3_3_0))
+              (portRef Q (instanceRef FF_22))))
+          (net rptr_9
+            (joined
+              (portRef B0 (instanceRef wcnt_5))
+              (portRef ADB12 (instanceRef pdp_ram_0_0_15))
+              (portRef ADB12 (instanceRef pdp_ram_0_1_14))
+              (portRef ADB12 (instanceRef pdp_ram_0_2_13))
+              (portRef ADB12 (instanceRef pdp_ram_0_3_12))
+              (portRef ADB12 (instanceRef pdp_ram_1_0_11))
+              (portRef ADB12 (instanceRef pdp_ram_1_1_10))
+              (portRef ADB12 (instanceRef pdp_ram_1_2_9))
+              (portRef ADB12 (instanceRef pdp_ram_1_3_8))
+              (portRef ADB12 (instanceRef pdp_ram_2_0_7))
+              (portRef ADB12 (instanceRef pdp_ram_2_1_6))
+              (portRef ADB12 (instanceRef pdp_ram_2_2_5))
+              (portRef ADB12 (instanceRef pdp_ram_2_3_4))
+              (portRef ADB12 (instanceRef pdp_ram_3_0_3))
+              (portRef ADB12 (instanceRef pdp_ram_3_1_2))
+              (portRef ADB12 (instanceRef pdp_ram_3_2_1))
+              (portRef ADB12 (instanceRef pdp_ram_3_3_0))
+              (portRef Q (instanceRef FF_23))))
+          (net wcount_10
+            (joined
+              (portRef A1 (instanceRef wcnt_5))
+              (portRef Q (instanceRef FF_64))
+              (portRef D (instanceRef FF_36))
+              (portRef A0 (instanceRef w_ctr_5))))
+          (net wcount_9
+            (joined
+              (portRef A0 (instanceRef wcnt_5))
+              (portRef Q (instanceRef FF_65))
+              (portRef D (instanceRef FF_37))
+              (portRef A1 (instanceRef w_ctr_4))))
+          (net co4_5
+            (joined
+              (portRef CIN (instanceRef wcnt_5))
+              (portRef COUT (instanceRef wcnt_4))))
+          (net wcnt_sub_11
+            (joined
+              (portRef S0 (instanceRef wcnt_6))
+              (portRef D (instanceRef FF_3))))
+          (net wcnt_sub_12
+            (joined
+              (portRef S1 (instanceRef wcnt_6))
+              (portRef D (instanceRef FF_2))))
+          (net rptr_12
+            (joined
+              (portRef B1 (instanceRef wcnt_6))
+              (portRef CSB1 (instanceRef pdp_ram_0_0_15))
+              (portRef CSB1 (instanceRef pdp_ram_0_1_14))
+              (portRef CSB1 (instanceRef pdp_ram_0_2_13))
+              (portRef CSB1 (instanceRef pdp_ram_0_3_12))
+              (portRef CSB1 (instanceRef pdp_ram_1_0_11))
+              (portRef CSB1 (instanceRef pdp_ram_1_1_10))
+              (portRef CSB1 (instanceRef pdp_ram_1_2_9))
+              (portRef CSB1 (instanceRef pdp_ram_1_3_8))
+              (portRef CSB1 (instanceRef pdp_ram_2_0_7))
+              (portRef CSB1 (instanceRef pdp_ram_2_1_6))
+              (portRef CSB1 (instanceRef pdp_ram_2_2_5))
+              (portRef CSB1 (instanceRef pdp_ram_2_3_4))
+              (portRef CSB1 (instanceRef pdp_ram_3_0_3))
+              (portRef CSB1 (instanceRef pdp_ram_3_1_2))
+              (portRef CSB1 (instanceRef pdp_ram_3_2_1))
+              (portRef CSB1 (instanceRef pdp_ram_3_3_0))
+              (portRef Q (instanceRef FF_20))
+              (portRef D (instanceRef FF_17))))
+          (net rptr_11
+            (joined
+              (portRef B0 (instanceRef wcnt_6))
+              (portRef CSB0 (instanceRef pdp_ram_0_0_15))
+              (portRef CSB0 (instanceRef pdp_ram_0_1_14))
+              (portRef CSB0 (instanceRef pdp_ram_0_2_13))
+              (portRef CSB0 (instanceRef pdp_ram_0_3_12))
+              (portRef CSB0 (instanceRef pdp_ram_1_0_11))
+              (portRef CSB0 (instanceRef pdp_ram_1_1_10))
+              (portRef CSB0 (instanceRef pdp_ram_1_2_9))
+              (portRef CSB0 (instanceRef pdp_ram_1_3_8))
+              (portRef CSB0 (instanceRef pdp_ram_2_0_7))
+              (portRef CSB0 (instanceRef pdp_ram_2_1_6))
+              (portRef CSB0 (instanceRef pdp_ram_2_2_5))
+              (portRef CSB0 (instanceRef pdp_ram_2_3_4))
+              (portRef CSB0 (instanceRef pdp_ram_3_0_3))
+              (portRef CSB0 (instanceRef pdp_ram_3_1_2))
+              (portRef CSB0 (instanceRef pdp_ram_3_2_1))
+              (portRef CSB0 (instanceRef pdp_ram_3_3_0))
+              (portRef Q (instanceRef FF_21))
+              (portRef D (instanceRef FF_18))))
+          (net wcount_12
+            (joined
+              (portRef A1 (instanceRef wcnt_6))
+              (portRef Q (instanceRef FF_62))
+              (portRef D (instanceRef FF_34))
+              (portRef A0 (instanceRef w_ctr_6))))
+          (net wcount_11
+            (joined
+              (portRef A0 (instanceRef wcnt_6))
+              (portRef Q (instanceRef FF_63))
+              (portRef D (instanceRef FF_35))
+              (portRef A1 (instanceRef w_ctr_5))))
+          (net co5_5
+            (joined
+              (portRef CIN (instanceRef wcnt_6))
+              (portRef COUT (instanceRef wcnt_5))))
+          (net wcnt_sub_13
+            (joined
+              (portRef S0 (instanceRef wcnt_7))
+              (portRef D (instanceRef FF_1))))
+          (net wcnt_sub_msb
+            (joined
+              (portRef A0 (instanceRef wcnt_7))
+              (portRef Z (instanceRef XOR2_t0))))
+          (net co6_3
+            (joined
+              (portRef CIN (instanceRef wcnt_7))
+              (portRef COUT (instanceRef wcnt_6))))
+          (net wren_i
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_ci_a))
+              (portRef Z (instanceRef AND2_t5))
+              (portRef A (instanceRef AND2_t3))
+              (portRef A (instanceRef XOR2_t2))
+              (portRef A (instanceRef INV_2))
+              (portRef AD1 (instanceRef LUT4_1))
+              (portRef A (instanceRef INV_1))
+              (portRef OCEA (instanceRef pdp_ram_0_0_15))
+              (portRef CEA (instanceRef pdp_ram_0_0_15))
+              (portRef OCEA (instanceRef pdp_ram_0_1_14))
+              (portRef CEA (instanceRef pdp_ram_0_1_14))
+              (portRef OCEA (instanceRef pdp_ram_0_2_13))
+              (portRef CEA (instanceRef pdp_ram_0_2_13))
+              (portRef OCEA (instanceRef pdp_ram_0_3_12))
+              (portRef CEA (instanceRef pdp_ram_0_3_12))
+              (portRef OCEA (instanceRef pdp_ram_1_0_11))
+              (portRef CEA (instanceRef pdp_ram_1_0_11))
+              (portRef OCEA (instanceRef pdp_ram_1_1_10))
+              (portRef CEA (instanceRef pdp_ram_1_1_10))
+              (portRef OCEA (instanceRef pdp_ram_1_2_9))
+              (portRef CEA (instanceRef pdp_ram_1_2_9))
+              (portRef OCEA (instanceRef pdp_ram_1_3_8))
+              (portRef CEA (instanceRef pdp_ram_1_3_8))
+              (portRef OCEA (instanceRef pdp_ram_2_0_7))
+              (portRef CEA (instanceRef pdp_ram_2_0_7))
+              (portRef OCEA (instanceRef pdp_ram_2_1_6))
+              (portRef CEA (instanceRef pdp_ram_2_1_6))
+              (portRef OCEA (instanceRef pdp_ram_2_2_5))
+              (portRef CEA (instanceRef pdp_ram_2_2_5))
+              (portRef OCEA (instanceRef pdp_ram_2_3_4))
+              (portRef CEA (instanceRef pdp_ram_2_3_4))
+              (portRef OCEA (instanceRef pdp_ram_3_0_3))
+              (portRef CEA (instanceRef pdp_ram_3_0_3))
+              (portRef OCEA (instanceRef pdp_ram_3_1_2))
+              (portRef CEA (instanceRef pdp_ram_3_1_2))
+              (portRef OCEA (instanceRef pdp_ram_3_2_1))
+              (portRef CEA (instanceRef pdp_ram_3_2_1))
+              (portRef OCEA (instanceRef pdp_ram_3_3_0))
+              (portRef CEA (instanceRef pdp_ram_3_3_0))
+              (portRef SP (instanceRef FF_74))
+              (portRef SP (instanceRef FF_73))
+              (portRef SP (instanceRef FF_72))
+              (portRef SP (instanceRef FF_71))
+              (portRef SP (instanceRef FF_70))
+              (portRef SP (instanceRef FF_69))
+              (portRef SP (instanceRef FF_68))
+              (portRef SP (instanceRef FF_67))
+              (portRef SP (instanceRef FF_66))
+              (portRef SP (instanceRef FF_65))
+              (portRef SP (instanceRef FF_64))
+              (portRef SP (instanceRef FF_63))
+              (portRef SP (instanceRef FF_62))
+              (portRef SP (instanceRef FF_61))
+              (portRef SP (instanceRef FF_46))
+              (portRef SP (instanceRef FF_45))
+              (portRef SP (instanceRef FF_44))
+              (portRef SP (instanceRef FF_43))
+              (portRef SP (instanceRef FF_42))
+              (portRef SP (instanceRef FF_41))
+              (portRef SP (instanceRef FF_40))
+              (portRef SP (instanceRef FF_39))
+              (portRef SP (instanceRef FF_38))
+              (portRef SP (instanceRef FF_37))
+              (portRef SP (instanceRef FF_36))
+              (portRef SP (instanceRef FF_35))
+              (portRef SP (instanceRef FF_34))
+              (portRef SP (instanceRef FF_33))
+              (portRef B0 (instanceRef g_cmp_0))
+              (portRef B1 (instanceRef g_cmp_0))
+              (portRef B0 (instanceRef g_cmp_1))
+              (portRef B1 (instanceRef g_cmp_1))
+              (portRef B0 (instanceRef g_cmp_2))
+              (portRef B1 (instanceRef g_cmp_2))
+              (portRef B0 (instanceRef g_cmp_3))
+              (portRef B1 (instanceRef g_cmp_3))
+              (portRef B0 (instanceRef g_cmp_4))
+              (portRef B1 (instanceRef g_cmp_4))
+              (portRef B0 (instanceRef g_cmp_5))
+              (portRef B1 (instanceRef g_cmp_5))
+              (portRef B0 (instanceRef g_cmp_6))
+              (portRef B1 (instanceRef af_set_cmp_ci_a))))
+          (net x
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_ci_a))
+              (portRef CIN (instanceRef bdcnt_bctr_cia))
+              (portRef CIN (instanceRef e_cmp_ci_a))
+              (portRef CIN (instanceRef g_cmp_ci_a))
+              (portRef CIN (instanceRef w_ctr_cia))
+              (portRef CIN (instanceRef r_ctr_cia))
+              (portRef CIN (instanceRef precin_inst474))))
+          (net cmp_ci_2
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_0))
+              (portRef COUT (instanceRef af_set_cmp_ci_a))))
+          (net wcnt_reg_0
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_0))
+              (portRef Q (instanceRef FF_14))))
+          (net wcnt_reg_1
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_0))
+              (portRef Q (instanceRef FF_13))))
+          (net co0_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_1))
+              (portRef COUT (instanceRef af_set_cmp_0))))
+          (net wcnt_reg_2
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_1))
+              (portRef Q (instanceRef FF_12))))
+          (net wcnt_reg_3
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_1))
+              (portRef Q (instanceRef FF_11))))
+          (net co1_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_2))
+              (portRef COUT (instanceRef af_set_cmp_1))))
+          (net wcnt_reg_4
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_2))
+              (portRef Q (instanceRef FF_10))))
+          (net wcnt_reg_5
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_2))
+              (portRef Q (instanceRef FF_9))))
+          (net co2_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_3))
+              (portRef COUT (instanceRef af_set_cmp_2))))
+          (net wcnt_reg_6
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_3))
+              (portRef Q (instanceRef FF_8))))
+          (net wcnt_reg_7
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_3))
+              (portRef Q (instanceRef FF_7))))
+          (net co3_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_4))
+              (portRef COUT (instanceRef af_set_cmp_3))))
+          (net wcnt_reg_8
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_4))
+              (portRef Q (instanceRef FF_6))))
+          (net wcnt_reg_9
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_4))
+              (portRef Q (instanceRef FF_5))))
+          (net co4_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_5))
+              (portRef COUT (instanceRef af_set_cmp_4))))
+          (net wcnt_reg_10
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_5))
+              (portRef Q (instanceRef FF_4))))
+          (net wcnt_reg_11
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_5))
+              (portRef Q (instanceRef FF_3))))
+          (net co5_6
+            (joined
+              (portRef CIN (instanceRef af_set_cmp_6))
+              (portRef COUT (instanceRef af_set_cmp_5))))
+          (net wcnt_reg_12
+            (joined
+              (portRef A0 (instanceRef af_set_cmp_6))
+              (portRef Q (instanceRef FF_2))))
+          (net wcnt_reg_13
+            (joined
+              (portRef A1 (instanceRef af_set_cmp_6))
+              (portRef Q (instanceRef FF_1))))
+          (net af_set
+            (joined
+              (portRef S0 (instanceRef a2))
+              (portRef D (instanceRef FF_0))))
+          (net scuba_vhi
+            (joined
+              (portRef Z (instanceRef scuba_vhi_inst))
+              (portRef OCEB (instanceRef pdp_ram_0_0_15))
+              (portRef WEA (instanceRef pdp_ram_0_0_15))
+              (portRef OCEB (instanceRef pdp_ram_0_1_14))
+              (portRef WEA (instanceRef pdp_ram_0_1_14))
+              (portRef OCEB (instanceRef pdp_ram_0_2_13))
+              (portRef WEA (instanceRef pdp_ram_0_2_13))
+              (portRef OCEB (instanceRef pdp_ram_0_3_12))
+              (portRef WEA (instanceRef pdp_ram_0_3_12))
+              (portRef OCEB (instanceRef pdp_ram_1_0_11))
+              (portRef WEA (instanceRef pdp_ram_1_0_11))
+              (portRef OCEB (instanceRef pdp_ram_1_1_10))
+              (portRef WEA (instanceRef pdp_ram_1_1_10))
+              (portRef OCEB (instanceRef pdp_ram_1_2_9))
+              (portRef WEA (instanceRef pdp_ram_1_2_9))
+              (portRef OCEB (instanceRef pdp_ram_1_3_8))
+              (portRef WEA (instanceRef pdp_ram_1_3_8))
+              (portRef OCEB (instanceRef pdp_ram_2_0_7))
+              (portRef WEA (instanceRef pdp_ram_2_0_7))
+              (portRef OCEB (instanceRef pdp_ram_2_1_6))
+              (portRef WEA (instanceRef pdp_ram_2_1_6))
+              (portRef OCEB (instanceRef pdp_ram_2_2_5))
+              (portRef WEA (instanceRef pdp_ram_2_2_5))
+              (portRef OCEB (instanceRef pdp_ram_2_3_4))
+              (portRef WEA (instanceRef pdp_ram_2_3_4))
+              (portRef OCEB (instanceRef pdp_ram_3_0_3))
+              (portRef WEA (instanceRef pdp_ram_3_0_3))
+              (portRef OCEB (instanceRef pdp_ram_3_1_2))
+              (portRef WEA (instanceRef pdp_ram_3_1_2))
+              (portRef OCEB (instanceRef pdp_ram_3_2_1))
+              (portRef WEA (instanceRef pdp_ram_3_2_1))
+              (portRef OCEB (instanceRef pdp_ram_3_3_0))
+              (portRef WEA (instanceRef pdp_ram_3_3_0))
+              (portRef C1 (instanceRef bdcnt_bctr_cia))
+              (portRef C0 (instanceRef bdcnt_bctr_cia))
+              (portRef D1 (instanceRef bdcnt_bctr_cia))
+              (portRef D0 (instanceRef bdcnt_bctr_cia))
+              (portRef D1 (instanceRef bdcnt_bctr_0))
+              (portRef D0 (instanceRef bdcnt_bctr_0))
+              (portRef C1 (instanceRef bdcnt_bctr_0))
+              (portRef C0 (instanceRef bdcnt_bctr_0))
+              (portRef D1 (instanceRef bdcnt_bctr_1))
+              (portRef D0 (instanceRef bdcnt_bctr_1))
+              (portRef C1 (instanceRef bdcnt_bctr_1))
+              (portRef C0 (instanceRef bdcnt_bctr_1))
+              (portRef D1 (instanceRef bdcnt_bctr_2))
+              (portRef D0 (instanceRef bdcnt_bctr_2))
+              (portRef C1 (instanceRef bdcnt_bctr_2))
+              (portRef C0 (instanceRef bdcnt_bctr_2))
+              (portRef D1 (instanceRef bdcnt_bctr_3))
+              (portRef D0 (instanceRef bdcnt_bctr_3))
+              (portRef C1 (instanceRef bdcnt_bctr_3))
+              (portRef C0 (instanceRef bdcnt_bctr_3))
+              (portRef D1 (instanceRef bdcnt_bctr_4))
+              (portRef D0 (instanceRef bdcnt_bctr_4))
+              (portRef C1 (instanceRef bdcnt_bctr_4))
+              (portRef C0 (instanceRef bdcnt_bctr_4))
+              (portRef D1 (instanceRef bdcnt_bctr_5))
+              (portRef D0 (instanceRef bdcnt_bctr_5))
+              (portRef C1 (instanceRef bdcnt_bctr_5))
+              (portRef C0 (instanceRef bdcnt_bctr_5))
+              (portRef D1 (instanceRef bdcnt_bctr_6))
+              (portRef D0 (instanceRef bdcnt_bctr_6))
+              (portRef C1 (instanceRef bdcnt_bctr_6))
+              (portRef C0 (instanceRef bdcnt_bctr_6))
+              (portRef C1 (instanceRef e_cmp_ci_a))
+              (portRef C0 (instanceRef e_cmp_ci_a))
+              (portRef D1 (instanceRef e_cmp_ci_a))
+              (portRef D0 (instanceRef e_cmp_ci_a))
+              (portRef B1 (instanceRef e_cmp_ci_a))
+              (portRef B0 (instanceRef e_cmp_ci_a))
+              (portRef A1 (instanceRef e_cmp_ci_a))
+              (portRef A0 (instanceRef e_cmp_ci_a))
+              (portRef D1 (instanceRef e_cmp_0))
+              (portRef D0 (instanceRef e_cmp_0))
+              (portRef C1 (instanceRef e_cmp_0))
+              (portRef C0 (instanceRef e_cmp_0))
+              (portRef D1 (instanceRef e_cmp_1))
+              (portRef D0 (instanceRef e_cmp_1))
+              (portRef C1 (instanceRef e_cmp_1))
+              (portRef C0 (instanceRef e_cmp_1))
+              (portRef D1 (instanceRef e_cmp_2))
+              (portRef D0 (instanceRef e_cmp_2))
+              (portRef C1 (instanceRef e_cmp_2))
+              (portRef C0 (instanceRef e_cmp_2))
+              (portRef D1 (instanceRef e_cmp_3))
+              (portRef D0 (instanceRef e_cmp_3))
+              (portRef C1 (instanceRef e_cmp_3))
+              (portRef C0 (instanceRef e_cmp_3))
+              (portRef D1 (instanceRef e_cmp_4))
+              (portRef D0 (instanceRef e_cmp_4))
+              (portRef C1 (instanceRef e_cmp_4))
+              (portRef C0 (instanceRef e_cmp_4))
+              (portRef D1 (instanceRef e_cmp_5))
+              (portRef D0 (instanceRef e_cmp_5))
+              (portRef C1 (instanceRef e_cmp_5))
+              (portRef C0 (instanceRef e_cmp_5))
+              (portRef D1 (instanceRef e_cmp_6))
+              (portRef D0 (instanceRef e_cmp_6))
+              (portRef C1 (instanceRef e_cmp_6))
+              (portRef C0 (instanceRef e_cmp_6))
+              (portRef C1 (instanceRef a0))
+              (portRef C0 (instanceRef a0))
+              (portRef D1 (instanceRef a0))
+              (portRef D0 (instanceRef a0))
+              (portRef C1 (instanceRef g_cmp_ci_a))
+              (portRef C0 (instanceRef g_cmp_ci_a))
+              (portRef D1 (instanceRef g_cmp_ci_a))
+              (portRef D0 (instanceRef g_cmp_ci_a))
+              (portRef B1 (instanceRef g_cmp_ci_a))
+              (portRef B0 (instanceRef g_cmp_ci_a))
+              (portRef A1 (instanceRef g_cmp_ci_a))
+              (portRef A0 (instanceRef g_cmp_ci_a))
+              (portRef D1 (instanceRef g_cmp_0))
+              (portRef D0 (instanceRef g_cmp_0))
+              (portRef C1 (instanceRef g_cmp_0))
+              (portRef C0 (instanceRef g_cmp_0))
+              (portRef D1 (instanceRef g_cmp_1))
+              (portRef D0 (instanceRef g_cmp_1))
+              (portRef C1 (instanceRef g_cmp_1))
+              (portRef C0 (instanceRef g_cmp_1))
+              (portRef D1 (instanceRef g_cmp_2))
+              (portRef D0 (instanceRef g_cmp_2))
+              (portRef C1 (instanceRef g_cmp_2))
+              (portRef C0 (instanceRef g_cmp_2))
+              (portRef D1 (instanceRef g_cmp_3))
+              (portRef D0 (instanceRef g_cmp_3))
+              (portRef C1 (instanceRef g_cmp_3))
+              (portRef C0 (instanceRef g_cmp_3))
+              (portRef D1 (instanceRef g_cmp_4))
+              (portRef D0 (instanceRef g_cmp_4))
+              (portRef C1 (instanceRef g_cmp_4))
+              (portRef C0 (instanceRef g_cmp_4))
+              (portRef D1 (instanceRef g_cmp_5))
+              (portRef D0 (instanceRef g_cmp_5))
+              (portRef C1 (instanceRef g_cmp_5))
+              (portRef C0 (instanceRef g_cmp_5))
+              (portRef D1 (instanceRef g_cmp_6))
+              (portRef D0 (instanceRef g_cmp_6))
+              (portRef C1 (instanceRef g_cmp_6))
+              (portRef C0 (instanceRef g_cmp_6))
+              (portRef C1 (instanceRef a1))
+              (portRef C0 (instanceRef a1))
+              (portRef D1 (instanceRef a1))
+              (portRef D0 (instanceRef a1))
+              (portRef C1 (instanceRef w_ctr_cia))
+              (portRef C0 (instanceRef w_ctr_cia))
+              (portRef D1 (instanceRef w_ctr_cia))
+              (portRef D0 (instanceRef w_ctr_cia))
+              (portRef B1 (instanceRef w_ctr_cia))
+              (portRef A1 (instanceRef w_ctr_cia))
+              (portRef D1 (instanceRef w_ctr_0))
+              (portRef D0 (instanceRef w_ctr_0))
+              (portRef C1 (instanceRef w_ctr_0))
+              (portRef C0 (instanceRef w_ctr_0))
+              (portRef D1 (instanceRef w_ctr_1))
+              (portRef D0 (instanceRef w_ctr_1))
+              (portRef C1 (instanceRef w_ctr_1))
+              (portRef C0 (instanceRef w_ctr_1))
+              (portRef D1 (instanceRef w_ctr_2))
+              (portRef D0 (instanceRef w_ctr_2))
+              (portRef C1 (instanceRef w_ctr_2))
+              (portRef C0 (instanceRef w_ctr_2))
+              (portRef D1 (instanceRef w_ctr_3))
+              (portRef D0 (instanceRef w_ctr_3))
+              (portRef C1 (instanceRef w_ctr_3))
+              (portRef C0 (instanceRef w_ctr_3))
+              (portRef D1 (instanceRef w_ctr_4))
+              (portRef D0 (instanceRef w_ctr_4))
+              (portRef C1 (instanceRef w_ctr_4))
+              (portRef C0 (instanceRef w_ctr_4))
+              (portRef D1 (instanceRef w_ctr_5))
+              (portRef D0 (instanceRef w_ctr_5))
+              (portRef C1 (instanceRef w_ctr_5))
+              (portRef C0 (instanceRef w_ctr_5))
+              (portRef D1 (instanceRef w_ctr_6))
+              (portRef D0 (instanceRef w_ctr_6))
+              (portRef C1 (instanceRef w_ctr_6))
+              (portRef C0 (instanceRef w_ctr_6))
+              (portRef C1 (instanceRef r_ctr_cia))
+              (portRef C0 (instanceRef r_ctr_cia))
+              (portRef D1 (instanceRef r_ctr_cia))
+              (portRef D0 (instanceRef r_ctr_cia))
+              (portRef B1 (instanceRef r_ctr_cia))
+              (portRef A1 (instanceRef r_ctr_cia))
+              (portRef D1 (instanceRef r_ctr_0))
+              (portRef D0 (instanceRef r_ctr_0))
+              (portRef C1 (instanceRef r_ctr_0))
+              (portRef C0 (instanceRef r_ctr_0))
+              (portRef D1 (instanceRef r_ctr_1))
+              (portRef D0 (instanceRef r_ctr_1))
+              (portRef C1 (instanceRef r_ctr_1))
+              (portRef C0 (instanceRef r_ctr_1))
+              (portRef D1 (instanceRef r_ctr_2))
+              (portRef D0 (instanceRef r_ctr_2))
+              (portRef C1 (instanceRef r_ctr_2))
+              (portRef C0 (instanceRef r_ctr_2))
+              (portRef D1 (instanceRef r_ctr_3))
+              (portRef D0 (instanceRef r_ctr_3))
+              (portRef C1 (instanceRef r_ctr_3))
+              (portRef C0 (instanceRef r_ctr_3))
+              (portRef D1 (instanceRef r_ctr_4))
+              (portRef D0 (instanceRef r_ctr_4))
+              (portRef C1 (instanceRef r_ctr_4))
+              (portRef C0 (instanceRef r_ctr_4))
+              (portRef D1 (instanceRef r_ctr_5))
+              (portRef D0 (instanceRef r_ctr_5))
+              (portRef C1 (instanceRef r_ctr_5))
+              (portRef C0 (instanceRef r_ctr_5))
+              (portRef D1 (instanceRef r_ctr_6))
+              (portRef D0 (instanceRef r_ctr_6))
+              (portRef C1 (instanceRef r_ctr_6))
+              (portRef C0 (instanceRef r_ctr_6))
+              (portRef C1 (instanceRef precin_inst474))
+              (portRef C0 (instanceRef precin_inst474))
+              (portRef D1 (instanceRef precin_inst474))
+              (portRef D0 (instanceRef precin_inst474))
+              (portRef B1 (instanceRef precin_inst474))
+              (portRef B0 (instanceRef precin_inst474))
+              (portRef A1 (instanceRef precin_inst474))
+              (portRef A0 (instanceRef precin_inst474))
+              (portRef C1 (instanceRef wcnt_0))
+              (portRef C0 (instanceRef wcnt_0))
+              (portRef D1 (instanceRef wcnt_0))
+              (portRef D0 (instanceRef wcnt_0))
+              (portRef C1 (instanceRef wcnt_1))
+              (portRef C0 (instanceRef wcnt_1))
+              (portRef D1 (instanceRef wcnt_1))
+              (portRef D0 (instanceRef wcnt_1))
+              (portRef C1 (instanceRef wcnt_2))
+              (portRef C0 (instanceRef wcnt_2))
+              (portRef D1 (instanceRef wcnt_2))
+              (portRef D0 (instanceRef wcnt_2))
+              (portRef C1 (instanceRef wcnt_3))
+              (portRef C0 (instanceRef wcnt_3))
+              (portRef D1 (instanceRef wcnt_3))
+              (portRef D0 (instanceRef wcnt_3))
+              (portRef C1 (instanceRef wcnt_4))
+              (portRef C0 (instanceRef wcnt_4))
+              (portRef D1 (instanceRef wcnt_4))
+              (portRef D0 (instanceRef wcnt_4))
+              (portRef C1 (instanceRef wcnt_5))
+              (portRef C0 (instanceRef wcnt_5))
+              (portRef D1 (instanceRef wcnt_5))
+              (portRef D0 (instanceRef wcnt_5))
+              (portRef C1 (instanceRef wcnt_6))
+              (portRef C0 (instanceRef wcnt_6))
+              (portRef D1 (instanceRef wcnt_6))
+              (portRef D0 (instanceRef wcnt_6))
+              (portRef C1 (instanceRef wcnt_7))
+              (portRef C0 (instanceRef wcnt_7))
+              (portRef D1 (instanceRef wcnt_7))
+              (portRef D0 (instanceRef wcnt_7))
+              (portRef C1 (instanceRef af_set_cmp_ci_a))
+              (portRef C0 (instanceRef af_set_cmp_ci_a))
+              (portRef D1 (instanceRef af_set_cmp_ci_a))
+              (portRef D0 (instanceRef af_set_cmp_ci_a))
+              (portRef D1 (instanceRef af_set_cmp_0))
+              (portRef D0 (instanceRef af_set_cmp_0))
+              (portRef C1 (instanceRef af_set_cmp_0))
+              (portRef C0 (instanceRef af_set_cmp_0))
+              (portRef D1 (instanceRef af_set_cmp_1))
+              (portRef D0 (instanceRef af_set_cmp_1))
+              (portRef C1 (instanceRef af_set_cmp_1))
+              (portRef C0 (instanceRef af_set_cmp_1))
+              (portRef D1 (instanceRef af_set_cmp_2))
+              (portRef D0 (instanceRef af_set_cmp_2))
+              (portRef C1 (instanceRef af_set_cmp_2))
+              (portRef C0 (instanceRef af_set_cmp_2))
+              (portRef D1 (instanceRef af_set_cmp_3))
+              (portRef D0 (instanceRef af_set_cmp_3))
+              (portRef C1 (instanceRef af_set_cmp_3))
+              (portRef C0 (instanceRef af_set_cmp_3))
+              (portRef D1 (instanceRef af_set_cmp_4))
+              (portRef D0 (instanceRef af_set_cmp_4))
+              (portRef C1 (instanceRef af_set_cmp_4))
+              (portRef C0 (instanceRef af_set_cmp_4))
+              (portRef D1 (instanceRef af_set_cmp_5))
+              (portRef D0 (instanceRef af_set_cmp_5))
+              (portRef C1 (instanceRef af_set_cmp_5))
+              (portRef C0 (instanceRef af_set_cmp_5))
+              (portRef D1 (instanceRef af_set_cmp_6))
+              (portRef D0 (instanceRef af_set_cmp_6))
+              (portRef C1 (instanceRef af_set_cmp_6))
+              (portRef C0 (instanceRef af_set_cmp_6))
+              (portRef C1 (instanceRef a2))
+              (portRef C0 (instanceRef a2))
+              (portRef D1 (instanceRef a2))
+              (portRef D0 (instanceRef a2))))
+          (net scuba_vlo
+            (joined
+              (portRef Z (instanceRef scuba_vlo_inst))
+              (portRef AD3 (instanceRef LUT4_1))
+              (portRef AD3 (instanceRef LUT4_0))
+              (portRef CSB2 (instanceRef pdp_ram_0_0_15))
+              (portRef CSA2 (instanceRef pdp_ram_0_0_15))
+              (portRef WEB (instanceRef pdp_ram_0_0_15))
+              (portRef ADB2 (instanceRef pdp_ram_0_0_15))
+              (portRef ADA2 (instanceRef pdp_ram_0_0_15))
+              (portRef ADB1 (instanceRef pdp_ram_0_0_15))
+              (portRef ADA1 (instanceRef pdp_ram_0_0_15))
+              (portRef ADB0 (instanceRef pdp_ram_0_0_15))
+              (portRef ADA0 (instanceRef pdp_ram_0_0_15))
+              (portRef DIB17 (instanceRef pdp_ram_0_0_15))
+              (portRef DIA17 (instanceRef pdp_ram_0_0_15))
+              (portRef DIB16 (instanceRef pdp_ram_0_0_15))
+              (portRef DIA16 (instanceRef pdp_ram_0_0_15))
+              (portRef DIB15 (instanceRef pdp_ram_0_0_15))
+              (portRef DIA15 (instanceRef pdp_ram_0_0_15))
+              (portRef DIB14 (instanceRef pdp_ram_0_0_15))
+              (portRef DIA14 (instanceRef pdp_ram_0_0_15))
+              (portRef DIB13 (instanceRef pdp_ram_0_0_15))
+              (portRef DIA13 (instanceRef pdp_ram_0_0_15))
+              (portRef DIB12 (instanceRef pdp_ram_0_0_15))
+              (portRef DIA12 (instanceRef pdp_ram_0_0_15))
+              (portRef DIB11 (instanceRef pdp_ram_0_0_15))
+              (portRef DIA11 (instanceRef pdp_ram_0_0_15))
+              (portRef DIB10 (instanceRef pdp_ram_0_0_15))
+              (portRef DIA10 (instanceRef pdp_ram_0_0_15))
+              (portRef DIB9 (instanceRef pdp_ram_0_0_15))
+              (portRef DIA9 (instanceRef pdp_ram_0_0_15))
+              (portRef DIB8 (instanceRef pdp_ram_0_0_15))
+              (portRef DIB7 (instanceRef pdp_ram_0_0_15))
+              (portRef DIB6 (instanceRef pdp_ram_0_0_15))
+              (portRef DIB5 (instanceRef pdp_ram_0_0_15))
+              (portRef DIB4 (instanceRef pdp_ram_0_0_15))
+              (portRef DIB3 (instanceRef pdp_ram_0_0_15))
+              (portRef DIB2 (instanceRef pdp_ram_0_0_15))
+              (portRef DIB1 (instanceRef pdp_ram_0_0_15))
+              (portRef DIB0 (instanceRef pdp_ram_0_0_15))
+              (portRef CSB2 (instanceRef pdp_ram_0_1_14))
+              (portRef CSA2 (instanceRef pdp_ram_0_1_14))
+              (portRef WEB (instanceRef pdp_ram_0_1_14))
+              (portRef ADB2 (instanceRef pdp_ram_0_1_14))
+              (portRef ADA2 (instanceRef pdp_ram_0_1_14))
+              (portRef ADB1 (instanceRef pdp_ram_0_1_14))
+              (portRef ADA1 (instanceRef pdp_ram_0_1_14))
+              (portRef ADB0 (instanceRef pdp_ram_0_1_14))
+              (portRef ADA0 (instanceRef pdp_ram_0_1_14))
+              (portRef DIB17 (instanceRef pdp_ram_0_1_14))
+              (portRef DIA17 (instanceRef pdp_ram_0_1_14))
+              (portRef DIB16 (instanceRef pdp_ram_0_1_14))
+              (portRef DIA16 (instanceRef pdp_ram_0_1_14))
+              (portRef DIB15 (instanceRef pdp_ram_0_1_14))
+              (portRef DIA15 (instanceRef pdp_ram_0_1_14))
+              (portRef DIB14 (instanceRef pdp_ram_0_1_14))
+              (portRef DIA14 (instanceRef pdp_ram_0_1_14))
+              (portRef DIB13 (instanceRef pdp_ram_0_1_14))
+              (portRef DIA13 (instanceRef pdp_ram_0_1_14))
+              (portRef DIB12 (instanceRef pdp_ram_0_1_14))
+              (portRef DIA12 (instanceRef pdp_ram_0_1_14))
+              (portRef DIB11 (instanceRef pdp_ram_0_1_14))
+              (portRef DIA11 (instanceRef pdp_ram_0_1_14))
+              (portRef DIB10 (instanceRef pdp_ram_0_1_14))
+              (portRef DIA10 (instanceRef pdp_ram_0_1_14))
+              (portRef DIB9 (instanceRef pdp_ram_0_1_14))
+              (portRef DIA9 (instanceRef pdp_ram_0_1_14))
+              (portRef DIB8 (instanceRef pdp_ram_0_1_14))
+              (portRef DIB7 (instanceRef pdp_ram_0_1_14))
+              (portRef DIB6 (instanceRef pdp_ram_0_1_14))
+              (portRef DIB5 (instanceRef pdp_ram_0_1_14))
+              (portRef DIB4 (instanceRef pdp_ram_0_1_14))
+              (portRef DIB3 (instanceRef pdp_ram_0_1_14))
+              (portRef DIB2 (instanceRef pdp_ram_0_1_14))
+              (portRef DIB1 (instanceRef pdp_ram_0_1_14))
+              (portRef DIB0 (instanceRef pdp_ram_0_1_14))
+              (portRef CSB2 (instanceRef pdp_ram_0_2_13))
+              (portRef CSA2 (instanceRef pdp_ram_0_2_13))
+              (portRef WEB (instanceRef pdp_ram_0_2_13))
+              (portRef ADB2 (instanceRef pdp_ram_0_2_13))
+              (portRef ADA2 (instanceRef pdp_ram_0_2_13))
+              (portRef ADB1 (instanceRef pdp_ram_0_2_13))
+              (portRef ADA1 (instanceRef pdp_ram_0_2_13))
+              (portRef ADB0 (instanceRef pdp_ram_0_2_13))
+              (portRef ADA0 (instanceRef pdp_ram_0_2_13))
+              (portRef DIB17 (instanceRef pdp_ram_0_2_13))
+              (portRef DIA17 (instanceRef pdp_ram_0_2_13))
+              (portRef DIB16 (instanceRef pdp_ram_0_2_13))
+              (portRef DIA16 (instanceRef pdp_ram_0_2_13))
+              (portRef DIB15 (instanceRef pdp_ram_0_2_13))
+              (portRef DIA15 (instanceRef pdp_ram_0_2_13))
+              (portRef DIB14 (instanceRef pdp_ram_0_2_13))
+              (portRef DIA14 (instanceRef pdp_ram_0_2_13))
+              (portRef DIB13 (instanceRef pdp_ram_0_2_13))
+              (portRef DIA13 (instanceRef pdp_ram_0_2_13))
+              (portRef DIB12 (instanceRef pdp_ram_0_2_13))
+              (portRef DIA12 (instanceRef pdp_ram_0_2_13))
+              (portRef DIB11 (instanceRef pdp_ram_0_2_13))
+              (portRef DIA11 (instanceRef pdp_ram_0_2_13))
+              (portRef DIB10 (instanceRef pdp_ram_0_2_13))
+              (portRef DIA10 (instanceRef pdp_ram_0_2_13))
+              (portRef DIB9 (instanceRef pdp_ram_0_2_13))
+              (portRef DIA9 (instanceRef pdp_ram_0_2_13))
+              (portRef DIB8 (instanceRef pdp_ram_0_2_13))
+              (portRef DIB7 (instanceRef pdp_ram_0_2_13))
+              (portRef DIB6 (instanceRef pdp_ram_0_2_13))
+              (portRef DIB5 (instanceRef pdp_ram_0_2_13))
+              (portRef DIB4 (instanceRef pdp_ram_0_2_13))
+              (portRef DIB3 (instanceRef pdp_ram_0_2_13))
+              (portRef DIB2 (instanceRef pdp_ram_0_2_13))
+              (portRef DIB1 (instanceRef pdp_ram_0_2_13))
+              (portRef DIB0 (instanceRef pdp_ram_0_2_13))
+              (portRef CSB2 (instanceRef pdp_ram_0_3_12))
+              (portRef CSA2 (instanceRef pdp_ram_0_3_12))
+              (portRef WEB (instanceRef pdp_ram_0_3_12))
+              (portRef ADB2 (instanceRef pdp_ram_0_3_12))
+              (portRef ADA2 (instanceRef pdp_ram_0_3_12))
+              (portRef ADB1 (instanceRef pdp_ram_0_3_12))
+              (portRef ADA1 (instanceRef pdp_ram_0_3_12))
+              (portRef ADB0 (instanceRef pdp_ram_0_3_12))
+              (portRef ADA0 (instanceRef pdp_ram_0_3_12))
+              (portRef DIB17 (instanceRef pdp_ram_0_3_12))
+              (portRef DIA17 (instanceRef pdp_ram_0_3_12))
+              (portRef DIB16 (instanceRef pdp_ram_0_3_12))
+              (portRef DIA16 (instanceRef pdp_ram_0_3_12))
+              (portRef DIB15 (instanceRef pdp_ram_0_3_12))
+              (portRef DIA15 (instanceRef pdp_ram_0_3_12))
+              (portRef DIB14 (instanceRef pdp_ram_0_3_12))
+              (portRef DIA14 (instanceRef pdp_ram_0_3_12))
+              (portRef DIB13 (instanceRef pdp_ram_0_3_12))
+              (portRef DIA13 (instanceRef pdp_ram_0_3_12))
+              (portRef DIB12 (instanceRef pdp_ram_0_3_12))
+              (portRef DIA12 (instanceRef pdp_ram_0_3_12))
+              (portRef DIB11 (instanceRef pdp_ram_0_3_12))
+              (portRef DIA11 (instanceRef pdp_ram_0_3_12))
+              (portRef DIB10 (instanceRef pdp_ram_0_3_12))
+              (portRef DIA10 (instanceRef pdp_ram_0_3_12))
+              (portRef DIB9 (instanceRef pdp_ram_0_3_12))
+              (portRef DIA9 (instanceRef pdp_ram_0_3_12))
+              (portRef DIB8 (instanceRef pdp_ram_0_3_12))
+              (portRef DIB7 (instanceRef pdp_ram_0_3_12))
+              (portRef DIB6 (instanceRef pdp_ram_0_3_12))
+              (portRef DIB5 (instanceRef pdp_ram_0_3_12))
+              (portRef DIB4 (instanceRef pdp_ram_0_3_12))
+              (portRef DIB3 (instanceRef pdp_ram_0_3_12))
+              (portRef DIB2 (instanceRef pdp_ram_0_3_12))
+              (portRef DIB1 (instanceRef pdp_ram_0_3_12))
+              (portRef DIB0 (instanceRef pdp_ram_0_3_12))
+              (portRef CSB2 (instanceRef pdp_ram_1_0_11))
+              (portRef CSA2 (instanceRef pdp_ram_1_0_11))
+              (portRef WEB (instanceRef pdp_ram_1_0_11))
+              (portRef ADB2 (instanceRef pdp_ram_1_0_11))
+              (portRef ADA2 (instanceRef pdp_ram_1_0_11))
+              (portRef ADB1 (instanceRef pdp_ram_1_0_11))
+              (portRef ADA1 (instanceRef pdp_ram_1_0_11))
+              (portRef ADB0 (instanceRef pdp_ram_1_0_11))
+              (portRef ADA0 (instanceRef pdp_ram_1_0_11))
+              (portRef DIB17 (instanceRef pdp_ram_1_0_11))
+              (portRef DIA17 (instanceRef pdp_ram_1_0_11))
+              (portRef DIB16 (instanceRef pdp_ram_1_0_11))
+              (portRef DIA16 (instanceRef pdp_ram_1_0_11))
+              (portRef DIB15 (instanceRef pdp_ram_1_0_11))
+              (portRef DIA15 (instanceRef pdp_ram_1_0_11))
+              (portRef DIB14 (instanceRef pdp_ram_1_0_11))
+              (portRef DIA14 (instanceRef pdp_ram_1_0_11))
+              (portRef DIB13 (instanceRef pdp_ram_1_0_11))
+              (portRef DIA13 (instanceRef pdp_ram_1_0_11))
+              (portRef DIB12 (instanceRef pdp_ram_1_0_11))
+              (portRef DIA12 (instanceRef pdp_ram_1_0_11))
+              (portRef DIB11 (instanceRef pdp_ram_1_0_11))
+              (portRef DIA11 (instanceRef pdp_ram_1_0_11))
+              (portRef DIB10 (instanceRef pdp_ram_1_0_11))
+              (portRef DIA10 (instanceRef pdp_ram_1_0_11))
+              (portRef DIB9 (instanceRef pdp_ram_1_0_11))
+              (portRef DIA9 (instanceRef pdp_ram_1_0_11))
+              (portRef DIB8 (instanceRef pdp_ram_1_0_11))
+              (portRef DIB7 (instanceRef pdp_ram_1_0_11))
+              (portRef DIB6 (instanceRef pdp_ram_1_0_11))
+              (portRef DIB5 (instanceRef pdp_ram_1_0_11))
+              (portRef DIB4 (instanceRef pdp_ram_1_0_11))
+              (portRef DIB3 (instanceRef pdp_ram_1_0_11))
+              (portRef DIB2 (instanceRef pdp_ram_1_0_11))
+              (portRef DIB1 (instanceRef pdp_ram_1_0_11))
+              (portRef DIB0 (instanceRef pdp_ram_1_0_11))
+              (portRef CSB2 (instanceRef pdp_ram_1_1_10))
+              (portRef CSA2 (instanceRef pdp_ram_1_1_10))
+              (portRef WEB (instanceRef pdp_ram_1_1_10))
+              (portRef ADB2 (instanceRef pdp_ram_1_1_10))
+              (portRef ADA2 (instanceRef pdp_ram_1_1_10))
+              (portRef ADB1 (instanceRef pdp_ram_1_1_10))
+              (portRef ADA1 (instanceRef pdp_ram_1_1_10))
+              (portRef ADB0 (instanceRef pdp_ram_1_1_10))
+              (portRef ADA0 (instanceRef pdp_ram_1_1_10))
+              (portRef DIB17 (instanceRef pdp_ram_1_1_10))
+              (portRef DIA17 (instanceRef pdp_ram_1_1_10))
+              (portRef DIB16 (instanceRef pdp_ram_1_1_10))
+              (portRef DIA16 (instanceRef pdp_ram_1_1_10))
+              (portRef DIB15 (instanceRef pdp_ram_1_1_10))
+              (portRef DIA15 (instanceRef pdp_ram_1_1_10))
+              (portRef DIB14 (instanceRef pdp_ram_1_1_10))
+              (portRef DIA14 (instanceRef pdp_ram_1_1_10))
+              (portRef DIB13 (instanceRef pdp_ram_1_1_10))
+              (portRef DIA13 (instanceRef pdp_ram_1_1_10))
+              (portRef DIB12 (instanceRef pdp_ram_1_1_10))
+              (portRef DIA12 (instanceRef pdp_ram_1_1_10))
+              (portRef DIB11 (instanceRef pdp_ram_1_1_10))
+              (portRef DIA11 (instanceRef pdp_ram_1_1_10))
+              (portRef DIB10 (instanceRef pdp_ram_1_1_10))
+              (portRef DIA10 (instanceRef pdp_ram_1_1_10))
+              (portRef DIB9 (instanceRef pdp_ram_1_1_10))
+              (portRef DIA9 (instanceRef pdp_ram_1_1_10))
+              (portRef DIB8 (instanceRef pdp_ram_1_1_10))
+              (portRef DIB7 (instanceRef pdp_ram_1_1_10))
+              (portRef DIB6 (instanceRef pdp_ram_1_1_10))
+              (portRef DIB5 (instanceRef pdp_ram_1_1_10))
+              (portRef DIB4 (instanceRef pdp_ram_1_1_10))
+              (portRef DIB3 (instanceRef pdp_ram_1_1_10))
+              (portRef DIB2 (instanceRef pdp_ram_1_1_10))
+              (portRef DIB1 (instanceRef pdp_ram_1_1_10))
+              (portRef DIB0 (instanceRef pdp_ram_1_1_10))
+              (portRef CSB2 (instanceRef pdp_ram_1_2_9))
+              (portRef CSA2 (instanceRef pdp_ram_1_2_9))
+              (portRef WEB (instanceRef pdp_ram_1_2_9))
+              (portRef ADB2 (instanceRef pdp_ram_1_2_9))
+              (portRef ADA2 (instanceRef pdp_ram_1_2_9))
+              (portRef ADB1 (instanceRef pdp_ram_1_2_9))
+              (portRef ADA1 (instanceRef pdp_ram_1_2_9))
+              (portRef ADB0 (instanceRef pdp_ram_1_2_9))
+              (portRef ADA0 (instanceRef pdp_ram_1_2_9))
+              (portRef DIB17 (instanceRef pdp_ram_1_2_9))
+              (portRef DIA17 (instanceRef pdp_ram_1_2_9))
+              (portRef DIB16 (instanceRef pdp_ram_1_2_9))
+              (portRef DIA16 (instanceRef pdp_ram_1_2_9))
+              (portRef DIB15 (instanceRef pdp_ram_1_2_9))
+              (portRef DIA15 (instanceRef pdp_ram_1_2_9))
+              (portRef DIB14 (instanceRef pdp_ram_1_2_9))
+              (portRef DIA14 (instanceRef pdp_ram_1_2_9))
+              (portRef DIB13 (instanceRef pdp_ram_1_2_9))
+              (portRef DIA13 (instanceRef pdp_ram_1_2_9))
+              (portRef DIB12 (instanceRef pdp_ram_1_2_9))
+              (portRef DIA12 (instanceRef pdp_ram_1_2_9))
+              (portRef DIB11 (instanceRef pdp_ram_1_2_9))
+              (portRef DIA11 (instanceRef pdp_ram_1_2_9))
+              (portRef DIB10 (instanceRef pdp_ram_1_2_9))
+              (portRef DIA10 (instanceRef pdp_ram_1_2_9))
+              (portRef DIB9 (instanceRef pdp_ram_1_2_9))
+              (portRef DIA9 (instanceRef pdp_ram_1_2_9))
+              (portRef DIB8 (instanceRef pdp_ram_1_2_9))
+              (portRef DIB7 (instanceRef pdp_ram_1_2_9))
+              (portRef DIB6 (instanceRef pdp_ram_1_2_9))
+              (portRef DIB5 (instanceRef pdp_ram_1_2_9))
+              (portRef DIB4 (instanceRef pdp_ram_1_2_9))
+              (portRef DIB3 (instanceRef pdp_ram_1_2_9))
+              (portRef DIB2 (instanceRef pdp_ram_1_2_9))
+              (portRef DIB1 (instanceRef pdp_ram_1_2_9))
+              (portRef DIB0 (instanceRef pdp_ram_1_2_9))
+              (portRef CSB2 (instanceRef pdp_ram_1_3_8))
+              (portRef CSA2 (instanceRef pdp_ram_1_3_8))
+              (portRef WEB (instanceRef pdp_ram_1_3_8))
+              (portRef ADB2 (instanceRef pdp_ram_1_3_8))
+              (portRef ADA2 (instanceRef pdp_ram_1_3_8))
+              (portRef ADB1 (instanceRef pdp_ram_1_3_8))
+              (portRef ADA1 (instanceRef pdp_ram_1_3_8))
+              (portRef ADB0 (instanceRef pdp_ram_1_3_8))
+              (portRef ADA0 (instanceRef pdp_ram_1_3_8))
+              (portRef DIB17 (instanceRef pdp_ram_1_3_8))
+              (portRef DIA17 (instanceRef pdp_ram_1_3_8))
+              (portRef DIB16 (instanceRef pdp_ram_1_3_8))
+              (portRef DIA16 (instanceRef pdp_ram_1_3_8))
+              (portRef DIB15 (instanceRef pdp_ram_1_3_8))
+              (portRef DIA15 (instanceRef pdp_ram_1_3_8))
+              (portRef DIB14 (instanceRef pdp_ram_1_3_8))
+              (portRef DIA14 (instanceRef pdp_ram_1_3_8))
+              (portRef DIB13 (instanceRef pdp_ram_1_3_8))
+              (portRef DIA13 (instanceRef pdp_ram_1_3_8))
+              (portRef DIB12 (instanceRef pdp_ram_1_3_8))
+              (portRef DIA12 (instanceRef pdp_ram_1_3_8))
+              (portRef DIB11 (instanceRef pdp_ram_1_3_8))
+              (portRef DIA11 (instanceRef pdp_ram_1_3_8))
+              (portRef DIB10 (instanceRef pdp_ram_1_3_8))
+              (portRef DIA10 (instanceRef pdp_ram_1_3_8))
+              (portRef DIB9 (instanceRef pdp_ram_1_3_8))
+              (portRef DIA9 (instanceRef pdp_ram_1_3_8))
+              (portRef DIB8 (instanceRef pdp_ram_1_3_8))
+              (portRef DIB7 (instanceRef pdp_ram_1_3_8))
+              (portRef DIB6 (instanceRef pdp_ram_1_3_8))
+              (portRef DIB5 (instanceRef pdp_ram_1_3_8))
+              (portRef DIB4 (instanceRef pdp_ram_1_3_8))
+              (portRef DIB3 (instanceRef pdp_ram_1_3_8))
+              (portRef DIB2 (instanceRef pdp_ram_1_3_8))
+              (portRef DIB1 (instanceRef pdp_ram_1_3_8))
+              (portRef DIB0 (instanceRef pdp_ram_1_3_8))
+              (portRef CSB2 (instanceRef pdp_ram_2_0_7))
+              (portRef CSA2 (instanceRef pdp_ram_2_0_7))
+              (portRef WEB (instanceRef pdp_ram_2_0_7))
+              (portRef ADB2 (instanceRef pdp_ram_2_0_7))
+              (portRef ADA2 (instanceRef pdp_ram_2_0_7))
+              (portRef ADB1 (instanceRef pdp_ram_2_0_7))
+              (portRef ADA1 (instanceRef pdp_ram_2_0_7))
+              (portRef ADB0 (instanceRef pdp_ram_2_0_7))
+              (portRef ADA0 (instanceRef pdp_ram_2_0_7))
+              (portRef DIB17 (instanceRef pdp_ram_2_0_7))
+              (portRef DIA17 (instanceRef pdp_ram_2_0_7))
+              (portRef DIB16 (instanceRef pdp_ram_2_0_7))
+              (portRef DIA16 (instanceRef pdp_ram_2_0_7))
+              (portRef DIB15 (instanceRef pdp_ram_2_0_7))
+              (portRef DIA15 (instanceRef pdp_ram_2_0_7))
+              (portRef DIB14 (instanceRef pdp_ram_2_0_7))
+              (portRef DIA14 (instanceRef pdp_ram_2_0_7))
+              (portRef DIB13 (instanceRef pdp_ram_2_0_7))
+              (portRef DIA13 (instanceRef pdp_ram_2_0_7))
+              (portRef DIB12 (instanceRef pdp_ram_2_0_7))
+              (portRef DIA12 (instanceRef pdp_ram_2_0_7))
+              (portRef DIB11 (instanceRef pdp_ram_2_0_7))
+              (portRef DIA11 (instanceRef pdp_ram_2_0_7))
+              (portRef DIB10 (instanceRef pdp_ram_2_0_7))
+              (portRef DIA10 (instanceRef pdp_ram_2_0_7))
+              (portRef DIB9 (instanceRef pdp_ram_2_0_7))
+              (portRef DIA9 (instanceRef pdp_ram_2_0_7))
+              (portRef DIB8 (instanceRef pdp_ram_2_0_7))
+              (portRef DIB7 (instanceRef pdp_ram_2_0_7))
+              (portRef DIB6 (instanceRef pdp_ram_2_0_7))
+              (portRef DIB5 (instanceRef pdp_ram_2_0_7))
+              (portRef DIB4 (instanceRef pdp_ram_2_0_7))
+              (portRef DIB3 (instanceRef pdp_ram_2_0_7))
+              (portRef DIB2 (instanceRef pdp_ram_2_0_7))
+              (portRef DIB1 (instanceRef pdp_ram_2_0_7))
+              (portRef DIB0 (instanceRef pdp_ram_2_0_7))
+              (portRef CSB2 (instanceRef pdp_ram_2_1_6))
+              (portRef CSA2 (instanceRef pdp_ram_2_1_6))
+              (portRef WEB (instanceRef pdp_ram_2_1_6))
+              (portRef ADB2 (instanceRef pdp_ram_2_1_6))
+              (portRef ADA2 (instanceRef pdp_ram_2_1_6))
+              (portRef ADB1 (instanceRef pdp_ram_2_1_6))
+              (portRef ADA1 (instanceRef pdp_ram_2_1_6))
+              (portRef ADB0 (instanceRef pdp_ram_2_1_6))
+              (portRef ADA0 (instanceRef pdp_ram_2_1_6))
+              (portRef DIB17 (instanceRef pdp_ram_2_1_6))
+              (portRef DIA17 (instanceRef pdp_ram_2_1_6))
+              (portRef DIB16 (instanceRef pdp_ram_2_1_6))
+              (portRef DIA16 (instanceRef pdp_ram_2_1_6))
+              (portRef DIB15 (instanceRef pdp_ram_2_1_6))
+              (portRef DIA15 (instanceRef pdp_ram_2_1_6))
+              (portRef DIB14 (instanceRef pdp_ram_2_1_6))
+              (portRef DIA14 (instanceRef pdp_ram_2_1_6))
+              (portRef DIB13 (instanceRef pdp_ram_2_1_6))
+              (portRef DIA13 (instanceRef pdp_ram_2_1_6))
+              (portRef DIB12 (instanceRef pdp_ram_2_1_6))
+              (portRef DIA12 (instanceRef pdp_ram_2_1_6))
+              (portRef DIB11 (instanceRef pdp_ram_2_1_6))
+              (portRef DIA11 (instanceRef pdp_ram_2_1_6))
+              (portRef DIB10 (instanceRef pdp_ram_2_1_6))
+              (portRef DIA10 (instanceRef pdp_ram_2_1_6))
+              (portRef DIB9 (instanceRef pdp_ram_2_1_6))
+              (portRef DIA9 (instanceRef pdp_ram_2_1_6))
+              (portRef DIB8 (instanceRef pdp_ram_2_1_6))
+              (portRef DIB7 (instanceRef pdp_ram_2_1_6))
+              (portRef DIB6 (instanceRef pdp_ram_2_1_6))
+              (portRef DIB5 (instanceRef pdp_ram_2_1_6))
+              (portRef DIB4 (instanceRef pdp_ram_2_1_6))
+              (portRef DIB3 (instanceRef pdp_ram_2_1_6))
+              (portRef DIB2 (instanceRef pdp_ram_2_1_6))
+              (portRef DIB1 (instanceRef pdp_ram_2_1_6))
+              (portRef DIB0 (instanceRef pdp_ram_2_1_6))
+              (portRef CSB2 (instanceRef pdp_ram_2_2_5))
+              (portRef CSA2 (instanceRef pdp_ram_2_2_5))
+              (portRef WEB (instanceRef pdp_ram_2_2_5))
+              (portRef ADB2 (instanceRef pdp_ram_2_2_5))
+              (portRef ADA2 (instanceRef pdp_ram_2_2_5))
+              (portRef ADB1 (instanceRef pdp_ram_2_2_5))
+              (portRef ADA1 (instanceRef pdp_ram_2_2_5))
+              (portRef ADB0 (instanceRef pdp_ram_2_2_5))
+              (portRef ADA0 (instanceRef pdp_ram_2_2_5))
+              (portRef DIB17 (instanceRef pdp_ram_2_2_5))
+              (portRef DIA17 (instanceRef pdp_ram_2_2_5))
+              (portRef DIB16 (instanceRef pdp_ram_2_2_5))
+              (portRef DIA16 (instanceRef pdp_ram_2_2_5))
+              (portRef DIB15 (instanceRef pdp_ram_2_2_5))
+              (portRef DIA15 (instanceRef pdp_ram_2_2_5))
+              (portRef DIB14 (instanceRef pdp_ram_2_2_5))
+              (portRef DIA14 (instanceRef pdp_ram_2_2_5))
+              (portRef DIB13 (instanceRef pdp_ram_2_2_5))
+              (portRef DIA13 (instanceRef pdp_ram_2_2_5))
+              (portRef DIB12 (instanceRef pdp_ram_2_2_5))
+              (portRef DIA12 (instanceRef pdp_ram_2_2_5))
+              (portRef DIB11 (instanceRef pdp_ram_2_2_5))
+              (portRef DIA11 (instanceRef pdp_ram_2_2_5))
+              (portRef DIB10 (instanceRef pdp_ram_2_2_5))
+              (portRef DIA10 (instanceRef pdp_ram_2_2_5))
+              (portRef DIB9 (instanceRef pdp_ram_2_2_5))
+              (portRef DIA9 (instanceRef pdp_ram_2_2_5))
+              (portRef DIB8 (instanceRef pdp_ram_2_2_5))
+              (portRef DIB7 (instanceRef pdp_ram_2_2_5))
+              (portRef DIB6 (instanceRef pdp_ram_2_2_5))
+              (portRef DIB5 (instanceRef pdp_ram_2_2_5))
+              (portRef DIB4 (instanceRef pdp_ram_2_2_5))
+              (portRef DIB3 (instanceRef pdp_ram_2_2_5))
+              (portRef DIB2 (instanceRef pdp_ram_2_2_5))
+              (portRef DIB1 (instanceRef pdp_ram_2_2_5))
+              (portRef DIB0 (instanceRef pdp_ram_2_2_5))
+              (portRef CSB2 (instanceRef pdp_ram_2_3_4))
+              (portRef CSA2 (instanceRef pdp_ram_2_3_4))
+              (portRef WEB (instanceRef pdp_ram_2_3_4))
+              (portRef ADB2 (instanceRef pdp_ram_2_3_4))
+              (portRef ADA2 (instanceRef pdp_ram_2_3_4))
+              (portRef ADB1 (instanceRef pdp_ram_2_3_4))
+              (portRef ADA1 (instanceRef pdp_ram_2_3_4))
+              (portRef ADB0 (instanceRef pdp_ram_2_3_4))
+              (portRef ADA0 (instanceRef pdp_ram_2_3_4))
+              (portRef DIB17 (instanceRef pdp_ram_2_3_4))
+              (portRef DIA17 (instanceRef pdp_ram_2_3_4))
+              (portRef DIB16 (instanceRef pdp_ram_2_3_4))
+              (portRef DIA16 (instanceRef pdp_ram_2_3_4))
+              (portRef DIB15 (instanceRef pdp_ram_2_3_4))
+              (portRef DIA15 (instanceRef pdp_ram_2_3_4))
+              (portRef DIB14 (instanceRef pdp_ram_2_3_4))
+              (portRef DIA14 (instanceRef pdp_ram_2_3_4))
+              (portRef DIB13 (instanceRef pdp_ram_2_3_4))
+              (portRef DIA13 (instanceRef pdp_ram_2_3_4))
+              (portRef DIB12 (instanceRef pdp_ram_2_3_4))
+              (portRef DIA12 (instanceRef pdp_ram_2_3_4))
+              (portRef DIB11 (instanceRef pdp_ram_2_3_4))
+              (portRef DIA11 (instanceRef pdp_ram_2_3_4))
+              (portRef DIB10 (instanceRef pdp_ram_2_3_4))
+              (portRef DIA10 (instanceRef pdp_ram_2_3_4))
+              (portRef DIB9 (instanceRef pdp_ram_2_3_4))
+              (portRef DIA9 (instanceRef pdp_ram_2_3_4))
+              (portRef DIB8 (instanceRef pdp_ram_2_3_4))
+              (portRef DIB7 (instanceRef pdp_ram_2_3_4))
+              (portRef DIB6 (instanceRef pdp_ram_2_3_4))
+              (portRef DIB5 (instanceRef pdp_ram_2_3_4))
+              (portRef DIB4 (instanceRef pdp_ram_2_3_4))
+              (portRef DIB3 (instanceRef pdp_ram_2_3_4))
+              (portRef DIB2 (instanceRef pdp_ram_2_3_4))
+              (portRef DIB1 (instanceRef pdp_ram_2_3_4))
+              (portRef DIB0 (instanceRef pdp_ram_2_3_4))
+              (portRef CSB2 (instanceRef pdp_ram_3_0_3))
+              (portRef CSA2 (instanceRef pdp_ram_3_0_3))
+              (portRef WEB (instanceRef pdp_ram_3_0_3))
+              (portRef ADB2 (instanceRef pdp_ram_3_0_3))
+              (portRef ADA2 (instanceRef pdp_ram_3_0_3))
+              (portRef ADB1 (instanceRef pdp_ram_3_0_3))
+              (portRef ADA1 (instanceRef pdp_ram_3_0_3))
+              (portRef ADB0 (instanceRef pdp_ram_3_0_3))
+              (portRef ADA0 (instanceRef pdp_ram_3_0_3))
+              (portRef DIB17 (instanceRef pdp_ram_3_0_3))
+              (portRef DIA17 (instanceRef pdp_ram_3_0_3))
+              (portRef DIB16 (instanceRef pdp_ram_3_0_3))
+              (portRef DIA16 (instanceRef pdp_ram_3_0_3))
+              (portRef DIB15 (instanceRef pdp_ram_3_0_3))
+              (portRef DIA15 (instanceRef pdp_ram_3_0_3))
+              (portRef DIB14 (instanceRef pdp_ram_3_0_3))
+              (portRef DIA14 (instanceRef pdp_ram_3_0_3))
+              (portRef DIB13 (instanceRef pdp_ram_3_0_3))
+              (portRef DIA13 (instanceRef pdp_ram_3_0_3))
+              (portRef DIB12 (instanceRef pdp_ram_3_0_3))
+              (portRef DIA12 (instanceRef pdp_ram_3_0_3))
+              (portRef DIB11 (instanceRef pdp_ram_3_0_3))
+              (portRef DIA11 (instanceRef pdp_ram_3_0_3))
+              (portRef DIB10 (instanceRef pdp_ram_3_0_3))
+              (portRef DIA10 (instanceRef pdp_ram_3_0_3))
+              (portRef DIB9 (instanceRef pdp_ram_3_0_3))
+              (portRef DIA9 (instanceRef pdp_ram_3_0_3))
+              (portRef DIB8 (instanceRef pdp_ram_3_0_3))
+              (portRef DIB7 (instanceRef pdp_ram_3_0_3))
+              (portRef DIB6 (instanceRef pdp_ram_3_0_3))
+              (portRef DIB5 (instanceRef pdp_ram_3_0_3))
+              (portRef DIB4 (instanceRef pdp_ram_3_0_3))
+              (portRef DIB3 (instanceRef pdp_ram_3_0_3))
+              (portRef DIB2 (instanceRef pdp_ram_3_0_3))
+              (portRef DIB1 (instanceRef pdp_ram_3_0_3))
+              (portRef DIB0 (instanceRef pdp_ram_3_0_3))
+              (portRef CSB2 (instanceRef pdp_ram_3_1_2))
+              (portRef CSA2 (instanceRef pdp_ram_3_1_2))
+              (portRef WEB (instanceRef pdp_ram_3_1_2))
+              (portRef ADB2 (instanceRef pdp_ram_3_1_2))
+              (portRef ADA2 (instanceRef pdp_ram_3_1_2))
+              (portRef ADB1 (instanceRef pdp_ram_3_1_2))
+              (portRef ADA1 (instanceRef pdp_ram_3_1_2))
+              (portRef ADB0 (instanceRef pdp_ram_3_1_2))
+              (portRef ADA0 (instanceRef pdp_ram_3_1_2))
+              (portRef DIB17 (instanceRef pdp_ram_3_1_2))
+              (portRef DIA17 (instanceRef pdp_ram_3_1_2))
+              (portRef DIB16 (instanceRef pdp_ram_3_1_2))
+              (portRef DIA16 (instanceRef pdp_ram_3_1_2))
+              (portRef DIB15 (instanceRef pdp_ram_3_1_2))
+              (portRef DIA15 (instanceRef pdp_ram_3_1_2))
+              (portRef DIB14 (instanceRef pdp_ram_3_1_2))
+              (portRef DIA14 (instanceRef pdp_ram_3_1_2))
+              (portRef DIB13 (instanceRef pdp_ram_3_1_2))
+              (portRef DIA13 (instanceRef pdp_ram_3_1_2))
+              (portRef DIB12 (instanceRef pdp_ram_3_1_2))
+              (portRef DIA12 (instanceRef pdp_ram_3_1_2))
+              (portRef DIB11 (instanceRef pdp_ram_3_1_2))
+              (portRef DIA11 (instanceRef pdp_ram_3_1_2))
+              (portRef DIB10 (instanceRef pdp_ram_3_1_2))
+              (portRef DIA10 (instanceRef pdp_ram_3_1_2))
+              (portRef DIB9 (instanceRef pdp_ram_3_1_2))
+              (portRef DIA9 (instanceRef pdp_ram_3_1_2))
+              (portRef DIB8 (instanceRef pdp_ram_3_1_2))
+              (portRef DIB7 (instanceRef pdp_ram_3_1_2))
+              (portRef DIB6 (instanceRef pdp_ram_3_1_2))
+              (portRef DIB5 (instanceRef pdp_ram_3_1_2))
+              (portRef DIB4 (instanceRef pdp_ram_3_1_2))
+              (portRef DIB3 (instanceRef pdp_ram_3_1_2))
+              (portRef DIB2 (instanceRef pdp_ram_3_1_2))
+              (portRef DIB1 (instanceRef pdp_ram_3_1_2))
+              (portRef DIB0 (instanceRef pdp_ram_3_1_2))
+              (portRef CSB2 (instanceRef pdp_ram_3_2_1))
+              (portRef CSA2 (instanceRef pdp_ram_3_2_1))
+              (portRef WEB (instanceRef pdp_ram_3_2_1))
+              (portRef ADB2 (instanceRef pdp_ram_3_2_1))
+              (portRef ADA2 (instanceRef pdp_ram_3_2_1))
+              (portRef ADB1 (instanceRef pdp_ram_3_2_1))
+              (portRef ADA1 (instanceRef pdp_ram_3_2_1))
+              (portRef ADB0 (instanceRef pdp_ram_3_2_1))
+              (portRef ADA0 (instanceRef pdp_ram_3_2_1))
+              (portRef DIB17 (instanceRef pdp_ram_3_2_1))
+              (portRef DIA17 (instanceRef pdp_ram_3_2_1))
+              (portRef DIB16 (instanceRef pdp_ram_3_2_1))
+              (portRef DIA16 (instanceRef pdp_ram_3_2_1))
+              (portRef DIB15 (instanceRef pdp_ram_3_2_1))
+              (portRef DIA15 (instanceRef pdp_ram_3_2_1))
+              (portRef DIB14 (instanceRef pdp_ram_3_2_1))
+              (portRef DIA14 (instanceRef pdp_ram_3_2_1))
+              (portRef DIB13 (instanceRef pdp_ram_3_2_1))
+              (portRef DIA13 (instanceRef pdp_ram_3_2_1))
+              (portRef DIB12 (instanceRef pdp_ram_3_2_1))
+              (portRef DIA12 (instanceRef pdp_ram_3_2_1))
+              (portRef DIB11 (instanceRef pdp_ram_3_2_1))
+              (portRef DIA11 (instanceRef pdp_ram_3_2_1))
+              (portRef DIB10 (instanceRef pdp_ram_3_2_1))
+              (portRef DIA10 (instanceRef pdp_ram_3_2_1))
+              (portRef DIB9 (instanceRef pdp_ram_3_2_1))
+              (portRef DIA9 (instanceRef pdp_ram_3_2_1))
+              (portRef DIB8 (instanceRef pdp_ram_3_2_1))
+              (portRef DIB7 (instanceRef pdp_ram_3_2_1))
+              (portRef DIB6 (instanceRef pdp_ram_3_2_1))
+              (portRef DIB5 (instanceRef pdp_ram_3_2_1))
+              (portRef DIB4 (instanceRef pdp_ram_3_2_1))
+              (portRef DIB3 (instanceRef pdp_ram_3_2_1))
+              (portRef DIB2 (instanceRef pdp_ram_3_2_1))
+              (portRef DIB1 (instanceRef pdp_ram_3_2_1))
+              (portRef DIB0 (instanceRef pdp_ram_3_2_1))
+              (portRef CSB2 (instanceRef pdp_ram_3_3_0))
+              (portRef CSA2 (instanceRef pdp_ram_3_3_0))
+              (portRef WEB (instanceRef pdp_ram_3_3_0))
+              (portRef ADB2 (instanceRef pdp_ram_3_3_0))
+              (portRef ADA2 (instanceRef pdp_ram_3_3_0))
+              (portRef ADB1 (instanceRef pdp_ram_3_3_0))
+              (portRef ADA1 (instanceRef pdp_ram_3_3_0))
+              (portRef ADB0 (instanceRef pdp_ram_3_3_0))
+              (portRef ADA0 (instanceRef pdp_ram_3_3_0))
+              (portRef DIB17 (instanceRef pdp_ram_3_3_0))
+              (portRef DIA17 (instanceRef pdp_ram_3_3_0))
+              (portRef DIB16 (instanceRef pdp_ram_3_3_0))
+              (portRef DIA16 (instanceRef pdp_ram_3_3_0))
+              (portRef DIB15 (instanceRef pdp_ram_3_3_0))
+              (portRef DIA15 (instanceRef pdp_ram_3_3_0))
+              (portRef DIB14 (instanceRef pdp_ram_3_3_0))
+              (portRef DIA14 (instanceRef pdp_ram_3_3_0))
+              (portRef DIB13 (instanceRef pdp_ram_3_3_0))
+              (portRef DIA13 (instanceRef pdp_ram_3_3_0))
+              (portRef DIB12 (instanceRef pdp_ram_3_3_0))
+              (portRef DIA12 (instanceRef pdp_ram_3_3_0))
+              (portRef DIB11 (instanceRef pdp_ram_3_3_0))
+              (portRef DIA11 (instanceRef pdp_ram_3_3_0))
+              (portRef DIB10 (instanceRef pdp_ram_3_3_0))
+              (portRef DIA10 (instanceRef pdp_ram_3_3_0))
+              (portRef DIB9 (instanceRef pdp_ram_3_3_0))
+              (portRef DIA9 (instanceRef pdp_ram_3_3_0))
+              (portRef DIB8 (instanceRef pdp_ram_3_3_0))
+              (portRef DIB7 (instanceRef pdp_ram_3_3_0))
+              (portRef DIB6 (instanceRef pdp_ram_3_3_0))
+              (portRef DIB5 (instanceRef pdp_ram_3_3_0))
+              (portRef DIB4 (instanceRef pdp_ram_3_3_0))
+              (portRef DIB3 (instanceRef pdp_ram_3_3_0))
+              (portRef DIB2 (instanceRef pdp_ram_3_3_0))
+              (portRef DIB1 (instanceRef pdp_ram_3_3_0))
+              (portRef DIB0 (instanceRef pdp_ram_3_3_0))
+              (portRef CD (instanceRef FF_18))
+              (portRef CD (instanceRef FF_17))
+              (portRef CD (instanceRef FF_16))
+              (portRef CD (instanceRef FF_15))
+              (portRef B0 (instanceRef bdcnt_bctr_cia))
+              (portRef A0 (instanceRef bdcnt_bctr_cia))
+              (portRef A1 (instanceRef e_cmp_0))
+              (portRef A0 (instanceRef e_cmp_1))
+              (portRef A1 (instanceRef e_cmp_1))
+              (portRef A0 (instanceRef e_cmp_2))
+              (portRef A1 (instanceRef e_cmp_2))
+              (portRef A0 (instanceRef e_cmp_3))
+              (portRef A1 (instanceRef e_cmp_3))
+              (portRef A0 (instanceRef e_cmp_4))
+              (portRef A1 (instanceRef e_cmp_4))
+              (portRef A0 (instanceRef e_cmp_5))
+              (portRef A1 (instanceRef e_cmp_5))
+              (portRef A0 (instanceRef e_cmp_6))
+              (portRef A1 (instanceRef e_cmp_6))
+              (portRef B1 (instanceRef a0))
+              (portRef B0 (instanceRef a0))
+              (portRef A1 (instanceRef a0))
+              (portRef A0 (instanceRef a0))
+              (portRef B1 (instanceRef a1))
+              (portRef B0 (instanceRef a1))
+              (portRef A1 (instanceRef a1))
+              (portRef A0 (instanceRef a1))
+              (portRef B0 (instanceRef w_ctr_cia))
+              (portRef A0 (instanceRef w_ctr_cia))
+              (portRef B1 (instanceRef w_ctr_0))
+              (portRef B0 (instanceRef w_ctr_0))
+              (portRef B1 (instanceRef w_ctr_1))
+              (portRef B0 (instanceRef w_ctr_1))
+              (portRef B1 (instanceRef w_ctr_2))
+              (portRef B0 (instanceRef w_ctr_2))
+              (portRef B1 (instanceRef w_ctr_3))
+              (portRef B0 (instanceRef w_ctr_3))
+              (portRef B1 (instanceRef w_ctr_4))
+              (portRef B0 (instanceRef w_ctr_4))
+              (portRef B1 (instanceRef w_ctr_5))
+              (portRef B0 (instanceRef w_ctr_5))
+              (portRef B1 (instanceRef w_ctr_6))
+              (portRef B0 (instanceRef w_ctr_6))
+              (portRef B0 (instanceRef r_ctr_cia))
+              (portRef A0 (instanceRef r_ctr_cia))
+              (portRef B1 (instanceRef r_ctr_0))
+              (portRef B0 (instanceRef r_ctr_0))
+              (portRef B1 (instanceRef r_ctr_1))
+              (portRef B0 (instanceRef r_ctr_1))
+              (portRef B1 (instanceRef r_ctr_2))
+              (portRef B0 (instanceRef r_ctr_2))
+              (portRef B1 (instanceRef r_ctr_3))
+              (portRef B0 (instanceRef r_ctr_3))
+              (portRef B1 (instanceRef r_ctr_4))
+              (portRef B0 (instanceRef r_ctr_4))
+              (portRef B1 (instanceRef r_ctr_5))
+              (portRef B0 (instanceRef r_ctr_5))
+              (portRef B1 (instanceRef r_ctr_6))
+              (portRef B0 (instanceRef r_ctr_6))
+              (portRef B1 (instanceRef wcnt_7))
+              (portRef B0 (instanceRef wcnt_7))
+              (portRef A1 (instanceRef wcnt_7))
+              (portRef B0 (instanceRef af_set_cmp_ci_a))
+              (portRef A0 (instanceRef af_set_cmp_ci_a))
+              (portRef B1 (instanceRef af_set_cmp_6))
+              (portRef B1 (instanceRef a2))
+              (portRef B0 (instanceRef a2))
+              (portRef A1 (instanceRef a2))
+              (portRef A0 (instanceRef a2))))
+          (net af_set_c
+            (joined
+              (portRef CIN (instanceRef a2))
+              (portRef COUT (instanceRef af_set_cmp_6))))
+          (net partial_full
+            (joined
+              (portRef AlmostFull)
+              (portRef Q (instanceRef FF_0))))
+          (net Full
+            (joined
+              (portRef Full)
+              (portRef Q (instanceRef FF_75))
+              (portRef A (instanceRef INV_5))
+              (portRef AD0 (instanceRef LUT4_0))))
+          (net Empty
+            (joined
+              (portRef Empty)
+              (portRef Q (instanceRef FF_76))
+              (portRef A (instanceRef INV_4))
+              (portRef AD0 (instanceRef LUT4_1))))
+          (net WCNT13
+            (joined
+              (portRef (member WCNT 0))
+              (portRef A1 (instanceRef g_cmp_6))
+              (portRef Q (instanceRef FF_77))
+              (portRef A1 (instanceRef bdcnt_bctr_6))
+              (portRef B1 (instanceRef e_cmp_6))))
+          (net WCNT12
+            (joined
+              (portRef (member WCNT 1))
+              (portRef A0 (instanceRef g_cmp_6))
+              (portRef Q (instanceRef FF_78))
+              (portRef A0 (instanceRef bdcnt_bctr_6))
+              (portRef B0 (instanceRef e_cmp_6))))
+          (net WCNT11
+            (joined
+              (portRef (member WCNT 2))
+              (portRef A1 (instanceRef g_cmp_5))
+              (portRef Q (instanceRef FF_79))
+              (portRef A1 (instanceRef bdcnt_bctr_5))
+              (portRef B1 (instanceRef e_cmp_5))))
+          (net WCNT10
+            (joined
+              (portRef (member WCNT 3))
+              (portRef A0 (instanceRef g_cmp_5))
+              (portRef Q (instanceRef FF_80))
+              (portRef A0 (instanceRef bdcnt_bctr_5))
+              (portRef B0 (instanceRef e_cmp_5))))
+          (net WCNT9
+            (joined
+              (portRef (member WCNT 4))
+              (portRef A1 (instanceRef g_cmp_4))
+              (portRef Q (instanceRef FF_81))
+              (portRef A1 (instanceRef bdcnt_bctr_4))
+              (portRef B1 (instanceRef e_cmp_4))))
+          (net WCNT8
+            (joined
+              (portRef (member WCNT 5))
+              (portRef A0 (instanceRef g_cmp_4))
+              (portRef Q (instanceRef FF_82))
+              (portRef A0 (instanceRef bdcnt_bctr_4))
+              (portRef B0 (instanceRef e_cmp_4))))
+          (net WCNT7
+            (joined
+              (portRef (member WCNT 6))
+              (portRef A1 (instanceRef g_cmp_3))
+              (portRef Q (instanceRef FF_83))
+              (portRef A1 (instanceRef bdcnt_bctr_3))
+              (portRef B1 (instanceRef e_cmp_3))))
+          (net WCNT6
+            (joined
+              (portRef (member WCNT 7))
+              (portRef A0 (instanceRef g_cmp_3))
+              (portRef Q (instanceRef FF_84))
+              (portRef A0 (instanceRef bdcnt_bctr_3))
+              (portRef B0 (instanceRef e_cmp_3))))
+          (net WCNT5
+            (joined
+              (portRef (member WCNT 8))
+              (portRef A1 (instanceRef g_cmp_2))
+              (portRef Q (instanceRef FF_85))
+              (portRef A1 (instanceRef bdcnt_bctr_2))
+              (portRef B1 (instanceRef e_cmp_2))))
+          (net WCNT4
+            (joined
+              (portRef (member WCNT 9))
+              (portRef A0 (instanceRef g_cmp_2))
+              (portRef Q (instanceRef FF_86))
+              (portRef A0 (instanceRef bdcnt_bctr_2))
+              (portRef B0 (instanceRef e_cmp_2))))
+          (net WCNT3
+            (joined
+              (portRef (member WCNT 10))
+              (portRef A1 (instanceRef g_cmp_1))
+              (portRef Q (instanceRef FF_87))
+              (portRef A1 (instanceRef bdcnt_bctr_1))
+              (portRef B1 (instanceRef e_cmp_1))))
+          (net WCNT2
+            (joined
+              (portRef (member WCNT 11))
+              (portRef A0 (instanceRef g_cmp_1))
+              (portRef Q (instanceRef FF_88))
+              (portRef A0 (instanceRef bdcnt_bctr_1))
+              (portRef B0 (instanceRef e_cmp_1))))
+          (net WCNT1
+            (joined
+              (portRef (member WCNT 12))
+              (portRef A1 (instanceRef g_cmp_0))
+              (portRef Q (instanceRef FF_89))
+              (portRef A1 (instanceRef bdcnt_bctr_0))
+              (portRef B1 (instanceRef e_cmp_0))))
+          (net WCNT0
+            (joined
+              (portRef (member WCNT 13))
+              (portRef A0 (instanceRef g_cmp_0))
+              (portRef Q (instanceRef FF_90))
+              (portRef A0 (instanceRef bdcnt_bctr_0))
+              (portRef B0 (instanceRef e_cmp_0))))
+          (net dataout35
+            (joined
+              (portRef (member Q 0))
+              (portRef Z (instanceRef mux_0))))
+          (net dataout34
+            (joined
+              (portRef (member Q 1))
+              (portRef Z (instanceRef mux_1))))
+          (net dataout33
+            (joined
+              (portRef (member Q 2))
+              (portRef Z (instanceRef mux_2))))
+          (net dataout32
+            (joined
+              (portRef (member Q 3))
+              (portRef Z (instanceRef mux_3))))
+          (net dataout31
+            (joined
+              (portRef (member Q 4))
+              (portRef Z (instanceRef mux_4))))
+          (net dataout30
+            (joined
+              (portRef (member Q 5))
+              (portRef Z (instanceRef mux_5))))
+          (net dataout29
+            (joined
+              (portRef (member Q 6))
+              (portRef Z (instanceRef mux_6))))
+          (net dataout28
+            (joined
+              (portRef (member Q 7))
+              (portRef Z (instanceRef mux_7))))
+          (net dataout27
+            (joined
+              (portRef (member Q 8))
+              (portRef Z (instanceRef mux_8))))
+          (net dataout26
+            (joined
+              (portRef (member Q 9))
+              (portRef Z (instanceRef mux_9))))
+          (net dataout25
+            (joined
+              (portRef (member Q 10))
+              (portRef Z (instanceRef mux_10))))
+          (net dataout24
+            (joined
+              (portRef (member Q 11))
+              (portRef Z (instanceRef mux_11))))
+          (net dataout23
+            (joined
+              (portRef (member Q 12))
+              (portRef Z (instanceRef mux_12))))
+          (net dataout22
+            (joined
+              (portRef (member Q 13))
+              (portRef Z (instanceRef mux_13))))
+          (net dataout21
+            (joined
+              (portRef (member Q 14))
+              (portRef Z (instanceRef mux_14))))
+          (net dataout20
+            (joined
+              (portRef (member Q 15))
+              (portRef Z (instanceRef mux_15))))
+          (net dataout19
+            (joined
+              (portRef (member Q 16))
+              (portRef Z (instanceRef mux_16))))
+          (net dataout18
+            (joined
+              (portRef (member Q 17))
+              (portRef Z (instanceRef mux_17))))
+          (net dataout17
+            (joined
+              (portRef (member Q 18))
+              (portRef Z (instanceRef mux_18))))
+          (net dataout16
+            (joined
+              (portRef (member Q 19))
+              (portRef Z (instanceRef mux_19))))
+          (net dataout15
+            (joined
+              (portRef (member Q 20))
+              (portRef Z (instanceRef mux_20))))
+          (net dataout14
+            (joined
+              (portRef (member Q 21))
+              (portRef Z (instanceRef mux_21))))
+          (net dataout13
+            (joined
+              (portRef (member Q 22))
+              (portRef Z (instanceRef mux_22))))
+          (net dataout12
+            (joined
+              (portRef (member Q 23))
+              (portRef Z (instanceRef mux_23))))
+          (net dataout11
+            (joined
+              (portRef (member Q 24))
+              (portRef Z (instanceRef mux_24))))
+          (net dataout10
+            (joined
+              (portRef (member Q 25))
+              (portRef Z (instanceRef mux_25))))
+          (net dataout9
+            (joined
+              (portRef (member Q 26))
+              (portRef Z (instanceRef mux_26))))
+          (net dataout8
+            (joined
+              (portRef (member Q 27))
+              (portRef Z (instanceRef mux_27))))
+          (net dataout7
+            (joined
+              (portRef (member Q 28))
+              (portRef Z (instanceRef mux_28))))
+          (net dataout6
+            (joined
+              (portRef (member Q 29))
+              (portRef Z (instanceRef mux_29))))
+          (net dataout5
+            (joined
+              (portRef (member Q 30))
+              (portRef Z (instanceRef mux_30))))
+          (net dataout4
+            (joined
+              (portRef (member Q 31))
+              (portRef Z (instanceRef mux_31))))
+          (net dataout3
+            (joined
+              (portRef (member Q 32))
+              (portRef Z (instanceRef mux_32))))
+          (net dataout2
+            (joined
+              (portRef (member Q 33))
+              (portRef Z (instanceRef mux_33))))
+          (net dataout1
+            (joined
+              (portRef (member Q 34))
+              (portRef Z (instanceRef mux_34))))
+          (net dataout0
+            (joined
+              (portRef (member Q 35))
+              (portRef Z (instanceRef mux_35))))
+          (net AmFullThresh12
+            (joined
+              (portRef (member AmFullThresh 0))
+              (portRef B0 (instanceRef af_set_cmp_6))))
+          (net AmFullThresh11
+            (joined
+              (portRef (member AmFullThresh 1))
+              (portRef B1 (instanceRef af_set_cmp_5))))
+          (net AmFullThresh10
+            (joined
+              (portRef (member AmFullThresh 2))
+              (portRef B0 (instanceRef af_set_cmp_5))))
+          (net AmFullThresh9
+            (joined
+              (portRef (member AmFullThresh 3))
+              (portRef B1 (instanceRef af_set_cmp_4))))
+          (net AmFullThresh8
+            (joined
+              (portRef (member AmFullThresh 4))
+              (portRef B0 (instanceRef af_set_cmp_4))))
+          (net AmFullThresh7
+            (joined
+              (portRef (member AmFullThresh 5))
+              (portRef B1 (instanceRef af_set_cmp_3))))
+          (net AmFullThresh6
+            (joined
+              (portRef (member AmFullThresh 6))
+              (portRef B0 (instanceRef af_set_cmp_3))))
+          (net AmFullThresh5
+            (joined
+              (portRef (member AmFullThresh 7))
+              (portRef B1 (instanceRef af_set_cmp_2))))
+          (net AmFullThresh4
+            (joined
+              (portRef (member AmFullThresh 8))
+              (portRef B0 (instanceRef af_set_cmp_2))))
+          (net AmFullThresh3
+            (joined
+              (portRef (member AmFullThresh 9))
+              (portRef B1 (instanceRef af_set_cmp_1))))
+          (net AmFullThresh2
+            (joined
+              (portRef (member AmFullThresh 10))
+              (portRef B0 (instanceRef af_set_cmp_1))))
+          (net AmFullThresh1
+            (joined
+              (portRef (member AmFullThresh 11))
+              (portRef B1 (instanceRef af_set_cmp_0))))
+          (net AmFullThresh0
+            (joined
+              (portRef (member AmFullThresh 12))
+              (portRef B0 (instanceRef af_set_cmp_0))))
+          (net reset
+            (joined
+              (portRef Reset)
+              (portRef RSTB (instanceRef pdp_ram_0_0_15))
+              (portRef RSTA (instanceRef pdp_ram_0_0_15))
+              (portRef RSTB (instanceRef pdp_ram_0_1_14))
+              (portRef RSTA (instanceRef pdp_ram_0_1_14))
+              (portRef RSTB (instanceRef pdp_ram_0_2_13))
+              (portRef RSTA (instanceRef pdp_ram_0_2_13))
+              (portRef RSTB (instanceRef pdp_ram_0_3_12))
+              (portRef RSTA (instanceRef pdp_ram_0_3_12))
+              (portRef RSTB (instanceRef pdp_ram_1_0_11))
+              (portRef RSTA (instanceRef pdp_ram_1_0_11))
+              (portRef RSTB (instanceRef pdp_ram_1_1_10))
+              (portRef RSTA (instanceRef pdp_ram_1_1_10))
+              (portRef RSTB (instanceRef pdp_ram_1_2_9))
+              (portRef RSTA (instanceRef pdp_ram_1_2_9))
+              (portRef RSTB (instanceRef pdp_ram_1_3_8))
+              (portRef RSTA (instanceRef pdp_ram_1_3_8))
+              (portRef RSTB (instanceRef pdp_ram_2_0_7))
+              (portRef RSTA (instanceRef pdp_ram_2_0_7))
+              (portRef RSTB (instanceRef pdp_ram_2_1_6))
+              (portRef RSTA (instanceRef pdp_ram_2_1_6))
+              (portRef RSTB (instanceRef pdp_ram_2_2_5))
+              (portRef RSTA (instanceRef pdp_ram_2_2_5))
+              (portRef RSTB (instanceRef pdp_ram_2_3_4))
+              (portRef RSTA (instanceRef pdp_ram_2_3_4))
+              (portRef RSTB (instanceRef pdp_ram_3_0_3))
+              (portRef RSTA (instanceRef pdp_ram_3_0_3))
+              (portRef RSTB (instanceRef pdp_ram_3_1_2))
+              (portRef RSTA (instanceRef pdp_ram_3_1_2))
+              (portRef RSTB (instanceRef pdp_ram_3_2_1))
+              (portRef RSTA (instanceRef pdp_ram_3_2_1))
+              (portRef RSTB (instanceRef pdp_ram_3_3_0))
+              (portRef RSTA (instanceRef pdp_ram_3_3_0))
+              (portRef CD (instanceRef FF_90))
+              (portRef CD (instanceRef FF_89))
+              (portRef CD (instanceRef FF_88))
+              (portRef CD (instanceRef FF_87))
+              (portRef CD (instanceRef FF_86))
+              (portRef CD (instanceRef FF_85))
+              (portRef CD (instanceRef FF_84))
+              (portRef CD (instanceRef FF_83))
+              (portRef CD (instanceRef FF_82))
+              (portRef CD (instanceRef FF_81))
+              (portRef CD (instanceRef FF_80))
+              (portRef CD (instanceRef FF_79))
+              (portRef CD (instanceRef FF_78))
+              (portRef CD (instanceRef FF_77))
+              (portRef PD (instanceRef FF_76))
+              (portRef CD (instanceRef FF_75))
+              (portRef PD (instanceRef FF_74))
+              (portRef CD (instanceRef FF_73))
+              (portRef CD (instanceRef FF_72))
+              (portRef CD (instanceRef FF_71))
+              (portRef CD (instanceRef FF_70))
+              (portRef CD (instanceRef FF_69))
+              (portRef CD (instanceRef FF_68))
+              (portRef CD (instanceRef FF_67))
+              (portRef CD (instanceRef FF_66))
+              (portRef CD (instanceRef FF_65))
+              (portRef CD (instanceRef FF_64))
+              (portRef CD (instanceRef FF_63))
+              (portRef CD (instanceRef FF_62))
+              (portRef CD (instanceRef FF_61))
+              (portRef PD (instanceRef FF_60))
+              (portRef CD (instanceRef FF_59))
+              (portRef CD (instanceRef FF_58))
+              (portRef CD (instanceRef FF_57))
+              (portRef CD (instanceRef FF_56))
+              (portRef CD (instanceRef FF_55))
+              (portRef CD (instanceRef FF_54))
+              (portRef CD (instanceRef FF_53))
+              (portRef CD (instanceRef FF_52))
+              (portRef CD (instanceRef FF_51))
+              (portRef CD (instanceRef FF_50))
+              (portRef CD (instanceRef FF_49))
+              (portRef CD (instanceRef FF_48))
+              (portRef CD (instanceRef FF_47))
+              (portRef CD (instanceRef FF_46))
+              (portRef CD (instanceRef FF_45))
+              (portRef CD (instanceRef FF_44))
+              (portRef CD (instanceRef FF_43))
+              (portRef CD (instanceRef FF_42))
+              (portRef CD (instanceRef FF_41))
+              (portRef CD (instanceRef FF_40))
+              (portRef CD (instanceRef FF_39))
+              (portRef CD (instanceRef FF_38))
+              (portRef CD (instanceRef FF_37))
+              (portRef CD (instanceRef FF_36))
+              (portRef CD (instanceRef FF_35))
+              (portRef CD (instanceRef FF_34))
+              (portRef CD (instanceRef FF_33))
+              (portRef CD (instanceRef FF_32))
+              (portRef CD (instanceRef FF_31))
+              (portRef CD (instanceRef FF_30))
+              (portRef CD (instanceRef FF_29))
+              (portRef CD (instanceRef FF_28))
+              (portRef CD (instanceRef FF_27))
+              (portRef CD (instanceRef FF_26))
+              (portRef CD (instanceRef FF_25))
+              (portRef CD (instanceRef FF_24))
+              (portRef CD (instanceRef FF_23))
+              (portRef CD (instanceRef FF_22))
+              (portRef CD (instanceRef FF_21))
+              (portRef CD (instanceRef FF_20))
+              (portRef CD (instanceRef FF_19))
+              (portRef CD (instanceRef FF_14))
+              (portRef CD (instanceRef FF_13))
+              (portRef CD (instanceRef FF_12))
+              (portRef CD (instanceRef FF_11))
+              (portRef CD (instanceRef FF_10))
+              (portRef CD (instanceRef FF_9))
+              (portRef CD (instanceRef FF_8))
+              (portRef CD (instanceRef FF_7))
+              (portRef CD (instanceRef FF_6))
+              (portRef CD (instanceRef FF_5))
+              (portRef CD (instanceRef FF_4))
+              (portRef CD (instanceRef FF_3))
+              (portRef CD (instanceRef FF_2))
+              (portRef CD (instanceRef FF_1))
+              (portRef CD (instanceRef FF_0))))
+          (net rden
+            (joined
+              (portRef RdEn)
+              (portRef A (instanceRef AND2_t4))))
+          (net wren
+            (joined
+              (portRef WrEn)
+              (portRef A (instanceRef AND2_t5))))
+          (net clk
+            (joined
+              (portRef Clock)
+              (portRef CLKB (instanceRef pdp_ram_0_0_15))
+              (portRef CLKA (instanceRef pdp_ram_0_0_15))
+              (portRef CLKB (instanceRef pdp_ram_0_1_14))
+              (portRef CLKA (instanceRef pdp_ram_0_1_14))
+              (portRef CLKB (instanceRef pdp_ram_0_2_13))
+              (portRef CLKA (instanceRef pdp_ram_0_2_13))
+              (portRef CLKB (instanceRef pdp_ram_0_3_12))
+              (portRef CLKA (instanceRef pdp_ram_0_3_12))
+              (portRef CLKB (instanceRef pdp_ram_1_0_11))
+              (portRef CLKA (instanceRef pdp_ram_1_0_11))
+              (portRef CLKB (instanceRef pdp_ram_1_1_10))
+              (portRef CLKA (instanceRef pdp_ram_1_1_10))
+              (portRef CLKB (instanceRef pdp_ram_1_2_9))
+              (portRef CLKA (instanceRef pdp_ram_1_2_9))
+              (portRef CLKB (instanceRef pdp_ram_1_3_8))
+              (portRef CLKA (instanceRef pdp_ram_1_3_8))
+              (portRef CLKB (instanceRef pdp_ram_2_0_7))
+              (portRef CLKA (instanceRef pdp_ram_2_0_7))
+              (portRef CLKB (instanceRef pdp_ram_2_1_6))
+              (portRef CLKA (instanceRef pdp_ram_2_1_6))
+              (portRef CLKB (instanceRef pdp_ram_2_2_5))
+              (portRef CLKA (instanceRef pdp_ram_2_2_5))
+              (portRef CLKB (instanceRef pdp_ram_2_3_4))
+              (portRef CLKA (instanceRef pdp_ram_2_3_4))
+              (portRef CLKB (instanceRef pdp_ram_3_0_3))
+              (portRef CLKA (instanceRef pdp_ram_3_0_3))
+              (portRef CLKB (instanceRef pdp_ram_3_1_2))
+              (portRef CLKA (instanceRef pdp_ram_3_1_2))
+              (portRef CLKB (instanceRef pdp_ram_3_2_1))
+              (portRef CLKA (instanceRef pdp_ram_3_2_1))
+              (portRef CLKB (instanceRef pdp_ram_3_3_0))
+              (portRef CLKA (instanceRef pdp_ram_3_3_0))
+              (portRef CK (instanceRef FF_90))
+              (portRef CK (instanceRef FF_89))
+              (portRef CK (instanceRef FF_88))
+              (portRef CK (instanceRef FF_87))
+              (portRef CK (instanceRef FF_86))
+              (portRef CK (instanceRef FF_85))
+              (portRef CK (instanceRef FF_84))
+              (portRef CK (instanceRef FF_83))
+              (portRef CK (instanceRef FF_82))
+              (portRef CK (instanceRef FF_81))
+              (portRef CK (instanceRef FF_80))
+              (portRef CK (instanceRef FF_79))
+              (portRef CK (instanceRef FF_78))
+              (portRef CK (instanceRef FF_77))
+              (portRef CK (instanceRef FF_76))
+              (portRef CK (instanceRef FF_75))
+              (portRef CK (instanceRef FF_74))
+              (portRef CK (instanceRef FF_73))
+              (portRef CK (instanceRef FF_72))
+              (portRef CK (instanceRef FF_71))
+              (portRef CK (instanceRef FF_70))
+              (portRef CK (instanceRef FF_69))
+              (portRef CK (instanceRef FF_68))
+              (portRef CK (instanceRef FF_67))
+              (portRef CK (instanceRef FF_66))
+              (portRef CK (instanceRef FF_65))
+              (portRef CK (instanceRef FF_64))
+              (portRef CK (instanceRef FF_63))
+              (portRef CK (instanceRef FF_62))
+              (portRef CK (instanceRef FF_61))
+              (portRef CK (instanceRef FF_60))
+              (portRef CK (instanceRef FF_59))
+              (portRef CK (instanceRef FF_58))
+              (portRef CK (instanceRef FF_57))
+              (portRef CK (instanceRef FF_56))
+              (portRef CK (instanceRef FF_55))
+              (portRef CK (instanceRef FF_54))
+              (portRef CK (instanceRef FF_53))
+              (portRef CK (instanceRef FF_52))
+              (portRef CK (instanceRef FF_51))
+              (portRef CK (instanceRef FF_50))
+              (portRef CK (instanceRef FF_49))
+              (portRef CK (instanceRef FF_48))
+              (portRef CK (instanceRef FF_47))
+              (portRef CK (instanceRef FF_46))
+              (portRef CK (instanceRef FF_45))
+              (portRef CK (instanceRef FF_44))
+              (portRef CK (instanceRef FF_43))
+              (portRef CK (instanceRef FF_42))
+              (portRef CK (instanceRef FF_41))
+              (portRef CK (instanceRef FF_40))
+              (portRef CK (instanceRef FF_39))
+              (portRef CK (instanceRef FF_38))
+              (portRef CK (instanceRef FF_37))
+              (portRef CK (instanceRef FF_36))
+              (portRef CK (instanceRef FF_35))
+              (portRef CK (instanceRef FF_34))
+              (portRef CK (instanceRef FF_33))
+              (portRef CK (instanceRef FF_32))
+              (portRef CK (instanceRef FF_31))
+              (portRef CK (instanceRef FF_30))
+              (portRef CK (instanceRef FF_29))
+              (portRef CK (instanceRef FF_28))
+              (portRef CK (instanceRef FF_27))
+              (portRef CK (instanceRef FF_26))
+              (portRef CK (instanceRef FF_25))
+              (portRef CK (instanceRef FF_24))
+              (portRef CK (instanceRef FF_23))
+              (portRef CK (instanceRef FF_22))
+              (portRef CK (instanceRef FF_21))
+              (portRef CK (instanceRef FF_20))
+              (portRef CK (instanceRef FF_19))
+              (portRef CK (instanceRef FF_18))
+              (portRef CK (instanceRef FF_17))
+              (portRef CK (instanceRef FF_16))
+              (portRef CK (instanceRef FF_15))
+              (portRef CK (instanceRef FF_14))
+              (portRef CK (instanceRef FF_13))
+              (portRef CK (instanceRef FF_12))
+              (portRef CK (instanceRef FF_11))
+              (portRef CK (instanceRef FF_10))
+              (portRef CK (instanceRef FF_9))
+              (portRef CK (instanceRef FF_8))
+              (portRef CK (instanceRef FF_7))
+              (portRef CK (instanceRef FF_6))
+              (portRef CK (instanceRef FF_5))
+              (portRef CK (instanceRef FF_4))
+              (portRef CK (instanceRef FF_3))
+              (portRef CK (instanceRef FF_2))
+              (portRef CK (instanceRef FF_1))
+              (portRef CK (instanceRef FF_0))))
+          (net datain35
+            (joined
+              (portRef (member Data 0))
+              (portRef DIA8 (instanceRef pdp_ram_0_3_12))
+              (portRef DIA8 (instanceRef pdp_ram_1_3_8))
+              (portRef DIA8 (instanceRef pdp_ram_2_3_4))
+              (portRef DIA8 (instanceRef pdp_ram_3_3_0))))
+          (net datain34
+            (joined
+              (portRef (member Data 1))
+              (portRef DIA7 (instanceRef pdp_ram_0_3_12))
+              (portRef DIA7 (instanceRef pdp_ram_1_3_8))
+              (portRef DIA7 (instanceRef pdp_ram_2_3_4))
+              (portRef DIA7 (instanceRef pdp_ram_3_3_0))))
+          (net datain33
+            (joined
+              (portRef (member Data 2))
+              (portRef DIA6 (instanceRef pdp_ram_0_3_12))
+              (portRef DIA6 (instanceRef pdp_ram_1_3_8))
+              (portRef DIA6 (instanceRef pdp_ram_2_3_4))
+              (portRef DIA6 (instanceRef pdp_ram_3_3_0))))
+          (net datain32
+            (joined
+              (portRef (member Data 3))
+              (portRef DIA5 (instanceRef pdp_ram_0_3_12))
+              (portRef DIA5 (instanceRef pdp_ram_1_3_8))
+              (portRef DIA5 (instanceRef pdp_ram_2_3_4))
+              (portRef DIA5 (instanceRef pdp_ram_3_3_0))))
+          (net datain31
+            (joined
+              (portRef (member Data 4))
+              (portRef DIA4 (instanceRef pdp_ram_0_3_12))
+              (portRef DIA4 (instanceRef pdp_ram_1_3_8))
+              (portRef DIA4 (instanceRef pdp_ram_2_3_4))
+              (portRef DIA4 (instanceRef pdp_ram_3_3_0))))
+          (net datain30
+            (joined
+              (portRef (member Data 5))
+              (portRef DIA3 (instanceRef pdp_ram_0_3_12))
+              (portRef DIA3 (instanceRef pdp_ram_1_3_8))
+              (portRef DIA3 (instanceRef pdp_ram_2_3_4))
+              (portRef DIA3 (instanceRef pdp_ram_3_3_0))))
+          (net datain29
+            (joined
+              (portRef (member Data 6))
+              (portRef DIA2 (instanceRef pdp_ram_0_3_12))
+              (portRef DIA2 (instanceRef pdp_ram_1_3_8))
+              (portRef DIA2 (instanceRef pdp_ram_2_3_4))
+              (portRef DIA2 (instanceRef pdp_ram_3_3_0))))
+          (net datain28
+            (joined
+              (portRef (member Data 7))
+              (portRef DIA1 (instanceRef pdp_ram_0_3_12))
+              (portRef DIA1 (instanceRef pdp_ram_1_3_8))
+              (portRef DIA1 (instanceRef pdp_ram_2_3_4))
+              (portRef DIA1 (instanceRef pdp_ram_3_3_0))))
+          (net datain27
+            (joined
+              (portRef (member Data 8))
+              (portRef DIA0 (instanceRef pdp_ram_0_3_12))
+              (portRef DIA0 (instanceRef pdp_ram_1_3_8))
+              (portRef DIA0 (instanceRef pdp_ram_2_3_4))
+              (portRef DIA0 (instanceRef pdp_ram_3_3_0))))
+          (net datain26
+            (joined
+              (portRef (member Data 9))
+              (portRef DIA8 (instanceRef pdp_ram_0_2_13))
+              (portRef DIA8 (instanceRef pdp_ram_1_2_9))
+              (portRef DIA8 (instanceRef pdp_ram_2_2_5))
+              (portRef DIA8 (instanceRef pdp_ram_3_2_1))))
+          (net datain25
+            (joined
+              (portRef (member Data 10))
+              (portRef DIA7 (instanceRef pdp_ram_0_2_13))
+              (portRef DIA7 (instanceRef pdp_ram_1_2_9))
+              (portRef DIA7 (instanceRef pdp_ram_2_2_5))
+              (portRef DIA7 (instanceRef pdp_ram_3_2_1))))
+          (net datain24
+            (joined
+              (portRef (member Data 11))
+              (portRef DIA6 (instanceRef pdp_ram_0_2_13))
+              (portRef DIA6 (instanceRef pdp_ram_1_2_9))
+              (portRef DIA6 (instanceRef pdp_ram_2_2_5))
+              (portRef DIA6 (instanceRef pdp_ram_3_2_1))))
+          (net datain23
+            (joined
+              (portRef (member Data 12))
+              (portRef DIA5 (instanceRef pdp_ram_0_2_13))
+              (portRef DIA5 (instanceRef pdp_ram_1_2_9))
+              (portRef DIA5 (instanceRef pdp_ram_2_2_5))
+              (portRef DIA5 (instanceRef pdp_ram_3_2_1))))
+          (net datain22
+            (joined
+              (portRef (member Data 13))
+              (portRef DIA4 (instanceRef pdp_ram_0_2_13))
+              (portRef DIA4 (instanceRef pdp_ram_1_2_9))
+              (portRef DIA4 (instanceRef pdp_ram_2_2_5))
+              (portRef DIA4 (instanceRef pdp_ram_3_2_1))))
+          (net datain21
+            (joined
+              (portRef (member Data 14))
+              (portRef DIA3 (instanceRef pdp_ram_0_2_13))
+              (portRef DIA3 (instanceRef pdp_ram_1_2_9))
+              (portRef DIA3 (instanceRef pdp_ram_2_2_5))
+              (portRef DIA3 (instanceRef pdp_ram_3_2_1))))
+          (net datain20
+            (joined
+              (portRef (member Data 15))
+              (portRef DIA2 (instanceRef pdp_ram_0_2_13))
+              (portRef DIA2 (instanceRef pdp_ram_1_2_9))
+              (portRef DIA2 (instanceRef pdp_ram_2_2_5))
+              (portRef DIA2 (instanceRef pdp_ram_3_2_1))))
+          (net datain19
+            (joined
+              (portRef (member Data 16))
+              (portRef DIA1 (instanceRef pdp_ram_0_2_13))
+              (portRef DIA1 (instanceRef pdp_ram_1_2_9))
+              (portRef DIA1 (instanceRef pdp_ram_2_2_5))
+              (portRef DIA1 (instanceRef pdp_ram_3_2_1))))
+          (net datain18
+            (joined
+              (portRef (member Data 17))
+              (portRef DIA0 (instanceRef pdp_ram_0_2_13))
+              (portRef DIA0 (instanceRef pdp_ram_1_2_9))
+              (portRef DIA0 (instanceRef pdp_ram_2_2_5))
+              (portRef DIA0 (instanceRef pdp_ram_3_2_1))))
+          (net datain17
+            (joined
+              (portRef (member Data 18))
+              (portRef DIA8 (instanceRef pdp_ram_0_1_14))
+              (portRef DIA8 (instanceRef pdp_ram_1_1_10))
+              (portRef DIA8 (instanceRef pdp_ram_2_1_6))
+              (portRef DIA8 (instanceRef pdp_ram_3_1_2))))
+          (net datain16
+            (joined
+              (portRef (member Data 19))
+              (portRef DIA7 (instanceRef pdp_ram_0_1_14))
+              (portRef DIA7 (instanceRef pdp_ram_1_1_10))
+              (portRef DIA7 (instanceRef pdp_ram_2_1_6))
+              (portRef DIA7 (instanceRef pdp_ram_3_1_2))))
+          (net datain15
+            (joined
+              (portRef (member Data 20))
+              (portRef DIA6 (instanceRef pdp_ram_0_1_14))
+              (portRef DIA6 (instanceRef pdp_ram_1_1_10))
+              (portRef DIA6 (instanceRef pdp_ram_2_1_6))
+              (portRef DIA6 (instanceRef pdp_ram_3_1_2))))
+          (net datain14
+            (joined
+              (portRef (member Data 21))
+              (portRef DIA5 (instanceRef pdp_ram_0_1_14))
+              (portRef DIA5 (instanceRef pdp_ram_1_1_10))
+              (portRef DIA5 (instanceRef pdp_ram_2_1_6))
+              (portRef DIA5 (instanceRef pdp_ram_3_1_2))))
+          (net datain13
+            (joined
+              (portRef (member Data 22))
+              (portRef DIA4 (instanceRef pdp_ram_0_1_14))
+              (portRef DIA4 (instanceRef pdp_ram_1_1_10))
+              (portRef DIA4 (instanceRef pdp_ram_2_1_6))
+              (portRef DIA4 (instanceRef pdp_ram_3_1_2))))
+          (net datain12
+            (joined
+              (portRef (member Data 23))
+              (portRef DIA3 (instanceRef pdp_ram_0_1_14))
+              (portRef DIA3 (instanceRef pdp_ram_1_1_10))
+              (portRef DIA3 (instanceRef pdp_ram_2_1_6))
+              (portRef DIA3 (instanceRef pdp_ram_3_1_2))))
+          (net datain11
+            (joined
+              (portRef (member Data 24))
+              (portRef DIA2 (instanceRef pdp_ram_0_1_14))
+              (portRef DIA2 (instanceRef pdp_ram_1_1_10))
+              (portRef DIA2 (instanceRef pdp_ram_2_1_6))
+              (portRef DIA2 (instanceRef pdp_ram_3_1_2))))
+          (net datain10
+            (joined
+              (portRef (member Data 25))
+              (portRef DIA1 (instanceRef pdp_ram_0_1_14))
+              (portRef DIA1 (instanceRef pdp_ram_1_1_10))
+              (portRef DIA1 (instanceRef pdp_ram_2_1_6))
+              (portRef DIA1 (instanceRef pdp_ram_3_1_2))))
+          (net datain9
+            (joined
+              (portRef (member Data 26))
+              (portRef DIA0 (instanceRef pdp_ram_0_1_14))
+              (portRef DIA0 (instanceRef pdp_ram_1_1_10))
+              (portRef DIA0 (instanceRef pdp_ram_2_1_6))
+              (portRef DIA0 (instanceRef pdp_ram_3_1_2))))
+          (net datain8
+            (joined
+              (portRef (member Data 27))
+              (portRef DIA8 (instanceRef pdp_ram_0_0_15))
+              (portRef DIA8 (instanceRef pdp_ram_1_0_11))
+              (portRef DIA8 (instanceRef pdp_ram_2_0_7))
+              (portRef DIA8 (instanceRef pdp_ram_3_0_3))))
+          (net datain7
+            (joined
+              (portRef (member Data 28))
+              (portRef DIA7 (instanceRef pdp_ram_0_0_15))
+              (portRef DIA7 (instanceRef pdp_ram_1_0_11))
+              (portRef DIA7 (instanceRef pdp_ram_2_0_7))
+              (portRef DIA7 (instanceRef pdp_ram_3_0_3))))
+          (net datain6
+            (joined
+              (portRef (member Data 29))
+              (portRef DIA6 (instanceRef pdp_ram_0_0_15))
+              (portRef DIA6 (instanceRef pdp_ram_1_0_11))
+              (portRef DIA6 (instanceRef pdp_ram_2_0_7))
+              (portRef DIA6 (instanceRef pdp_ram_3_0_3))))
+          (net datain5
+            (joined
+              (portRef (member Data 30))
+              (portRef DIA5 (instanceRef pdp_ram_0_0_15))
+              (portRef DIA5 (instanceRef pdp_ram_1_0_11))
+              (portRef DIA5 (instanceRef pdp_ram_2_0_7))
+              (portRef DIA5 (instanceRef pdp_ram_3_0_3))))
+          (net datain4
+            (joined
+              (portRef (member Data 31))
+              (portRef DIA4 (instanceRef pdp_ram_0_0_15))
+              (portRef DIA4 (instanceRef pdp_ram_1_0_11))
+              (portRef DIA4 (instanceRef pdp_ram_2_0_7))
+              (portRef DIA4 (instanceRef pdp_ram_3_0_3))))
+          (net datain3
+            (joined
+              (portRef (member Data 32))
+              (portRef DIA3 (instanceRef pdp_ram_0_0_15))
+              (portRef DIA3 (instanceRef pdp_ram_1_0_11))
+              (portRef DIA3 (instanceRef pdp_ram_2_0_7))
+              (portRef DIA3 (instanceRef pdp_ram_3_0_3))))
+          (net datain2
+            (joined
+              (portRef (member Data 33))
+              (portRef DIA2 (instanceRef pdp_ram_0_0_15))
+              (portRef DIA2 (instanceRef pdp_ram_1_0_11))
+              (portRef DIA2 (instanceRef pdp_ram_2_0_7))
+              (portRef DIA2 (instanceRef pdp_ram_3_0_3))))
+          (net datain1
+            (joined
+              (portRef (member Data 34))
+              (portRef DIA1 (instanceRef pdp_ram_0_0_15))
+              (portRef DIA1 (instanceRef pdp_ram_1_0_11))
+              (portRef DIA1 (instanceRef pdp_ram_2_0_7))
+              (portRef DIA1 (instanceRef pdp_ram_3_0_3))))
+          (net datain0
+            (joined
+              (portRef (member Data 35))
+              (portRef DIA0 (instanceRef pdp_ram_0_0_15))
+              (portRef DIA0 (instanceRef pdp_ram_1_0_11))
+              (portRef DIA0 (instanceRef pdp_ram_2_0_7))
+              (portRef DIA0 (instanceRef pdp_ram_3_0_3))))))))
+  (design fifo_36x8k_oreg
+    (cellRef fifo_36x8k_oreg
+      (libraryRef ORCLIB)))
+)

diff --git a/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.fdc b/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.fdc
new file mode 100644 (file)
index 0000000..6fbcac9
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.fdc
@@ -0,0 +1,2 @@
+###==== Start Configuration
+

diff --git a/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.lpc b/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.lpc
new file mode 100644 (file)
index 0000000..eac07d5
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.lpc
@@ -0,0 +1,50 @@
+[Device]
+Family=ecp5um
+PartType=LFE5UM-85F
+PartName=LFE5UM-85F-8MG285C
+SpeedGrade=8
+Package=CSFBGA285
+OperatingCondition=COM
+Status=C
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO
+CoreRevision=5.0
+ModuleName=fifo_36x8k_oreg
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=03/18/2015
+Time=14:41:45
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=8192
+Width=36
+regout=1
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=1
+PfMode=Dynamic - Single Threshold
+PfAssert=508
+PfDeassert=506
+Reset=Async
+Reset1=Sync
+RDataCount=1
+EnECC=0
+EnFWFT=0
+
+[Command]
+cmd_line= -w -n fifo_36x8k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 8192 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill

diff --git a/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.ngd b/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.ngd
new file mode 100644 (file)
index 0000000..ff7f458
Binary files /dev/null and b/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.ngd differ

diff --git a/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.ngo b/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.ngo
new file mode 100644 (file)
index 0000000..3d987c6
Binary files /dev/null and b/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.ngo differ

diff --git a/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.vhd b/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.vhd
new file mode 100644 (file)
index 0000000..d5a618c
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.vhd
@@ -0,0 +1,2200 @@
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80
+-- Module  Version: 5.0
+--/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x8k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 8192 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.fdc 
+
+-- Wed Mar 18 14:41:46 2015
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity fifo_36x8k_oreg is
+    port (
+        Data: in  std_logic_vector(35 downto 0); 
+        Clock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        AmFullThresh: in  std_logic_vector(12 downto 0); 
+        Q: out  std_logic_vector(35 downto 0); 
+        WCNT: out  std_logic_vector(13 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic; 
+        AlmostFull: out  std_logic);
+end fifo_36x8k_oreg;
+
+architecture Structure of fifo_36x8k_oreg is
+
+    -- internal signal declarations
+    signal invout_2: std_logic;
+    signal invout_1: std_logic;
+    signal rden_i_inv: std_logic;
+    signal invout_0: std_logic;
+    signal r_nw: std_logic;
+    signal fcnt_en: std_logic;
+    signal empty_i: std_logic;
+    signal empty_d: std_logic;
+    signal full_i: std_logic;
+    signal full_d: std_logic;
+    signal wptr_0: std_logic;
+    signal wptr_1: std_logic;
+    signal wptr_2: std_logic;
+    signal wptr_3: std_logic;
+    signal wptr_4: std_logic;
+    signal wptr_5: std_logic;
+    signal wptr_6: std_logic;
+    signal wptr_7: std_logic;
+    signal wptr_8: std_logic;
+    signal wptr_9: std_logic;
+    signal wptr_10: std_logic;
+    signal wptr_11: std_logic;
+    signal wptr_12: std_logic;
+    signal wptr_13: std_logic;
+    signal rptr_13: std_logic;
+    signal rptr_11_ff: std_logic;
+    signal rptr_12_ff: std_logic;
+    signal ifcount_0: std_logic;
+    signal ifcount_1: std_logic;
+    signal bdcnt_bctr_ci: std_logic;
+    signal ifcount_2: std_logic;
+    signal ifcount_3: std_logic;
+    signal co0: std_logic;
+    signal ifcount_4: std_logic;
+    signal ifcount_5: std_logic;
+    signal co1: std_logic;
+    signal ifcount_6: std_logic;
+    signal ifcount_7: std_logic;
+    signal co2: std_logic;
+    signal ifcount_8: std_logic;
+    signal ifcount_9: std_logic;
+    signal co3: std_logic;
+    signal ifcount_10: std_logic;
+    signal ifcount_11: std_logic;
+    signal co4: std_logic;
+    signal ifcount_12: std_logic;
+    signal ifcount_13: std_logic;
+    signal co6: std_logic;
+    signal co5: std_logic;
+    signal cmp_ci: std_logic;
+    signal rden_i: std_logic;
+    signal co0_1: std_logic;
+    signal co1_1: std_logic;
+    signal co2_1: std_logic;
+    signal co3_1: std_logic;
+    signal co4_1: std_logic;
+    signal co5_1: std_logic;
+    signal cmp_le_1: std_logic;
+    signal cmp_le_1_c: std_logic;
+    signal cmp_ci_1: std_logic;
+    signal fcount_0: std_logic;
+    signal fcount_1: std_logic;
+    signal co0_2: std_logic;
+    signal fcount_2: std_logic;
+    signal fcount_3: std_logic;
+    signal co1_2: std_logic;
+    signal fcount_4: std_logic;
+    signal fcount_5: std_logic;
+    signal co2_2: std_logic;
+    signal fcount_6: std_logic;
+    signal fcount_7: std_logic;
+    signal co3_2: std_logic;
+    signal fcount_8: std_logic;
+    signal fcount_9: std_logic;
+    signal co4_2: std_logic;
+    signal fcount_10: std_logic;
+    signal fcount_11: std_logic;
+    signal co5_2: std_logic;
+    signal wren_i_inv: std_logic;
+    signal fcount_12: std_logic;
+    signal fcount_13: std_logic;
+    signal cmp_ge_d1: std_logic;
+    signal cmp_ge_d1_c: std_logic;
+    signal iwcount_0: std_logic;
+    signal iwcount_1: std_logic;
+    signal w_ctr_ci: std_logic;
+    signal iwcount_2: std_logic;
+    signal iwcount_3: std_logic;
+    signal co0_3: std_logic;
+    signal iwcount_4: std_logic;
+    signal iwcount_5: std_logic;
+    signal co1_3: std_logic;
+    signal iwcount_6: std_logic;
+    signal iwcount_7: std_logic;
+    signal co2_3: std_logic;
+    signal iwcount_8: std_logic;
+    signal iwcount_9: std_logic;
+    signal co3_3: std_logic;
+    signal iwcount_10: std_logic;
+    signal iwcount_11: std_logic;
+    signal co4_3: std_logic;
+    signal iwcount_12: std_logic;
+    signal iwcount_13: std_logic;
+    signal co6_1: std_logic;
+    signal co5_3: std_logic;
+    signal wcount_13: std_logic;
+    signal ircount_0: std_logic;
+    signal ircount_1: std_logic;
+    signal r_ctr_ci: std_logic;
+    signal rcount_0: std_logic;
+    signal rcount_1: std_logic;
+    signal ircount_2: std_logic;
+    signal ircount_3: std_logic;
+    signal co0_4: std_logic;
+    signal rcount_2: std_logic;
+    signal rcount_3: std_logic;
+    signal ircount_4: std_logic;
+    signal ircount_5: std_logic;
+    signal co1_4: std_logic;
+    signal rcount_4: std_logic;
+    signal rcount_5: std_logic;
+    signal ircount_6: std_logic;
+    signal ircount_7: std_logic;
+    signal co2_4: std_logic;
+    signal rcount_6: std_logic;
+    signal rcount_7: std_logic;
+    signal ircount_8: std_logic;
+    signal ircount_9: std_logic;
+    signal co3_4: std_logic;
+    signal rcount_8: std_logic;
+    signal rcount_9: std_logic;
+    signal ircount_10: std_logic;
+    signal ircount_11: std_logic;
+    signal co4_4: std_logic;
+    signal rcount_10: std_logic;
+    signal rcount_11: std_logic;
+    signal ircount_12: std_logic;
+    signal ircount_13: std_logic;
+    signal co6_2: std_logic;
+    signal co5_4: std_logic;
+    signal rcount_12: std_logic;
+    signal rcount_13: std_logic;
+    signal mdout1_3_0: std_logic;
+    signal mdout1_2_0: std_logic;
+    signal mdout1_1_0: std_logic;
+    signal mdout1_0_0: std_logic;
+    signal mdout1_3_1: std_logic;
+    signal mdout1_2_1: std_logic;
+    signal mdout1_1_1: std_logic;
+    signal mdout1_0_1: std_logic;
+    signal mdout1_3_2: std_logic;
+    signal mdout1_2_2: std_logic;
+    signal mdout1_1_2: std_logic;
+    signal mdout1_0_2: std_logic;
+    signal mdout1_3_3: std_logic;
+    signal mdout1_2_3: std_logic;
+    signal mdout1_1_3: std_logic;
+    signal mdout1_0_3: std_logic;
+    signal mdout1_3_4: std_logic;
+    signal mdout1_2_4: std_logic;
+    signal mdout1_1_4: std_logic;
+    signal mdout1_0_4: std_logic;
+    signal mdout1_3_5: std_logic;
+    signal mdout1_2_5: std_logic;
+    signal mdout1_1_5: std_logic;
+    signal mdout1_0_5: std_logic;
+    signal mdout1_3_6: std_logic;
+    signal mdout1_2_6: std_logic;
+    signal mdout1_1_6: std_logic;
+    signal mdout1_0_6: std_logic;
+    signal mdout1_3_7: std_logic;
+    signal mdout1_2_7: std_logic;
+    signal mdout1_1_7: std_logic;
+    signal mdout1_0_7: std_logic;
+    signal mdout1_3_8: std_logic;
+    signal mdout1_2_8: std_logic;
+    signal mdout1_1_8: std_logic;
+    signal mdout1_0_8: std_logic;
+    signal mdout1_3_9: std_logic;
+    signal mdout1_2_9: std_logic;
+    signal mdout1_1_9: std_logic;
+    signal mdout1_0_9: std_logic;
+    signal mdout1_3_10: std_logic;
+    signal mdout1_2_10: std_logic;
+    signal mdout1_1_10: std_logic;
+    signal mdout1_0_10: std_logic;
+    signal mdout1_3_11: std_logic;
+    signal mdout1_2_11: std_logic;
+    signal mdout1_1_11: std_logic;
+    signal mdout1_0_11: std_logic;
+    signal mdout1_3_12: std_logic;
+    signal mdout1_2_12: std_logic;
+    signal mdout1_1_12: std_logic;
+    signal mdout1_0_12: std_logic;
+    signal mdout1_3_13: std_logic;
+    signal mdout1_2_13: std_logic;
+    signal mdout1_1_13: std_logic;
+    signal mdout1_0_13: std_logic;
+    signal mdout1_3_14: std_logic;
+    signal mdout1_2_14: std_logic;
+    signal mdout1_1_14: std_logic;
+    signal mdout1_0_14: std_logic;
+    signal mdout1_3_15: std_logic;
+    signal mdout1_2_15: std_logic;
+    signal mdout1_1_15: std_logic;
+    signal mdout1_0_15: std_logic;
+    signal mdout1_3_16: std_logic;
+    signal mdout1_2_16: std_logic;
+    signal mdout1_1_16: std_logic;
+    signal mdout1_0_16: std_logic;
+    signal mdout1_3_17: std_logic;
+    signal mdout1_2_17: std_logic;
+    signal mdout1_1_17: std_logic;
+    signal mdout1_0_17: std_logic;
+    signal mdout1_3_18: std_logic;
+    signal mdout1_2_18: std_logic;
+    signal mdout1_1_18: std_logic;
+    signal mdout1_0_18: std_logic;
+    signal mdout1_3_19: std_logic;
+    signal mdout1_2_19: std_logic;
+    signal mdout1_1_19: std_logic;
+    signal mdout1_0_19: std_logic;
+    signal mdout1_3_20: std_logic;
+    signal mdout1_2_20: std_logic;
+    signal mdout1_1_20: std_logic;
+    signal mdout1_0_20: std_logic;
+    signal mdout1_3_21: std_logic;
+    signal mdout1_2_21: std_logic;
+    signal mdout1_1_21: std_logic;
+    signal mdout1_0_21: std_logic;
+    signal mdout1_3_22: std_logic;
+    signal mdout1_2_22: std_logic;
+    signal mdout1_1_22: std_logic;
+    signal mdout1_0_22: std_logic;
+    signal mdout1_3_23: std_logic;
+    signal mdout1_2_23: std_logic;
+    signal mdout1_1_23: std_logic;
+    signal mdout1_0_23: std_logic;
+    signal mdout1_3_24: std_logic;
+    signal mdout1_2_24: std_logic;
+    signal mdout1_1_24: std_logic;
+    signal mdout1_0_24: std_logic;
+    signal mdout1_3_25: std_logic;
+    signal mdout1_2_25: std_logic;
+    signal mdout1_1_25: std_logic;
+    signal mdout1_0_25: std_logic;
+    signal mdout1_3_26: std_logic;
+    signal mdout1_2_26: std_logic;
+    signal mdout1_1_26: std_logic;
+    signal mdout1_0_26: std_logic;
+    signal mdout1_3_27: std_logic;
+    signal mdout1_2_27: std_logic;
+    signal mdout1_1_27: std_logic;
+    signal mdout1_0_27: std_logic;
+    signal mdout1_3_28: std_logic;
+    signal mdout1_2_28: std_logic;
+    signal mdout1_1_28: std_logic;
+    signal mdout1_0_28: std_logic;
+    signal mdout1_3_29: std_logic;
+    signal mdout1_2_29: std_logic;
+    signal mdout1_1_29: std_logic;
+    signal mdout1_0_29: std_logic;
+    signal mdout1_3_30: std_logic;
+    signal mdout1_2_30: std_logic;
+    signal mdout1_1_30: std_logic;
+    signal mdout1_0_30: std_logic;
+    signal mdout1_3_31: std_logic;
+    signal mdout1_2_31: std_logic;
+    signal mdout1_1_31: std_logic;
+    signal mdout1_0_31: std_logic;
+    signal mdout1_3_32: std_logic;
+    signal mdout1_2_32: std_logic;
+    signal mdout1_1_32: std_logic;
+    signal mdout1_0_32: std_logic;
+    signal mdout1_3_33: std_logic;
+    signal mdout1_2_33: std_logic;
+    signal mdout1_1_33: std_logic;
+    signal mdout1_0_33: std_logic;
+    signal mdout1_3_34: std_logic;
+    signal mdout1_2_34: std_logic;
+    signal mdout1_1_34: std_logic;
+    signal mdout1_0_34: std_logic;
+    signal rptr_12_ff2: std_logic;
+    signal rptr_11_ff2: std_logic;
+    signal mdout1_3_35: std_logic;
+    signal mdout1_2_35: std_logic;
+    signal mdout1_1_35: std_logic;
+    signal mdout1_0_35: std_logic;
+    signal wcnt_sub_0: std_logic;
+    signal rptr_0: std_logic;
+    signal cnt_con_inv: std_logic;
+    signal wcount_0: std_logic;
+    signal cnt_con: std_logic;
+    signal precin: std_logic;
+    signal wcnt_sub_1: std_logic;
+    signal wcnt_sub_2: std_logic;
+    signal rptr_2: std_logic;
+    signal rptr_1: std_logic;
+    signal wcount_2: std_logic;
+    signal wcount_1: std_logic;
+    signal co0_5: std_logic;
+    signal wcnt_sub_3: std_logic;
+    signal wcnt_sub_4: std_logic;
+    signal rptr_4: std_logic;
+    signal rptr_3: std_logic;
+    signal wcount_4: std_logic;
+    signal wcount_3: std_logic;
+    signal co1_5: std_logic;
+    signal wcnt_sub_5: std_logic;
+    signal wcnt_sub_6: std_logic;
+    signal rptr_6: std_logic;
+    signal rptr_5: std_logic;
+    signal wcount_6: std_logic;
+    signal wcount_5: std_logic;
+    signal co2_5: std_logic;
+    signal wcnt_sub_7: std_logic;
+    signal wcnt_sub_8: std_logic;
+    signal rptr_8: std_logic;
+    signal rptr_7: std_logic;
+    signal wcount_8: std_logic;
+    signal wcount_7: std_logic;
+    signal co3_5: std_logic;
+    signal wcnt_sub_9: std_logic;
+    signal wcnt_sub_10: std_logic;
+    signal rptr_10: std_logic;
+    signal rptr_9: std_logic;
+    signal wcount_10: std_logic;
+    signal wcount_9: std_logic;
+    signal co4_5: std_logic;
+    signal wcnt_sub_11: std_logic;
+    signal wcnt_sub_12: std_logic;
+    signal rptr_12: std_logic;
+    signal rptr_11: std_logic;
+    signal wcount_12: std_logic;
+    signal wcount_11: std_logic;
+    signal co5_5: std_logic;
+    signal wcnt_sub_13: std_logic;
+    signal wcnt_sub_msb: std_logic;
+    signal co6_3: std_logic;
+    signal wren_i: std_logic;
+    signal cmp_ci_2: std_logic;
+    signal wcnt_reg_0: std_logic;
+    signal wcnt_reg_1: std_logic;
+    signal co0_6: std_logic;
+    signal wcnt_reg_2: std_logic;
+    signal wcnt_reg_3: std_logic;
+    signal co1_6: std_logic;
+    signal wcnt_reg_4: std_logic;
+    signal wcnt_reg_5: std_logic;
+    signal co2_6: std_logic;
+    signal wcnt_reg_6: std_logic;
+    signal wcnt_reg_7: std_logic;
+    signal co3_6: std_logic;
+    signal wcnt_reg_8: std_logic;
+    signal wcnt_reg_9: std_logic;
+    signal co4_6: std_logic;
+    signal wcnt_reg_10: std_logic;
+    signal wcnt_reg_11: std_logic;
+    signal co5_6: std_logic;
+    signal wcnt_reg_12: std_logic;
+    signal wcnt_reg_13: std_logic;
+    signal af_set: std_logic;
+    signal scuba_vhi: std_logic;
+    signal scuba_vlo: std_logic;
+    signal af_set_c: std_logic;
+
+    attribute MEM_LPC_FILE : string; 
+    attribute MEM_INIT_FILE : string; 
+    attribute GSR : string; 
+    attribute MEM_LPC_FILE of pdp_ram_0_0_15 : label is "fifo_36x8k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_0_15 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_0_1_14 : label is "fifo_36x8k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_1_14 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_0_2_13 : label is "fifo_36x8k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_2_13 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_0_3_12 : label is "fifo_36x8k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_3_12 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_1_0_11 : label is "fifo_36x8k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_1_0_11 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_1_1_10 : label is "fifo_36x8k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_1_1_10 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_1_2_9 : label is "fifo_36x8k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_1_2_9 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_1_3_8 : label is "fifo_36x8k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_1_3_8 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_2_0_7 : label is "fifo_36x8k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_2_0_7 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_2_1_6 : label is "fifo_36x8k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_2_1_6 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_2_2_5 : label is "fifo_36x8k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_2_2_5 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_2_3_4 : label is "fifo_36x8k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_2_3_4 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_3_0_3 : label is "fifo_36x8k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_3_0_3 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_3_1_2 : label is "fifo_36x8k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_3_1_2 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_3_2_1 : label is "fifo_36x8k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_3_2_1 : label is "";
+    attribute MEM_LPC_FILE of pdp_ram_3_3_0 : label is "fifo_36x8k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_3_3_0 : label is "";
+    attribute GSR of FF_90 : label is "ENABLED";
+    attribute GSR of FF_89 : label is "ENABLED";
+    attribute GSR of FF_88 : label is "ENABLED";
+    attribute GSR of FF_87 : label is "ENABLED";
+    attribute GSR of FF_86 : label is "ENABLED";
+    attribute GSR of FF_85 : label is "ENABLED";
+    attribute GSR of FF_84 : label is "ENABLED";
+    attribute GSR of FF_83 : label is "ENABLED";
+    attribute GSR of FF_82 : label is "ENABLED";
+    attribute GSR of FF_81 : label is "ENABLED";
+    attribute GSR of FF_80 : label is "ENABLED";
+    attribute GSR of FF_79 : label is "ENABLED";
+    attribute GSR of FF_78 : label is "ENABLED";
+    attribute GSR of FF_77 : label is "ENABLED";
+    attribute GSR of FF_76 : label is "ENABLED";
+    attribute GSR of FF_75 : label is "ENABLED";
+    attribute GSR of FF_74 : label is "ENABLED";
+    attribute GSR of FF_73 : label is "ENABLED";
+    attribute GSR of FF_72 : label is "ENABLED";
+    attribute GSR of FF_71 : label is "ENABLED";
+    attribute GSR of FF_70 : label is "ENABLED";
+    attribute GSR of FF_69 : label is "ENABLED";
+    attribute GSR of FF_68 : label is "ENABLED";
+    attribute GSR of FF_67 : label is "ENABLED";
+    attribute GSR of FF_66 : label is "ENABLED";
+    attribute GSR of FF_65 : label is "ENABLED";
+    attribute GSR of FF_64 : label is "ENABLED";
+    attribute GSR of FF_63 : label is "ENABLED";
+    attribute GSR of FF_62 : label is "ENABLED";
+    attribute GSR of FF_61 : label is "ENABLED";
+    attribute GSR of FF_60 : label is "ENABLED";
+    attribute GSR of FF_59 : label is "ENABLED";
+    attribute GSR of FF_58 : label is "ENABLED";
+    attribute GSR of FF_57 : label is "ENABLED";
+    attribute GSR of FF_56 : label is "ENABLED";
+    attribute GSR of FF_55 : label is "ENABLED";
+    attribute GSR of FF_54 : label is "ENABLED";
+    attribute GSR of FF_53 : label is "ENABLED";
+    attribute GSR of FF_52 : label is "ENABLED";
+    attribute GSR of FF_51 : label is "ENABLED";
+    attribute GSR of FF_50 : label is "ENABLED";
+    attribute GSR of FF_49 : label is "ENABLED";
+    attribute GSR of FF_48 : label is "ENABLED";
+    attribute GSR of FF_47 : label is "ENABLED";
+    attribute GSR of FF_46 : label is "ENABLED";
+    attribute GSR of FF_45 : label is "ENABLED";
+    attribute GSR of FF_44 : label is "ENABLED";
+    attribute GSR of FF_43 : label is "ENABLED";
+    attribute GSR of FF_42 : label is "ENABLED";
+    attribute GSR of FF_41 : label is "ENABLED";
+    attribute GSR of FF_40 : label is "ENABLED";
+    attribute GSR of FF_39 : label is "ENABLED";
+    attribute GSR of FF_38 : label is "ENABLED";
+    attribute GSR of FF_37 : label is "ENABLED";
+    attribute GSR of FF_36 : label is "ENABLED";
+    attribute GSR of FF_35 : label is "ENABLED";
+    attribute GSR of FF_34 : label is "ENABLED";
+    attribute GSR of FF_33 : label is "ENABLED";
+    attribute GSR of FF_32 : label is "ENABLED";
+    attribute GSR of FF_31 : label is "ENABLED";
+    attribute GSR of FF_30 : label is "ENABLED";
+    attribute GSR of FF_29 : label is "ENABLED";
+    attribute GSR of FF_28 : label is "ENABLED";
+    attribute GSR of FF_27 : label is "ENABLED";
+    attribute GSR of FF_26 : label is "ENABLED";
+    attribute GSR of FF_25 : label is "ENABLED";
+    attribute GSR of FF_24 : label is "ENABLED";
+    attribute GSR of FF_23 : label is "ENABLED";
+    attribute GSR of FF_22 : label is "ENABLED";
+    attribute GSR of FF_21 : label is "ENABLED";
+    attribute GSR of FF_20 : label is "ENABLED";
+    attribute GSR of FF_19 : label is "ENABLED";
+    attribute GSR of FF_18 : label is "ENABLED";
+    attribute GSR of FF_17 : label is "ENABLED";
+    attribute GSR of FF_16 : label is "ENABLED";
+    attribute GSR of FF_15 : label is "ENABLED";
+    attribute GSR of FF_14 : label is "ENABLED";
+    attribute GSR of FF_13 : label is "ENABLED";
+    attribute GSR of FF_12 : label is "ENABLED";
+    attribute GSR of FF_11 : label is "ENABLED";
+    attribute GSR of FF_10 : label is "ENABLED";
+    attribute GSR of FF_9 : label is "ENABLED";
+    attribute GSR of FF_8 : label is "ENABLED";
+    attribute GSR of FF_7 : label is "ENABLED";
+    attribute GSR of FF_6 : label is "ENABLED";
+    attribute GSR of FF_5 : label is "ENABLED";
+    attribute GSR of FF_4 : label is "ENABLED";
+    attribute GSR of FF_3 : label is "ENABLED";
+    attribute GSR of FF_2 : label is "ENABLED";
+    attribute GSR of FF_1 : label is "ENABLED";
+    attribute GSR of FF_0 : label is "ENABLED";
+    attribute syn_keep : boolean;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    AND2_t5: AND2
+        port map (A=>WrEn, B=>invout_2, Z=>wren_i);
+
+    INV_5: INV
+        port map (A=>full_i, Z=>invout_2);
+
+    AND2_t4: AND2
+        port map (A=>RdEn, B=>invout_1, Z=>rden_i);
+
+    INV_4: INV
+        port map (A=>empty_i, Z=>invout_1);
+
+    AND2_t3: AND2
+        port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
+
+    XOR2_t2: XOR2
+        port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
+
+    INV_3: INV
+        port map (A=>rden_i, Z=>rden_i_inv);
+
+    INV_2: INV
+        port map (A=>wren_i, Z=>wren_i_inv);
+
+    LUT4_1: ROM16X1A
+        generic map (initval=> X"3232")
+        port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, 
+            AD0=>empty_i, DO0=>empty_d);
+
+    LUT4_0: ROM16X1A
+        generic map (initval=> X"3232")
+        port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, 
+            AD0=>full_i, DO0=>full_d);
+
+    AND2_t1: AND2
+        port map (A=>rden_i, B=>invout_0, Z=>r_nw);
+
+    INV_1: INV
+        port map (A=>wren_i, Z=>invout_0);
+
+    XOR2_t0: XOR2
+        port map (A=>wcount_13, B=>rptr_13, Z=>wcnt_sub_msb);
+
+    INV_0: INV
+        port map (A=>cnt_con, Z=>cnt_con_inv);
+
+    pdp_ram_0_0_15: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), 
+            DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), 
+            DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, 
+            ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, 
+            ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, 
+            ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, 
+            CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, 
+            CSA2=>scuba_vlo, CSA1=>wptr_12, CSA0=>wptr_11, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>rptr_12, CSB0=>rptr_11, RSTB=>Reset, 
+            DOA17=>open, DOA16=>open, DOA15=>open, DOA14=>open, 
+            DOA13=>open, DOA12=>open, DOA11=>open, DOA10=>open, 
+            DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open, 
+            DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open, 
+            DOB17=>open, DOB16=>open, DOB15=>open, DOB14=>open, 
+            DOB13=>open, DOB12=>open, DOB11=>open, DOB10=>open, 
+            DOB9=>open, DOB8=>mdout1_0_8, DOB7=>mdout1_0_7, 
+            DOB6=>mdout1_0_6, DOB5=>mdout1_0_5, DOB4=>mdout1_0_4, 
+            DOB3=>mdout1_0_3, DOB2=>mdout1_0_2, DOB1=>mdout1_0_1, 
+            DOB0=>mdout1_0_0);
+
+    pdp_ram_0_1_14: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), 
+            DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), 
+            DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, CSA1=>wptr_12, 
+            CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, 
+            ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, 
+            ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, 
+            ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>rptr_12, 
+            CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, DOA16=>open, 
+            DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, 
+            DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, 
+            DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, 
+            DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, 
+            DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, 
+            DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_0_17, 
+            DOB7=>mdout1_0_16, DOB6=>mdout1_0_15, DOB5=>mdout1_0_14, 
+            DOB4=>mdout1_0_13, DOB3=>mdout1_0_12, DOB2=>mdout1_0_11, 
+            DOB1=>mdout1_0_10, DOB0=>mdout1_0_9);
+
+    pdp_ram_0_2_13: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), 
+            DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), 
+            DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, CSA1=>wptr_12, 
+            CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, 
+            ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, 
+            ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, 
+            ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>rptr_12, 
+            CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, DOA16=>open, 
+            DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, 
+            DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, 
+            DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, 
+            DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, 
+            DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, 
+            DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_0_26, 
+            DOB7=>mdout1_0_25, DOB6=>mdout1_0_24, DOB5=>mdout1_0_23, 
+            DOB4=>mdout1_0_22, DOB3=>mdout1_0_21, DOB2=>mdout1_0_20, 
+            DOB1=>mdout1_0_19, DOB0=>mdout1_0_18);
+
+    pdp_ram_0_3_12: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), 
+            DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), 
+            DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, CSA1=>wptr_12, 
+            CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, 
+            ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, 
+            ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, 
+            ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>rptr_12, 
+            CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, DOA16=>open, 
+            DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, 
+            DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, 
+            DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, 
+            DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, 
+            DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, 
+            DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_0_35, 
+            DOB7=>mdout1_0_34, DOB6=>mdout1_0_33, DOB5=>mdout1_0_32, 
+            DOB4=>mdout1_0_31, DOB3=>mdout1_0_30, DOB2=>mdout1_0_29, 
+            DOB1=>mdout1_0_28, DOB0=>mdout1_0_27);
+
+    pdp_ram_1_0_11: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), 
+            DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), 
+            DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, 
+            ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, 
+            ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, 
+            ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, 
+            CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, 
+            CSA2=>scuba_vlo, CSA1=>wptr_12, CSA0=>wptr_11, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>rptr_12, CSB0=>rptr_11, RSTB=>Reset, 
+            DOA17=>open, DOA16=>open, DOA15=>open, DOA14=>open, 
+            DOA13=>open, DOA12=>open, DOA11=>open, DOA10=>open, 
+            DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open, 
+            DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open, 
+            DOB17=>open, DOB16=>open, DOB15=>open, DOB14=>open, 
+            DOB13=>open, DOB12=>open, DOB11=>open, DOB10=>open, 
+            DOB9=>open, DOB8=>mdout1_1_8, DOB7=>mdout1_1_7, 
+            DOB6=>mdout1_1_6, DOB5=>mdout1_1_5, DOB4=>mdout1_1_4, 
+            DOB3=>mdout1_1_3, DOB2=>mdout1_1_2, DOB1=>mdout1_1_1, 
+            DOB0=>mdout1_1_0);
+
+    pdp_ram_1_1_10: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), 
+            DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), 
+            DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, CSA1=>wptr_12, 
+            CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, 
+            ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, 
+            ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, 
+            ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>rptr_12, 
+            CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, DOA16=>open, 
+            DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, 
+            DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, 
+            DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, 
+            DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, 
+            DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, 
+            DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_1_17, 
+            DOB7=>mdout1_1_16, DOB6=>mdout1_1_15, DOB5=>mdout1_1_14, 
+            DOB4=>mdout1_1_13, DOB3=>mdout1_1_12, DOB2=>mdout1_1_11, 
+            DOB1=>mdout1_1_10, DOB0=>mdout1_1_9);
+
+    pdp_ram_1_2_9: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), 
+            DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), 
+            DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, CSA1=>wptr_12, 
+            CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, 
+            ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, 
+            ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, 
+            ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>rptr_12, 
+            CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, DOA16=>open, 
+            DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, 
+            DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, 
+            DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, 
+            DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, 
+            DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, 
+            DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_1_26, 
+            DOB7=>mdout1_1_25, DOB6=>mdout1_1_24, DOB5=>mdout1_1_23, 
+            DOB4=>mdout1_1_22, DOB3=>mdout1_1_21, DOB2=>mdout1_1_20, 
+            DOB1=>mdout1_1_19, DOB0=>mdout1_1_18);
+
+    pdp_ram_1_3_8: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), 
+            DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), 
+            DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, CSA1=>wptr_12, 
+            CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, 
+            ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, 
+            ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, 
+            ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>rptr_12, 
+            CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, DOA16=>open, 
+            DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, 
+            DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, 
+            DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, 
+            DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, 
+            DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, 
+            DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_1_35, 
+            DOB7=>mdout1_1_34, DOB6=>mdout1_1_33, DOB5=>mdout1_1_32, 
+            DOB4=>mdout1_1_31, DOB3=>mdout1_1_30, DOB2=>mdout1_1_29, 
+            DOB1=>mdout1_1_28, DOB0=>mdout1_1_27);
+
+    pdp_ram_2_0_7: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), 
+            DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), 
+            DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, 
+            ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, 
+            ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, 
+            ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, 
+            CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, 
+            CSA2=>scuba_vlo, CSA1=>wptr_12, CSA0=>wptr_11, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>rptr_12, CSB0=>rptr_11, RSTB=>Reset, 
+            DOA17=>open, DOA16=>open, DOA15=>open, DOA14=>open, 
+            DOA13=>open, DOA12=>open, DOA11=>open, DOA10=>open, 
+            DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open, 
+            DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open, 
+            DOB17=>open, DOB16=>open, DOB15=>open, DOB14=>open, 
+            DOB13=>open, DOB12=>open, DOB11=>open, DOB10=>open, 
+            DOB9=>open, DOB8=>mdout1_2_8, DOB7=>mdout1_2_7, 
+            DOB6=>mdout1_2_6, DOB5=>mdout1_2_5, DOB4=>mdout1_2_4, 
+            DOB3=>mdout1_2_3, DOB2=>mdout1_2_2, DOB1=>mdout1_2_1, 
+            DOB0=>mdout1_2_0);
+
+    pdp_ram_2_1_6: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), 
+            DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), 
+            DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, CSA1=>wptr_12, 
+            CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, 
+            ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, 
+            ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, 
+            ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>rptr_12, 
+            CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, DOA16=>open, 
+            DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, 
+            DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, 
+            DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, 
+            DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, 
+            DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, 
+            DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_2_17, 
+            DOB7=>mdout1_2_16, DOB6=>mdout1_2_15, DOB5=>mdout1_2_14, 
+            DOB4=>mdout1_2_13, DOB3=>mdout1_2_12, DOB2=>mdout1_2_11, 
+            DOB1=>mdout1_2_10, DOB0=>mdout1_2_9);
+
+    pdp_ram_2_2_5: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), 
+            DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), 
+            DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, CSA1=>wptr_12, 
+            CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, 
+            ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, 
+            ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, 
+            ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>rptr_12, 
+            CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, DOA16=>open, 
+            DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, 
+            DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, 
+            DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, 
+            DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, 
+            DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, 
+            DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_2_26, 
+            DOB7=>mdout1_2_25, DOB6=>mdout1_2_24, DOB5=>mdout1_2_23, 
+            DOB4=>mdout1_2_22, DOB3=>mdout1_2_21, DOB2=>mdout1_2_20, 
+            DOB1=>mdout1_2_19, DOB0=>mdout1_2_18);
+
+    pdp_ram_2_3_4: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), 
+            DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), 
+            DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, CSA1=>wptr_12, 
+            CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, 
+            ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, 
+            ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, 
+            ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>rptr_12, 
+            CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, DOA16=>open, 
+            DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, 
+            DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, 
+            DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, 
+            DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, 
+            DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, 
+            DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_2_35, 
+            DOB7=>mdout1_2_34, DOB6=>mdout1_2_33, DOB5=>mdout1_2_32, 
+            DOB4=>mdout1_2_31, DOB3=>mdout1_2_30, DOB2=>mdout1_2_29, 
+            DOB1=>mdout1_2_28, DOB0=>mdout1_2_27);
+
+    pdp_ram_3_0_3: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), 
+            DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), 
+            DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, 
+            ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, 
+            ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, 
+            ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, 
+            CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, 
+            CSA2=>scuba_vlo, CSA1=>wptr_12, CSA0=>wptr_11, RSTA=>Reset, 
+            DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, 
+            ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, 
+            ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, 
+            ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, 
+            OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, 
+            CSB2=>scuba_vlo, CSB1=>rptr_12, CSB0=>rptr_11, RSTB=>Reset, 
+            DOA17=>open, DOA16=>open, DOA15=>open, DOA14=>open, 
+            DOA13=>open, DOA12=>open, DOA11=>open, DOA10=>open, 
+            DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open, 
+            DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open, 
+            DOB17=>open, DOB16=>open, DOB15=>open, DOB14=>open, 
+            DOB13=>open, DOB12=>open, DOB11=>open, DOB10=>open, 
+            DOB9=>open, DOB8=>mdout1_3_8, DOB7=>mdout1_3_7, 
+            DOB6=>mdout1_3_6, DOB5=>mdout1_3_5, DOB4=>mdout1_3_4, 
+            DOB3=>mdout1_3_3, DOB2=>mdout1_3_2, DOB1=>mdout1_3_1, 
+            DOB0=>mdout1_3_0);
+
+    pdp_ram_3_1_2: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), 
+            DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), 
+            DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, CSA1=>wptr_12, 
+            CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, 
+            ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, 
+            ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, 
+            ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>rptr_12, 
+            CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, DOA16=>open, 
+            DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, 
+            DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, 
+            DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, 
+            DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, 
+            DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, 
+            DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_3_17, 
+            DOB7=>mdout1_3_16, DOB6=>mdout1_3_15, DOB5=>mdout1_3_14, 
+            DOB4=>mdout1_3_13, DOB3=>mdout1_3_12, DOB2=>mdout1_3_11, 
+            DOB1=>mdout1_3_10, DOB0=>mdout1_3_9);
+
+    pdp_ram_3_2_1: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), 
+            DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), 
+            DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, CSA1=>wptr_12, 
+            CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, 
+            ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, 
+            ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, 
+            ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>rptr_12, 
+            CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, DOA16=>open, 
+            DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, 
+            DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, 
+            DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, 
+            DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, 
+            DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, 
+            DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_3_26, 
+            DOB7=>mdout1_3_25, DOB6=>mdout1_3_24, DOB5=>mdout1_3_23, 
+            DOB4=>mdout1_3_22, DOB3=>mdout1_3_21, DOB2=>mdout1_3_20, 
+            DOB1=>mdout1_3_19, DOB0=>mdout1_3_18);
+
+    pdp_ram_3_3_0: DP16KD
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, 
+            DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), 
+            DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), 
+            DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), 
+            ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, 
+            ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, 
+            ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, 
+            CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, CSA1=>wptr_12, 
+            CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, 
+            ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, 
+            ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, 
+            ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, 
+            WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>rptr_12, 
+            CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, DOA16=>open, 
+            DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, 
+            DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, 
+            DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, 
+            DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, 
+            DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, 
+            DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_3_35, 
+            DOB7=>mdout1_3_34, DOB6=>mdout1_3_33, DOB5=>mdout1_3_32, 
+            DOB4=>mdout1_3_31, DOB3=>mdout1_3_30, DOB2=>mdout1_3_29, 
+            DOB1=>mdout1_3_28, DOB0=>mdout1_3_27);
+
+    FF_90: FD1P3DX
+        port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_0);
+
+    FF_89: FD1P3DX
+        port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_1);
+
+    FF_88: FD1P3DX
+        port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_2);
+
+    FF_87: FD1P3DX
+        port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_3);
+
+    FF_86: FD1P3DX
+        port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_4);
+
+    FF_85: FD1P3DX
+        port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_5);
+
+    FF_84: FD1P3DX
+        port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_6);
+
+    FF_83: FD1P3DX
+        port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_7);
+
+    FF_82: FD1P3DX
+        port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_8);
+
+    FF_81: FD1P3DX
+        port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_9);
+
+    FF_80: FD1P3DX
+        port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_10);
+
+    FF_79: FD1P3DX
+        port map (D=>ifcount_11, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_11);
+
+    FF_78: FD1P3DX
+        port map (D=>ifcount_12, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_12);
+
+    FF_77: FD1P3DX
+        port map (D=>ifcount_13, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_13);
+
+    FF_76: FD1S3BX
+        port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
+
+    FF_75: FD1S3DX
+        port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
+
+    FF_74: FD1P3BX
+        port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset, 
+            Q=>wcount_0);
+
+    FF_73: FD1P3DX
+        port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_1);
+
+    FF_72: FD1P3DX
+        port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_2);
+
+    FF_71: FD1P3DX
+        port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_3);
+
+    FF_70: FD1P3DX
+        port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_4);
+
+    FF_69: FD1P3DX
+        port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_5);
+
+    FF_68: FD1P3DX
+        port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_6);
+
+    FF_67: FD1P3DX
+        port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_7);
+
+    FF_66: FD1P3DX
+        port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_8);
+
+    FF_65: FD1P3DX
+        port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_9);
+
+    FF_64: FD1P3DX
+        port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_10);
+
+    FF_63: FD1P3DX
+        port map (D=>iwcount_11, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_11);
+
+    FF_62: FD1P3DX
+        port map (D=>iwcount_12, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_12);
+
+    FF_61: FD1P3DX
+        port map (D=>iwcount_13, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_13);
+
+    FF_60: FD1P3BX
+        port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset, 
+            Q=>rcount_0);
+
+    FF_59: FD1P3DX
+        port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_1);
+
+    FF_58: FD1P3DX
+        port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_2);
+
+    FF_57: FD1P3DX
+        port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_3);
+
+    FF_56: FD1P3DX
+        port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_4);
+
+    FF_55: FD1P3DX
+        port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_5);
+
+    FF_54: FD1P3DX
+        port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_6);
+
+    FF_53: FD1P3DX
+        port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_7);
+
+    FF_52: FD1P3DX
+        port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_8);
+
+    FF_51: FD1P3DX
+        port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_9);
+
+    FF_50: FD1P3DX
+        port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_10);
+
+    FF_49: FD1P3DX
+        port map (D=>ircount_11, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_11);
+
+    FF_48: FD1P3DX
+        port map (D=>ircount_12, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_12);
+
+    FF_47: FD1P3DX
+        port map (D=>ircount_13, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_13);
+
+    FF_46: FD1P3DX
+        port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_0);
+
+    FF_45: FD1P3DX
+        port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_1);
+
+    FF_44: FD1P3DX
+        port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_2);
+
+    FF_43: FD1P3DX
+        port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_3);
+
+    FF_42: FD1P3DX
+        port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_4);
+
+    FF_41: FD1P3DX
+        port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_5);
+
+    FF_40: FD1P3DX
+        port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_6);
+
+    FF_39: FD1P3DX
+        port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_7);
+
+    FF_38: FD1P3DX
+        port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_8);
+
+    FF_37: FD1P3DX
+        port map (D=>wcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_9);
+
+    FF_36: FD1P3DX
+        port map (D=>wcount_10, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_10);
+
+    FF_35: FD1P3DX
+        port map (D=>wcount_11, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_11);
+
+    FF_34: FD1P3DX
+        port map (D=>wcount_12, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_12);
+
+    FF_33: FD1P3DX
+        port map (D=>wcount_13, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wptr_13);
+
+    FF_32: FD1P3DX
+        port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_0);
+
+    FF_31: FD1P3DX
+        port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_1);
+
+    FF_30: FD1P3DX
+        port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_2);
+
+    FF_29: FD1P3DX
+        port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_3);
+
+    FF_28: FD1P3DX
+        port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_4);
+
+    FF_27: FD1P3DX
+        port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_5);
+
+    FF_26: FD1P3DX
+        port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_6);
+
+    FF_25: FD1P3DX
+        port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_7);
+
+    FF_24: FD1P3DX
+        port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_8);
+
+    FF_23: FD1P3DX
+        port map (D=>rcount_9, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_9);
+
+    FF_22: FD1P3DX
+        port map (D=>rcount_10, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_10);
+
+    FF_21: FD1P3DX
+        port map (D=>rcount_11, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_11);
+
+    FF_20: FD1P3DX
+        port map (D=>rcount_12, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_12);
+
+    FF_19: FD1P3DX
+        port map (D=>rcount_13, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rptr_13);
+
+    FF_18: FD1P3DX
+        port map (D=>rptr_11, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, 
+            Q=>rptr_11_ff);
+
+    FF_17: FD1P3DX
+        port map (D=>rptr_12, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, 
+            Q=>rptr_12_ff);
+
+    FF_16: FD1P3DX
+        port map (D=>rptr_11_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, 
+            Q=>rptr_11_ff2);
+
+    FF_15: FD1P3DX
+        port map (D=>rptr_12_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, 
+            Q=>rptr_12_ff2);
+
+    FF_14: FD1S3DX
+        port map (D=>wcnt_sub_0, CK=>Clock, CD=>Reset, Q=>wcnt_reg_0);
+
+    FF_13: FD1S3DX
+        port map (D=>wcnt_sub_1, CK=>Clock, CD=>Reset, Q=>wcnt_reg_1);
+
+    FF_12: FD1S3DX
+        port map (D=>wcnt_sub_2, CK=>Clock, CD=>Reset, Q=>wcnt_reg_2);
+
+    FF_11: FD1S3DX
+        port map (D=>wcnt_sub_3, CK=>Clock, CD=>Reset, Q=>wcnt_reg_3);
+
+    FF_10: FD1S3DX
+        port map (D=>wcnt_sub_4, CK=>Clock, CD=>Reset, Q=>wcnt_reg_4);
+
+    FF_9: FD1S3DX
+        port map (D=>wcnt_sub_5, CK=>Clock, CD=>Reset, Q=>wcnt_reg_5);
+
+    FF_8: FD1S3DX
+        port map (D=>wcnt_sub_6, CK=>Clock, CD=>Reset, Q=>wcnt_reg_6);
+
+    FF_7: FD1S3DX
+        port map (D=>wcnt_sub_7, CK=>Clock, CD=>Reset, Q=>wcnt_reg_7);
+
+    FF_6: FD1S3DX
+        port map (D=>wcnt_sub_8, CK=>Clock, CD=>Reset, Q=>wcnt_reg_8);
+
+    FF_5: FD1S3DX
+        port map (D=>wcnt_sub_9, CK=>Clock, CD=>Reset, Q=>wcnt_reg_9);
+
+    FF_4: FD1S3DX
+        port map (D=>wcnt_sub_10, CK=>Clock, CD=>Reset, Q=>wcnt_reg_10);
+
+    FF_3: FD1S3DX
+        port map (D=>wcnt_sub_11, CK=>Clock, CD=>Reset, Q=>wcnt_reg_11);
+
+    FF_2: FD1S3DX
+        port map (D=>wcnt_sub_12, CK=>Clock, CD=>Reset, Q=>wcnt_reg_12);
+
+    FF_1: FD1S3DX
+        port map (D=>wcnt_sub_13, CK=>Clock, CD=>Reset, Q=>wcnt_reg_13);
+
+    FF_0: FD1S3DX
+        port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull);
+
+    bdcnt_bctr_cia: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>'X', S0=>open, S1=>open, COUT=>bdcnt_bctr_ci);
+
+    bdcnt_bctr_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_0, A1=>fcount_1, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>bdcnt_bctr_ci, S0=>ifcount_0, S1=>ifcount_1, COUT=>co0);
+
+    bdcnt_bctr_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co0, S0=>ifcount_2, S1=>ifcount_3, COUT=>co1);
+
+    bdcnt_bctr_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_4, A1=>fcount_5, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co1, S0=>ifcount_4, S1=>ifcount_5, COUT=>co2);
+
+    bdcnt_bctr_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_6, A1=>fcount_7, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co2, S0=>ifcount_6, S1=>ifcount_7, COUT=>co3);
+
+    bdcnt_bctr_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_8, A1=>fcount_9, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co3, S0=>ifcount_8, S1=>ifcount_9, COUT=>co4);
+
+    bdcnt_bctr_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_10, A1=>fcount_11, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co4, S0=>ifcount_10, S1=>ifcount_11, COUT=>co5);
+
+    bdcnt_bctr_6: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_12, A1=>fcount_13, B0=>cnt_con, B1=>cnt_con, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co5, S0=>ifcount_12, S1=>ifcount_13, COUT=>co6);
+
+    e_cmp_ci_a: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci);
+
+    e_cmp_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>rden_i, A1=>scuba_vlo, B0=>fcount_0, B1=>fcount_1, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>cmp_ci, S0=>open, S1=>open, COUT=>co0_1);
+
+    e_cmp_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_2, 
+            B1=>fcount_3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co0_1, S0=>open, S1=>open, COUT=>co1_1);
+
+    e_cmp_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_4, 
+            B1=>fcount_5, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co1_1, S0=>open, S1=>open, COUT=>co2_1);
+
+    e_cmp_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_6, 
+            B1=>fcount_7, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co2_1, S0=>open, S1=>open, COUT=>co3_1);
+
+    e_cmp_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_8, 
+            B1=>fcount_9, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co3_1, S0=>open, S1=>open, COUT=>co4_1);
+
+    e_cmp_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_10, 
+            B1=>fcount_11, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co4_1, S0=>open, S1=>open, COUT=>co5_1);
+
+    e_cmp_6: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_12, 
+            B1=>fcount_13, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co5_1, S0=>open, S1=>open, 
+            COUT=>cmp_le_1_c);
+
+    a0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>cmp_le_1_c, S0=>cmp_le_1, S1=>open, 
+            COUT=>open);
+
+    g_cmp_ci_a: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_1);
+
+    g_cmp_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>cmp_ci_1, S0=>open, S1=>open, COUT=>co0_2);
+
+    g_cmp_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co0_2, S0=>open, S1=>open, COUT=>co1_2);
+
+    g_cmp_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co1_2, S0=>open, S1=>open, COUT=>co2_2);
+
+    g_cmp_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co2_2, S0=>open, S1=>open, COUT=>co3_2);
+
+    g_cmp_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co3_2, S0=>open, S1=>open, COUT=>co4_2);
+
+    g_cmp_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_10, A1=>fcount_11, B0=>wren_i, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co4_2, S0=>open, S1=>open, COUT=>co5_2);
+
+    g_cmp_6: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>fcount_12, A1=>fcount_13, B0=>wren_i, 
+            B1=>wren_i_inv, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co5_2, S0=>open, S1=>open, 
+            COUT=>cmp_ge_d1_c);
+
+    a1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>cmp_ge_d1_c, S0=>cmp_ge_d1, S1=>open, 
+            COUT=>open);
+
+    w_ctr_cia: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>w_ctr_ci);
+
+    w_ctr_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>w_ctr_ci, S0=>iwcount_0, S1=>iwcount_1, 
+            COUT=>co0_3);
+
+    w_ctr_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_2, A1=>wcount_3, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co0_3, S0=>iwcount_2, S1=>iwcount_3, 
+            COUT=>co1_3);
+
+    w_ctr_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_4, A1=>wcount_5, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co1_3, S0=>iwcount_4, S1=>iwcount_5, 
+            COUT=>co2_3);
+
+    w_ctr_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_6, A1=>wcount_7, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co2_3, S0=>iwcount_6, S1=>iwcount_7, 
+            COUT=>co3_3);
+
+    w_ctr_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_8, A1=>wcount_9, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co3_3, S0=>iwcount_8, S1=>iwcount_9, 
+            COUT=>co4_3);
+
+    w_ctr_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_10, A1=>wcount_11, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co4_3, S0=>iwcount_10, S1=>iwcount_11, 
+            COUT=>co5_3);
+
+    w_ctr_6: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>wcount_12, A1=>wcount_13, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co5_3, S0=>iwcount_12, S1=>iwcount_13, 
+            COUT=>co6_1);
+
+    r_ctr_cia: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>r_ctr_ci);
+
+    r_ctr_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>r_ctr_ci, S0=>ircount_0, S1=>ircount_1, 
+            COUT=>co0_4);
+
+    r_ctr_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_2, A1=>rcount_3, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co0_4, S0=>ircount_2, S1=>ircount_3, 
+            COUT=>co1_4);
+
+    r_ctr_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_4, A1=>rcount_5, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co1_4, S0=>ircount_4, S1=>ircount_5, 
+            COUT=>co2_4);
+
+    r_ctr_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_6, A1=>rcount_7, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co2_4, S0=>ircount_6, S1=>ircount_7, 
+            COUT=>co3_4);
+
+    r_ctr_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_8, A1=>rcount_9, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co3_4, S0=>ircount_8, S1=>ircount_9, 
+            COUT=>co4_4);
+
+    r_ctr_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_10, A1=>rcount_11, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co4_4, S0=>ircount_10, S1=>ircount_11, 
+            COUT=>co5_4);
+
+    r_ctr_6: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>rcount_12, A1=>rcount_13, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co5_4, S0=>ircount_12, S1=>ircount_13, 
+            COUT=>co6_2);
+
+    mux_35: MUX41
+        port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0, 
+            D3=>mdout1_3_0, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(0));
+
+    mux_34: MUX41
+        port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1, 
+            D3=>mdout1_3_1, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(1));
+
+    mux_33: MUX41
+        port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2, 
+            D3=>mdout1_3_2, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(2));
+
+    mux_32: MUX41
+        port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3, 
+            D3=>mdout1_3_3, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(3));
+
+    mux_31: MUX41
+        port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4, 
+            D3=>mdout1_3_4, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(4));
+
+    mux_30: MUX41
+        port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5, 
+            D3=>mdout1_3_5, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(5));
+
+    mux_29: MUX41
+        port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6, 
+            D3=>mdout1_3_6, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(6));
+
+    mux_28: MUX41
+        port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7, 
+            D3=>mdout1_3_7, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(7));
+
+    mux_27: MUX41
+        port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8, 
+            D3=>mdout1_3_8, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(8));
+
+    mux_26: MUX41
+        port map (D0=>mdout1_0_9, D1=>mdout1_1_9, D2=>mdout1_2_9, 
+            D3=>mdout1_3_9, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(9));
+
+    mux_25: MUX41
+        port map (D0=>mdout1_0_10, D1=>mdout1_1_10, D2=>mdout1_2_10, 
+            D3=>mdout1_3_10, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            Z=>Q(10));
+
+    mux_24: MUX41
+        port map (D0=>mdout1_0_11, D1=>mdout1_1_11, D2=>mdout1_2_11, 
+            D3=>mdout1_3_11, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            Z=>Q(11));
+
+    mux_23: MUX41
+        port map (D0=>mdout1_0_12, D1=>mdout1_1_12, D2=>mdout1_2_12, 
+            D3=>mdout1_3_12, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            Z=>Q(12));
+
+    mux_22: MUX41
+        port map (D0=>mdout1_0_13, D1=>mdout1_1_13, D2=>mdout1_2_13, 
+            D3=>mdout1_3_13, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            Z=>Q(13));
+
+    mux_21: MUX41
+        port map (D0=>mdout1_0_14, D1=>mdout1_1_14, D2=>mdout1_2_14, 
+            D3=>mdout1_3_14, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            Z=>Q(14));
+
+    mux_20: MUX41
+        port map (D0=>mdout1_0_15, D1=>mdout1_1_15, D2=>mdout1_2_15, 
+            D3=>mdout1_3_15, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            Z=>Q(15));
+
+    mux_19: MUX41
+        port map (D0=>mdout1_0_16, D1=>mdout1_1_16, D2=>mdout1_2_16, 
+            D3=>mdout1_3_16, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            Z=>Q(16));
+
+    mux_18: MUX41
+        port map (D0=>mdout1_0_17, D1=>mdout1_1_17, D2=>mdout1_2_17, 
+            D3=>mdout1_3_17, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            Z=>Q(17));
+
+    mux_17: MUX41
+        port map (D0=>mdout1_0_18, D1=>mdout1_1_18, D2=>mdout1_2_18, 
+            D3=>mdout1_3_18, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            Z=>Q(18));
+
+    mux_16: MUX41
+        port map (D0=>mdout1_0_19, D1=>mdout1_1_19, D2=>mdout1_2_19, 
+            D3=>mdout1_3_19, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            Z=>Q(19));
+
+    mux_15: MUX41
+        port map (D0=>mdout1_0_20, D1=>mdout1_1_20, D2=>mdout1_2_20, 
+            D3=>mdout1_3_20, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            Z=>Q(20));
+
+    mux_14: MUX41
+        port map (D0=>mdout1_0_21, D1=>mdout1_1_21, D2=>mdout1_2_21, 
+            D3=>mdout1_3_21, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            Z=>Q(21));
+
+    mux_13: MUX41
+        port map (D0=>mdout1_0_22, D1=>mdout1_1_22, D2=>mdout1_2_22, 
+            D3=>mdout1_3_22, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            Z=>Q(22));
+
+    mux_12: MUX41
+        port map (D0=>mdout1_0_23, D1=>mdout1_1_23, D2=>mdout1_2_23, 
+            D3=>mdout1_3_23, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            Z=>Q(23));
+
+    mux_11: MUX41
+        port map (D0=>mdout1_0_24, D1=>mdout1_1_24, D2=>mdout1_2_24, 
+            D3=>mdout1_3_24, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            Z=>Q(24));
+
+    mux_10: MUX41
+        port map (D0=>mdout1_0_25, D1=>mdout1_1_25, D2=>mdout1_2_25, 
+            D3=>mdout1_3_25, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            Z=>Q(25));
+
+    mux_9: MUX41
+        port map (D0=>mdout1_0_26, D1=>mdout1_1_26, D2=>mdout1_2_26, 
+            D3=>mdout1_3_26, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            Z=>Q(26));
+
+    mux_8: MUX41
+        port map (D0=>mdout1_0_27, D1=>mdout1_1_27, D2=>mdout1_2_27, 
+            D3=>mdout1_3_27, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            Z=>Q(27));
+
+    mux_7: MUX41
+        port map (D0=>mdout1_0_28, D1=>mdout1_1_28, D2=>mdout1_2_28, 
+            D3=>mdout1_3_28, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            Z=>Q(28));
+
+    mux_6: MUX41
+        port map (D0=>mdout1_0_29, D1=>mdout1_1_29, D2=>mdout1_2_29, 
+            D3=>mdout1_3_29, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            Z=>Q(29));
+
+    mux_5: MUX41
+        port map (D0=>mdout1_0_30, D1=>mdout1_1_30, D2=>mdout1_2_30, 
+            D3=>mdout1_3_30, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            Z=>Q(30));
+
+    mux_4: MUX41
+        port map (D0=>mdout1_0_31, D1=>mdout1_1_31, D2=>mdout1_2_31, 
+            D3=>mdout1_3_31, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            Z=>Q(31));
+
+    mux_3: MUX41
+        port map (D0=>mdout1_0_32, D1=>mdout1_1_32, D2=>mdout1_2_32, 
+            D3=>mdout1_3_32, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            Z=>Q(32));
+
+    mux_2: MUX41
+        port map (D0=>mdout1_0_33, D1=>mdout1_1_33, D2=>mdout1_2_33, 
+            D3=>mdout1_3_33, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            Z=>Q(33));
+
+    mux_1: MUX41
+        port map (D0=>mdout1_0_34, D1=>mdout1_1_34, D2=>mdout1_2_34, 
+            D3=>mdout1_3_34, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            Z=>Q(34));
+
+    mux_0: MUX41
+        port map (D0=>mdout1_0_35, D1=>mdout1_1_35, D2=>mdout1_2_35, 
+            D3=>mdout1_3_35, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, 
+            Z=>Q(35));
+
+    precin_inst474: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"0000", 
+        INIT0=> X"0000")
+        port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, 
+            B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>precin);
+
+    wcnt_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>cnt_con, A1=>wcount_0, B0=>cnt_con_inv, B1=>rptr_0, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>precin, S0=>open, S1=>wcnt_sub_0, COUT=>co0_5);
+
+    wcnt_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_1, A1=>wcount_2, B0=>rptr_1, B1=>rptr_2, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co0_5, S0=>wcnt_sub_1, S1=>wcnt_sub_2, COUT=>co1_5);
+
+    wcnt_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_3, A1=>wcount_4, B0=>rptr_3, B1=>rptr_4, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co1_5, S0=>wcnt_sub_3, S1=>wcnt_sub_4, COUT=>co2_5);
+
+    wcnt_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_5, A1=>wcount_6, B0=>rptr_5, B1=>rptr_6, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co2_5, S0=>wcnt_sub_5, S1=>wcnt_sub_6, COUT=>co3_5);
+
+    wcnt_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_7, A1=>wcount_8, B0=>rptr_7, B1=>rptr_8, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co3_5, S0=>wcnt_sub_7, S1=>wcnt_sub_8, COUT=>co4_5);
+
+    wcnt_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_9, A1=>wcount_10, B0=>rptr_9, B1=>rptr_10, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co4_5, S0=>wcnt_sub_9, S1=>wcnt_sub_10, COUT=>co5_5);
+
+    wcnt_6: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcount_11, A1=>wcount_12, B0=>rptr_11, B1=>rptr_12, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>co5_5, S0=>wcnt_sub_11, S1=>wcnt_sub_12, COUT=>co6_3);
+
+    wcnt_7: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co6_3, S0=>wcnt_sub_13, S1=>open, 
+            COUT=>open);
+
+    af_set_cmp_ci_a: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, 
+            C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, 
+            CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_2);
+
+    af_set_cmp_0: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0), 
+            B1=>AmFullThresh(1), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>cmp_ci_2, S0=>open, 
+            S1=>open, COUT=>co0_6);
+
+    af_set_cmp_1: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2), 
+            B1=>AmFullThresh(3), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co0_6, S0=>open, S1=>open, 
+            COUT=>co1_6);
+
+    af_set_cmp_2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4), 
+            B1=>AmFullThresh(5), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co1_6, S0=>open, S1=>open, 
+            COUT=>co2_6);
+
+    af_set_cmp_3: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6), 
+            B1=>AmFullThresh(7), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co2_6, S0=>open, S1=>open, 
+            COUT=>co3_6);
+
+    af_set_cmp_4: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8), 
+            B1=>AmFullThresh(9), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co3_6, S0=>open, S1=>open, 
+            COUT=>co4_6);
+
+    af_set_cmp_5: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_10, A1=>wcnt_reg_11, B0=>AmFullThresh(10), 
+            B1=>AmFullThresh(11), C0=>scuba_vhi, C1=>scuba_vhi, 
+            D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co4_6, S0=>open, S1=>open, 
+            COUT=>co5_6);
+
+    af_set_cmp_6: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", 
+        INIT0=> X"99AA")
+        port map (A0=>wcnt_reg_12, A1=>wcnt_reg_13, B0=>AmFullThresh(12), 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>co5_6, S0=>open, S1=>open, 
+            COUT=>af_set_c);
+
+    scuba_vhi_inst: VHI
+        port map (Z=>scuba_vhi);
+
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    a2: CCU2C
+        generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", 
+        INIT0=> X"66AA")
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, 
+            D1=>scuba_vhi, CIN=>af_set_c, S0=>af_set, S1=>open, 
+            COUT=>open);
+
+    WCNT(0) <= fcount_0;
+    WCNT(1) <= fcount_1;
+    WCNT(2) <= fcount_2;
+    WCNT(3) <= fcount_3;
+    WCNT(4) <= fcount_4;
+    WCNT(5) <= fcount_5;
+    WCNT(6) <= fcount_6;
+    WCNT(7) <= fcount_7;
+    WCNT(8) <= fcount_8;
+    WCNT(9) <= fcount_9;
+    WCNT(10) <= fcount_10;
+    WCNT(11) <= fcount_11;
+    WCNT(12) <= fcount_12;
+    WCNT(13) <= fcount_13;
+    Empty <= empty_i;
+    Full <= full_i;
+end Structure;

diff --git a/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg_ngd.asd b/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg_ngd.asd
new file mode 100644 (file)
index 0000000..c265c78
--- /dev/null
+++ b/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg_ngd.asd
@@ -0,0 +1 @@
+[ActiveSupport NGD]

diff --git a/lattice/ecp5/PLL/PLL.sbx b/lattice/ecp5/PLL/PLL.sbx
new file mode 100644 (file)
index 0000000..5cdb2e4
--- /dev/null
+++ b/lattice/ecp5/PLL/PLL.sbx
@@ -0,0 +1,661 @@
+<!DOCTYPE PLL>
+<lattice:project>
+    <spirit:component>
+        <spirit:vendor>LATTICE</spirit:vendor>
+        <spirit:library>LOCAL</spirit:library>
+        <spirit:name>PLL</spirit:name>
+        <spirit:version>1.0</spirit:version>
+        <spirit:fileSets>
+            <spirit:fileset>
+                <spirit:name>Diamond_Synthesis</spirit:name>
+                <spirit:group>synthesis</spirit:group>
+            </spirit:fileset>
+            <spirit:fileset>
+                <spirit:name>Diamond_Simulation</spirit:name>
+                <spirit:group>simulation</spirit:group>
+            </spirit:fileset>
+        </spirit:fileSets>
+        <spirit:componentGenerators/>
+        <spirit:model>
+            <spirit:views/>
+            <spirit:ports>
+                <spirit:port>
+                    <spirit:name>pll_in200_out100_CLKI</spirit:name>
+                    <spirit:displayName>pll_in200_out100_CLKI</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">pll_in200_out100.CLKI</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>pll_in200_out100_CLKOP</spirit:name>
+                    <spirit:displayName>pll_in200_out100_CLKOP</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">pll_in200_out100.CLKOP</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>pll_in200_out100_CLKOS</spirit:name>
+                    <spirit:displayName>pll_in200_out100_CLKOS</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">pll_in200_out100.CLKOS</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>pll_in200_out100_LOCK</spirit:name>
+                    <spirit:displayName>pll_in200_out100_LOCK</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">pll_in200_out100.LOCK</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+            </spirit:ports>
+        </spirit:model>
+        <spirit:vendorExtensions>
+            <lattice:device>LFE5UM-85F-8MG285C</lattice:device>
+            <lattice:synthesis>synplify</lattice:synthesis>
+            <lattice:date>2015-03-17.15:29:30</lattice:date>
+            <lattice:modified>2015-03-17.15:44:52</lattice:modified>
+            <lattice:diamond>3.4.0.80</lattice:diamond>
+            <lattice:language>VHDL</lattice:language>
+            <lattice:attributes>
+                <lattice:attribute lattice:name="AddComponent">true</lattice:attribute>
+                <lattice:attribute lattice:name="Change4to5">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeConnect">true</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangePack">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangePart">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute>
+                <lattice:attribute lattice:name="Migrate">false</lattice:attribute>
+                <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute>
+            </lattice:attributes>
+            <lattice:elements/>
+            <lattice:lpc/>
+            <lattice:groups/>
+        </spirit:vendorExtensions>
+    </spirit:component>
+    <spirit:design>
+        <spirit:vendor>LATTICE</spirit:vendor>
+        <spirit:library>LOCAL</spirit:library>
+        <spirit:name>PLL</spirit:name>
+        <spirit:version>1.0</spirit:version>
+        <spirit:componentInstances>
+            <spirit:componentInstance>
+                <spirit:instanceName>pll_in200_out100</spirit:instanceName>
+                <spirit:componentRef>
+                    <spirit:vendor>Lattice Semiconductor Corporation</spirit:vendor>
+                    <spirit:library>LEGACY</spirit:library>
+                    <spirit:name>PLL</spirit:name>
+                    <spirit:version>5.7</spirit:version>
+                    <spirit:fileSets>
+                        <spirit:fileset>
+                            <spirit:name>Diamond_Simulation</spirit:name>
+                            <spirit:group>simulation</spirit:group>
+                            <spirit:file>
+                                <spirit:name>./pll_in200_out100/pll_in200_out100.vhd</spirit:name>
+                                <spirit:fileType>vhdlSource</spirit:fileType>
+                            </spirit:file>
+                        </spirit:fileset>
+                        <spirit:fileset>
+                            <spirit:name>Diamond_Synthesis</spirit:name>
+                            <spirit:group>synthesis</spirit:group>
+                            <spirit:file>
+                                <spirit:name>./pll_in200_out100/pll_in200_out100.vhd</spirit:name>
+                                <spirit:fileType>vhdlSource</spirit:fileType>
+                            </spirit:file>
+                        </spirit:fileset>
+                    </spirit:fileSets>
+                    <spirit:componentGenerators>
+                        <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                            <spirit:name>Configuration</spirit:name>
+                            <spirit:apiType>none</spirit:apiType>
+                            <spirit:generatorExe>${sbp_path}/${instance}/generate_core.tcl</spirit:generatorExe>
+                            <spirit:group>CONFIG</spirit:group>
+                        </spirit:componentGenerator>
+                        <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                            <spirit:name>CreateNGD</spirit:name>
+                            <spirit:apiType>none</spirit:apiType>
+                            <spirit:generatorExe>${sbp_path}/${instance}/generate_ngd.tcl</spirit:generatorExe>
+                            <spirit:group>CONFIG</spirit:group>
+                        </spirit:componentGenerator>
+                        <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                            <spirit:name>Generation</spirit:name>
+                            <spirit:apiType>none</spirit:apiType>
+                            <spirit:generatorExe>${sbp_path}/${instance}/generate_core.tcl</spirit:generatorExe>
+                            <spirit:group>GENERATE</spirit:group>
+                        </spirit:componentGenerator>
+                    </spirit:componentGenerators>
+                    <spirit:model>
+                        <spirit:views/>
+                        <spirit:ports>
+                            <spirit:port>
+                                <spirit:name>CLKI</spirit:name>
+                                <spirit:displayName>CLKI</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                                <spirit:vendorExtensions>
+                                    <lattice:attributes>
+                                        <lattice:attribute lattice:name="PadPin">true</lattice:attribute>
+                                    </lattice:attributes>
+                                </spirit:vendorExtensions>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>CLKOP</spirit:name>
+                                <spirit:displayName>CLKOP</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>CLKOS</spirit:name>
+                                <spirit:displayName>CLKOS</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>LOCK</spirit:name>
+                                <spirit:displayName>LOCK</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                        </spirit:ports>
+                    </spirit:model>
+                    <spirit:vendorExtensions>
+                        <lattice:synthesis>synplify</lattice:synthesis>
+                        <lattice:modified>2015-03-17.15:44:52</lattice:modified>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="AddComponent">false</lattice:attribute>
+                            <lattice:attribute lattice:name="BBox">false</lattice:attribute>
+                            <lattice:attribute lattice:name="Change4to5">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeConnect">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangePack">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangePart">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute>
+                            <lattice:attribute lattice:name="CoreType">LPM</lattice:attribute>
+                            <lattice:attribute lattice:name="DCU_RXREFCLK">PRIMARY</lattice:attribute>
+                            <lattice:attribute lattice:name="DCU_TXREFCLK">PRIMARY</lattice:attribute>
+                            <lattice:attribute lattice:name="Migrate">false</lattice:attribute>
+                            <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute>
+                            <lattice:attribute lattice:name="Resource">IO:2;PLL:1;DLL:0</lattice:attribute>
+                        </lattice:attributes>
+                        <lattice:elements>
+                            <lattice:element>
+                                <lattice:name>CLKI</lattice:name>
+                                <lattice:type>IO</lattice:type>
+                                <lattice:attributes>
+                                    <lattice:attribute lattice:name="Block_Name">Inst1_IB</lattice:attribute>
+                                    <lattice:attribute lattice:name="CLK_SRC">true</lattice:attribute>
+                                    <lattice:attribute lattice:name="ElementDrag">true</lattice:attribute>
+                                    <lattice:attribute lattice:name="ElementHide">false</lattice:attribute>
+                                    <lattice:attribute lattice:name="ElementType">IO</lattice:attribute>
+                                    <lattice:attribute lattice:name="isPort">true</lattice:attribute>
+                                </lattice:attributes>
+                            </lattice:element>
+                            <lattice:element>
+                                <lattice:name>CLKI~</lattice:name>
+                                <lattice:type>IO</lattice:type>
+                                <lattice:attributes>
+                                    <lattice:attribute lattice:name="ElementDrag">true</lattice:attribute>
+                                    <lattice:attribute lattice:name="ElementHide">false</lattice:attribute>
+                                    <lattice:attribute lattice:name="ElementType">IO</lattice:attribute>
+                                    <lattice:attribute lattice:name="ngd">true</lattice:attribute>
+                                </lattice:attributes>
+                            </lattice:element>
+                            <lattice:element>
+                                <lattice:name>pll_in200_out100</lattice:name>
+                                <lattice:type>GXPLL</lattice:type>
+                                <lattice:attributes>
+                                    <lattice:attribute lattice:name="ElementDrag">true</lattice:attribute>
+                                    <lattice:attribute lattice:name="ElementHide">false</lattice:attribute>
+                                    <lattice:attribute lattice:name="ElementType">GXPLL</lattice:attribute>
+                                </lattice:attributes>
+                            </lattice:element>
+                        </lattice:elements>
+                        <lattice:lpc>
+                            <lattice:lpcsection lattice:name="Device"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Family</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">ecp5um</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>OperatingCondition</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">COM</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Package</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">CSFBGA285</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PartName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F-8MG285C</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PartType</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>SpeedGrade</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Status</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">C</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcsection lattice:name="IP"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">PLL</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreRevision</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">5.7</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreStatus</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Demo</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreType</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">LPM</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Date</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">03/17/2015</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>ModuleName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">pll_in200_out100</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>ParameterFileVersion</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1.0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>SourceFormat</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">VHDL</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Time</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">15:42:59</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>VendorName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Lattice Semiconductor Corporation</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcsection lattice:name="Parameters"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKFB_DIV</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKI_DIV</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">2</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKI_FREQ</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">200</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOP_ACTUAL_FREQ</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">100.000000</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOP_APHASE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0.00</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOP_DIV</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">6</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOP_DPHASE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOP_FREQ</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">100.00</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOP_MUXA</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOP_TOL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0.0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOP_TRIM_DELAY</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOP_TRIM_POL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Rising</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS2_ACTUAL_FREQ</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS2_APHASE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0.00</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS2_DIV</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS2_DPHASE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS2_Enable</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS2_FREQ</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">100.00</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS2_MUXC</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS2_TOL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0.0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS2_TRIM_DELAY</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS2_TRIM_POL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Rising</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS3_ACTUAL_FREQ</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS3_APHASE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0.00</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS3_DIV</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS3_DPHASE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS3_Enable</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS3_FREQ</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">100.00</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS3_MUXD</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS3_TOL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0.0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS3_TRIM_DELAY</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS3_TRIM_POL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Rising</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS_ACTUAL_FREQ</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">200.000000</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS_APHASE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0.00</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS_DIV</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS_DPHASE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS_Enable</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">ENABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS_FREQ</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">100.00</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS_MUXB</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">ENABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS_TOL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0.0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS_TRIM_DELAY</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS_TRIM_POL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Rising</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKSEL_ENA</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>DPHASE_SOURCE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">STATIC</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Destination</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Synplicity</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>EDIF</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>ENABLE_CLKOP</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>ENABLE_CLKOS</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>ENABLE_CLKOS2</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>ENABLE_CLKOS3</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>ENABLE_HBW</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Expression</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">None</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>FEEDBK_PATH</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">CLKOP</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>FRACN_DIV</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>FRACN_ENABLE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>IO</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>IOBUF</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">LVDS</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Order</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">None</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PLLRST_ENA</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PLL_BW</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">8.185</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PLL_LOCK_MODE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">ENABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PLL_LOCK_STK</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PLL_USE_SMI</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>REFERENCE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>STDBY_ENABLE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>VCO_RATE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">600.000</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>VHDL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Verilog</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcsection lattice:name="Command"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>cmd_line</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">-w -n pll_in200_out100 -lang vhdl -synth synplify -arch sa5p00m -type pll -fin 200 -clkibuf LVDS -fclkop 100.00 -fclkop_tol 0.0 -bypass_divs -phase_cntl STATIC -lock -fb_mode 1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                        </lattice:lpc>
+                        <lattice:groups>
+                            <lattice:group>
+                                <lattice:name>GXPLL</lattice:name>
+                                <lattice:category>1</lattice:category>
+                                <lattice:attributes>
+                                    <lattice:attribute lattice:name="GroupDrag">true</lattice:attribute>
+                                    <lattice:attribute lattice:name="GroupHide">true</lattice:attribute>
+                                    <lattice:attribute lattice:name="GroupType">GXPLL</lattice:attribute>
+                                </lattice:attributes>
+                                <lattice:elementref>pll_in200_out100</lattice:elementref>
+                            </lattice:group>
+                            <lattice:group>
+                                <lattice:name>IO</lattice:name>
+                                <lattice:category>1</lattice:category>
+                                <lattice:attributes>
+                                    <lattice:attribute lattice:name="GroupDrag">true</lattice:attribute>
+                                    <lattice:attribute lattice:name="GroupHide">true</lattice:attribute>
+                                    <lattice:attribute lattice:name="GroupType">IO</lattice:attribute>
+                                </lattice:attributes>
+                                <lattice:elementref>CLKI</lattice:elementref>
+                                <lattice:elementref>CLKI~</lattice:elementref>
+                            </lattice:group>
+                            <lattice:group>
+                                <lattice:name>pll</lattice:name>
+                                <lattice:category>0</lattice:category>
+                                <lattice:attributes>
+                                    <lattice:attribute lattice:name="GroupDrag">true</lattice:attribute>
+                                    <lattice:attribute lattice:name="GroupHide">false</lattice:attribute>
+                                    <lattice:attribute lattice:name="GroupType">PLL</lattice:attribute>
+                                </lattice:attributes>
+                                <lattice:elementref>CLKI</lattice:elementref>
+                                <lattice:elementref>CLKI~</lattice:elementref>
+                                <lattice:elementref>pll_in200_out100</lattice:elementref>
+                            </lattice:group>
+                        </lattice:groups>
+                    </spirit:vendorExtensions>
+                </spirit:componentRef>
+            </spirit:componentInstance>
+        </spirit:componentInstances>
+        <spirit:adHocConnections>
+            <spirit:adHocConnection>
+                <spirit:name>pll_in200_out100_CLKI</spirit:name>
+                <spirit:displayName>pll_in200_out100_CLKI</spirit:displayName>
+                <spirit:vendorExtensions>
+                    <lattice:attributes>
+                        <lattice:attribute lattice:name="export">sys_yes</lattice:attribute>
+                    </lattice:attributes>
+                </spirit:vendorExtensions>
+                <spirit:internalPortReference spirit:portRef="CLKI" spirit:componentRef="pll_in200_out100"/>
+                <spirit:externalPortReference spirit:portRef="pll_in200_out100_CLKI"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>pll_in200_out100_CLKOP</spirit:name>
+                <spirit:displayName>pll_in200_out100_CLKOP</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="CLKOP" spirit:componentRef="pll_in200_out100"/>
+                <spirit:externalPortReference spirit:portRef="pll_in200_out100_CLKOP"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>pll_in200_out100_CLKOS</spirit:name>
+                <spirit:displayName>pll_in200_out100_CLKOS</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="CLKOS" spirit:componentRef="pll_in200_out100"/>
+                <spirit:externalPortReference spirit:portRef="pll_in200_out100_CLKOS"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>pll_in200_out100_LOCK</spirit:name>
+                <spirit:displayName>pll_in200_out100_LOCK</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="LOCK" spirit:componentRef="pll_in200_out100"/>
+                <spirit:externalPortReference spirit:portRef="pll_in200_out100_LOCK"/>
+            </spirit:adHocConnection>
+        </spirit:adHocConnections>
+    </spirit:design>
+</lattice:project>

diff --git a/lattice/ecp5/PLL/archv/pll_in200_out100.zip b/lattice/ecp5/PLL/archv/pll_in200_out100.zip
new file mode 100644 (file)
index 0000000..c8b86e5
Binary files /dev/null and b/lattice/ecp5/PLL/archv/pll_in200_out100.zip differ

diff --git a/lattice/ecp5/PLL/pll_in200_out100/licbug.txt b/lattice/ecp5/PLL/pll_in200_out100/licbug.txt
new file mode 100644 (file)
index 0000000..ecb7ba4
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/licbug.txt
@@ -0,0 +1,16 @@
+main called
+main 10
+main 20
+main 30
+main 40
+main 50
+main 60
+main 70
+main 80
+main 90
+main 100
+main 110
+MainAppInit 10
+MainAppInit 20
+MainAppInit 30
+MainAppInit 40

diff --git a/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100.cmd b/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100.cmd
new file mode 100644 (file)
index 0000000..2974efe
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100.cmd
@@ -0,0 +1,18 @@
+PROJECT: pll_in200_out100
+               working_path: "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results"
+               module: pll_in200_out100
+               verilog_file_list: "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd"
+               vlog_std_v2001: true
+               constraint_file_name: "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc"
+               suffix_name: edn
+               output_file_name: pll_in200_out100
+               write_prf: true
+               disable_io_insertion: true
+               force_gsr: false
+               frequency: 100
+               fanout_limit: 50
+               retiming: false
+               pipe: false
+               part: LFE5UM-85F
+               speed_grade: 8
+               

diff --git a/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100.edn b/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100.edn
new file mode 100644 (file)
index 0000000..56b4d1c
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100.edn
@@ -0,0 +1,234 @@
+(edif pll_in200_out100
+  (edifVersion 2 0 0)
+  (edifLevel 0)
+  (keywordMap (keywordLevel 0))
+  (status
+    (written
+      (timestamp 2015 3 17 15 43 11)
+      (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80"))))
+      (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n pll_in200_out100 -lang vhdl -synth synplify -arch sa5p00m -type pll -fin 200 -clkibuf LVDS -fclkop 100.00 -fclkop_tol 0.0 -bypass_divs -phase_cntl STATIC -lock -fb_mode 1 -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc ")
+  (library ORCLIB
+    (edifLevel 0)
+    (technology
+      (numberDefinition))
+    (cell EHXPLLL
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port CLKI
+            (direction INPUT))
+          (port CLKFB
+            (direction INPUT))
+          (port PHASESEL1
+            (direction INPUT))
+          (port PHASESEL0
+            (direction INPUT))
+          (port PHASEDIR
+            (direction INPUT))
+          (port PHASESTEP
+            (direction INPUT))
+          (port PHASELOADREG
+            (direction INPUT))
+          (port STDBY
+            (direction INPUT))
+          (port PLLWAKESYNC
+            (direction INPUT))
+          (port RST
+            (direction INPUT))
+          (port ENCLKOP
+            (direction INPUT))
+          (port ENCLKOS
+            (direction INPUT))
+          (port ENCLKOS2
+            (direction INPUT))
+          (port ENCLKOS3
+            (direction INPUT))
+          (port CLKOP
+            (direction OUTPUT))
+          (port CLKOS
+            (direction OUTPUT))
+          (port CLKOS2
+            (direction OUTPUT))
+          (port CLKOS3
+            (direction OUTPUT))
+          (port LOCK
+            (direction OUTPUT))
+          (port INTLOCK
+            (direction OUTPUT))
+          (port REFCLK
+            (direction OUTPUT))
+          (port CLKINTFB
+            (direction OUTPUT)))))
+    (cell VHI
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port Z
+            (direction OUTPUT)))))
+    (cell VLO
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port Z
+            (direction OUTPUT)))))
+    (cell IB
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port I
+            (direction INPUT))
+          (port O
+            (direction OUTPUT)))))
+    (cell pll_in200_out100
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port CLKI
+            (direction INPUT))
+          (port CLKOP
+            (direction OUTPUT))
+          (port CLKOS
+            (direction OUTPUT))
+          (port LOCK
+            (direction OUTPUT)))
+        (property NGD_DRC_MASK (integer 1))
+        (contents
+          (instance Inst1_IB
+            (viewRef view1 
+              (cellRef IB))
+            (property IO_TYPE
+              (string "LVDS")))
+          (instance scuba_vhi_inst
+            (viewRef view1 
+              (cellRef VHI)))
+          (instance scuba_vlo_inst
+            (viewRef view1 
+              (cellRef VLO)))
+          (instance PLLInst_0
+            (viewRef view1 
+              (cellRef EHXPLLL))
+            (property PLLRST_ENA
+              (string "DISABLED"))
+            (property INTFB_WAKE
+              (string "DISABLED"))
+            (property STDBY_ENABLE
+              (string "DISABLED"))
+            (property DPHASE_SOURCE
+              (string "DISABLED"))
+            (property CLKOS3_FPHASE
+              (string "0"))
+            (property CLKOS3_CPHASE
+              (string "0"))
+            (property CLKOS2_FPHASE
+              (string "0"))
+            (property CLKOS2_CPHASE
+              (string "0"))
+            (property CLKOS_FPHASE
+              (string "0"))
+            (property CLKOS_CPHASE
+              (string "0"))
+            (property CLKOP_FPHASE
+              (string "0"))
+            (property CLKOP_CPHASE
+              (string "5"))
+            (property PLL_LOCK_MODE
+              (string "0"))
+            (property CLKOS_TRIM_DELAY
+              (string "0"))
+            (property CLKOS_TRIM_POL
+              (string "FALLING"))
+            (property CLKOP_TRIM_DELAY
+              (string "0"))
+            (property CLKOP_TRIM_POL
+              (string "FALLING"))
+            (property OUTDIVIDER_MUXD
+              (string "DIVD"))
+            (property CLKOS3_ENABLE
+              (string "DISABLED"))
+            (property OUTDIVIDER_MUXC
+              (string "DIVC"))
+            (property CLKOS2_ENABLE
+              (string "DISABLED"))
+            (property FREQUENCY_PIN_CLKOS
+              (string "200.000000"))
+            (property OUTDIVIDER_MUXB
+              (string "DIVB"))
+            (property CLKOS_ENABLE
+              (string "ENABLED"))
+            (property FREQUENCY_PIN_CLKOP
+              (string "100.000000"))
+            (property OUTDIVIDER_MUXA
+              (string "DIVA"))
+            (property CLKOP_ENABLE
+              (string "ENABLED"))
+            (property FREQUENCY_PIN_CLKI
+              (string "200.000000"))
+            (property ICP_CURRENT
+              (string "9"))
+            (property LPF_RESISTOR
+              (string "72"))
+            (property CLKOS3_DIV
+              (string "1"))
+            (property CLKOS2_DIV
+              (string "1"))
+            (property CLKOS_DIV
+              (string "1"))
+            (property CLKOP_DIV
+              (string "6"))
+            (property CLKFB_DIV
+              (string "1"))
+            (property CLKI_DIV
+              (string "2"))
+            (property FEEDBK_PATH
+              (string "CLKOP")))
+          (net REFCLK
+            (joined
+              (portRef REFCLK (instanceRef PLLInst_0))))
+          (net buf_CLKI
+            (joined
+              (portRef O (instanceRef Inst1_IB))
+              (portRef CLKI (instanceRef PLLInst_0))))
+          (net scuba_vhi
+            (joined
+              (portRef Z (instanceRef scuba_vhi_inst))))
+          (net scuba_vlo
+            (joined
+              (portRef Z (instanceRef scuba_vlo_inst))
+              (portRef ENCLKOS3 (instanceRef PLLInst_0))
+              (portRef ENCLKOS2 (instanceRef PLLInst_0))
+              (portRef ENCLKOS (instanceRef PLLInst_0))
+              (portRef ENCLKOP (instanceRef PLLInst_0))
+              (portRef RST (instanceRef PLLInst_0))
+              (portRef PLLWAKESYNC (instanceRef PLLInst_0))
+              (portRef STDBY (instanceRef PLLInst_0))
+              (portRef PHASELOADREG (instanceRef PLLInst_0))
+              (portRef PHASESTEP (instanceRef PLLInst_0))
+              (portRef PHASEDIR (instanceRef PLLInst_0))
+              (portRef PHASESEL1 (instanceRef PLLInst_0))
+              (portRef PHASESEL0 (instanceRef PLLInst_0))))
+          (net LOCK
+            (joined
+              (portRef LOCK)
+              (portRef LOCK (instanceRef PLLInst_0))))
+          (net CLKOS
+            (joined
+              (portRef CLKOS)
+              (portRef CLKOS (instanceRef PLLInst_0))))
+          (net CLKOP
+            (joined
+              (portRef CLKOP)
+              (portRef CLKFB (instanceRef PLLInst_0))
+              (portRef CLKOP (instanceRef PLLInst_0))))
+          (net CLKI
+            (joined
+              (portRef CLKI)
+              (portRef I (instanceRef Inst1_IB))))))))
+  (design pll_in200_out100
+    (cellRef pll_in200_out100
+      (libraryRef ORCLIB)))
+)

diff --git a/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc b/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc
new file mode 100644 (file)
index 0000000..6fbcac9
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc
@@ -0,0 +1,2 @@
+###==== Start Configuration
+

diff --git a/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100.lpc b/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100.lpc
new file mode 100644 (file)
index 0000000..cb1b7d9
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100.lpc
@@ -0,0 +1,93 @@
+[Device]
+Family=ecp5um
+PartType=LFE5UM-85F
+PartName=LFE5UM-85F-8MG285C
+SpeedGrade=8
+Package=CSFBGA285
+OperatingCondition=COM
+Status=C
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.7
+ModuleName=pll_in200_out100
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=03/17/2015
+Time=15:42:59
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=None
+Order=None
+IO=0
+CLKI_FREQ=200
+CLKI_DIV=2
+ENABLE_HBW=DISABLED
+REFERENCE=1
+IOBUF=LVDS
+CLKOP_FREQ=100.00
+CLKOP_TOL=0.0
+CLKOP_DIV=6
+CLKOP_ACTUAL_FREQ=100.000000
+CLKOP_MUXA=DISABLED
+CLKOS_Enable=ENABLED
+CLKOS_FREQ=100.00
+CLKOS_TOL=0.0
+CLKOS_DIV=1
+CLKOS_ACTUAL_FREQ=200.000000
+CLKOS_MUXB=ENABLED
+CLKOS2_Enable=DISABLED
+CLKOS2_FREQ=100.00
+CLKOS2_TOL=0.0
+CLKOS2_DIV=1
+CLKOS2_ACTUAL_FREQ=
+CLKOS2_MUXC=DISABLED
+CLKOS3_Enable=DISABLED
+CLKOS3_FREQ=100.00
+CLKOS3_TOL=0.0
+CLKOS3_DIV=1
+CLKOS3_ACTUAL_FREQ=
+CLKOS3_MUXD=DISABLED
+FEEDBK_PATH=CLKOP
+CLKFB_DIV=1
+FRACN_ENABLE=DISABLED
+FRACN_DIV=
+VCO_RATE=600.000
+PLL_BW=8.185
+CLKOP_DPHASE=0
+CLKOP_APHASE=0.00
+CLKOP_TRIM_POL=Rising
+CLKOP_TRIM_DELAY=0
+CLKOS_DPHASE=0
+CLKOS_APHASE=0.00
+CLKOS_TRIM_POL=Rising
+CLKOS_TRIM_DELAY=0
+CLKOS2_DPHASE=0
+CLKOS2_APHASE=0.00
+CLKOS2_TRIM_POL=Rising
+CLKOS2_TRIM_DELAY=0
+CLKOS3_DPHASE=0
+CLKOS3_APHASE=0.00
+CLKOS3_TRIM_POL=Rising
+CLKOS3_TRIM_DELAY=0
+CLKSEL_ENA=DISABLED
+DPHASE_SOURCE=STATIC
+ENABLE_CLKOP=DISABLED
+ENABLE_CLKOS=DISABLED
+ENABLE_CLKOS2=DISABLED
+ENABLE_CLKOS3=DISABLED
+STDBY_ENABLE=DISABLED
+PLLRST_ENA=DISABLED
+PLL_LOCK_MODE=ENABLED
+PLL_LOCK_STK=DISABLED
+PLL_USE_SMI=DISABLED
+
+[Command]
+cmd_line= -w -n pll_in200_out100 -lang vhdl -synth synplify -arch sa5p00m -type pll -fin 200 -clkibuf LVDS -fclkop 100.00 -fclkop_tol 0.0 -bypass_divs -phase_cntl STATIC -lock -fb_mode 1

diff --git a/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100.ngd b/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100.ngd
new file mode 100644 (file)
index 0000000..a8dd8bc
Binary files /dev/null and b/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100.ngd differ

diff --git a/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100.ngo b/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100.ngo
new file mode 100644 (file)
index 0000000..417aa39
Binary files /dev/null and b/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100.ngo differ

diff --git a/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd b/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd
new file mode 100644 (file)
index 0000000..0d6e70d
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd
@@ -0,0 +1,86 @@
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80
+-- Module  Version: 5.7
+--/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n pll_in200_out100 -lang vhdl -synth synplify -arch sa5p00m -type pll -fin 200 -clkibuf LVDS -fclkop 100.00 -fclkop_tol 0.0 -bypass_divs -phase_cntl STATIC -lock -fb_mode 1 -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc 
+
+-- Tue Mar 17 15:43:11 2015
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity pll_in200_out100 is
+    port (
+        CLKI: in  std_logic; 
+        CLKOP: out  std_logic; 
+        CLKOS: out  std_logic; 
+        LOCK: out  std_logic);
+ attribute dont_touch : boolean;
+ attribute dont_touch of pll_in200_out100 : entity is true;
+end pll_in200_out100;
+
+architecture Structure of pll_in200_out100 is
+
+    -- internal signal declarations
+    signal REFCLK: std_logic;
+    signal CLKOS_t: std_logic;
+    signal CLKOP_t: std_logic;
+    signal buf_CLKI: std_logic;
+    signal scuba_vhi: std_logic;
+    signal scuba_vlo: std_logic;
+
+    attribute IO_TYPE : string; 
+    attribute FREQUENCY_PIN_CLKOS : string; 
+    attribute FREQUENCY_PIN_CLKOP : string; 
+    attribute FREQUENCY_PIN_CLKI : string; 
+    attribute ICP_CURRENT : string; 
+    attribute LPF_RESISTOR : string; 
+    attribute IO_TYPE of Inst1_IB : label is "LVDS";
+    attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "200.000000";
+    attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "100.000000";
+    attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000";
+    attribute ICP_CURRENT of PLLInst_0 : label is "9";
+    attribute LPF_RESISTOR of PLLInst_0 : label is "72";
+    attribute syn_keep : boolean;
+    attribute syn_noprune : boolean;
+    attribute syn_noprune of Structure : architecture is true;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    Inst1_IB: IB
+        port map (I=>CLKI, O=>buf_CLKI);
+
+    scuba_vhi_inst: VHI
+        port map (Z=>scuba_vhi);
+
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    PLLInst_0: EHXPLLL
+        generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED", 
+        STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED", 
+        CLKOS3_FPHASE=>  0, CLKOS3_CPHASE=>  0, CLKOS2_FPHASE=>  0, 
+        CLKOS2_CPHASE=>  0, CLKOS_FPHASE=>  0, CLKOS_CPHASE=>  0, 
+        CLKOP_FPHASE=>  0, CLKOP_CPHASE=>  5, PLL_LOCK_MODE=>  0, 
+        CLKOS_TRIM_DELAY=>  0, CLKOS_TRIM_POL=> "FALLING", 
+        CLKOP_TRIM_DELAY=>  0, CLKOP_TRIM_POL=> "FALLING", 
+        OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED", 
+        OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "DISABLED", 
+        OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "ENABLED", 
+        OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=>  1, 
+        CLKOS2_DIV=>  1, CLKOS_DIV=>  1, CLKOP_DIV=>  6, CLKFB_DIV=>  1, 
+        CLKI_DIV=>  2, FEEDBK_PATH=> "CLKOP")
+        port map (CLKI=>buf_CLKI, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo, 
+            PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo, 
+            PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo, 
+            STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, 
+            ENCLKOP=>scuba_vlo, ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo, 
+            ENCLKOS3=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t, 
+            CLKOS2=>open, CLKOS3=>open, LOCK=>LOCK, INTLOCK=>open, 
+            REFCLK=>REFCLK, CLKINTFB=>open);
+
+    CLKOS <= CLKOS_t;
+    CLKOP <= CLKOP_t;
+end Structure;

diff --git a/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100_ngd.asd b/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100_ngd.asd
new file mode 100644 (file)
index 0000000..c265c78
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100_ngd.asd
@@ -0,0 +1 @@
+[ActiveSupport NGD]

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/.recordref b/lattice/ecp5/PLL/pll_in200_out100/syn_results/.recordref
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/dm/layer0.xdm b/lattice/ecp5/PLL/pll_in200_out100/syn_results/dm/layer0.xdm
new file mode 100644 (file)
index 0000000..68f68d0
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/dm/layer0.xdm
@@ -0,0 +1,177 @@
+%%% protect protected_file
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+@ 

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/licbug.txt b/lattice/ecp5/PLL/pll_in200_out100/syn_results/licbug.txt
new file mode 100644 (file)
index 0000000..085ef99
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/licbug.txt
@@ -0,0 +1 @@
+MainAppInit 50

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.areasrr b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.areasrr
new file mode 100644 (file)
index 0000000..b4a79ee
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.areasrr
@@ -0,0 +1,16 @@
+----------------------------------------------------------------------
+Report for cell pll_in200_out100.structure
+
+Register bits: 0 of 24288 (0%)
+PIC Latch:       0
+I/O cells:       1
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                            EHXPLLL        1       100.0
+                                GSR        1       100.0
+                                 IB        1       100.0
+                                PUR        1       100.0
+                                VHI        1       100.0
+                                VLO        1       100.0
+                            
+                         TOTAL             6           

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.edn b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.edn
new file mode 100644 (file)
index 0000000..e7f7754
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.edn
@@ -0,0 +1,236 @@
+(edif pll_in200_out100
+  (edifVersion 2 0 0)
+  (edifLevel 0)
+  (keywordMap (keywordLevel 0))
+  (status
+    (written
+      (timeStamp 2015 3 17 15 43 13)
+      (author "Synopsys, Inc.")
+      (program "Synplify Pro" (version "J-2014.09-SP2, mapper maprc, Build 2453R"))
+     )
+   )
+  (library ecp5um
+    (edifLevel 0)
+    (technology (numberDefinition ))
+    (cell EHXPLLL (cellType GENERIC)
+       (view syn_black_box (viewType NETLIST)
+         (interface
+           (port CLKI (direction INPUT))
+           (port CLKFB (direction INPUT))
+           (port PHASESEL1 (direction INPUT))
+           (port PHASESEL0 (direction INPUT))
+           (port PHASEDIR (direction INPUT))
+           (port PHASESTEP (direction INPUT))
+           (port PHASELOADREG (direction INPUT))
+           (port STDBY (direction INPUT))
+           (port PLLWAKESYNC (direction INPUT))
+           (port RST (direction INPUT))
+           (port ENCLKOP (direction INPUT))
+           (port ENCLKOS (direction INPUT))
+           (port ENCLKOS2 (direction INPUT))
+           (port ENCLKOS3 (direction INPUT))
+           (port CLKOP (direction OUTPUT))
+           (port CLKOS (direction OUTPUT))
+           (port CLKOS2 (direction OUTPUT))
+           (port CLKOS3 (direction OUTPUT))
+           (port LOCK (direction OUTPUT))
+           (port INTLOCK (direction OUTPUT))
+           (port REFCLK (direction OUTPUT))
+           (port CLKINTFB (direction OUTPUT))
+         )
+        (property CLKI_DIV (integer 1))
+        (property CLKFB_DIV (integer 1))
+        (property CLKOP_DIV (integer 8))
+        (property CLKOS_DIV (integer 8))
+        (property CLKOS2_DIV (integer 8))
+        (property CLKOS3_DIV (integer 8))
+        (property CLKOP_ENABLE (string "ENABLED"))
+        (property CLKOS_ENABLE (string "DISABLED"))
+        (property CLKOS2_ENABLE (string "DISABLED"))
+        (property CLKOS3_ENABLE (string "DISABLED"))
+        (property CLKOP_CPHASE (integer 0))
+        (property CLKOS_CPHASE (integer 0))
+        (property CLKOS2_CPHASE (integer 0))
+        (property CLKOS3_CPHASE (integer 0))
+        (property CLKOP_FPHASE (integer 0))
+        (property CLKOS_FPHASE (integer 0))
+        (property CLKOS2_FPHASE (integer 0))
+        (property CLKOS3_FPHASE (integer 0))
+        (property FEEDBK_PATH (string "CLKOP"))
+        (property CLKOP_TRIM_POL (string "RISING"))
+        (property CLKOP_TRIM_DELAY (integer 0))
+        (property CLKOS_TRIM_POL (string "RISING"))
+        (property CLKOS_TRIM_DELAY (integer 0))
+        (property OUTDIVIDER_MUXA (string "DIVA"))
+        (property OUTDIVIDER_MUXB (string "DIVB"))
+        (property OUTDIVIDER_MUXC (string "DIVC"))
+        (property OUTDIVIDER_MUXD (string "DIVD"))
+        (property PLL_LOCK_MODE (integer 0))
+        (property PLL_LOCK_DELAY (integer 200))
+        (property STDBY_ENABLE (string "DISABLED"))
+        (property REFIN_RESET (string "DISABLED"))
+        (property SYNC_ENABLE (string "DISABLED"))
+        (property INT_LOCK_STICKY (string "ENABLED"))
+        (property DPHASE_SOURCE (string "DISABLED"))
+        (property PLLRST_ENA (string "DISABLED"))
+        (property INTFB_WAKE (string "DISABLED"))
+        (property orig_inst_of (string "EHXPLLL"))
+       )
+    )
+  )
+  (library LUCENT
+    (edifLevel 0)
+    (technology (numberDefinition ))
+    (cell IB (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port I (direction INPUT))
+           (port O (direction OUTPUT))
+         )
+       )
+    )
+    (cell GSR (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port GSR (direction INPUT))
+         )
+       )
+    )
+    (cell VHI (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port Z (direction OUTPUT))
+         )
+       )
+    )
+    (cell VLO (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port Z (direction OUTPUT))
+         )
+       )
+    )
+  )
+  (library work
+    (edifLevel 0)
+    (technology (numberDefinition ))
+    (cell pll_in200_out100 (cellType GENERIC)
+       (view structure (viewType NETLIST)
+         (interface
+           (port CLKI (direction INPUT))
+           (port CLKOP (direction OUTPUT))
+           (port CLKOS (direction OUTPUT))
+           (port LOCK (direction OUTPUT))
+         )
+         (contents
+          (instance GND_0 (viewRef PRIM (cellRef VLO (libraryRef LUCENT)))          )
+          (instance VCC_0 (viewRef PRIM (cellRef VHI (libraryRef LUCENT)))          )
+          (instance GSR_INST (viewRef PRIM (cellRef GSR (libraryRef LUCENT)))
+          )
+          (instance Inst1_IB (viewRef PRIM (cellRef IB (libraryRef LUCENT)))
+           (property IO_TYPE (string "LVDS"))
+          )
+          (instance PLLInst_0 (viewRef syn_black_box (cellRef EHXPLLL (libraryRef ecp5um)))
+           (property INTFB_WAKE (string "DISABLED"))
+           (property PLLRST_ENA (string "DISABLED"))
+           (property DPHASE_SOURCE (string "DISABLED"))
+           (property STDBY_ENABLE (string "DISABLED"))
+           (property PLL_LOCK_MODE (integer 0))
+           (property OUTDIVIDER_MUXD (string "DIVD"))
+           (property OUTDIVIDER_MUXC (string "DIVC"))
+           (property OUTDIVIDER_MUXB (string "DIVB"))
+           (property OUTDIVIDER_MUXA (string "DIVA"))
+           (property CLKOS_TRIM_DELAY (integer 0))
+           (property CLKOS_TRIM_POL (string "FALLING"))
+           (property CLKOP_TRIM_DELAY (integer 0))
+           (property CLKOP_TRIM_POL (string "FALLING"))
+           (property FEEDBK_PATH (string "CLKOP"))
+           (property CLKOS3_FPHASE (integer 0))
+           (property CLKOS2_FPHASE (integer 0))
+           (property CLKOS_FPHASE (integer 0))
+           (property CLKOP_FPHASE (integer 0))
+           (property CLKOS3_CPHASE (integer 0))
+           (property CLKOS2_CPHASE (integer 0))
+           (property CLKOS_CPHASE (integer 0))
+           (property CLKOP_CPHASE (integer 5))
+           (property CLKOS3_ENABLE (string "DISABLED"))
+           (property CLKOS2_ENABLE (string "DISABLED"))
+           (property CLKOS_ENABLE (string "ENABLED"))
+           (property CLKOP_ENABLE (string "ENABLED"))
+           (property CLKOS3_DIV (integer 1))
+           (property CLKOS2_DIV (integer 1))
+           (property CLKOS_DIV (integer 1))
+           (property CLKOP_DIV (integer 6))
+           (property CLKFB_DIV (integer 1))
+           (property CLKI_DIV (integer 2))
+           (property LPF_RESISTOR (string "72"))
+           (property ICP_CURRENT (string "9"))
+           (property FREQUENCY_PIN_CLKI (string "200.000000"))
+           (property FREQUENCY_PIN_CLKOP (string "100.000000"))
+           (property FREQUENCY_PIN_CLKOS (string "200.000000"))
+          )
+          (net CLKI (joined
+           (portRef CLKI)
+           (portRef I (instanceRef Inst1_IB))
+          ))
+          (net CLKOP (joined
+           (portRef CLKOP (instanceRef PLLInst_0))
+           (portRef CLKFB (instanceRef PLLInst_0))
+           (portRef CLKOP)
+          ))
+          (net CLKOS (joined
+           (portRef CLKOS (instanceRef PLLInst_0))
+           (portRef CLKOS)
+          ))
+          (net LOCK (joined
+           (portRef LOCK (instanceRef PLLInst_0))
+           (portRef LOCK)
+          ))
+          (net CLKOS2 (joined
+           (portRef CLKOS2 (instanceRef PLLInst_0))
+          ))
+          (net CLKOS3 (joined
+           (portRef CLKOS3 (instanceRef PLLInst_0))
+          ))
+          (net INTLOCK (joined
+           (portRef INTLOCK (instanceRef PLLInst_0))
+          ))
+          (net CLKINTFB (joined
+           (portRef CLKINTFB (instanceRef PLLInst_0))
+          ))
+          (net buf_CLKI (joined
+           (portRef O (instanceRef Inst1_IB))
+           (portRef CLKI (instanceRef PLLInst_0))
+          ))
+          (net REFCLK (joined
+           (portRef REFCLK (instanceRef PLLInst_0))
+          ))
+          (net GND (joined
+           (portRef Z (instanceRef GND_0))
+           (portRef ENCLKOS3 (instanceRef PLLInst_0))
+           (portRef ENCLKOS2 (instanceRef PLLInst_0))
+           (portRef ENCLKOS (instanceRef PLLInst_0))
+           (portRef ENCLKOP (instanceRef PLLInst_0))
+           (portRef RST (instanceRef PLLInst_0))
+           (portRef PLLWAKESYNC (instanceRef PLLInst_0))
+           (portRef STDBY (instanceRef PLLInst_0))
+           (portRef PHASELOADREG (instanceRef PLLInst_0))
+           (portRef PHASESTEP (instanceRef PLLInst_0))
+           (portRef PHASEDIR (instanceRef PLLInst_0))
+           (portRef PHASESEL0 (instanceRef PLLInst_0))
+           (portRef PHASESEL1 (instanceRef PLLInst_0))
+          ))
+          (net VCC (joined
+           (portRef Z (instanceRef VCC_0))
+           (portRef GSR (instanceRef GSR_INST))
+          ))
+         )
+        (property NGD_DRC_MASK (integer 1))
+        (property dont_touch (integer 1))
+        (property orig_inst_of (string "pll_in200_out100"))
+       )
+    )
+  )
+  (design pll_in200_out100 (cellRef pll_in200_out100 (libraryRef work))
+       (property PART (string "lfe5um_25f-6") ))
+)

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.fse b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.fse
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.htm b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.htm
new file mode 100644 (file)
index 0000000..db9de8a
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.htm
@@ -0,0 +1,9 @@
+<html>
+ <head>
+ <title>syntmp/pll_in200_out100_srr.htm log file</title>
+ </head>
+ <frameset cols="20%, 80%">
+ <frame src="syntmp/pll_in200_out100_toc.htm" name="tocFrame" />
+                                <frame src="syntmp/pll_in200_out100_srr.htm" name="srrFrame"/>
+</frameset>
+ </html>

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.prj b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.prj
new file mode 100644 (file)
index 0000000..1131742
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.prj
@@ -0,0 +1,46 @@
+#-- Lattice Semiconductor Corporation Ltd.
+#-- Synplify OEM project file /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.prj
+#-- Written on Tue Mar 17 15:43:11 2015
+
+
+#device options
+set_option -technology ecp5um
+set_option -part LFE5UM-85F
+set_option -speed_grade 8
+
+#use verilog 2001 standard option
+set_option -vlog_std v2001
+
+#map options
+set_option -frequency 100
+set_option -fanout_limit 50
+set_option -disable_io_insertion true
+set_option -retiming false
+set_option -pipe false
+set_option -pipe false
+set_option -force_gsr false
+
+#simulation options
+set_option -write_verilog true
+set_option -write_vhdl true
+
+#timing analysis options
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#-- add_file options
+add_file -vhdl -lib work "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd"
+add_file -constraint {"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc"}
+
+#-- top module name
+set_option -top_module pll_in200_out100
+
+#-- set result format/file last
+project -result_file "pll_in200_out100.edn"
+
+#-- error message log file
+project -log_file pll_in200_out100.srf
+
+#-- run Synplify with 'arrange VHDL file'
+project -run

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srd b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srd
new file mode 100644 (file)
index 0000000..979e704
Binary files /dev/null and b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srd differ

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srf b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srf
new file mode 100644 (file)
index 0000000..15854e8
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srf
@@ -0,0 +1,373 @@
+#Build: Synplify Pro J-2014.09-SP2, Build 1283R, Nov 20 2014
+#install: /opt/synopsys/J-2014.09-SP2
+#OS: Linux 
+#Hostname: depc363
+
+#Implementation: syn_results
+
+Synopsys HDL Compiler, version comp201409sp2rc, Build 069R, built Nov 20 2014
+@N|Running in 64-bit mode
+Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
+
+Running on host :depc363
+Synopsys VHDL Compiler, version comp201409sp2rc, Build 069R, built Nov 20 2014
+@N|Running in 64-bit mode
+Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
+
+@N: CD720 :"/opt/synopsys/J-2014.09-SP2/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ns
+@N:"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":12:7:12:22|Top entity is set to pll_in200_out100.
+VHDL syntax check successful!
+@N: CD630 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":12:7:12:22|Synthesizing work.pll_in200_out100.structure 
+@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":2081:10:2081:16|Synthesizing ecp5um.ehxplll.syn_black_box 
+Post processing for ecp5um.ehxplll.syn_black_box
+@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":830:10:830:12|Synthesizing ecp5um.vlo.syn_black_box 
+Post processing for ecp5um.vlo.syn_black_box
+@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":823:10:823:12|Synthesizing ecp5um.vhi.syn_black_box 
+Post processing for ecp5um.vhi.syn_black_box
+@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":998:10:998:11|Synthesizing ecp5um.ib.syn_black_box 
+Post processing for ecp5um.ib.syn_black_box
+Post processing for work.pll_in200_out100.structure
+@W: CL168 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":55:4:55:17|Pruning instance scuba_vhi_inst -- not in use ... 
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Tue Mar 17 15:43:11 2015
+
+###########################################################]
+Synopsys Netlist Linker, version comp201409sp2rc, Build 069R, built Nov 20 2014
+@N|Running in 64-bit mode
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Tue Mar 17 15:43:11 2015
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Tue Mar 17 15:43:11 2015
+
+###########################################################]
+Synopsys Netlist Linker, version comp201409sp2rc, Build 069R, built Nov 20 2014
+@N|Running in 64-bit mode
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Tue Mar 17 15:43:12 2015
+
+###########################################################]
+Pre-mapping Report
+
+Synopsys Lattice Technology Pre-mapping, Version maprc, Build 2453R, Built Nov 20 2014 09:28:55
+Copyright (C) 1994-2014, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
+Product Version J-2014.09-SP2
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
+
+Reading constraint file: /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc
+@L: /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100_scck.rpt 
+Printing clock  summary report in "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100_scck.rpt" file 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:     0
+syn_allowed_resources : blockrams=56  set on top level netlist pll_in200_out100
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
+
+
+
+@S |Clock Summary
+****************
+
+Start      Requested     Requested     Clock      Clock          
+Clock      Frequency     Period        Type       Group          
+-----------------------------------------------------------------
+System     100.0 MHz     10.000        system     system_clkgroup
+=================================================================
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 140MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Tue Mar 17 15:43:13 2015
+
+###########################################################]
+Map & Optimize Report
+
+Synopsys Lattice Technology Mapper, Version maprc, Build 2453R, Built Nov 20 2014 09:28:55
+Copyright (C) 1994-2014, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
+Product Version J-2014.09-SP2
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
+
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 110MB peak: 111MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+
+Available hyper_sources - for debug and ip models
+       None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+Pass            CPU time               Worst Slack             Luts / Registers
+------------------------------------------------------------
+Pass            CPU time               Worst Slack             Luts / Registers
+------------------------------------------------------------
+------------------------------------------------------------
+
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
+
+
+
+#### START OF CLOCK OPTIMIZATION REPORT #####[
+
+0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+Writing Analyst data base /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+Writing Analyst data base /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+Writing EDIF Netlist and constraint files
+J-2014.09-SP2
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB)
+
+@W: MT246 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":61:4:61:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
+
+
+@S |##### START OF TIMING REPORT #####[
+# Timing Report written on Tue Mar 17 15:43:14 2015
+#
+
+
+Top view:               pll_in200_out100
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc
+                       
+@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
+
+@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
+
+
+
+Performance Summary 
+*******************
+
+
+Worst slack in design: 10.000
+
+@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching.
+                   Requested     Estimated     Requested     Estimated                Clock      Clock          
+Starting Clock     Frequency     Frequency     Period        Period        Slack      Type       Group          
+----------------------------------------------------------------------------------------------------------------
+System             100.0 MHz     NA            10.000        0.000         10.000     system     system_clkgroup
+================================================================================================================
+@N: MT582 |Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks            |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+---------------------------------------------------------------------------------------------------------
+Starting  Ending  |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
+---------------------------------------------------------------------------------------------------------
+System    System  |  10.000      10.000  |  No paths    -      |  No paths    -      |  No paths    -    
+=========================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                      Arrival           
+Instance      Reference     Type        Pin       Net       Time        Slack 
+              Clock                                                           
+------------------------------------------------------------------------------
+PLLInst_0     System        EHXPLLL     CLKOP     CLKOP     0.000       10.000
+==============================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+              Starting                                      Required           
+Instance      Reference     Type        Pin       Net       Time         Slack 
+              Clock                                                            
+-------------------------------------------------------------------------------
+PLLInst_0     System        EHXPLLL     CLKFB     CLKOP     10.000       10.000
+===============================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.000
+    + Clock delay at ending point:           0.000 (ideal)
+    + Estimated clock delay at ending point: 0.000
+    = Required time:                         10.000
+
+    - Propagation time:                      0.000
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (critical) :                     10.000
+
+    Number of logic level(s):                0
+    Starting point:                          PLLInst_0 / CLKOP
+    Ending point:                            PLLInst_0 / CLKFB
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            System [rising]
+
+Instance / Net                 Pin       Pin               Arrival     No. of    
+Name               Type        Name      Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+PLLInst_0          EHXPLLL     CLKOP     Out     0.000     0.000       -         
+CLKOP              Net         -         -       -         -           2         
+PLLInst_0          EHXPLLL     CLKFB     In      0.000     0.000       -         
+=================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+
+Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lfe5um_25f-6
+
+Register bits: 0 of 24288 (0%)
+PIC Latch:       0
+I/O cells:       1
+
+
+Details:
+EHXPLLL:        1
+GSR:            1
+IB:             1
+PUR:            1
+VHI:            1
+VLO:            1
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 143MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Tue Mar 17 15:43:14 2015
+
+###########################################################]

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srm b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srm
new file mode 100644 (file)
index 0000000..98174c4
Binary files /dev/null and b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srm differ

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srr b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srr
new file mode 100644 (file)
index 0000000..15854e8
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srr
@@ -0,0 +1,373 @@
+#Build: Synplify Pro J-2014.09-SP2, Build 1283R, Nov 20 2014
+#install: /opt/synopsys/J-2014.09-SP2
+#OS: Linux 
+#Hostname: depc363
+
+#Implementation: syn_results
+
+Synopsys HDL Compiler, version comp201409sp2rc, Build 069R, built Nov 20 2014
+@N|Running in 64-bit mode
+Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
+
+Running on host :depc363
+Synopsys VHDL Compiler, version comp201409sp2rc, Build 069R, built Nov 20 2014
+@N|Running in 64-bit mode
+Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
+
+@N: CD720 :"/opt/synopsys/J-2014.09-SP2/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ns
+@N:"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":12:7:12:22|Top entity is set to pll_in200_out100.
+VHDL syntax check successful!
+@N: CD630 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":12:7:12:22|Synthesizing work.pll_in200_out100.structure 
+@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":2081:10:2081:16|Synthesizing ecp5um.ehxplll.syn_black_box 
+Post processing for ecp5um.ehxplll.syn_black_box
+@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":830:10:830:12|Synthesizing ecp5um.vlo.syn_black_box 
+Post processing for ecp5um.vlo.syn_black_box
+@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":823:10:823:12|Synthesizing ecp5um.vhi.syn_black_box 
+Post processing for ecp5um.vhi.syn_black_box
+@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":998:10:998:11|Synthesizing ecp5um.ib.syn_black_box 
+Post processing for ecp5um.ib.syn_black_box
+Post processing for work.pll_in200_out100.structure
+@W: CL168 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":55:4:55:17|Pruning instance scuba_vhi_inst -- not in use ... 
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Tue Mar 17 15:43:11 2015
+
+###########################################################]
+Synopsys Netlist Linker, version comp201409sp2rc, Build 069R, built Nov 20 2014
+@N|Running in 64-bit mode
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Tue Mar 17 15:43:11 2015
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Tue Mar 17 15:43:11 2015
+
+###########################################################]
+Synopsys Netlist Linker, version comp201409sp2rc, Build 069R, built Nov 20 2014
+@N|Running in 64-bit mode
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Tue Mar 17 15:43:12 2015
+
+###########################################################]
+Pre-mapping Report
+
+Synopsys Lattice Technology Pre-mapping, Version maprc, Build 2453R, Built Nov 20 2014 09:28:55
+Copyright (C) 1994-2014, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
+Product Version J-2014.09-SP2
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
+
+Reading constraint file: /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc
+@L: /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100_scck.rpt 
+Printing clock  summary report in "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100_scck.rpt" file 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:     0
+syn_allowed_resources : blockrams=56  set on top level netlist pll_in200_out100
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
+
+
+
+@S |Clock Summary
+****************
+
+Start      Requested     Requested     Clock      Clock          
+Clock      Frequency     Period        Type       Group          
+-----------------------------------------------------------------
+System     100.0 MHz     10.000        system     system_clkgroup
+=================================================================
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 140MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Tue Mar 17 15:43:13 2015
+
+###########################################################]
+Map & Optimize Report
+
+Synopsys Lattice Technology Mapper, Version maprc, Build 2453R, Built Nov 20 2014 09:28:55
+Copyright (C) 1994-2014, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
+Product Version J-2014.09-SP2
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
+
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 110MB peak: 111MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+
+Available hyper_sources - for debug and ip models
+       None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+Pass            CPU time               Worst Slack             Luts / Registers
+------------------------------------------------------------
+Pass            CPU time               Worst Slack             Luts / Registers
+------------------------------------------------------------
+------------------------------------------------------------
+
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
+
+
+
+#### START OF CLOCK OPTIMIZATION REPORT #####[
+
+0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+Writing Analyst data base /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+Writing Analyst data base /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+Writing EDIF Netlist and constraint files
+J-2014.09-SP2
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB)
+
+@W: MT246 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":61:4:61:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
+
+
+@S |##### START OF TIMING REPORT #####[
+# Timing Report written on Tue Mar 17 15:43:14 2015
+#
+
+
+Top view:               pll_in200_out100
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc
+                       
+@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
+
+@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
+
+
+
+Performance Summary 
+*******************
+
+
+Worst slack in design: 10.000
+
+@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching.
+                   Requested     Estimated     Requested     Estimated                Clock      Clock          
+Starting Clock     Frequency     Frequency     Period        Period        Slack      Type       Group          
+----------------------------------------------------------------------------------------------------------------
+System             100.0 MHz     NA            10.000        0.000         10.000     system     system_clkgroup
+================================================================================================================
+@N: MT582 |Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks            |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+---------------------------------------------------------------------------------------------------------
+Starting  Ending  |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
+---------------------------------------------------------------------------------------------------------
+System    System  |  10.000      10.000  |  No paths    -      |  No paths    -      |  No paths    -    
+=========================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                      Arrival           
+Instance      Reference     Type        Pin       Net       Time        Slack 
+              Clock                                                           
+------------------------------------------------------------------------------
+PLLInst_0     System        EHXPLLL     CLKOP     CLKOP     0.000       10.000
+==============================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+              Starting                                      Required           
+Instance      Reference     Type        Pin       Net       Time         Slack 
+              Clock                                                            
+-------------------------------------------------------------------------------
+PLLInst_0     System        EHXPLLL     CLKFB     CLKOP     10.000       10.000
+===============================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.000
+    + Clock delay at ending point:           0.000 (ideal)
+    + Estimated clock delay at ending point: 0.000
+    = Required time:                         10.000
+
+    - Propagation time:                      0.000
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (critical) :                     10.000
+
+    Number of logic level(s):                0
+    Starting point:                          PLLInst_0 / CLKOP
+    Ending point:                            PLLInst_0 / CLKFB
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            System [rising]
+
+Instance / Net                 Pin       Pin               Arrival     No. of    
+Name               Type        Name      Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+PLLInst_0          EHXPLLL     CLKOP     Out     0.000     0.000       -         
+CLKOP              Net         -         -       -         -           2         
+PLLInst_0          EHXPLLL     CLKFB     In      0.000     0.000       -         
+=================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+
+Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lfe5um_25f-6
+
+Register bits: 0 of 24288 (0%)
+PIC Latch:       0
+I/O cells:       1
+
+
+Details:
+EHXPLLL:        1
+GSR:            1
+IB:             1
+PUR:            1
+VHI:            1
+VLO:            1
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 143MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Tue Mar 17 15:43:14 2015
+
+###########################################################]

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srs b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srs
new file mode 100644 (file)
index 0000000..57d784a
Binary files /dev/null and b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srs differ

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.vhm b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.vhm
new file mode 100644 (file)
index 0000000..89d3c09
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.vhm
@@ -0,0 +1,139 @@
+--
+-- Written by Synplicity
+-- Product Version "J-2014.09-SP2"
+-- Program "Synplify Pro", Mapper "maprc, Build 2453R"
+-- Tue Mar 17 15:43:14 2015
+--
+
+--
+-- Written by Synplify Pro version Build 2453R
+-- Tue Mar 17 15:43:14 2015
+--
+
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library synplify;
+use synplify.components.all;
+library pmi;
+use pmi.pmi_components.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity pll_in200_out100 is
+port(
+  CLKI :  in std_logic;
+  CLKOP :  out std_logic;
+  CLKOS :  out std_logic;
+  LOCK :  out std_logic);
+end pll_in200_out100;
+
+architecture beh of pll_in200_out100 is
+  signal CLKOP_0 : std_logic ;
+  signal CLKOS2 : std_logic ;
+  signal CLKOS3 : std_logic ;
+  signal INTLOCK : std_logic ;
+  signal CLKINTFB : std_logic ;
+  signal BUF_CLKI : std_logic ;
+  signal REFCLK : std_logic ;
+  signal GND : std_logic ;
+  signal VCC : std_logic ;
+  component EHXPLLL
+    port(
+      CLKI :  in std_logic;
+      CLKFB :  in std_logic;
+      PHASESEL1 :  in std_logic;
+      PHASESEL0 :  in std_logic;
+      PHASEDIR :  in std_logic;
+      PHASESTEP :  in std_logic;
+      PHASELOADREG :  in std_logic;
+      STDBY :  in std_logic;
+      PLLWAKESYNC :  in std_logic;
+      RST :  in std_logic;
+      ENCLKOP :  in std_logic;
+      ENCLKOS :  in std_logic;
+      ENCLKOS2 :  in std_logic;
+      ENCLKOS3 :  in std_logic;
+      CLKOP :  out std_logic;
+      CLKOS :  out std_logic;
+      CLKOS2 :  out std_logic;
+      CLKOS3 :  out std_logic;
+      LOCK :  out std_logic;
+      INTLOCK :  out std_logic;
+      REFCLK :  out std_logic;
+      CLKINTFB :  out std_logic  );
+  end component;
+begin
+GND_0: VLO port map (
+    Z => GND);
+VCC_0: VHI port map (
+    Z => VCC);
+PUR_INST: PUR port map (
+    PUR => VCC);
+GSR_INST: GSR port map (
+    GSR => VCC);
+INST1_IB: IB port map (
+    I => CLKI,
+    O => BUF_CLKI);
+PLLINST_0: EHXPLLL 
+  generic map( 
+    CLKI_DIV => 2, 
+    CLKFB_DIV => 1, 
+    CLKOP_DIV => 6, 
+    CLKOS_DIV => 1, 
+    CLKOS2_DIV => 1, 
+    CLKOS3_DIV => 1, 
+    CLKOP_ENABLE => "ENABLED", 
+    CLKOS_ENABLE => "ENABLED", 
+    CLKOS2_ENABLE => "DISABLED", 
+    CLKOS3_ENABLE => "DISABLED", 
+    CLKOP_CPHASE => 5, 
+    CLKOS_CPHASE => 0, 
+    CLKOS2_CPHASE => 0, 
+    CLKOS3_CPHASE => 0, 
+    CLKOP_FPHASE => 0, 
+    CLKOS_FPHASE => 0, 
+    CLKOS2_FPHASE => 0, 
+    CLKOS3_FPHASE => 0, 
+    FEEDBK_PATH => "CLKOP", 
+    CLKOP_TRIM_POL => "FALLING", 
+    CLKOP_TRIM_DELAY => 0, 
+    CLKOS_TRIM_POL => "FALLING", 
+    CLKOS_TRIM_DELAY => 0, 
+    OUTDIVIDER_MUXA => "DIVA", 
+    OUTDIVIDER_MUXB => "DIVB", 
+    OUTDIVIDER_MUXC => "DIVC", 
+    OUTDIVIDER_MUXD => "DIVD", 
+    PLL_LOCK_MODE => 0, 
+    STDBY_ENABLE => "DISABLED", 
+    DPHASE_SOURCE => "DISABLED", 
+    PLLRST_ENA => "DISABLED", 
+    INTFB_WAKE => "DISABLED"
+  ) 
+  port map (
+    CLKI => BUF_CLKI,
+    CLKFB => CLKOP_0,
+    PHASESEL1 => GND,
+    PHASESEL0 => GND,
+    PHASEDIR => GND,
+    PHASESTEP => GND,
+    PHASELOADREG => GND,
+    STDBY => GND,
+    PLLWAKESYNC => GND,
+    RST => GND,
+    ENCLKOP => GND,
+    ENCLKOS => GND,
+    ENCLKOS2 => GND,
+    ENCLKOS3 => GND,
+    CLKOP => CLKOP_0,
+    CLKOS => CLKOS,
+    CLKOS2 => CLKOS2,
+    CLKOS3 => CLKOS3,
+    LOCK => LOCK,
+    INTLOCK => INTLOCK,
+    REFCLK => REFCLK,
+    CLKINTFB => CLKINTFB);
+CLKOP <= CLKOP_0;
+end beh;
+

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.vm b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.vm
new file mode 100644 (file)
index 0000000..2c7d22b
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.vm
@@ -0,0 +1,120 @@
+//
+// Written by Synplify Pro 
+// Product Version "J-2014.09-SP2"
+// Program "Synplify Pro", Mapper "maprc, Build 2453R"
+// Tue Mar 17 15:43:14 2015
+//
+// Source file index table:
+// Object locations will have the form <file>:<line>
+// file 0 "\/opt/synopsys/J-2014.09-SP2/lib/vhd/std.vhd "
+// file 1 "\/opt/synopsys/J-2014.09-SP2/lib/vhd/snps_haps_pkg.vhd "
+// file 2 "\/opt/synopsys/J-2014.09-SP2/lib/vhd/std1164.vhd "
+// file 3 "\/opt/synopsys/J-2014.09-SP2/lib/vhd/numeric.vhd "
+// file 4 "\/opt/synopsys/J-2014.09-SP2/lib/vhd/umr_capim.vhd "
+// file 5 "\/opt/synopsys/J-2014.09-SP2/lib/vhd/arith.vhd "
+// file 6 "\/opt/synopsys/J-2014.09-SP2/lib/vhd/unsigned.vhd "
+// file 7 "\/opt/synopsys/J-2014.09-SP2/lib/vhd/hyperents.vhd "
+// file 8 "\/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd "
+// file 9 "\/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd "
+// file 10 "\/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc "
+
+`timescale 100 ps/100 ps
+module pll_in200_out100 (
+  CLKI,
+  CLKOP,
+  CLKOS,
+  LOCK
+)
+;
+input CLKI ;
+output CLKOP ;
+output CLKOS ;
+output LOCK ;
+wire CLKI ;
+wire CLKOP ;
+wire CLKOS ;
+wire LOCK ;
+wire CLKOS2 ;
+wire CLKOS3 ;
+wire INTLOCK ;
+wire CLKINTFB ;
+wire buf_CLKI ;
+wire REFCLK ;
+wire GND ;
+wire VCC ;
+  VLO GND_0 (
+       .Z(GND)
+);
+  VHI VCC_0 (
+       .Z(VCC)
+);
+  PUR PUR_INST (
+       .PUR(VCC)
+);
+  GSR GSR_INST (
+       .GSR(VCC)
+);
+// @8:52
+  IB Inst1_IB (
+       .I(CLKI),
+       .O(buf_CLKI)
+);
+// @8:61
+  EHXPLLL PLLInst_0 (
+       .CLKI(buf_CLKI),
+       .CLKFB(CLKOP),
+       .PHASESEL1(GND),
+       .PHASESEL0(GND),
+       .PHASEDIR(GND),
+       .PHASESTEP(GND),
+       .PHASELOADREG(GND),
+       .STDBY(GND),
+       .PLLWAKESYNC(GND),
+       .RST(GND),
+       .ENCLKOP(GND),
+       .ENCLKOS(GND),
+       .ENCLKOS2(GND),
+       .ENCLKOS3(GND),
+       .CLKOP(CLKOP),
+       .CLKOS(CLKOS),
+       .CLKOS2(CLKOS2),
+       .CLKOS3(CLKOS3),
+       .LOCK(LOCK),
+       .INTLOCK(INTLOCK),
+       .REFCLK(REFCLK),
+       .CLKINTFB(CLKINTFB)
+);
+defparam PLLInst_0.CLKI_DIV = 2;
+defparam PLLInst_0.CLKFB_DIV = 1;
+defparam PLLInst_0.CLKOP_DIV = 6;
+defparam PLLInst_0.CLKOS_DIV = 1;
+defparam PLLInst_0.CLKOS2_DIV = 1;
+defparam PLLInst_0.CLKOS3_DIV = 1;
+defparam PLLInst_0.CLKOP_ENABLE = "ENABLED";
+defparam PLLInst_0.CLKOS_ENABLE = "ENABLED";
+defparam PLLInst_0.CLKOS2_ENABLE = "DISABLED";
+defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED";
+defparam PLLInst_0.CLKOP_CPHASE = 5;
+defparam PLLInst_0.CLKOS_CPHASE = 0;
+defparam PLLInst_0.CLKOS2_CPHASE = 0;
+defparam PLLInst_0.CLKOS3_CPHASE = 0;
+defparam PLLInst_0.CLKOP_FPHASE = 0;
+defparam PLLInst_0.CLKOS_FPHASE = 0;
+defparam PLLInst_0.CLKOS2_FPHASE = 0;
+defparam PLLInst_0.CLKOS3_FPHASE = 0;
+defparam PLLInst_0.FEEDBK_PATH = "CLKOP";
+defparam PLLInst_0.CLKOP_TRIM_POL = "FALLING";
+defparam PLLInst_0.CLKOP_TRIM_DELAY = 0;
+defparam PLLInst_0.CLKOS_TRIM_POL = "FALLING";
+defparam PLLInst_0.CLKOS_TRIM_DELAY = 0;
+defparam PLLInst_0.OUTDIVIDER_MUXA = "DIVA";
+defparam PLLInst_0.OUTDIVIDER_MUXB = "DIVB";
+defparam PLLInst_0.OUTDIVIDER_MUXC = "DIVC";
+defparam PLLInst_0.OUTDIVIDER_MUXD = "DIVD";
+defparam PLLInst_0.PLL_LOCK_MODE = 0;
+defparam PLLInst_0.STDBY_ENABLE = "DISABLED";
+defparam PLLInst_0.DPHASE_SOURCE = "DISABLED";
+defparam PLLInst_0.PLLRST_ENA = "DISABLED";
+defparam PLLInst_0.INTFB_WAKE = "DISABLED";
+endmodule /* pll_in200_out100 */
+

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100_synplify.lpf b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100_synplify.lpf
new file mode 100644 (file)
index 0000000..15716ec
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100_synplify.lpf
@@ -0,0 +1,20 @@
+#
+# Logical Preferences generated for Lattice by Synplify maprc, Build 2453R.
+#
+
+# Period Constraints 
+
+
+# Output Constraints 
+
+# Input Constraints 
+
+# Point-to-point Delay Constraints 
+
+
+
+# Block Path Constraints 
+
+BLOCK ASYNCPATHS;
+
+# End of generated Logical Preferences.

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/run_options.txt b/lattice/ecp5/PLL/pll_in200_out100/syn_results/run_options.txt
new file mode 100644 (file)
index 0000000..97483f5
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/run_options.txt
@@ -0,0 +1,67 @@
+#--  Synopsys, Inc.
+#--  Version J-2014.09-SP2
+#--  Project file /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/run_options.txt
+#--  Written on Tue Mar 17 15:43:11 2015
+
+
+#project files
+add_file -vhdl -lib work "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd"
+add_file -fpga_constraint "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc"
+
+
+
+#implementation: "syn_results"
+impl -add syn_results -type fpga
+
+#
+#implementation attributes
+
+set_option -vlog_std v2001
+
+#device options
+set_option -technology ecp5um
+set_option -part LFE5UM_25F
+set_option -package MG285C
+set_option -speed_grade -6
+set_option -part_companion ""
+
+#compilation/mapping options
+set_option -top_module "pll_in200_out100"
+
+# mapper_options
+set_option -frequency 100
+set_option -write_verilog 1
+set_option -write_vhdl 1
+set_option -srs_instrumentation 1
+
+# Lattice XP
+set_option -maxfan 50
+set_option -disable_io_insertion 1
+set_option -retiming 0
+set_option -pipe 0
+set_option -forcegsr false
+set_option -fix_gated_and_generated_clocks 1
+set_option -RWCheckOnRam 1
+set_option -update_models_cp 0
+set_option -syn_edif_array_rename 1
+set_option -Write_declared_clocks_only 1
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+
+# Compiler Options
+set_option -auto_infer_blackbox 0
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_file "./pll_in200_out100.edn"
+
+#set log file 
+set_option log_file "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srf" 
+impl -active "syn_results"

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/scratchproject.prs b/lattice/ecp5/PLL/pll_in200_out100/syn_results/scratchproject.prs
new file mode 100644 (file)
index 0000000..02b31aa
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/scratchproject.prs
@@ -0,0 +1,65 @@
+#--  Synopsys, Inc.
+#--  Version J-2014.09-SP2
+#--  Project file /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/scratchproject.prs
+
+#project files
+add_file -vhdl -lib work "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd"
+add_file -fpga_constraint "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc"
+
+
+
+#implementation: "syn_results"
+impl -add /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results -type fpga
+
+#
+#implementation attributes
+
+set_option -vlog_std v2001
+
+#device options
+set_option -technology ecp5um
+set_option -part LFE5UM_25F
+set_option -package MG285C
+set_option -speed_grade -6
+set_option -part_companion ""
+
+#compilation/mapping options
+set_option -top_module "pll_in200_out100"
+
+# mapper_options
+set_option -frequency 100
+set_option -write_verilog 1
+set_option -write_vhdl 1
+set_option -srs_instrumentation 1
+
+# Lattice XP
+set_option -maxfan 50
+set_option -disable_io_insertion 1
+set_option -retiming 0
+set_option -pipe 0
+set_option -forcegsr false
+set_option -fix_gated_and_generated_clocks 1
+set_option -RWCheckOnRam 1
+set_option -update_models_cp 0
+set_option -syn_edif_array_rename 1
+set_option -Write_declared_clocks_only 1
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+
+# Compiler Options
+set_option -auto_infer_blackbox 0
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_file "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.edn"
+
+#set log file 
+set_option log_file "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srf" 
+impl -active "syn_results"

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/map.srr.rptmap b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/map.srr.rptmap
new file mode 100644 (file)
index 0000000..14f4991
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/map.srr.rptmap
@@ -0,0 +1 @@
+./synlog/pll_in200_out100_fpga_mapper.srr,map.srr,Map Log

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_compiler.srr b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_compiler.srr
new file mode 100644 (file)
index 0000000..929e022
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_compiler.srr
@@ -0,0 +1,47 @@
+Synopsys HDL Compiler, version comp201409sp2rc, Build 069R, built Nov 20 2014
+@N|Running in 64-bit mode
+Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
+
+Running on host :depc363
+Synopsys VHDL Compiler, version comp201409sp2rc, Build 069R, built Nov 20 2014
+@N|Running in 64-bit mode
+Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
+
+@N: CD720 :"/opt/synopsys/J-2014.09-SP2/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ns
+@N:"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":12:7:12:22|Top entity is set to pll_in200_out100.
+VHDL syntax check successful!
+@N: CD630 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":12:7:12:22|Synthesizing work.pll_in200_out100.structure 
+@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":2081:10:2081:16|Synthesizing ecp5um.ehxplll.syn_black_box 
+Post processing for ecp5um.ehxplll.syn_black_box
+@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":830:10:830:12|Synthesizing ecp5um.vlo.syn_black_box 
+Post processing for ecp5um.vlo.syn_black_box
+@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":823:10:823:12|Synthesizing ecp5um.vhi.syn_black_box 
+Post processing for ecp5um.vhi.syn_black_box
+@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":998:10:998:11|Synthesizing ecp5um.ib.syn_black_box 
+Post processing for ecp5um.ib.syn_black_box
+Post processing for work.pll_in200_out100.structure
+@W: CL168 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":55:4:55:17|Pruning instance scuba_vhi_inst -- not in use ... 
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Tue Mar 17 15:43:11 2015
+
+###########################################################]
+Synopsys Netlist Linker, version comp201409sp2rc, Build 069R, built Nov 20 2014
+@N|Running in 64-bit mode
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Tue Mar 17 15:43:11 2015
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Tue Mar 17 15:43:11 2015
+
+###########################################################]

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_compiler.srr.rptmap b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_compiler.srr.rptmap
new file mode 100644 (file)
index 0000000..8315622
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_compiler.srr.rptmap
@@ -0,0 +1 @@
+./synlog/pll_in200_out100_compiler.srr,pll_in200_out100_compiler.srr,Compile Log

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_fpga_mapper.srr b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_fpga_mapper.srr
new file mode 100644 (file)
index 0000000..600fb8e
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_fpga_mapper.srr
@@ -0,0 +1,257 @@
+Synopsys Lattice Technology Mapper, Version maprc, Build 2453R, Built Nov 20 2014 09:28:55
+Copyright (C) 1994-2014, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
+Product Version J-2014.09-SP2
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
+
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 110MB peak: 111MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+
+Available hyper_sources - for debug and ip models
+       None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+Pass            CPU time               Worst Slack             Luts / Registers
+------------------------------------------------------------
+Pass            CPU time               Worst Slack             Luts / Registers
+------------------------------------------------------------
+------------------------------------------------------------
+
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
+
+
+
+#### START OF CLOCK OPTIMIZATION REPORT #####[
+
+0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+Writing Analyst data base /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+Writing Analyst data base /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+Writing EDIF Netlist and constraint files
+J-2014.09-SP2
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB)
+
+@W: MT246 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":61:4:61:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
+
+
+@S |##### START OF TIMING REPORT #####[
+# Timing Report written on Tue Mar 17 15:43:14 2015
+#
+
+
+Top view:               pll_in200_out100
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc
+                       
+@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
+
+@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
+
+
+
+Performance Summary 
+*******************
+
+
+Worst slack in design: 10.000
+
+@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching.
+                   Requested     Estimated     Requested     Estimated                Clock      Clock          
+Starting Clock     Frequency     Frequency     Period        Period        Slack      Type       Group          
+----------------------------------------------------------------------------------------------------------------
+System             100.0 MHz     NA            10.000        0.000         10.000     system     system_clkgroup
+================================================================================================================
+@N: MT582 |Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks            |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+---------------------------------------------------------------------------------------------------------
+Starting  Ending  |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
+---------------------------------------------------------------------------------------------------------
+System    System  |  10.000      10.000  |  No paths    -      |  No paths    -      |  No paths    -    
+=========================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                      Arrival           
+Instance      Reference     Type        Pin       Net       Time        Slack 
+              Clock                                                           
+------------------------------------------------------------------------------
+PLLInst_0     System        EHXPLLL     CLKOP     CLKOP     0.000       10.000
+==============================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+              Starting                                      Required           
+Instance      Reference     Type        Pin       Net       Time         Slack 
+              Clock                                                            
+-------------------------------------------------------------------------------
+PLLInst_0     System        EHXPLLL     CLKFB     CLKOP     10.000       10.000
+===============================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.000
+    + Clock delay at ending point:           0.000 (ideal)
+    + Estimated clock delay at ending point: 0.000
+    = Required time:                         10.000
+
+    - Propagation time:                      0.000
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (critical) :                     10.000
+
+    Number of logic level(s):                0
+    Starting point:                          PLLInst_0 / CLKOP
+    Ending point:                            PLLInst_0 / CLKFB
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            System [rising]
+
+Instance / Net                 Pin       Pin               Arrival     No. of    
+Name               Type        Name      Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+PLLInst_0          EHXPLLL     CLKOP     Out     0.000     0.000       -         
+CLKOP              Net         -         -       -         -           2         
+PLLInst_0          EHXPLLL     CLKFB     In      0.000     0.000       -         
+=================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+
+Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lfe5um_25f-6
+
+Register bits: 0 of 24288 (0%)
+PIC Latch:       0
+I/O cells:       1
+
+
+Details:
+EHXPLLL:        1
+GSR:            1
+IB:             1
+PUR:            1
+VHI:            1
+VLO:            1
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 143MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Tue Mar 17 15:43:14 2015
+
+###########################################################]

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_fpga_mapper.srr_Min b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_fpga_mapper.srr_Min
new file mode 100644 (file)
index 0000000..f1b7379
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_fpga_mapper.srr_Min
@@ -0,0 +1,116 @@
+
+
+@S |##### START OF TIMING REPORT #####[
+# Timing Report written on Tue Mar 17 15:43:14 2015
+#
+
+
+Top view:               pll_in200_out100
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc
+                       
+@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
+
+@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
+
+
+
+Performance Summary 
+*******************
+
+
+Worst slack in design: 0.000
+
+@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching.
+                   Requested     Estimated     Requested     Estimated               Clock      Clock          
+Starting Clock     Frequency     Frequency     Period        Period        Slack     Type       Group          
+---------------------------------------------------------------------------------------------------------------
+System             100.0 MHz     100.0 MHz     10.000        10.000        0.000     system     system_clkgroup
+===============================================================================================================
+
+
+
+Clock Relationships
+*******************
+
+Clocks            |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+--------------------------------------------------------------------------------------------------------
+Starting  Ending  |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
+--------------------------------------------------------------------------------------------------------
+System    System  |  0.000       0.000  |  No paths    -      |  No paths    -      |  No paths    -    
+========================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                      Arrival          
+Instance      Reference     Type        Pin       Net       Time        Slack
+              Clock                                                          
+-----------------------------------------------------------------------------
+PLLInst_0     System        EHXPLLL     CLKOP     CLKOP     0.000       0.000
+=============================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+              Starting                                      Required          
+Instance      Reference     Type        Pin       Net       Time         Slack
+              Clock                                                           
+------------------------------------------------------------------------------
+PLLInst_0     System        EHXPLLL     CLKFB     CLKOP     0.000        0.000
+==============================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+    Propagation time:                        0.000
+    + Clock delay at starting point:         0.000 (ideal)
+-0.000
+    - Requested Period:                      0.000
+    - Hold time:                             0.000
+    - Clock delay at ending point:           0.000 (ideal)
+0.000
+    = Slack (critical) :                     0.000
+
+    Number of logic level(s):                0
+    Starting point:                          PLLInst_0 / CLKOP
+    Ending point:                            PLLInst_0 / CLKFB
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            System [rising]
+
+Instance / Net                 Pin       Pin               Arrival     No. of    
+Name               Type        Name      Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+PLLInst_0          EHXPLLL     CLKOP     Out     0.000     0.000       -         
+CLKOP              Net         -         -       -         -           2         
+PLLInst_0          EHXPLLL     CLKFB     In      0.000     0.000       -         
+=================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_fpga_mapper.szr b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_fpga_mapper.szr
new file mode 100644 (file)
index 0000000..d632b3c
Binary files /dev/null and b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_fpga_mapper.szr differ

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_multi_srs_gen.srr b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_multi_srs_gen.srr
new file mode 100644 (file)
index 0000000..cded582
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_multi_srs_gen.srr
@@ -0,0 +1,9 @@
+Synopsys Netlist Linker, version comp201409sp2rc, Build 069R, built Nov 20 2014
+@N|Running in 64-bit mode
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Tue Mar 17 15:43:12 2015
+
+###########################################################]

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_premap.srr b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_premap.srr
new file mode 100644 (file)
index 0000000..391303f
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_premap.srr
@@ -0,0 +1,49 @@
+Synopsys Lattice Technology Pre-mapping, Version maprc, Build 2453R, Built Nov 20 2014 09:28:55
+Copyright (C) 1994-2014, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
+Product Version J-2014.09-SP2
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
+
+Reading constraint file: /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc
+@L: /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100_scck.rpt 
+Printing clock  summary report in "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100_scck.rpt" file 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:     0
+syn_allowed_resources : blockrams=56  set on top level netlist pll_in200_out100
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
+
+
+
+@S |Clock Summary
+****************
+
+Start      Requested     Requested     Clock      Clock          
+Clock      Frequency     Period        Type       Group          
+-----------------------------------------------------------------
+System     100.0 MHz     10.000        system     system_clkgroup
+=================================================================
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 140MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Tue Mar 17 15:43:13 2015
+
+###########################################################]

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_premap.szr b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_premap.szr
new file mode 100644 (file)
index 0000000..bbfc77c
Binary files /dev/null and b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_premap.szr differ

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pre_map.srr.rptmap b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pre_map.srr.rptmap
new file mode 100644 (file)
index 0000000..d87f979
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pre_map.srr.rptmap
@@ -0,0 +1 @@
+./synlog/pll_in200_out100_premap.srr,pre_map.srr,Pre_Map Log

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_compiler_notes.txt b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_compiler_notes.txt
new file mode 100644 (file)
index 0000000..73b8299
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_compiler_notes.txt
@@ -0,0 +1,11 @@
+@N|Running in 64-bit mode
+@N|Running in 64-bit mode
+@N: CD720 :"/opt/synopsys/J-2014.09-SP2/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ns
+@N:"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":12:7:12:22|Top entity is set to pll_in200_out100.
+@N: CD630 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":12:7:12:22|Synthesizing work.pll_in200_out100.structure 
+@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":2081:10:2081:16|Synthesizing ecp5um.ehxplll.syn_black_box 
+@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":830:10:830:12|Synthesizing ecp5um.vlo.syn_black_box 
+@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":823:10:823:12|Synthesizing ecp5um.vhi.syn_black_box 
+@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":998:10:998:11|Synthesizing ecp5um.ib.syn_black_box 
+@N|Running in 64-bit mode
+

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_compiler_runstatus.xml b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_compiler_runstatus.xml
new file mode 100644 (file)
index 0000000..26e4c2a
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_compiler_runstatus.xml
@@ -0,0 +1,41 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the job information from compiler to be displayed as part of the summary report.
+*******************************************************************************************-->
+
+<job_run_status name="compiler"> 
+  <report_link name="Detailed report">
+    <data>/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_compiler.srr</data>
+    <title>Synopsys HDL Compiler</title>
+  </report_link> 
+  <job_status>
+    <data>Completed    </data>
+  </job_status>
+<job_info> 
+                       <info name="Notes">
+  <data>10</data>
+  <report_link name="more"><data>/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_compiler_notes.txt</data></report_link>
+  </info>
+                       <info name="Warnings">
+  <data>1</data>
+  <report_link name="more"><data>/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_compiler_warnings.txt</data></report_link>
+  </info>
+                       <info name="Errors">
+  <data>0</data>
+  <report_link name="more"><data>/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_compiler_errors.txt</data></report_link>
+  </info>
+                       <info name="CPU Time">
+  <data>-</data>
+  </info>
+                       <info name="Real Time">
+  <data>00h:00m:00s</data>
+  </info>
+                       <info name="Peak Memory">
+  <data>-</data>
+  </info>
+                       <info name="Date &amp;Time">
+  <data type="timestamp">1426603391</data>
+  </info>
+                       </job_info>
+</job_run_status>
\ No newline at end of file

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_compiler_warnings.txt b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_compiler_warnings.txt
new file mode 100644 (file)
index 0000000..46bf347
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_compiler_warnings.txt
@@ -0,0 +1,2 @@
+@W: CL168 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":55:4:55:17|Pruning instance scuba_vhi_inst -- not in use ... 
+

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_area_report.xml b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_area_report.xml
new file mode 100644 (file)
index 0000000..4a0f6ea
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_area_report.xml
@@ -0,0 +1,26 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the area information from mapper to be displayed as part of the summary report.
+*******************************************************************************************-->
+<report_table display_priority="1" name="Area Summary">
+<report_link name="Detailed report">
+<data>/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_resourceusage.rpt</data>
+<title>Resource Usage</title>
+</report_link>
+<parameter tooltip="Total Register bits used" name="Register bits">
+<data>0</data>
+</parameter>
+<parameter tooltip="Total I/O cells used" name="I/O cells">
+<data>1</data>
+</parameter>
+<parameter tcl_name="v_ram" tooltip="Total Block RAMs used" name="Block RAMs">
+<data>0</data>
+</parameter>
+<parameter tcl_name="dsp_used" tooltip="Total DSPs used" name="DSPs">
+<data>0</data>
+</parameter>
+<parameter tcl_name="total_luts" tooltip="Total ORCA LUTs used" name="ORCA LUTs">
+<data>0</data>
+</parameter>
+</report_table>

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_errors.txt b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_errors.txt
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_notes.txt b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_notes.txt
new file mode 100644 (file)
index 0000000..0ac2949
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_notes.txt
@@ -0,0 +1,11 @@
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled 
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
+@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
+@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching.
+@N: MT582 |Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack
+@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
+@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
+@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching.

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_opt_report.xml b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_opt_report.xml
new file mode 100644 (file)
index 0000000..bace87f
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_opt_report.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the optimization information from mapper to be displayed as part of the summary report.
+*******************************************************************************************-->
+<report_table display_priority="3" name="Optimizations Summary">
+<parameter tooltip="Non-gated/non-generated clock trees / Gated/generated clock trees" name="Combined Clock Conversion">
+<data>0 / 0</data>
+<report_link name="more">
+<data>/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_combined_clk.rpt</data>
+<title>START OF CLOCK OPTIMIZATION REPORT</title>
+</report_link>
+</parameter>
+</report_table>

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_runstatus.xml b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_runstatus.xml
new file mode 100644 (file)
index 0000000..aa39edd
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_runstatus.xml
@@ -0,0 +1,46 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the job information from mapper to be displayed as part of the summary report.
+*******************************************************************************************-->
+<job_run_status name="Mapper">
+<report_link name="Detailed report">
+<data>/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_fpga_mapper.srr</data>
+<title>Synopsys Lattice Technology Mapper</title>
+</report_link>
+<job_status>
+<data>Completed</data>
+</job_status>
+<job_info>
+<info name="Notes">
+<data>11</data>
+<report_link name="more">
+<data>/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_notes.txt</data>
+</report_link>
+</info>
+<info name="Warnings">
+<data>1</data>
+<report_link name="more">
+<data>/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_warnings.txt</data>
+</report_link>
+</info>
+<info name="Errors">
+<data>0</data>
+<report_link name="more">
+<data>/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_errors.txt</data>
+</report_link>
+</info>
+<info name="CPU Time">
+<data>0h:00m:01s</data>
+</info>
+<info name="Real Time">
+<data>0h:00m:01s</data>
+</info>
+<info name="Peak Memory">
+<data>143MB</data>
+</info>
+<info name="Date &amp; Time">
+<data type="timestamp">1426603394</data>
+</info>
+</job_info>
+</job_run_status>

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_timing_report.xml b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_timing_report.xml
new file mode 100644 (file)
index 0000000..5d08600
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_timing_report.xml
@@ -0,0 +1,23 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+Max Top 5 critical clocks will be reported. For rest user needs to refer to Detailed report
+*******************************************************************************************-->
+<report_table display_priority="2" name="Timing Summary">
+<report_link name="Detailed report">
+<data>/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_fpga_mapper.srr</data>
+<title>START OF TIMING REPORT</title>
+</report_link>
+<row>
+<data tcl_name="clock_name">Clock Name</data>
+<data tcl_name="req_freq">Req Freq</data>
+<data tcl_name="est_freq">Est Freq</data>
+<data tcl_name="slack">Slack</data>
+</row>
+<row>
+<data>System</data>
+<data>100.0 MHz</data>
+<data>NA</data>
+<data>10.000</data>
+</row>
+</report_table>

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_warnings.txt b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_warnings.txt
new file mode 100644 (file)
index 0000000..97bd277
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_warnings.txt
@@ -0,0 +1 @@
+@W: MT246 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":61:4:61:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_premap_errors.txt b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_premap_errors.txt
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_premap_notes.txt b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_premap_notes.txt
new file mode 100644 (file)
index 0000000..4081b54
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_premap_notes.txt
@@ -0,0 +1,2 @@
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled 

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_premap_runstatus.xml b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_premap_runstatus.xml
new file mode 100644 (file)
index 0000000..2f16611
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_premap_runstatus.xml
@@ -0,0 +1,46 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the job information from mapper to be displayed as part of the summary report.
+*******************************************************************************************-->
+<job_run_status name="Mapper">
+<report_link name="Detailed report">
+<data>/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_premap.srr</data>
+<title>Synopsys Lattice Technology Pre-mapping</title>
+</report_link>
+<job_status>
+<data>Completed</data>
+</job_status>
+<job_info>
+<info name="Notes">
+<data>2</data>
+<report_link name="more">
+<data>/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_premap_notes.txt</data>
+</report_link>
+</info>
+<info name="Warnings">
+<data>0</data>
+<report_link name="more">
+<data>/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_premap_warnings.txt</data>
+</report_link>
+</info>
+<info name="Errors">
+<data>0</data>
+<report_link name="more">
+<data>/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_premap_errors.txt</data>
+</report_link>
+</info>
+<info name="CPU Time">
+<data>0h:00m:00s</data>
+</info>
+<info name="Real Time">
+<data>0h:00m:00s</data>
+</info>
+<info name="Peak Memory">
+<data>140MB</data>
+</info>
+<info name="Date &amp; Time">
+<data type="timestamp">1426603393</data>
+</info>
+</job_info>
+</job_run_status>

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_premap_warnings.txt b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_premap_warnings.txt
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/closed.png b/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/closed.png
new file mode 100644 (file)
index 0000000..0d78634
Binary files /dev/null and b/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/closed.png differ

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/namekey.txt b/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/namekey.txt
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/open.png b/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/open.png
new file mode 100644 (file)
index 0000000..a227005
Binary files /dev/null and b/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/open.png differ

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100.plg b/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100.plg
new file mode 100644 (file)
index 0000000..c01538b
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100.plg
@@ -0,0 +1,14 @@
+@P:  Worst Slack : 10.000
+@P:  System - Estimated Frequency : NA
+@P:  System - Requested Frequency : 100.0 MHz
+@P:  System - Estimated Period : 0.000
+@P:  System - Requested Period : 10.000
+@P:  System - Slack : 10.000
+@P:  Worst Slack(min analysis) : 0.000
+@P:  System - Estimated Frequency(min analysis) : 100.0 MHz
+@P:  System - Requested Frequency(min analysis) : 100.0 MHz
+@P:  System - Estimated Period(min analysis) : 10.000
+@P:  System - Requested Period(min analysis) : 10.000
+@P:  System - Slack(min analysis) : 0.000
+@P:  Total Area : 0.0
+@P:  CPU Time : 0h:00m:01s

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100_srr.htm b/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100_srr.htm
new file mode 100644 (file)
index 0000000..60bcd8c
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100_srr.htm
@@ -0,0 +1,378 @@
+<html><body><samp><pre>
+<!@TC:1426603391>
+#Build: Synplify Pro J-2014.09-SP2, Build 1283R, Nov 20 2014
+#install: /opt/synopsys/J-2014.09-SP2
+#OS: Linux 
+#Hostname: depc363
+
+#Implementation: syn_results
+
+<a name=compilerReport1>Synopsys HDL Compiler, version comp201409sp2rc, Build 069R, built Nov 20 2014</a>
+@N: : <!@TM:1426603391> | Running in 64-bit mode 
+Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
+
+Running on host :depc363
+<a name=compilerReport2>Synopsys VHDL Compiler, version comp201409sp2rc, Build 069R, built Nov 20 2014</a>
+@N: : <!@TM:1426603391> | Running in 64-bit mode 
+Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
+
+@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="/opt/synopsys/J-2014.09-SP2/lib/vhd/std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1426603391> | Setting time resolution to ns
+@N: : <a href="/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd:12:7:12:23:@N::@XP_MSG">pll_in200_out100.vhd(12)</a><!@TM:1426603391> | Top entity is set to pll_in200_out100.
+VHDL syntax check successful!
+@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd:12:7:12:23:@N:CD630:@XP_MSG">pll_in200_out100.vhd(12)</a><!@TM:1426603391> | Synthesizing work.pll_in200_out100.structure 
+@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd:2081:10:2081:17:@N:CD630:@XP_MSG">ecp5um.vhd(2081)</a><!@TM:1426603391> | Synthesizing ecp5um.ehxplll.syn_black_box 
+Post processing for ecp5um.ehxplll.syn_black_box
+@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd:830:10:830:13:@N:CD630:@XP_MSG">ecp5um.vhd(830)</a><!@TM:1426603391> | Synthesizing ecp5um.vlo.syn_black_box 
+Post processing for ecp5um.vlo.syn_black_box
+@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd:823:10:823:13:@N:CD630:@XP_MSG">ecp5um.vhd(823)</a><!@TM:1426603391> | Synthesizing ecp5um.vhi.syn_black_box 
+Post processing for ecp5um.vhi.syn_black_box
+@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd:998:10:998:12:@N:CD630:@XP_MSG">ecp5um.vhd(998)</a><!@TM:1426603391> | Synthesizing ecp5um.ib.syn_black_box 
+Post processing for ecp5um.ib.syn_black_box
+Post processing for work.pll_in200_out100.structure
+<font color=#A52A2A>@W:<a href="@W:CL168:@XP_HELP">CL168</a> : <a href="/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd:55:4:55:18:@W:CL168:@XP_MSG">pll_in200_out100.vhd(55)</a><!@TM:1426603391> | Pruning instance scuba_vhi_inst -- not in use ... </font>
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Tue Mar 17 15:43:11 2015
+
+###########################################################]
+<a name=compilerReport3>Synopsys Netlist Linker, version comp201409sp2rc, Build 069R, built Nov 20 2014</a>
+@N: : <!@TM:1426603391> | Running in 64-bit mode 
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Tue Mar 17 15:43:11 2015
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Tue Mar 17 15:43:11 2015
+
+###########################################################]
+<a name=compilerReport4>Synopsys Netlist Linker, version comp201409sp2rc, Build 069R, built Nov 20 2014</a>
+@N: : <!@TM:1426603392> | Running in 64-bit mode 
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Tue Mar 17 15:43:12 2015
+
+###########################################################]
+Pre-mapping Report
+
+<a name=mapperReport5>Synopsys Lattice Technology Pre-mapping, Version maprc, Build 2453R, Built Nov 20 2014 09:28:55</a>
+Copyright (C) 1994-2014, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
+Product Version J-2014.09-SP2
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
+
+Reading constraint file: /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc
+Linked File: <a href="/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100_scck.rpt:@XP_FILE">pll_in200_out100_scck.rpt</a>
+Printing clock  summary report in "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100_scck.rpt" file 
+@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1426603393> | Running in 64-bit mode. 
+@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1426603393> | Clock conversion enabled  
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:     0
+syn_allowed_resources : blockrams=56  set on top level netlist pll_in200_out100
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
+
+
+
+<a name=mapperReport6>@S |Clock Summary</a>
+****************
+
+Start      Requested     Requested     Clock      Clock          
+Clock      Frequency     Period        Type       Group          
+-----------------------------------------------------------------
+System     100.0 MHz     10.000        system     system_clkgroup
+=================================================================
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 140MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Tue Mar 17 15:43:13 2015
+
+###########################################################]
+Map & Optimize Report
+
+<a name=mapperReport7>Synopsys Lattice Technology Mapper, Version maprc, Build 2453R, Built Nov 20 2014 09:28:55</a>
+Copyright (C) 1994-2014, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
+Product Version J-2014.09-SP2
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
+
+@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1426603394> | Running in 64-bit mode. 
+@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1426603394> | Clock conversion enabled  
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 110MB peak: 111MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+
+Available hyper_sources - for debug and ip models
+       None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+Pass            CPU time               Worst Slack             Luts / Registers
+------------------------------------------------------------
+Pass            CPU time               Worst Slack             Luts / Registers
+------------------------------------------------------------
+------------------------------------------------------------
+
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1426603394> | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
+
+
+
+<a name=clockReport8>#### START OF CLOCK OPTIMIZATION REPORT #####[</a>
+
+0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+Writing Analyst data base /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+Writing Analyst data base /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+Writing EDIF Netlist and constraint files
+J-2014.09-SP2
+@N:<a href="@N:BW106:@XP_HELP">BW106</a> : <!@TM:1426603394> | Synplicity Constraint File capacitance units using default value of 1pF  
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB)
+
+<font color=#A52A2A>@W:<a href="@W:MT246:@XP_HELP">MT246</a> : <a href="/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd:61:4:61:13:@W:MT246:@XP_MSG">pll_in200_out100.vhd(61)</a><!@TM:1426603394> | Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) </font>
+
+
+<a name=timingReport9>@S |##### START OF TIMING REPORT #####[</a>
+# Timing Report written on Tue Mar 17 15:43:14 2015
+#
+
+
+Top view:               pll_in200_out100
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc
+                       
+@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1426603394> | Timing report estimates place and route data. Please look at the place and route timing report for final timing. 
+
+@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1426603394> | Clock constraints cover only FF-to-FF paths associated with the clock. 
+
+
+
+<a name=performanceSummary10>Performance Summary </a>
+*******************
+
+
+Worst slack in design: 10.000
+
+@N:<a href="@N:MT286:@XP_HELP">MT286</a> : <!@TM:1426603394> | System clock period 0.000 stretches to negative invalid value -- ignoring stretching. 
+                   Requested     Estimated     Requested     Estimated                Clock      Clock          
+Starting Clock     Frequency     Frequency     Period        Period        Slack      Type       Group          
+----------------------------------------------------------------------------------------------------------------
+System             100.0 MHz     NA            10.000        0.000         10.000     system     system_clkgroup
+================================================================================================================
+@N:<a href="@N:MT582:@XP_HELP">MT582</a> : <!@TM:1426603394> | Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack 
+
+
+
+
+
+<a name=clockRelationships11>Clock Relationships</a>
+*******************
+
+Clocks            |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+---------------------------------------------------------------------------------------------------------
+Starting  Ending  |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
+---------------------------------------------------------------------------------------------------------
+System    System  |  10.000      10.000  |  No paths    -      |  No paths    -      |  No paths    -    
+=========================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+<a name=interfaceInfo12>Interface Information </a>
+*********************
+
+No IO constraint found
+
+
+
+====================================
+<a name=clockReport13>Detailed Report for Clock: System</a>
+====================================
+
+
+
+<a name=startingSlack14>Starting Points with Worst Slack</a>
+********************************
+
+              Starting                                      Arrival           
+Instance      Reference     Type        Pin       Net       Time        Slack 
+              Clock                                                           
+------------------------------------------------------------------------------
+PLLInst_0     System        EHXPLLL     CLKOP     CLKOP     0.000       10.000
+==============================================================================
+
+
+<a name=endingSlack15>Ending Points with Worst Slack</a>
+******************************
+
+              Starting                                      Required           
+Instance      Reference     Type        Pin       Net       Time         Slack 
+              Clock                                                            
+-------------------------------------------------------------------------------
+PLLInst_0     System        EHXPLLL     CLKFB     CLKOP     10.000       10.000
+===============================================================================
+
+
+
+<a name=worstPaths16>Worst Path Information</a>
+<a href="/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srr:srsf/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srs:fp:16238:16484:@XP_NAMES_GATE">View Worst Path in Analyst</a>
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.000
+    + Clock delay at ending point:           0.000 (ideal)
+    + Estimated clock delay at ending point: 0.000
+    = Required time:                         10.000
+
+    - Propagation time:                      0.000
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (critical) :                     10.000
+
+    Number of logic level(s):                0
+    Starting point:                          PLLInst_0 / CLKOP
+    Ending point:                            PLLInst_0 / CLKFB
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            System [rising]
+
+Instance / Net                 Pin       Pin               Arrival     No. of    
+Name               Type        Name      Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+PLLInst_0          EHXPLLL     CLKOP     Out     0.000     0.000       -         
+CLKOP              Net         -         -       -         -           2         
+PLLInst_0          EHXPLLL     CLKFB     In      0.000     0.000       -         
+=================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+
+Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB)
+
+---------------------------------------
+<a name=resourceUsage17>Resource Usage Report</a>
+Part: lfe5um_25f-6
+
+Register bits: 0 of 24288 (0%)
+PIC Latch:       0
+I/O cells:       1
+
+
+Details:
+EHXPLLL:        1
+GSR:            1
+IB:             1
+PUR:            1
+VHI:            1
+VLO:            1
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 143MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Tue Mar 17 15:43:14 2015
+
+###########################################################]
+
+</pre></samp></body></html>

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100_toc.htm b/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100_toc.htm
new file mode 100644 (file)
index 0000000..8c7cd79
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100_toc.htm
@@ -0,0 +1,44 @@
+ <html> 
+  <head>
+    <script type="text/javascript" src="file:///opt/synopsys/J-2014.09-SP2/lib/report/reportlog_tree.js"></script>
+    <link rel="stylesheet" type="text/css" href="file:///opt/synopsys/J-2014.09-SP2/lib/report/reportlog_tree.css" />  
+  </head> 
+
+  <body style="background-color:#e0e0ff;">
+   <script type="text/javascript"> reportLogObj.loadImage("closed.png", "open.png")</script>
+    <ul id="syn_results-menu" class="treeview" style="padding-left:12;">
+        <li style="font-size:12; font-style:normal"> <b style="background-color:#a2bff0; font-weight:bold">pll_in200_out100 (syn_results)</b> 
+         <ul rel="open" style="font-size:small;">
+
+<li style="font-size:12; font-style:normal"><b style="background-color:#a2bff0; font-weight:bold">Synthesis -  </b> 
+<ul rel="open">
+<li><a href="file:///home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100_srr.htm#compilerReport1" target="srrFrame" title="">Compiler Report</a>  </li>
+<li><a href="file:///home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100_srr.htm#compilerReport3" target="srrFrame" title="">Compiler Constraint Applicator</a>  </li>
+<li><a href="file:///home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100_srr.htm#mapperReport5" target="srrFrame" title="">Pre-mapping Report</a>  
+<ul rel="open" >
+<li><a href="file:///home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100_srr.htm#mapperReport6" target="srrFrame" title="">Clock Summary</a>  </li></ul></li>
+<li><a href="file:///home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100_srr.htm#mapperReport7" target="srrFrame" title="">Mapper Report</a>  
+<ul rel="open" >
+<li><a href="file:///home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100_srr.htm#clockReport8" target="srrFrame" title="">Clock Conversion</a>  </li>
+<li><a href="file:///home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100_srr.htm#timingReport9" target="srrFrame" title="">Timing Report</a>  
+<ul rel="open" >
+<li><a href="file:///home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100_srr.htm#performanceSummary10" target="srrFrame" title="">Performance Summary</a>  </li>
+<li><a href="file:///home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100_srr.htm#clockRelationships11" target="srrFrame" title="">Clock Relationships</a>  </li>
+<li><a href="file:///home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100_srr.htm#interfaceInfo12" target="srrFrame" title="">Interface Information</a>  </li>
+<li><a href="file://#" target="srrFrame" title="">Detailed Report for Clocks</a>  
+<ul  >
+<li><a href="file:///home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100_srr.htm#clockReport13" target="srrFrame" title="">Clock: System</a>  
+<ul  >
+<li><a href="file:///home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100_srr.htm#startingSlack14" target="srrFrame" title="">Starting Points with Worst Slack</a>  </li>
+<li><a href="file:///home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100_srr.htm#endingSlack15" target="srrFrame" title="">Ending Points with Worst Slack</a>  </li>
+<li><a href="file:///home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100_srr.htm#worstPaths16" target="srrFrame" title="">Worst Path Information</a>  </li></ul></li></ul></li></ul></li>
+<li><a href="file:///home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100_srr.htm#resourceUsage17" target="srrFrame" title="">Resource Utilization</a>  </li></ul></li></ul></li>
+<li><a href="file:///home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/stdout.log" target="srrFrame" title="">Session Log (15:43 17-Mar)</a>  
+<ul  ></ul></li>         </ul>
+        </li>
+   </ul>
+
+   <script type="text/javascript"> reportLogObj.generateLog("syn_results-menu")</script>
+
+  </body>
+ </html>
\ No newline at end of file

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/run_option.xml b/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/run_option.xml
new file mode 100644 (file)
index 0000000..3addc49
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/run_option.xml
@@ -0,0 +1,22 @@
+<?xml version="1.0" encoding="utf-8"?> 
+<!-- 
+  Synopsys, Inc.
+  Version J-2014.09-SP2
+  Project file /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/syntmp/run_option.xml
+  Written on Tue Mar 17 15:43:11 2015
+
+
+--> 
+<project_attribute_list name="Project Settings"> 
+     <option name="project_name" display_name="Project Name">pll_in200_out100</option>
+     <option name="impl_name" display_name="Implementation Name">syn_results</option>
+     <option name="top_module" display_name="Top Module">pll_in200_out100</option>
+     <option name="pipe" display_name="Pipelining">0</option>
+     <option name="retiming" display_name="Retiming">0</option>
+     <option name="resource_sharing" display_name="Resource Sharing">1</option>
+     <option name="maxfan" display_name="Fanout Guide">50</option>
+     <option name="disable_io_insertion" display_name="Disable I/O Insertion">1</option>
+     <option name="fix_gated_and_generated_clocks" display_name="Clock Conversion">1</option>
+     <option name="symbolic_fsm_compiler" display_name="FSM Compiler">1</option>
+</project_attribute_list>
+

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/statusReport.html b/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/statusReport.html
new file mode 100644 (file)
index 0000000..275f5ce
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/statusReport.html
@@ -0,0 +1,110 @@
+<html> 
+                       <head>                  <meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1" />
+                       <title>Project Status Summary Page</title>
+                       <link rel="stylesheet" type="text/css" href="projectstatuspage.css" />
+                       </head>
+                       
+                       <body style="background-color:#f0f0ff;">
+                       
+<table style="border:none;" width="100%" ><tr> <td class="outline">
+<table width="100%" border="0" cellspacing="0" cellpadding="0">             <thead class="tablehead"><tr><th colspan="4">Project Settings</th><tr> 
+ <tr> <td class="optionTitle" align="left"> Project Name</td> <td> pll_in200_out100</td> <td class="optionTitle" align="left"> Implementation Name</td> <td> syn_results</td> </tr>
+                </thead> 
+                <tbody> <tr> <td class="optionTitle" align="left"> Top Module</td> <td> pll_in200_out100</td> <td class="optionTitle" align="left"> Pipelining</td> <td> 0</td> </tr>
+<tr> <td class="optionTitle" align="left"> Retiming</td> <td> 0</td> <td class="optionTitle" align="left"> Resource Sharing</td> <td> 1</td> </tr>
+<tr> <td class="optionTitle" align="left"> Fanout Guide</td> <td> 50</td> <td class="optionTitle" align="left"> Disable I/O Insertion</td> <td> 1</td> </tr>
+<tr> <td class="optionTitle" align="left"> Clock Conversion</td> <td> 1</td> <td class="optionTitle" align="left"> FSM Compiler</td> <td> 1</td> </tr>
+ 
+</tbody> 
+  </table><br>  <table width="100%" border="0" cellspacing= "0" cellpadding= "0">
+                                  <thead class="tablehead"><tr><th colspan="9">Run Status</th></tr></thead>
+         <tbody>
+               <tr>
+                       <th align="left" width="17%">Job Name</th>
+                       <th align="left">Status</th>
+                       <td class="lnote" align="center" title="Notes"></td>
+                       <td class="lwarn" align="center" title="Warnings"></td>
+                       <td class="lerror" align="center" title="Errors"></td>
+                       <th align="left">CPU Time</th>
+                       <th align="left">Real Time</th>
+                       <th align="left">Memory</th>
+                       <th align="left">Date/Time</th>
+         </tr>
+  <tr>
+  <td class="optionTitle"> (compiler)</td><td>Complete</td>
+ <td>10</td>
+ <td>1</td>
+<td>0</td>
+<td>-</td>
+<td>00m:00s</td>
+<td>-</td>
+<td><font size="-1">17.03.2015</font><br/><font size="-2">15:43</font></td>
+</tr> 
+
+ <tr>
+  <td class="optionTitle"> (premap)</td><td>Complete</td>
+ <td>2</td>
+<td>0</td>
+<td>0</td>
+<td>0m:00s</td>
+<td>0m:00s</td>
+<td>140MB</td>
+<td><font size="-1">17.03.2015</font><br/><font size="-2">15:43</font></td>
+</tr> 
+
+ <tr>
+  <td class="optionTitle"> (fpga_mapper)</td><td>Complete</td>
+ <td>11</td>
+ <td>1</td>
+<td>0</td>
+<td>0m:01s</td>
+<td>0m:01s</td>
+<td>143MB</td>
+<td><font size="-1">17.03.2015</font><br/><font size="-2">15:43</font></td>
+</tr> 
+
+<tr>
+  <td class="optionTitle">Multi-srs Generator</td>
+  <td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td>00m:00s</td><td class="empty"></td><td class="empty"></td><td><font size="-1">17.03.2015</font><br/><font size="-2">15:43</font></td>              </tbody>
+     </table>
+ <br> 
+ <table width="100%" border="0" cellspacing= "0" cellpadding= "0">
+                                  <thead class="tablehead"><tr><th colspan="4">Area Summary</th></tr></thead>
+<tfoot> <tr> <td class="optionTitle" colspan="4"></td></tr> 
+ </tfoot> 
+ <tbody> <tr> 
+<td title ="Total Register bits used" class="optionTitle" align="left">Register bits</td> <td>0</td>
+<td title ="Total I/O cells used" class="optionTitle" align="left">I/O cells</td> <td>1</td>
+</tr>
+<tr> 
+<td title ="Total Block RAMs used" class="optionTitle" align="left">Block RAMs
+(v_ram)</td> <td>0</td>
+<td title ="Total DSPs used" class="optionTitle" align="left">DSPs
+(dsp_used)</td> <td>0</td>
+</tr>
+<tr> 
+<td title ="Total ORCA LUTs used" class="optionTitle" align="left">ORCA LUTs
+(total_luts)</td> <td>0</td>
+<td class="optionTitle"></td><td></td></tr> 
+</tbody>
+    </table><br> 
+ <table width="100%" border="0" cellspacing= "0" cellpadding= "0">
+                                  <thead class="tablehead"><tr><th colspan="4">Timing Summary</th></tr></thead>
+<tfoot> <tr> <td class="optionTitle" colspan="2"></td></tr> 
+ </tfoot> 
+<tbody> 
+   <tr><th class="optionTitle" align= "left ">Clock Name</th><th class="optionTitle" align= "left ">Req Freq</th><th class="optionTitle" align= "left ">Est Freq</th><th class="optionTitle" align= "left ">Slack</th></tr> 
+<tr> <td  align="left">System</td><td  align="left">100.0 MHz</td><td  align="left">NA</td><td  align="left">10.000</td></tr> 
+</tbody> 
+ </table>
+<br> 
+ <table width="100%" border="0" cellspacing= "0" cellpadding= "0">
+                                  <thead class="tablehead"><tr><th colspan="4">Optimizations Summary</th></tr></thead>
+ <tbody> <tr> 
+<td title ="Non-gated/non-generated clock trees / Gated/generated clock trees" class="optionTitle" align="left">Combined Clock Conversion</td> <td>0 / 0</td>
+<td class="optionTitle"></td><td></td></tr> 
+</tbody>
+    </table><br> 
+<br> 
+</td></tr></table></body> 
+ </html>
\ No newline at end of file

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/.cckTransfer b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/.cckTransfer
new file mode 100644 (file)
index 0000000..c567c7c
Binary files /dev/null and b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/.cckTransfer differ

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/_mh_info b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/_mh_info
new file mode 100644 (file)
index 0000000..37bc105
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/_mh_info
@@ -0,0 +1 @@
+|1|

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/layer0.fdep b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/layer0.fdep
new file mode 100644 (file)
index 0000000..524f434
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/layer0.fdep
@@ -0,0 +1,28 @@
+#defaultlanguage:vhdl
+#OPTIONS:"|-layerid|0|-top|pll_in200_out100|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
+#CUR:"/opt/synopsys/J-2014.09-SP2/linux_a_64/c_vhdl":1416524537
+#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/location.map":1416524427
+#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/std.vhd":1416524427
+#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/snps_haps_pkg.vhd":1416524427
+#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/std1164.vhd":1416524427
+#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/numeric.vhd":1416524427
+#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/umr_capim.vhd":1416524427
+#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/arith.vhd":1416524427
+#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/unsigned.vhd":1416524427
+#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/hyperents.vhd":1416524427
+#CUR:"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":1426603391
+#CUR:"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":1416503391
+0 "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd" vhdl
+
+# Dependency Lists (Uses list)
+0 -1
+
+# Dependency Lists (Users Of)
+0 -1
+
+# Design Unit to File Association
+arch work pll_in200_out100 structure 0
+module work pll_in200_out100 0
+
+
+# Configuration files used

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/layer0.fdeporig b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/layer0.fdeporig
new file mode 100644 (file)
index 0000000..ff57353
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/layer0.fdeporig
@@ -0,0 +1,24 @@
+#defaultlanguage:vhdl
+#OPTIONS:"|-layerid|0|-top|pll_in200_out100|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
+#CUR:"/opt/synopsys/J-2014.09-SP2/linux_a_64/c_vhdl":1416524537
+#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/location.map":1416524427
+#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/std.vhd":1416524427
+#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/snps_haps_pkg.vhd":1416524427
+#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/std1164.vhd":1416524427
+#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/numeric.vhd":1416524427
+#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/umr_capim.vhd":1416524427
+#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/arith.vhd":1416524427
+#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/unsigned.vhd":1416524427
+#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/hyperents.vhd":1416524427
+#CUR:"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":1426603391
+0 "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd" vhdl
+
+# Dependency Lists (Uses list)
+0 -1
+
+# Dependency Lists (Users Of)
+0 -1
+
+# Design Unit to File Association
+arch work pll_in200_out100 structure 0
+module work pll_in200_out100 0

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/layer0.srs b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/layer0.srs
new file mode 100644 (file)
index 0000000..7b4c239
Binary files /dev/null and b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/layer0.srs differ

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/layer0.tlg b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/layer0.tlg
new file mode 100644 (file)
index 0000000..7aa3ebb
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/layer0.tlg
@@ -0,0 +1,11 @@
+@N: CD630 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":12:7:12:22|Synthesizing work.pll_in200_out100.structure 
+@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":2081:10:2081:16|Synthesizing ecp5um.ehxplll.syn_black_box 
+Post processing for ecp5um.ehxplll.syn_black_box
+@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":830:10:830:12|Synthesizing ecp5um.vlo.syn_black_box 
+Post processing for ecp5um.vlo.syn_black_box
+@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":823:10:823:12|Synthesizing ecp5um.vhi.syn_black_box 
+Post processing for ecp5um.vhi.syn_black_box
+@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":998:10:998:11|Synthesizing ecp5um.ib.syn_black_box 
+Post processing for ecp5um.ib.syn_black_box
+Post processing for work.pll_in200_out100.structure
+@W: CL168 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":55:4:55:17|Pruning instance scuba_vhi_inst -- not in use ... 

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_comp.fdep b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_comp.fdep
new file mode 100644 (file)
index 0000000..0b16619
--- /dev/null
+++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_comp.fdep
@@ -0,0 +1,21 @@
+#OPTIONS:"|-layerid|0|-top|pll_in200_out100|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
+#CUR:"/opt/synopsys/J-2014.09-SP2/linux_a_64/c_vhdl":1416524537
+#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/location.map":1416524427
+#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/std.vhd":1416524427
+#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/snps_haps_pkg.vhd":1416524427
+#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/std1164.vhd":1416524427
+#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/numeric.vhd":1416524427
+#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/umr_capim.vhd":1416524427
+#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/arith.vhd":1416524427
+#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/unsigned.vhd":1416524427
+#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/hyperents.vhd":1416524427
+#CUR:"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":1426603391
+#CUR:"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":1416503391
+0                      "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd" vhdl
+#Dependency Lists(Uses List)
+0 -1
+#Dependency Lists(Users Of)
+0 -1
+#Design Unit to File Association
+module work pll_in200_out100 0
+arch work pll_in200_out100 structure 0

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_comp.srs b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_comp.srs
new file mode 100644 (file)
index 0000000..a123472
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diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_m.srm b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_m.srm
new file mode 100644 (file)
index 0000000..98174c4
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diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_mult.srs b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_mult.srs
new file mode 100644 (file)
index 0000000..57d784a
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diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_mult_srs/skeleton.srs b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_mult_srs/skeleton.srs
new file mode 100644 (file)
index 0000000..977f6ae
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diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_prem.fse b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_prem.fse
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_prem.srd b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_prem.srd
new file mode 100644 (file)
index 0000000..088c601
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diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_s.srm b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_s.srm
new file mode 100644 (file)
index 0000000..ea888b6
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diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_s.srs b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_s.srs
new file mode 100644 (file)
index 0000000..a123472
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