\r
\r
entity trb_net_bridge_pcie_apl is\r
+ generic(\r
+ USE_CHANNELS : channel_config_t := (c_YES,c_YES,c_NO,c_YES)\r
+ );\r
port(\r
CLK : in std_logic;\r
RESET : in std_logic;\r
APL_READ_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);\r
APL_RUN_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);\r
APL_SEQNR_IN : in std_logic_vector (8*2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_FIFO_COUNT_IN : in std_logic_vector (11*2**(c_MUX_WIDTH)-1 downto 0);\r
\r
--Internal Data Bus\r
BUS_ADDR_IN : in std_logic_vector(31 downto 0);\r
- BUS_WDAT_IN : in std_logic_vector(63 downto 0);\r
- BUS_RDAT_OUT : out std_logic_vector(63 downto 0);\r
- BUS_SEL_IN : in std_logic_vector(7 downto 0);\r
+ BUS_WDAT_IN : in std_logic_vector(31 downto 0);\r
+ BUS_RDAT_OUT : out std_logic_vector(31 downto 0);\r
+ BUS_SEL_IN : in std_logic_vector(3 downto 0);\r
BUS_WE_IN : in std_logic;\r
BUS_CYC_IN : in std_logic;\r
BUS_STB_IN : in std_logic;\r
\r
architecture trb_net_bridge_pcie_apl_arch of trb_net_bridge_pcie_apl is\r
signal fifo_net_to_pci_read : std_logic_vector(2**c_MUX_WIDTH-1 downto 0);\r
- signal fifo_net_to_pci_write : std_logic_vector(2**c_MUX_WIDTH-1 downto 0);\r
+-- signal fifo_net_to_pci_write : std_logic_vector(2**c_MUX_WIDTH-1 downto 0);\r
signal fifo_net_to_pci_dout : std_logic_vector(32*2**c_MUX_WIDTH-1 downto 0);\r
- signal fifo_net_to_pci_din : std_logic_vector(18*2**c_MUX_WIDTH-1 downto 0);\r
+-- signal fifo_net_to_pci_din : std_logic_vector(18*2**c_MUX_WIDTH-1 downto 0);\r
signal fifo_net_to_pci_valid_read : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0);\r
- signal fifo_net_to_pci_full : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0);\r
signal fifo_net_to_pci_empty : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0);\r
- signal fifo_pci_to_net_read : std_logic_vector(2**c_MUX_WIDTH-1 downto 0);\r
- signal fifo_pci_to_net_write : std_logic_vector(2**c_MUX_WIDTH-1 downto 0);\r
- signal fifo_pci_to_net_valid_read : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0);\r
- signal fifo_pci_to_net_dout : std_logic_vector(18*2**c_MUX_WIDTH-1 downto 0);\r
- signal fifo_pci_to_net_full : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0);\r
- signal fifo_pci_to_net_empty : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0);\r
+-- signal fifo_pci_to_net_read : std_logic_vector(2**c_MUX_WIDTH-1 downto 0);\r
+-- signal fifo_pci_to_net_write : std_logic_vector(2**c_MUX_WIDTH-1 downto 0);\r
+-- signal fifo_pci_to_net_valid_read : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0);\r
+-- signal fifo_pci_to_net_dout : std_logic_vector(18*2**c_MUX_WIDTH-1 downto 0);\r
+-- signal fifo_pci_to_net_full : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0);\r
+-- signal fifo_pci_to_net_empty : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0);\r
signal next_APL_SEND_OUT : std_logic_vector(2**c_MUX_WIDTH-1 downto 0);\r
- type data_count_t is array(0 to 2**c_MUX_WIDTH-1) of std_logic_vector(10 downto 0);\r
- signal fifo_pci_to_net_data_count : data_count_t;\r
- signal fifo_net_to_pci_data_count : data_count_t;\r
signal sender_control : std_logic_vector(32*2**(c_MUX_WIDTH)-1 downto 0);\r
signal sender_target : std_logic_vector(32*2**(c_MUX_WIDTH)-1 downto 0);\r
signal sender_error : std_logic_vector(32*2**(c_MUX_WIDTH)-1 downto 0);\r
-- signal comb_channel_address : integer range 0 to 7;\r
-- signal last_CPU_ADDRESS : std_logic_vector(15 downto 0);\r
\r
- signal next_CPU_DATA_OUT: std_logic_vector(31 downto 0);\r
- signal buf_CPU_DATA_OUT : std_logic_vector(31 downto 0);\r
- signal last_fifo_read : std_logic;\r
- signal buf_CPU_DATAREADY_OUT : std_logic;\r
- signal b_CPU_DATAREADY_OUT : std_logic;\r
+-- signal next_CPU_DATA_OUT: std_logic_vector(31 downto 0);\r
+-- signal buf_CPU_DATA_OUT : std_logic_vector(31 downto 0);\r
+-- signal last_fifo_read : std_logic;\r
+-- signal buf_CPU_DATAREADY_OUT : std_logic;\r
+-- signal b_CPU_DATAREADY_OUT : std_logic;\r
\r
\r
signal bus_ack_i : std_logic;\r
- signal bus_data_i : std_logic_vector(63 downto 0);\r
- signal bus_rdat_i : std_logic_vector(63 downto 0);\r
+ signal bus_data_i : std_logic_vector(31 downto 0);\r
+ signal bus_rdat_i : std_logic_vector(31 downto 0);\r
signal bus_read_i : std_logic;\r
signal bus_write_i : std_logic;\r
signal bus_stb_rising : std_logic;\r
STAT(12) <= bus_ack_i;\r
STAT(13) <= fifo_net_to_pci_read(1);\r
STAT(15 downto 14) <= BUS_WDAT_IN(1 downto 0);\r
- STAT(16) <= fifo_pci_to_net_read(1);\r
- STAT(17) <= fifo_pci_to_net_valid_read(1);\r
- STAT(18) <= fifo_pci_to_net_empty(1);\r
- STAT(19) <= fifo_pci_to_net_write(1);\r
+ STAT(16) <= '0'; --fifo_pci_to_net_read(1);\r
+ STAT(17) <= '0'; --fifo_pci_to_net_valid_read(1);\r
+ STAT(18) <= '0'; --fifo_pci_to_net_empty(1);\r
+ STAT(19) <= '0'; --fifo_pci_to_net_write(1);\r
STAT(20) <= APL_READ_IN(1);\r
- STAT(21) <= fifo_pci_to_net_full(1);\r
+ STAT(21) <= '0'; --fifo_pci_to_net_full(1);\r
STAT(22) <= RESET;\r
STAT(23) <= '0';\r
STAT(24) <= fifo_net_to_pci_empty(1);\r
STAT(25) <= fifo_net_to_pci_read(1);\r
- STAT(26) <= fifo_net_to_pci_write(1);\r
+ STAT(26) <= '0'; --fifo_net_to_pci_write(1);\r
STAT(31 downto 27) <= (others => '0');\r
\r
--------------------------------\r
bus_write_i <= BUS_WE_IN and bus_stb_rising;\r
\r
channel_address <= to_integer(unsigned(BUS_ADDR_IN(6 downto 4)));\r
--- comb_channel_address <= conv_integer(CPU_ADDRESS(6 downto 4));\r
\r
- read_regs : process(sender_control, sender_target, sender_error, sender_status, fifo_net_to_pci_data_count,\r
- fifo_pci_to_net_data_count, BUS_ADDR_IN, bus_read_i, bus_write_i, api_status,\r
- fifo_net_to_pci_full, fifo_net_to_pci_empty, fifo_pci_to_net_full, fifo_pci_to_net_empty,\r
- bus_data_i, BUS_WDAT_IN, channel_address, CTRL)\r
+ read_regs : process(sender_control, sender_target, sender_error, sender_status, APL_FIFO_COUNT_IN,\r
+ BUS_ADDR_IN, api_status, fifo_net_to_pci_empty, bus_data_i, channel_address, fifo_net_to_pci_dout)\r
variable tmp : std_logic_vector(7 downto 0);\r
begin\r
bus_data_i <= (others => '0');\r
case tmp is\r
--middle nibble is dont care\r
when x"10" =>\r
- bus_data_i <= x"00000000" & sender_control(channel_address*32+31 downto channel_address*32);\r
+ bus_data_i <= sender_control(channel_address*32+31 downto channel_address*32);\r
when x"11" =>\r
- bus_data_i <= x"00000000" & sender_target(channel_address*32+31 downto channel_address*32);\r
+ bus_data_i <= sender_target(channel_address*32+31 downto channel_address*32);\r
when x"12" =>\r
- bus_data_i <= x"00000000" & sender_error(channel_address*32+31 downto channel_address*32);\r
- when x"14" =>\r
- bus_data_i <= x"00000000" & x"000" & "00" & fifo_pci_to_net_empty(channel_address) & fifo_pci_to_net_full(channel_address)\r
- & "000000" & fifo_pci_to_net_data_count(channel_address)(9 downto 0);\r
+ bus_data_i <= sender_error(channel_address*32+31 downto channel_address*32);\r
+-- when x"14" =>\r
+-- bus_data_i <= x"000" & "00" & fifo_pci_to_net_empty(channel_address) & fifo_pci_to_net_full(channel_address)\r
+-- & "000000" & fifo_pci_to_net_data_count(channel_address)(9 downto 0);\r
when x"1F" =>\r
- bus_data_i <= x"00000000" & sender_status(channel_address*32+31 downto channel_address*32);\r
+ bus_data_i <= sender_status(channel_address*32+31 downto channel_address*32);\r
+ when x"23" =>\r
+ bus_data_i <= fifo_net_to_pci_dout(channel_address*32+31 downto channel_address*32);\r
when x"24" =>\r
- bus_data_i <= x"00000000" & x"000" & "00" & fifo_net_to_pci_empty(channel_address) & fifo_net_to_pci_full(channel_address)\r
- & "00000" & fifo_net_to_pci_data_count(channel_address)(10 downto 0);\r
- when x"30" =>\r
- bus_data_i <= x"00000000" & api_status(channel_address*32+31 downto channel_address*32);\r
+ bus_data_i <= x"000" & "00" & fifo_net_to_pci_empty(channel_address) & '0'\r
+ & "00000" & APL_FIFO_COUNT_IN(11*channel_address+10 downto 11*channel_address);\r
+ when x"30" =>-- fifo_pci_to_net_read(i) <= APL_READ_IN(i); --NOT CORRECT - last packet may be lost, but transfer size is limited anyhow\r
+\r
+ bus_data_i <= api_status(channel_address*32+31 downto channel_address*32);\r
when others =>\r
- bus_data_i <= x"00000000" & x"10000000"; --"1000000000000000000" & CTRL(31 downto 19);\r
+ bus_data_i <= x"10000000"; --"1000000000000000000" & CTRL(31 downto 19);\r
end case;\r
end process;\r
\r
\r
\r
--connection to API\r
- next_APL_SEND_OUT(i) <= '1' when BUS_ADDR_IN(11 downto 8) = "0001"\r
+ next_APL_SEND_OUT(i) <= '1' when BUS_ADDR_IN(11 downto 8) = x"1"\r
and BUS_ADDR_IN(7 downto 4) = std_logic_vector(to_unsigned(i,4))\r
- and BUS_ADDR_IN(3 downto 0) = "0000"\r
+ and BUS_ADDR_IN(3 downto 0) = x"0"\r
and bus_write_last = '1' else '0';\r
\r
- APL_DATAREADY_OUT(i) <= fifo_pci_to_net_valid_read(i);\r
- APL_DATA_OUT((i+1)*16-1 downto i*16) <= fifo_pci_to_net_dout(i*18+c_DATA_WIDTH-1 downto i*18);\r
- APL_PACKET_NUM_OUT((i)*3+1 downto i*3) <= fifo_pci_to_net_dout(i*18+c_DATA_WIDTH+1 downto i*18+c_DATA_WIDTH);\r
- APL_PACKET_NUM_OUT(i*3+2) <= '0';\r
+ APL_DATAREADY_OUT(i) <= '1' when BUS_ADDR_IN(11 downto 8) = x"1"\r
+ and BUS_ADDR_IN(7 downto 4) = std_logic_vector(to_unsigned(i,4))\r
+ and BUS_ADDR_IN(3 downto 0) = x"3"\r
+ and bus_write_i = '1' else '0';\r
+\r
+ APL_DATA_OUT((i+1)*16-1 downto i*16) <= BUS_WDAT_IN(15 downto 0);\r
+ APL_PACKET_NUM_OUT((i)*3+1 downto i*3) <= BUS_WDAT_IN(17 downto 16);\r
+ APL_PACKET_NUM_OUT(i*3+2) <= '0';\r
APL_SHORT_TRANSFER_OUT(i) <= sender_control(i*32+8);\r
APL_ERROR_PATTERN_OUT(i*32+31 downto i*32) <= sender_error(i*32+31 downto i*32);\r
APL_TARGET_ADDRESS_OUT(i*16+15 downto i*16) <= sender_target(i*32+15 downto i*32);\r
APL_DTYPE_OUT(i*4+3 downto i*4) <= sender_control(i*32+3 downto i*32);\r
- fifo_pci_to_net_read(i) <= APL_READ_IN(i); --NOT CORRECT - last packet may be lost, but transfer size is limited anyhow\r
\r
\r
--connection from API\r
- fifo_net_to_pci_dout(i*32+31 downto i*32+25) <= fifo_net_to_pci_data_count(i)(6 downto 0);\r
- fifo_net_to_pci_dout(i*32+23 downto i*32+18) <= (others => '0');\r
- fifo_net_to_pci_dout(i*32+24) <= fifo_net_to_pci_valid_read(i);\r
-\r
- fifo_net_to_pci_din(18*i+c_DATA_WIDTH-1 downto 18*i) <= APL_DATA_IN(c_DATA_WIDTH*(i+1)-1 downto c_DATA_WIDTH*i);\r
- fifo_net_to_pci_din(18*i+c_DATA_WIDTH) <= APL_PACKET_NUM_IN(c_NUM_WIDTH*i);\r
- fifo_net_to_pci_din(18*i+c_DATA_WIDTH+1) <= APL_PACKET_NUM_IN(c_NUM_WIDTH*i+2);\r
- fifo_net_to_pci_write(i) <= APL_DATAREADY_IN(i) and not fifo_net_to_pci_full(i);\r
- APL_READ_OUT(i) <= not fifo_net_to_pci_full(i);\r
+ fifo_net_to_pci_empty(i) <= not APL_DATAREADY_IN(i); --or_all(APL_FIFO_COUNT_IN(11*i+10 downto 11*i));\r
+\r
+ fifo_net_to_pci_dout(32*i+c_DATA_WIDTH-1 downto 32*i) <= APL_DATA_IN(c_DATA_WIDTH*(i+1)-1 downto c_DATA_WIDTH*i);\r
+ fifo_net_to_pci_dout(32*i+c_DATA_WIDTH) <= APL_PACKET_NUM_IN(c_NUM_WIDTH*i);\r
+ fifo_net_to_pci_dout(32*i+c_DATA_WIDTH+1) <= APL_PACKET_NUM_IN(c_NUM_WIDTH*i+2);\r
+ fifo_net_to_pci_dout(i*32+31 downto i*32+25) <= (others => '0');\r
+ fifo_net_to_pci_dout(i*32+24) <= fifo_net_to_pci_valid_read(i);\r
+ fifo_net_to_pci_dout(i*32+23 downto i*32+18) <= (others => '0');\r
+ APL_READ_OUT(i) <= fifo_net_to_pci_read(i);\r
+\r
+-- fifo_net_to_pci_din(18*i+c_DATA_WIDTH-1 downto 18*i) <= APL_DATA_IN(c_DATA_WIDTH*(i+1)-1 downto c_DATA_WIDTH*i);\r
+-- fifo_net_to_pci_din(18*i+c_DATA_WIDTH) <= APL_PACKET_NUM_IN(c_NUM_WIDTH*i);\r
+-- fifo_net_to_pci_din(18*i+c_DATA_WIDTH+1) <= APL_PACKET_NUM_IN(c_NUM_WIDTH*i+2);\r
+-- fifo_net_to_pci_write(i) <= APL_DATAREADY_IN(i) and not fifo_net_to_pci_full(i);\r
+-- APL_DATAREADY_OUT(i) <= fifo_pci_to_net_valid_read(i);\r
+-- APL_DATA_OUT((i+1)*16-1 downto i*16) <= fifo_pci_to_net_dout(i*18+c_DATA_WIDTH-1 downto i*18);\r
+-- APL_PACKET_NUM_OUT((i)*3+1 downto i*3) <= fifo_pci_to_net_dout(i*18+c_DATA_WIDTH+1 downto i*18+c_DATA_WIDTH);\r
+-- APL_PACKET_NUM_OUT(i*3+2) <= '0';\r
+-- fifo_pci_to_net_read(i) <= APL_READ_IN(i); --NOT CORRECT - last packet may be lost, but transfer size is limited anyhow\r
\r
end generate;\r
\r
\r
\r
---------------------------------\r
--- fifo as bridge to pci\r
---------------------------------\r
-\r
-\r
- gen_incoming_fifos : for i in 0 to 2**(c_MUX_WIDTH)-1 generate\r
-\r
- FIFO_NET_TO_PCI: trb_net16_fifo\r
- generic map(\r
- USE_VENDOR_CORES => c_YES,\r
- USE_DATA_COUNT => c_YES,\r
- DEPTH => 6\r
- )\r
- port map(\r
- CLK => CLK,\r
- RESET => RESET,\r
- CLK_EN => '1',\r
- READ_ENABLE_IN => fifo_net_to_pci_read(i),\r
- WRITE_ENABLE_IN => fifo_net_to_pci_write(i),\r
- DATA_IN => fifo_net_to_pci_din(18*i+15 downto 18*i),\r
- PACKET_NUM_IN => fifo_net_to_pci_din(18*i+17 downto 18*i+16),\r
- DATA_OUT => fifo_net_to_pci_dout(32*i+15 downto 32*i),\r
- PACKET_NUM_OUT => fifo_net_to_pci_dout(32*i+17 downto 32*i+16),\r
- DATA_COUNT_OUT => fifo_net_to_pci_data_count(i)(10 downto 0),\r
- full_out => fifo_net_to_pci_full(i),\r
- empty_out => fifo_net_to_pci_empty(i)\r
- );\r
-\r
- FIFO_PCI_TO_NET: trb_net16_fifo\r
- generic map(\r
- USE_VENDOR_CORES => c_YES,\r
- USE_DATA_COUNT => c_YES,\r
- DEPTH => 6\r
- )\r
- port map(\r
- CLK => CLK,\r
- RESET => RESET,\r
- CLK_EN => '1',\r
- READ_ENABLE_IN => fifo_pci_to_net_read(i),\r
- WRITE_ENABLE_IN => fifo_pci_to_net_write(i),\r
- DATA_IN => BUS_WDAT_IN(15 downto 0),\r
- PACKET_NUM_IN => BUS_WDAT_IN(17 downto 16),\r
- DATA_OUT => fifo_pci_to_net_dout(18*i+15 downto 18*i),\r
- PACKET_NUM_OUT => fifo_pci_to_net_dout(18*i+17 downto 18*i+16),\r
- DATA_COUNT_OUT => fifo_pci_to_net_data_count(i)(10 downto 0),\r
- full_out => fifo_pci_to_net_full(i),\r
- empty_out => fifo_pci_to_net_empty(i)\r
- );\r
-\r
- end generate;\r
-\r
- proc_valid_read : process(CLK)\r
- begin\r
- if rising_edge(CLK) then\r
- fifo_pci_to_net_valid_read <= fifo_pci_to_net_read and not fifo_pci_to_net_empty;\r
- fifo_net_to_pci_valid_read <= fifo_net_to_pci_read and not fifo_net_to_pci_empty;\r
- end if;\r
- end process;\r
\r
- proc_fifo_readwrite : process(BUS_ADDR_IN, bus_read_i, bus_write_i, channel_address)\r
+ proc_fifo_readwrite : process(BUS_ADDR_IN, bus_read_i, channel_address, APL_DATAREADY_IN, fifo_net_to_pci_read)\r
begin\r
+ fifo_net_to_pci_valid_read <= fifo_net_to_pci_read and APL_DATAREADY_IN;\r
fifo_net_to_pci_read <= (others => '0');\r
- fifo_pci_to_net_write <= (others => '0');\r
if BUS_ADDR_IN(11 downto 8) & BUS_ADDR_IN(3 downto 0) = x"23" then\r
fifo_net_to_pci_read(channel_address) <= bus_read_i;\r
end if;\r
- if BUS_ADDR_IN(11 downto 8) & BUS_ADDR_IN(3 downto 0) = x"13" then\r
- fifo_pci_to_net_write(channel_address) <= bus_write_i;\r
- end if;\r
end process;\r
\r
+\r
+ bus_rdat_i <= bus_data_i(31 downto 0);\r
+ bus_ack_i <= (bus_read_i or bus_write_i);\r
+\r
proc_register_cpu_output : process(CLK)\r
begin\r
if rising_edge(CLK) then\r
end if;\r
end process;\r
\r
- process(BUS_ADDR_IN, bus_data_i, fifo_net_to_pci_dout, bus_read_i, bus_write_i, channel_address)\r
- begin\r
- if BUS_ADDR_IN(11 downto 8) & BUS_ADDR_IN(3 downto 0) = x"23" then\r
- bus_rdat_i <= fifo_net_to_pci_dout(channel_address*32+31 downto channel_address*32) & fifo_net_to_pci_dout(channel_address*32+31 downto channel_address*32);\r
- bus_ack_i <= (bus_read_last or bus_write_i);\r
- else\r
- bus_rdat_i <= bus_data_i(31 downto 0) & bus_data_i(31 downto 0);\r
- bus_ack_i <= (bus_read_i or bus_write_i);\r
- end if;\r
- end process;\r
+-- process(BUS_ADDR_IN, bus_data_i, fifo_net_to_pci_dout, bus_read_i, bus_write_i, channel_address)\r
+-- begin\r
+-- if BUS_ADDR_IN(11 downto 8) & BUS_ADDR_IN(3 downto 0) = x"23" then\r
+-- bus_rdat_i <= fifo_net_to_pci_dout(channel_address*32+31 downto channel_address*32);\r
+-- bus_ack_i <= (bus_read_i or bus_write_i);\r
+-- else\r
+\r
+-- end if;\r
+-- end process;\r
+\r
+\r
+--------------------------------\r
+-- fifo as bridge to pci\r
+--------------------------------\r
+\r
+\r
+-- gen_incoming_fifos : for i in 0 to 2**(c_MUX_WIDTH)-1 generate\r
+-- gen_used_fifos : if USE_CHANNELS(i/2) = c_YES generate\r
+-- -- FIFO_NET_TO_PCI: trb_net16_fifo\r
+-- -- generic map(\r
+-- -- USE_VENDOR_CORES => c_YES,\r
+-- -- USE_DATA_COUNT => c_YES,\r
+-- -- DEPTH => 6\r
+-- -- )\r
+-- -- port map(\r
+-- -- CLK => CLK,\r
+-- -- RESET => RESET,\r
+-- -- CLK_EN => '1',\r
+-- -- READ_ENABLE_IN => fifo_net_to_pci_read(i),\r
+-- -- WRITE_ENABLE_IN => fifo_net_to_pci_write(i),\r
+-- -- DATA_IN => fifo_net_to_pci_din(18*i+15 downto 18*i),\r
+-- -- PACKET_NUM_IN => fifo_net_to_pci_din(18*i+17 downto 18*i+16),\r
+-- -- DATA_OUT => fifo_net_to_pci_dout(32*i+15 downto 32*i),\r
+-- -- PACKET_NUM_OUT => fifo_net_to_pci_dout(32*i+17 downto 32*i+16),\r
+-- -- DATA_COUNT_OUT => fifo_net_to_pci_data_count(i)(10 downto 0),\r
+-- -- full_out => fifo_net_to_pci_full(i),\r
+-- -- empty_out => fifo_net_to_pci_empty(i)\r
+-- -- );\r
+--\r
+-- -- FIFO_PCI_TO_NET: trb_net16_fifo\r
+-- -- generic map(\r
+-- -- USE_VENDOR_CORES => c_YES,\r
+-- -- USE_DATA_COUNT => c_YES,\r
+-- -- DEPTH => 6\r
+-- -- )\r
+-- -- port map(\r
+-- -- CLK => CLK,\r
+-- -- RESET => RESET,\r
+-- -- CLK_EN => '1',\r
+-- -- READ_ENABLE_IN => fifo_pci_to_net_read(i),\r
+-- -- WRITE_ENABLE_IN => fifo_pci_to_net_write(i),\r
+-- -- DATA_IN => BUS_WDAT_IN(15 downto 0),\r
+-- -- PACKET_NUM_IN => BUS_WDAT_IN(17 downto 16),\r
+-- -- DATA_OUT => fifo_pci_to_net_dout(18*i+15 downto 18*i),\r
+-- -- PACKET_NUM_OUT => fifo_pci_to_net_dout(18*i+17 downto 18*i+16),\r
+-- -- DATA_COUNT_OUT => fifo_pci_to_net_data_count(i)(10 downto 0),\r
+-- -- full_out => fifo_pci_to_net_full(i),\r
+-- -- empty_out => fifo_pci_to_net_empty(i)\r
+-- -- );\r
+-- end generate;\r
+-- end generate;\r
+\r
+-- proc_valid_read : process(CLK)\r
+-- begin\r
+-- if rising_edge(CLK) then\r
+-- end if;\r
+-- end process;\r
\r
\r
--------------------------------\r
entity trb_net_bridge_pcie_endpoint is
generic(
USE_CHANNELS : channel_config_t := (c_YES,c_YES,c_NO,c_YES);
- AUTO_ANSWER_INCOMING_REQUESTS : channel_config_t := (c_NO,c_NO,c_NO,c_NO)
+ AUTO_ANSWER_INCOMING_REQUESTS : channel_config_t := (c_YES,c_YES,c_YES,c_YES)
);
port(
RESET : in std_logic;
CLK: in std_logic;
BUS_ADDR_IN : in std_logic_vector(31 downto 0);
- BUS_WDAT_IN : in std_logic_vector(63 downto 0);
- BUS_RDAT_OUT : out std_logic_vector(63 downto 0);
- BUS_SEL_IN : in std_logic_vector(7 downto 0);
+ BUS_WDAT_IN : in std_logic_vector(31 downto 0);
+ BUS_RDAT_OUT : out std_logic_vector(31 downto 0);
+ BUS_SEL_IN : in std_logic_vector(3 downto 0);
BUS_WE_IN : in std_logic;
BUS_CYC_IN : in std_logic;
BUS_STB_IN : in std_logic;
signal APL_TARGET_ADDRESS_OUT : std_logic_vector(2**(c_MUX_WIDTH)*16-1 downto 0);
signal APL_ERROR_PATTERN_IN : std_logic_vector(2**(c_MUX_WIDTH)*32-1 downto 0);
signal APL_TARGET_ADDRESS_IN : std_logic_vector(2**(c_MUX_WIDTH)*16-1 downto 0);
+ signal APL_FIFO_COUNT_OUT : std_logic_vector(2**(c_MUX_WIDTH)*11-1 downto 0);
signal APL_MY_ADDRESS_IN : std_logic_vector(15 downto 0);
signal buf_api_stat_fifo_to_int : std_logic_vector(2**(c_MUX_WIDTH)*32-1 downto 0);
APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN,
APL_LENGTH_IN => x"FFFF",
APL_SEQNR_OUT => APL_SEQNR_OUT((2*i+2)*8-1 downto (2*i+1)*8),
+ APL_FIFO_COUNT_OUT => APL_FIFO_COUNT_OUT((2*i+1)*11+10 downto (2*i+1)*11),
-- Internal direction port
INT_MASTER_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY(i),
- INT_MASTER_DATA_OUT => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ INT_MASTER_DATA_OUT => tmp_apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
INT_MASTER_READ_IN => apl_to_buf_INIT_READ(i),
- INT_MASTER_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY(i),
- INT_MASTER_DATA_IN => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_MASTER_PACKET_NUM_IN => buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_MASTER_READ_OUT => buf_to_apl_REPLY_READ(i),
+ INT_MASTER_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i),
+ INT_MASTER_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ INT_MASTER_PACKET_NUM_IN => buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+ INT_MASTER_READ_OUT => buf_to_apl_INIT_READ(i),
INT_SLAVE_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i),
INT_SLAVE_DATA_OUT => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
INT_SLAVE_READ_IN => apl_to_buf_REPLY_READ(i),
- INT_SLAVE_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i),
- INT_SLAVE_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_SLAVE_READ_OUT => buf_to_apl_INIT_READ(i),
- CTRL_SEQNR_RESET => '0',
+ INT_SLAVE_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY(i),
+ INT_SLAVE_DATA_IN => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ INT_SLAVE_PACKET_NUM_IN => buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+ INT_SLAVE_READ_OUT => buf_to_apl_REPLY_READ(i),
+ CTRL_SEQNR_RESET => '0',
-- Status and control port
STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int((2*i+2)*32-1 downto (2*i+1)*32),
STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl((2*i+2)*32-1 downto (2*i+1)*32)
+ APL_READ_OUT(2*i) <= '0';
+ APL_DATAREADY_OUT(2*i) <= '0';
+ APL_RUN_OUT(2*i) <= '0';
+ APL_SEQNR_OUT(2*i*8+7 downto 2*i*8) <= (others => '0');
+ APL_DATA_OUT(2*i*c_DATA_WIDTH+15 downto 2*i*c_DATA_WIDTH) <= (others => '0');
+ APL_PACKET_NUM_OUT(2*i*c_NUM_WIDTH+2 downto 2*i*c_NUM_WIDTH) <= (others => '0');
+ APL_TYP_OUT(2*i*3+2 downto 2*i*3) <= (others => '0');
+ APL_FIFO_COUNT_OUT(2*i*11+10 downto 2*i*11) <= (others => '0');
+ buf_api_stat_fifo_to_int(2*i*32+31 downto 2*i*32) <= (others => '0');
+ buf_api_stat_fifo_to_apl(2*i*32+31 downto 2*i*32) <= (others => '0');
+
+
end generate;
end generate;
gen_no_api : if USE_CHANNELS(i) = c_NO generate
APL_READ_OUT(2*i+1) <= '1';
- APL_DATA_OUT((2*i+2)*c_DATA_WIDTH-1 downto (2*i+1)*c_DATA_WIDTH) <= (others => '0');
- APL_PACKET_NUM_OUT((2*i+2)*c_NUM_WIDTH-1 downto (2*i+1)*c_NUM_WIDTH) <= (others => '0');
- APL_TYP_OUT((2*i+2)*3-1 downto (2*i+1)*3) <= (others => '0');
+ APL_READ_OUT(2*i) <= '1';
+ APL_DATA_OUT((2*i+2)*c_DATA_WIDTH-1 downto (2*i)*c_DATA_WIDTH) <= (others => '0');
+ APL_PACKET_NUM_OUT((2*i+2)*c_NUM_WIDTH-1 downto (2*i)*c_NUM_WIDTH) <= (others => '0');
+ APL_TYP_OUT((2*i+2)*3-1 downto (2*i)*3) <= (others => '0');
APL_DATAREADY_OUT(2*i+1) <= '0';
+ APL_DATAREADY_OUT(2*i) <= '0';
APL_RUN_OUT(2*i+1) <= '0';
- APL_SEQNR_OUT((2*i+2)*8-1 downto (2*i+1)*8) <= (others => '0');
- buf_api_stat_fifo_to_int((2*i+2)*32-1 downto (2*i+1)*32) <= (others => '0');
- buf_api_stat_fifo_to_apl((2*i+2)*32-1 downto (2*i+1)*32) <= (others => '0');
+ APL_RUN_OUT(2*i) <= '0';
+ APL_SEQNR_OUT((2*i+2)*8-1 downto (2*i)*8) <= (others => '0');
+ buf_api_stat_fifo_to_int((2*i+2)*32-1 downto (2*i)*32) <= (others => '0');
+ buf_api_stat_fifo_to_apl((2*i+2)*32-1 downto (2*i)*32) <= (others => '0');
+ tmp_apl_to_buf_init_data(i*16+15 downto i*16) <= (others => '0');
+ APL_FIFO_COUNT_OUT(2*i*11+21 downto 2*i*11) <= (others => '0');
end generate;
end generate;
APL : trb_net_bridge_pcie_apl
+ generic map(
+ USE_CHANNELS => USE_CHANNELS
+ )
port map(
CLK => CLK,
RESET => RESET_i,
APL_RUN_IN => APL_RUN_OUT,
APL_SEQNR_IN => APL_SEQNR_OUT,
APL_TARGET_ADDRESS_OUT => APL_TARGET_ADDRESS_IN,
+ APL_FIFO_COUNT_IN => APL_FIFO_COUNT_OUT,
EXT_TRIGGER_INFO => reg_extended_trigger_information,
BUS_ADDR_IN => BUS_ADDR_IN,
BUS_WDAT_IN => BUS_WDAT_IN,