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\7fCD
\ No newline at end of file
--- /dev/null
+--------------------------------------------------------------------------------
+-- This file is owned and controlled by Xilinx and must be used --
+-- solely for design, simulation, implementation and creation of --
+-- design files limited to Xilinx devices or technologies. Use --
+-- with non-Xilinx devices or technologies is expressly prohibited --
+-- and immediately terminates your license. --
+-- --
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
+-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
+-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
+-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
+-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
+-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
+-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
+-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
+-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
+-- FOR A PARTICULAR PURPOSE. --
+-- --
+-- Xilinx products are not intended for use in life support --
+-- appliances, devices, or systems. Use in such applications are --
+-- expressly prohibited. --
+-- --
+-- (c) Copyright 1995-2007 Xilinx, Inc. --
+-- All rights reserved. --
+--------------------------------------------------------------------------------
+-- You must compile the wrapper file bit_fifo.vhd when simulating
+-- the core, bit_fifo. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
+-- The synthesis directives "translate_off/translate_on" specified
+-- below are supported by Xilinx, Mentor Graphics and Synplicity
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+-- synthesis translate_off
+Library XilinxCoreLib;
+-- synthesis translate_on
+ENTITY bit_fifo IS
+ port (
+ clk: IN std_logic;
+ din: IN std_logic_VECTOR(0 downto 0);
+ rd_en: IN std_logic;
+ rst: IN std_logic;
+ wr_en: IN std_logic;
+ data_count: OUT std_logic_VECTOR(6 downto 0);
+ dout: OUT std_logic_VECTOR(0 downto 0);
+ empty: OUT std_logic;
+ full: OUT std_logic);
+END bit_fifo;
+
+ARCHITECTURE bit_fifo_a OF bit_fifo IS
+-- synthesis translate_off
+component wrapped_bit_fifo
+ port (
+ clk: IN std_logic;
+ din: IN std_logic_VECTOR(0 downto 0);
+ rd_en: IN std_logic;
+ rst: IN std_logic;
+ wr_en: IN std_logic;
+ data_count: OUT std_logic_VECTOR(6 downto 0);
+ dout: OUT std_logic_VECTOR(0 downto 0);
+ empty: OUT std_logic;
+ full: OUT std_logic);
+end component;
+
+-- Configuration specification
+ for all : wrapped_bit_fifo use entity XilinxCoreLib.fifo_generator_v3_3(behavioral)
+ generic map(
+ c_rd_freq => 100,
+ c_wr_response_latency => 1,
+ c_has_srst => 0,
+ c_has_rd_data_count => 0,
+ c_din_width => 1,
+ c_has_wr_data_count => 0,
+ c_implementation_type => 0,
+ c_family => "virtex4",
+ c_has_wr_rst => 0,
+ c_wr_freq => 100,
+ c_underflow_low => 0,
+ c_has_meminit_file => 0,
+ c_has_overflow => 0,
+ c_preload_latency => 1,
+ c_dout_width => 1,
+ c_rd_depth => 128,
+ c_default_value => "BlankString",
+ c_mif_file_name => "BlankString",
+ c_has_underflow => 0,
+ c_has_rd_rst => 0,
+ c_has_almost_full => 0,
+ c_has_rst => 1,
+ c_data_count_width => 7,
+ c_has_wr_ack => 0,
+ c_use_ecc => 0,
+ c_wr_ack_low => 0,
+ c_common_clock => 1,
+ c_rd_pntr_width => 7,
+ c_has_almost_empty => 0,
+ c_rd_data_count_width => 7,
+ c_enable_rlocs => 0,
+ c_wr_pntr_width => 7,
+ c_overflow_low => 0,
+ c_prog_empty_type => 0,
+ c_optimization_mode => 0,
+ c_wr_data_count_width => 7,
+ c_preload_regs => 0,
+ c_dout_rst_val => "0",
+ c_has_data_count => 1,
+ c_prog_full_thresh_negate_val => 125,
+ c_wr_depth => 128,
+ c_prog_empty_thresh_negate_val => 3,
+ c_prog_empty_thresh_assert_val => 2,
+ c_has_valid => 0,
+ c_init_wr_pntr_val => 0,
+ c_prog_full_thresh_assert_val => 126,
+ c_use_fifo16_flags => 0,
+ c_has_backup => 0,
+ c_valid_low => 0,
+ c_prim_fifo_type => "4kx4",
+ c_count_type => 0,
+ c_prog_full_type => 0,
+ c_memory_type => 1);
+-- synthesis translate_on
+BEGIN
+-- synthesis translate_off
+U0 : wrapped_bit_fifo
+ port map (
+ clk => clk,
+ din => din,
+ rd_en => rd_en,
+ rst => rst,
+ wr_en => wr_en,
+ data_count => data_count,
+ dout => dout,
+ empty => empty,
+ full => full);
+-- synthesis translate_on
+
+END bit_fifo_a;
+
--- /dev/null
+#!/usr/bin/perl
+###########################################
+# Script file to run the flow
+#
+###########################################
+#
+# Command line for synplify_pro
+#
+
+
+use FileHandle;
+
+
+$ENV{LM_LICENSE_FILE}="1709\@hadeb05";
+
+
+
+$PLD_DEVICE="xc4vlx40-10-ff1148";
+$TOPNAME="trb_v2b_fpga";
+
+
+
+#set -e
+#set -o errexit
+
+system("env| grep LM_");
+
+#$c="/opt/Synplicity/fpga_861/bin/synplify_pro -batch $TOPNAME"."_syn.prj";
+#$c="/opt/Synplicity/fpga_8804/bin/synplify_pro -batch $TOPNAME"."_syn.prj";
+$c="/opt/Synplicity/fpga_89/bin/synplify_pro -disable_rainbow_dongle -batch $TOPNAME"."_syn.prj";
+#$c=("( netcat -w2 -l -u -p 6001 < data_for_synbatch_6001.raw >/dev/null 2>&1)& /opt/Synplicity/fpga_89/bin/synplify_pro -batch $TOPNAME"."_syn.prj");
+$r=execute($c, "do_not_exit" );
+
+
+chdir "workdir";
+my $fh = new FileHandle("<trb_v2b_fpga.srr");
+my @a = <$fh>;
+$fh -> close;
+
+#if ($r) {
+#$c="cat $TOPNAME.srr";
+#system($c);
+#exit 129;
+#}
+
+foreach (@a)
+{
+ if(/\@E:/)
+ {
+ $c="cat $TOPNAME.srr";
+ system($c);
+ print "bdabdhsadbhjasdhasldhbas";
+ exit 129;
+ }
+}
+#
+# Command line to synthesize
+#
+
+#chdir "..";
+#$c="xst -intstyle xflow -ifn $TOPNAME.xst -ofn $TOPNAME.syr";
+#execute($c);
+#chdir "workdir";
+
+#
+# Command line for ngdbuild
+#
+#$c="ngdbuild -p $PLD_DEVICE -nt timestamp -intstyle xflow -uc ../$TOPNAME.ucf ../$TOPNAME.ngc $TOPNAME.ngd";
+$c="ngdbuild -p $PLD_DEVICE -nt timestamp -intstyle xflow -uc ../$TOPNAME.ucf -sd ../ $TOPNAME.edf $TOPNAME.ngd";
+execute($c);
+#
+# Command line for fpgafit
+#
+$c="map -detail -u -p $PLD_DEVICE -cm speed -pr b -k 4 -c 100 -tx off -intstyle xflow -o $TOPNAME"."_map.ncd $TOPNAME.ngd $TOPNAME.pcf";
+execute($c);
+
+#
+# Command line for Place & Route
+#
+
+$c="par -w -intstyle xflow -ol std -t 1 $TOPNAME"."_map.ncd $TOPNAME.ncd $TOPNAME.pcf";
+execute($c);
+
+#
+# Command line for genarate programming file (.bit)
+#
+
+
+foreach (<$TOPNAME"."_pad.txt>) {
+ @a=split (/\s*\|\s*/,$_);
+ if( ($a[2] ne "" &&
+ $a[2] ne "Signal Name") &&
+ $a[13] ne "LOCATED"
+ )
+ {
+ print "error, pins were assigned automatically:\n$_\n";
+ exit;
+ }
+}
+
+print "_pad.txt tested for automatically assigned pins\n";
+
+#$c="bitgen -w -intstyle ise -g DebugBitstream:No -g Binary:no -g Gclkdel0:11111 -g Gclkdel1:11111 -g Gclkdel2:11111 -g Gclkdel3:11111 -g ConfigRate:4 -g CclkPin:PullUp -g M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g DonePin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GSR_cycle:6 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No $TOPNAME";
+$c="bitgen -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g ConfigRate:4 -g CclkPin:PullUp -g M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g DonePin:PullUp -g InitPin:Pullup -g CsPin:Pullup -g DinPin:Pullup -g BusyPin:Pullup -g RdWrPin:Pullup -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g DCMShutdown:Disable -g DisableBandgap:No -g DCIUpdateMode:AsRequired -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No -g Encrypt:No $TOPNAME.ncd";
+
+execute($c);
+#
+# Command line for generate .stapl file
+#
+
+$c="XIL_IMPACT_ENV_LPT_COMPATIBILITY_MODE=true impact -batch ../impact_batch_b.txt";
+
+execute($c);
+
+
+#ssh depc152 'cd ~/files/vhdl/xilinx; . ~/bin/xilinx_setup; XIL_IMPACT_ENV_LPT_COMPATIBILITY_MODE=true impact -batch conf_xilinx_impact.txt '
+
+#
+#to download file on ETRAX chip
+#
+
+#$c="lftp root:pass@hades18;put RPCBoardContrller;exit";
+#execute($c)
+
+chdir "..";
+
+sub execute {
+ my ($c, $op) = @_;
+ #print "option: $op \n";
+
+ print "\n\ncommand to execute: $c \n";
+ $r=system($c);
+ if($r) {
+ print "$!";
+ if($op ne "do_not_exit") {
+ exit;
+ }
+ }
+
+ return $r;
+
+}
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.all;
+library ieee;
+library work;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.all;
+
+entity ctu is
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ LVL1_TRIGG: in std_logic_vector(7 downto 0);
+ LVL1_START: out std_logic;
+ LVL1_TAG : out std_logic_vector(7 downto 0);
+ LVL1_CODE : out std_logic_vector(3 downto 0);
+ LVL1_BUSY : in std_logic;
+ LVL2_TRIGG: in std_logic_vector(1 downto 0);
+ LVL2_START: out std_logic_vector(1 downto 0);
+ LVL2_TAG : out std_logic_vector(7 downto 0);
+ LVL2_BUSY : in std_logic;
+ LVL2_DOWNSCALING : in std_logic_vector(7 downto 0);
+ CTU_CONTROL: in std_logic_vector(31 downto 0);
+ LVL1_CTU_STATUS : out std_logic_vector(31 downto 0);
+ LVL2_CTU_STATUS : out std_logic_vector(31 downto 0)
+ );
+end ctu;
+architecture ctu of ctu is
+ component edge_to_pulse
+ port (
+ clock : in std_logic;
+ en_clk : in std_logic;
+ signal_in : in std_logic;
+ pulse : out std_logic);
+ end component;
+ component bit_fifo
+ port (
+ clk : IN std_logic;
+ din : IN std_logic_VECTOR(0 downto 0);
+ rd_en : IN std_logic;
+ rst : IN std_logic;
+ wr_en : IN std_logic;
+ data_count: OUT std_logic_VECTOR(6 downto 0);
+ dout : OUT std_logic_VECTOR(0 downto 0);
+ empty : OUT std_logic;
+ full : OUT std_logic);
+ end component;
+ signal lvl1_trigger_pulse : std_logic_vector(7 downto 0);
+ signal lvl1_trigger_tag : std_logic_vector(7 downto 0);
+ signal lvl1_code_i : std_logic_vector(3 downto 0);
+ signal lvl1_debug_fsm : std_logic_vector(1 downto 0);
+ signal lvl1_trigger_i : std_logic;
+ signal start_trigger_enable : std_logic;
+ signal lvl2_pulser : std_logic;
+ signal lvl2_pulser_trigger : std_logic;
+ signal lvl2_pulser_trigger_i : std_logic;
+ signal lvl2_trigger_i : std_logic;
+ signal lvl2_debug_fsm : std_logic_vector(1 downto 0);
+ signal counter_for_downscaling : std_logic_vector(7 downto 0);
+ type send_lvl2_trigger is (IDLE, SEND_TRIGGER, READ_FIFO, WAIT_FOR_BUSY_1, WAIT_FOR_BUSY_2);
+signal current_state_send_lvl2_trigger, next_state_send_lvl2_trigger : send_lvl2_trigger;
+ type send_lvl1_trigger is (IDLE, SEND_TRIGGER, WAIT_FOR_BUSY_1, WAIT_FOR_BUSY_2);
+signal current_state_send_lvl1_trigger, next_state_send_lvl1_trigger : send_lvl1_trigger;
+ signal data_valid : std_logic_vector(0 downto 0);
+ signal data_valid_out : std_logic_vector(0 downto 0);
+
+ signal fifo_rd_en : std_logic;
+ signal eneble_write_to_fifo : std_logic;
+ signal fifo_empty : std_logic;
+ signal fifo_full : std_logic;
+ signal fifo_counter : std_logic_vector(6 downto 0);
+ signal lvl2_ctu_busy : std_logic;
+ signal not_lvl2_busy : std_logic;
+ signal lvl2_tag_counter : std_logic_vector(7 downto 0);
+
+begin
+ LVL1_TRIGGER_PULSE_0 : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => LVL1_TRIGG(0),
+ pulse => lvl1_trigger_pulse(0));
+ LVL1_TRIGGER_PULSE_1 : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => LVL1_TRIGG(1),
+ pulse => lvl1_trigger_pulse(1));
+ LVL1_TRIGGER_PULSE_2 : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => LVL1_TRIGG(2),
+ pulse => lvl1_trigger_pulse(2));
+ LVL1_TRIGGER_PULSE_3 : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => LVL1_TRIGG(3),
+ pulse => lvl1_trigger_pulse(3));
+ LVL1_TRIGGER_PULSE_4 : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => LVL1_TRIGG(4),
+ pulse => lvl1_trigger_pulse(4));
+ LVL1_TRIGGER_PULSE_5 : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => LVL1_TRIGG(5),
+ pulse => lvl1_trigger_pulse(5));
+ LVL1_TRIGGER_PULSE_6 : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => LVL1_TRIGG(6),
+ pulse => lvl1_trigger_pulse(6));
+ LVL1_TRIGGER_PULSE_7 : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => LVL1_TRIGG(7),
+ pulse => lvl1_trigger_pulse(7));
+-------------------------------------------------------------------------------
+-- LVL1
+-------------------------------------------------------------------------------
+LVL1_TAG_COUNT: process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ lvl1_trigger_tag <= x"fe";--(others => '0');
+ elsif lvl1_trigger_pulse /= x"00" and current_state_send_lvl1_trigger = IDLE and CTU_CONTROL(0) = '1' and lvl2_ctu_busy = '0' and LVL1_BUSY = '0' then
+ lvl1_trigger_tag <= lvl1_trigger_tag + 1;
+ else
+ lvl1_trigger_tag <= lvl1_trigger_tag;
+ end if;
+ end if;
+ end process LVL1_TAG_COUNT;
+ START_TRIGGER: process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ start_trigger_enable <= '1';
+ elsif current_state_send_lvl1_trigger = WAIT_FOR_BUSY_2 then
+ start_trigger_enable <= '0';
+ else
+ start_trigger_enable <= start_trigger_enable;
+ end if;
+ end if;
+ end process START_TRIGGER;
+
+ LVL1_CODE_SET: process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' or start_trigger_enable = '1'then
+ lvl1_code_i <= x"d";
+ elsif lvl1_trigger_pulse(0) = '1' and current_state_send_lvl1_trigger = IDLE and LVL1_BUSY = '0' then
+ lvl1_code_i <= x"1";
+ elsif lvl1_trigger_pulse(1) = '1' and current_state_send_lvl1_trigger = IDLE and LVL1_BUSY = '0' then
+ lvl1_code_i <= x"2";
+ elsif lvl1_trigger_pulse(2) = '1' and current_state_send_lvl1_trigger = IDLE and LVL1_BUSY = '0' then
+ lvl1_code_i <= x"3";
+ elsif lvl1_trigger_pulse(3) = '1' and current_state_send_lvl1_trigger = IDLE and LVL1_BUSY = '0' then
+ lvl1_code_i <= x"4";
+ elsif lvl1_trigger_pulse(4) = '1' and current_state_send_lvl1_trigger = IDLE and LVL1_BUSY = '0' then
+ lvl1_code_i <= x"5";
+ else
+ lvl1_code_i <= lvl1_code_i;
+ end if;
+ end if;
+ end process LVL1_CODE_SET;
+
+ SEND_LVL1_TRIGGER_FSM : process (CLK,RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ current_state_send_lvl1_trigger <= IDLE;
+ else
+ current_state_send_lvl1_trigger <= next_state_send_lvl1_trigger;
+ end if;
+ end if;
+ end process SEND_LVL1_TRIGGER_FSM;
+
+ SEND_LVL1_TRIGGER_PROC: process (LVL1_BUSY,CLK,lvl1_trigger_pulse)
+ begin
+ case current_state_send_lvl1_trigger is
+ when IDLE =>
+ lvl1_debug_fsm <= "00";
+ lvl1_trigger_i <= '0';
+ if lvl1_trigger_pulse /= x"00" and CTU_CONTROL(0) = '1' and LVL1_BUSY = '0' and lvl2_ctu_busy = '0' then
+ next_state_send_lvl1_trigger <= SEND_TRIGGER;
+ else
+ next_state_send_lvl1_trigger <= IDLE;
+ end if;
+ when SEND_TRIGGER =>
+ lvl1_debug_fsm <= "01";
+ lvl1_trigger_i <= '1';
+ next_state_send_lvl1_trigger <= WAIT_FOR_BUSY_1;
+ when WAIT_FOR_BUSY_1 =>
+ lvl1_debug_fsm <= "10";
+ lvl1_trigger_i <= '0';
+ next_state_send_lvl1_trigger <= WAIT_FOR_BUSY_2;
+ when WAIT_FOR_BUSY_2 =>
+ lvl1_debug_fsm <= "11";
+ lvl1_trigger_i <= '0';
+ if LVL1_BUSY ='1' then
+ next_state_send_lvl1_trigger <= WAIT_FOR_BUSY_2;
+ else
+ next_state_send_lvl1_trigger <= IDLE;
+ end if;
+ when others =>
+ next_state_send_lvl1_trigger <= IDLE;
+ end case;
+ end process SEND_LVL1_TRIGGER_PROC;
+
+ LVL1_START <= lvl1_trigger_i;
+ LVL1_TAG <= lvl1_trigger_tag;
+ LVL1_CODE <= lvl1_code_i;
+ LVL1_CTU_STATUS <= x"aaa" & '0' & CTU_CONTROL(3 downto 0)& lvl1_debug_fsm & LVL1_BUSY & lvl1_code_i & lvl1_trigger_tag;
+ -----------------------------------------------------------------------------
+ -- LVL2
+ -----------------------------------------------------------------------------
+ --downscaling
+ lvl2_pulser <= not LVL1_BUSY;
+ LVL2_TRIGGER_PULSER : edge_to_pulse --when external generator is used
+ port map (
+ clock => CLK,
+ en_clk => '1', --enable/disable generator
+ signal_in => lvl2_pulser,
+ pulse => lvl2_pulser_trigger_i);
+ lvl2_pulser_trigger <= lvl2_pulser_trigger_i and CTU_CONTROL(4);
+
+ DOWNSCALING_COUNTER: process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' or counter_for_downscaling = x"00" then --LVL2_DOWNSCALING then
+ counter_for_downscaling <= (others => '0');
+ elsif lvl2_pulser_trigger = '1' or LVL2_TRIGG(0) = '1' then
+ counter_for_downscaling <= counter_for_downscaling + 1;
+ else
+ counter_for_downscaling <= counter_for_downscaling;
+ end if;
+ end if;
+ end process DOWNSCALING_COUNTER;
+
+ --from MU
+ SYNCH_VALID_AND_WRITE: process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ eneble_write_to_fifo <= '0';
+ data_valid(0) <= '0';
+ elsif counter_for_downscaling = x"00" then
+
+ eneble_write_to_fifo <= lvl2_pulser_trigger or LVL2_TRIGG(0);
+ data_valid(0) <= LVL2_TRIGG(1);-- or CTU_CONTROL(4);
+ else
+ eneble_write_to_fifo <= lvl2_pulser_trigger or LVL2_TRIGG(0);
+ data_valid(0) <= '1';
+ end if;
+ end if;
+ end process SYNCH_VALID_AND_WRITE;
+ not_lvl2_busy <= not LVL2_BUSY;
+-- LVL2_FIFO_UP : edge_to_pulse
+-- port map (
+-- clock => CLK,
+-- en_clk => '1',
+-- signal_in => not_lvl2_busy,
+-- pulse => fifo_rd_en); --next data from fifo
+ BIT_FIFO_FOR_LVL2: bit_fifo
+ port map (
+ clk => CLK,
+ din => data_valid,
+ rd_en => fifo_rd_en,
+ rst => RESET,
+ wr_en => eneble_write_to_fifo,
+ data_count => fifo_counter,
+ dout => data_valid_out,
+ empty => fifo_empty,
+ full => fifo_full);
+ LVL2_START(1) <= data_valid_out(0);
+ lvl2_ctu_busy <= '1' when fifo_counter > "0111111" else '0';
+ LVL2_TAG_CHECK: process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ lvl2_tag_counter <= (others => '0');
+ elsif lvl2_trigger_i = '1' then
+ lvl2_tag_counter <= lvl2_tag_counter + 1;
+ else
+ lvl2_tag_counter <= lvl2_tag_counter;
+ end if;
+ end if;
+ end process LVL2_TAG_CHECK;
+
+ SEND_LVL2_TRIGGER_FSM : process (CLK,RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ current_state_send_lvl2_trigger <= IDLE;
+ else
+ current_state_send_lvl2_trigger <= next_state_send_lvl2_trigger;
+ end if;
+ end if;
+ end process SEND_LVL2_TRIGGER_FSM;
+
+ SEND_LVL2_TRIGGER_PROC: process (fifo_empty,CLK,LVL2_BUSY)
+ begin
+ case current_state_send_lvl2_trigger is
+ when IDLE =>
+ lvl2_debug_fsm <= "00";
+ lvl2_trigger_i <= '0';
+ fifo_rd_en <= '0';
+ if fifo_empty = '0' and LVL2_BUSY = '0' then
+ next_state_send_lvl2_trigger <= READ_FIFO;
+ else
+ next_state_send_lvl2_trigger <= IDLE;
+ end if;
+ when READ_FIFO =>
+ lvl2_debug_fsm <= "00";
+ lvl2_trigger_i <= '0';
+ fifo_rd_en <= '1';
+ next_state_send_lvl2_trigger <= SEND_TRIGGER;
+ when SEND_TRIGGER =>
+ lvl2_debug_fsm <= "01";
+ lvl2_trigger_i <= '1';
+ fifo_rd_en <= '0';
+ next_state_send_lvl2_trigger <= WAIT_FOR_BUSY_1;
+ when WAIT_FOR_BUSY_1 =>
+ lvl2_debug_fsm <= "10";
+ lvl2_trigger_i <= '0';
+ fifo_rd_en <= '0';
+ next_state_send_lvl2_trigger <= WAIT_FOR_BUSY_2;
+ when WAIT_FOR_BUSY_2 =>
+ lvl2_debug_fsm <= "11";
+ lvl2_trigger_i <= '0';
+ if LVL2_BUSY ='0' then
+ next_state_send_lvl2_trigger <= IDLE;
+ else
+ next_state_send_lvl2_trigger <= WAIT_FOR_BUSY_2;
+ end if;
+ when others =>
+ next_state_send_lvl2_trigger <= IDLE;
+ end case;
+ end process SEND_LVL2_TRIGGER_PROC;
+ LVL2_TAG <= lvl2_tag_counter;
+ LVL2_START(0) <= lvl2_trigger_i;
+ LVL2_CTU_STATUS <= "00" & lvl2_tag_counter & counter_for_downscaling( 7 downto 0) & lvl2_ctu_busy & fifo_empty & fifo_full & fifo_counter & CTU_CONTROL(7 downto 4);
+end ctu;
+-- po resecie wprowadzic w idle - linia bms - juz jest week pull up
+-- sli to nie pomoze moze trzeba sprawdzic(8ustawic) busylock ?raczej nie bo
+-- tojest output
+-- jak powiedzeic ze host jest masterem ?
+-- moze boff pomoze ?
+-- obserwowac msh, ms1-0
+-- sprobowac brst
+-- sprawdzic br0-7 bus request from others dsps
+-- TMR0E - powinno pulsowac chyba
+-- hme in syscon mowi o szerokosci szyny ?
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
signal reg_address_dsp, next_address_dsp : std_logic_vector(31 downto 0);
signal reg_write_dsp_data, next_write_dsp_data : std_logic_vector(31 downto 0);
signal reg_read_dsp_data, next_read_dsp_data : std_logic_vector(31 downto 0);
-
-
-begin -- behavioural
-
+begin
DEBUGSTATE_MACHINE(2 downto 0) <= debug_register;
-
-
-
REGISTER_ADDR_DATA_MODE : process (CLK) --in this way the reset is syn with the
--incoming clock
begin
begin
--!!default vaue!!that i can change in
--another state, they are default for all the machine
-
---INOUT
- DSP_DATA_OUT <= (others => 'Z');
- -- INTERNAL_DATA <= (others => 'Z');
- WRH <= 'Z';
- WRL <= 'Z'; --in for virtex to read dsp(it's out =0 if I
- --write into dsp)
+--IN
+ DSP_DATA_OUT <= (others => 'Z');
+ WRH <= 'Z';
+ WRL <= 'Z'; --in for virtex to read dsp(it's out =0 if I
+ --write into dsp)
--OUT
- HBR_OUT <= '1';
- ADDRESS_DSP <= (others => 'Z');
- VALID_DATA_SENT <= '0';
- RD_OUT <= 'Z';
- debug_register <= "000";
- BRST <= 'Z';
--- BRST <= '1'; --write in main entity TLD !!!!
-
- next_read_dsp_data <= reg_read_dsp_data;
- next_address_dsp <= reg_address_dsp;
- next_write_dsp_data <= reg_write_dsp_data;
- next_state <= IDLE;
-
-
- case current_state is
- when IDLE =>
- debug_register <= "000";
- HBR_OUT <= '1';
- if TRIGGER = '1' and R_W_ENABLE = '1' then --read when high
- next_address_dsp <= INTERNAL_ADDRESS;
- next_state <= READ_DSP_WAIT_FOR_HBR;
- elsif TRIGGER = '1' and R_W_ENABLE = '0'then --write into the dsp bus
- next_state <= WRITE_DSP_WAIT_FOR_HBR;
- next_address_dsp <= INTERNAL_ADDRESS;
- next_write_dsp_data <= INTERNAL_DATA_IN;
- else
- next_state <= IDLE;
- end if;
-
- when READ_DSP_WAIT_FOR_HBR =>
- debug_register <= "001";
- HBR_OUT <= '0';
- if HBG_IN = '0' then
- next_state <= READ_DSP_MEMORY_NEXT;
- else
- next_state <= READ_DSP_WAIT_FOR_HBR;
- end if;
-
- when READ_DSP_MEMORY_NEXT =>
- debug_register <= "010";
- ADDRESS_DSP <= reg_address_dsp;
--- DSP_DATA_OUT <= (others => x"a5a5a5a5");
- DSP_DATA_OUT <= (others => 'Z');
- RD_OUT <= '0';
- WRL <= '1';
- WRH <= '1';
- HBR_OUT <= '0';
- BRST <= '1';
- -- next_state <= READ_DSP_WAIT1;
- next_state <= READ_DSP_DUMMY;
-
- when READ_DSP_DUMMY =>
- debug_register <= "010";
- ADDRESS_DSP <= reg_address_dsp;
- DSP_DATA_OUT <= (others => 'Z');
- RD_OUT <= '0';
- WRL <= '1';
- WRH <= '1';
- HBR_OUT <= '0';
- BRST <= '1';
- next_state <= READ_DSP_WAIT1;
-
- when READ_DSP_WAIT1 =>
- debug_register <= "011";
- next_state <= READ_DSP_WAIT2;
- RD_OUT <= '1';
- WRL <= '1';
- WRH <= '1';
- HBR_OUT <= '0';
- BRST <= '1';
-
- when READ_DSP_WAIT2 =>
- debug_register <= "100";
- next_state <= READ_DSP_WAIT3;
- RD_OUT <= '1';
- WRL <= '1';
- WRH <= '1';
- HBR_OUT <= '0';
- BRST <= '1';
-
- when READ_DSP_WAIT3 =>
- debug_register <= "101";
- next_state <= READ_DSP_WAIT4;
- RD_OUT <= '1';
- WRL <= '1';
- WRH <= '1';
- HBR_OUT <= '0';
- BRST <= '1';
-
- when READ_DSP_WAIT4 =>
- debug_register <= "101";
- next_state <= READ_DSP_MEMORY;
- RD_OUT <= '1';
- WRL <= '1';
- WRH <= '1';
- HBR_OUT <= '0';
- BRST <= '1';
-
- when READ_DSP_MEMORY =>
- debug_register <= "110";
- RD_OUT <= '1';
- WRL <= '1';
- WRH <= '1';
- HBR_OUT <= '0';
- BRST <= '1';
- if ACK = '0' then
- next_state <= READ_DSP_MEMORY;
+ HBR_OUT <= '1';
+ ADDRESS_DSP <= (others => 'Z');
+ VALID_DATA_SENT <= '0';
+ RD_OUT <= 'Z';
+ debug_register <= "000";
+ BRST <= 'Z';
+ next_read_dsp_data <= reg_read_dsp_data;
+ next_address_dsp <= reg_address_dsp;
+ -- next_write_dsp_data <= reg_write_dsp_data;
+ next_state <= IDLE;
+ case current_state is
+ when IDLE =>
+ VALID_DATA_SENT <= '0';
+ debug_register <= "000";
+ ADDRESS_DSP <= (others => 'Z');
+ DSP_DATA_OUT <= (others => 'Z');
+ RD_OUT <= 'Z';
+ WRL <= 'Z';
+ WRH <= 'Z';
+ HBR_OUT <= '1';
+ BRST <= '1';
+ if TRIGGER = '1' and R_W_ENABLE = '1' then --read when high
+ next_address_dsp <= INTERNAL_ADDRESS;
+ next_state <= READ_DSP_WAIT_FOR_HBR;
+ elsif TRIGGER = '1' and R_W_ENABLE = '0'then --write into the dsp bus
+ next_state <= WRITE_DSP_WAIT_FOR_HBR;
+ next_address_dsp <= INTERNAL_ADDRESS;
+ next_write_dsp_data <= INTERNAL_DATA_IN;
+ else
+ next_state <= IDLE;
+ end if;
+ when READ_DSP_WAIT_FOR_HBR =>
+ debug_register <= "001";
+ HBR_OUT <= '0';
+ if HBG_IN = '0' then
+ next_state <= READ_DSP_MEMORY_NEXT;
else
- next_state <= SENT_DATA_TO_INTERNAL_ENTITY;
- next_read_dsp_data <= DSP_DATA_IN;
+ next_state <= READ_DSP_WAIT_FOR_HBR;
end if;
-
-
- when SENT_DATA_TO_INTERNAL_ENTITY =>
- debug_register <= "111";
- VALID_DATA_SENT <= '1';
- INTERNAL_DATA_OUT <= reg_read_dsp_data;
- next_state <= IDLE;
-
+ when READ_DSP_MEMORY_NEXT =>
+ debug_register <= "010";
+ ADDRESS_DSP <= reg_address_dsp;
+ DSP_DATA_OUT <= (others => 'Z');
+ RD_OUT <= '0';
+ WRL <= '1';
+ WRH <= '1';
+ HBR_OUT <= '0';
+ BRST <= '1';
+ next_state <= READ_DSP_DUMMY;
+ when READ_DSP_DUMMY =>
+ debug_register <= "010";
+ ADDRESS_DSP <= reg_address_dsp;
+ DSP_DATA_OUT <= (others => 'Z');
+ RD_OUT <= '0';
+ WRL <= '1';
+ WRH <= '1';
+ HBR_OUT <= '0';
+ BRST <= '1';
+ next_state <= READ_DSP_WAIT1;
+ when READ_DSP_WAIT1 =>
+ debug_register <= "011";
+ next_state <= READ_DSP_WAIT2;
+ RD_OUT <= '1';
+ WRL <= '1';
+ WRH <= '1';
+ HBR_OUT <= '0';
+ BRST <= '1';
+ when READ_DSP_WAIT2 =>
+ debug_register <= "100";
+ next_state <= READ_DSP_WAIT3;
+ RD_OUT <= '1';
+ WRL <= '1';
+ WRH <= '1';
+ HBR_OUT <= '0';
+ BRST <= '1';
+ when READ_DSP_WAIT3 =>
+ debug_register <= "101";
+ next_state <= READ_DSP_WAIT4;
+ RD_OUT <= '1';
+ WRL <= '1';
+ WRH <= '1';
+ HBR_OUT <= '0';
+ BRST <= '1';
+ when READ_DSP_WAIT4 =>
+ debug_register <= "101";
+ next_state <= READ_DSP_MEMORY;
+ RD_OUT <= '1';
+ WRL <= '1';
+ WRH <= '1';
+ HBR_OUT <= '0';
+ BRST <= '1';
+ when READ_DSP_MEMORY =>
+ debug_register <= "110";
+ RD_OUT <= '1';
+ WRL <= '1';
+ WRH <= '1';
+ HBR_OUT <= '0';
+ BRST <= '1';
+ if ACK = '0' then
+ next_state <= READ_DSP_MEMORY;
+ else
+ next_state <= SENT_DATA_TO_INTERNAL_ENTITY;
+ next_read_dsp_data <= DSP_DATA_IN;
+ end if;
+ when SENT_DATA_TO_INTERNAL_ENTITY =>
+ debug_register <= "111";
+ VALID_DATA_SENT <= '1';
+ INTERNAL_DATA_OUT <= reg_read_dsp_data;
+ next_state <= IDLE;
-----------------------------------------------------------------------
-- WRITING part
-----------------------------------------------------------------------
- when WRITE_DSP_WAIT_FOR_HBR =>
- debug_register <= "001";
- HBR_OUT <= '0';
- if HBG_IN = '0' then
- next_state <= WRITE_DSP_DUMMY;
+ when WRITE_DSP_WAIT_FOR_HBR =>
+ debug_register <= "001";
+ HBR_OUT <= '0';
+ if HBG_IN = '0' then
+ next_state <= WRITE_DSP_DUMMY;
else
- next_state <= WRITE_DSP_WAIT_FOR_HBR;
+ next_state <= WRITE_DSP_WAIT_FOR_HBR;
end if;
-
- when WRITE_DSP_DUMMY =>
- debug_register <= "111";
- HBR_OUT <= '0';
- ADDRESS_DSP <= (others => '0');
- WRL <= '1';
- WRH <= '1';
- RD_OUT <= '1';
- BRST <= '1';
- next_state <= WRITE_DSP_MEMORY_NEXT;
-
- when WRITE_DSP_MEMORY_NEXT =>
- debug_register <= "010";
- DSP_DATA_OUT <= x"5a5a5a5a";
- ADDRESS_DSP <= reg_address_dsp;
- WRL <= '0';
- WRH <= '1';
- HBR_OUT <= '0';
- RD_OUT <= '1';
- BRST <= '1';
- next_state <= WRITE_DSP_MEMORY;
-
- when WRITE_DSP_MEMORY =>
+ when WRITE_DSP_DUMMY =>
+ debug_register <= "111";
+ HBR_OUT <= '0';
+ ADDRESS_DSP <= (others => '0');
+ WRL <= '1';
+ WRH <= '1';
+ RD_OUT <= '1';
+ BRST <= '1';
+ DSP_DATA_OUT <= next_write_dsp_data;
+ next_state <= WRITE_DSP_MEMORY_NEXT;
+ when WRITE_DSP_MEMORY_NEXT =>
+ debug_register <= "010";
+ DSP_DATA_OUT <= next_write_dsp_data;-- (others => 'Z') ;
+ ADDRESS_DSP <= reg_address_dsp;
+ WRL <= '0';
+ WRH <= '1';
+ HBR_OUT <= '0';
+ RD_OUT <= '1';
+ BRST <= '1';
+ next_state <= WRITE_DSP_MEMORY;
+ when WRITE_DSP_MEMORY =>
debug_register <= "011";
- DSP_DATA_OUT <= reg_write_dsp_data;
+ DSP_DATA_OUT <= next_write_dsp_data;
WRL <= '1';
WRH <= '1';
HBR_OUT <= '0';
RD_OUT <= '1';
- BRST <= '1';
-
+ BRST <= '1';
if ACK = '1' then
- next_state <= WAIT_ACKNOWLEDGMENT;
+ next_state <= WAIT_ACKNOWLEDGMENT;
else
- next_state <= WRITE_DSP_MEMORY;
+ next_state <= WRITE_DSP_MEMORY;
end if;
-
when WAIT_ACKNOWLEDGMENT =>
VALID_DATA_SENT <= '1';
next_state <= IDLE;
-
- when others =>
- next_state <= IDLE;
-
+ when others =>
+ next_state <= IDLE;
end case;
end process;
-
- ------------------------------------------------------------------------------
- -- SINCRONISE WITH OTHER ENTITY OF MAREK --------------------------------------
- ------------------------------------------------------------------------------
- ------------------------------------------------------------------------------
--- clock_output: process (CLK, RESET)
--- begin -- process clocke_output
--- if rising_edge(CLK) then -- rising clock edge
--- if RESET = '1' then
--- INTERNAL_DATA <= "0000";
--- else
--- reg_internal_data <= next_internal_data;
--- end if;
--- end if;
--- end process clock_output;
-
end dsp_interface;
library IEEE;
--- use IEEE.STD_LOGIC_1164.ALL;
--- use IEEE.STD_LOGIC_ARITH.ALL;
- use IEEE.STD_LOGIC_UNSIGNED.ALL;
--- use IEEE.NUMERIC_STD.all;
-
--- -- use work.support.all;
- library UNISIM;
- use UNISIM.VCOMPONENTS.all;
--- use ieee.numeric_std.all;
--- use ieee.std_logic_arith.all;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.all;
library ieee;
library work;
-
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
---library unisim;
---use unisim.all;
use work.all;
--- -- Uncomment the following lines to use the declarations that are
--- -- provided for instantiating Xilinx primitive components.
--- library UNISIM;
--- use UNISIM.VComponents.all;
+
entity dtu_interface is
signal lvl1_trigger_data_bus_pulse : std_logic;
signal lvl1_trigger_bus_pulse_synch : std_logic;
signal lvl1_trigger_data_bus_pulse_synch : std_logic;
+signal lvl1_error_bus_i : std_logic;
signal lvl2_code_i : std_logic_vector(3 downto 0);
signal lvl2_tag_i : std_logic_vector(7 downto 0);
signal lvl2_trigger_data_bus_pulse : std_logic;
signal lvl2_trigger_bus_pulse_synch : std_logic;
signal lvl2_trigger_data_bus_pulse_synch : std_logic;
+signal lvl2_error_bus_i : std_logic;
signal lvl2_fifo_address_in : std_logic_vector(3 downto 0):=x"0";
signal lvl2_fifo_address_out : std_logic_vector(3 downto 0):=x"0";
end if;
end if;
end process LVL1_COUNTER_FOR_CODE_AND_TAG;
-
LVL1_SAVE_CODE_AND_TAG: process (CLK, RESET,lvl1_trigger_bus_pulse_synch,lvl1_trigger_data_bus_pulse_synch,lvl1_trigger_counter)
begin
if rising_edge(CLK) then
pulse => lvl1_trigger_i );
LVL1_TRIGGER <= lvl1_trigger_i;
- LVL1_BUSY_BUS <= LVL1_BUSY;
+ LVL1_BUSY_BUS <= LVL1_BUSY;-- or lvl1_error_bus_i;
LVL1_COUNT_TRIGGERS: process (CLK, RESET, lvl1_trigger_bus_pulse_synch)
begin
if rising_edge(CLK) then
if RESET = '1' then
- lvl1_triggers_counter <= x"00";
+ lvl1_triggers_counter <= x"ff";
elsif lvl1_trigger_bus_pulse_synch = '1' then
lvl1_triggers_counter <= lvl1_triggers_counter +1;
+ else
+ lvl1_triggers_counter <= lvl1_triggers_counter;
end if;
end if;
end process LVL1_COUNT_TRIGGERS;
LVL1_CHECK_TAG: process (CLK, RESET, lvl1_trigger_i,lvl1_triggers_counter,lvl1_tag_i )
begin
- if RESET = '1' then
- LVL1_ERROR_BUS <= '0';
if rising_edge(CLK) then
- if lvl1_trigger_i = '1' then
- if lvl1_triggers_counter /= lvl1_tag_i then
- LVL1_ERROR_BUS <= '1';
- end if;
+ if RESET = '1' then
+ lvl1_error_bus_i <= '0';
+ elsif lvl1_trigger_i = '1' and (lvl1_triggers_counter /= lvl1_tag_i)then
+ lvl1_error_bus_i <= '1';
end if;
end if;
-end if;
end process LVL1_CHECK_TAG;
-
+ LVL1_ERROR_BUS <= '0';--lvl1_error_bus_i;
-----------------------------------------------------------------------------
-- LVL2
lvl2_fifo_full <= '0' when fifo_counter < x"e" else '1';
lvl2_fifo_not_empty <= '1' when fifo_counter > x"0" else '0';
-- LVL2_BUSY_BUS <= LVL2_BUSY or lvl2_fifo_full;
- LVL2_BUSY_BUS <= lvl2_fifo_full;
+ LVL2_BUSY_BUS <= lvl2_fifo_full;-- or lvl2_error_bus_i;
SEND_LVL2_TRIGGER_FSM : process (CLK,RESET)
begin
if rising_edge(CLK) then
end case;
end process SEND_LVL2_TRIGGER_PROC;
LVL2_TRIGGER <= lvl2_trigger_i;
+ LVL2_COUNT_TRIGGERS: process (CLK, RESET, lvl2_trigger_bus_pulse_synch)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ lvl2_triggers_counter <= x"00";
+ elsif LVL2_TRB_ACK = '1' then
+ lvl2_triggers_counter <= lvl2_triggers_counter +1;
+ else
+ lvl2_triggers_counter <= lvl2_triggers_counter;
+ end if;
+ end if;
+ end process LVL2_COUNT_TRIGGERS;
+ LVL2_CHECK_TAG: process (CLK, RESET, lvl2_trigger_i,lvl2_triggers_counter,lvl2_fifo_data_out )
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ lvl2_error_bus_i <= '0';
+ elsif lvl2_trigger_i = '1' and (lvl2_triggers_counter /= lvl2_fifo_data_out(7 downto 0))then
+ lvl2_error_bus_i <= '1';
+ end if;
+ end if;
+ end process LVL2_CHECK_TAG;
+ LVL2_ERROR_BUS <= '0';--lvl2_error_bus_i;
end dtu_interface;
FPGA_REGISTER_03 : in std_logic_vector(31 downto 0);
FPGA_REGISTER_04 : in std_logic_vector(31 downto 0);
FPGA_REGISTER_05 : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_06 : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_07 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_06 : out std_logic_vector(31 downto 0);
+ FPGA_REGISTER_07 : out std_logic_vector(31 downto 0);
FPGA_REGISTER_08 : in std_logic_vector(31 downto 0);
FPGA_REGISTER_09 : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_10 : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_11 : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_12 : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_13 : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_14 : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_15 : in std_logic_vector(31 downto 0);
- FPGA_REGISTER_16 : out std_logic_vector(31 downto 0);
- FPGA_REGISTER_17 : out std_logic_vector(31 downto 0);
- FPGA_REGISTER_18 : out std_logic_vector(31 downto 0);
- FPGA_REGISTER_19 : out std_logic_vector(31 downto 0);
- FPGA_REGISTER_20 : out std_logic_vector(31 downto 0);
- FPGA_REGISTER_21 : out std_logic_vector(31 downto 0);
- FPGA_REGISTER_22 : out std_logic_vector(31 downto 0);
- FPGA_REGISTER_23 : out std_logic_vector(31 downto 0);
- FPGA_REGISTER_24 : out std_logic_vector(31 downto 0);
- FPGA_REGISTER_25 : out std_logic_vector(31 downto 0);
- FPGA_REGISTER_26 : out std_logic_vector(31 downto 0);
- FPGA_REGISTER_27 : out std_logic_vector(31 downto 0);
- FPGA_REGISTER_28 : out std_logic_vector(31 downto 0);
- FPGA_REGISTER_29 : out std_logic_vector(31 downto 0);
- FPGA_REGISTER_30 : out std_logic_vector(31 downto 0);
- FPGA_REGISTER_31 : out std_logic_vector(31 downto 0);
+ FPGA_REGISTER_0A : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_0B : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_0C : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_0D : in std_logic_vector(31 downto 0);
EXTERNAL_RESET : out std_logic;
LVL2_VALID : in std_logic
+ -- DEBUG_REGISTER_OO : out std_logic_vector(31 downto 0)
);
end etrax_interface;
architecture etrax_interface of etrax_interface is
signal saved_data : std_logic_vector(31 downto 0);
signal saved_data_fpga : std_logic_vector(31 downto 0);
- signal data_to_etrax_valid : std_logic;
signal fpga_register_00_i : std_logic_vector(31 downto 0);
signal fpga_register_01_i : std_logic_vector(31 downto 0);
signal fpga_register_02_i : std_logic_vector(31 downto 0);
signal fpga_register_07_i : std_logic_vector(31 downto 0);
signal fpga_register_08_i : std_logic_vector(31 downto 0);
signal fpga_register_09_i : std_logic_vector(31 downto 0);
- signal fpga_register_10_i : std_logic_vector(31 downto 0);
- signal fpga_register_11_i : std_logic_vector(31 downto 0);
- signal fpga_register_12_i : std_logic_vector(31 downto 0);
- signal fpga_register_13_i : std_logic_vector(31 downto 0);
- signal fpga_register_14_i : std_logic_vector(31 downto 0);
- signal fpga_register_15_i : std_logic_vector(31 downto 0);
- signal fpga_register_16_i : std_logic_vector(31 downto 0);
- signal fpga_register_17_i : std_logic_vector(31 downto 0);
- signal fpga_register_18_i : std_logic_vector(31 downto 0);
- signal fpga_register_19_i : std_logic_vector(31 downto 0);
- signal fpga_register_20_i : std_logic_vector(31 downto 0);
- signal fpga_register_21_i : std_logic_vector(31 downto 0);
- signal fpga_register_22_i : std_logic_vector(31 downto 0);
- signal fpga_register_23_i : std_logic_vector(31 downto 0);
- signal fpga_register_24_i : std_logic_vector(31 downto 0);
- signal fpga_register_25_i : std_logic_vector(31 downto 0);
- signal fpga_register_26_i : std_logic_vector(31 downto 0);
- signal fpga_register_27_i : std_logic_vector(31 downto 0);
- signal fpga_register_28_i : std_logic_vector(31 downto 0);
- signal fpga_register_29_i : std_logic_vector(31 downto 0);
- signal fpga_register_30_i : std_logic_vector(31 downto 0);
- signal fpga_register_31_i : std_logic_vector(31 downto 0);
- signal counter_for_test : std_logic_vector(16 downto 0);
+ signal fpga_register_0A_i : std_logic_vector(31 downto 0);
+ signal fpga_register_0B_i : std_logic_vector(31 downto 0);
+ signal fpga_register_0C_i : std_logic_vector(31 downto 0);
+ signal fpga_register_0D_i : std_logic_vector(31 downto 0);
signal saved_external_data : std_logic_vector(31 downto 0);
- signal debug_reg_00 : std_logic_vector(3 downto 0);
- signal debug_reg_01 : std_logic_vector(3 downto 0);
- signal debug_reg_02 : std_logic_vector(3 downto 0);
- signal debug_reg_03 : std_logic_vector(3 downto 0);
- signal etrax_data_pulse_0 : std_logic;
- signal etrax_data_pulse_1 : std_logic;
- signal etrax_data_pulse_2 : std_logic;
- signal etrax_data_pulse_3: std_logic;
- signal debug_reg_04 : std_logic_vector(15 downto 0);
signal etrax_is_ready_to_read_i : std_logic;
- signal pulse_clock : std_logic;
signal lvl2_not_valid_pulse : std_logic;
signal counter_for_pulses : std_logic_vector(2 downto 0);
+ signal internal_reset_i : std_logic;
begin
+ MAKE_RESET: process (CLK, ETRAX_DATA_BUS_C(16),ETRAX_DATA_BUS_C(17))
+ begin
+ if rising_edge(CLK) then
+ if (ETRAX_DATA_BUS_C(16)='1' and ETRAX_DATA_BUS_C(17)='1') then
+ internal_reset_i <= '1';
+ elsif ETRAX_DATA_BUS_C(16)='0' and ETRAX_DATA_BUS_C(17)='0' then
+ internal_reset_i <= '0';
+ else
+ internal_reset_i <= '0';
+ end if;
+ end if;
+ end process MAKE_RESET;
ETRAX_TRIGG_PULSER : edge_to_pulse
port map (
clock => CLK,
en_clk => DATA_VALID,--'1',
signal_in => ETRAX_DATA_BUS_C(17),
pulse => etrax_is_ready_to_read_i);
- MAKE_PULSES: process (CLK, RESET)
+ MAKE_PULSES: process (CLK, internal_reset_i)
begin
if rising_edge(CLK) then
- if RESET = '1' then
+ if internal_reset_i = '1' then
counter_for_pulses <= "000";
- -- pulse_clock <= '0';
else
--- pulse_clock <= not pulse_clock;
counter_for_pulses <= counter_for_pulses + 1;
end if;
end if;
port map (
clock => CLK,
en_clk => '1',
--- signal_in => pulse_clock,
signal_in => counter_for_pulses(2),
pulse => lvl2_not_valid_pulse);
--- ETRAX_READY_CLOCKED : process (CLK, RESET,ETRAX_DATA_BUS_C(16),ETRAX_DATA_BUS_C(17))
--- begin
--- if rising_edge(CLK) then
--- if RESET = '1' or (ETRAX_DATA_BUS_C(16)='1' and ETRAX_DATA_BUS_C(17)='1') then
--- ETRAX_RW_STATE_currentstate <= IDLE;
--- else
--- ETRAX_RW_STATE_currentstate <= ETRAX_RW_STATE_nextstate;
--- end if;
--- end if;
--- end process ETRAX_FPGA_COMUNICATION_CLOCK;
ETRAX_IS_READY_TO_READ <= etrax_is_ready_to_read_i or (DATA_VALID and lvl2_not_valid_pulse and LVL2_VALID);
RW_FINISHED_PULSER : edge_to_pulse
en_clk => '1',
signal_in => EXTERNAL_VALID,
pulse => rw_operation_finished_pulse);
- DELAY_COUNTER : up_counter_17bit
- port map (
- CLK => CLK,
- UP => etrax_trigger_pulse,
- CLR => RESET,
- QOUT => counter_for_test
- );
- TDC_TRST <= not fpga_register_18_i(0);--etrax_trigger_pulse and ETRAX_DATA_BUS_C(17);
- TDC_RESET <= fpga_register_17_i(0);
- EXTERNAL_RESET <= ETRAX_DATA_BUS_C(16) and ETRAX_DATA_BUS_C(17);
+ TDC_TRST <= not fpga_register_06_i(2);--etrax_trigger_pulse and ETRAX_DATA_BUS_C(17);
+ TDC_RESET <= fpga_register_06_i(1);
+ EXTERNAL_RESET <= internal_reset_i;--ETRAX_DATA_BUS_C(16) and ETRAX_DATA_BUS_C(17);
ETRAX_BUS_BUSY <= '0' when ETRAX_RW_STATE_currentstate = IDLE else '1';
REGISTERS: process (CLK)
begin
if rising_edge(CLK) then
--- if RESET = '1' then
--- fpga_register_16_i <= (others => '0');
--- fpga_register_17_i <= (others => '0');
--- fpga_register_18_i <= (others => '0');
--- fpga_register_19_i <= (others => '0');
--- fpga_register_10_i <= (others => '0');
--- fpga_register_20_i <= (others => '0');
--- fpga_register_21_i <= (others => '0');
--- fpga_register_22_i <= (others => '0');
--- fpga_register_23_i <= (others => '0');
--- fpga_register_24_i <= (others => '0');
--- fpga_register_25_i <= (others => '0');
--- fpga_register_26_i <= (others => '0');
--- fpga_register_27_i <= (others => '0');
--- fpga_register_28_i <= (others => '0');
--- fpga_register_29_i <= (others => '0');
--- fpga_register_30_i <= (others => '0');
--- fpga_register_31_i <= (others => '0');
--- else
--- fpga_register_00_i <= FPGA_REGISTER_00;
+-- if RESET = '1' or (ETRAX_DATA_BUS_C(16)='1' and ETRAX_DATA_BUS_C(17)='1') then
fpga_register_01_i <= FPGA_REGISTER_01;
fpga_register_02_i <= FPGA_REGISTER_02;
fpga_register_03_i <= FPGA_REGISTER_03;
fpga_register_04_i <= FPGA_REGISTER_04;
fpga_register_05_i <= FPGA_REGISTER_05;
- fpga_register_06_i <= FPGA_REGISTER_06;
- fpga_register_07_i <= FPGA_REGISTER_07;
+ FPGA_REGISTER_06 <= fpga_register_06_i; --this used for TDCjtag enable(0)
+ FPGA_REGISTER_07 <= fpga_register_07_i;
fpga_register_08_i <= FPGA_REGISTER_08;
fpga_register_09_i <= FPGA_REGISTER_09;
- fpga_register_10_i <= FPGA_REGISTER_10;
- fpga_register_11_i <= FPGA_REGISTER_11;
- fpga_register_12_i <= FPGA_REGISTER_12;
- fpga_register_13_i <= FPGA_REGISTER_13;
- fpga_register_14_i <= FPGA_REGISTER_14;
- fpga_register_15_i <= FPGA_REGISTER_15;
- FPGA_REGISTER_16 <= fpga_register_16_i; --this used for TDCjtag enable(0)
- FPGA_REGISTER_17 <= fpga_register_17_i; --this is used for TDC reset(0)
- FPGA_REGISTER_18 <= fpga_register_18_i; --this is used for jatgTDC
- --reset
- FPGA_REGISTER_19 <= fpga_register_19_i;
- FPGA_REGISTER_20 <= fpga_register_20_i; --enable TDC clock
- FPGA_REGISTER_21 <= fpga_register_21_i;
- FPGA_REGISTER_22 <= fpga_register_22_i;
- FPGA_REGISTER_23 <= fpga_register_23_i;
- FPGA_REGISTER_24 <= fpga_register_24_i;
- FPGA_REGISTER_25 <= fpga_register_25_i;
- FPGA_REGISTER_26 <= fpga_register_26_i;
- FPGA_REGISTER_27 <= fpga_register_27_i;
- FPGA_REGISTER_28 <= fpga_register_28_i;
- FPGA_REGISTER_29 <= fpga_register_29_i;
- FPGA_REGISTER_30 <= fpga_register_30_i;
- FPGA_REGISTER_31 <= fpga_register_31_i;
--- end if;
+ fpga_register_0A_i <= FPGA_REGISTER_0A;
+ fpga_register_0B_i <= FPGA_REGISTER_0B;
+ fpga_register_0c_i <= FPGA_REGISTER_0C;
+ fpga_register_0d_i <= FPGA_REGISTER_0D;
end if;
end process REGISTERS;
- ETRAX_FPGA_COMUNICATION_CLOCK : process (CLK, RESET,ETRAX_DATA_BUS_C(16),ETRAX_DATA_BUS_C(17))
+ -- DEBUG_REGISTER_OO(7 downto 0) <= fpga_register_00_i(7 downto 0);
+ -- FPGA_REGISTER_23(7 downto 0) <= fpga_register_00_i(7 downto 0);
+ ETRAX_FPGA_COMUNICATION_CLOCK : process (CLK, internal_reset_i)
begin
if rising_edge(CLK) then
- if RESET = '1' or (ETRAX_DATA_BUS_C(16)='1' and ETRAX_DATA_BUS_C(17)='1') then
+ if internal_reset_i = '1' then --(ETRAX_DATA_BUS_C(16)='1' and ETRAX_DATA_BUS_C(17)='1') then
ETRAX_RW_STATE_currentstate <= IDLE;
else
ETRAX_RW_STATE_currentstate <= ETRAX_RW_STATE_nextstate;
end if;
end if;
end process ETRAX_FPGA_COMUNICATION_CLOCK;
- ETRAX_FPGA_COMUNICATION: process (ETRAX_RW_STATE_currentstate,etrax_trigger_pulse,saved_rw_mode(15),rw_operation_finished_pulse)
+ ETRAX_FPGA_COMUNICATION: process (ETRAX_RW_STATE_currentstate,data_valid,etrax_trigger_pulse,saved_rw_mode(15),rw_operation_finished_pulse)
begin
fpga_register_00_i <= x"00000001";
case ETRAX_RW_STATE_currentstate is
when IDLE =>
fpga_register_00_i <= x"00000001";
- if etrax_trigger_pulse = '1' then
+ if etrax_trigger_pulse = '1' and DATA_VALID ='0' then
ETRAX_RW_STATE_nextstate <= SAVE_ADDRESS_1;
else
ETRAX_RW_STATE_nextstate <= IDLE;
else
ETRAX_RW_STATE_nextstate <= SEND_DATA_2;
end if;
- when others =>
- ETRAX_RW_STATE_nextstate <= IDLE;
end case;
end process ETRAX_FPGA_COMUNICATION;
- REGISTER_ETRAX_BUS: process (CLK, RESET,ETRAX_RW_STATE_currentstate)
+ REGISTER_ETRAX_BUS: process (CLK, internal_reset_i, ETRAX_RW_STATE_currentstate)
begin
if rising_edge(CLK) then
- if RESET = '1' then
+ if internal_reset_i = '1' then--(ETRAX_DATA_BUS_C(16)='1' and ETRAX_DATA_BUS_C(17)='1') then
saved_rw_mode <= (others => '0');
saved_address <= (others => '0');
saved_data <= (others => '0');
saved_data(31 downto 16) <= ETRAX_DATA_BUS_C(15 downto 0);
elsif ETRAX_RW_STATE_currentstate = SAVE_DATA_2 and etrax_trigger_pulse = '1' then
saved_data(15 downto 0) <= ETRAX_DATA_BUS_C(15 downto 0);
- else
- saved_rw_mode <= saved_rw_mode;
- saved_address <= saved_address;
- saved_data <= saved_data;
end if;
end if;
end process REGISTER_ETRAX_BUS;
EXTERNAL_ADDRESS <= saved_address;
EXTERNAL_MODE <= saved_rw_mode(15 downto 0);
EXTERNAL_DATA_OUT <= saved_data;
- EXTERNAL_DATA_LOGIC: process (CLK, RESET)
+ EXTERNAL_DATA_LOGIC: process (CLK, internal_reset_i)
begin
if rising_edge(CLK) then
- if RESET = '1' then
+ if internal_reset_i = '1' then--(ETRAX_DATA_BUS_C(16)='1' and ETRAX_DATA_BUS_C(17)='1') then
+ EXTERNAL_ACK <= '0';
elsif ETRAX_RW_STATE_currentstate = SEND_EXTERNAL_TRIGGER and saved_rw_mode(15) = '1' then
EXTERNAL_ACK <= '1';
elsif ETRAX_RW_STATE_currentstate = SEND_EXTERNAL_TRIGGER and saved_rw_mode(15) = '0' then
end if;
end if;
end process EXTERNAL_DATA_LOGIC;
- ETRAX_DATA_BUS_CHOOSE : process (CLK, RESET,ETRAX_RW_STATE_currentstate, DATA_VALID)
+ ETRAX_DATA_BUS_CHOOSE : process (CLK, internal_reset_i,ETRAX_RW_STATE_currentstate, DATA_VALID)
begin
if rising_edge(CLK) then
- if RESET = '1' then
+ if internal_reset_i = '1' then--(ETRAX_DATA_BUS_C(16)='1' and ETRAX_DATA_BUS_C(17)='1') then
ETRAX_DATA_BUS_B(16 downto 0) <= "0"& x"0000";--(others => 'Z');
- elsif ETRAX_RW_STATE_currentstate = SEND_DATA_1 then
+ elsif ETRAX_RW_STATE_currentstate = SEND_DATA_1 then
ETRAX_DATA_BUS_B(15 downto 0) <= saved_data_fpga(31 downto 16);--fpga_register_07_i(15 downto 0);--
ETRAX_DATA_BUS_B(16) <= '1';
- -- ETRAX_DATA_BUS_B(17) <= '0';
- elsif ETRAX_RW_STATE_currentstate = SEND_DATA_2 or ETRAX_RW_STATE_currentstate = SEND_VALID then
+ elsif ETRAX_RW_STATE_currentstate = SEND_DATA_2 or ETRAX_RW_STATE_currentstate = SEND_VALID then
ETRAX_DATA_BUS_B(15 downto 0) <= saved_data_fpga(15 downto 0);--fpga_register_07_i(15 downto 0);--
ETRAX_DATA_BUS_B(16) <= '1';
- -- ETRAX_DATA_BUS_B(17) <= '0';
- elsif DATA_VALID = '1' then
+ elsif DATA_VALID = '1' then
ETRAX_DATA_BUS_B(15 downto 0) <= DATA_BUS(15 downto 0);
- -- ETRAX_DATA_BUS_B(17) <= CLK;
ETRAX_DATA_BUS_B(16) <= '1' and not(LVL2_VALID);
else
- ETRAX_DATA_BUS_B(15 downto 0) <= fpga_register_07_i(15 downto 0);
+ ETRAX_DATA_BUS_B(15 downto 0) <= fpga_register_06_i(15 downto 0);
ETRAX_DATA_BUS_B(16) <= '0';
end if;
end if;
end process ETRAX_DATA_BUS_CHOOSE;
-
- ETRAX_DATA_BUS_B(17) <= CLK when DATA_VALID = '1' else '0';
-
- TDC_JAM_SIGNALS : process (CLK, RESET, DATA_VALID, fpga_register_16_i(0))
+-- ETRAX_DATA_BUS_B(17) <= CLK when DATA_VALID = '1' else '0'; -trigger
+ ETRAX_DATA_BUS_B(17) <= '1';
+ TDC_JAM_SIGNALS : process (CLK, internal_reset_i, DATA_VALID, fpga_register_06_i(0))
begin
if rising_edge(CLK) then
- if RESET = '1' then
+ if internal_reset_i = '1' then
TDC_TMS <= '1';
TDC_TCK <= '1';
TDC_TDI <= '1';
ETRAX_DATA_BUS_C <= (others => 'Z');
- elsif fpga_register_16_i(0) = '1' then
--- ETRAX_DATA_BUS_C <= (others => 'Z');
+ elsif fpga_register_06_i(0) = '1' then
TDC_TMS <= ETRAX_DATA_BUS_C(1);
TDC_TCK <= ETRAX_DATA_BUS_C(2);
TDC_TDI <= ETRAX_DATA_BUS_C(3);
ETRAX_DATA_BUS_C(0) <= TDC_TDO;
ETRAX_DATA_BUS_C(17 downto 1) <= (others => 'Z');
--- ETRAX_DATA_BUS_C(13 downto 0) <= (others => 'Z');
elsif DATA_VALID = '1' then
ETRAX_DATA_BUS_C(15 downto 0) <= DATA_BUS(31 downto 16);
ETRAX_DATA_BUS_C(16) <= 'Z';
end if;
end if;
end process TDC_JAM_SIGNALS;
- DATA_SOURCE_SELECT : process (CLK,RESET,saved_rw_mode,saved_address)
+ DATA_SOURCE_SELECT : process (CLK,internal_reset_i,saved_rw_mode,saved_address)
begin
if rising_edge(CLK) then
- if RESET ='1' or (ETRAX_DATA_BUS_C(16) = '1' and ETRAX_DATA_BUS_C(17) = '1') then
- fpga_register_16_i <= x"00000000";
- fpga_register_19_i <= (others => '0');
+ if internal_reset_i = '1' then--(ETRAX_DATA_BUS_C(16) = '1' and ETRAX_DATA_BUS_C(17) = '1') then
+ fpga_register_06_i <= x"00000000";
else
case saved_rw_mode(7 downto 0) is
when "00000000" =>
when x"00000007" => saved_data_fpga <= fpga_register_07_i;
when x"00000008" => saved_data_fpga <= fpga_register_08_i;
when x"00000009" => saved_data_fpga <= fpga_register_09_i;
- when x"00000010" => saved_data_fpga <= fpga_register_10_i;
- when x"00000011" => saved_data_fpga <= fpga_register_11_i;
- when x"00000012" => saved_data_fpga <= fpga_register_12_i;
- when x"00000013" => saved_data_fpga <= fpga_register_13_i;
- when x"00000014" => saved_data_fpga <= fpga_register_14_i;
- when x"00000015" => saved_data_fpga <= fpga_register_15_i;
- when x"00000016" => saved_data_fpga <= fpga_register_16_i;
- when x"00000017" => saved_data_fpga <= fpga_register_17_i;
- when x"00000018" => saved_data_fpga <= fpga_register_18_i;
- when x"00000019" => saved_data_fpga <= fpga_register_19_i;
- when x"00000020" => saved_data_fpga <= fpga_register_20_i;
- when x"00000021" => saved_data_fpga <= fpga_register_21_i;
- when x"00000022" => saved_data_fpga <= fpga_register_22_i;
- when x"00000023" => saved_data_fpga <= fpga_register_23_i;
- when x"00000024" => saved_data_fpga <= fpga_register_24_i;
- when x"00000025" => saved_data_fpga <= fpga_register_25_i;
- when x"00000026" => saved_data_fpga <= fpga_register_26_i;
- when x"00000027" => saved_data_fpga <= fpga_register_27_i;
- when x"00000028" => saved_data_fpga <= fpga_register_28_i;
- when x"00000029" => saved_data_fpga <= fpga_register_29_i;
- when x"00000030" => saved_data_fpga <= fpga_register_30_i;
- when x"00000031" => saved_data_fpga <= fpga_register_31_i;
+ when x"0000000A" => saved_data_fpga <= fpga_register_0A_i;
+ when x"0000000B" => saved_data_fpga <= fpga_register_0B_i;
+ when x"0000000C" => saved_data_fpga <= fpga_register_0C_i;
+ when x"0000000D" => saved_data_fpga <= fpga_register_0D_i;
when others => saved_data_fpga <= x"deadface";
end case;
elsif saved_rw_mode(15) = '0' and ETRAX_RW_STATE_currentstate = WAIT_FOR_DATA then
case saved_address(31 downto 0) is
- when x"00000016" => fpga_register_16_i <= saved_data;
- when x"00000017" => fpga_register_17_i <= saved_data;
- when x"00000018" => fpga_register_18_i <= saved_data;
- when x"00000019" => fpga_register_19_i <= saved_data;
- when x"00000020" => fpga_register_20_i <= saved_data;
- when x"00000021" => fpga_register_21_i <= saved_data;
- when x"00000022" => fpga_register_22_i <= saved_data;
- when x"00000023" => fpga_register_23_i <= saved_data;
- when x"00000024" => fpga_register_24_i <= saved_data;
- when x"00000025" => fpga_register_25_i <= saved_data;
- when x"00000026" => fpga_register_26_i <= saved_data;
- when x"00000027" => fpga_register_27_i <= saved_data;
- when x"00000028" => fpga_register_28_i <= saved_data;
- when x"00000029" => fpga_register_29_i <= saved_data;
- when x"00000030" => fpga_register_30_i <= saved_data;
- when x"00000031" => fpga_register_31_i <= saved_data;
+ when x"00000006" => fpga_register_06_i <= saved_data;
+ when x"00000007" => fpga_register_07_i <= saved_data;
when others => null;
end case;
end if;
when "00000001" => --DSP write read
saved_data_fpga <= saved_external_data;
+ when x"02" =>
+ saved_data_fpga <= saved_external_data;
+ when x"03" =>
+ saved_data_fpga <= saved_external_data;
when others => --ADDON board write read
saved_data_fpga <= x"deadface";
end case;
--- /dev/null
+setMode -bs
+setMode -bs
+setCable -port stapl -file "../trb_v2b_fpga.stapl"
+addDevice -p 1 -file "trb_v2b_fpga.bit"
+Program -p 1 -defaultVersion 0
+quit
\ No newline at end of file
--- /dev/null
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.4e
+$63b
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\7fjw/qlwvZad4?49:6``rlefj+`kjea$oaeboe-`|+tcp&zex
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\7f9>?:181
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\7fp7`5=839p1>k=:3:g?85a:3;h963<e2816g=z{:o96=4<{<1f6?45j278i9495:?0b6<1=2wx?h;50;1x96c32;2o70=i3;3`1>;4m<09>o5rs2g7>5<4s49n87<=b:?0a3<1=278j9495:
\7fp7`1=839p1>k9:3:g?85a<3;h963<e6816g=z{:o=6=4<{<1f2?45j278i5495:?0b0<1=2wx?h750;1x96c?2;2o70=i5;3`1>;4m009>o5rs2g;>5<4s49n47<=b:?0ad<1=278j;495:
\7fp7`d=839p1>kn:3:g?85a>3;h963<ec816g=z{:oj6=4<{<1fe?45j278in495:?0b2<1=2wx?hj50;1x96cd2;2o70=i7;3`1>;4mm09>o5rs2g`>5<4s49no7<=b:?0a`<1=278j5495:
\7fp7``=839p1>kj:3:g?85a03;h963<eg816g=z{:on6=4={<1fa?45j278j4495:
\7fp7cg=838p1>h6:0a6?85ai389n6s|43`94?5|5=9>6;l4=52e>7>c34>9<7<=b:
\7fp07e=838p19=9:7`891462;8i7p};2e83>7}:<:=1:o52430967d<uz>9i7>52z?77=<1j27?>>4=2c9~w14a2909w0:<9;4a?825<389n6s|42294?4|5=9j6;l4=506>74e3ty??<4?:3y>06d=>k168?8523`8yv24:3:1>v3;3b85f>;3:>09>o5rs510>5<5s4>8h78m;<61<?45j2wx8>:50;0x915b2?h019<6:30a?xu38o0;6>u241d967d<5=;;6;;4=502>33<uz>:=7>53z?755<50m168??51b7891762;8i7p};1183>6}:<8:1>?l4=531>33<5=896;;4}r627?6=;r7?=?4=8e9>074=9j?019?<:30a?xu39;0;6>u2400967d<5=;?6;;4=500>33<uz>:97>53z?751<50m168?=51b7891722;8i7p};1583>6}:<8>1>?l4=535>33<5=8?6;;4}r623?6=;r7?=;4=8e9>072=9j?019?8:30a?xu39?0;6>u2404967d<5=;36;;4=506>33<uz>:57>53z?75=<50m168?;51b78917>2;8i7p};1983>6}:<821>?l4=53b>33<5=8=6;;4}r62f?6=;r7?=l4=8e9>070=9j?019?m:30a?xu39h0;6>u240c967d<5=;h6;;4=504>33<uz>:h7>53z?75f<50m168?951b78917c2;8i7p};1b83>6}:<8i1>?l4=53f>33<5=836;;4}r62b?6=;r7?=h4=8e9>07>=9j?019?i:30a?xu39l0;6?u240g967d<5=826;;4}r61e?6=:r7?>44>c49>07g=:;h0q~=lb;297~;4l<0=n63<ag81<a=:;j:1>?l4}r1`g?6=:r78h;49b:?0g4<5:k1v
\7f>mk:181
\7f85c?3<i70=l2;01f>{t;jo1<7<t=2f;>3d<5:i86?<m;|q0gc<72;q6?i756c9>7f2=:;h0q~=k0;296~;4lh0=n63<c4816g=z{:n:6=4={<1gf?0e349h:7<=b:
\7fp7a4=838p1>jl:7`896e02;8i7p}<d283>7}:;mn1:o523b:967d<uz9o87>52z?0``<1j278o44=2c9~w6ga2908w0=nf;01f>;4j90=963<c0851>{t;k;1<7=t=2`3>7>c349h=7?l5:?0f4<5:k1v
\7f>l?:180
\7f85e8389n63<b3851>;4k;0=96s|3c194?5|5:h96?6k;<1`6?7d=278n>4=2c9~w6d52908w0=m2;01f>;4j=0=963<c2851>{t;k?1<7=t=2`7>7>c349h?7?l5:?0f0<5:k1v
\7f>l;:180
\7f85e<389n63<b7851>;4k=0=96s|3c594?5|5:h=6?6k;<1`0?7d=278n:4=2c9~w6d12908w0=m6;01f>;4j10=963<c4851>{t;k31<7=t=2`;>7>c349h97?l5:?0f<<5:k1v
\7f>l7:180
\7f85e0389n63<b`851>;4k?0=96s|3c`94?5|5:hj6?6k;<1`2?7d=278no4=2c9~w6df2908w0=ma;01f>;4jj0=963<c6851>{t;kn1<7=t=2``>7>c349h;7?l5:?0fa<5:k1v
\7f>ll:180
\7f85ek389n63<bd851>;4k10=96s|3cd94?5|5:hn6?6k;<1`<?7d=278nk4=2c9~w6db2909w0=me;01f>;4k00=96s|3bc94?4|5:i26<m:;<1`e?45j2wx:=m50;0x93602;2o708>1;01f>{t>991<7<t=724>74e34<;478:;|q54a<72;q6:=6529f893752;8i7p}90583>7}:>921>?l4=72:>33<uz<;i7>52z?54<<50m16:<=523`8yv07=3:1>v3908816g=:>9k1:85rs72e>5<5s4<;m7<7d:?551<5:k1v
\7f;>9:181
\7f807i389n6390c851>{t>8:1<7<t=72a>7>c34<:97<=b:
\7fp27?=838p1;>m:30a?80793;<96s|60d94?4|5?;j6?6k;<410?45j2wx:<850;0x937f2;8i708>b;46?xu1:90;6?u260`96=b<5?8>6?<m;|q552<72;q6:<l523`8937d2??0q~8=1;296~;19j094i52634967d<uz<:47>52z?55f<5:k16:<j5649~w3452909w08>d;0;`>;1:>09>o5rs73:>5<5s4<:h7<=b:?55`<1=2wx:?=50;0x937b2;2o708=8;01f>{t>;k1<7<t=73f>74e34<;=7?84:
\7fp256=838p1;>=:7`893662;8i7p}93683>7}:>:81>5j4=71`>74e3ty=>h4?:3y>264=:;h01;=<:778yv0403:1>v393281<a=:>:n1>?l4}r41b?6=:r7=?>4=2c9>262=><1v
\7f;=6:181
\7f804<383h6393d816g=z{?9;6=4={<400?45j27=?8495:
\7fp26g=838p1;=::3:g?804n389n6s|62394?4|5?9>6?<m;<402?023ty=?o4?:3y>260=:1n01;:?:30a?xu1==0;6?u2624967d<5?8h6<9:;|q50d<72;q6:9;529f8932a2;8i7p}94083>7}:>=?1>?l4=765>33<uz<?n7>52z?503<50m16:8>523`8yv03:3:1>v3947816g=:>==1:85rs76`>5<5s4<?;7<7d:?514<5:k1v
\7f;:<:181
\7f803?389n63949851>{t>=n1<7<t=76;>7>c34<>>7<=b:
\7fp212=838p1;:7:30a?80313<>7p}94d83>7}:>=31>5j4=770>74e3ty=984?:3y>21?=:;h01;<l:057?xu1:k0;6?u263f92g=:>;i1>?l4}r7a`?6=:r7>n54=8e9>1f4=:;h0q~;m4;296~;2j109>o525c;920=z{<hn6=4={<7a=?4?l27>o>4=2c9~w0d22909w0;m9;01f>;2jh0=96s|5cd94?4|5<hj6?6k;<7`0?45j2wx9o850;0x90df2;8i70;mb;46?xu2k90;6?u25c`96=b<5<i>6?<m;|q6f2<72;q69ol523`890dd2??0q~;l1;296~;2jj094i525b4967d<uz?o<7>52z?6gg<50m169i;523`8yv3d?3:1>v3:cc816g=:=ji1:85rs4f2>5<5s4?ho7<7d:?6`3<5:k1v
\7f8m7:181
\7f83dk389n63:ce851>{t=m81<7<t=4ag>7>c34?o;7<=b:
\7fp1f?=838p18mk:30a?83dm3<>7p}:d283>7}:=jo1>5j4=4f;>74e3ty>ol4?:3y>1fc=:;h018mi:778yv3c<3:1>v3:cg81<a=:=m31>?l4}r7f7?6=:r7>hh4=8e9>1`>=:;h0q~;ka;296~;2ll09>o525ed920=z{<o?6=4={<7gb?4?l27>i44=2c9~w0be2909w0;kf;01f>;2m90=96s|5d794?4|5<o;6?6k;<7fe?45j2wx9im50;0x90c72;8i70;j1;46?xu2m?0;6?u25d396=b<5<oi6?<m;|q6`a<72;q69h?523`890c52??0q~;j7;296~;2m;094i525da967d<uz?m:7>52z?6b4<50m169kl523`8yv3bl3:1>v3:f0816g=:=o81:85rs4d4>5<5s4?m>7<7d:?6bf<5:k1v
\7f8kj:181
\7f83a:389n63:f2851>{t=o21<7<t=4d0>7>c34?mh7<=b:
\7fp1``=838p18h<:30a?83a<3<>7p}:f883>7}:=o>1>5j4=4df>74e3ty>j=4?:3y>1c2=:;h018h::778yv3ai3:1>v3:f481<a=:=ol1>?l4}r720?6==r7?i<49b:?65`<5?>168h=5161891c228=970:j7;341>{t<l81<7<t=5g3>3d<5=o86?<m;|q7a1<72;q68ih56c9>0`3=:;h0q~:j6;29<~;3ll0=n63;e6816g=:<l31=:=4=5ga>41334>nh7?85:?7b7<6?;168k:5160891`128=97p};e983>7}:<mn1:o524d;967d<uz>nm7>52z?7`f<1j27?io4=2c9~w1cd2909w0:kb;4a?82bl389n6s|4dg94?4|5=nj6;l4=5d1>74e3ty?j>4?:3y>0a?=>k168k:523`8yv2a=3:1>v3;d985f>;3n?09>o5rs40;>5<5s4?:i78m;<706?40?2wx9?950;0x907c2?h018=>:354?xu29:0;69u250f9621<5=o86<9=;<6f1?70;27?i:4>759~w0412909w0;>c;4a?834838<;6s|50094?5|5<;h6?98;<6f1?70<27?i:4>729~w0422909w0;>b;4a?835n38<;6s|50394?4|5<;i6?98;<6f3?70:2wx9?:50;0x907f2?h018<j:354?xu2990;6:u250c9621<5=o26<9=;<6ff?70;27?ii4>759>0c4=9>9019h;:050?82a>3;<?6s|53194?4|5<;26;l4=40g>7103ty><k4?:7y>14?=:>=019km:051?82bl3;<?63;f38231=:<o>1=::4=5d5>4133ty>>?4?:3y>14>=>k169?m52658yv37m3:19v3:198132=:<ln1=:<4=5ge>41534>m<7?82:?7b4<6?;1v
\7f8<>:181
\7f836?3<i70;=b;043>{t=9n1<7:t=434>71034>nj7?83:?7b5<6?:168k?51618yv3583:1>v3:1785f>;2:h09;:5rs42`>5<4s4?::7<87:?7b5<6?=168k?51668yv36n3:1>v3:1485f>;2:009;:5rs42a>5<5s4?:97<87:?7b4<6?<1v
\7f8>?:181
\7f834:3<i70;?a;043>{t<ol1<7<t=412>3d<5<:26?98;|q7b`<72;q69>>56c9>15>=:>=0q~:id;296~;2:o0=n63:068132=z{=lh6=4={<71a?0e34?;:7<87:
\7fp0cd=838p18<k:7`890622;=<7p};f`83>7}:=;i1:o525169621<uz>m57>52z?66g<1j27><>4=769~w1`?2909w0;=a;4a?837:38<;6s|4g594?4|5<826;l4=422>7103ty>?>4?:3y>15?=>k168nh523`8yv34<3:1>v3:0985f>;3l909>o5rs416>5<5s4?;;78m;<6g5?45j2wx9>850;0x90612?h019j=:30a?xu2;>0;6?u251792g=:<m91>?l4}r70<?6=:r7><949b:?7`1<5:k1v
\7f8=6:181
\7f837;3<i70:k5;01f>{t=:k1<7<t=421>3d<5=n=6?<m;|q67g<72;q69=?56c9>0a1=:;h0q~;71;291~;2<l0=n63:8c8132=:=<:1=:=4=471>41534?>87?85:
\7fp11`=838p18:k:7`890372;8i7p}:5083>7}:==i1:o52540967d<uz?>?7>58z?60g<1j27>994=2c9>100=9>9018;7:057?832i3;<963:5g8237=:=?;1=:<4=440>4153ty>984?:3y>11g=>k16988523`8yv32?3:1>v3:4885f>;2=109>o5rs47:>5<5s4??478m;<76e?45j2wx98l50;0x90202?h018;i:30a?xu2>90;6?u255492g=:=?;1>?l4}r756?6=:r7>8849b:?626<5:k1v
\7f87::181
\7f83?j3<i70;6f;043>{t=0>1<7<t=4:b>3d<5<3n6?98;|q6<5<72=q695o52658903728=970;:2;347>;2==0:;95rs4;0>5<5s4?3578m;<7:`?40?2wx9:h50;1x90>>2;=<70;:2;340>;2==0:;>5rs4;1>5<5s4?3478m;<7:g?40?2wx9:k50;0x90>?2;=<70;:4;346>{t=0;1<7<t=4:4>3d<5<3i6?98;|q63a<72>q695952658903128=970;:8;347>;2=h0:;95254d9525<5<<:6<9<;<757?70;2wx94>50;0x90>12?h0187n:354?xu2?j0;6;u25949621<5<?36<9=;<76e?70;27>9k4>759>137=9>>0188<:057?xu20o0;6?u259792g=:=031>:94}r74f?6==r7>484=769>10g=9>8018;l:051?832l3;<>63:5d8237=z{<2n6=4={<7;0?0e34?247<87:
\7fp12g=83>p186;:354?832k3;<?63:5e8236=:=<o1=:=4}r7;`?6=:r7>4>49b:?6=2<5?>1v
\7f896:180
\7f83?;38<;63:5e8231=:=<o1=::4}r7;g?6=:r7>4?49b:?6=3<5?>1v
\7f897:181
\7f83?:38<;63:5d8230=z{<<o6=4={<7:b?0e34?<;7<87:
\7fp13e=838p187j:7`890112;=<7p}:6c83>7}:=0n1:o525679621<uz?=m7>52z?6=f<1j27>;94=769~w00>2909w0;6b;4a?830;38<;6s|57:94?4|5<3j6;l4=451>7103ty>::4?:3y>1<?=>k169:?52658yv31>3:1>v3:9985f>;2?909;:5rs446>5<5s4?2;78m;<75b?40?2wx9;:50;0x90?12?h0188j:354?xu2i90;6?u256492g=:=:i1>?l4}r7b5?6=:r7>;849b:?67a<5:k1v
\7f8o=:181
\7f830<3<i70;<e;01f>{t=h91<7<t=450>3d<5<9m6?<m;|q6e1<72;q69:<56c9>116=:;h0q~;n5;296~;2?80=n63:40816g=z{<k=6=4={<744?0e34??>7<=b:
\7fp1d1=838p188i:7`890242;8i7p}:a983>7}:=?o1:o52556967d<uz>i<7>52z?7g1<1=27?n=4=2c9~w1eb2909w0:l4;3`1>;3jh09>o5rs5c1>5<5s4>h87<=b:?6f7<1j2wx8lh50;1x91e42??019l?:77891ga2;8i7p};ce83>6}:<j91=n;4=5`3>7>c34>i57<=b:
\7fp0d7=838p19m<:30a?83e93<i7p};ad83>6}:<j81:8524`d920=:<ho1>?l4}r6`g?6=;r7?o?4>c49>0d`=:1n019l7:30a?xu3i90;6?u24b0967d<5<h;6;l4}r6b`?6=;r7?o<495:?7e`<1=27?mi4=2c9~w1ee2908w0:l1;3`1>;3il094i524c5967d<uz>2j7>52z?7g4<5:k169lh56c9~w1gd2908w0:l0;46?82fl3<>70:nc;01f>{t<jk1<7=t=5a3>4e234>jh7<7d:?7f3<5:k1v
\7f9o9:181
\7f82d8389n63:ad85f>{t<hh1<7=t=5`e>33<5=kh6;;4=5ca>74e3ty?o44?:2y>0g`=9j?019ol:3:g?82e=389n6s|4`794?4|5=hm6?<m;<7b`?0e3ty?ml4?:2y>0gc=><168ll5649>0dg=:;h0q~:l8;297~;3jl0:o8524``96=b<5=h?6?<m;|q7e1<72;q68ok523`890gd2?h0q~:n9;297~;3jm0=963;a`851>;3i009>o5rs5a4>5<4s4>ih7?l5:?7ed<50m168o=523`8yv2f;3:1>v3;be816g=:=hh1:o5rs5c;>5<4s4>io78:;<6b=?0234>j47<=b:
\7fp0f0=839p19ll:0a6?82f1383h63;b3816g=z{=k<6=4={<6ag?45j27>ml49b:
\7fp0f3=839p19lm:0a6?82f0383h63;b0816g=z{??=6=4={<6af?45j27>m449b:
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\7f?<<:181
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\7fM4>12wei::50;3xL7?>3twvqMNL{0335?31<<o35nsO@Cy3yEFWstJK
\ No newline at end of file
--- /dev/null
+--------------------------------------------------------------------------------
+-- This file is owned and controlled by Xilinx and must be used --
+-- solely for design, simulation, implementation and creation of --
+-- design files limited to Xilinx devices or technologies. Use --
+-- with non-Xilinx devices or technologies is expressly prohibited --
+-- and immediately terminates your license. --
+-- --
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
+-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
+-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
+-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
+-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
+-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
+-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
+-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
+-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
+-- FOR A PARTICULAR PURPOSE. --
+-- --
+-- Xilinx products are not intended for use in life support --
+-- appliances, devices, or systems. Use in such applications are --
+-- expressly prohibited. --
+-- --
+-- (c) Copyright 1995-2007 Xilinx, Inc. --
+-- All rights reserved. --
+--------------------------------------------------------------------------------
+-- You must compile the wrapper file lvl1_buffer.vhd when simulating
+-- the core, lvl1_buffer. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
+-- The synthesis directives "translate_off/translate_on" specified
+-- below are supported by Xilinx, Mentor Graphics and Synplicity
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+-- synthesis translate_off
+Library XilinxCoreLib;
+-- synthesis translate_on
+ENTITY lvl1_buffer IS
+ port (
+ din: IN std_logic_VECTOR(31 downto 0);
+ rd_clk: IN std_logic;
+ rd_en: IN std_logic;
+ rst: IN std_logic;
+ wr_clk: IN std_logic;
+ wr_en: IN std_logic;
+ dout: OUT std_logic_VECTOR(31 downto 0);
+ empty: OUT std_logic;
+ full: OUT std_logic;
+ rd_data_count: OUT std_logic_VECTOR(9 downto 0));
+END lvl1_buffer;
+
+ARCHITECTURE lvl1_buffer_a OF lvl1_buffer IS
+-- synthesis translate_off
+component wrapped_lvl1_buffer
+ port (
+ din: IN std_logic_VECTOR(31 downto 0);
+ rd_clk: IN std_logic;
+ rd_en: IN std_logic;
+ rst: IN std_logic;
+ wr_clk: IN std_logic;
+ wr_en: IN std_logic;
+ dout: OUT std_logic_VECTOR(31 downto 0);
+ empty: OUT std_logic;
+ full: OUT std_logic;
+ rd_data_count: OUT std_logic_VECTOR(9 downto 0));
+end component;
+
+-- Configuration specification
+ for all : wrapped_lvl1_buffer use entity XilinxCoreLib.fifo_generator_v3_3(behavioral)
+ generic map(
+ c_rd_freq => 100,
+ c_wr_response_latency => 1,
+ c_has_srst => 0,
+ c_has_rd_data_count => 1,
+ c_din_width => 32,
+ c_has_wr_data_count => 0,
+ c_implementation_type => 2,
+ c_family => "virtex4",
+ c_has_wr_rst => 0,
+ c_wr_freq => 100,
+ c_underflow_low => 0,
+ c_has_meminit_file => 0,
+ c_has_overflow => 0,
+ c_preload_latency => 1,
+ c_dout_width => 32,
+ c_rd_depth => 1024,
+ c_default_value => "BlankString",
+ c_mif_file_name => "BlankString",
+ c_has_underflow => 0,
+ c_has_rd_rst => 0,
+ c_has_almost_full => 0,
+ c_has_rst => 1,
+ c_data_count_width => 10,
+ c_has_wr_ack => 0,
+ c_use_ecc => 0,
+ c_wr_ack_low => 0,
+ c_common_clock => 0,
+ c_rd_pntr_width => 10,
+ c_has_almost_empty => 0,
+ c_rd_data_count_width => 10,
+ c_enable_rlocs => 0,
+ c_wr_pntr_width => 10,
+ c_overflow_low => 0,
+ c_prog_empty_type => 0,
+ c_optimization_mode => 0,
+ c_wr_data_count_width => 10,
+ c_preload_regs => 0,
+ c_dout_rst_val => "0",
+ c_has_data_count => 0,
+ c_prog_full_thresh_negate_val => 1021,
+ c_wr_depth => 1024,
+ c_prog_empty_thresh_negate_val => 3,
+ c_prog_empty_thresh_assert_val => 2,
+ c_has_valid => 0,
+ c_init_wr_pntr_val => 0,
+ c_prog_full_thresh_assert_val => 1022,
+ c_use_fifo16_flags => 0,
+ c_has_backup => 0,
+ c_valid_low => 0,
+ c_prim_fifo_type => "1kx36",
+ c_count_type => 0,
+ c_prog_full_type => 0,
+ c_memory_type => 1);
+-- synthesis translate_on
+BEGIN
+-- synthesis translate_off
+U0 : wrapped_lvl1_buffer
+ port map (
+ din => din,
+ rd_clk => rd_clk,
+ rd_en => rd_en,
+ rst => rst,
+ wr_clk => wr_clk,
+ wr_en => wr_en,
+ dout => dout,
+ empty => empty,
+ full => full,
+ rd_data_count => rd_data_count);
+-- synthesis translate_on
+
+END lvl1_buffer_a;
+
--- /dev/null
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.4e
+$`76
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\ No newline at end of file
--- /dev/null
+--------------------------------------------------------------------------------
+-- This file is owned and controlled by Xilinx and must be used --
+-- solely for design, simulation, implementation and creation of --
+-- design files limited to Xilinx devices or technologies. Use --
+-- with non-Xilinx devices or technologies is expressly prohibited --
+-- and immediately terminates your license. --
+-- --
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
+-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
+-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
+-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
+-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
+-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
+-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
+-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
+-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
+-- FOR A PARTICULAR PURPOSE. --
+-- --
+-- Xilinx products are not intended for use in life support --
+-- appliances, devices, or systems. Use in such applications are --
+-- expressly prohibited. --
+-- --
+-- (c) Copyright 1995-2007 Xilinx, Inc. --
+-- All rights reserved. --
+--------------------------------------------------------------------------------
+-- You must compile the wrapper file lvl1_fifo.vhd when simulating
+-- the core, lvl1_fifo. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
+-- The synthesis directives "translate_off/translate_on" specified
+-- below are supported by Xilinx, Mentor Graphics and Synplicity
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+-- synthesis translate_off
+Library XilinxCoreLib;
+-- synthesis translate_on
+ENTITY lvl1_fifo IS
+ port (
+ clk: IN std_logic;
+ din: IN std_logic_VECTOR(31 downto 0);
+ rd_en: IN std_logic;
+ rst: IN std_logic;
+ wr_en: IN std_logic;
+ data_count: OUT std_logic_VECTOR(13 downto 0);
+ dout: OUT std_logic_VECTOR(31 downto 0);
+ empty: OUT std_logic;
+ full: OUT std_logic);
+END lvl1_fifo;
+
+ARCHITECTURE lvl1_fifo_a OF lvl1_fifo IS
+-- synthesis translate_off
+component wrapped_lvl1_fifo
+ port (
+ clk: IN std_logic;
+ din: IN std_logic_VECTOR(31 downto 0);
+ rd_en: IN std_logic;
+ rst: IN std_logic;
+ wr_en: IN std_logic;
+ data_count: OUT std_logic_VECTOR(13 downto 0);
+ dout: OUT std_logic_VECTOR(31 downto 0);
+ empty: OUT std_logic;
+ full: OUT std_logic);
+end component;
+
+-- Configuration specification
+ for all : wrapped_lvl1_fifo use entity XilinxCoreLib.fifo_generator_v3_3(behavioral)
+ generic map(
+ c_rd_freq => 100,
+ c_wr_response_latency => 1,
+ c_has_srst => 0,
+ c_has_rd_data_count => 0,
+ c_din_width => 32,
+ c_has_wr_data_count => 0,
+ c_implementation_type => 0,
+ c_family => "virtex4",
+ c_has_wr_rst => 0,
+ c_wr_freq => 100,
+ c_underflow_low => 0,
+ c_has_meminit_file => 0,
+ c_has_overflow => 0,
+ c_preload_latency => 1,
+ c_dout_width => 32,
+ c_rd_depth => 16384,
+ c_default_value => "BlankString",
+ c_mif_file_name => "BlankString",
+ c_has_underflow => 0,
+ c_has_rd_rst => 0,
+ c_has_almost_full => 0,
+ c_has_rst => 1,
+ c_data_count_width => 14,
+ c_has_wr_ack => 0,
+ c_use_ecc => 0,
+ c_wr_ack_low => 0,
+ c_common_clock => 1,
+ c_rd_pntr_width => 14,
+ c_has_almost_empty => 0,
+ c_rd_data_count_width => 14,
+ c_enable_rlocs => 0,
+ c_wr_pntr_width => 14,
+ c_overflow_low => 0,
+ c_prog_empty_type => 0,
+ c_optimization_mode => 0,
+ c_wr_data_count_width => 14,
+ c_preload_regs => 0,
+ c_dout_rst_val => "0",
+ c_has_data_count => 1,
+ c_prog_full_thresh_negate_val => 16381,
+ c_wr_depth => 16384,
+ c_prog_empty_thresh_negate_val => 3,
+ c_prog_empty_thresh_assert_val => 2,
+ c_has_valid => 0,
+ c_init_wr_pntr_val => 0,
+ c_prog_full_thresh_assert_val => 16382,
+ c_use_fifo16_flags => 0,
+ c_has_backup => 0,
+ c_valid_low => 0,
+ c_prim_fifo_type => "8kx4",
+ c_count_type => 0,
+ c_prog_full_type => 0,
+ c_memory_type => 1);
+-- synthesis translate_on
+BEGIN
+-- synthesis translate_off
+U0 : wrapped_lvl1_fifo
+ port map (
+ clk => clk,
+ din => din,
+ rd_en => rd_en,
+ rst => rst,
+ wr_en => wr_en,
+ data_count => data_count,
+ dout => dout,
+ empty => empty,
+ full => full);
+-- synthesis translate_on
+
+END lvl1_fifo_a;
+
--- /dev/null
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.4e
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\ No newline at end of file
--- /dev/null
+--------------------------------------------------------------------------------
+-- This file is owned and controlled by Xilinx and must be used --
+-- solely for design, simulation, implementation and creation of --
+-- design files limited to Xilinx devices or technologies. Use --
+-- with non-Xilinx devices or technologies is expressly prohibited --
+-- and immediately terminates your license. --
+-- --
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
+-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
+-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
+-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
+-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
+-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
+-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
+-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
+-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
+-- FOR A PARTICULAR PURPOSE. --
+-- --
+-- Xilinx products are not intended for use in life support --
+-- appliances, devices, or systems. Use in such applications are --
+-- expressly prohibited. --
+-- --
+-- (c) Copyright 1995-2006 Xilinx, Inc. --
+-- All rights reserved. --
+--------------------------------------------------------------------------------
+-- You must compile the wrapper file ram16x1D_virtex.vhd when simulating
+-- the core, ram16x1D_virtex. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
+-- The synthesis directives "translate_off/translate_on" specified
+-- below are supported by Xilinx, Mentor Graphics and Synplicity
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+-- synthesis translate_off
+Library XilinxCoreLib;
+-- synthesis translate_on
+ENTITY ram16x1D_virtex IS
+ port (
+ A: IN std_logic_VECTOR(3 downto 0);
+ CLK: IN std_logic;
+ D: IN std_logic_VECTOR(11 downto 0);
+ WE: IN std_logic;
+ DPRA: IN std_logic_VECTOR(3 downto 0);
+ DPO: OUT std_logic_VECTOR(11 downto 0);
+ SPO: OUT std_logic_VECTOR(11 downto 0));
+END ram16x1D_virtex;
+
+ARCHITECTURE ram16x1D_virtex_a OF ram16x1D_virtex IS
+-- synthesis translate_off
+component wrapped_ram16x1D_virtex
+ port (
+ A: IN std_logic_VECTOR(3 downto 0);
+ CLK: IN std_logic;
+ D: IN std_logic_VECTOR(11 downto 0);
+ WE: IN std_logic;
+ DPRA: IN std_logic_VECTOR(3 downto 0);
+ DPO: OUT std_logic_VECTOR(11 downto 0);
+ SPO: OUT std_logic_VECTOR(11 downto 0));
+end component;
+
+-- Configuration specification
+ for all : wrapped_ram16x1D_virtex use entity XilinxCoreLib.C_DIST_MEM_V7_1(behavioral)
+ generic map(
+ c_qualify_we => 0,
+ c_mem_type => 2,
+ c_has_qdpo_rst => 0,
+ c_has_qspo => 0,
+ c_has_qspo_rst => 0,
+ c_has_dpo => 1,
+ c_has_qdpo_clk => 0,
+ c_has_d => 1,
+ c_qce_joined => 0,
+ c_width => 12,
+ c_reg_a_d_inputs => 0,
+ c_latency => 0,
+ c_has_spo => 1,
+ c_has_we => 1,
+ c_depth => 16,
+ c_has_i_ce => 0,
+ c_default_data_radix => 1,
+ c_default_data => "0",
+ c_has_dpra => 1,
+ c_has_clk => 1,
+ c_enable_rlocs => 1,
+ c_generate_mif => 1,
+ c_has_qspo_ce => 0,
+ c_addr_width => 4,
+ c_has_qdpo_srst => 0,
+ c_mux_type => 0,
+ c_has_spra => 0,
+ c_has_qdpo => 0,
+ c_reg_dpra_input => 0,
+ c_mem_init_file => "ram16x1D_virtex.mif",
+ c_has_qspo_srst => 0,
+ c_has_rd_en => 0,
+ c_read_mif => 0,
+ c_sync_enable => 0,
+ c_has_qdpo_ce => 0);
+-- synthesis translate_on
+BEGIN
+-- synthesis translate_off
+U0 : wrapped_ram16x1D_virtex
+ port map (
+ A => A,
+ CLK => CLK,
+ D => D,
+ WE => WE,
+ DPRA => DPRA,
+ DPO => DPO,
+ SPO => SPO);
+-- synthesis translate_on
+
+END ram16x1D_virtex_a;
+
--- /dev/null
+library IEEE;
+
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.NUMERIC_STD.all;
+--use work.support.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.all;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+
+
+ entity sdram_interface is
+
+ port (
+ --sdram
+ CLK_SDRAM : out std_logic;
+ CKE : out std_logic;
+ CS : out std_logic;
+ RAS : out std_logic;
+ CAS : out std_logic;
+ WE : out std_logic;
+ DQM : out std_logic_vector(3 downto 0);
+ BA : out std_logic_vector (1 downto 0);
+ A : out std_logic_vector(12 downto 0);
+ DQ : inout std_logic_vector(31 downto 0);
+ --internal
+ CLK : in std_logic;
+ RESET : in std_logic;
+ TRIGGER : in std_logic;
+ INTERNAL_DATA_IN : in std_logic_vector(31 downto 0);
+ INTERNAL_DATA_OUT : out std_logic_vector(31 downto 0);
+ INTERNAL_ADDRESS : in std_logic_vector(31 downto 0);
+ INTERNAL_MODE : in std_logic_vector(15 downto 0);
+ VALID_DATA_SENT : out std_logic;
+ DEBUGSTATE_MACHINE : out std_logic_vector(31 downto 0)
+ );
+
+ end sdram_interface;
+architecture sdram_interface of sdram_interface is
+ signal refresh_counter : std_logic_vector(7 downto 0);
+ signal init_counter : std_logic_vector(15 downto 0);
+ type SDRAM_INTERFACE_STATES is (INIT_1, INIT_2, INIT_3, INIT_4, INIT_5, INIT_6, INIT_7,
+ IDLE, SELF_REFRESH, AUTO_REFRESH, NOP, INHIBIT,PRECHARGE,
+ LOAD_MODE_REGISTER, READ_SDRAM_1, READ_SDRAM_2, READ_SDRAM_3,
+ READ_SDRAM_4, READ_SDRAM_5,READ_SDRAM_6, WRITE_SDRAM_1 ,WRITE_SDRAM_2 ,WRITE_SDRAM_3 ,
+ WRITE_SDRAM_4 ,CLEAR_REQUEST );
+ signal SDRAM_INTERFACE_fsm_currentstate,SDRAM_INTERFACE_fsm_nextstate : SDRAM_INTERFACE_STATES;
+ signal etrax_request_adress : std_logic_vector(31 downto 0);
+ signal etrax_request_data : std_logic_vector(31 downto 0);
+ signal etrax_request_mode : std_logic_vector(15 downto 0);
+ signal saved_sdram_data : std_logic_vector(31 downto 0);
+ signal reset_refresh_counter : std_logic;
+ signal CS_i, RAS_i, CAS_i, WE_i : std_logic;
+ signal A_i : std_logic_vector(31 downto 0);
+begin
+ SAVE_MODE_ADRES_AND_DATA: process (CLK, RESET, TRIGGER)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1'
+ -- or SDRAM_INTERFACE_fsm_currentstate = READ_SDRAM_1
+ -- or SDRAM_INTERFACE_fsm_currentstate = WRITE_SDRAM_1
+ or SDRAM_INTERFACE_fsm_currentstate = CLEAR_REQUEST
+
+ then
+-- etrax_request_adress <= (others => '0');
+-- etrax_request_data <= (others => '0');
+ etrax_request_mode <= (others => '0');
+ elsif TRIGGER = '1' then
+ etrax_request_adress <= INTERNAL_ADDRESS;
+ etrax_request_data <= INTERNAL_DATA_IN;
+ etrax_request_mode <= INTERNAL_MODE;
+ else
+ etrax_request_adress <= etrax_request_adress;
+ etrax_request_data <= etrax_request_data;
+ etrax_request_mode <= etrax_request_mode;
+ end if;
+ end if;
+ end process SAVE_MODE_ADRES_AND_DATA;
+ COUNTER_FOR_REFRESH : process (CLK, RESET,refresh_counter)
+ begin -- process COUNTER_FOR_REFRESH
+ if rising_edge(CLK) then
+ if RESET = '1' or reset_refresh_counter = '1'then
+ refresh_counter <= x"00";
+ elsif refresh_counter < x"ff" then
+ refresh_counter <= refresh_counter +1;
+ else
+ refresh_counter <= refresh_counter;
+ end if;
+ end if;
+ end process COUNTER_FOR_REFRESH;
+ COUNTER_FOR_INIT : process (CLK, RESET,refresh_counter)
+ begin -- process COUNTER_FOR_REFRESH
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ init_counter <= x"0000";
+ elsif refresh_counter < x"ffff" then
+ init_counter <= init_counter +1;
+ else
+ init_counter <= init_counter;
+ end if;
+ end if;
+ end process COUNTER_FOR_INIT;
+
+ SDRAM_FSM_CLOCK : process (CLK, RESET)
+ begin -- process DELAY_FSM_CLOCK
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ SDRAM_INTERFACE_fsm_currentstate <= INIT_1;
+ else
+ SDRAM_INTERFACE_fsm_currentstate <= SDRAM_INTERFACE_fsm_nextstate;
+ end if;
+ end if;
+ end process SDRAM_FSM_CLOCK;
+ SAVE_SDRAM_DATA: process (CLK, RESET,SDRAM_INTERFACE_fsm_currentstate)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ saved_sdram_data <= (others => '0');
+ elsif SDRAM_INTERFACE_fsm_currentstate = CLEAR_REQUEST then
+ saved_sdram_data <= DQ;
+ else
+ saved_sdram_data <= saved_sdram_data;
+ end if;
+ end if;
+ end process SAVE_SDRAM_DATA;
+ INTERNAL_DATA_OUT <= saved_sdram_data;
+ CKE <= '1';
+ CLK_SDRAM <= not CLK;
+ SDRAM_FSM : process (CLK,SDRAM_INTERFACE_fsm_currentstate,init_counter,refresh_counter,etrax_request_mode)
+ begin
+ CS <= '0';
+ RAS <= '1';
+ CAS <= '1';
+ WE <= '1';
+ DQM <= x"0";
+ A(12 downto 0) <= (others => '0');
+
+
+ DQ <= (others => 'Z');
+ BA <= "00";
+ VALID_DATA_SENT <= '0';
+ DEBUGSTATE_MACHINE(7 downto 0) <= x"00";
+ reset_refresh_counter <= '0';
+ case SDRAM_INTERFACE_fsm_currentstate is
+ when INIT_1 => --INHIBIT
+ CS <= '1';
+ RAS <= '0';
+ CAS <= '0';
+ WE <= '0';
+ DQM <= x"0";
+ A(9 downto 0) <= (others => '0');
+ A(10) <= '0';
+ DQ <= (others => 'Z');
+ BA <= "00";
+ VALID_DATA_SENT <= '0';
+ DEBUGSTATE_MACHINE(7 downto 0) <= x"01";
+ if init_counter = x"ffff" then
+ SDRAM_INTERFACE_fsm_nextstate <= INIT_2;
+ else
+ SDRAM_INTERFACE_fsm_nextstate <= INIT_1;
+ end if;
+ when INIT_2 => --PRECHARGE
+ CS <= '0';
+ RAS <= '0';
+ CAS <= '1';
+ WE <= '0';
+ DQM <= x"0";
+ A(9 downto 0) <= (others => '0');
+ A(10) <= '1';
+ DQ <= (others => 'Z');
+ BA <= "00";
+ VALID_DATA_SENT <= '0';
+ DEBUGSTATE_MACHINE(7 downto 0) <= x"02";
+ SDRAM_INTERFACE_fsm_nextstate <= INIT_3;
+ when INIT_3 => --NOP(20ns )
+ CS <= '0';
+ RAS <= '1';
+ CAS <= '1';
+ WE <= '1';
+ DQM <= x"0";
+ A(9 downto 0) <= (others => '0');
+ A(10) <= '1';
+ DQ <= (others => 'Z');
+ BA <= "00";
+ VALID_DATA_SENT <= '0';
+ DEBUGSTATE_MACHINE(7 downto 0) <= x"03";
+ SDRAM_INTERFACE_fsm_nextstate <= INIT_4;
+ when INIT_4 => --NOP
+ CS <= '0';
+ RAS <= '1';
+ CAS <= '1';
+ WE <= '1';
+ DQM <= x"0";
+ A(9 downto 0) <= (others => '0');
+ A(10) <= '1';
+ DQ <= (others => 'Z');
+ BA <= "00";
+ VALID_DATA_SENT <= '0';
+ DEBUGSTATE_MACHINE(7 downto 0) <= x"04";
+ SDRAM_INTERFACE_fsm_nextstate <= INIT_5;
+ when INIT_5 => --AUTO_REFRESH
+ CS <= '0';
+ RAS <= '0';
+ CAS <= '0';
+ WE <= '1';
+ DQM <= x"0";
+ A(9 downto 0) <= (others => '0');
+ A(10) <= '1';
+ DQ <= (others => 'Z');
+ BA <= "00";
+ VALID_DATA_SENT <= '0';
+ DEBUGSTATE_MACHINE(7 downto 0) <= x"05";
+ SDRAM_INTERFACE_fsm_nextstate <= INIT_6;
+ when INIT_6 => --AUTO_REFRESH
+ CS <= '0';
+ RAS <= '0';
+ CAS <= '0';
+ WE <= '1';
+ DQM <= x"0";
+ A(9 downto 0) <= (others => '0');
+ A(10) <= '1';
+ DQ <= (others => 'Z');
+ BA <= "00";
+ VALID_DATA_SENT <= '0';
+ DEBUGSTATE_MACHINE(7 downto 0) <= x"06";
+ SDRAM_INTERFACE_fsm_nextstate <= INIT_7;
+ when INIT_7 => --MODE_REGISTER
+ CS <= '0';
+ RAS <= '0';
+ CAS <= '0';
+ WE <= '0';
+ DQM <= x"0";
+ A(9 downto 0) <= "1000100000"; --single access,std.oper,CAS=2,Sequenctial,burstlenght=1
+ A(10) <= '1'; --enables precharge feature
+ DQ <= (others => 'Z');
+ BA <= "00";
+ VALID_DATA_SENT <= '0';
+ DEBUGSTATE_MACHINE(7 downto 0) <= x"07";
+ SDRAM_INTERFACE_fsm_nextstate <= IDLE;
+ when IDLE =>
+ CS <= '0';
+ RAS <= '1';
+ CAS <= '1';
+ WE <= '1';
+ DQM <= x"0";
+ A(9 downto 0) <= (others => '0');
+ A(10) <= '1';
+ DQ <= (others => 'Z');
+ BA <= "00";
+ VALID_DATA_SENT <= '0';
+ reset_refresh_counter <= '0';
+ DEBUGSTATE_MACHINE(7 downto 0) <= x"00";
+
+ if refresh_counter = x"ff" then
+ SDRAM_INTERFACE_fsm_nextstate <= AUTO_REFRESH;
+ elsif etrax_request_mode(15 downto 0)= x"8002" then
+ SDRAM_INTERFACE_fsm_nextstate <= READ_SDRAM_1;
+ elsif etrax_request_mode(15 downto 0)= x"0002" then
+ SDRAM_INTERFACE_fsm_nextstate <= WRITE_SDRAM_1;
+ elsif etrax_request_mode(15 downto 0)= x"1002" then --part_of_address
+ SDRAM_INTERFACE_fsm_nextstate <= LOAD_MODE_REGISTER; --and other
+ --should be
+ --added -
+ --burst read,burst write
+ else
+ SDRAM_INTERFACE_fsm_nextstate <= IDLE;
+ end if;
+--read
+ when READ_SDRAM_1 => --ACTIVE
+ CS <= '0';
+ RAS <= '0';
+ CAS <= '1';
+ WE <= '1';
+ DQM <= x"0";
+ A(12 downto 0) <= etrax_request_adress(12 downto 0);
+-- A(10) <= '1';
+ DQ <= (others => 'Z');
+ BA <= etrax_request_adress(14 downto 13);
+ VALID_DATA_SENT <= '0';
+ DEBUGSTATE_MACHINE(7 downto 0) <= x"08";
+ SDRAM_INTERFACE_fsm_nextstate <= READ_SDRAM_2;
+ when READ_SDRAM_2 => --NOP
+ CS <= '0';
+ RAS <= '1';
+ CAS <= '1';
+ WE <= '1';
+ DQM <= x"0";
+ A(9 downto 0) <=(others => '0');
+ A(10) <= '1';
+ DQ <= (others => 'Z');
+ BA <= etrax_request_adress(14 downto 13);
+ VALID_DATA_SENT <= '0';
+ DEBUGSTATE_MACHINE(7 downto 0) <= x"09";
+ SDRAM_INTERFACE_fsm_nextstate <= READ_SDRAM_3;
+ when READ_SDRAM_3 => --NOP
+ CS <= '0';
+ RAS <= '1';
+ CAS <= '1';
+ WE <= '1';
+ DQM <= x"0";
+ A(9 downto 0) <= (others => '0');
+ A(10) <= '1';
+ DQ <= (others => 'Z');
+ BA <= "00";
+ VALID_DATA_SENT <= '0';
+ DEBUGSTATE_MACHINE(7 downto 0) <= x"0a";
+ SDRAM_INTERFACE_fsm_nextstate <= READ_SDRAM_4;
+ when READ_SDRAM_4 => --READ
+ CS <= '0';
+ RAS <= '1';
+ CAS <= '0';
+ WE <= '1';
+ DQM <= x"0";
+ A(9 downto 0) <= etrax_request_adress(24 downto 15);
+ A(10) <= '1';
+ DQ <= (others => 'Z');
+ BA <= etrax_request_adress(14 downto 13);
+ VALID_DATA_SENT <= '0';
+ DEBUGSTATE_MACHINE(7 downto 0) <= x"0b";
+ SDRAM_INTERFACE_fsm_nextstate <= READ_SDRAM_5;
+ when READ_SDRAM_5 => --NOP
+ CS <= '0';
+ RAS <= '1';
+ CAS <= '1';
+ WE <= '1';
+ DQM <= x"0";
+ A(9 downto 0) <= (others => '0');
+ A(10) <= '1';
+ DQ <= (others => 'Z');
+ BA <= "00";
+ VALID_DATA_SENT <= '0';
+ DEBUGSTATE_MACHINE(7 downto 0) <= x"0c";
+ SDRAM_INTERFACE_fsm_nextstate <= READ_SDRAM_6;--CLEAR_REQUEST;
+ --
+ when READ_SDRAM_6 => --NOP
+ CS <= '0';
+ RAS <= '1';
+ CAS <= '1';
+ WE <= '1';
+ DQM <= x"0";
+ A(9 downto 0) <= (others => '0');
+ A(10) <= '1';
+ DQ <= (others => 'Z');
+ BA <= "00";
+ VALID_DATA_SENT <= '0';
+ DEBUGSTATE_MACHINE(7 downto 0) <= x"0d";
+ SDRAM_INTERFACE_fsm_nextstate <= CLEAR_REQUEST;
+
+--write
+ when WRITE_SDRAM_1 => --ACTIVE
+ CS <= '0';
+ RAS <= '0';
+ CAS <= '1';
+ WE <= '1';
+ DQM <= x"0";
+ A(12 downto 0) <= etrax_request_adress(12 downto 0);
+-- A(10) <= '1';
+ DQ <= (others => 'Z');
+ BA <= etrax_request_adress(14 downto 13);
+ VALID_DATA_SENT <= '0';
+ DEBUGSTATE_MACHINE(7 downto 0) <= x"0d";
+ SDRAM_INTERFACE_fsm_nextstate <= WRITE_SDRAM_2;
+ when WRITE_SDRAM_2 => --NOP
+ CS <= '0';
+ RAS <= '1';
+ CAS <= '1';
+ WE <= '1';
+ DQM <= x"0";
+ A(9 downto 0) <= (others => '0');
+ A(10) <= '1'; --precharge
+ DQ <= (others => 'Z');
+ BA <= etrax_request_adress(14 downto 13);
+ VALID_DATA_SENT <= '0';
+ DEBUGSTATE_MACHINE(7 downto 0) <= x"0e";
+ SDRAM_INTERFACE_fsm_nextstate <= WRITE_SDRAM_3;
+ when WRITE_SDRAM_3 => --NOP
+ CS <= '0';
+ RAS <= '1';
+ CAS <= '1';
+ WE <= '1';
+ DQM <= x"0";
+ A(9 downto 0) <= (others => '0');
+ A(10) <= '1';
+ DQ <= (others => 'Z');
+ BA <= "00";
+ VALID_DATA_SENT <= '0';
+ DEBUGSTATE_MACHINE(7 downto 0) <= x"0f";
+ SDRAM_INTERFACE_fsm_nextstate <= WRITE_SDRAM_4;
+ when WRITE_SDRAM_4 => --WRITE
+ CS <= '0';
+ RAS <= '1';
+ CAS <= '0';
+ WE <= '0';
+ DQM <= x"0";
+ A(9 downto 0) <= etrax_request_adress(24 downto 15);
+ A(10) <= '1';
+ DQ <= etrax_request_data;
+ BA <= etrax_request_adress(14 downto 13);
+ VALID_DATA_SENT <= '0';
+ DEBUGSTATE_MACHINE(7 downto 0) <= x"10";
+ SDRAM_INTERFACE_fsm_nextstate <= CLEAR_REQUEST;
+ when AUTO_REFRESH =>
+ CS <= '0';
+ RAS <= '0';
+ CAS <= '0';
+ WE <= '1';
+ DQM <= x"0";
+ A(9 downto 0) <= (others => '0');
+ A(10) <= '1';
+ DQ <= (others => 'Z');
+ BA <= "00";
+ VALID_DATA_SENT <= '0';
+ DEBUGSTATE_MACHINE(7 downto 0) <= x"11";
+ reset_refresh_counter <= '1';
+ SDRAM_INTERFACE_fsm_nextstate <= IDLE;
+ when CLEAR_REQUEST =>
+ CS <= '0';
+ RAS <= '1';
+ CAS <= '1';
+ WE <= '1';
+ DQM <= x"0";
+ A(9 downto 0) <= (others => '0');
+ A(10) <= '1';
+ DQ <= (others => 'Z');
+ BA <= "00";
+ VALID_DATA_SENT <= '1';
+ DEBUGSTATE_MACHINE(7 downto 0) <= x"12";
+ SDRAM_INTERFACE_fsm_nextstate <= IDLE;
+ when others =>
+ SDRAM_INTERFACE_fsm_nextstate <= IDLE;
+ end case;
+ end process;
+end sdram_interface;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
-
library UNISIM;
use UNISIM.VComponents.all;
entity tdc_interface is
COUNTER_f : in std_logic_vector(31 downto 0);
COUNTER_g : in std_logic_vector(31 downto 0);
COUNTER_h : in std_logic_vector(31 downto 0);
- COUNTER_i : in std_logic_vector(31 downto 0);
- COUNTER_j : in std_logic_vector(31 downto 0);
- COUNTER_k : in std_logic_vector(31 downto 0);
- COUNTER_l : in std_logic_vector(31 downto 0);
- COUNTER_m : in std_logic_vector(31 downto 0);
LVL2_TRIGGER : in std_logic_vector(1 downto 0);
TDC_DATA_OUT : out std_logic_vector (31 downto 0); --data to ETRAX (LVL2)
TDC_DATA_VALID : out std_logic; -- The TDC_DATA_OUT can be written
ETRAX_IS_READY_TO_READ : in std_logic;
- TDC_LVL1_BUSY : out std_logic;
- TDC_LVL2_BUSY : out std_logic;
+ LVL1_BUSY : out std_logic;
+ LVL2_BUSY : out std_logic;
TDC_REGISTER_00 : out std_logic_vector(31 downto 0);
+ TDC_REGISTER_01 : out std_logic_vector(31 downto 0);
+ TDC_REGISTER_02 : out std_logic_vector(31 downto 0);
+ TDC_REGISTER_03 : out std_logic_vector(31 downto 0);
+ TDC_REGISTER_04 : out std_logic_vector(31 downto 0);
BUNCH_RESET : out std_logic;
EVENT_RESET : out std_logic;
- READ_ADRESS_END_UP : in std_logic;
- MY_LVL1_COUNTER : in std_logic_vector(7 downto 0)
+ READ_ADRESS_END_UP : out std_logic; --here
+ DELAY_TRIGGER : in std_logic_vector(7 downto 0);
+ TDC_START : out std_logic;
+ TRIGGER_WITHOUT_HADES : in std_logic;
+ TRIGGER_WITH_GEN_EN : in std_logic;
+ TRIGGER_WITH_GEN : in std_logic
);
end tdc_interface;
architecture tdc_interface of tdc_interface is
signal_in : in std_logic;
pulse : out std_logic);
end component;
- component lvl1_memory
- port (
- addra : IN std_logic_VECTOR(14 downto 0);
- addrb : IN std_logic_VECTOR(14 downto 0);
- clka : IN std_logic;
- clkb : IN std_logic;
- dina : IN std_logic_VECTOR(31 downto 0);
- doutb : OUT std_logic_VECTOR(31 downto 0);
- wea : IN std_logic);
- end component;
component up_down_counter_16_bit
port (
QOUT : out std_logic_vector(15 downto 0);
I: in std_ulogic
);
end component;
-component DCM_ADV
- generic( CLK_FEEDBACK : string := "1X";
- CLKDV_DIVIDE : real := 2.0;
- CLKFX_DIVIDE : integer := 1;
- CLKFX_MULTIPLY : integer := 4;
- CLKIN_DIVIDE_BY_2 : boolean := FALSE;
- CLKIN_PERIOD : real := 10.0;
- CLKOUT_PHASE_SHIFT : string := "NONE";
- DCM_AUTOCALIBRATION : boolean := TRUE;
- DCM_PERFORMANCE_MODE : string := "MAX_SPEED";
- DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
- DFS_FREQUENCY_MODE : string := "LOW";
- DLL_FREQUENCY_MODE : string := "LOW";
- DUTY_CYCLE_CORRECTION : boolean := TRUE;
- FACTORY_JF : bit_vector := x"F0F0";
- PHASE_SHIFT : integer := 0;
- STARTUP_WAIT : boolean := FALSE;
- SIM_DEVICE : string := "VIRTEX4");
- port ( CLKIN : in std_logic;
- CLKFB : in std_logic;
- DADDR : in std_logic_vector (6 downto 0);
- DI : in std_logic_vector (15 downto 0);
- DWE : in std_logic;
- DEN : in std_logic;
- DCLK : in std_logic;
- RST : in std_logic;
- PSEN : in std_logic;
- PSINCDEC : in std_logic;
- PSCLK : in std_logic;
- CLK0 : out std_logic;
- CLK90 : out std_logic;
- CLK180 : out std_logic;
- CLK270 : out std_logic;
- CLKDV : out std_logic;
- CLK2X : out std_logic;
- CLK2X180 : out std_logic;
- CLKFX : out std_logic;
- CLKFX180 : out std_logic;
- DRDY : out std_logic;
- DO : out std_logic_vector (15 downto 0);
- LOCKED : out std_logic;
- PSDONE : out std_logic);
- end component;
-
-
- signal tdc_ready : std_logic:='0';
- signal write_eneble_and_tdc_ready : std_logic_vector(23 downto 0):=(others => '0');
- signal write_address : std_logic_vector(14 downto 0):=(others => '0');
- signal write_address_tdc_data : std_logic_vector(14 downto 0):=(others => '0');
- signal read_address : std_logic_vector(14 downto 0):=(others => '0');
- signal data_to_lvl1_fifo : std_logic_vector (31 downto 0):=(others => '0');
- signal tdc_ready_or_add_word : std_logic:='0';
+ component simpleupcounter_8bit
+ port (
+ QOUT : out std_logic_vector(7 downto 0);
+ UP : in std_logic;
+ CLK : in std_logic;
+ CLR : in std_logic);
+ end component;
+ component lvl1_buffer
+ port (
+ din : IN std_logic_VECTOR(31 downto 0);
+ rd_clk : IN std_logic;
+ rd_en : IN std_logic;
+ rst : IN std_logic;
+ wr_clk : IN std_logic;
+ wr_en : IN std_logic;
+ dout : OUT std_logic_VECTOR(31 downto 0);
+ empty : OUT std_logic;
+ full : OUT std_logic;
+ rd_data_count : OUT std_logic_VECTOR(9 downto 0));
+ end component;
+ component lvl1_fifo
+ port (
+ clk : IN std_logic;
+ din : IN std_logic_VECTOR(31 downto 0);
+ rd_en : IN std_logic;
+ rst : IN std_logic;
+ wr_en : IN std_logic;
+ data_count : OUT std_logic_VECTOR(13 downto 0);
+ dout : OUT std_logic_VECTOR(31 downto 0);
+ empty : OUT std_logic;
+ full : OUT std_logic);
+ end component;
+ signal tdc_ready : std_logic;
signal counter_a_i : std_logic_vector(31 downto 0);
signal counter_b_i : std_logic_vector(31 downto 0);
signal counter_c_i : std_logic_vector(31 downto 0);
signal counter_f_i : std_logic_vector(31 downto 0);
signal counter_g_i : std_logic_vector(31 downto 0);
signal counter_h_i : std_logic_vector(31 downto 0);
- signal counter_i_i : std_logic_vector(31 downto 0);
- signal counter_j_i : std_logic_vector(31 downto 0);
- signal counter_k_i : std_logic_vector(31 downto 0);
- signal counter_l_i : std_logic_vector(31 downto 0);
- signal counter_m_i : std_logic_vector(31 downto 0);
signal add_data_counter : std_logic_vector(7 downto 0):=(others => '0');
- signal add_data_pulse : std_logic:='0';
- signal received_tdc_token_pulse : std_logic:='0';
- signal data_selector : std_logic_vector(4 downto 0):=(others => '0');
- signal saved_address : std_logic_vector(14 downto 0):=(others => '0');
+ signal add_data_pulse : std_logic;
signal first_header : std_logic_vector(31 downto 0):=(others => '0');
signal second_header : std_logic_vector(31 downto 0):=(others => '0');
signal words_in_event : std_logic_vector(15 downto 0):=(others => '0');
- signal read_data_address_up : std_logic:='0';
- signal word_count_up : std_logic:='0';
- signal word_count_up_clk : std_logic := '0';
- signal word_count_up_pulse : std_logic:='0';
- signal how_many_words_in_fifo : std_logic_vector(9 downto 0):=(others => '0');
- signal how_many_words_in_ram : std_logic_vector(9 downto 0):=(others => '0');
- signal tdc_data_valid_i : std_logic:='0';
- signal lvl2_trigger_pulse : std_logic;
- signal how_many_words_in_event : std_logic_vector(19 downto 0);
- signal lvl2_valid_saved : std_logic;
- signal start_tdc_readout_pulse : std_logic;
- signal start_tdc_readout_90_deg : std_logic;
- signal word_count_up_synch : std_logic;
- signal doutb_i : std_logic_vector(31 downto 0);
- signal end_event_marker_in_i : std_logic;
- signal first_trigger : std_logic;
- signal clkfx_i : std_logic;
- signal clkfx_bufg_i : std_logic;
- signal clk0_i : std_logic;
- signal clkfb_i : std_logic;
- signal word_count_down_clk: std_logic;
- signal word_count_down_pulse: std_logic;
- signal locked_i : std_logic;
- signal word_ram_counter_up : std_logic_vector(9 downto 0);
- signal word_ram_counter_down : std_logic_vector(9 downto 0);
- signal lvl1_tag_minus_one : std_logic_vector(7 downto 0);
- signal saved_beg_address : std_logic_vector( 14 downto 0) ;
- signal lvl2_trigger_pulse_1delay : std_logic;
- signal lvl2_trigger_pulse_2delay : std_logic;
- signal lvl2_trigger_pulse_3delay : std_logic;
- signal lvl2_trigger_pulse_4delay : std_logic;
- signal lvl2_trigger_pulse_delay : std_logic;
+ signal tdc_data_valid_i : std_logic;
+ signal how_many_words_in_event : std_logic_vector(16 downto 0);
+ signal delay_up : std_logic;
+ signal delay_clr : std_logic;
+ signal delay_qout : std_logic_vector(7 downto 0);
+ signal lvl1_trigger_pulse_start : std_logic;
+ signal lvl1_trigger_pulse_delay : std_logic;
+ type DELAY_FSM_TRIGG is
+ (IDLE ,DELAY_1,DELAY_2);
+ signal delay_fsm_currentstate, delay_fsm_nextstate: DELAY_FSM_TRIGG;
+ type LVL1_START_FSM is
+ (IDLE, SEND_LVL1_TRIGG_1, SEND_LVL1_TRIGG_2, SEND_LVL1_TRIGG_3, SEND_LVL1_TRIGG_4, WAIT_FOR_TOKEN, SAVE_ADD_DATA_1, SAVE_ADD_DATA_2, SAVE_ADD_DATA_3, SAVE_ADD_DATA_4, SEND_LVL2_TRIGG);
+ signal LVL1_START_fsm_currentstate, LVL1_START_fsm_nextstate : LVL1_START_FSM;
+ type LVL2_START_FSM is
+ (IDLE, READOUT_WORD1, READOUT_WORD2 ,SAVE_EVENT_SIZE ,SEND_DATA1);
+ signal LVL2_START_fsm_currentstate, LVL2_START_fsm_nextstate : LVL2_START_FSM;
+ signal lvl1_busy_i : std_logic;
+ signal lvl1_busy_ff : std_logic;
+ signal lvl1_memory_busy_i : std_logic;
+ signal lvl2_busy_i : std_logic;
+ signal lvl1_trigger_pulse : std_logic;
+ signal lvl1_tdc_trigg_i : std_logic;
+ signal lvl1_tdc_trigg_ff : std_logic;
+
+ signal trigger_register_00_i : std_logic_vector(5 downto 0);
+ signal lvl2_busy_end_pulse : std_logic;
+ signal not_tdc_data_valid_i : std_logic;
+
+ signal not_tdc_clk : std_logic;
+ signal test_counter_0 : std_logic_vector(7 downto 0);
+ signal test_counter_1 : std_logic_vector(7 downto 0);
+ signal test_counter_2 : std_logic_vector(7 downto 0);
+ signal test_counter_3 : std_logic_vector(7 downto 0);
+ signal add_data_i : std_logic_vector(31 downto 0);
+ signal lvl1_fifo_out : std_logic_vector(31 downto 0);
+ signal lvl1_fifo_in : std_logic_vector(31 downto 0);
+ signal lvl1_fifo_counter : std_logic_vector(13 downto 0);
+ signal lvl1_fifo_empty : std_logic;
+ signal lvl1_fifo_full : std_logic;
+ signal lvl1_fifo_wr_en : std_logic;
+ signal lvl1_fifo_rd_en : std_logic;
+ signal lvl1_buffer_out : std_logic_vector(31 downto 0);
+ signal lvl1_buffer_in : std_logic_vector(31 downto 0);
+ signal lvl1_buffer_counter : std_logic_vector(9 downto 0);
+ signal lvl1_buffer_empty : std_logic;
+ signal lvl1_buffer_full : std_logic;
+ signal lvl1_buffer_wr_en : std_logic;
+ signal lvl1_buffer_rd_en : std_logic;
+ signal lvl1_or_lvl2_is_busy : std_logic;
+ signal trigger_with_gen_pulse : std_logic;
+ signal lvl1_tag_minus1 : std_logic_vector(7 downto 0);
+ signal lvl2_debug : std_logic_vector(2 downto 0);
+ signal tdc_start_i : std_logic;
+ signal lvl2_busy_start_pulse : std_logic;
+
+ signal lvl1_tdc_trigg_i_fsm : std_logic;
+ signal lvl1_fifo_wr_en_fsm : std_logic;
+ signal lvl1_fifo_in_fsm : std_logic_vector(31 downto 0);
+ signal lvl1_buffer_rd_en_fsm : std_logic;
+ signal lvl1_busy_i_fsm : std_logic;
+ signal lvl1_fifo_rd_en_fsm : std_logic;
+ signal tdc_data_valid_i_fsm : std_logic;
+ signal lvl1_data_counter : std_logic_vector(15 downto 0):=(others => '0');
begin
+ READ_ADRESS_END_UP <= lvl2_busy_end_pulse; --here
TDC_REGISTER : process (CLK, RESET)
begin
if rising_edge(CLK) then
- if RESET = '1' then
- TDC_REGISTER_00 <= (others => '0');
- else
TDC_REGISTER_00(0) <= A_TDC_ERROR;
TDC_REGISTER_00(1) <= B_TDC_ERROR;
TDC_REGISTER_00(2) <= C_TDC_ERROR;
TDC_REGISTER_00(3) <= D_TDC_ERROR;
- TDC_REGISTER_00(19 downto 4) <= "000000"&how_many_words_in_fifo;
- TDC_REGISTER_00(20) <= clkfx_bufg_i;
- TDC_REGISTER_00(30 downto 21) <= (others => '0');
- TDC_REGISTER_00(31) <= locked_i;
- end if;
+ TDC_REGISTER_00(13 downto 4) <= lvl1_buffer_counter;
+ TDC_REGISTER_00(14) <= lvl1_busy_i;
+ TDC_REGISTER_00(15) <= lvl1_or_lvl2_is_busy;--lvl1_memory_busy_i;
+ TDC_REGISTER_00(30) <= lvl1_fifo_wr_en;
+ TDC_REGISTER_00(31) <= lvl2_busy_i;
+ TDC_REGISTER_00(29 downto 16) <= lvl1_fifo_counter;
+ TDC_REGISTER_01(26 downto 0) <= lvl2_debug & trigger_register_00_i(5 downto 2) & "00" & trigger_register_00_i(1 downto 0)& how_many_words_in_event(15 downto 0);
+ TDC_REGISTER_01(31 downto 27) <= (others => '0');
+ TDC_REGISTER_02(31 downto 0) <= lvl1_buffer_out;--lvl1_fifo_out;
+ TDC_REGISTER_03(31 downto 0) <= lvl1_fifo_out;
+ TDC_REGISTER_04(31 downto 0) <= test_counter_3 & test_counter_2 & test_counter_1 & test_counter_0;
end if;
end process TDC_REGISTER;
- A_TDC_POWERUP <= '1';
- B_TDC_POWERUP <= '1';
- C_TDC_POWERUP <= '1';
- D_TDC_POWERUP <= '1';
- SEND_TDC_TOKEN <= start_tdc_readout_90_deg;
- tdc_ready <= A_TDC_READY or B_TDC_READY or C_TDC_READY or D_TDC_READY;
- GET_TDC_DATA <= '1';
- LVL1_MEMORY_32kW: lvl1_memory
- port map (
- addra => write_address,--addra_i,
- addrb => read_address,--addrb_i,
- clka => TDC_CLK,--clka_i,
- clkb => CLK,--clkb_i,
- dina => data_to_lvl1_fifo,
- doutb => doutb_i,--TDC_DATA_OUT,
- wea => tdc_ready_or_add_word);
- BUNCH_RESET_90deg_shift: process (TDC_CLK, RESET)
+ A_TDC_POWERUP <= '1';
+ B_TDC_POWERUP <= '1';
+ C_TDC_POWERUP <= '1';
+ D_TDC_POWERUP <= '1';
+ tdc_ready <= A_TDC_READY or B_TDC_READY or C_TDC_READY or D_TDC_READY;
+ GET_TDC_DATA <= '1';
+ SEND_BUNCH_RESET: process (TDC_CLK, RESET)
begin
- if falling_edge(TDC_CLK) then
+ if rising_edge(TDC_CLK) then
if RESET = '1' then
BUNCH_RESET <= '1';
EVENT_RESET <= '1';
else
EVENT_RESET <= '0';
- BUNCH_RESET <= received_tdc_token_pulse;
+ BUNCH_RESET <= RECEIVED_TDC_TOKEN;
end if;
end if;
- end process BUNCH_RESET_90deg_shift;
-
- TDC_DATA_OUT <= doutb_i;
+ end process SEND_BUNCH_RESET;
-----------------------------------------------------------------------------
----------------------------------------------------------------------------
- -- LVL1 logic only TDC_CLK domain
+ -- LVL1 logic
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
- WRITE_ADDRESS_CHANGE : process (TDC_CLK, RESET,tdc_ready,add_data_pulse)
- begin
- if rising_edge(TDC_CLK) then
+
+ LVL1_BUFF: lvl1_buffer
+ port map (
+ din => TDC_DATA_IN,
+ rd_clk => CLK,
+ rd_en => lvl1_buffer_rd_en,
+ rst => RESET,
+ wr_clk => TDC_CLK,
+ wr_en => lvl1_buffer_wr_en,
+ dout => lvl1_buffer_out,
+ empty => lvl1_buffer_empty,
+ full => lvl1_buffer_full,
+ rd_data_count => lvl1_buffer_counter);
+ lvl1_buffer_wr_en <= tdc_ready;
+ lvl1_buffer_in <= TDC_DATA_IN;
+ LVL1_FIFO_LVL2: lvl1_fifo
+ port map (
+ clk => CLK,
+ din => lvl1_fifo_in,
+ rd_en => lvl1_fifo_rd_en,
+ rst => RESET,
+ wr_en => lvl1_fifo_wr_en,
+ data_count => lvl1_fifo_counter,
+ dout => lvl1_fifo_out,
+ empty => lvl1_fifo_empty,
+ full => lvl1_fifo_full);
+ TDC_DATA_OUT <= lvl1_fifo_out;
+ lvl1_trigger_pulse <= START_TDC_READOUT;
+ DELAY_COUNTER : simpleupcounter_8bit
+ port map (
+ CLK => CLK,
+ UP => delay_up,
+ CLR => delay_clr,
+ QOUT => delay_qout
+ );
+ DELAY_FSM_CLOCK : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
if RESET = '1' then
- write_address_tdc_data <= "0000000" & HOW_MANY_ADD_DATA + 1; --+1_beacause_data_selector_count_to_0_!
- elsif tdc_ready = '1' or add_data_pulse = '1' then
- write_address_tdc_data <= write_address_tdc_data + 1;
+ delay_fsm_currentstate <= IDLE;
else
- write_address_tdc_data <= write_address_tdc_data;
+ delay_fsm_currentstate <= delay_fsm_nextstate;
end if;
end if;
- end process WRITE_ADDRESS_CHANGE;
- SAVE_DATA : process (CLK, RESET,START_TDC_READOUT )
+ end process DELAY_FSM_CLOCK;
+ -- purpose: delay trigger whitch is sending to TDC
+ TO_DELAY_TRIGG : process (delay_fsm_currentstate,lvl1_trigger_pulse,delay_qout,DELAY_TRIGGER)
+ begin
+ case (delay_fsm_currentstate) is
+ when IDLE =>
+ trigger_register_00_i(1 downto 0) <= "01";
+ lvl1_trigger_pulse_delay <= '0';
+ delay_clr <= '1';
+ delay_up <= '0';
+ if lvl1_trigger_pulse = '1' and DELAY_TRIGGER /= x"00" then
+ delay_fsm_nextstate <= DELAY_1;
+ else
+ delay_fsm_nextstate <= IDLE;
+ end if;
+ when DELAY_1 =>
+ trigger_register_00_i(1 downto 0) <= "10";
+ lvl1_trigger_pulse_delay <= '0';
+ delay_clr <= '0';
+ delay_up <= '1';
+ if delay_qout = DELAY_TRIGGER(7 downto 0) then
+ delay_fsm_nextstate <= DELAY_2;
+ else
+ delay_fsm_nextstate <= DELAY_1;
+ end if;
+ when DELAY_2 =>
+ trigger_register_00_i(1 downto 0) <= "11";
+ lvl1_trigger_pulse_delay <= '1';
+ delay_clr <= '1';
+ delay_up <= '0';
+ delay_fsm_nextstate <= IDLE;
+ when others =>
+ trigger_register_00_i(1 downto 0) <= "11";
+ lvl1_trigger_pulse_delay <= '0';
+ delay_clr <= '1';
+ delay_up <= '0';
+ delay_fsm_nextstate <= IDLE;
+ end case;
+ end process TO_DELAY_TRIGG;
+ lvl1_trigger_pulse_start <= lvl1_trigger_pulse when DELAY_TRIGGER = x"00" else lvl1_trigger_pulse_delay;
+ LVL1_START : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ LVL1_START_fsm_currentstate <= IDLE;
+ lvl1_tdc_trigg_i <= '0';
+ lvl1_fifo_wr_en <= '0';
+ lvl1_fifo_in <= lvl1_buffer_out;
+ lvl1_buffer_rd_en <= '0';
+ lvl1_busy_i <= '0';
+ lvl1_tdc_trigg_i <= '0';
+ else
+ LVL1_START_fsm_currentstate <= LVL1_START_fsm_nextstate;
+ lvl1_tdc_trigg_i <= lvl1_tdc_trigg_i_fsm;
+ lvl1_fifo_wr_en <= lvl1_fifo_wr_en_fsm;
+ lvl1_fifo_in <= lvl1_fifo_in_fsm ;
+ lvl1_buffer_rd_en <= lvl1_buffer_rd_en_fsm;
+ lvl1_busy_i <= lvl1_busy_i_fsm;
+ lvl1_tdc_trigg_i <= lvl1_tdc_trigg_i_fsm;
+ end if;
+ end if;
+ end process LVL1_START;
+
+ TRIGGER_WITHOUT_HADES_PULSER : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => TRIGGER_WITH_GEN,
+ pulse => trigger_with_gen_pulse);
+ LVL1_START_FSM_PROC : process (LVL1_START_fsm_currentstate,RECEIVED_TDC_TOKEN, trigger_with_gen_pulse, lvl1_trigger_pulse_start, add_data_counter, lvl1_data_counter, lvl1_or_lvl2_is_busy, how_many_add_data, lvl1_code, lvl1_buffer_empty, trigger_with_gen_en, add_data_i, second_header, first_header, lvl1_buffer_out)
+ begin
+ lvl1_tdc_trigg_i_fsm <= '0';
+ lvl1_fifo_wr_en_fsm <= '0';
+ lvl1_fifo_in_fsm <= lvl1_buffer_out;
+ lvl1_buffer_rd_en_fsm <= '0';
+ lvl1_busy_i_fsm <= '0';
+ lvl1_tdc_trigg_i_fsm <= '0';
+ LVL1_START_fsm_nextstate <= IDLE;
+
+ case (LVL1_START_fsm_currentstate) is
+ when IDLE =>
+ trigger_register_00_i(5 downto 2) <= x"1";
+ lvl1_fifo_wr_en_fsm <= '0';
+ lvl1_fifo_in_fsm <= first_header;
+ lvl1_buffer_rd_en_fsm <= '0';
+ lvl1_tdc_trigg_i_fsm <= '0';
+ lvl1_busy_i_fsm <= '0';
+ if (lvl1_trigger_pulse_start = '1'and LVL1_CODE /= x"d") or (TRIGGER_WITH_GEN_EN ='1' and trigger_with_gen_pulse = '1' and lvl1_or_lvl2_is_busy = '0' ) then
+ LVL1_START_fsm_nextstate <= SEND_LVL1_TRIGG_1;
+ else
+ LVL1_START_fsm_nextstate <= IDLE;
+ end if;
+ when SEND_LVL1_TRIGG_1 =>
+ trigger_register_00_i(5 downto 2) <= x"2";
+ lvl1_tdc_trigg_i_fsm <= '1';
+ lvl1_fifo_wr_en_fsm <= '0';
+ lvl1_fifo_in_fsm <= first_header;
+ lvl1_buffer_rd_en_fsm <= '0';
+ lvl1_busy_i_fsm <= '1';
+ LVL1_START_fsm_nextstate <= SEND_LVL1_TRIGG_2;
+ when SEND_LVL1_TRIGG_2 =>
+ trigger_register_00_i(5 downto 2) <= x"3";
+ lvl1_tdc_trigg_i_fsm <= '1';
+ lvl1_fifo_wr_en_fsm <= '0';
+ lvl1_fifo_in_fsm <= first_header;
+ lvl1_buffer_rd_en_fsm <= '0';
+ lvl1_busy_i_fsm <= '1';
+ LVL1_START_fsm_nextstate <= SEND_LVL1_TRIGG_3;
+ when SEND_LVL1_TRIGG_3 =>
+ trigger_register_00_i(5 downto 2) <= x"4";
+ lvl1_tdc_trigg_i_fsm <= '1';
+ lvl1_fifo_wr_en_fsm <= '0';
+ lvl1_fifo_in_fsm <= first_header;
+ lvl1_buffer_rd_en_fsm <= '0';
+ lvl1_busy_i_fsm <= '1';
+ LVL1_START_fsm_nextstate <= SEND_LVL1_TRIGG_4;
+ when SEND_LVL1_TRIGG_4 =>
+ trigger_register_00_i(5 downto 2) <= x"5";
+ lvl1_tdc_trigg_i_fsm <= '0';
+ lvl1_fifo_wr_en_fsm <= '0';
+ lvl1_fifo_in_fsm <= first_header;
+ lvl1_buffer_rd_en_fsm <= '0';
+ lvl1_busy_i_fsm <= '1';
+ LVL1_START_fsm_nextstate <= WAIT_FOR_TOKEN;
+ when WAIT_FOR_TOKEN =>
+ trigger_register_00_i(5 downto 2) <= x"6";
+ lvl1_tdc_trigg_i_fsm <= '0';
+ lvl1_fifo_wr_en_fsm <= '0';
+ lvl1_fifo_in_fsm <= first_header;
+ lvl1_buffer_rd_en_fsm <= '0';
+ lvl1_busy_i_fsm <= '1';
+ if RECEIVED_TDC_TOKEN = '1' then
+ LVL1_START_fsm_nextstate <= SAVE_ADD_DATA_1;
+ else
+ LVL1_START_fsm_nextstate <= WAIT_FOR_TOKEN;
+ end if;
+ when SAVE_ADD_DATA_1 =>
+ trigger_register_00_i(5 downto 2) <= x"7";
+ lvl1_tdc_trigg_i_fsm <= '0';
+ lvl1_fifo_in_fsm <= first_header;
+ lvl1_fifo_wr_en_fsm <= '1';
+ lvl1_buffer_rd_en_fsm <= '1';
+ lvl1_busy_i_fsm <= '1';
+ LVL1_START_fsm_nextstate <= SAVE_ADD_DATA_2;
+ when SAVE_ADD_DATA_2 =>
+ trigger_register_00_i(5 downto 2) <= x"8";
+ lvl1_tdc_trigg_i_fsm <= '0';
+ lvl1_fifo_in_fsm <= second_header;
+ lvl1_fifo_wr_en_fsm <= '1';
+ lvl1_buffer_rd_en_fsm <= '0';
+ lvl1_busy_i_fsm <= '1';
+ if HOW_MANY_ADD_DATA = x"00" then
+ LVL1_START_fsm_nextstate <= SAVE_ADD_DATA_4;
+ else
+ LVL1_START_fsm_nextstate <= SAVE_ADD_DATA_3;
+ end if;
+ when SAVE_ADD_DATA_3 =>
+ trigger_register_00_i(5 downto 2) <= x"9";
+ lvl1_tdc_trigg_i_fsm <= '0';
+ lvl1_fifo_in_fsm <= add_data_i;
+ lvl1_fifo_wr_en_fsm <= '1';
+ lvl1_buffer_rd_en_fsm <= '0';
+ lvl1_busy_i_fsm <= '1';
+ if add_data_counter = x"0f" then
+ LVL1_START_fsm_nextstate <= SAVE_ADD_DATA_4;
+ else
+ LVL1_START_fsm_nextstate <= SAVE_ADD_DATA_3;
+ end if;
+ when SAVE_ADD_DATA_4 =>
+ trigger_register_00_i(5 downto 2) <= x"a";
+ lvl1_tdc_trigg_i_fsm <= '0';
+ lvl1_fifo_wr_en_fsm <= '1';
+ lvl1_fifo_in_fsm <= lvl1_buffer_out;
+ lvl1_buffer_rd_en_fsm <= '1';
+ lvl1_busy_i_fsm <= '1';
+-- if lvl1_buffer_empty = '1' then --here !!! correct this !!!
+ if lvl1_data_counter = x"0000" then
+ LVL1_START_fsm_nextstate <= SEND_LVL2_TRIGG;
+ else
+ LVL1_START_fsm_nextstate <= SAVE_ADD_DATA_4;
+ end if;
+ when SEND_LVL2_TRIGG =>
+ trigger_register_00_i(5 downto 2) <= x"c";
+ lvl1_tdc_trigg_i_fsm <= '0';
+ lvl1_fifo_wr_en_fsm <= '0';
+ lvl1_fifo_in_fsm <= lvl1_buffer_out;
+ lvl1_buffer_rd_en_fsm <= '0';
+ lvl1_busy_i_fsm <= '1';
+ lvl1_tdc_trigg_i_fsm <= '0';
+ LVL1_START_fsm_nextstate <= IDLE;
+ when others =>
+ trigger_register_00_i(5 downto 2) <= x"d";
+ lvl1_tdc_trigg_i_fsm <= '0';
+ lvl1_fifo_wr_en_fsm <= '0';
+ lvl1_fifo_in_fsm <= lvl1_buffer_out;
+ lvl1_buffer_rd_en_fsm <= '0';
+ lvl1_busy_i_fsm <= '1';
+ lvl1_tdc_trigg_i_fsm <= '0';
+ LVL1_START_fsm_nextstate <= IDLE;
+ end case;
+ end process LVL1_START_FSM_PROC;
+ SAVE_NUMBER_OF_LVL1_WORDS: process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ lvl1_data_counter <= (others => '0');
+ elsif LVL1_START_fsm_currentstate = SAVE_ADD_DATA_3 then
+ lvl1_data_counter <= words_in_event - 3 - HOW_MANY_ADD_DATA;
+ elsif LVL1_START_fsm_currentstate = SAVE_ADD_DATA_4 and lvl1_data_counter > 0 then
+ lvl1_data_counter <= lvl1_data_counter - 1;
+ else
+ lvl1_data_counter <= lvl1_data_counter;
+ end if;
+ end if;
+ end process SAVE_NUMBER_OF_LVL1_WORDS;
+-- not_tdc_clk <= TDC_CLK;
+ TDC_TRIGGER_PULSER : edge_to_pulse
+ port map (
+ clock => TDC_CLK,
+ en_clk => '1',
+ signal_in => lvl1_tdc_trigg_i,
+ pulse => tdc_start_i);
+ TDC_START <= tdc_start_i;--lvl1_tdc_trigg_ff;--tdc_start_i;
+ SEND_TOKEN: process (TDC_CLK, RESET)
+ begin
+ if rising_edge(TDC_CLK) then
+ if RESET = '1' then
+ SEND_TDC_TOKEN <= '0';
+ else
+ SEND_TDC_TOKEN <= tdc_start_i;
+ end if;
+ end if;
+ end process SEND_TOKEN;
+ SAVE_DATA : process (CLK, RESET,lvl1_tdc_trigg_i)
begin
if rising_edge(CLK) then
if RESET = '1' then
counter_f_i <= (others => '0');
counter_g_i <= (others => '0');
counter_h_i <= (others => '0');
- counter_i_i <= (others => '0');
- counter_j_i <= (others => '0');
- counter_k_i <= (others => '0');
- counter_l_i <= (others => '0');
- counter_m_i <= (others => '0');
- elsif START_TDC_READOUT = '1' then
- counter_a_i <= x"00000" & "00" & how_many_words_in_fifo;--COUNTER_a;
- counter_b_i <= x"000000" & MY_LVL1_COUNTER;--COUNTER_b;
+ elsif lvl1_tdc_trigg_i = '1' then
+ counter_a_i <= COUNTER_a;
+ counter_b_i <= COUNTER_b;
counter_c_i <= COUNTER_c;
counter_d_i <= COUNTER_d;
counter_e_i <= COUNTER_e;
counter_f_i <= COUNTER_f;
counter_g_i <= COUNTER_g;
counter_h_i <= COUNTER_h;
- counter_i_i <= COUNTER_i;
- counter_j_i <= COUNTER_j;
- counter_k_i <= COUNTER_k;
- counter_l_i <= COUNTER_l;
- counter_m_i <= COUNTER_m;
end if;
end if;
end process SAVE_DATA;
- TOKEN_PULSE : edge_to_pulse
- port map (
- clock => TDC_CLK,
- en_clk => '1',
- signal_in => RECEIVED_TDC_TOKEN,
- pulse => received_tdc_token_pulse);
- ADD_DATA_PULSE_MAKE : process (TDC_CLK, RESET,received_tdc_token_pulse,add_data_counter)
+ CHOOSE_DATA : process (CLK, RESET, add_data_counter)
begin
- if rising_edge(TDC_CLK) then
- if RESET = '1' or add_data_counter = x"0" then
- add_data_pulse <= '0';
- elsif received_tdc_token_pulse = '1' then
- add_data_pulse <= '1';
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ add_data_i <= x"00000000";
else
- add_data_pulse <= add_data_pulse;
+ case add_data_counter(3 downto 0) is
+ when "0000" => add_data_i <= counter_a_i;
+ when "0001" => add_data_i <= counter_b_i;
+ when "0010" => add_data_i <= counter_c_i;
+ when "0011" => add_data_i <= counter_d_i;
+ when "0100" => add_data_i <= counter_e_i;
+ when "0101" => add_data_i <= counter_f_i;
+ when "0110" => add_data_i <= counter_g_i;
+ when "0111" => add_data_i <= counter_h_i;
+ when others => add_data_i <= x"deadface";
+ end case;
end if;
- end if;
- end process ADD_DATA_PULSE_MAKE;
- data_selector <= add_data_pulse & add_data_counter(3 downto 0);
- CHOOSE_DATA : process (TDC_CLK, RESET, data_selector)
- begin
--- if rising_edge(TDC_CLK) then
- case data_selector is
- when "10000" => data_to_lvl1_fifo <= first_header;
- when "10001" => data_to_lvl1_fifo <= second_header;
- when "10010" => data_to_lvl1_fifo <= counter_a_i;
- when "10011" => data_to_lvl1_fifo <= counter_b_i;
- when "10100" => data_to_lvl1_fifo <= counter_c_i;
- when "10101" => data_to_lvl1_fifo <= counter_d_i;
- when "10110" => data_to_lvl1_fifo <= counter_e_i;
- when "10111" => data_to_lvl1_fifo <= counter_f_i;
- when "11000" => data_to_lvl1_fifo <= counter_g_i;
- when "11001" => data_to_lvl1_fifo <= counter_h_i;
- when "11010" => data_to_lvl1_fifo <= counter_i_i;
- when "11011" => data_to_lvl1_fifo <= counter_j_i;
- when "11100" => data_to_lvl1_fifo <= counter_k_i;
- when "11101" => data_to_lvl1_fifo <= counter_l_i;
- when "11110" => data_to_lvl1_fifo <= counter_m_i;
- when others => data_to_lvl1_fifo <= TDC_DATA_IN;
- end case;
- -- end if;
+ end if;
end process CHOOSE_DATA;
- end_event_marker_in_i <= '1' when data_selector = "10000" else '0';
- TDC_READOUT_COMPLETED <= end_event_marker_in_i;
- LVL1_TRIGGER_PULSE : edge_to_pulse
- port map (
- clock => TDC_CLK,
- en_clk => '1',
- signal_in => START_TDC_READOUT,
- pulse => start_tdc_readout_pulse);
- process (TDC_CLK, RESET)
- begin
- if falling_edge(TDC_CLK) then
- if RESET = '1' then
- start_tdc_readout_90_deg <= start_tdc_readout_90_deg;
- else
- start_tdc_readout_90_deg <= start_tdc_readout_pulse;
- end if;
- end if;
- end process;
- ADD_DATA_COUNTER_CONTROL : process (TDC_CLK, RESET,START_TDC_READOUT,add_data_pulse, start_tdc_readout_pulse)
+ add_data_pulse <= '1' when SAVE_ADD_DATA_3 = LVL1_START_fsm_nextstate else '0';
+ not_tdc_clk <= TDC_CLK;
+ ADD_DATA_COUNTER_CONTROL : process (CLK,RESET,lvl1_tdc_trigg_i,add_data_pulse)
begin
- if rising_edge(TDC_CLK) then
- if RESET = '1' or start_tdc_readout_pulse = '1' then
- add_data_counter <= HOW_MANY_ADD_DATA + 1;
- saved_address <= write_address_tdc_data;
+ if rising_edge(CLK) then
+ if RESET = '1' or lvl1_tdc_trigg_i = '1' then
+ add_data_counter <= x"1" & HOW_MANY_ADD_DATA(3 downto 0) - 1;
elsif add_data_pulse = '1' then
add_data_counter <= add_data_counter - 1;
- saved_address <= saved_address - 1;
- else
- add_data_counter <= add_data_counter;
- saved_address <= saved_address;
end if;
end if;
end process ADD_DATA_COUNTER_CONTROL;
- tdc_ready_or_add_word <= tdc_ready or add_data_pulse;
- COUNT_WORDS_IN_EVENT : process (TDC_CLK, RESET, tdc_ready_or_add_word,start_tdc_readout_pulse)
- begin
- if rising_edge(TDC_CLK) then
- if RESET = '1' or start_tdc_readout_pulse = '1' then
- words_in_event <= x"0000";
- elsif tdc_ready_or_add_word = '1' then
- words_in_event <= words_in_event +1;
- else
- words_in_event <= words_in_event;
- end if;
- end if;
- end process COUNT_WORDS_IN_EVENT;
- lvl1_tag_minus_one <= LVL1_TAG - 1;
- first_header <= x"a" & LVL1_CODE & LVL1_TAG & words_in_event;
-
- second_header <= x"02" & x"00" & x"00" & HOW_MANY_ADD_DATA;
- write_address <= write_address_tdc_data when add_data_pulse = '0' else saved_address;
+ COUNT_WORDS_IN_EVENT : process (TDC_CLK, RESET, tdc_ready, lvl1_tdc_trigg_i)
+ begin
+ if rising_edge(TDC_CLK) then
+ if RESET = '1' or tdc_start_i = '1' then
+ words_in_event <= x"0003" + HOW_MANY_ADD_DATA;
+ elsif tdc_ready = '1' then
+ words_in_event <= words_in_event + 1;
+ end if;
+ end if;
+ end process COUNT_WORDS_IN_EVENT;
+ -- words_in_event <= x"0001" + HOW_MANY_ADD_DATA + 2 + lvl1_buffer_counter;
+ lvl1_tag_minus1 <= LVL1_TAG - 1;
+ first_header <= x"0" & LVL1_CODE & lvl1_tag_minus1 & words_in_event;
+ second_header <= x"030000" & HOW_MANY_ADD_DATA;
+
-----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- LVL2 logic (only CLK domain)
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
- SAVE_LVL2_VALID: process (CLK, RESET,lvl2_trigger_pulse)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- lvl2_valid_saved <= '0';
- elsif lvl2_trigger_pulse = '1' then
- lvl2_valid_saved <= LVL2_TRIGGER(1);
+ LVL2_START : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ LVL2_START_fsm_currentstate <= IDLE;
+ lvl1_fifo_rd_en <= '0';
+ tdc_data_valid_i <= '0';
+ else
+ lvl1_fifo_rd_en <= lvl1_fifo_rd_en_fsm;
+ tdc_data_valid_i <= tdc_data_valid_i_fsm;
+ LVL2_START_fsm_currentstate <= LVL2_START_fsm_nextstate;
+ end if;
end if;
- end if;
- end process SAVE_LVL2_VALID;
- LVL2_TRIGGER_PULSER : edge_to_pulse
- port map (
- clock => CLK,
- en_clk => '1',
- signal_in => LVL2_TRIGGER(0),
- pulse => lvl2_trigger_pulse);
- COUNT_DOWN_READOUT: process (CLK, RESET,lvl2_trigger_pulse,how_many_words_in_event)
+ end process LVL2_START;
+ START_LVL2_FSM: process (LVL2_START_fsm_currentstate, LVL1_START_fsm_currentstate, how_many_words_in_event, lvl1_fifo_out, etrax_is_ready_to_read)
+ begin
+ lvl2_debug (2 downto 0) <= "000";
+ lvl1_fifo_rd_en_fsm <= '0';
+ tdc_data_valid_i_fsm <= '0';
+ LVL2_START_fsm_nextstate <= IDLE;
+ case (LVL2_START_fsm_currentstate) is
+ when IDLE =>
+ lvl2_debug (2 downto 0) <= "001";
+ lvl1_fifo_rd_en_fsm <= '0';
+ tdc_data_valid_i_fsm <= '0';
+ if LVL1_START_fsm_currentstate = SEND_LVL2_TRIGG then
+ LVL2_START_fsm_nextstate <= READOUT_WORD1;
+ else
+ LVL2_START_fsm_nextstate <= IDLE;
+ end if;
+ when READOUT_WORD1 =>
+ lvl2_debug (2 downto 0) <= "010";
+ lvl1_fifo_rd_en_fsm <= '1';
+ tdc_data_valid_i_fsm <= '0';
+ LVL2_START_fsm_nextstate <= READOUT_WORD2;
+ when READOUT_WORD2 =>
+ lvl2_debug (2 downto 0) <= "011";
+ lvl1_fifo_rd_en_fsm <= '0';
+ tdc_data_valid_i_fsm <= '0';
+ LVL2_START_fsm_nextstate <= SAVE_EVENT_SIZE;
+ when SAVE_EVENT_SIZE =>
+ lvl2_debug (2 downto 0) <= "100";
+ lvl1_fifo_rd_en_fsm <= '0';
+ tdc_data_valid_i_fsm <= '0';
+ LVL2_START_fsm_nextstate <= SEND_DATA1;
+ when SEND_DATA1 =>
+ lvl2_debug (2 downto 0) <= "101";
+ lvl1_fifo_rd_en_fsm <= ETRAX_IS_READY_TO_READ;
+ tdc_data_valid_i_fsm <= '1';
+ if how_many_words_in_event(15 downto 0) = x"0000" then
+ LVL2_START_fsm_nextstate <= IDLE;
+ else
+ LVL2_START_fsm_nextstate <= SEND_DATA1;
+ end if;
+ end case;
+ end process START_LVL2_FSM;
+ COUNT_DOWN_READOUT: process (CLK, RESET,how_many_words_in_event)
begin
if rising_edge(CLK) then
if RESET = '1' then
how_many_words_in_event <= (others => '0');
- elsif lvl2_trigger_pulse_delay = '1' then
- how_many_words_in_event <= x"1" & doutb_i(15 downto 0);
- elsif lvl2_trigger_pulse_delay = '0' and how_many_words_in_event > x"0ffff" and (ETRAX_IS_READY_TO_READ = '1' or READ_ADRESS_END_UP='1')then
- --this should be without and ETRAX_IS_READY_TO_READ - this is simple
- --version of readout - in next whole event has to be written without
- --waiting for etrax - ifthere is no LVL2 busy from etrax
+ elsif LVL2_START_fsm_currentstate = SAVE_EVENT_SIZE then
+ how_many_words_in_event <= '1' & lvl1_fifo_out(15 downto 0);
+ elsif how_many_words_in_event > x"0ffff" and ETRAX_IS_READY_TO_READ = '1' then -- or READ_ADRESS_END_UP='1')then
how_many_words_in_event <= how_many_words_in_event - 1;
end if;
end if;
end process COUNT_DOWN_READOUT;
-
- MAKE_LVL2_PULSE : process (CLK, RESET, how_many_words_in_event )
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- tdc_data_valid_i <= '0';
- read_data_address_up <= '0';
- elsif how_many_words_in_event > x"10000" then
- tdc_data_valid_i <= '1';--lvl2_valid_saved;
- read_data_address_up <= '1';
- elsif how_many_words_in_event = x"10000" then
- tdc_data_valid_i <= '0';--lvl2_valid_saved;
- read_data_address_up <= '1';
- else
- tdc_data_valid_i <= '0';--tdc_data_valid_i;
- read_data_address_up <= '0';--read_data_address_up;
- end if;
- end if;
- end process MAKE_LVL2_PULSE;
SYNCH_DATA_VALID: process (CLK, RESET)
begin
- if falling_edge(CLK) then --correct this !!!!!!!!!!!!!!!!(falling?)
+ if rising_edge(CLK) then --correct this !!!!!!!!!!!!!!!!(falling?)
if RESET = '1' then
TDC_DATA_VALID <= '0';
else
end if;
end if;
end process SYNCH_DATA_VALID;
- TDC_LVL2_BUSY <= tdc_data_valid_i;
- DELAY_LVL2_TRIGGER: process (CLK, RESET)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- lvl2_trigger_pulse_delay <= '0';
-
- lvl2_trigger_pulse_1delay <= '0';
- lvl2_trigger_pulse_2delay <= '0';
- lvl2_trigger_pulse_3delay <= '0';
- lvl2_trigger_pulse_4delay <= '0';
-
- else
- lvl2_trigger_pulse_1delay <= lvl2_trigger_pulse;
- lvl2_trigger_pulse_2delay <= lvl2_trigger_pulse_1delay;
- lvl2_trigger_pulse_3delay <= lvl2_trigger_pulse_2delay;
- lvl2_trigger_pulse_4delay <= lvl2_trigger_pulse_3delay;
- lvl2_trigger_pulse_delay <= lvl2_trigger_pulse_4delay;
-
--- lvl2_trigger_pulse_delay <= lvl2_trigger_pulse;
- end if;
- end if;
- end process DELAY_LVL2_TRIGGER;
- READ_ADDRESS_CHANGE : process (CLK, RESET, read_data_address_up)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- read_address <= (others => '0');
--- saved_beg_address <= (others => '0');
--- elsif lvl2_trigger_pulse_delay = '1' then
--- -- saved_beg_address <= saved_beg_address + doutb_i(14 downto 0);
--- read_address <= saved_beg_address + doutb_i(14 downto 0);
- elsif (read_data_address_up = '1' and ETRAX_IS_READY_TO_READ = '1') or READ_ADRESS_END_UP='1' then
- read_address <= read_address + 1;
- else
- read_address <= read_address;
- saved_beg_address <= saved_beg_address;
- end if;
- end if;
- end process READ_ADDRESS_CHANGE;
--- SAVE_BEG_ADDRESS: process (CLK, RESET)
--- begin
--- if rising_edge(CLK) then -- rising clock edge
--- if RESET = '1' then
--- saved_beg_address <= (others => '0');
--- elsif lvl2_trigger_pulse = '1' then
--- saved_beg_address <= saved_beg_address + doutb_i(14 downto 0);
--- else
--- saved_beg_address <= saved_beg_address;
--- end if;
--- end if;
--- end process SAVE_BEG_ADDRESS;
- -----------------------------------------------------------------------------
- ----------------------------------------------------------------------------
- -- Mixed LVL1 and LVL2
- -----------------------------------------------------------------------------
- -----------------------------------------------------------------------------
- WORD_ADD_TO_MEMORY: process (TDC_CLK, RESET)
- begin
- if rising_edge(TDC_CLK) then
- if RESET = '1' then
- word_ram_counter_up <= (others => '0');
- elsif tdc_ready_or_add_word = '1' then
- word_ram_counter_up <= word_ram_counter_up + 1;
- end if;
- end if;
- end process WORD_ADD_TO_MEMORY;
- WORD_SEND_FROM_MEMORY: process (CLK, RESET,ETRAX_IS_READY_TO_READ)
+
+ not_tdc_data_valid_i <= not tdc_data_valid_i;
+ LVL2_BUSY_END_PULSER : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => not_tdc_data_valid_i,
+ pulse => lvl2_busy_end_pulse);
+ LVL2_BUSY_SET: process (CLK, RESET)
begin
- if rising_edge(CLK) then
- if RESET = '1' then
- word_ram_counter_down <= (others => '0');
--- elsif (read_data_address_up = '1' and ETRAX_IS_READY_TO_READ = '1') or READ_ADRESS_END_UP='1' then
- elsif ((tdc_data_valid_i = '1' and ETRAX_IS_READY_TO_READ = '1') or READ_ADRESS_END_UP='1') and how_many_words_in_fifo /= "0000000000000000" then
- word_ram_counter_down <= word_ram_counter_down + 1;
- end if;
- end if;
- end process WORD_SEND_FROM_MEMORY;
- REGISTER_DIFFERENCE: process (CLK, RESET)
- begin
- if CLK'event and CLK = '1' then -- rising clock edge
- if RESET = '1' then -- asynchronous reset (active low)
- how_many_words_in_fifo <= (others => '0');
- else
- how_many_words_in_fifo <= word_ram_counter_up - word_ram_counter_down;
+ if rising_edge(CLK) then
+ if RESET = '1' or lvl2_busy_end_pulse = '1'then
+ lvl2_busy_i <= '0';
+ elsif LVL2_START_fsm_currentstate /= IDLE then
+ lvl2_busy_i <= '1';
end if;
end if;
- end process REGISTER_DIFFERENCE;
-
- TDC_LVL1_BUSY <= '1' when how_many_words_in_fifo > "011111111" else '0';
+ end process LVL2_BUSY_SET;
+ LVL2_BUSY_START_PULSER : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => lvl2_busy_i,
+ pulse => lvl2_busy_start_pulse);
+ lvl1_memory_busy_i <= '1' when lvl1_fifo_counter > "00001111111111" else '0';
--set
--to
--max
--value
--!!!!!!! and cut data funktion should
--be implemented - with busy or max
- --size or last event ? or both
-
+ --size or last event ? or both
+ LVL1_OR_LVL2_BUSY: process (CLK, RESET, lvl1_busy_i, lvl2_busy_end_pulse)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ lvl1_or_lvl2_is_busy <= '0';
+ elsif lvl1_busy_i = '1' then
+ lvl1_or_lvl2_is_busy <= '1';
+ elsif lvl2_busy_end_pulse = '1' then
+ lvl1_or_lvl2_is_busy <= '0';
+ end if;
+ end if;
+ end process LVL1_OR_LVL2_BUSY;
+
+ LVL2_BUSY <= lvl2_busy_i;
+ TDC_READOUT_COMPLETED <= lvl2_busy_end_pulse;
-----------------------------------------------------------------------------
-- end writing to fifo when TDC_LVL1_BUSY and read all data and send finish signal
-----------------------------------------------------------------------------
+ TEST_COUNTER_a : simpleupcounter_8bit
+ port map (
+ CLK => TDC_CLK,
+ UP => tdc_start_i,
+ CLR => RESET,
+ QOUT => test_counter_0
+ );
+ TEST_COUNTER_b : simpleupcounter_8bit
+ port map (
+ CLK => TDC_CLK,
+ UP => RECEIVED_TDC_TOKEN,
+ CLR => RESET,
+ QOUT => test_counter_1
+ );
+ TEST_COUNTER_c : simpleupcounter_8bit
+ port map (
+ CLK => CLK,
+ UP => lvl2_busy_start_pulse,--lvl2_trigger_pulse,
+ CLR => RESET,
+ QOUT => test_counter_2
+ );
+ TEST_COUNTER_d : simpleupcounter_8bit
+ port map (
+ CLK => CLK,
+ UP => lvl2_busy_end_pulse,
+ CLR => RESET,
+ QOUT => test_counter_3
+ );
+ REGITERING_SIGNALS: process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then -- rising clock edge
+ if RESET = '1' then
+ LVL1_BUSY <= '0';
+ else
+ LVL1_BUSY <= lvl1_or_lvl2_is_busy;--lvl1_busy_i or lvl1_memory_busy_i;--lvl1_or_lvl2_is_busy;--lvl1_busy_i; --here
+ end if;
+ end if;
+ end process REGITERING_SIGNALS;
end tdc_interface;
--- etrax czasem widzi za wczesnie header zamiast headera widzi dana z poprzedniego eventu ¿
--- moze READ_ADRESS_END_UP gdzeis jest zgubione ?
+
--- /dev/null
+NOTE "CREATOR" "Xilinx iMPACT Software";
+NOTE "DATE" "2008/01/07";
+NOTE "STAPL_VERSION" "JESD71";
+NOTE "ALG_VERSION" "1";
+NOTE "DEVICE" "UNSPECIFIED";
+NOTE "CHECKSUM" "UNSPECIFIED";
+NOTE "IDCODE" "UNSPECIFIED";
+NOTE "USERCODE" "UNSPECIFIED";
+NOTE "TARGET" "UNSPECIFIED";
+NOTE "STACK_DEPTH" "4";
+NOTE "MAX_FREQ" "1000000";
+ACTION RUN_XILINX_PROC "Run Xilinx Procedure" = XILINX_PROC;
+DATA MAINDATA;
+INTEGER I = 0;
+INTEGER D = 0;
+ENDDATA;
+PROCEDURE XILINX_PROC USES ADJUST_DELAY, MAINDATA;
+BOOLEAN X = 0;
+IRSTOP IDLE;
+DRSTOP IDLE;
+STATE RESET IDLE;
+POSTIR 0 ;
+PREIR 0 ;
+POSTDR 0 ;
+PREDR 0 ;
+POSTIR 0 ;
+PREIR 0 ;
+PREDR 0 ;
+POSTDR 0 ;
+' //Loading device with 'idcode' instruction.
+IRSCAN 10, $03c9
+ ;
+DRSCAN 32, $00000000
+, COMPARE $f16a4093
+, $0fffffff
+, X;
+IF (!X) THEN GOTO F;
+POSTIR 0 ;
+PREIR 0 ;
+POSTDR 0 ;
+PREDR 0 ;
+POSTIR 0 ;
+PREIR 0 ;
+POSTDR 0 ;
+PREDR 0 ;
+POSTIR 0 ;
+PREIR 0 ;
+PREDR 0 ;
+POSTDR 0 ;
+' //Loading device with 'idcode' instruction.
+IRSCAN 10, $03c9
+ ;
+DRSCAN 32, $00000000
+, COMPARE $f16a4093
+, $0fffffff
+, X;
+IF (!X) THEN GOTO F;
+' //Loading device with 'bypass' instruction.
+IRSCAN 10, $03ff
+ ;
+' // Loading device with a `jprogram` instruction.
+IRSCAN 10, $03cb
+ ;
+D = 1;
+WAIT D CYCLES;
+' // Loading device with a `bypass` instruction.
+IRSCAN 10, $03ff
+ ;
+D = 21000;
+WAIT D CYCLES;
+' // Loading device with a `cfg_in` instruction.
+IRSCAN 10, $03c5
+ ;
+D = 100000;
+WAIT D CYCLES;
+' // Check init_complete in ircapture.
+' //Loading device with 'Bypass' instruction.
+IRSCAN 10, $03ff
+, COMPARE $0010
+, $0010
+, X;
+IF (!X) THEN GOTO F;
+' STATE RESET;
+' // Loading device with a `cfg_in` instruction.
+IRSCAN 10, $03c5
+, COMPARE $0000
+, $0000
+, X;
+IF (!X) THEN GOTO F;
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
+' which might exceed the capacity of your run-time environment.
+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+' WARNING: This STAPL file describes a data shift of more than 16K bits
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+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@Fn0000m3KqV_p0020G
+0000WY00000Ca1W10c000004a001H0WG80G4408120K0106WGZnCaGI3C43W10W0010WGH06
+0G0020000q47Cm00200000C0G1H0O0000GoNLdWd1040W0000WDtXV0m@@3
+ ;
+' // Loading device with a `jstart` instruction.
+IRSCAN 10, $03cc
+ ;
+D = 12;
+WAIT D CYCLES;
+' //Loading device with 'bypass' instruction.
+IRSCAN 10, $03ff
+ ;
+' //Loading device with 'bypass' instruction.
+IRSCAN 10, $03ff
+ ;
+POSTIR 0 ;
+PREIR 0 ;
+PREDR 0 ;
+POSTDR 0 ;
+POSTIR 0 ;
+PREIR 0 ;
+PREDR 0 ;
+POSTDR 0 ;
+' // Loading device with a `jstart` instruction.
+IRSCAN 10, $03cc
+ ;
+D = 12;
+WAIT D CYCLES;
+' //Checking done pin status.
+' //Loading device with 'Bypass' instruction.
+IRSCAN 10, $03ff
+, COMPARE $0021
+, $0020
+, X;
+IF (!X) THEN GOTO F;
+POSTIR 0 ;
+PREIR 0 ;
+POSTDR 0 ;
+PREDR 0 ;
+IRSCAN 10, $03ff
+ ;
+DRSCAN 1, $00
+ ;
+
+SUCCESS:
+PRINT "Successful File Execution.";
+EXIT 0;
+
+F:
+PRINT "File Execution Failure.";
+EXIT 16;
+
+ENDPROC;
+
+DATA TMPDATA;
+INTEGER TMP_DELAY;
+ENDDATA;
+
+PROCEDURE ADJUST_BIG_DELAY USES TMPDATA, MAINDATA;
+TMP_DELAY = D / 100;
+TMP_DELAY = TMP_DELAY * 25;
+D = D + TMP_DELAY;
+ENDPROC;
+
+PROCEDURE ADJUST_SMALL_DELAY USES TMPDATA, MAINDATA;
+TMP_DELAY = D * 25;
+TMP_DELAY = TMP_DELAY / 100;
+D = D + TMP_DELAY;
+ENDPROC;
+
+PROCEDURE ADJUST_DELAY USES MAINDATA, ADJUST_BIG_DELAY, ADJUST_SMALL_DELAY;
+IF D > 2500 THEN CALL ADJUST_BIG_DELAY;
+IF D <= 2500 THEN CALL ADJUST_SMALL_DELAY;
+ENDPROC;
+
+CRC CB18;
--- /dev/null
+ # NET +<1> LOC = AE28;
+ # NET +<2> LOC ="L2| IOSTANDARD = "LVTTL";
+ # NET +<3> LOC ="AJ18| IOSTANDARD = "LVTTL";
+ # NET ADDON_TO_TRB_CLKINN LOC ="G16| IOSTANDARD = "LVTTL";
+ # NET ADDON_TO_TRB_CLKINP LOC ="G17| IOSTANDARD = "LVTTL";
+ NET ADO_LV<0> LOC ="AC9";
+ NET ADO_LV<1> LOC ="AC8";
+ NET ADO_LV<2> LOC ="AG3";
+ NET ADO_LV<3> LOC ="AF3";
+ NET ADO_LV<4> LOC ="AF6";
+ NET ADO_LV<5> LOC ="AE6";
+ NET ADO_LV<6> LOC ="AF5";
+ NET ADO_LV<7> LOC ="AF4";
+ NET ADO_LV<8> LOC ="AL1";
+ NET ADO_LV<9> LOC ="AK1";
+ NET ADO_LV<10> LOC ="AJ2";
+ NET ADO_LV<11> LOC ="AJ1";
+ NET ADO_LV<12> LOC ="AB6";
+ NET ADO_LV<13> LOC ="AB5";
+ NET ADO_LV<14> LOC ="AC3";
+ NET ADO_LV<15> LOC ="AC2";
+ NET ADO_LV<16> LOC ="Y11";
+ NET ADO_LV<17> LOC ="AA11";
+ NET ADO_LV<18> LOC ="AD2";
+ NET ADO_LV<19> LOC ="AD1";
+ NET ADO_LV<20> LOC ="Y14";
+ NET ADO_LV<21> LOC ="AA13";
+ NET ADO_LV<22> LOC ="AC5";
+ NET ADO_LV<23> LOC ="AC4";
+ NET ADO_LV<24> LOC ="AF1";
+ NET ADO_LV<25> LOC ="AE1";
+ NET ADO_LV<26> LOC ="AE3";
+ NET ADO_LV<27> LOC ="AE2";
+ NET ADO_LV<28> LOC ="AD6";
+ NET ADO_LV<29> LOC ="AD5";
+ NET ADO_LV<30> LOC ="AC7";
+ NET ADO_LV<31> LOC ="AB8";
+ NET ADO_LV<32> LOC ="Y16";
+ NET ADO_LV<33> LOC ="AA15";
+ NET ADO_LV<34> LOC ="AE4";
+ NET ADO_LV<35> LOC ="AD4";
+ NET ADO_LV<36> LOC ="AH3";
+ NET ADO_LV<37> LOC ="AH2";
+ NET ADO_LV<38> LOC ="AG2";
+ NET ADO_LV<39> LOC ="AG1";
+ NET ADO_LV<40> LOC ="AK3";
+ NET ADO_LV<41> LOC ="AK2";
+ NET ADO_LV<42> LOC ="AF8";
+ NET ADO_LV<43> LOC ="AE8";
+ NET ADO_LV<44> LOC ="AH5";
+ NET ADO_LV<45> LOC ="AH4";
+ NET ADO_LV<46> LOC ="AB13";
+ NET ADO_LV<47> LOC ="AB12";
+ NET ADO_LV<48> LOC ="AM2";
+ NET ADO_LV<49> LOC ="AM1";
+ NET ADO_LV<50> LOC ="AG8";
+ NET ADO_LV<51> LOC ="AG7";
+# NET ADO_LV<52> LOC ="AM3";
+# NET ADO_LV<53> LOC ="AL3";
+# NET ADO_LV<54> LOC ="AK22";
+# NET ADO_LV<55> LOC ="AK23";
+# NET ADO_LV<56> LOC ="AL28";
+# NET ADO_LV<57> LOC ="AL29";
+ # NET ADO_LV<58> LOC ="AP25";
+ # NET ADO_LV<59> LOC ="AP26";
+ # NET ADO_LV<60> LOC ="AJ27";
+ # NET ADO_LV<61> LOC ="AH27";
+ NET ADO_TTL<0> LOC ="AL11"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<1> LOC ="AL10"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<2> LOC ="AE11"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<3> LOC ="AF11"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<4> LOC ="AM12"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<5> LOC ="AM11"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<6> LOC ="AL9"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<7> LOC ="AK9"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<8> LOC ="AP11"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<9> LOC ="AP10"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<10> LOC ="AH10"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<11> LOC ="AG10"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<12> LOC ="AN12"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<13> LOC ="AP12"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<14> LOC ="AP9"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<15> LOC ="AN9"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<16> LOC ="AH12"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<17> LOC ="AG11"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<18> LOC ="AN7"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<19> LOC ="AM7"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<20> LOC ="AN10"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<21> LOC ="AM10"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<22> LOC ="AF10"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<23> LOC ="AE9"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<24> LOC ="AJ12"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<25> LOC ="L33"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<26> LOC ="L34"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<27> LOC ="M32"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<28> LOC ="M33"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<29> LOC ="D5"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<30> LOC ="G7"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<31> LOC ="G6"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<32> LOC ="E14"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<33> LOC ="D14"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<34> LOC ="AL20"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<35> LOC ="AJ15"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<36> LOC ="AJ14"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<37> LOC ="AG20"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<38> LOC ="AH20"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<39> LOC ="AG15"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<40> LOC ="AH14"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<41> LOC ="AL16"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<42> LOC ="AK16"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<43> LOC ="C28"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<44> LOC ="L26"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<45> LOC ="B32"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<46> LOC ="B33"| IOSTANDARD = "LVTTL";
+ NET A_CSB LOC ="P9";
+ NET A_CS LOC ="P10";
+ NET A_DATA_READY LOC ="B12"| IOSTANDARD = "LVTTL";
+ NET A_RESERVED LOC ="J11"| IOSTANDARD = "LVTTL";
+ NET A_SCK LOC ="H3";
+ NET A_SCKB LOC ="H2";
+ NET A_SDI LOC ="F1";
+ NET A_SDIB LOC ="G1";
+ NET A_SDO LOC ="J4";
+ NET A_SDOB LOC ="K4";
+ NET A_TDC_BU_RESET LOC ="AK27";
+ NET A_TDC_BU_RESETB LOC ="AK28";
+ NET A_TDC_ERROR LOC ="F11"| IOSTANDARD = "LVTTL";
+ NET A_TDC_EV_RESET LOC ="AK24";
+ NET A_TDC_EV_RESETB LOC ="AJ24";
+ NET A_TDC_POWERUP LOC ="H8"| IOSTANDARD = "LVTTL";
+ NET A_TEMP LOC ="B7"| IOSTANDARD = "LVTTL";
+ NET A_TEST1B LOC ="N7";
+ NET A_TEST2B LOC ="L4";
+ NET A_TEST1 LOC ="M7";
+ NET A_TEST2 LOC ="L5";
+ NET A_TRIGGER LOC ="J6";
+ NET A_TRIGGERB LOC ="J5";
+ NET B_CSB LOC ="G5";
+ NET B_CS LOC ="F5";
+ NET B_DATA_READY LOC ="A8"| IOSTANDARD = "LVTTL";
+ NET B_RESERVED LOC ="C7"| IOSTANDARD = "LVTTL";
+ NET B_SCK LOC ="C4";
+ NET B_SCKB LOC ="C3";
+ NET B_SDI LOC ="R11";
+ NET B_SDIB LOC ="T11";
+ NET B_SDO LOC ="G3";
+ NET B_SDOB LOC ="G2";
+ NET B_TDC_BU_RESET LOC ="AG25";
+ NET B_TDC_BU_RESETB LOC ="AG26";
+ NET B_TDC_ERROR LOC ="A6"| IOSTANDARD = "LVTTL";
+ NET B_TDC_EV_RESET LOC ="AG23";
+ NET B_TDC_EV_RESETB LOC ="AF24";
+ NET B_TDC_POWERUP LOC ="H7"| IOSTANDARD = "LVTTL";
+ NET B_TEMP LOC ="A10"| IOSTANDARD = "LVTTL";
+ NET B_TEST2B LOC ="L9";
+ NET B_TEST1B LOC ="E4";
+ NET B_TEST1 LOC ="D4";
+ NET B_TEST2 LOC ="M10";
+ NET B_TRIGGER LOC ="H5";
+ NET B_TRIGGERB LOC ="H4";
+ NET C_CSB LOC ="R9";
+ NET C_CS LOC ="T10";
+ NET C_DATA_READY LOC ="B8"| IOSTANDARD = "LVTTL";
+ NET C_RESERVED LOC ="F8"| IOSTANDARD = "LVTTL";
+ NET C_SCK LOC ="P7";
+ NET C_SCKB LOC ="P6";
+ NET C_SDI LOC ="D1";
+ NET C_SDIB LOC ="E1";
+ NET C_SDO LOC ="F4";
+ NET C_SDOB LOC ="F3";
+ NET C_TDC_BU_RESET LOC ="AP31";
+ NET C_TDC_BU_RESETB LOC ="AP32";
+ NET C_TDC_ERROR LOC ="B6"| IOSTANDARD = "LVTTL";
+ NET C_TDC_EV_RESET LOC ="AP27";
+ NET C_TDC_EV_RESETB LOC ="AN27";
+ NET C_TDC_POWERUP LOC ="K8"| IOSTANDARD = "LVTTL";
+ NET C_TEMP LOC ="A9"| IOSTANDARD = "LVTTL";
+ NET C_TEST2B LOC ="N12";
+ NET C_TEST1B LOC ="D2";
+ NET C_TEST1 LOC ="C2";
+ NET C_TEST2 LOC ="N13";
+ NET C_TOKEN_OUT_TTL LOC ="F6"| IOSTANDARD = "LVTTL";
+ NET C_TRIGGER LOC ="N10";
+ NET C_TRIGGERB LOC ="N9";
+ NET DBAD LOC ="M28"| IOSTANDARD = "LVTTL";
+ NET DGOOD LOC ="H34"| IOSTANDARD = "LVTTL";
+ NET DINT LOC ="L31"| IOSTANDARD = "LVTTL";
+ NET DSPADDR<0> LOC ="AA23"| IOSTANDARD = "LVTTL";
+ NET DSPADDR<1> LOC ="AA24"| IOSTANDARD = "LVTTL";
+ NET DSPADDR<2> LOC ="AJ34"| IOSTANDARD = "LVTTL";
+ NET DSPADDR<3> LOC ="AH34"| IOSTANDARD = "LVTTL";
+ NET DSPADDR<4> LOC ="AD27"| IOSTANDARD = "LVTTL";
+ NET DSPADDR<5> LOC ="AC27"| IOSTANDARD = "LVTTL";
+ NET DSPADDR<6> LOC ="AB25"| IOSTANDARD = "LVTTL";
+ NET DSPADDR<7> LOC ="AB26"| IOSTANDARD = "LVTTL";
+ NET DSPADDR<8> LOC ="AG30"| IOSTANDARD = "LVTTL";
+ NET DSPADDR<9> LOC ="AG31"| IOSTANDARD = "LVTTL";
+ NET DSPADDR<10> LOC ="AH32"| IOSTANDARD = "LVTTL";
+ NET DSPADDR<11> LOC ="AH33"| IOSTANDARD = "LVTTL";
+ NET DSPADDR<12> LOC ="AF29"| IOSTANDARD = "LVTTL";
+ NET DSPADDR<13> LOC ="AF30"| IOSTANDARD = "LVTTL";
+ NET DSPADDR<14> LOC ="AA28"| IOSTANDARD = "LVTTL";
+ NET DSPADDR<15> LOC ="AA29"| IOSTANDARD = "LVTTL";
+ NET DSPADDR<16> LOC ="W24"| IOSTANDARD = "LVTTL";
+ NET DSPADDR<17> LOC ="Y24"| IOSTANDARD = "LVTTL";
+ NET DSPADDR<18> LOC ="AB30"| IOSTANDARD = "LVTTL";
+ NET DSPADDR<19> LOC ="AA30"| IOSTANDARD = "LVTTL";
+ NET DSPADDR<20> LOC ="W25"| IOSTANDARD = "LVTTL";
+ NET DSPADDR<21> LOC ="Y26"| IOSTANDARD = "LVTTL";
+ NET DSPADDR<22> LOC ="AE33"| IOSTANDARD = "LVTTL";
+ NET DSPADDR<23> LOC ="AE34"| IOSTANDARD = "LVTTL";
+ NET DSPADDR<24> LOC ="AC32"| IOSTANDARD = "LVTTL";
+ NET DSPADDR<25> LOC ="AC33"| IOSTANDARD = "LVTTL";
+ NET DSPADDR<26> LOC ="AC29"| IOSTANDARD = "LVTTL";
+ NET DSPADDR<27> LOC ="AC30"| IOSTANDARD = "LVTTL";
+ NET DSPADDR<28> LOC ="AD34"| IOSTANDARD = "LVTTL";
+ NET DSPADDR<29> LOC ="AC34"| IOSTANDARD = "LVTTL";
+ NET DSPADDR<30> LOC ="AH18"| IOSTANDARD = "LVTTL";
+ NET DSPADDR<31> LOC ="AK18"| IOSTANDARD = "LVTTL";
+ NET DSPDAT<0> LOC ="AA25"| IOSTANDARD = "LVTTL";
+ NET DSPDAT<1> LOC ="AA26"| IOSTANDARD = "LVTTL";
+ NET DSPDAT<2> LOC ="AE32"| IOSTANDARD = "LVTTL";
+ NET DSPDAT<3> LOC ="AD32"| IOSTANDARD = "LVTTL";
+ NET DSPDAT<4> LOC ="AC28"| IOSTANDARD = "LVTTL";
+ NET DSPDAT<5> LOC ="AB28"| IOSTANDARD = "LVTTL";
+ NET DSPDAT<6> LOC ="AD30"| IOSTANDARD = "LVTTL";
+ NET DSPDAT<7> LOC ="AD31"| IOSTANDARD = "LVTTL";
+ NET DSPDAT<8> LOC ="AG32"| IOSTANDARD = "LVTTL";
+ NET DSPDAT<9> LOC ="AG33"| IOSTANDARD = "LVTTL";
+ NET DSPDAT<10> LOC ="AF33"| IOSTANDARD = "LVTTL";
+ NET DSPDAT<11> LOC ="AF34"| IOSTANDARD = "LVTTL";
+ NET DSPDAT<12> LOC ="AE29"| IOSTANDARD = "LVTTL";
+ NET DSPDAT<13> LOC ="AD29"| IOSTANDARD = "LVTTL";
+ NET DSPDAT<14> LOC ="AF31"| IOSTANDARD = "LVTTL";
+ NET DSPDAT<15> LOC ="AE31"| IOSTANDARD = "LVTTL";
+ NET DSPDAT<16> LOC ="AK31"| IOSTANDARD = "LVTTL";
+ NET DSPDAT<17> LOC ="AK32"| IOSTANDARD = "LVTTL";
+ NET DSPDAT<18> LOC ="AK33"| IOSTANDARD = "LVTTL";
+ NET DSPDAT<19> LOC ="AK34"| IOSTANDARD = "LVTTL";
+ NET DSPDAT<20> LOC ="AM32"| IOSTANDARD = "LVTTL";
+ NET DSPDAT<21> LOC ="AM33"| IOSTANDARD = "LVTTL";
+ NET DSPDAT<22> LOC ="AJ31"| IOSTANDARD = "LVTTL";
+ NET DSPDAT<23> LOC ="AJ32"| IOSTANDARD = "LVTTL";
+ NET DSPDAT<24> LOC ="AB22"| IOSTANDARD = "LVTTL";
+ NET DSPDAT<25> LOC ="AB23"| IOSTANDARD = "LVTTL";
+ NET DSPDAT<26> LOC ="AL33"| IOSTANDARD = "LVTTL";
+ NET DSPDAT<27> LOC ="AL34"| IOSTANDARD = "LVTTL";
+ NET DSPDAT<28> LOC ="AM31"| IOSTANDARD = "LVTTL";
+ NET DSPDAT<29> LOC ="AL31"| IOSTANDARD = "LVTTL";
+ NET DSPDAT<30> LOC ="AJ30"| IOSTANDARD = "LVTTL";
+ NET DSPDAT<31> LOC ="AH30"| IOSTANDARD = "LVTTL";
+ NET DSP_ACK LOC ="AB15"| IOSTANDARD = "LVTTL";
+ NET DSP_BM LOC ="AH19"| IOSTANDARD = "LVTTL";
+ NET DSP_BMS LOC ="AF15"| IOSTANDARD = "LVTTL";
+ NET DSP_BOFF LOC ="AK14"| IOSTANDARD = "LVTTL";
+ NET DSP_BRST LOC ="AN20"| IOSTANDARD = "LVTTL";
+ # NET DSP_BUSLOCK LOC ="AC19"| IOSTANDARD = "LVTTL";
+ # NET DSP_DMAR<0> LOC ="AD17"| IOSTANDARD = "LVTTL";
+ # NET DSP_DMAR<1> LOC ="AC17"| IOSTANDARD = "LVTTL";
+ # NET DSP_DMAR<2> LOC ="AM20"| IOSTANDARD = "LVTTL";
+ # NET DSP_DMAR<3> LOC ="AL19"| IOSTANDARD = "LVTTL";
+ # NET DSP_FLAG<0> LOC ="AE21"| IOSTANDARD = "LVTTL";
+ # NET DSP_FLAG<1> LOC ="AF21"| IOSTANDARD = "LVTTL";
+ # NET DSP_FLAG<2> LOC ="AP15"| IOSTANDARD = "LVTTL";
+ # NET DSP_FLAG<3> LOC ="AN15"| IOSTANDARD = "LVTTL";
+ NET DSP_HBG LOC ="AD16"| IOSTANDARD = "LVTTL";
+ NET DSP_HBR LOC ="AB18"| IOSTANDARD = "LVTTL";
+ # NET DSP_IOEN LOC ="AL18"| IOSTANDARD = "LVTTL";
+ # NET DSP_IORD LOC ="AB16"| IOSTANDARD = "LVTTL";
+ # NET DSP_IOWR LOC ="AB17"| IOSTANDARD = "LVTTL";
+ NET DSP_IRQ<0> LOC ="AG21"| IOSTANDARD = "LVTTL";
+ NET DSP_IRQ<1> LOC ="AF20"| IOSTANDARD = "LVTTL";
+ NET DSP_IRQ<2> LOC ="AF14"| IOSTANDARD = "LVTTL";
+ NET DSP_IRQ<3> LOC ="AG13"| IOSTANDARD = "LVTTL";
+ # NET DSP_L1DATIP<0> LOC ="AK29"| IOSTANDARD = "LVTTL";
+ # NET DSP_L0ACKI LOC ="AM18"| IOSTANDARD = "LVTTL";
+ # NET DSP_L1ACKO LOC ="AM15"| IOSTANDARD = "LVTTL";
+ # NET DSP_L0BCMPI LOC ="AM16"| IOSTANDARD = "LVTTL";
+ # NET DSP_L0BCMPO LOC ="AD21"| IOSTANDARD = "LVTTL";
+ # NET DSP_L1DATIN<0> LOC ="AJ29"| IOSTANDARD = "LVTTL";
+ # NET DSP_L1BCMPO LOC ="AJ20"| IOSTANDARD = "LVTTL";
+ # NET DSP_L1DATOP<0> LOC ="AK21"| IOSTANDARD = "LVTTL";
+ # NET DSP_L0DATON<0> LOC ="AM23"| IOSTANDARD = "LVTTL";
+ # NET DSP_L0ACKO LOC ="AM17"| IOSTANDARD = "LVTTL";
+ # NET DSP_L1CLKINN LOC ="AL30"| IOSTANDARD = "LVTTL";
+ # NET DSP_L1CLKOUTP LOC ="K18"| IOSTANDARD = "LVTTL";
+ # NET DSP_L0DATIN<0> LOC ="AM25"| IOSTANDARD = "LVTTL";
+ # NET DSP_L0CLKINP LOC ="AP29"| IOSTANDARD = "LVTTL";
+ # NET DSP_L1CLKOUTN LOC ="K17"| IOSTANDARD = "LVTTL";
+ # NET DSP_L1BCMPI LOC ="AL15"| IOSTANDARD = "LVTTL";
+ # NET DSP_L0CLKOUTN LOC ="AL25"| IOSTANDARD = "LVTTL";
+ # NET DSP_L1CLKINP LOC ="AM30"| IOSTANDARD = "LVTTL";
+ # NET DSP_L0DATOP<0> LOC ="AL23"| IOSTANDARD = "LVTTL";
+ # NET DSP_L1ACKI LOC ="AD20"| IOSTANDARD = "LVTTL";
+ # NET DSP_L0CLKINN LOC ="AN29"| IOSTANDARD = "LVTTL";
+ # NET DSP_L0DATIP<0> LOC ="AN25"| IOSTANDARD = "LVTTL";
+ # NET DSP_L1DATON<0> LOC ="AL21"| IOSTANDARD = "LVTTL";
+ # NET DSP_L0CLKOUTP LOC ="AL24"| IOSTANDARD = "LVTTL";
+ # NET DSP_L0DATIN<1> LOC ="AN24"| IOSTANDARD = "LVTTL";
+ # NET DSP_L1DATIP<1> LOC ="AF28"| IOSTANDARD = "LVTTL";
+ # NET DSP_L1DATIN<1> LOC ="AE27"| IOSTANDARD = "LVTTL";
+ # NET DSP_L0DATON<1> LOC ="AN23"| IOSTANDARD = "LVTTL";
+ # NET DSP_L0DATOP<1> LOC ="AN22"| IOSTANDARD = "LVTTL";
+ # NET DSP_L1DATOP<1> LOC ="AH28"| IOSTANDARD = "LVTTL";
+ # NET DSP_L0DATIP<1> LOC ="AP24"| IOSTANDARD = "LVTTL";
+ # NET DSP_L1DATON<1> LOC ="AH29"| IOSTANDARD = "LVTTL";
+ # NET DSP_L0DATON<2> LOC ="AH25"| IOSTANDARD = "LVTTL";
+ # NET DSP_L0DATOP<2> LOC ="AJ25"| IOSTANDARD = "LVTTL";
+ # NET DSP_L1DATIP<2> LOC ="AF26"| IOSTANDARD = "LVTTL";
+ # NET DSP_L1DATOP<2> LOC ="AP30"| IOSTANDARD = "LVTTL";
+ # NET DSP_L0DATIP<2> LOC ="AM26"| IOSTANDARD = "LVTTL";
+ # NET DSP_L1DATIN<2> LOC ="AE26"| IOSTANDARD = "LVTTL";
+ # NET DSP_L1DATON<2> LOC ="AN30"| IOSTANDARD = "LVTTL";
+ # NET DSP_L0DATIN<2> LOC ="AM27"| IOSTANDARD = "LVTTL";
+ # NET DSP_L1DATIP<3> LOC ="AN32"| IOSTANDARD = "LVTTL";
+ # NET DSP_L0DATIP<3> LOC ="AP21"| IOSTANDARD = "LVTTL";
+ # NET DSP_L0DATOP<3> LOC ="AL26"| IOSTANDARD = "LVTTL";
+ # NET DSP_L0DATIN<3> LOC ="AP22"| IOSTANDARD = "LVTTL";
+ # NET DSP_L1DATON<3> LOC ="AG28"| IOSTANDARD = "LVTTL";
+ # NET DSP_L1DATOP<3> LOC ="AG27"| IOSTANDARD = "LVTTL";
+ # NET DSP_L1DATIN<3> LOC ="AN33"| IOSTANDARD = "LVTTL";
+ # NET DSP_L0DATON<3> LOC ="AK26"| IOSTANDARD = "LVTTL";
+ # NET DSP_MSH LOC ="AL14"| IOSTANDARD = "LVTTL";
+ NET DSP_RD LOC ="AJ22"| IOSTANDARD = "LVTTL";
+ NET DSP_RESET LOC ="AG22"| IOSTANDARD = "LVTTL";
+ NET DSP_RESET_OUT LOC ="AH22"| IOSTANDARD = "LVTTL";
+ # NET DSP_TMROE LOC ="AP20"| IOSTANDARD = "LVTTL";
+ NET DSP_WRH LOC ="AJ21"| IOSTANDARD = "LVTTL";
+ NET DSP_WRL LOC ="AC15"| IOSTANDARD = "LVTTL";
+ NET DWAIT LOC ="H33"| IOSTANDARD = "LVTTL";
+ NET D_CSB LOC ="M2";
+ NET D_CS LOC ="M3";
+ NET D_DATA_READY LOC ="E11"| IOSTANDARD = "LVTTL";
+ NET D_RESERVED LOC ="G8"| IOSTANDARD = "LVTTL";
+ NET D_SCK LOC ="M6";
+ NET D_SCKB LOC ="M5";
+ NET D_SDI LOC ="K3";
+ NET D_SDIB LOC ="L3";
+ NET D_SDO LOC ="K2";
+ NET D_SDOB LOC ="K1";
+ NET D_TDC_BU_RESET LOC ="K6";
+ NET D_TDC_BU_RESETB LOC ="L6";
+ NET D_TDC_ERROR LOC ="H12"| IOSTANDARD = "LVTTL";
+ NET D_TDC_EV_RESET LOC ="L8";
+ NET D_TDC_EV_RESETB LOC ="M8";
+ NET D_TDC_POWERUP LOC ="J7"| IOSTANDARD = "LVTTL";
+ NET D_TEMP LOC ="C14"| IOSTANDARD = "LVTTL";
+ NET D_TEST1B LOC ="M1";
+ NET D_TEST2B LOC ="P5";
+ NET D_TEST1 LOC ="L1";
+ NET D_TEST2 LOC ="N5";
+ NET D_TRIGGER LOC ="P12";
+ NET D_TRIGGERB LOC ="P11";
+ NET ETRAX_IRQ LOC ="AK12"| IOSTANDARD = "LVTTL";
+ NET FS_PB<0> LOC ="AL5"| IOSTANDARD = "LVTTL";
+ NET FS_PB<1> LOC ="AL4"| IOSTANDARD = "LVTTL";
+ NET FS_PB<2> LOC ="AK4"| IOSTANDARD = "LVTTL";
+ NET FS_PB<3> LOC ="AJ4"| IOSTANDARD = "LVTTL";
+ NET FS_PB<4> LOC ="AP4"| IOSTANDARD = "LVTTL";
+ NET FS_PB<5> LOC ="AN4"| IOSTANDARD = "LVTTL";
+ NET FS_PB<6> LOC ="AD10"| IOSTANDARD = "LVTTL";
+ NET FS_PB<7> LOC ="AD9"| IOSTANDARD = "LVTTL";
+ NET FS_PB<8> LOC ="AN14"| IOSTANDARD = "LVTTL";
+ NET FS_PB<9> LOC ="AP14"| IOSTANDARD = "LVTTL";
+ NET FS_PB<10> LOC ="AJ6"| IOSTANDARD = "LVTTL";
+ NET FS_PB<11> LOC ="AJ5"| IOSTANDARD = "LVTTL";
+ NET FS_PB<12> LOC ="AK7"| IOSTANDARD = "LVTTL";
+ NET FS_PB<13> LOC ="AJ7"| IOSTANDARD = "LVTTL";
+ NET FS_PB<14> LOC ="AN3"| IOSTANDARD = "LVTTL";
+ NET FS_PB<15> LOC ="AN2"| IOSTANDARD = "LVTTL";
+ NET FS_PB<16> LOC ="AK13"| IOSTANDARD = "LVTTL";
+ NET FS_PB<17> LOC ="AL13"| IOSTANDARD = "LVTTL";
+ NET FS_PC<0> LOC ="AL6"| IOSTANDARD = "LVTTL";
+ NET FS_PC<1> LOC ="AK6"| IOSTANDARD = "LVTTL";
+ NET FS_PC<2> LOC ="AL8"| IOSTANDARD = "LVTTL";
+ NET FS_PC<3> LOC ="AK8"| IOSTANDARD = "LVTTL";
+ NET FS_PC<4> LOC ="AH8"| IOSTANDARD = "LVTTL";
+ NET FS_PC<5> LOC ="AH7"| IOSTANDARD = "LVTTL";
+ NET FS_PC<6> LOC ="AM13"| IOSTANDARD = "LVTTL";
+ NET FS_PC<7> LOC ="AN13"| IOSTANDARD = "LVTTL";
+ NET FS_PC<8> LOC ="AM6"| IOSTANDARD = "LVTTL";
+ NET FS_PC<9> LOC ="AM5"| IOSTANDARD = "LVTTL";
+ NET FS_PC<10> LOC ="AJ10"| IOSTANDARD = "LVTTL";
+ NET FS_PC<11> LOC ="AJ9"| IOSTANDARD = "LVTTL";
+ NET FS_PC<12> LOC ="AP5"| IOSTANDARD = "LVTTL";
+ NET FS_PC<13> LOC ="AN5"| IOSTANDARD = "LVTTL";
+ NET FS_PC<14> LOC ="AP6"| IOSTANDARD = "LVTTL";
+ NET FS_PC<15> LOC ="AP7"| IOSTANDARD = "LVTTL";
+ NET FS_PC<16> LOC ="AM8"| IOSTANDARD = "LVTTL";
+ NET FS_PC<17> LOC ="AN8"| IOSTANDARD = "LVTTL";
+ # NET FS_PE<0> LOC ="V18"| IOSTANDARD = "LVTTL";
+ # NET FS_PE<1> LOC ="V13"| IOSTANDARD = "LVTTL";
+ # NET FS_PE<2> LOC ="V14"| IOSTANDARD = "LVTTL";
+ # NET FS_PE<3> LOC ="W17"| IOSTANDARD = "LVTTL";
+ NET GET_DATA LOC ="B13"| IOSTANDARD = "LVTTL";
+ # NET GND LOC ="V22"| IOSTANDARD = "LVTTL";
+ # NET N<18064815> LOC ="T16"| IOSTANDARD = "LVTTL";
+ # NET N<18064816> LOC ="U17"| IOSTANDARD = "LVTTL";
+ # NET N<18064817> LOC ="U21"| IOSTANDARD = "LVTTL";
+ # NET N<18064818> LOC ="Y18"| IOSTANDARD = "LVTTL";
+ # NET N<18064820> LOC ="T18"| IOSTANDARD = "LVTTL";
+ # NET N<23483794> LOC ="W20"| IOSTANDARD = "LVTTL";
+ # NET N<23492722> LOC ="V20"| IOSTANDARD = "LVTTL";
+ # NET N<23538587> LOC ="U22"| IOSTANDARD = "LVTTL";
+ # NET N<23548060> LOC ="R17"| IOSTANDARD = "LVTTL";
+ # NET N<23548615> LOC ="U15"| IOSTANDARD = "LVTTL";
+ # NET N<24265542> LOC ="W21"| IOSTANDARD = "LVTTL";
+ # NET N<24267225> LOC ="U13"| IOSTANDARD = "LVTTL";
+ # NET N<24269436> LOC ="F15"| IOSTANDARD = "LVTTL";
+ # NET N<24269444> LOC ="D15"| IOSTANDARD = "LVTTL";
+ # NET N<24326445> LOC ="AJ11"| IOSTANDARD = "LVTTL";
+ # NET N<24328654> LOC ="AK11"| IOSTANDARD = "LVTTL";
+ # NET N<33988559> LOC ="J31"| IOSTANDARD = "LVTTL";
+ # NET N<33988561> LOC ="K31"| IOSTANDARD = "LVTTL";
+ # NET N<34495448> LOC ="E22"| IOSTANDARD = "LVTTL";
+ # NET N<34503651> LOC ="D22"| IOSTANDARD = "LVTTL";
+ # NET N<36044982> LOC ="AK17"| IOSTANDARD = "LVTTL";
+ # NET N<36648023> LOC ="AG18"| IOSTANDARD = "LVTTL";
+ # NET N<36648025> LOC ="AG17"| IOSTANDARD = "LVTTL";
+ # NET N<36648033> LOC ="AE17"| IOSTANDARD = "LVTTL";
+ # NET N<36648035> LOC ="AE16"| IOSTANDARD = "LVTTL";
+ # NET N<36650772> LOC ="AJ17"| IOSTANDARD = "LVTTL";
+ # NET N<36650774> LOC ="AH17"| IOSTANDARD = "LVTTL";
+ # NET N<36704661> LOC ="AN28"| IOSTANDARD = "LVTTL";
+ # NET N<36704663> LOC ="AM28"| IOSTANDARD = "LVTTL";
+ # NET N<38694350> LOC ="AG5"| IOSTANDARD = "LVTTL";
+ # NET N<38697708> LOC ="AG6"| IOSTANDARD = "LVTTL";
+ # NET N<38810822> LOC ="K19"| IOSTANDARD = "LVTTL";
+ # NET N<38810824> LOC ="J19"| IOSTANDARD = "LVTTL";
+ # NET N<38810850> LOC ="E16"| IOSTANDARD = "LVTTL";
+ # NET N<38810852> LOC ="F16"| IOSTANDARD = "LVTTL";
+ # NET N<38813734> LOC ="G13"| IOSTANDARD = "LVTTL";
+ # NET N<38813742> LOC ="M17"| IOSTANDARD = "LVTTL";
+ # NET N<38813744> LOC ="N17"| IOSTANDARD = "LVTTL";
+ # NET N<38813770> LOC ="M18"| IOSTANDARD = "LVTTL";
+ # NET N<38813772> LOC ="L18"| IOSTANDARD = "LVTTL";
+ # NET N<38813774> LOC ="F13"| IOSTANDARD = "LVTTL";
+ # NET N<38821674> LOC ="D19"| IOSTANDARD = "LVTTL";
+ # NET N<38821676> LOC ="C19"| IOSTANDARD = "LVTTL";
+ # NET N<38821684> LOC ="C18"| IOSTANDARD = "LVTTL";
+ # NET N<38821698> LOC ="C17"| IOSTANDARD = "LVTTL";
+ # NET N<38821700> LOC ="D17"| IOSTANDARD = "LVTTL";
+ # NET N<38821702> LOC ="E19"| IOSTANDARD = "LVTTL";
+ # NET N<38824618> LOC ="C15"| IOSTANDARD = "LVTTL";
+ # NET N<38824620> LOC ="M16"| IOSTANDARD = "LVTTL";
+ # NET N<38824628> LOC ="N15"| IOSTANDARD = "LVTTL";
+ # NET N<38824642> LOC ="D20"| IOSTANDARD = "LVTTL";
+ # NET N<38824644> LOC ="C20"| IOSTANDARD = "LVTTL";
+ # NET N<38824646> LOC ="D16"| IOSTANDARD = "LVTTL";
+ # NET N<38827574> LOC ="A20"| IOSTANDARD = "LVTTL";
+ # NET N<38827602> LOC ="B20"| IOSTANDARD = "LVTTL";
+ # NET N<38857742> LOC ="AH23"| IOSTANDARD = "LVTTL";
+ # NET N<38857748> LOC ="AH24"| IOSTANDARD = "LVTTL";
+ # NET N<41716249> LOC ="W19"| IOSTANDARD = "LVTTL";
+ # NET N<44929647> LOC ="J2"| IOSTANDARD = "LVTTL";
+ # NET N<44929649> LOC ="J1"| IOSTANDARD = "LVTTL";
+ # NET N<44985997> LOC ="J17"| IOSTANDARD = "LVTTL";
+ # NET N<44986035> LOC ="H17"| IOSTANDARD = "LVTTL";
+ # NET N<45004261> LOC ="AK19"| IOSTANDARD = "LVTTL";
+ # NET N<45004289> LOC ="AJ19"| IOSTANDARD = "LVTTL";
+ # NET N<45476888> LOC ="K16"| IOSTANDARD = "LVTTL";
+ # NET N<45476902> LOC ="L16"| IOSTANDARD = "LVTTL";
+ # NET N<46190669> LOC ="E18"| IOSTANDARD = "LVTTL";
+ # NET N<46190671> LOC ="E17"| IOSTANDARD = "LVTTL";
+ # NET N<46461605> LOC ="E8"| IOSTANDARD = "LVTTL";
+ # NET N<46464939> LOC ="E7"| IOSTANDARD = "LVTTL";
+ # NET N<46481442> LOC ="AD19"| IOSTANDARD = "LVTTL";
+ # NET N<46481444> LOC ="AE19"| IOSTANDARD = "LVTTL";
+ # NET N<46736961> LOC ="AC25"| IOSTANDARD = "LVTTL";
+ # NET N<46741878> LOC ="AD26"| IOSTANDARD = "LVTTL";
+ NET REF_TDC_CLK LOC ="F18";
+ NET REF_TDC_CLKB LOC ="G18";
+ NET RESET_VIRT LOC ="AF16"| IOSTANDARD = "LVTTL";
+ NET SFP_LOS LOC ="M27"| IOSTANDARD = "LVTTL";
+ # NET SFP_MOD<0> LOC ="R23"| IOSTANDARD = "LVTTL";
+ # NET SFP_MOD<1> LOC ="K32"| IOSTANDARD = "LVTTL";
+ # NET SFP_MOD<2> LOC ="K33"| IOSTANDARD = "LVTTL";
+ # NET SFP_RATE_SEL LOC ="P27"| IOSTANDARD = "LVTTL";
+ NET SFP_TX_DIS LOC ="N27"| IOSTANDARD = "LVTTL";
+ # NET SFP_TX_FAULT LOC ="J32"| IOSTANDARD = "LVTTL";
+ NET TDC_OUT<0> LOC ="D12"| IOSTANDARD = "LVTTL";
+ NET TDC_OUT<1> LOC ="C12"| IOSTANDARD = "LVTTL";
+ NET TDC_OUT<2> LOC ="B10"| IOSTANDARD = "LVTTL";
+ NET TDC_OUT<3> LOC ="C10"| IOSTANDARD = "LVTTL";
+ NET TDC_OUT<4> LOC ="A11"| IOSTANDARD = "LVTTL";
+ NET TDC_OUT<5> LOC ="B11"| IOSTANDARD = "LVTTL";
+ NET TDC_OUT<6> LOC ="C9"| IOSTANDARD = "LVTTL";
+ NET TDC_OUT<7> LOC ="C8"| IOSTANDARD = "LVTTL";
+ NET TDC_OUT<8> LOC ="G12"| IOSTANDARD = "LVTTL";
+ NET TDC_OUT<9> LOC ="G11"| IOSTANDARD = "LVTTL";
+ NET TDC_OUT<10> LOC ="F10"| IOSTANDARD = "LVTTL";
+ NET TDC_OUT<11> LOC ="G10"| IOSTANDARD = "LVTTL";
+ NET TDC_OUT<12> LOC ="D11"| IOSTANDARD = "LVTTL";
+ NET TDC_OUT<13> LOC ="D10"| IOSTANDARD = "LVTTL";
+ NET TDC_OUT<14> LOC ="H10"| IOSTANDARD = "LVTTL";
+ NET TDC_OUT<15> LOC ="H9"| IOSTANDARD = "LVTTL";
+ NET TDC_OUT<16> LOC ="A14"| IOSTANDARD = "LVTTL";
+ NET TDC_OUT<17> LOC ="A13"| IOSTANDARD = "LVTTL";
+ NET TDC_OUT<18> LOC ="D7"| IOSTANDARD = "LVTTL";
+ NET TDC_OUT<19> LOC ="D6"| IOSTANDARD = "LVTTL";
+ NET TDC_OUT<20> LOC ="D9"| IOSTANDARD = "LVTTL";
+ NET TDC_OUT<21> LOC ="E9"| IOSTANDARD = "LVTTL";
+ NET TDC_OUT<22> LOC ="A4"| IOSTANDARD = "LVTTL";
+ NET TDC_OUT<23> LOC ="A3"| IOSTANDARD = "LVTTL";
+ NET TDC_OUT<24> LOC ="E13"| IOSTANDARD = "LVTTL";
+ NET TDC_OUT<25> LOC ="E12"| IOSTANDARD = "LVTTL";
+ NET TDC_OUT<26> LOC ="A5"| IOSTANDARD = "LVTTL";
+ NET TDC_OUT<27> LOC ="B5"| IOSTANDARD = "LVTTL";
+ NET TDC_OUT<28> LOC ="J9"| IOSTANDARD = "LVTTL";
+ NET TDC_OUT<29> LOC ="K9"| IOSTANDARD = "LVTTL";
+ NET TDC_OUT<30> LOC ="B3"| IOSTANDARD = "LVTTL";
+ NET TDC_OUT<31> LOC ="B2"| IOSTANDARD = "LVTTL";
+ NET TDC_RESET LOC ="C5"| IOSTANDARD = "LVTTL";
+ NET TLK_CLK LOC ="AG16"| IOSTANDARD = "LVTTL";
+ NET TLK_ENABLE LOC ="R24"| IOSTANDARD = "LVTTL";
+ NET TLK_LCKREFN LOC ="L28"| IOSTANDARD = "LVTTL";
+ NET TLK_LOOPEN LOC ="R19"| IOSTANDARD = "LVTTL";
+ NET TLK_PRBSEN LOC ="H32"| IOSTANDARD = "LVTTL";
+ NET TLK_RXD<0> LOC ="G30"| IOSTANDARD = "LVTTL";
+ NET TLK_RXD<1> LOC ="G31"| IOSTANDARD = "LVTTL";
+ NET TLK_RXD<2> LOC ="J29"| IOSTANDARD = "LVTTL";
+ NET TLK_RXD<3> LOC ="J30"| IOSTANDARD = "LVTTL";
+ NET TLK_RXD<4> LOC ="E32"| IOSTANDARD = "LVTTL";
+ NET TLK_RXD<5> LOC ="E33"| IOSTANDARD = "LVTTL";
+ NET TLK_RXD<6> LOC ="N25"| IOSTANDARD = "LVTTL";
+ NET TLK_RXD<7> LOC ="P26"| IOSTANDARD = "LVTTL";
+ NET TLK_RXD<8> LOC ="P22"| IOSTANDARD = "LVTTL";
+ NET TLK_RXD<9> LOC ="R21"| IOSTANDARD = "LVTTL";
+ NET TLK_RXD<10> LOC ="F33"| IOSTANDARD = "LVTTL";
+ NET TLK_RXD<11> LOC ="F34"| IOSTANDARD = "LVTTL";
+ NET TLK_RXD<12> LOC ="K28"| IOSTANDARD = "LVTTL";
+ NET TLK_RXD<13> LOC ="K29"| IOSTANDARD = "LVTTL";
+ NET TLK_RXD<14> LOC ="G32"| IOSTANDARD = "LVTTL";
+ NET TLK_RXD<15> LOC ="G33"| IOSTANDARD = "LVTTL";
+ NET TLK_RX_CLK LOC ="AF18"| IOSTANDARD = "LVTTL";
+ NET TLK_RX_DV LOC ="M30"| IOSTANDARD = "LVTTL";
+ NET TLK_RX_ER LOC ="P20"| IOSTANDARD = "LVTTL";
+ NET TLK_TXD<0> LOC ="H27"| IOSTANDARD = "LVTTL";
+ NET TLK_TXD<1> LOC ="H28"| IOSTANDARD = "LVTTL";
+ NET TLK_TXD<2> LOC ="C32"| IOSTANDARD = "LVTTL";
+ NET TLK_TXD<3> LOC ="D32"| IOSTANDARD = "LVTTL";
+ NET TLK_TXD<4> LOC ="J27"| IOSTANDARD = "LVTTL";
+ NET TLK_TXD<5> LOC ="K27"| IOSTANDARD = "LVTTL";
+ NET TLK_TXD<6> LOC ="M25"| IOSTANDARD = "LVTTL";
+ NET TLK_TXD<7> LOC ="M26"| IOSTANDARD = "LVTTL";
+ NET TLK_TXD<8> LOC ="N22"| IOSTANDARD = "LVTTL";
+ NET TLK_TXD<9> LOC ="N23"| IOSTANDARD = "LVTTL";
+ NET TLK_TXD<10> LOC ="H29"| IOSTANDARD = "LVTTL";
+ NET TLK_TXD<11> LOC ="H30"| IOSTANDARD = "LVTTL";
+ NET TLK_TXD<12> LOC ="C33"| IOSTANDARD = "LVTTL";
+ NET TLK_TXD<13> LOC ="C34"| IOSTANDARD = "LVTTL";
+ NET TLK_TXD<14> LOC ="D34"| IOSTANDARD = "LVTTL";
+ NET TLK_TXD<15> LOC ="E34"| IOSTANDARD = "LVTTL";
+ NET TLK_TX_EN LOC ="L29"| IOSTANDARD = "LVTTL";
+ NET TLK_TX_ER LOC ="P24"| IOSTANDARD = "LVTTL";
+ NET TOKEN_IN LOC ="E6"| IOSTANDARD = "LVTTL";
+ NET TOKEN_OUT LOC ="C13"| IOSTANDARD = "LVTTL";
+ NET VIRT_CLK LOC ="H19";
+ NET VIRT_CLKB LOC ="H18";
+ NET VIRT_TCK LOC ="K34"| IOSTANDARD = "LVTTL";
+ NET VIRT_TDI LOC ="M31"| IOSTANDARD = "LVTTL";
+ NET VIRT_TDO LOC ="N30"| IOSTANDARD = "LVTTL";
+ NET VIRT_TMS LOC ="J34"| IOSTANDARD = "LVTTL";
+ NET VIRT_TRST LOC ="N29"| IOSTANDARD = "LVTTL";
+ NET VIR_TRIG LOC ="E3";
+ NET VIR_TRIGB LOC ="E2";
+ NET VSD_A<0> LOC ="F23"| IOSTANDARD = "LVTTL";
+ NET VSD_A<1> LOC ="E23"| IOSTANDARD = "LVTTL";
+ NET VSD_A<2> LOC ="D26"| IOSTANDARD = "LVTTL";
+ NET VSD_A<3> LOC ="E26"| IOSTANDARD = "LVTTL";
+ NET VSD_A<4> LOC ="F24"| IOSTANDARD = "LVTTL";
+ NET VSD_A<5> LOC ="E24"| IOSTANDARD = "LVTTL";
+ NET VSD_A<6> LOC ="D27"| IOSTANDARD = "LVTTL";
+ NET VSD_A<7> LOC ="E27"| IOSTANDARD = "LVTTL";
+ NET VSD_A<8> LOC ="G23"| IOSTANDARD = "LVTTL";
+ NET VSD_A<9> LOC ="H24"| IOSTANDARD = "LVTTL";
+ NET VSD_A<10> LOC ="A28"| IOSTANDARD = "LVTTL";
+ NET VSD_A<11> LOC ="A29"| IOSTANDARD = "LVTTL";
+ NET VSD_A<12> LOC ="B25"| IOSTANDARD = "LVTTL";
+ NET VSD_BA<0> LOC ="C25"| IOSTANDARD = "LVTTL";
+ NET VSD_BA<1> LOC ="J25"| IOSTANDARD = "LVTTL";
+ NET VSD_CAS LOC ="G28"| IOSTANDARD = "LVTTL";
+ NET VSD_CKE LOC ="D30"| IOSTANDARD = "LVTTL";
+ NET VSD_CLOCK LOC ="B28"| IOSTANDARD = "LVTTL";
+ NET VSD_CSEH LOC ="G27"| IOSTANDARD = "LVTTL";
+ NET VSD_CSEL LOC ="D31"| IOSTANDARD = "LVTTL";
+ NET VSD_D<0> LOC ="B23"| IOSTANDARD = "LVTTL";
+ NET VSD_D<1> LOC ="A23"| IOSTANDARD = "LVTTL";
+ NET VSD_D<2> LOC ="A26"| IOSTANDARD = "LVTTL";
+ NET VSD_D<3> LOC ="B26"| IOSTANDARD = "LVTTL";
+ NET VSD_D<4> LOC ="A24"| IOSTANDARD = "LVTTL";
+ NET VSD_D<5> LOC ="A25"| IOSTANDARD = "LVTTL";
+ NET VSD_D<6> LOC ="G25"| IOSTANDARD = "LVTTL";
+ NET VSD_D<7> LOC ="H25"| IOSTANDARD = "LVTTL";
+ NET VSD_D<8> LOC ="C23"| IOSTANDARD = "LVTTL";
+ NET VSD_D<9> LOC ="C24"| IOSTANDARD = "LVTTL";
+ NET VSD_D<10> LOC ="F25"| IOSTANDARD = "LVTTL";
+ NET VSD_D<11> LOC ="F26"| IOSTANDARD = "LVTTL";
+ NET VSD_D<12> LOC ="D24"| IOSTANDARD = "LVTTL";
+ NET VSD_D<13> LOC ="D25"| IOSTANDARD = "LVTTL";
+ NET VSD_D<14> LOC ="B27"| IOSTANDARD = "LVTTL";
+ NET VSD_D<15> LOC ="C27"| IOSTANDARD = "LVTTL";
+ NET VSD_D<16> LOC ="C22"| IOSTANDARD = "LVTTL";
+ NET VSD_D<17> LOC ="B22"| IOSTANDARD = "LVTTL";
+ NET VSD_D<18> LOC ="A30"| IOSTANDARD = "LVTTL";
+ NET VSD_D<19> LOC ="B30"| IOSTANDARD = "LVTTL";
+ NET VSD_D<20> LOC ="K24"| IOSTANDARD = "LVTTL";
+ NET VSD_D<21> LOC ="J24"| IOSTANDARD = "LVTTL";
+ NET VSD_D<22> LOC ="C29"| IOSTANDARD = "LVTTL";
+ NET VSD_D<23> LOC ="C30"| IOSTANDARD = "LVTTL";
+ NET VSD_D<24> LOC ="B21"| IOSTANDARD = "LVTTL";
+ NET VSD_D<25> LOC ="A21"| IOSTANDARD = "LVTTL";
+ NET VSD_D<26> LOC ="E28"| IOSTANDARD = "LVTTL";
+ NET VSD_D<27> LOC ="F28"| IOSTANDARD = "LVTTL";
+ NET VSD_D<28> LOC ="A31"| IOSTANDARD = "LVTTL";
+ NET VSD_D<29> LOC ="B31"| IOSTANDARD = "LVTTL";
+ NET VSD_D<30> LOC ="E31"| IOSTANDARD = "LVTTL";
+ NET VSD_D<31> LOC ="F31"| IOSTANDARD = "LVTTL";
+ NET VSD_DQML<0> LOC ="F30"| IOSTANDARD = "LVTTL";
+ NET VSD_DQML<1> LOC ="D29"| IOSTANDARD = "LVTTL";
+ NET VSD_DQML<2> LOC ="E29"| IOSTANDARD = "LVTTL";
+ NET VSD_DQML<3> LOC ="L25"| IOSTANDARD = "LVTTL";
+ NET VSD_RAS LOC ="F29"| IOSTANDARD = "LVTTL";
+ NET VSD_WE LOC ="K26"| IOSTANDARD = "LVTTL";
+# OFFSET=OUT 2 ns BEFORE "VIRT_CLK" HIGH;
+# OFFSET=IN 6 ns BEFORE "VIRT_CLK" HIGH;
+
+# OFFSET=IN 6 ns BEFORE "REF_TDC_CLK" HIGH;
+# OFFSET=OUT 2 ns BEFORE "REF_TDC_CLK" HIGH;
+
+ NET "VIRT_CLK" TNM_NET =VIRT_CLK;
+ TIMESPEC TS_VIRT_CLK =PERIOD "VIRT_CLK" 9 ns;
+ NET "REF_TDC_CLK" TNM_NET = REF_TDC_CLK;
+ TIMESPEC TS_REF_TDC_CLK = PERIOD "REF_TDC_CLK" 10 ns;
+
+ NET "TOKEN_OUT" OFFSET = OUT 12 ns AFTER "REF_TDC_CLK" HIGH;
+ NET "A_DATA_READY" OFFSET = IN 0.5 ns BEFORE "REF_TDC_CLK" HIGH;
+ NET "B_DATA_READY" OFFSET = IN 0.5 ns BEFORE "REF_TDC_CLK" HIGH;
+ NET "C_DATA_READY" OFFSET = IN 0.5 ns BEFORE "REF_TDC_CLK" HIGH;
+ NET "D_DATA_READY" OFFSET = IN 0.5 ns BEFORE "REF_TDC_CLK" HIGH;
\ No newline at end of file
--- /dev/null
+ library IEEE;
+-- use IEEE.STD_LOGIC_1164.ALL;
+-- use IEEE.STD_LOGIC_ARITH.ALL;
+ use IEEE.STD_LOGIC_UNSIGNED.ALL;
+-- use IEEE.NUMERIC_STD.all;
+
+-- -- use work.support.all;
+ library UNISIM;
+ use UNISIM.VCOMPONENTS.all;
+-- use ieee.numeric_std.all;
+-- use ieee.std_logic_arith.all;
+library ieee;
+library work;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+--library unisim;
+--use unisim.all;
+use work.all;
+-- -- Uncomment the following lines to use the declarations that are
+-- -- provided for instantiating Xilinx primitive components.
+-- library UNISIM;
+-- use UNISIM.VComponents.all;
+
+entity trb_v2b_fpga is
+ port (
+ -------------------------------------------------------------------------
+ -- GENERAL
+ -------------------------------------------------------------------------
+ VIRT_CLK : in std_logic;
+ VIRT_CLKB : in std_logic;
+ RESET_VIRT : in std_logic;
+ DBAD : out std_logic; --diode
+ DGOOD : out std_logic; --diode
+ DINT : out std_logic; --diode
+ DWAIT : out std_logic; --diode
+ A_RESERVED : in std_logic; --TDC connector 75,76(line 3 from end)
+ A_TEMP : in std_logic; -- |
+ B_RESERVED : in std_logic; -- |
+ B_TEMP : in std_logic; -- V
+ C_RESERVED : in std_logic;
+ C_TEMP : in std_logic;
+ D_RESERVED : in std_logic;
+ D_TEMP : in std_logic;
+ VIR_TRIG : in std_logic; --fast trigger
+ VIR_TRIGB : in std_logic;
+ -------------------------------------------------------------------------
+ -- TDC connections
+ -------------------------------------------------------------------------
+ A_TDC_ERROR : in std_logic;
+ B_TDC_ERROR : in std_logic;
+ C_TDC_ERROR : in std_logic;
+ D_TDC_ERROR : in std_logic;
+ A_TDC_POWERUP : out std_logic; --turn on TDC -should be one ?!
+ B_TDC_POWERUP : out std_logic;
+ C_TDC_POWERUP : out std_logic;
+ D_TDC_POWERUP : out std_logic;
+ TOKEN_IN : in std_logic;
+ TOKEN_OUT : out std_logic;
+ C_TOKEN_OUT_TTL : in std_logic;
+ GET_DATA : out std_logic;
+ A_DATA_READY : in std_logic;
+ B_DATA_READY : in std_logic;
+ C_DATA_READY : in std_logic;
+ D_DATA_READY : in std_logic;
+ REF_TDC_CLK : in std_logic;
+ REF_TDC_CLKB : in std_logic;
+ -- TDC_BU_RESET : out std_logic;
+ -- TDC_BU_RESETB : out std_logic;
+ -- TDC_EV_RESET : out std_logic;
+ -- TDC_EV_RESETB : out std_logic;
+ A_TDC_BU_RESET : out std_logic;
+ A_TDC_BU_RESETB : out std_logic;
+ A_TDC_EV_RESET : out std_logic;
+ A_TDC_EV_RESETB : out std_logic;
+ B_TDC_BU_RESET : out std_logic;
+ B_TDC_BU_RESETB : out std_logic;
+ B_TDC_EV_RESET : out std_logic;
+ B_TDC_EV_RESETB : out std_logic;
+ C_TDC_BU_RESET : out std_logic;
+ C_TDC_BU_RESETB : out std_logic;
+ C_TDC_EV_RESET : out std_logic;
+ C_TDC_EV_RESETB : out std_logic;
+ D_TDC_BU_RESET : out std_logic;
+ D_TDC_BU_RESETB : out std_logic;
+ D_TDC_EV_RESET : out std_logic;
+ D_TDC_EV_RESETB : out std_logic;
+
+ TDC_OUT : in std_logic_vector (31 downto 0);
+ TDC_RESET : out std_logic;
+ A_TRIGGER : out std_logic;
+ A_TRIGGERB : out std_logic;
+ B_TRIGGER : out std_logic;
+ B_TRIGGERB : out std_logic;
+ C_TRIGGER : out std_logic;
+ C_TRIGGERB : out std_logic;
+ D_TRIGGER : out std_logic;
+ D_TRIGGERB : out std_logic;
+ -------------------------------------------------------------------------
+ -- ETRAX connections
+ -------------------------------------------------------------------------
+ FS_PB : out std_logic_vector (17 downto 0);
+ FS_PC : inout std_logic_vector (17 downto 0);
+ ETRAX_IRQ : out std_logic;
+ -------------------------------------------------------------------------
+ -- SPI
+ -------------------------------------------------------------------------
+ A_SCK : out std_logic;
+ A_SCKB : out std_logic;
+ A_SDI : in std_logic;
+ A_SDIB : in std_logic;
+ A_SDO : out std_logic;
+ A_SDOB : out std_logic;
+ A_CSB : out std_logic;
+ A_CS : out std_logic;
+
+ B_SCK : out std_logic;
+ B_SCKB : out std_logic;
+ B_SDI : in std_logic;
+ B_SDIB : in std_logic;
+ B_SDO : out std_logic;
+ B_SDOB : out std_logic;
+ B_CSB : out std_logic;
+ B_CS : out std_logic;
+
+ C_SCK : out std_logic;
+ C_SCKB : out std_logic;
+ C_SDI : in std_logic;
+ C_SDIB : in std_logic;
+ C_SDO : out std_logic;
+ C_SDOB : out std_logic;
+ C_CSB : out std_logic;
+ C_CS : out std_logic;
+
+ D_SCK : out std_logic;
+ D_SCKB : out std_logic;
+ D_SDI : in std_logic;
+ D_SDIB : in std_logic;
+ D_SDO : out std_logic;
+ D_SDOB : out std_logic;
+ D_CSB : out std_logic;
+ D_CS : out std_logic;
+ -------------------------------------------------------------------------
+ -- TEST SIGNALS - for RPC
+ -------------------------------------------------------------------------
+ A_TEST1 : out std_logic;
+ A_TEST1B : out std_logic;
+ A_TEST2 : out std_logic;
+ A_TEST2B : out std_logic;
+ B_TEST1 : out std_logic;
+ B_TEST1B : out std_logic;
+ B_TEST2 : out std_logic;
+ B_TEST2B : out std_logic;
+ C_TEST1 : out std_logic;
+ C_TEST1B : out std_logic;
+ C_TEST2 : out std_logic;
+ C_TEST2B : out std_logic;
+ D_TEST1 : out std_logic;
+ D_TEST1B : out std_logic;
+ D_TEST2 : out std_logic;
+ D_TEST2B : out std_logic;
+ -------------------------------------------------------------------------
+ -- SHARC
+ -------------------------------------------------------------------------
+ DSPADDR : out std_logic_vector (31 downto 0);
+ DSPDAT : inout std_logic_vector (31 downto 0);
+ DSP_ACK : in std_logic;
+ DSP_BM : inout std_logic;
+ DSP_BMS : out std_logic; --LOC = AF15;
+ DSP_BOFF : out std_logic; -- LOC = AK14;
+ DSP_BRST : inout std_logic;
+ DSP_HBG : in std_logic;
+ DSP_HBR : out std_logic;
+ DSP_IRQ : out std_logic_vector (3 downto 0);
+
+
+
+-- --link0
+-- DSP_L0DATIP : out std_logic_vector (3 downto 0);
+-- DSP_L0DATIN : out std_logic_vector (3 downto 0);
+-- DSP_L0DATOP : in std_logic_vector (3 downto 0);
+-- DSP_L0DATON : in std_logic_vector (3 downto 0);
+-- DSP_L0CLKINP : out std_logic;
+-- DSP_L0CLKINN : out std_logic;
+-- DSP_L0CLKOUTP : in std_logic;
+-- DSP_L0CLKOUTN : in std_logic;
+-- DSP_L0BCMPO : in std_logic;
+-- DSP_L0ACKO : in std_logic;
+-- DSP_L0BCMPI : out std_logic;
+-- DSP_L0ACKI : out std_logic;
+-- --link1
+-- DSP_L1DATIP : out std_logic_vector (3 downto 0);
+-- DSP_L1DATIN : out std_logic_vector (3 downto 0);
+-- DSP_L1DATOP : in std_logic_vector (3 downto 0);
+-- DSP_L1DATON : in std_logic_vector (3 downto 0);
+-- DSP_L1CLKINP : out std_logic;
+-- DSP_L1CLKINN : out std_logic;
+-- DSP_L1CLKOUTP : in std_logic;
+-- DSP_L1CLKOUTN : in std_logic;
+-- DSP_L1ACKO : in std_logic;
+-- DSP_L1BCMPO : in std_logic;
+-- DSP_L1BCMPI : out std_logic;
+-- DSP_L1ACKI : out std_logic;
+
+
+
+
+
+-- DSP_TMROE : LOC = AP20; --link data widt now is 4 bit --pullup
+
+
+ DSP_RD : out std_logic;
+ DSP_RESET : out std_logic;
+ DSP_RESET_OUT : in std_logic;
+ DSP_WRH : out std_logic;
+ DSP_WRL : out std_logic;
+ -- DSP_MSH LOC = AL14;
+ -- DSP_IOEN LOC = AL18;
+ -- DSP_IORD LOC = AB16;
+ -- DSP_IOWR LOC = AB17;
+ -- DSP_BUSLOCK LOC = AC19;
+ -- DSP_DMAR : std_logic_vector (3 downto 0);
+ -- DSP_FLAG : std_logic_vector (3 downto 0);
+
+ -------------------------------------------------------------------------
+ -- SDRAM
+ -------------------------------------------------------------------------
+ VSD_A : out std_logic_vector (12 downto 0);
+ VSD_BA : out std_logic_vector (1 downto 0);
+ VSD_CAS : out std_logic;
+ VSD_CKE : out std_logic;
+ VSD_CLOCK : out std_logic;
+ VSD_CSEH : out std_logic;
+ VSD_CSEL : out std_logic;
+ VSD_D : inout std_logic_vector (31 downto 0);
+ VSD_DQML : out std_logic_vector (3 downto 0);
+ VSD_RAS : out std_logic;
+ VSD_WE : out std_logic;
+ -------------------------------------------------------------------------
+ -- TLK
+ -------------------------------------------------------------------------
+ TLK_CLK : in std_logic;
+ TLK_ENABLE : out std_logic;
+ TLK_LCKREFN : out std_logic;
+ TLK_LOOPEN : out std_logic;
+ TLK_PRBSEN : out std_logic;
+ TLK_RXD : in std_logic_vector (15 downto 0);
+ TLK_RX_CLK : in std_logic;
+ TLK_RX_DV : in std_logic;
+ TLK_RX_ER : in std_logic;
+ TLK_TXD : out std_logic_vector (15 downto 0);
+ TLK_TX_EN : out std_logic;
+ TLK_TX_ER : out std_logic;
+ -------------------------------------------------------------------------
+ -- SFP
+ -------------------------------------------------------------------------
+ SFP_LOS : in std_logic;
+ -- SFP_MOD<0> LOC = R23;
+ -- SFP_MOD<1> LOC = K32;
+ -- SFP_MOD<2> LOC = K33;
+ -- SFP_RATE_SEL : out std_logic;
+ SFP_TX_DIS : out std_logic;
+ SFP_TX_FAULT : in std_logic;
+ -------------------------------------------------------------------------
+ -- ADDON board
+ -------------------------------------------------------------------------
+ -- ADDON_TO_TRB_CLKINN : std_logic;
+ -- ADDON_TO_TRB_CLKINP : std_logic;
+ ADO_LV : in std_logic_vector(51 downto 0); --lvds signal
+ ADO_TTL : inout std_logic_vector(46 downto 0);
+ -------------------------------------------------------------------------------
+ --JTAG
+ -------------------------------------------------------------------------------
+ VIRT_TCK : out std_logic;
+ VIRT_TDI : out std_logic;
+ VIRT_TDO : in std_logic;
+ VIRT_TMS : out std_logic;
+ VIRT_TRST : out std_logic
+ );
+ end trb_v2b_fpga;
+architecture trb_v2b_fpga of trb_v2b_fpga is
+ component trb_net16_endpoint_0_trg_1_api
+ generic (
+ API_TYPE : integer range 0 to 1;
+ INIT_DEPTH : integer range 0 to 6;
+ REPLY_DEPTH : integer range 0 to 6;
+ FIFO_TO_INT_DEPTH : integer range 0 to 6;
+ FIFO_TO_APL_DEPTH : integer range 0 to 6;
+ SBUF_VERSION : integer range 0 to 1;
+ MUX_WIDTH : integer range 1 to 5;
+ MUX_SECURE_MODE : integer range 0 to 1;
+ DAT_CHANNEL : integer range 0 to 3;--**(MUX_WIDTH-1);
+ DATA_WIDTH : integer;
+ NUM_WIDTH : integer);
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ MED_DATAREADY_OUT : out std_logic;
+ MED_DATA_OUT : out std_logic_vector (15 downto 0);
+ MED_PACKET_NUM_OUT : out std_logic_vector (1 downto 0);
+ MED_READ_IN : in std_logic;
+ MED_DATAREADY_IN : in std_logic;
+ MED_DATA_IN : in std_logic_vector (15 downto 0);
+ MED_PACKET_NUM_IN : in std_logic_vector (1 downto 0);
+ MED_READ_OUT : out std_logic;
+ MED_ERROR_IN : in std_logic_vector (2 downto 0);
+ APL_DATA_IN : in std_logic_vector (15 downto 0);
+ APL_PACKET_NUM_IN : in std_logic_vector (1 downto 0);
+ APL_WRITE_IN : in std_logic;
+ APL_FIFO_FULL_OUT : out std_logic;
+ APL_SHORT_TRANSFER_IN : in std_logic;
+ APL_DTYPE_IN : in std_logic_vector (3 downto 0);
+ APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0);
+ APL_SEND_IN : in std_logic;
+ APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0);
+ APL_DATA_OUT : out std_logic_vector (15 downto 0);
+ APL_PACKET_NUM_OUT : out std_logic_vector (1 downto 0);
+ APL_TYP_OUT : out std_logic_vector (2 downto 0);
+ APL_DATAREADY_OUT : out std_logic;
+ APL_READ_IN : in std_logic;
+ APL_RUN_OUT : out std_logic;
+ APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0);
+ APL_SEQNR_OUT : out std_logic_vector (7 downto 0);
+ STAT_GEN : out std_logic_vector (31 downto 0);
+ STAT_LOCKED : out std_logic_vector (31 downto 0);
+ STAT_INIT_BUFFER : out std_logic_vector (31 downto 0);
+ STAT_REPLY_BUFFER : out std_logic_vector (31 downto 0);
+ STAT_api_control_signals : out std_logic_vector(31 downto 0);
+ STAT_MPLEX : out std_logic_vector(31 downto 0);
+ CTRL_GEN : in std_logic_vector (31 downto 0);
+ CTRL_LOCKED : in std_logic_vector (31 downto 0);
+ STAT_CTRL_INIT_BUFFER : in std_logic_vector (31 downto 0);
+ STAT_CTRL_REPLY_BUFFER : in std_logic_vector (31 downto 0);
+ MPLEX_CTRL : in std_logic_vector (31 downto 0);
+ API_STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0);
+ API_STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0));
+ end component;
+ component tdc_interface
+ port (
+ CLK : in std_logic;
+ TDC_CLK : in std_logic;
+ RESET : in std_logic;
+ TDC_DATA_IN : in std_logic_vector (31 downto 0);
+ START_TDC_READOUT : in std_logic;
+ A_TDC_READY : in std_logic;
+ B_TDC_READY : in std_logic;
+ C_TDC_READY : in std_logic;
+ D_TDC_READY : in std_logic;
+ A_TDC_ERROR : in std_logic;
+ B_TDC_ERROR : in std_logic;
+ C_TDC_ERROR : in std_logic;
+ D_TDC_ERROR : in std_logic;
+ A_TDC_POWERUP : out std_logic;
+ B_TDC_POWERUP : out std_logic;
+ C_TDC_POWERUP : out std_logic;
+ D_TDC_POWERUP : out std_logic;
+ SEND_TDC_TOKEN : out std_logic;
+ RECEIVED_TDC_TOKEN : in std_logic;
+ GET_TDC_DATA : out std_logic;
+ TO_MANY_TDC_DATA : in std_logic;
+ TDC_READOUT_COMPLETED : out std_logic;
+ LVL1_TAG : in std_logic_vector(7 downto 0);
+ LVL1_CODE : in std_logic_vector(3 downto 0);
+ HOW_MANY_ADD_DATA : in std_logic_vector(7 downto 0);
+ COUNTER_a : in std_logic_vector(31 downto 0);
+ COUNTER_b : in std_logic_vector(31 downto 0);
+ COUNTER_c : in std_logic_vector(31 downto 0);
+ COUNTER_d : in std_logic_vector(31 downto 0);
+ COUNTER_e : in std_logic_vector(31 downto 0);
+ COUNTER_f : in std_logic_vector(31 downto 0);
+ COUNTER_g : in std_logic_vector(31 downto 0);
+ COUNTER_h : in std_logic_vector(31 downto 0);
+ LVL2_TRIGGER : in std_logic_vector(1 downto 0);
+ TDC_DATA_OUT : out std_logic_vector(31 downto 0);
+ TDC_DATA_VALID : out std_logic;
+ ETRAX_IS_READY_TO_READ : in std_logic;
+ LVL1_BUSY : out std_logic;
+ LVL2_BUSY : out std_logic;
+ TDC_REGISTER_00 : out std_logic_vector(31 downto 0);
+ TDC_REGISTER_01 : out std_logic_vector(31 downto 0);
+ TDC_REGISTER_02 : out std_logic_vector(31 downto 0);
+ TDC_REGISTER_03 : out std_logic_vector(31 downto 0);
+ TDC_REGISTER_04 : out std_logic_vector(31 downto 0);
+ BUNCH_RESET : out std_logic;
+ EVENT_RESET : out std_logic;
+ READ_ADRESS_END_UP : out std_logic; --here
+ DELAY_TRIGGER : in std_logic_vector(7 downto 0);
+ TDC_START : out std_logic;
+ TRIGGER_WITHOUT_HADES : in std_logic;
+ TRIGGER_WITH_GEN_EN : in std_logic;
+ TRIGGER_WITH_GEN : in std_logic
+ );
+ end component;
+ component etrax_interface
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ DATA_BUS : in std_logic_vector(31 downto 0);
+ ETRAX_DATA_BUS_B : out std_logic_vector(17 downto 0);
+ ETRAX_DATA_BUS_C : inout std_logic_vector(17 downto 0);
+ DATA_VALID : in std_logic;
+ ETRAX_BUS_BUSY : out std_logic;
+ ETRAX_IS_READY_TO_READ : out std_logic;
+ TDC_TCK : out std_logic;
+ TDC_TDI : out std_logic;
+ TDC_TMS : out std_logic;
+ TDC_TRST : out std_logic;
+ TDC_TDO : in std_logic;
+ TDC_RESET : out std_logic;
+ EXTERNAL_ADDRESS : out std_logic_vector(31 downto 0);
+ EXTERNAL_DATA_OUT : out std_logic_vector(31 downto 0);
+ EXTERNAL_DATA_IN : in std_logic_vector(31 downto 0);
+ EXTERNAL_ACK : out std_logic;
+ EXTERNAL_VALID : in std_logic;
+ EXTERNAL_MODE : out std_logic_vector(15 downto 0);
+ FPGA_REGISTER_00 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_01 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_02 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_03 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_04 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_05 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_06 : out std_logic_vector(31 downto 0);
+ FPGA_REGISTER_07 : out std_logic_vector(31 downto 0);
+ FPGA_REGISTER_08 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_09 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_0A : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_0B : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_0C : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_0D : in std_logic_vector(31 downto 0);
+ EXTERNAL_RESET : out std_logic;
+ LVL2_VALID : in std_logic
+ );
+ end component;
+ component tlk_interface
+ port (
+ VIRT_CLK : in std_logic;
+ ENABLE : out std_logic;
+ LCKREFN : out std_logic;
+ LOOPEN : out std_logic;
+ PRBSEN : out std_logic;
+ RX_CLK : in std_logic;
+ RX_DV : in std_logic;
+ RX_ER : in std_logic;
+ TLK_CLK : in std_logic;
+ TLK_RXD : in std_logic_vector (15 downto 0);
+ TLK_TXD : out std_logic_vector (15 downto 0);
+ TX_EN : out std_logic;
+ TX_ER : out std_logic;
+ RESET_VIRT : in std_logic;
+ TLK_REGISTER_00 : out std_logic_vector(31 downto 0);
+ TLK_REGISTER_01 : out std_logic_vector(31 downto 0);
+ SFP_LOS : in std_logic;
+ TX_DIS : out std_logic);
+ end component;
+ component dsp_interface
+ port (
+ -- signal to/from dsp
+ HBR_OUT : out std_logic; -- Host Bus Request to DSP
+ HBG_IN : in std_logic; -- Host Bus Grant from DSP
+ RD_OUT : out std_logic; -- read/write enable of DSP
+ DSP_DATA_OUT : out std_logic_vector(31 downto 0);
+ DSP_DATA_IN : in std_logic_vector(31 downto 0);
+ ADDRESS_DSP : out std_logic_vector(31 downto 0);
+ WRL : out std_logic; --when dsp slave is output
+ WRH : out std_logic; --when dsp slave is output
+ BM_IN : in std_logic; --Bus Master. For debug
+ DSP_RESET : out std_logic;
+ BRST : inout std_logic;
+ ACK : in std_logic;
+ --internal data and address bus
+ CLK : in std_logic;
+ RESET : in std_logic;
+ R_W_ENABLE : in std_logic;
+ TRIGGER : in std_logic;
+ INTERNAL_DATA_IN : in std_logic_vector(31 downto 0); --63 downto 0
+ INTERNAL_DATA_OUT : out std_logic_vector(31 downto 0); --63 downto 0
+ INTERNAL_ADDRESS : in std_logic_vector(31 downto 0);
+ VALID_DATA_SENT : out std_logic;
+ ACKNOWLEDGE : in std_logic;
+ DEBUGSTATE_MACHINE : out std_logic_vector(31 downto 0)
+ );
+ end component;
+ component dtu_interface
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ LVL1_TRIGGER_BUS : in std_logic;
+ LVL1_DATA_TRIGGER_BUS : in std_logic;
+ LVL1_DATA_BUS : in std_logic_vector(3 downto 0);
+ LVL1_ERROR_BUS : out std_logic;
+ LVL1_BUSY_BUS : out std_logic;
+ LVL1_TRIGGER : out std_logic;
+ LVL1_CODE : out std_logic_vector(3 downto 0);
+ LVL1_TAG : out std_logic_vector(7 downto 0);
+ LVL1_BUSY : in std_logic;
+ LVL2_TRIGGER_BUS : in std_logic;
+ LVL2_DATA_TRIGGER_BUS : in std_logic;
+ LVL2_DATA_BUS : in std_logic_vector(3 downto 0);
+ LVL2_ERROR_BUS : out std_logic;
+ LVL2_BUSY_BUS : out std_logic;
+ LVL2_TRIGGER : out std_logic;
+ LVL2_CODE : out std_logic_vector(3 downto 0);
+ LVL2_TAG : out std_logic_vector(7 downto 0);
+ LVL2_BUSY : in std_logic;
+ LVL2_TRB_ACK : in std_logic;
+ DTU_DEBUG_00 : out std_logic_vector( 31 downto 0));
+ end component;
+
+ component sdram_interface
+ port (
+--connection with sdram
+ CLK_SDRAM : out std_logic;
+ CKE : out std_logic;
+ CS : out std_logic;
+ RAS : out std_logic;
+ CAS : out std_logic;
+ WE : out std_logic;
+ DQM : out std_logic_vector(3 downto 0);
+ BA : out std_logic_vector (1 downto 0);
+ A : out std_logic_vector(12 downto 0);
+ DQ : inout std_logic_vector(31 downto 0);
+--internal signals
+ CLK : in std_logic;
+ RESET : in std_logic;
+ TRIGGER : in std_logic;
+ INTERNAL_DATA_IN : in std_logic_vector(31 downto 0);
+ INTERNAL_DATA_OUT : out std_logic_vector(31 downto 0);
+ INTERNAL_ADDRESS : in std_logic_vector(31 downto 0);
+ INTERNAL_MODE : in std_logic_vector(15 downto 0);
+ VALID_DATA_SENT : out std_logic;
+ DEBUGSTATE_MACHINE : out std_logic_vector(31 downto 0)
+ );
+ end component;
+ component ctu
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ LVL1_TRIGG : in std_logic_vector(7 downto 0);
+ LVL1_START : out std_logic;
+ LVL1_TAG : out std_logic_vector(7 downto 0);
+ LVL1_CODE : out std_logic_vector(3 downto 0);
+ LVL1_BUSY : in std_logic;
+ LVL2_TRIGG : in std_logic_vector(1 downto 0);
+ LVL2_START : out std_logic_vector(1 downto 0);
+ LVL2_TAG : out std_logic_vector(7 downto 0);
+ LVL2_BUSY : in std_logic;
+ LVL2_DOWNSCALING : in std_logic_vector(7 downto 0);
+ CTU_CONTROL : in std_logic_vector(31 downto 0);
+ LVL1_CTU_STATUS : out std_logic_vector(31 downto 0);
+ LVL2_CTU_STATUS : out std_logic_vector(31 downto 0));
+ end component;
+ component simpleupcounter_32bit
+ port (
+ QOUT : out std_logic_vector(31 downto 0);
+ UP : in std_logic;
+ CLK : in std_logic;
+ CLR : in std_logic);
+ end component;
+
+ -----------------------------------------------------------------------------
+ -- SPI --component !!!
+ -----------------------------------------------------------------------------
+
+
+ -----------------------------------------------------------------------------
+ -- EDGE TO PULSE
+ -----------------------------------------------------------------------------
+ component edge_to_pulse
+ port (
+ clock : in std_logic;
+ en_clk : in std_logic;
+ signal_in : in std_logic;
+ pulse : out std_logic);
+ end component;
+-------------------------------------------------------------------------------
+-- SIGNALS
+-------------------------------------------------------------------------------
+ signal CLK : std_logic;
+ signal a_trigg : std_logic;
+ signal b_trigg : std_logic;
+ signal c_trigg : std_logic;
+ signal d_trigg : std_logic;
+ signal reference_signal : std_logic;
+ signal tdc_clk : std_logic;
+ signal to_many_tdc_data_i : std_logic;
+ signal tdc_readout_completed_i : std_logic;
+ signal how_many_add_data_i : std_logic_vector(7 downto 0);
+ signal tdc_data_out_i : std_logic_vector(31 downto 0);
+ signal tdc_data_valid_i : std_logic;
+ signal lvl1_busy_i : std_logic;
+ signal not_lvl1_busy : std_logic;
+ signal lvl2_busy_i : std_logic;
+ signal lvl1_tdc_trigg_i : std_logic;
+ signal lvl2_tdc_trigg_i : std_logic_vector(1 downto 0);
+ signal lvl1_trigger_code_i : std_logic_vector(3 downto 0);
+ signal lvl1_trigger_tag_i : std_logic_vector(7 downto 0);
+ signal tdc_code_i : std_logic_vector(3 downto 0);
+ signal tdc_tag_i : std_logic_vector(7 downto 0);
+ signal lvl2_trigger_i : std_logic_vector(1 downto 0);
+ signal lvl1_trigger_i : std_logic;
+ signal trigg_without_hades_i : std_logic;
+ signal trigg_without_hades_t : std_logic;
+ signal tdc_control_register_i : std_logic_vector(7 downto 0);
+ signal delay_trigger_i : std_logic_vector(7 downto 0);
+ signal trb_ack_lvl1_i : std_logic;
+ signal trb_ack_lvl2_i : std_logic;
+ signal etrax_data_bus_i : std_logic_vector(35 downto 0);
+ signal etrax_bus_busy_i : std_logic; --should go to busy logic !?
+ signal tdc_lvl1_busy_i : std_logic;
+ signal tdc_lvl2_busy_i : std_logic;
+ signal etrax_is_ready_to_read_i : std_logic;
+ signal tlk_rx_clk_io : std_logic;
+ signal tlk_clk_io : std_logic;
+ signal tlk_rx_clk_r : std_logic;
+ signal tlk_clk_r : std_logic;
+ signal tlk_register_00_i : std_logic_vector(31 downto 0);
+ signal tlk_register_01_i : std_logic_vector(31 downto 0);
+ signal link_status_i : std_logic_vector(3 downto 0);
+ signal fpga_register_18_i : std_logic_vector(31 downto 0);
+ signal fpga_register_10_i : std_logic_vector(31 downto 0);
+ signal dsp_register_00_i : std_logic_vector(31 downto 0);
+ signal external_address_i : std_logic_vector(31 downto 0);
+ signal external_data_in_i : std_logic_vector(31 downto 0);
+ signal external_data_out_i : std_logic_vector(31 downto 0);
+ signal external_ack_i : std_logic;
+ signal external_valid_i : std_logic;
+ signal external_mode_i : std_logic_vector(15 downto 0);
+ signal dsp_strobe_i : std_logic;
+ signal dsp_external_valid_i : std_logic;
+ signal reset_i : std_logic;
+ signal fpga_register_01_i : std_logic_vector(31 downto 0);
+ signal fpga_register_02_i : std_logic_vector(31 downto 0);
+ signal fpga_register_03_i : std_logic_vector(31 downto 0);
+ signal fpga_register_04_i : std_logic_vector(31 downto 0);
+ signal fpga_register_05_i : std_logic_vector(31 downto 0);
+ signal fpga_register_06_i : std_logic_vector(31 downto 0);
+ signal fpga_register_07_i : std_logic_vector(31 downto 0);
+ signal fpga_register_08_i : std_logic_vector(31 downto 0);
+ signal fpga_register_09_i : std_logic_vector(31 downto 0);
+ signal fpga_register_0A_i : std_logic_vector(31 downto 0);
+ signal fpga_register_0b_i : std_logic_vector(31 downto 0);
+ signal fpga_register_0c_i : std_logic_vector(31 downto 0);
+ signal fpga_register_0d_i : std_logic_vector(31 downto 0);
+
+ signal fpga_register_19_i : std_logic_vector(31 downto 0);
+ signal fpga_register_20_i : std_logic_vector(31 downto 0);
+
+ signal fpga_register_22_i : std_logic_vector(31 downto 0);
+ signal fpga_register_23_i : std_logic_vector(31 downto 0);
+ signal fpga_register_24_i : std_logic_vector(31 downto 0):=x"00000000";
+ signal fpga_register_25_i : std_logic_vector(31 downto 0);
+ signal dsp_hbr_i : std_logic;
+ signal external_reset_i : std_logic;
+ signal dspdat_out_i : std_logic_vector(31 downto 0);
+ signal dspdat_in_i : std_logic_vector(31 downto 0);
+ signal dsp_data_out_i : std_logic_vector(31 downto 0);
+ signal dspaddr_i : std_logic_vector(31 downto 0);
+ signal internal_clock : std_logic;
+ signal internal_clock_not : std_logic;
+ signal external_debug_i : std_logic;
+ signal DSP_WRL_i: std_logic;
+ signal DSP_RD_i: std_logic;
+ signal tdc_register_00_i : std_logic_vector(31 downto 0);
+ signal tdc_register_01_i : std_logic_vector(31 downto 0);
+ signal tdc_register_02_i : std_logic_vector(31 downto 0);
+ signal tdc_register_03_i : std_logic_vector(31 downto 0);
+ signal tdc_register_04_i : std_logic_vector(31 downto 0);
+ signal tdc_control_register_e : std_logic_vector(31 downto 0);
+ signal simulation_00 : std_logic_vector(3 downto 0);
+ signal bunch_reset_i : std_logic;
+ signal event_reset_i : std_logic;
+ signal trigger_to_tdc_i : std_logic;
+ signal trb_status_register_00 : std_logic_vector(31 downto 0);
+ signal token_out_i : std_logic;
+ signal test_en_tdc_clk : std_logic;
+ signal test_en : std_logic;
+ signal busy_register_00_i : std_logic_vector(31 downto 0);
+ signal busy_register_01_i : std_logic_vector(31 downto 0);
+ signal trigger_register_00_i : std_logic_vector(31 downto 0);
+ signal lvl2_trigger_code_i : std_logic_vector(3 downto 0):=x"0";
+ signal trb_ack_lvl1_long_i : std_logic;
+ signal trb_ack_lvl2_long_i : std_logic;
+ signal lvl1_counter_ack : std_logic_vector(7 downto 0);
+ signal lvl2_counter_ack : std_logic_vector(7 downto 0);
+ signal lvl2_trigger_delay : std_logic;
+ signal lvl2_delay_trigg_count : std_logic_vector(7 downto 0);
+ signal lvl2_trigger_code_synch : std_logic;
+ signal write_lvl1_busy_i : std_logic;
+ signal dsp_data_reg_in_i : std_logic_vector(31 downto 0);
+ signal dsp_data_reg_out_i : std_logic_vector(31 downto 0);
+ signal lvds_add_on_data : std_logic_vector(31 downto 0);
+ signal dsp_bm_reg : std_logic;
+ signal dsp_link_data_in_0 : std_logic_vector(3 downto 0);
+ signal dsp_link_data_out_0 : std_logic_vector(3 downto 0);
+ signal dsp_link_clk_in_0 : std_logic;
+ signal dsp_link_clk_out_0 : std_logic;
+ signal dsp_link_data_in_1 : std_logic_vector(3 downto 0);
+ signal dsp_link_data_out_1 : std_logic_vector(3 downto 0);
+ signal dsp_link_clk_in_1 : std_logic;
+ signal dsp_link_clk_out_1 : std_logic;
+ signal trigger_without_hades_mdc_add : std_logic;
+ signal not_reset_pulse : std_logic;
+ signal switch_for_start : std_logic;
+ signal not_external_reset : std_logic;
+ signal sdram_register_00_i : std_logic_vector(31 downto 0);
+ signal sdram_external_valid_i : std_logic;
+ signal sdram_data_out_i : std_logic_vector(31 downto 0);
+ signal vsd_cs_i : std_logic;
+ signal sdram_data_i : std_logic_vector(31 downto 0);
+ signal sdram_address_i : std_logic_vector(31 downto 0);
+ signal etrax_register_00_i : std_logic_vector(31 downto 0);
+ signal lvl1_triggers : std_logic_vector(7 downto 0);
+ signal scaler_counter_0 : std_logic_vector(31 downto 0);
+ signal scaler_counter_1 : std_logic_vector(31 downto 0);
+ signal scaler_counter_2 : std_logic_vector(31 downto 0);
+ signal scaler_counter_3 : std_logic_vector(31 downto 0);
+ signal scaler_counter_4 : std_logic_vector(31 downto 0);
+ signal scaler_counter_5 : std_logic_vector(31 downto 0);
+ signal scaler_counter_6 : std_logic_vector(31 downto 0);
+ signal scaler_counter_7 : std_logic_vector(31 downto 0);
+ signal scaler_pulse : std_logic_vector(7 downto 0);
+ signal lvl1_ctu_status_i : std_logic_vector(31 downto 0);
+ signal lvl2_ctu_status_i : std_logic_vector(31 downto 0);
+ signal lvl2_busy_fast : std_logic;
+ signal lvl2_busy_out : std_logic;
+ signal token_counter : std_logic_vector(7 downto 0);
+ signal self_token :std_logic;
+ signal self_data_valid : std_logic;
+ signal external_reset : std_logic;
+ signal generator_trigger : std_logic;
+ signal check_pulse : std_logic;
+ signal check_counter : std_logic_vector(16 downto 0);
+--api
+ signal med_dataready_out_i : STD_LOGIC;
+ signal med_data_out_i : STD_LOGIC_VECTOR (63 downto 0);
+ signal med_dataready_in_i : STD_LOGIC;
+ signal med_dataready_in_synch : STD_LOGIC;
+ signal med_data_in_i : STD_LOGIC_VECTOR (63 downto 0);
+ signal med_read_out_i : STD_LOGIC;
+ signal med_read_in_i : STD_LOGIC;
+ signal med_error_in_i : STD_LOGIC_VECTOR (2 downto 0);
+ signal apl_data_in_i : STD_LOGIC_VECTOR (47 downto 0);
+ signal apl_write_in_i : STD_LOGIC;
+ signal apl_fifo_full_out_i : STD_LOGIC;
+ signal apl_short_transfer_in_i : STD_LOGIC;
+ signal apl_dtype_in_i : STD_LOGIC_VECTOR (3 downto 0);
+ signal apl_error_pattern_in_i : STD_LOGIC_VECTOR (31 downto 0);
+ signal apl_send_in_i : STD_LOGIC;
+ signal apl_target_address_in_i : STD_LOGIC_VECTOR (15 downto 0);
+ signal apl_data_out_i : STD_LOGIC_VECTOR (47 downto 0);
+ signal apl_typ_out_i : STD_LOGIC_VECTOR (2 downto 0);
+ signal apl_dataready_out_i : STD_LOGIC;
+ signal apl_read_in_i : STD_LOGIC;
+ signal apl_run_out_i : STD_LOGIC;
+ signal apl_my_address_in_i : STD_LOGIC_VECTOR (15 downto 0);
+ signal apl_seqnr_out_i : STD_LOGIC_VECTOR (7 downto 0);
+ signal stat_gen_i : STD_LOGIC_VECTOR (31 downto 0);
+ signal stat_locked_i : STD_LOGIC_VECTOR (31 downto 0);
+ signal stat_init_buffer_i : STD_LOGIC_VECTOR (31 downto 0);
+ signal stat_reply_buffer_i : STD_LOGIC_VECTOR (31 downto 0);
+ signal stat_api_control_signals_i : std_logic_vector (31 downto 0);
+ signal ctrl_gen_i : STD_LOGIC_VECTOR (31 downto 0);
+ signal ctrl_locked_i : STD_LOGIC_VECTOR (31 downto 0);
+ signal stat_ctrl_init_buffer_i : STD_LOGIC_VECTOR (31 downto 0);
+ signal stat_ctrl_reply_buffer_i : STD_LOGIC_VECTOR (31 downto 0);
+ signal mplex_ctrl_i : STD_LOGIC_VECTOR (31 downto 0);
+ signal api_stat_fifo_to_int_i : std_logic_vector (31 downto 0);
+ signal api_stat_fifo_to_apl_i : std_logic_vector (31 downto 0);
+ signal not_link_status_i : std_logic;
+--spi
+ --a
+ signal spi_sck_a : std_logic;
+ signal spi_cs_a : std_logic;
+ signal spi_sdi_a : std_logic;
+ signal spi_sdo_a : std_logic;
+ --b
+ signal spi_sck_b : std_logic;
+ signal spi_cs_b : std_logic;
+ signal spi_sdi_b : std_logic;
+ signal spi_sdo_b : std_logic;
+ --c
+ signal spi_sck_c : std_logic;
+ signal spi_cs_c : std_logic;
+ signal spi_sdi_c : std_logic;
+ signal spi_sdo_c : std_logic;
+ --d
+ signal spi_sck_d : std_logic;
+ signal spi_cs_d : std_logic;
+ signal spi_sdi_d : std_logic;
+ signal spi_sdo_d : std_logic;
+--test signals
+ signal test_a1 : std_logic;
+ signal test_a2 : std_logic;
+ signal test_b1 : std_logic;
+ signal test_b2 : std_logic;
+ signal test_c1 : std_logic;
+ signal test_c2 : std_logic;
+ signal test_d1 : std_logic;
+ signal test_d2 : std_logic;
+ signal test_counter_1 : std_logic_vector(31 downto 0);
+ signal test_counter_2 : std_logic_vector(31 downto 0);
+ signal trigger_for_test_signal : std_logic;
+ signal not_hades_trigger : std_logic;
+--internal
+ signal lvds_or : std_logic;
+ signal med_data_in_i_saved : std_logic_vector(63 downto 0);
+ signal end_of_transfer : std_logic;
+ signal saved_txd : std_logic_vector(15 downto 0);
+ signal fs_pc17 : std_logic;
+ signal med_packet_num_in_i : std_logic_vector(1 downto 0);
+begin
+ ------------------------------------------------------------------------------
+ -- LVDS signals
+ ------------------------------------------------------------------------------
+ -- CLK
+ IBUFGDS_CLK : IBUFGDS
+ generic map (
+ IOSTANDARD => "LVDS_25_DCI")
+ port map (
+ O => CLK,--CLK,
+ I => VIRT_CLK,
+ IB => VIRT_CLKB -- Diff_n clock buffer input (connect to top-level port)
+ );
+ -- TDC
+ IBUFGDS_TDC_CLK : IBUFGDS
+ generic map (
+ IOSTANDARD => "LVDS_25_DCI") --_DCI
+ port map (
+ O => tdc_clk,
+ I => REF_TDC_CLK,
+ IB => REF_TDC_CLKB-- Diff_n clock buffer input (connect to top-level port)
+ );
+ IBUFDS_TRIGG_A : OBUFDS
+ port map (
+ O => A_TRIGGER,
+ OB => A_TRIGGERB,
+ I => a_trigg
+ );
+ IBUFDS_TRIGG_B : OBUFDS
+ port map (
+ O => B_TRIGGER,
+ OB => B_TRIGGERB,
+ I => b_trigg
+ );
+ IBUFDS_TRIGG_C : OBUFDS
+ port map (
+ O => C_TRIGGER,
+ OB => C_TRIGGERB,
+ I => c_trigg
+ );
+ IBUFDS_TRIGG_D : OBUFDS
+ port map (
+ O => D_TRIGGER,
+ OB => D_TRIGGERB,
+ I => d_trigg
+ );
+ IBUFDS_REFERENCE : IBUFGDS
+ generic map (
+ IOSTANDARD => "LVDS_25_DCI")
+ port map (
+ O => reference_signal,
+ I => VIR_TRIG,
+ IB => VIR_TRIGB
+ );
+
+ OBUFDS_BUNCH_RESET_A : OBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25"
+ )
+ port map (
+ O => A_TDC_BU_RESET,
+ OB =>A_TDC_BU_RESETB ,
+ I => bunch_reset_i
+ );
+ OBUFDS_EVENT_RESET_A : OBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25"
+ )
+ port map (
+ O => A_TDC_EV_RESET,
+ OB =>A_TDC_EV_RESETB ,
+ I => event_reset_i
+ );
+ OBUFDS_BUNCH_RESET_B : OBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25"
+ )
+ port map (
+ O => B_TDC_BU_RESET,
+ OB =>B_TDC_BU_RESETB ,
+ I => bunch_reset_i
+ );
+ OBUFDS_EVENT_RESET_B : OBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25"
+ )
+ port map (
+ O => B_TDC_EV_RESET,
+ OB =>B_TDC_EV_RESETB ,
+ I => event_reset_i
+ );
+ OBUFDS_BUNCH_RESET_C : OBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25"
+ )
+ port map (
+ O => C_TDC_BU_RESET,
+ OB =>C_TDC_BU_RESETB ,
+ I => bunch_reset_i
+ );
+ OBUFDS_EVENT_RESET_C : OBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25"
+ )
+ port map (
+ O => C_TDC_EV_RESET,
+ OB =>C_TDC_EV_RESETB ,
+ I => event_reset_i
+ );
+
+ OBUFDS_BUNCH_RESET_D : OBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25"
+ )
+ port map (
+ O => D_TDC_BU_RESET,
+ OB =>D_TDC_BU_RESETB ,
+ I => bunch_reset_i
+ );
+ OBUFDS_EVENT_RESET_D : OBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25"
+ )
+ port map (
+ O => D_TDC_EV_RESET,
+ OB =>D_TDC_EV_RESETB ,
+ I => event_reset_i
+ );
+-- SPI
+ --A
+ OBUFDS_SCK_A : OBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25"
+ )
+ port map (
+ O => A_SCK,
+ OB => A_SCKB,
+ I => spi_sck_a
+ );
+ OBUFDS_SDO_A : OBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25"
+ )
+ port map (
+ O => A_SDO,
+ OB => A_SDOB,
+ I => spi_sdo_a
+ );
+ OBUFDS_CS_A : OBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25"
+ )
+ port map (
+ O => A_CS,
+ OB => A_CSB,
+ I => spi_cs_a
+ );
+ IBUFDS_SDI_A : IBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25_DCI"
+ )
+ port map (
+ I => A_SDI,
+ IB => A_SDIB,
+ O => spi_sdi_a
+ );
+ spi_sck_a <= fpga_register_07_i(0);
+ spi_sdo_a <= fpga_register_07_i(1);
+ spi_cs_a <= fpga_register_07_i(2);
+ fpga_register_08_i(0) <= spi_sdi_a;
+ --B
+ OBUFDS_SCK_B : OBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25"
+ )
+ port map (
+ O => B_SCK,
+ OB => B_SCKB,
+ I => spi_sck_b
+ );
+ OBUFDS_SDO_B : OBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25"
+ )
+ port map (
+ O => B_SDO,
+ OB => B_SDOB,
+ I => spi_sdo_b
+ );
+ OBUFDS_CS_B : OBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25"
+ )
+ port map (
+ O => B_CS,
+ OB => B_CSB,
+ I => spi_cs_b
+ );
+ IBUFDS_SDI_B : IBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25_DCI"
+ )
+ port map (
+ I => B_SDI,
+ IB => B_SDIB,
+ O => spi_sdi_b
+ );
+ spi_sck_b <= fpga_register_07_i(3);
+ spi_sdo_b <= fpga_register_07_i(4);
+ spi_cs_b <= fpga_register_07_i(5);
+ fpga_register_08_i(1) <= spi_sdi_b;
+ --C
+ OBUFDS_SCK_C : OBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25"
+ )
+ port map (
+ O => C_SCK,
+ OB => C_SCKB,
+ I => spi_sck_c
+ );
+ OBUFDS_SDO_C : OBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25"
+ )
+ port map (
+ O => C_SDO,
+ OB => C_SDOB,
+ I => spi_sdo_c
+ );
+ OBUFDS_CS_C : OBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25"
+ )
+ port map (
+ O => C_CS,
+ OB => C_CSB,
+ I => spi_cs_c
+ );
+ IBUFDS_SDI_C : IBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25_DCI"
+ )
+ port map (
+ I => C_SDI,
+ IB => C_SDIB,
+ O => spi_sdi_c
+ );
+ spi_sck_c <= fpga_register_07_i(6);
+ spi_sdo_c <= fpga_register_07_i(7);
+ spi_cs_c <= fpga_register_07_i(8);
+ fpga_register_08_i(2) <= spi_sdi_c;
+ --D
+ OBUFDS_SCK_D : OBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25"
+ )
+ port map (
+ O => D_SCK,
+ OB => D_SCKB,
+ I => spi_sck_d
+ );
+ OBUFDS_SDO_D : OBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25"
+ )
+ port map (
+ O => D_SDO,
+ OB => D_SDOB,
+ I => spi_sdo_d
+ );
+ OBUFDS_CS_D : OBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25"
+ )
+ port map (
+ O => D_CS,
+ OB => D_CSB,
+ I => spi_cs_d
+ );
+ IBUFDS_SDI_D : IBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25_DCI"
+ )
+ port map (
+ I => D_SDI,
+ IB => D_SDIB,
+ O => spi_sdi_d
+ );
+ spi_sck_d <= fpga_register_07_i(9);
+ spi_sdo_d <= fpga_register_07_i(10);
+ spi_cs_d <= fpga_register_07_i(11);
+ fpga_register_08_i(3) <= spi_sdi_d;
+-- Test signals
+ OBUFDS_TEST_A1 : OBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25"
+ )
+ port map (
+ O => A_TEST1,
+ OB => A_TEST1B,
+ I => test_a1
+ );
+ OBUFDS_TEST_A2 : OBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25"
+ )
+ port map (
+ O => A_TEST2,
+ OB => A_TEST2B,
+ I => test_a2
+ );
+ OBUFDS_TEST_B1 : OBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25"
+ )
+ port map (
+ O => B_TEST1,
+ OB => B_TEST1B,
+ I => test_b1
+ );
+ OBUFDS_TEST_B2 : OBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25"
+ )
+ port map (
+ O => B_TEST2,
+ OB => B_TEST2B,
+ I => test_b2
+ );
+ OBUFDS_TEST_C1 : OBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25"
+ )
+ port map (
+ O => C_TEST1,
+ OB => C_TEST1B,
+ I => test_c1
+ );
+ OBUFDS_TEST_C2 : OBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25"
+ )
+ port map (
+ O => C_TEST2,
+ OB => C_TEST2B,
+ I => test_c2
+ );
+ OBUFDS_TEST_D1 : OBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25"
+ )
+ port map (
+ O => D_TEST1,
+ OB => D_TEST1B,
+ I => test_d1
+ );
+ OBUFDS_TEST_D2 : OBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25"
+ )
+ port map (
+ O => D_TEST2,
+ OB => D_TEST2B,
+ I => test_d2 --i should be able to switch on off 1
+ --or 2
+ );
+ COUNTER_FOR_TEST_1: process (CLK, external_reset_i,test_counter_1)
+ begin
+ if rising_edge(CLK) then
+ if external_reset_i = '1' or test_counter_1 > x"186A0"then --1kHz
+ test_counter_1 <= (others => '0');
+ else
+ test_counter_1 <= test_counter_1 + 1;
+ end if;
+ end if;
+ end process COUNTER_FOR_TEST_1;
+ COUNTER_FOR_TEST_2: process (CLK, external_reset_i,test_counter_2)
+ begin
+ if rising_edge(CLK) then
+ if external_reset_i = '1' or test_counter_2 > x"186A0" then --1kHz
+ test_counter_2 <= (others => '0');
+ else
+ test_counter_2 <= test_counter_2 + 1;
+ end if;
+ end if;
+ end process COUNTER_FOR_TEST_2;
+ --lenght of signal depend on this condition: test_counter_1 < x". ."
+ --frequency in process:. . or test_counter_x > x". ."
+ test_a1 <= '1' when (test_counter_1 < x"64" and fpga_register_06_i(1)='1') else '0';
+ test_b1 <= '1' when (test_counter_1 < x"64" and fpga_register_06_i(1)='1') else '0';
+ test_c1 <= '1' when (test_counter_1 < x"64" and fpga_register_06_i(1)='1') else '0';
+ test_d1 <= '1' when (test_counter_1 < x"64" and fpga_register_06_i(1)='1') else '0';
+ test_a2 <= '1' when (test_counter_2 < x"64" and fpga_register_06_i(2)='1') else '0';
+ test_b2 <= '1' when (test_counter_2 < x"64" and fpga_register_06_i(2)='1') else '0';
+ test_c2 <= '1' when (test_counter_2 < x"64" and fpga_register_06_i(2)='1') else '0';
+ test_d2 <= '1' when (test_counter_2 < x"64" and fpga_register_06_i(2)='1') else '0';
+ trigger_for_test_signal <= '1' when ((test_counter_1 > x"C8" and test_counter_1 < x"CC") and (fpga_register_06_i(1)='1' or fpga_register_06_i(2) ='1' )) else '0';
+-- ADD_LVDS
+ IBUFDS_LVDS_0 : IBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25_DCI"
+ )
+ port map (
+ I => ADO_LV(0),
+ IB => ADO_LV(1),
+ O => lvds_add_on_data(0)
+ );
+ IBUFDS_LVDS_1 : IBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25_DCI"
+ )
+ port map (
+ I => ADO_LV(2),
+ IB => ADO_LV(3),
+ O => lvds_add_on_data(1)
+ );
+ IBUFDS_LVDS_2 : IBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25_DCI"
+ )
+ port map (
+ I => ADO_LV(4),
+ IB => ADO_LV(5),
+ O => lvds_add_on_data(2)
+ );
+ IBUFDS_LVDS_3 : IBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25_DCI"
+ )
+ port map (
+ I => ADO_LV(6),
+ IB => ADO_LV(7),
+ O => lvds_add_on_data(3)
+ );
+ IBUFDS_LVDS_4 : IBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25_DCI"
+ )
+ port map (
+ I => ADO_LV(8),
+ IB => ADO_LV(9),
+ O => lvds_add_on_data(4)
+ );
+ IBUFDS_LVDS_5 : IBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25_DCI"
+ )
+ port map (
+ I => ADO_LV(10),
+ IB => ADO_LV(11),
+ O => lvds_add_on_data(5)
+ );
+ IBUFDS_LVDS_6 : IBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25_DCI"
+ )
+ port map (
+ I => ADO_LV(12),
+ IB => ADO_LV(13),
+ O => lvds_add_on_data(6)
+ );
+ IBUFDS_LVDS_7 : IBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25_DCI"
+ )
+ port map (
+ I => ADO_LV(14),
+ IB => ADO_LV(15),
+ O => lvds_add_on_data(7)
+ );
+ IBUFDS_LVDS_8 : IBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25_DCI"
+ )
+ port map (
+ I => ADO_LV(16),
+ IB => ADO_LV(17),
+ O => lvds_add_on_data(8)
+ );
+ IBUFDS_LVDS_9 : IBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25_DCI"
+ )
+ port map (
+ I => ADO_LV(18),
+ IB => ADO_LV(19),
+ O => lvds_add_on_data(9)
+ );
+ IBUFDS_LVDS_10 : IBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25_DCI"
+ )
+ port map (
+ I => ADO_LV(20),
+ IB => ADO_LV(21),
+ O => lvds_add_on_data(10)
+ );
+ IBUFDS_LVDS_11 : IBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25_DCI"
+ )
+ port map (
+ I => ADO_LV(22),
+ IB => ADO_LV(23),
+ O => lvds_add_on_data(11)
+ );
+ IBUFDS_LVDS_12 : IBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25_DCI"
+ )
+ port map (
+ I => ADO_LV(24),
+ IB => ADO_LV(25),
+ O => lvds_add_on_data(12)
+ );
+ IBUFDS_LVDS_13 : IBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25_DCI"
+ )
+ port map (
+ I => ADO_LV(26),
+ IB => ADO_LV(27),
+ O => lvds_add_on_data(13)
+ );
+ IBUFDS_LVDS_14 : IBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25_DCI"
+ )
+ port map (
+ I => ADO_LV(28),
+ IB => ADO_LV(29),
+ O => lvds_add_on_data(14)
+ );
+ IBUFDS_LVDS_15 : IBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25_DCI"
+ )
+ port map (
+ I => ADO_LV(30),
+ IB => ADO_LV(31),
+ O => lvds_add_on_data(15)
+ );
+ IBUFDS_LVDS_16 : IBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25_DCI"
+ )
+ port map (
+ I => ADO_LV(32),
+ IB => ADO_LV(33),
+ O => lvds_add_on_data(16)
+ );
+ IBUFDS_LVDS_17 : IBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25_DCI"
+ )
+ port map (
+ I => ADO_LV(34),
+ IB => ADO_LV(35),
+ O => lvds_add_on_data(17)
+ );
+ IBUFDS_LVDS_18 : IBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25_DCI"
+ )
+ port map (
+ I => ADO_LV(36),
+ IB => ADO_LV(37),
+ O => lvds_add_on_data(18)
+ );
+ IBUFDS_LVDS_19 : IBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25_DCI"
+ )
+ port map (
+ I => ADO_LV(38),
+ IB => ADO_LV(39),
+ O => lvds_add_on_data(19)
+ );
+ IBUFDS_LVDS_20 : IBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25_DCI"
+ )
+ port map (
+ I => ADO_LV(40),
+ IB => ADO_LV(41),
+ O => lvds_add_on_data(20)
+ );
+ IBUFDS_LVDS_21 : IBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25_DCI"
+ )
+ port map (
+ I => ADO_LV(42),
+ IB => ADO_LV(43),
+ O => lvds_add_on_data(21)
+ );
+ IBUFDS_LVDS_22 : IBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25_DCI"
+ )
+ port map (
+ I => ADO_LV(44),
+ IB => ADO_LV(45),
+ O => lvds_add_on_data(22)
+ );
+ IBUFDS_LVDS_23 : IBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25_DCI"
+ )
+ port map (
+ I => ADO_LV(46),
+ IB => ADO_LV(47),
+ O => lvds_add_on_data(23)
+ );
+ IBUFDS_LVDS_24 : IBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25_DCI"
+ )
+ port map (
+ I => ADO_LV(48),
+ IB => ADO_LV(49),
+ O => lvds_add_on_data(24)
+ );
+ IBUFDS_LVDS_25_DCI : IBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25_DCI"
+ )
+ port map (
+ I => ADO_LV(50),
+ IB => ADO_LV(51),
+ O => lvds_add_on_data(25)
+ );
+-- IBUFDS_LVDS_26 : IBUFDS
+-- generic map (
+-- IOSTANDARD => "LVDS_25_DCI"
+-- )
+-- port map (
+-- I => ADO_LV(52),
+-- IB => ADO_LV(53),
+-- O => lvds_add_on_data(26)
+-- );
+-- IBUFDS_LVDS_27 : IBUFDS
+-- generic map (
+-- IOSTANDARD => "LVDS_25_DCI"
+-- )
+-- port map (
+-- I => ADO_LV(54),
+-- IB => ADO_LV(55),
+-- O => lvds_add_on_data(27)
+-- );
+-- IBUFDS_LVDS_28 : IBUFDS
+-- generic map (
+-- IOSTANDARD => "LVDS_25_DCI"
+-- )
+-- port map (
+-- I => ADO_LV(56) ,
+-- IB => ADO_LV(57),
+-- O => lvds_add_on_data(28)
+-- );
+-- IBUFDS_LVDS_29 : IBUFDS
+-- generic map (
+-- IOSTANDARD => "LVDS_25_DCI"
+-- )
+-- port map (
+-- I => ADO_LV(58),
+-- IB => ADO_LV(59),
+-- O => lvds_add_on_data(29)
+-- );
+-- IBUFDS_LVDS_30 : IBUFDS
+-- generic map (
+-- IOSTANDARD => "LVDS_25_DCI"
+-- )
+-- port map (
+-- I => ADO_LV(60),
+-- IB => ADO_LV(61),
+-- O => lvds_add_on_data(30)
+-- );
+ save_tlk_data: process (tlk_rx_clk_r, external_reset_i)
+ begin
+ if rising_edge(tlk_rx_clk_r) then
+ if external_reset_i = '1' then
+ saved_txd <= (others => '0');
+ elsif TLK_RX_DV ='1'and TLK_RX_ER = '0' then
+ saved_txd <= TLK_RXD;
+ else
+ saved_txd <=saved_txd;
+ end if;
+ end if;
+ end process save_tlk_data;
+
+-- ADO_TTL(0) <= apl_dataready_out_i;
+-- ADO_TTL(4 downto 1) <= apl_seqnr_out_i(3 downto 0);
+-- ADO_TTL(8) <= med_dataready_out_i;
+-- ADO_TTL(6 downto 5) <= apl_data_out_i(1 downto 0);
+-- ADO_TTL(7) <= end_of_transfer;
+-- ADO_TTL(9) <= med_dataready_in_i;
+-- ADO_TTL(10) <= apl_send_in_i;
+-- ADO_TTL(12 downto 11) <= stat_reply_buffer_i(15 downto 14);
+-- ADO_TTL(15 downto 13) <= api_stat_fifo_to_int_i(31 downto 29);--stat_reply_buffer_i(15 downto 14);
+
+-- MED_DATA_READY_SYNCH: process (CLK, external_reset_i)
+-- begin
+-- if rising_edge( CLK) then
+-- if external_reset_i = '1' then
+-- med_dataready_in_i <= '0';
+-- else
+-- med_dataready_in_i <= med_dataready_in_synch;
+-- end if;
+-- end if;
+-- end process MED_DATA_READY_SYNCH;
+
+--
+-- STARTUP_VIRTEX4_inst : STARTUP_VIRTEX4
+-- port map (
+-- EOS => open, -- End of Startup 1-bit output
+-- CLK => CLK, -- Clock input for start-up sequence
+-- GSR => FS_PB(17), -- Global Set/Reset input (GSR cannot be used for the port name)
+-- GTS => open, -- Global 3-state input (GTS cannot be used for the port name)
+-- USRCCLKO => open, -- USRCCLKO 1-bit input
+-- USRCCLKTS => open, -- USRCCLKTS 1-bit input
+-- USRDONEO => open, -- USRDONEO 1-bit input
+-- USRDONETS => open -- USRDONETS 1-bit input
+-- );
+--Shark links
+-- DSP_L0DATIP : out std_logic_vector (3 downto 0);
+-- DSP_L0DATIN : out std_logic_vector (3 downto 0);
+-- DSP_L0DATOP : in std_logic_vector (3 downto 0);
+-- DSP_L0DATON : in std_logic_vector (3 downto 0);
+-- DSP_L0CLKINP : out std_logic;
+-- DSP_L0CLKINN : out std_logic;
+-- DSP_L0CLKOUTP : in std_logic;
+-- DSP_L0CLKOUTN : in std_logic;
+-- DSP_DATA_LINK0_OUT_0 : IBUFDS
+-- generic map (
+-- IOSTANDARD => "LVDS_25"
+-- )
+-- port map (
+-- I => ,
+-- IB =>,
+-- O =>
+-- );
+-- DSP_DATA_LINK0_OUT_1 : IBUFDS
+-- generic map (
+-- IOSTANDARD => "LVDS_25"
+-- )
+-- port map (
+-- I => ,
+-- IB =>,
+-- O =>
+-- );
+-- DSP_DATA_LINK0_OUT_2 : IBUFDS
+-- generic map (
+-- IOSTANDARD => "LVDS_25"
+-- )
+-- port map (
+-- I => ,
+-- IB =>,
+-- O =>
+-- );
+-- DSP_DATA_LINK0_OUT_3 : IBUFDS
+-- generic map (
+-- IOSTANDARD => "LVDS_25"
+-- )
+-- port map (
+-- I => ,
+-- IB =>,
+-- O =>
+-- );
+-- DSP_DATA_LINK0_IN_0 : OBUFDS
+-- generic map (
+-- IOSTANDARD => "LVDS_25"
+-- )
+-- port map (
+-- I => ,
+-- IB =>,
+-- O => dsp_link_data_in_0(0)
+-- );
+-- DSP_DATA_LINK0_IN_1 : OBUFDS
+-- generic map (
+-- IOSTANDARD => "LVDS_25"
+-- )
+-- port map (
+-- I => ,
+-- IB =>,
+-- O => dsp_link_data_in_0(1)
+-- ;
+-- DSP_DATA_LINK0_IN_2 : OBUFDS
+-- generic map (
+-- IOSTANDARD => "LVDS_25"
+-- )
+-- port map (
+-- I => ,
+-- IB =>,
+-- O =>dsp_link_data_in_0(2)
+-- );
+-- DSP_DATA_LINK0_IN_3 : OBUFDS
+-- generic map (
+-- IOSTANDARD => "LVDS_25"
+-- )
+-- port map (
+-- I => ,
+-- IB =>,
+-- O => dsp_link_data_in_0(3)
+-- );
+-------------------------------------------------------------------------------
+-- api
+-------------------------------------------------------------------------------
+-- API_INST: trb_net16_endpoint_0_trg_1_api
+-- generic map (
+-- API_TYPE => 0,
+-- INIT_DEPTH => 1,
+-- REPLY_DEPTH => 1,
+-- FIFO_TO_INT_DEPTH => 1,
+-- FIFO_TO_APL_DEPTH => 1,
+-- SBUF_VERSION => 0,
+-- MUX_WIDTH => 1,
+-- MUX_SECURE_MODE => 0,
+-- DAT_CHANNEL => 0,
+-- DATA_WIDTH => 16,
+-- NUM_WIDTH => 2)
+-- port map (
+-- CLK => CLK,
+-- RESET => external_reset_i,
+-- CLK_EN => '1',
+-- MED_DATAREADY_OUT => TLK_TX_EN,--media_data_valid_in_i,
+-- MED_DATA_OUT => TLK_TXD,--media_data_in_i,
+-- MED_PACKET_NUM_OUT => open,--MED_PACKET_NUM_OUT_i,
+-- MED_READ_IN => '1',
+-- MED_DATAREADY_IN => TLK_RX_DV,--media_data_valid_out_i,
+-- MED_DATA_IN => TLK_RXD,--media_data_out_i,
+-- MED_PACKET_NUM_IN => med_packet_num_in_i,
+-- MED_READ_OUT => open, --MED_READ_OUT_i, enable reading
+-- --data from trbv2_tlk_api_fifo
+-- MED_ERROR_IN => "000",--MED_ERROR_IN_i, - if there is
+-- --link lok
+-- APL_DATA_IN => x"0000",
+-- APL_PACKET_NUM_IN => "00",
+-- APL_WRITE_IN => '0',
+-- APL_FIFO_FULL_OUT => open,
+-- APL_SHORT_TRANSFER_IN => '1',
+-- APL_DTYPE_IN => (others => '0'),
+-- APL_ERROR_PATTERN_IN => x"12345678",
+-- APL_SEND_IN => apl_send_in_i,
+-- APL_TARGET_ADDRESS_IN => x"FFFF",
+-- APL_DATA_OUT => open,
+-- APL_PACKET_NUM_OUT => open,
+-- APL_TYP_OUT => open,--lvl1_trigger_code_i,
+-- APL_DATAREADY_OUT => lvl1_trigger_i,
+-- APL_READ_IN => '1',
+-- APL_RUN_OUT => open,
+-- APL_MY_ADDRESS_IN => x"0001",
+-- APL_SEQNR_OUT => apl_seqnr_out_i,
+-- STAT_GEN => open,--STAT_GEN_i,
+-- STAT_LOCKED => open,--STAT_LOCKED_i,
+-- STAT_INIT_BUFFER => open,--STAT_INIT_BUFFER_i,
+-- STAT_REPLY_BUFFER => open,--STAT_REPLY_BUFFER_i,
+-- STAT_api_control_signals => open,--STAT_api_control_signals_i,
+-- STAT_MPLEX => open,--STAT_MPLEX_i,
+-- CTRL_GEN => x"00000000",--CTRL_GEN_i,
+-- CTRL_LOCKED => x"00000000",
+-- STAT_CTRL_INIT_BUFFER => x"00000000",--STAT_CTRL_INIT_BUFFER_i,
+-- STAT_CTRL_REPLY_BUFFER => x"00000000",--STAT_CTRL_REPLY_BUFFER_i,
+-- MPLEX_CTRL => x"00000000",--MPLEX_CTRL_i,
+-- API_STAT_FIFO_TO_INT => open,--API_STAT_FIFO_TO_INT_i,
+-- API_STAT_FIFO_TO_APL => open--API_STAT_FIFO_TO_APL_i
+-- );
+-- COUNTER_FOR_API: process (CLK, external_reset_i)
+-- begin
+-- if rising_edge(CLK) then
+-- if external_reset_i = '1' then
+-- med_packet_num_in_i <= (others => '0');
+-- elsif TLK_RX_DV = '1' then
+-- med_packet_num_in_i <= med_packet_num_in_i + 1;
+-- end if;
+-- end if;
+-- end process COUNTER_FOR_API;
+
+ -----------------------------------------------------------------------------
+ -- Component Instance
+ -----------------------------------------------------------------------------
+ reset_i <= not RESET_VIRT;
+ TOKEN_OUT <= token_out_i;
+ TDC_INT: tdc_interface
+ port map (
+ CLK => CLK,
+ TDC_CLK => tdc_clk,--CLK,--tdc_clk,--mdc addon or CLK
+ RESET => external_reset_i,--not RESET_VIRT,
+ -- TDC_RESET => TDC_RESET,
+ TDC_DATA_IN => TDC_OUT,--x"0" & "00" & lvds_add_on_data(25 downto 0),--TDC_OUT,--mdc addon or
+ START_TDC_READOUT => lvl1_trigger_i,--lvl1_tdc_trigg_i,
+ A_TDC_ERROR => A_TDC_ERROR,
+ B_TDC_ERROR => B_TDC_ERROR,
+ C_TDC_ERROR => C_TDC_ERROR,
+ D_TDC_ERROR => D_TDC_ERROR,
+ A_TDC_POWERUP => open, --A_TDC_POWERUP,
+ B_TDC_POWERUP => open, --B_TDC_POWERUP,
+ C_TDC_POWERUP => open, --C_TDC_POWERUP,
+ D_TDC_POWERUP => open, --D_TDC_POWERUP,
+ A_TDC_READY => A_DATA_READY,--ADO_TTL(3),--A_DATA_READY,mdc addon or
+ B_TDC_READY => B_DATA_READY,--ADO_TTL(3),--B_DATA_READY,mdc addon or
+ C_TDC_READY => C_DATA_READY,--ADO_TTL(3),--C_DATA_READY,mdc addon or
+ D_TDC_READY => D_DATA_READY,--ADO_TTL(3),--D_DATA_READY,mdc addon or
+ SEND_TDC_TOKEN => token_out_i,
+ RECEIVED_TDC_TOKEN => TOKEN_IN,--ADO_TTL(2),--TOKEN_IN,--mdc addon or
+ --normal
+ GET_TDC_DATA => GET_DATA,
+ TO_MANY_TDC_DATA => to_many_tdc_data_i,
+ TDC_READOUT_COMPLETED => tdc_readout_completed_i,
+ LVL1_TAG => lvl1_trigger_tag_i,--TLK_RXD(7 downto 0),--apl_seqnr_out_i,--tdc_tag_i,
+ LVL1_CODE => lvl1_trigger_code_i,--TLK_RXD(11 downto 8),--apl_data_out_i(3 downto 0),--tdc_code_i,
+ HOW_MANY_ADD_DATA => fpga_register_06_i(23 downto 16),--how_many_add_data_i,
+ COUNTER_a => test_counter_1,--scaler_counter_0,--x"12311231",
+ COUNTER_b => scaler_counter_0,--x"12321232",
+ COUNTER_c => scaler_counter_1,--x"12331233",
+ COUNTER_d => scaler_counter_2,--x"12341234",
+ COUNTER_e => scaler_counter_3,--x"12351235",
+ COUNTER_f => scaler_counter_4,--x"12361236",
+ COUNTER_g => scaler_counter_5,--x"12371237",
+ COUNTER_h => scaler_counter_6,--x"12381238",
+ LVL2_TRIGGER => lvl2_trigger_i,--lvl2_tdc_trigg_i, here
+ TDC_DATA_OUT => tdc_data_out_i,
+ TDC_DATA_VALID => tdc_data_valid_i,
+ ETRAX_IS_READY_TO_READ => etrax_is_ready_to_read_i,
+ LVL1_BUSY => lvl1_busy_i,
+ LVL2_BUSY => lvl2_busy_i,
+ TDC_REGISTER_00 => tdc_register_00_i,
+ TDC_REGISTER_01 => tdc_register_01_i,
+ TDC_REGISTER_02 => tdc_register_02_i,
+ TDC_REGISTER_03 => tdc_register_03_i,
+ TDC_REGISTER_04 => tdc_register_04_i,
+ BUNCH_RESET => bunch_reset_i,
+ EVENT_RESET => event_reset_i,
+ READ_ADRESS_END_UP => trb_ack_lvl2_i,
+ DELAY_TRIGGER => x"00",--fpga_register_06_i(31 downto 24),
+ TDC_START => trigger_to_tdc_i,
+ TRIGGER_WITHOUT_HADES => fpga_register_06_i(7),
+ TRIGGER_WITH_GEN_EN => fpga_register_06_i(8),
+ TRIGGER_WITH_GEN => not_hades_trigger--trigger_for_test_signal or generator_trigger
+ );
+ ADO_TTL(42 downto 35) <= tdc_register_01_i(26 downto 19);
+ not_hades_trigger <= trigger_for_test_signal or generator_trigger;
+ end_of_transfer <= not tdc_data_valid_i;
+ LVL2_BUSY_END_PULSER : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => end_of_transfer,
+ pulse => apl_send_in_i);
+ not_lvl1_busy <= not lvl1_busy_i;
+ LVL1_BUSY_PULSER : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => lvl1_busy_i,
+ pulse => apl_read_in_i);
+ LVL1_OPT_PULSER : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => TLK_RX_DV,
+ pulse => lvl1_tdc_trigg_i);
+ LVL2_OPT_END_PULSER : edge_to_pulse
+ port map (
+ clock => tlk_rx_clk_r,
+ en_clk => '1',
+ signal_in => end_of_transfer,
+ pulse => TLK_TX_EN);
+ TLK_TXD <= x"abcd";
+ TLK_TX_ER <= '0';
+-- SFP_TX_DIS <= '0';
+ TLK_LOOPEN <= '0';
+ TLK_LCKREFN <= '1';
+ TLK_ENABLE <= '1';
+ TLK_PRBSEN <= '0';
+
+-- ADO_TTL(0) <= TLK_RX_DV;
+-- ADO_TTL(1) <= lvl1_tdc_trigg_i;
+-- ADO_TTL(2) <= fs_pc17;--FS_PC(17);--'0';
+-- ADO_TTL(3) <= tdc_data_valid_i;--'0';
+-- ADO_TTL(4) <= etrax_is_ready_to_read_i;--D_DATA_READY;
+-- ADO_TTL(5) <= lvl2_busy_i;
+-- ADO_TTL(6) <= end_of_transfer;
+-- ADO_TTL(7) <= TLK_RX_ER;
+
+-- lvl2_tdc_trigg_i <= '0' & apl_send_in_i; --should be real in normal operation
+-- 0 reset 1 token 2-5 code 6 token_back 7 data valid
+ --------------------------------------------------------------------------
+ -- MDCaddon mdc addon or . . .
+-- --------------------------------------------------------------------------
+-- lvds_add_on_data(31) <= '1';
+-- SEND_CODE: process (CLK, external_reset_i)
+-- begin
+-- if rising_edge(CLK) then -- rising clock edge
+-- if external_reset_i = '1' then
+-- switch_for_start <= '0';
+-- elsif ADO_TTL(2) ='1' then
+-- switch_for_start <= '1';
+-- end if;
+-- end if;
+-- end process SEND_CODE;
+-- ADO_TTL(7 downto 4) <= x"d" when switch_for_start ='0' else x"1";
+-- not_external_reset <= not external_reset_i;
+
+-- SEND_TDC_TRIGGER : edge_to_pulse
+-- port map (
+-- clock => clk,
+-- en_clk => '1',
+-- signal_in => not_external_reset,
+-- pulse => not_reset_pulse);
+
+-- ADO_TTL(1) <= token_out_i or not_reset_pulse;
+-- ADO_TTL(2) <= 'Z';
+-- ADO_TTL(3) <= 'Z';
+
+ -- ADO_TTL(0) <= external_reset_i;
+ --------------------------------------------------------------------------
+ -- self mdc
+ --------------------------------------------------------------------------
+-- COUNTER_FOR_SELF_TOKEN_BACK: process (CLK,token_out_i)
+-- begin -- process COUNTER_FOR_SELF_TOKEN_BACK
+-- if rising_edge(CLK) then
+-- if token_out_i = '1' then
+-- token_counter <= x"00";
+-- elsif token_counter < x"0a" + 1 then
+-- token_counter <= token_counter + 1;
+-- else
+-- token_counter <= token_counter;
+-- end if;
+-- end if;
+-- end process COUNTER_FOR_SELF_TOKEN_BACK;
+-- self_token <= '1' when token_counter = x"0a" else '0';
+-- self_data_valid <= '1' when token_counter < x"0a" else '0';
+
+-- SYNCH_EXT_TRIGG: process (CLK, external_reset_i)
+-- begin -- process SYNCH_EXT_TRIGG
+-- if rising_edge(CLK) then -- rising clock edge
+-- if external_reset_i = '1' then -- asynchronous reset (active low)
+-- trigg_without_hades_i <= '0';
+-- else
+-- -- trigg_without_hades_i <= CLK and tdc_control_register_e(0) and (not lvl1_busy_i) and (not tdc_lvl2_busy_i) and (not busy_register_00_i(0)) and(not etrax_bus_busy_i);--
+-- -- trigg_without_hades_i <= TDC_CLK and fpga_register_06_i(7) and (not lvl1_busy_i) and (not tdc_lvl2_busy_i) and (not busy_register_00_i(0)) and(not etrax_bus_busy_i);--
+-- --mdc addon
+-- -- trigg_without_hades_i <= TDC_CLK and tdc_control_register_e(0) and (not lvl1_busy_i) and (not tdc_lvl2_busy_i) and (not busy_register_00_i(0)) and(not etrax_bus_busy_i);
+-- trigg_without_hades_i <= generator_trigger and not ;
+-- end if;
+-- end if;
+-- end process SYNCH_EXT_TRIGG;
+ a_trigg <= trigger_to_tdc_i;
+ b_trigg <= trigger_to_tdc_i;
+ c_trigg <= trigger_to_tdc_i;
+ d_trigg <= trigger_to_tdc_i;
+
+ tdc_control_register_i <= "0000000" & fpga_register_06_i(7);--tdc_control_register_e(7 downto 0);
+
+ MULTIPLEX_DATA_TO_ETRAX: process(CLK,external_reset_i,external_mode_i)
+ begin
+ if rising_edge(CLK) then
+ if external_reset_i = '1' then
+ external_data_in_i <= (others => '0');
+ elsif external_mode_i(7 downto 0) = x"01" then
+ external_data_in_i <= dsp_data_out_i;
+ elsif external_mode_i(7 downto 0) = x"02" then
+ external_data_in_i <= sdram_data_out_i;
+-- elsif external_mode_i(7 downto 0) = x"03" then
+-- external_data_in_i <= x"add000" & ADO_TTL(42 downto 35);
+ else
+ external_data_in_i <= x"0000"&external_mode_i;
+ end if;
+ end if;
+ end process MULTIPLEX_DATA_TO_ETRAX;
+-- ADO_TTL(42 downto 35) <= (others => 'Z');
+-- ADO_TTL(34 downto 19) <= external_address_i(15 downto 0);
+-- ADO_TTL(18 downto 11) <= external_data_out_i(7 downto 0);
+-- ADO_TTL(10) <= external_mode_i(15);
+-- ADO_TTL(9) <= '1' when external_mode_i(7 downto 0) = x"03" and external_ack_i = '1' else '0';
+-- dsp_strobe_i <= '1' when external_mode_i(7 downto 0) = x"01" and external_ack_i = '1' else '0';
+-- -- external_valid_i <= dsp_external_valid_i or sdram_external_valid_i or ADO_TTL(12);
+-- external_valid_i <= ADO_TTL(8);
+-- ADO_TTL(8) <= 'Z';
+
+
+ ETRAX_INTERFACE_LOGIC : etrax_interface
+ port map (
+ CLK => CLK,
+ RESET => reset_i,
+ DATA_BUS => tdc_data_out_i,
+ ETRAX_DATA_BUS_B => FS_PB,
+ ETRAX_DATA_BUS_C => FS_PC,
+ DATA_VALID => tdc_data_valid_i,
+ ETRAX_BUS_BUSY => etrax_bus_busy_i,
+ ETRAX_IS_READY_TO_READ => etrax_is_ready_to_read_i,
+ TDC_TCK => VIRT_TCK,
+ TDC_TDI => VIRT_TDI,
+ TDC_TMS => VIRT_TMS,
+ TDC_TRST => open, --VIRT_TRST,
+ TDC_TDO => VIRT_TDO,
+ TDC_RESET => open, --TDC_RESET,
+ EXTERNAL_ADDRESS => external_address_i,
+ EXTERNAL_DATA_OUT => external_data_out_i,
+ EXTERNAL_DATA_IN => external_data_in_i,
+ EXTERNAL_ACK => external_ack_i,
+ EXTERNAL_VALID => external_valid_i,
+ EXTERNAL_MODE => external_mode_i,
+ FPGA_REGISTER_00 => x"00000000",
+ FPGA_REGISTER_01 => fpga_register_01_i,--ppp tlk_register_00_i,
+ FPGA_REGISTER_02 => fpga_register_02_i,--ppp tlk_register_01_i,
+ FPGA_REGISTER_03 => fpga_register_03_i,--ppp tdc_register_00_i,--x"abbaab02",
+ FPGA_REGISTER_04 => fpga_register_04_i, --ppp busy_register_00_i,
+ FPGA_REGISTER_05 => tdc_register_04_i,--lvds_add_on_data(31 downto 0),--tdc_register_04_i,--fpga_register_05_i, --ppp trigger_register_00_i,
+ FPGA_REGISTER_06 => fpga_register_06_i,--open, -- ppp x"abbaab05",
+ FPGA_REGISTER_07 => fpga_register_07_i,
+ FPGA_REGISTER_08 => fpga_register_08_i,
+ FPGA_REGISTER_09 => fpga_register_09_i,
+ FPGA_REGISTER_0A => fpga_register_0A_i,
+ FPGA_REGISTER_0B => fpga_register_0b_i,
+ FPGA_REGISTER_0C => fpga_register_0c_i,
+ FPGA_REGISTER_0D => fpga_register_0d_i,
+ EXTERNAL_RESET => external_reset,
+ LVL2_VALID => '0'--lvl2_trigger_code_i(3)
+ );
+-- lvl2_valid_i <= lvl2_trigger_code_i(3);
+ fpga_register_01_i <= tdc_register_00_i;
+ fpga_register_02_i <= tdc_register_01_i;--tdc_data_valid_i & write_lvl1_busy_i & lvl2_busy_fast & lvl2_busy_i & tdc_lvl2_busy_i & tdc_lvl1_busy_i & lvl1_busy_i & trigger_register_00_i(11 downto 0) & sdram_register_00_i(5 downto 0) & dsp_register_00_i(2 downto 0);
+ fpga_register_03_i <= tdc_register_02_i;--busy_register_01_i;
+ fpga_register_04_i <= tdc_register_03_i;
+ fpga_register_05_i <= tdc_register_04_i;
+ fpga_register_09_i <= x"000" & "00" & TLK_RX_ER & TLK_RX_DV & TLK_RXD;--tlk_register_00_i;
+ fpga_register_0a_i <= tlk_register_01_i;
+ fpga_register_0b_i <= saved_txd & x"00" & apl_seqnr_out_i;
+ fpga_register_0c_i <= med_data_in_i_saved(63 downto 32);--stat_reply_buffer_i;
+ fpga_register_0d_i <= med_data_in_i_saved(31 downto 0);--stat_init_buffer_i;
+-- lvds_or <= lvds_add_on_data(0) or lvds_add_on_data(1) or
+-- lvds_add_on_data(2) or lvds_add_on_data(3) or
+-- lvds_add_on_data(4) or lvds_add_on_data(5) or
+-- lvds_add_on_data(6) or lvds_add_on_data(7) or
+-- lvds_add_on_data(8) or lvds_add_on_data(9) or
+-- lvds_add_on_data(10) or lvds_add_on_data(11) or
+-- lvds_add_on_data(12) or lvds_add_on_data(13) or
+-- lvds_add_on_data(14) or lvds_add_on_data(15) or
+-- lvds_add_on_data(16) or lvds_add_on_data(17) or
+-- lvds_add_on_data(18) or lvds_add_on_data(19) or
+-- lvds_add_on_data(20) or lvds_add_on_data(21) or
+-- lvds_add_on_data(22) or lvds_add_on_data(23) or
+-- lvds_add_on_data(24) or lvds_add_on_data(25) ;
+
+
+ SYNCH_RESET: process (CLK)
+ begin -- process SYNCH_RESET
+ if rising_edge(CLK) then -- rising clock edge
+ external_reset_i <= external_reset;
+ else
+ external_reset_i <= external_reset_i;
+ end if;
+ end process SYNCH_RESET;
+ fpga_register_10_i <= x"0000"& external_mode_i;
+ TLK_RX_CLK_BUFR: BUFR
+ port map(
+ CE => '1',
+ CLR => '0',
+ I => TLK_RX_CLK,
+ O => tlk_rx_clk_r
+ );
+ TLK_CLK_BUFR: BUFR
+ port map(
+ CE => '1',
+ CLR => '0',
+ I => TLK_CLK,
+ O => tlk_clk_r
+ );
+-- tlk_interface_logic: tlk_interface
+-- port map (
+-- VIRT_CLK => CLK,
+-- ENABLE => TLK_ENABLE,
+-- LCKREFN => TLK_LCKREFN,
+-- LOOPEN => TLK_LOOPEN,
+-- PRBSEN => TLK_PRBSEN,
+-- RX_CLK => tlk_rx_clk_r,
+-- RX_DV => TLK_RX_DV,
+-- RX_ER => TLK_RX_ER,
+-- TLK_CLK => tlk_clk_r,
+-- TLK_RXD => TLK_RXD,
+-- TLK_TXD => TLK_TXD,
+-- TX_EN => open,--TLK_TX_EN,
+-- TX_ER => open,--TLK_TX_ER,
+-- RESET_VIRT => external_reset_i,
+-- TLK_REGISTER_00 => tlk_register_00_i,
+-- TLK_REGISTER_01 => tlk_register_01_i,
+-- SFP_LOS => SFP_LOS,
+-- TX_DIS => open--SFP_TX_DIS
+-- );
+-- -- TLK_LCKREFN <= fpga_register_06_i(15);
+-- -- TLK_TXD <= x"abcd";
+-- TLK_TX_EN <= '0';
+-- TLK_TX_ER <= '0';
+-- fpga_register_08_i(4) <= SFP_LOS;
+ SFP_TX_DIS <= fpga_register_06_i(15);
+
+
+ DSP_DATA_REGISTER: process (CLK, external_reset_i)
+ begin -- process DSP_DATA_REGISTER
+ if CLK'event and CLK = '1' then
+ if external_reset_i = '1' then
+ dsp_data_reg_in_i <= x"00000000";
+ dsp_data_reg_out_i <= x"00000000";
+ dsp_bm_reg <= '0';
+ sdram_data_i <= x"00000000";
+-- fs_pc17 <= '0';
+ else
+ dsp_bm_reg <= DSP_BM;
+ dsp_data_reg_in_i <= DSPDAT;
+ dsp_data_reg_out_i <= dspdat_out_i;
+ sdram_data_i <= VSD_D ;
+-- fs_pc17 <= FS_PC(17);
+ end if;
+ end if;
+ end process DSP_DATA_REGISTER;
+
+-- DSP_HBR <= '1';
+
+-- DSP_RESET <= fpga_register_06_i(4);
+-- DSP_HBR <= dsp_hbr_i;
+-- DSPDAT <= dspdat_out_i;
+-- dspdat_in_i <= DSPDAT;
+-- DSP_WRL <= DSP_WRL_i;
+-- DSP_RD <= DSP_RD_i;
+-- DSPADDR <= dspaddr_i;
+-- DSP_BOFF <= fpga_register_06_i(5);
+
+-- DSP_IRQ <= x"1";
+-- DSP_BMS <= '1' when fpga_register_06_i(3) = '0' else 'Z';
+-- DSP_BM <= '0' when fpga_register_06_i(3) = '0' else 'Z';
+-- DSP_INTERFACE_LOGIC: dsp_interface
+-- port map (
+-- HBR_OUT => dsp_hbr_i,
+-- HBG_IN => DSP_HBG,
+-- RD_OUT => DSP_RD_i,
+-- DSP_DATA_OUT => dspdat_out_i,--DSPDAT to DSP,
+-- DSP_DATA_IN => dspdat_in_i,--DSPDAT to FPGA,
+-- ADDRESS_DSP => dspaddr_i,--DSPADDR,
+-- WRL => DSP_WRL_i,
+-- WRH => DSP_WRH,
+-- BM_IN => DSP_BM,
+-- DSP_RESET => open,
+-- BRST => DSP_BRST,
+-- ACK => DSP_ACK,
+-- CLK => CLK,
+-- RESET => external_reset_i,
+-- R_W_ENABLE => external_mode_i(15),
+-- TRIGGER => dsp_strobe_i,
+-- INTERNAL_DATA_IN => external_data_out_i,
+-- INTERNAL_DATA_OUT => dsp_data_out_i,--external_data_in_i,
+-- INTERNAL_ADDRESS => external_address_i,
+-- VALID_DATA_SENT => dsp_external_valid_i,
+-- ACKNOWLEDGE => dsp_strobe_i,
+-- DEBUGSTATE_MACHINE => dsp_register_00_i);
+-- SDRAM_INTERFACE_LOGIC: sdram_interface
+-- port map (
+-- CLK_SDRAM => VSD_CLOCK,
+-- CKE => VSD_CKE,
+-- CS => vsd_cs_i,
+-- RAS => VSD_RAS,
+-- CAS => VSD_CAS,
+-- WE => VSD_WE,
+-- DQM => VSD_DQML,
+-- BA => VSD_BA,
+-- A => VSD_A,
+-- DQ => VSD_D,
+-- CLK => CLK,
+-- RESET => external_reset_i,
+-- TRIGGER => external_ack_i,
+-- INTERNAL_DATA_IN => external_data_out_i,
+-- INTERNAL_DATA_OUT => sdram_data_out_i,
+-- INTERNAL_ADDRESS => external_address_i,
+-- INTERNAL_MODE => external_mode_i,
+-- VALID_DATA_SENT => sdram_external_valid_i,
+-- DEBUGSTATE_MACHINE => sdram_register_00_i);
+ VSD_CSEH <= vsd_cs_i;
+ VSD_CSEL <= vsd_cs_i;
+-- ADO_TTL(18) <= '1';
+-- ADO_TTL(15 downto 0) <= (others => 'Z');
+-- DTU_INT: dtu_interface
+-- port map (
+-- CLK => CLK,
+-- RESET => external_reset_i,
+-- LVL1_TRIGGER_BUS => ADO_TTL(4),
+-- LVL1_DATA_TRIGGER_BUS => ADO_TTL(9),
+-- LVL1_DATA_BUS => ADO_TTL(8 downto 5),
+-- LVL1_ERROR_BUS => ADO_TTL(1),
+-- LVL1_BUSY_BUS => ADO_TTL(0),
+-- LVL1_TRIGGER => lvl1_trigger_i,
+-- LVL1_CODE => lvl1_trigger_code_i,
+-- LVL1_TAG => lvl1_trigger_tag_i,
+-- LVL1_BUSY => lvl1_busy_i,
+-- LVL2_TRIGGER_BUS => ADO_TTL(10),
+-- LVL2_DATA_TRIGGER_BUS => ADO_TTL(15),
+-- LVL2_DATA_BUS => ADO_TTL(14 downto 11),
+-- LVL2_ERROR_BUS => open,--ADO_TTL(3),
+-- LVL2_BUSY_BUS => open,--ADO_TTL(2), --here
+-- LVL2_TRIGGER => lvl2_trigger_i(0),
+-- LVL2_CODE => lvl2_trigger_code_i,
+-- LVL2_TAG => open,
+-- LVL2_BUSY => '0',--lvl2_busy_i, --1:1 downscaling
+-- LVL2_TRB_ACK => trb_ack_lvl2_i,
+-- DTU_DEBUG_00 => open);
+ ADO_TTL(15 downto 4) <= (others => 'Z');
+ ADO_TTL(2) <= '0';
+ ADO_TTL(3) <= '0';
+-- lvl2_trigger_code_i(3) <= '0';--mdc lvl2_trigger_i(1);
+-- ADO_TTL(15 downto 0) <= (others => 'Z');
+-- CTU_INT: ctu
+-- port map (
+-- CLK => CLK,
+-- RESET => external_reset_i,
+-- LVL1_TRIGG => ADO_TTL(7 downto 0),
+-- LVL1_START => lvl1_trigger_i,
+-- LVL1_TAG => lvl1_trigger_tag_i,
+-- LVL1_CODE => lvl1_trigger_code_i,
+-- LVL1_BUSY => lvl1_busy_i,
+-- LVL2_TRIGG => "00", --MU
+-- LVL2_START => lvl2_trigger_i,
+-- LVL2_TAG => open,
+-- LVL2_BUSY => lvl2_busy_out,--tdc_lvl2_busy_i,--lvl2_busy_i,
+-- LVL2_DOWNSCALING => fpga_register_06_i(15 downto 8),
+-- CTU_CONTROL => x"0000" & fpga_register_06_i(23 downto16), --26
+-- LVL1_CTU_STATUS => lvl1_ctu_status_i,
+-- LVL2_CTU_STATUS => lvl2_ctu_status_i);
+ PULSE_TO_EDGE_0: edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => ADO_TTL(35),
+ pulse => scaler_pulse(0));
+ SCALER_0: simpleupcounter_32bit
+ port map (
+ QOUT => scaler_counter_0,
+ UP => scaler_pulse(0),
+ CLK => CLK,
+ CLR => external_reset_i);
+ PULSE_TO_EDGE_1: edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => ADO_TTL(36),
+ pulse => scaler_pulse(1));
+ SCALER_1: simpleupcounter_32bit
+ port map (
+ QOUT => scaler_counter_1,
+ UP => scaler_pulse(1),
+ CLK => CLK,
+ CLR => external_reset_i);
+ PULSE_TO_EDGE_2: edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => ADO_TTL(37),
+ pulse => scaler_pulse(2));
+ SCALER_2: simpleupcounter_32bit
+ port map (
+ QOUT => scaler_counter_2,
+ UP => scaler_pulse(2),
+ CLK => CLK,
+ CLR => external_reset_i);
+ PULSE_TO_EDGE_3: edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => ADO_TTL(38),
+ pulse => scaler_pulse(3));
+ SCALER_3: simpleupcounter_32bit
+ port map (
+ QOUT => scaler_counter_3,
+ UP => scaler_pulse(3),
+ CLK => CLK,
+ CLR => external_reset_i);
+ PULSE_TO_EDGE_4: edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => ADO_TTL(39),
+ pulse => scaler_pulse(4));
+ SCALER_4: simpleupcounter_32bit
+ port map (
+ QOUT => scaler_counter_4,
+ UP => scaler_pulse(4),
+ CLK => CLK,
+ CLR => external_reset_i);
+ PULSE_TO_EDGE_5: edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => ADO_TTL(40),
+ pulse => scaler_pulse(5));
+ SCALER_5: simpleupcounter_32bit
+ port map (
+ QOUT => scaler_counter_5,
+ UP => scaler_pulse(5),
+ CLK => CLK,
+ CLR => external_reset_i);
+ PULSE_TO_EDGE_6: edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => ADO_TTL(41),
+ pulse => scaler_pulse(6));
+ SCALER_6: simpleupcounter_32bit
+ port map (
+ QOUT => scaler_counter_6,
+ UP => scaler_pulse(6),
+ CLK => CLK,
+ CLR => external_reset_i);
+ PULSE_TO_EDGE_7: edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => ADO_TTL(42),
+ pulse => scaler_pulse(7));
+ SCALER_7: simpleupcounter_32bit
+ port map (
+ QOUT => scaler_counter_7,
+ UP => scaler_pulse(7),
+ CLK => CLK,
+ CLR => external_reset_i);
+ TRIGG_WITHOUT_HAD: edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => ADO_TTL(0),
+ pulse => generator_trigger);
+ MAKE_LONG_LVL2_ACK: process (CLK, external_reset_i)
+ begin -- process MAKE_LONG_ACK
+ if rising_edge(CLK) then -- rising clock edge
+ if external_reset_i = '1' then--or trb_ack_lvl2_i ='1' then -- asynchronous reset (active low)
+ lvl2_counter_ack <= x"1f";
+ elsif trb_ack_lvl2_i ='1' then
+ lvl2_counter_ack <= x"00";
+ elsif lvl2_counter_ack < x"1f" then
+ lvl2_counter_ack <= lvl2_counter_ack + 1;
+ else
+ lvl2_counter_ack <= lvl2_counter_ack;
+ end if;
+ end if;
+ end process MAKE_LONG_LVL2_ACK;
+ LVL2_CODE_SYNCH: process (CLK, external_reset_i)
+ begin
+ if rising_edge(CLK) then
+ if external_reset_i = '1' then
+
+ lvl2_trigger_code_synch <= '0' ;
+ else
+ lvl2_trigger_code_synch <= lvl2_trigger_code_i(3);
+ end if;
+ end if;
+ end process LVL2_CODE_SYNCH;
+ trb_ack_lvl2_long_i <= '1' when lvl2_counter_ack < x"1f" else '0';
+
+ ETRAX_IRQ <= '1';
+ DBAD <= lvl1_busy_i;
+ DGOOD <= lvl2_busy_i;
+ --DINT <= '1';
+ DINT <= etrax_bus_busy_i;
+ DWAIT <= fpga_register_06_i(6); --'0'enable clock for TDC
+
+
+
+
+
+ COUNTER_FOR_CLOCK_CHECK: process (CLK, external_reset_i)
+ begin
+ if rising_edge(CLK) then
+ if external_reset_i = '1' then
+ check_counter <= (others => '0');
+ else
+ check_counter <= check_counter + 1;
+ end if;
+ end if;
+ end process COUNTER_FOR_CLOCK_CHECK;
+ check_pulse <= '1' when check_counter > x"fffe" else '0';
+ TDC_RESET <= '0';--fpga_register_06_i(5);--'0';
+ VIRT_TRST <= not fpga_register_06_i(5);--'1';
+
+ A_TDC_POWERUP <= '1';
+ B_TDC_POWERUP <= '1';
+ C_TDC_POWERUP <= '1';
+ D_TDC_POWERUP <= '1';
+end trb_v2b_fpga;
--- /dev/null
+#-- Synplicity, Inc.
+#-- Version Synplify Pro 8.2.1
+
+
+#add_file options
+add_file -vhdl -lib work "~/trbnet/optical_link/simpleupcounter_8bit.vhd"
+add_file -vhdl -lib work "~/trbnet/optical_link/simpleupcounter_16bit.vhd"
+add_file -vhdl -lib work "~/trbnet/optical_link/simpleupcounter_32bit.vhd"
+add_file -vhdl -lib work "etrax_interface.vhd"
+add_file -vhdl -lib work "f_divider.vhd"
+add_file -vhdl -lib work "tdc_interface.vhd"
+add_file -vhdl -lib work "trb_v2b_fpga.vhd"
+add_file -vhdl -lib work "dtu_interface.vhd"
+add_file -vhdl -lib work "dsp_interface.vhd"
+add_file -vhdl -lib work "sdram_interface.vhd"
+add_file -vhdl -lib work "ctu.vhd"
+add_file -vhdl -lib work "bit_fifo.vhd"
+#add_file -vhdl -lib work "api/trbnet/xilinx/trb_net_fifo_arch.vhd"
+#add_file -vhdl -lib work "api/trbnet/trb_net_base_api.vhd"
+#add_file -vhdl -lib work "api/trbnet/trb_net_std.vhd"
+#add_file -vhdl -lib work "api/trbnet/trb_net_fifo.vhd"
+#add_file -vhdl -lib work "api/trbnet/trb_net_iobuf.vhd"
+#add_file -vhdl -lib work "api/trbnet/trb_net_active_api.vhd"
+#add_file -vhdl -lib work "api/trbnet/trb_net_passive_api.vhd"
+#add_file -vhdl -lib work "api/trbnet/xilinx/shift_lut_x16.vhd"
+#add_file -vhdl -lib work "api/trbnet/trb_net_dummy_fifo.vhd"
+#add_file -vhdl -lib work "api/trbnet/trb_net_ibuf.vhd"
+#add_file -vhdl -lib work "api/trbnet/trb_net_io_multiplexer.vhd"
+#add_file -vhdl -lib work "api/trbnet/trb_net_obuf.vhd"
+#add_file -vhdl -lib work "api/trbnet/trb_net_pattern_gen.vhd"
+#add_file -vhdl -lib work "api/trbnet/trb_net_priority_arbiter.vhd"
+#add_file -vhdl -lib work "api/trbnet/trb_net_priority_encoder.vhd"
+#add_file -vhdl -lib work "api/trbnet/trb_net_sbuf.vhd"
+#add_file -vhdl -lib work "api/trbnet/trb_net_term_ibuf.vhd"
+#add_file -vhdl -lib work "api/trbnet/trb_net_term.vhd"
+#add_file -vhdl -lib work "api/trbnet/trb_net_active_apimbuf.vhd"
+#add_file -vhdl -lib work "api/trbnet/trb_net_passive_apimbuf.vhd"
+#add_file -vhdl -lib work "trbnet/tlk_interface.vhd"
+#add_file -vhdl -lib work "trbnet/optical_link_test.vhd"
+
+#add_file -constraint "trb_v2a_fpga_syn.sdc"
+
+
+#implementation: "workdir"
+impl -add workdir
+
+#device options
+set_option -technology VIRTEX4
+set_option -part xc4vlx40
+set_option -package ff1148
+set_option -speed_grade -10
+
+#compilation/mapping options
+set_option -default_enum_encoding gray
+set_option -symbolic_fsm_compiler 0
+set_option -resource_sharing 1
+set_option -use_fsm_explorer 0
+set_option -top_module "trb_v2b_fpga"
+
+#map options
+set_option -frequency 120.000
+set_option -run_prop_extract 0
+set_option -fanout_limit 100
+set_option -disable_io_insertion 0
+set_option -pipe 1
+set_option -update_models_cp 0
+set_option -verification_mode 0
+set_option -fixgatedclocks 0
+set_option -no_sequential_opt 0
+set_option -retiming 0
+
+#simulation options
+set_option -write_verilog 0
+set_option -write_vhdl 0
+
+#VIF options
+set_option -write_vif 1
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_file "workdir/trb_v2b_fpga.edf"
+
+#
+#implementation attributes
+
+set_option -synthesis_onoff_pragma 0
+impl -active "workdir"
--- /dev/null
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE ieee.numeric_std.ALL;
+
+ENTITY trb_v2b_fpga_tb IS
+END trb_v2b_fpga_tb;
+
+ARCHITECTURE behavior OF trb_v2b_fpga_tb IS
+ component trb_v2b_fpga
+ port (
+ VIRT_CLK : in std_logic;
+ VIRT_CLKB : in std_logic;
+ RESET_VIRT : in std_logic;
+ DBAD : out std_logic;
+ DGOOD : out std_logic;
+ DINT : out std_logic;
+ DWAIT : out std_logic;
+ A_RESERVED : in std_logic;
+ A_TEMP : in std_logic;
+ B_RESERVED : in std_logic;
+ B_TEMP : in std_logic;
+ C_RESERVED : in std_logic;
+ C_TEMP : in std_logic;
+ D_RESERVED : in std_logic;
+ D_TEMP : in std_logic;
+ VIR_TRIG : in std_logic;
+ VIR_TRIGB : in std_logic;
+ A_TDC_ERROR : in std_logic;
+ B_TDC_ERROR : in std_logic;
+ C_TDC_ERROR : in std_logic;
+ D_TDC_ERROR : in std_logic;
+ A_TDC_POWERUP : out std_logic;
+ B_TDC_POWERUP : out std_logic;
+ C_TDC_POWERUP : out std_logic;
+ D_TDC_POWERUP : out std_logic;
+ TOKEN_IN : in std_logic;
+ TOKEN_OUT : out std_logic;
+ C_TOKEN_OUT_TTL : in std_logic;
+ GET_DATA : out std_logic;
+ A_DATA_READY : in std_logic;
+ B_DATA_READY : in std_logic;
+ C_DATA_READY : in std_logic;
+ D_DATA_READY : in std_logic;
+ REF_TDC_CLK : in std_logic;
+ REF_TDC_CLKB : in std_logic;
+ A_TDC_BU_RESET : out std_logic;
+ A_TDC_BU_RESETB : out std_logic;
+ A_TDC_EV_RESET : out std_logic;
+ A_TDC_EV_RESETB : out std_logic;
+ B_TDC_BU_RESET : out std_logic;
+ B_TDC_BU_RESETB : out std_logic;
+ B_TDC_EV_RESET : out std_logic;
+ B_TDC_EV_RESETB : out std_logic;
+ C_TDC_BU_RESET : out std_logic;
+ C_TDC_BU_RESETB : out std_logic;
+ C_TDC_EV_RESET : out std_logic;
+ C_TDC_EV_RESETB : out std_logic;
+ D_TDC_BU_RESET : out std_logic;
+ D_TDC_BU_RESETB : out std_logic;
+ D_TDC_EV_RESET : out std_logic;
+ D_TDC_EV_RESETB : out std_logic;
+ TDC_OUT : in std_logic_vector (31 downto 0);
+ TDC_RESET : out std_logic;
+ A_TRIGGER : out std_logic;
+ A_TRIGGERB : out std_logic;
+ B_TRIGGER : out std_logic;
+ B_TRIGGERB : out std_logic;
+ C_TRIGGER : out std_logic;
+ C_TRIGGERB : out std_logic;
+ D_TRIGGER : out std_logic;
+ D_TRIGGERB : out std_logic;
+ FS_PB : out std_logic_vector (17 downto 0);
+ FS_PC : inout std_logic_vector (17 downto 0);
+ ETRAX_IRQ : out std_logic;
+ A_SCK : out std_logic;
+ A_SCKB : out std_logic;
+ A_SDI : in std_logic;
+ A_SDIB : in std_logic;
+ A_SDO : out std_logic;
+ A_SDOB : out std_logic;
+ A_CSB : out std_logic;
+ A_CS : out std_logic;
+ B_SCK : out std_logic;
+ B_SCKB : out std_logic;
+ B_SDI : in std_logic;
+ B_SDIB : in std_logic;
+ B_SDO : out std_logic;
+ B_SDOB : out std_logic;
+ B_CSB : out std_logic;
+ B_CS : out std_logic;
+ C_SCK : out std_logic;
+ C_SCKB : out std_logic;
+ C_SDI : in std_logic;
+ C_SDIB : in std_logic;
+ C_SDO : out std_logic;
+ C_SDOB : out std_logic;
+ C_CSB : out std_logic;
+ C_CS : out std_logic;
+ D_SCK : out std_logic;
+ D_SCKB : out std_logic;
+ D_SDI : in std_logic;
+ D_SDIB : in std_logic;
+ D_SDO : out std_logic;
+ D_SDOB : out std_logic;
+ D_CSB : out std_logic;
+ D_CS : out std_logic;
+ A_TEST1 : out std_logic;
+ A_TEST1B : out std_logic;
+ A_TEST2 : out std_logic;
+ A_TEST2B : out std_logic;
+ B_TEST1 : out std_logic;
+ B_TEST1B : out std_logic;
+ B_TEST2 : out std_logic;
+ B_TEST2B : out std_logic;
+ C_TEST1 : out std_logic;
+ C_TEST1B : out std_logic;
+ C_TEST2 : out std_logic;
+ C_TEST2B : out std_logic;
+ D_TEST1 : out std_logic;
+ D_TEST1B : out std_logic;
+ D_TEST2 : out std_logic;
+ D_TEST2B : out std_logic;
+ DSPADDR : out std_logic_vector (31 downto 0);
+ DSPDAT : inout std_logic_vector (31 downto 0);
+ DSP_ACK : in std_logic;
+ DSP_BM : inout std_logic;
+ DSP_BMS : out std_logic;
+ DSP_BOFF : out std_logic;
+ DSP_BRST : inout std_logic;
+ DSP_HBG : in std_logic;
+ DSP_HBR : out std_logic;
+ DSP_IRQ : out std_logic_vector (3 downto 0);
+ DSP_RD : out std_logic;
+ DSP_RESET : out std_logic;
+ DSP_RESET_OUT : in std_logic;
+ DSP_WRH : out std_logic;
+ DSP_WRL : out std_logic;
+ VSD_A : out std_logic_vector (12 downto 0);
+ VSD_BA : out std_logic_vector (1 downto 0);
+ VSD_CAS : out std_logic;
+ VSD_CKE : out std_logic;
+ VSD_CLOCK : out std_logic;
+ VSD_CSEH : out std_logic;
+ VSD_CSEL : out std_logic;
+ VSD_D : inout std_logic_vector (31 downto 0);
+ VSD_DQML : out std_logic_vector (3 downto 0);
+ VSD_RAS : out std_logic;
+ VSD_WE : out std_logic;
+ TLK_CLK : in std_logic;
+ TLK_ENABLE : out std_logic;
+ TLK_LCKREFN : out std_logic;
+ TLK_LOOPEN : out std_logic;
+ TLK_PRBSEN : out std_logic;
+ TLK_RXD : in std_logic_vector (15 downto 0);
+ TLK_RX_CLK : in std_logic;
+ TLK_RX_DV : in std_logic;
+ TLK_RX_ER : in std_logic;
+ TLK_TXD : out std_logic_vector (15 downto 0);
+ TLK_TX_EN : out std_logic;
+ TLK_TX_ER : out std_logic;
+ SFP_LOS : in std_logic;
+ SFP_TX_DIS : out std_logic;
+ SFP_TX_FAULT : in std_logic;
+ ADO_LV : in std_logic_vector(51 downto 0);
+ ADO_TTL : inout std_logic_vector(46 downto 0);
+ VIRT_TCK : out std_logic;
+ VIRT_TDI : out std_logic;
+ VIRT_TDO : in std_logic;
+ VIRT_TMS : out std_logic;
+ VIRT_TRST : out std_logic);
+ end component;
+ signal VIRT_CLK : std_logic;
+ signal VIRT_CLKB : std_logic;
+ signal RESET_VIRT : std_logic;
+ signal DBAD : std_logic;
+ signal DGOOD : std_logic;
+ signal DINT : std_logic;
+ signal DWAIT : std_logic;
+ signal A_RESERVED : std_logic;
+ signal A_TEMP : std_logic;
+ signal B_RESERVED : std_logic;
+ signal B_TEMP : std_logic;
+ signal C_RESERVED : std_logic;
+ signal C_TEMP : std_logic;
+ signal D_RESERVED : std_logic;
+ signal D_TEMP : std_logic;
+ signal VIR_TRIG : std_logic;
+ signal VIR_TRIGB : std_logic;
+ signal A_TDC_ERROR : std_logic;
+ signal B_TDC_ERROR : std_logic;
+ signal C_TDC_ERROR : std_logic;
+ signal D_TDC_ERROR : std_logic;
+ signal A_TDC_POWERUP : std_logic;
+ signal B_TDC_POWERUP : std_logic;
+ signal C_TDC_POWERUP : std_logic;
+ signal D_TDC_POWERUP : std_logic;
+ signal TOKEN_IN : std_logic;
+ signal TOKEN_OUT : std_logic;
+ signal C_TOKEN_OUT_TTL : std_logic;
+ signal GET_DATA : std_logic;
+ signal A_DATA_READY : std_logic;
+ signal B_DATA_READY : std_logic;
+ signal C_DATA_READY : std_logic;
+ signal D_DATA_READY : std_logic;
+ signal REF_TDC_CLK : std_logic;
+ signal REF_TDC_CLKB : std_logic;
+ signal A_TDC_BU_RESET : std_logic;
+ signal A_TDC_BU_RESETB : std_logic;
+ signal A_TDC_EV_RESET : std_logic;
+ signal A_TDC_EV_RESETB : std_logic;
+ signal B_TDC_BU_RESET : std_logic;
+ signal B_TDC_BU_RESETB : std_logic;
+ signal B_TDC_EV_RESET : std_logic;
+ signal B_TDC_EV_RESETB : std_logic;
+ signal C_TDC_BU_RESET : std_logic;
+ signal C_TDC_BU_RESETB : std_logic;
+ signal C_TDC_EV_RESET : std_logic;
+ signal C_TDC_EV_RESETB : std_logic;
+ signal D_TDC_BU_RESET : std_logic;
+ signal D_TDC_BU_RESETB : std_logic;
+ signal D_TDC_EV_RESET : std_logic;
+ signal D_TDC_EV_RESETB : std_logic;
+ signal TDC_OUT : std_logic_vector (31 downto 0);
+ signal TDC_RESET : std_logic;
+ signal A_TRIGGER : std_logic;
+ signal A_TRIGGERB : std_logic;
+ signal B_TRIGGER : std_logic;
+ signal B_TRIGGERB : std_logic;
+ signal C_TRIGGER : std_logic;
+ signal C_TRIGGERB : std_logic;
+ signal D_TRIGGER : std_logic;
+ signal D_TRIGGERB : std_logic;
+ signal FS_PB : std_logic_vector (17 downto 0);
+ signal FS_PC : std_logic_vector (17 downto 0);
+ signal ETRAX_IRQ : std_logic;
+ signal A_SCK : std_logic;
+ signal A_SCKB : std_logic;
+ signal A_SDI : std_logic;
+ signal A_SDIB : std_logic;
+ signal A_SDO : std_logic;
+ signal A_SDOB : std_logic;
+ signal A_CSB : std_logic;
+ signal A_CS : std_logic;
+ signal B_SCK : std_logic;
+ signal B_SCKB : std_logic;
+ signal B_SDI : std_logic;
+ signal B_SDIB : std_logic;
+ signal B_SDO : std_logic;
+ signal B_SDOB : std_logic;
+ signal B_CSB : std_logic;
+ signal B_CS : std_logic;
+ signal C_SCK : std_logic;
+ signal C_SCKB : std_logic;
+ signal C_SDI : std_logic;
+ signal C_SDIB : std_logic;
+ signal C_SDO : std_logic;
+ signal C_SDOB : std_logic;
+ signal C_CSB : std_logic;
+ signal C_CS : std_logic;
+ signal D_SCK : std_logic;
+ signal D_SCKB : std_logic;
+ signal D_SDI : std_logic;
+ signal D_SDIB : std_logic;
+ signal D_SDO : std_logic;
+ signal D_SDOB : std_logic;
+ signal D_CSB : std_logic;
+ signal D_CS : std_logic;
+ signal A_TEST1 : std_logic;
+ signal A_TEST1B : std_logic;
+ signal A_TEST2 : std_logic;
+ signal A_TEST2B : std_logic;
+ signal B_TEST1 : std_logic;
+ signal B_TEST1B : std_logic;
+ signal B_TEST2 : std_logic;
+ signal B_TEST2B : std_logic;
+ signal C_TEST1 : std_logic;
+ signal C_TEST1B : std_logic;
+ signal C_TEST2 : std_logic;
+ signal C_TEST2B : std_logic;
+ signal D_TEST1 : std_logic;
+ signal D_TEST1B : std_logic;
+ signal D_TEST2 : std_logic;
+ signal D_TEST2B : std_logic;
+ signal DSPADDR : std_logic_vector (31 downto 0);
+ signal DSPDAT : std_logic_vector (31 downto 0);
+ signal DSP_ACK : std_logic;
+ signal DSP_BM : std_logic;
+ signal DSP_BMS : std_logic;
+ signal DSP_BOFF : std_logic;
+ signal DSP_BRST : std_logic;
+ signal DSP_HBG : std_logic;
+ signal DSP_HBR : std_logic;
+ signal DSP_IRQ : std_logic_vector (3 downto 0);
+ signal DSP_RD : std_logic;
+ signal DSP_RESET : std_logic;
+ signal DSP_RESET_OUT : std_logic;
+ signal DSP_WRH : std_logic;
+ signal DSP_WRL : std_logic;
+ signal VSD_A : std_logic_vector (12 downto 0);
+ signal VSD_BA : std_logic_vector (1 downto 0);
+ signal VSD_CAS : std_logic;
+ signal VSD_CKE : std_logic;
+ signal VSD_CLOCK : std_logic;
+ signal VSD_CSEH : std_logic;
+ signal VSD_CSEL : std_logic;
+ signal VSD_D : std_logic_vector (31 downto 0);
+ signal VSD_DQML : std_logic_vector (3 downto 0);
+ signal VSD_RAS : std_logic;
+ signal VSD_WE : std_logic;
+ signal TLK_CLK : std_logic;
+ signal TLK_ENABLE : std_logic;
+ signal TLK_LCKREFN : std_logic;
+ signal TLK_LOOPEN : std_logic;
+ signal TLK_PRBSEN : std_logic;
+ signal TLK_RXD : std_logic_vector (15 downto 0);
+ signal TLK_RX_CLK : std_logic;
+ signal TLK_RX_DV : std_logic;
+ signal TLK_RX_ER : std_logic;
+ signal TLK_TXD : std_logic_vector (15 downto 0);
+ signal TLK_TX_EN : std_logic;
+ signal TLK_TX_ER : std_logic;
+ signal SFP_LOS : std_logic;
+ signal SFP_TX_DIS : std_logic;
+ signal SFP_TX_FAULT : std_logic;
+ signal ADO_LV : std_logic_vector(51 downto 0);
+ signal ADO_TTL : std_logic_vector(46 downto 0);
+ signal VIRT_TCK : std_logic;
+ signal VIRT_TDI : std_logic;
+ signal VIRT_TDO : std_logic;
+ signal VIRT_TMS : std_logic;
+ signal VIRT_TRST : std_logic;
+
+
+ signal test_synch_00 : std_logic;
+ signal dtu_clk : std_logic;
+ signal dtu_lvl1_tag : std_logic_vector(7 downto 0);
+ signal dtu_lvl2_tag : std_logic_vector(7 downto 0);
+ signal lvl1_trig : std_logic;
+ signal lvl2_trig : std_logic;
+BEGIN
+ trb: trb_v2b_fpga
+ port map (
+ VIRT_CLK => VIRT_CLK,
+ VIRT_CLKB => VIRT_CLKB,
+ RESET_VIRT => RESET_VIRT,
+ DBAD => DBAD,
+ DGOOD => DGOOD,
+ DINT => DINT,
+ DWAIT => DWAIT,
+ A_RESERVED => A_RESERVED,
+ A_TEMP => A_TEMP,
+ B_RESERVED => B_RESERVED,
+ B_TEMP => B_TEMP,
+ C_RESERVED => C_RESERVED,
+ C_TEMP => C_TEMP,
+ D_RESERVED => D_RESERVED,
+ D_TEMP => D_TEMP,
+ VIR_TRIG => VIR_TRIG,
+ VIR_TRIGB => VIR_TRIGB,
+ A_TDC_ERROR => A_TDC_ERROR,
+ B_TDC_ERROR => B_TDC_ERROR,
+ C_TDC_ERROR => C_TDC_ERROR,
+ D_TDC_ERROR => D_TDC_ERROR,
+ A_TDC_POWERUP => A_TDC_POWERUP,
+ B_TDC_POWERUP => B_TDC_POWERUP,
+ C_TDC_POWERUP => C_TDC_POWERUP,
+ D_TDC_POWERUP => D_TDC_POWERUP,
+ TOKEN_IN => TOKEN_IN,
+ TOKEN_OUT => TOKEN_OUT,
+ C_TOKEN_OUT_TTL => C_TOKEN_OUT_TTL,
+ GET_DATA => GET_DATA,
+ A_DATA_READY => A_DATA_READY,
+ B_DATA_READY => B_DATA_READY,
+ C_DATA_READY => C_DATA_READY,
+ D_DATA_READY => D_DATA_READY,
+ REF_TDC_CLK => REF_TDC_CLK,
+ REF_TDC_CLKB => REF_TDC_CLKB,
+ A_TDC_BU_RESET => A_TDC_BU_RESET,
+ A_TDC_BU_RESETB => A_TDC_BU_RESETB,
+ A_TDC_EV_RESET => A_TDC_EV_RESET,
+ A_TDC_EV_RESETB => A_TDC_EV_RESETB,
+ B_TDC_BU_RESET => B_TDC_BU_RESET,
+ B_TDC_BU_RESETB => B_TDC_BU_RESETB,
+ B_TDC_EV_RESET => B_TDC_EV_RESET,
+ B_TDC_EV_RESETB => B_TDC_EV_RESETB,
+ C_TDC_BU_RESET => C_TDC_BU_RESET,
+ C_TDC_BU_RESETB => C_TDC_BU_RESETB,
+ C_TDC_EV_RESET => C_TDC_EV_RESET,
+ C_TDC_EV_RESETB => C_TDC_EV_RESETB,
+ D_TDC_BU_RESET => D_TDC_BU_RESET,
+ D_TDC_BU_RESETB => D_TDC_BU_RESETB,
+ D_TDC_EV_RESET => D_TDC_EV_RESET,
+ D_TDC_EV_RESETB => D_TDC_EV_RESETB,
+ TDC_OUT => TDC_OUT,
+ TDC_RESET => TDC_RESET,
+ A_TRIGGER => A_TRIGGER,
+ A_TRIGGERB => A_TRIGGERB,
+ B_TRIGGER => B_TRIGGER,
+ B_TRIGGERB => B_TRIGGERB,
+ C_TRIGGER => C_TRIGGER,
+ C_TRIGGERB => C_TRIGGERB,
+ D_TRIGGER => D_TRIGGER,
+ D_TRIGGERB => D_TRIGGERB,
+ FS_PB => FS_PB,
+ FS_PC => FS_PC,
+ ETRAX_IRQ => ETRAX_IRQ,
+ A_SCK => A_SCK,
+ A_SCKB => A_SCKB,
+ A_SDI => A_SDI,
+ A_SDIB => A_SDIB,
+ A_SDO => A_SDO,
+ A_SDOB => A_SDOB,
+ A_CSB => A_CSB,
+ A_CS => A_CS,
+ B_SCK => B_SCK,
+ B_SCKB => B_SCKB,
+ B_SDI => B_SDI,
+ B_SDIB => B_SDIB,
+ B_SDO => B_SDO,
+ B_SDOB => B_SDOB,
+ B_CSB => B_CSB,
+ B_CS => B_CS,
+ C_SCK => C_SCK,
+ C_SCKB => C_SCKB,
+ C_SDI => C_SDI,
+ C_SDIB => C_SDIB,
+ C_SDO => C_SDO,
+ C_SDOB => C_SDOB,
+ C_CSB => C_CSB,
+ C_CS => C_CS,
+ D_SCK => D_SCK,
+ D_SCKB => D_SCKB,
+ D_SDI => D_SDI,
+ D_SDIB => D_SDIB,
+ D_SDO => D_SDO,
+ D_SDOB => D_SDOB,
+ D_CSB => D_CSB,
+ D_CS => D_CS,
+ A_TEST1 => A_TEST1,
+ A_TEST1B => A_TEST1B,
+ A_TEST2 => A_TEST2,
+ A_TEST2B => A_TEST2B,
+ B_TEST1 => B_TEST1,
+ B_TEST1B => B_TEST1B,
+ B_TEST2 => B_TEST2,
+ B_TEST2B => B_TEST2B,
+ C_TEST1 => C_TEST1,
+ C_TEST1B => C_TEST1B,
+ C_TEST2 => C_TEST2,
+ C_TEST2B => C_TEST2B,
+ D_TEST1 => D_TEST1,
+ D_TEST1B => D_TEST1B,
+ D_TEST2 => D_TEST2,
+ D_TEST2B => D_TEST2B,
+ DSPADDR => DSPADDR,
+ DSPDAT => DSPDAT,
+ DSP_ACK => DSP_ACK,
+ DSP_BM => DSP_BM,
+ DSP_BMS => DSP_BMS,
+ DSP_BOFF => DSP_BOFF,
+ DSP_BRST => DSP_BRST,
+ DSP_HBG => DSP_HBG,
+ DSP_HBR => DSP_HBR,
+ DSP_IRQ => DSP_IRQ,
+ DSP_RD => DSP_RD,
+ DSP_RESET => DSP_RESET,
+ DSP_RESET_OUT => DSP_RESET_OUT,
+ DSP_WRH => DSP_WRH,
+ DSP_WRL => DSP_WRL,
+ VSD_A => VSD_A,
+ VSD_BA => VSD_BA,
+ VSD_CAS => VSD_CAS,
+ VSD_CKE => VSD_CKE,
+ VSD_CLOCK => VSD_CLOCK,
+ VSD_CSEH => VSD_CSEH,
+ VSD_CSEL => VSD_CSEL,
+ VSD_D => VSD_D,
+ VSD_DQML => VSD_DQML,
+ VSD_RAS => VSD_RAS,
+ VSD_WE => VSD_WE,
+ TLK_CLK => TLK_CLK,
+ TLK_ENABLE => TLK_ENABLE,
+ TLK_LCKREFN => TLK_LCKREFN,
+ TLK_LOOPEN => TLK_LOOPEN,
+ TLK_PRBSEN => TLK_PRBSEN,
+ TLK_RXD => TLK_RXD,
+ TLK_RX_CLK => TLK_RX_CLK,
+ TLK_RX_DV => TLK_RX_DV,
+ TLK_RX_ER => TLK_RX_ER,
+ TLK_TXD => TLK_TXD,
+ TLK_TX_EN => TLK_TX_EN,
+ TLK_TX_ER => TLK_TX_ER,
+ SFP_LOS => SFP_LOS,
+ SFP_TX_DIS => SFP_TX_DIS,
+ SFP_TX_FAULT => SFP_TX_FAULT,
+ ADO_LV => ADO_LV,
+ ADO_TTL => ADO_TTL,
+ VIRT_TCK => VIRT_TCK,
+ VIRT_TDI => VIRT_TDI,
+ VIRT_TDO => VIRT_TDO,
+ VIRT_TMS => VIRT_TMS,
+ VIRT_TRST => VIRT_TRST);
+
+-------------------------------------------------------------------------------
+-- etraxnt_test
+-------------------------------------------------------------------------------
+
+ etrax_intf : PROCESS
+ BEGIN
+
+ --reading DSP(dev number 1)
+ wait for 10 ns;
+ RESET_VIRT <= '0';
+
+ wait for 10 ns;
+ FS_PC(16) <= '1';
+ FS_PC(17) <= '1';
+ RESET_VIRT <= '1';
+ wait for 10 ns;
+
+ wait for 30 ns;
+ -- FS_PC(16) <= '0';
+ -- FS_PC(17) <= '0';
+ -- wait for 10 ns;
+ FS_PC(15 downto 0) <= x"0000";
+ FS_PC(16) <= '0';
+ FS_PC(17) <= '0';
+ wait on VIRT_CLK until FS_PB(16) = '0';
+ wait for 20 ns;
+ FS_PC(16) <= '1';
+ wait for 20 ns;
+ FS_PC(15) <= '1'; --read mode(1)
+ FS_PC(14 downto 8) <= (others => '0');
+ FS_PC(7 downto 0) <= x"00"; --device
+ FS_PC(16) <= '0';
+ FS_PC(17) <= '0';
+ wait for 20 ns;
+ FS_PC(15 downto 0) <= x"0000"; --address upper part
+ FS_PC(16) <= '1';
+ FS_PC(17) <= '0';
+ wait for 20 ns;
+ FS_PC(16) <= '0';
+ wait for 20 ns;
+ FS_PC(16) <= '1';
+ FS_PC(15 downto 0) <= x"0025"; --adrees lower part
+ FS_PC(16) <= '1';
+ FS_PC(17) <= '0';
+ wait for 20 ns;
+ FS_PC(16) <= '0';
+ wait on VIRT_CLK until FS_PB(16)= '1';
+ FS_PC(16) <= '1';
+ wait for 20 ns;
+ FS_PC(16) <= '0';
+ wait on VIRT_CLK until FS_PB(16) = '0';
+ FS_PC(16) <= '1';
+ wait for 20 ns;
+ FS_PC(16) <= '0';
+ wait on VIRT_CLK until FS_PB(16)= '1';
+ FS_PC(16) <= '1';
+ wait for 20 ns;
+ FS_PC(16) <= '0';
+ --writing DSP
+ wait for 20 ns;
+ FS_PC(16) <= '1';
+ test_synch_00 <= '1';
+ wait for 20 ns;
+ FS_PC(15) <= '0'; --write mode
+ FS_PC(14 downto 8) <= (others => '0');
+ FS_PC(7 downto 0) <= x"00"; --device
+ FS_PC(16) <= '0';
+ FS_PC(17) <= '0';
+ wait for 20 ns;
+ FS_PC(15 downto 0) <= x"0000"; --address upper part
+ FS_PC(16) <= '1';
+ FS_PC(17) <= '0';
+ wait for 20 ns;
+ FS_PC(16) <= '0';
+ wait for 20 ns;
+ FS_PC(16) <= '1';
+ FS_PC(15 downto 0) <= x"0006"; --adrees lower part
+ FS_PC(16) <= '1';
+ FS_PC(17) <= '0';
+ wait for 20 ns;
+ FS_PC(16) <= '0';
+ wait for 20 ns;
+ FS_PC(15 downto 0) <= x"0004"; --data upper part
+ FS_PC(16) <= '1';
+ FS_PC(17) <= '0';
+ wait for 20 ns;
+ FS_PC(16) <= '0';
+ wait for 20 ns;
+ FS_PC(15 downto 0) <= x"0000"; --data lower part - 1 switch on
+ --internal generation of trigger
+ FS_PC(16) <= '1';
+ FS_PC(17) <= '0';
+ wait for 20 ns;
+ FS_PC(16) <= '0';
+ wait for 20 ns;
+ test_synch_00 <= '0';
+ FS_PC(16) <= '1';
+ wait for 20 ns;
+ FS_PC(16) <= '0';
+ FS_PC(15 downto 0) <= (others => 'Z');
+-- wait on VIRT_CLK until FS_PB(16)= '1';
+ loop
+ wait on VIRT_CLK until FS_PB(16) = '1';
+ FS_PC(17) <= '1';
+ wait for 50 ns;
+ FS_PC(17) <= '0';
+ wait for 50 ns;
+ end loop;
+
+ wait; -- will wait forever
+ end process;
+
+
+
+
+ clock_gclk : process
+ begin
+ VIRT_CLK <= '0';
+ VIRT_CLKB <= '1';
+ wait for 5 ns;
+ VIRT_CLKB <= '0';
+ VIRT_CLK <= '1';
+ wait for 5 ns;
+ end process;
+
+
+
+ dsp : process
+ begin
+ DSP_ACK <= '1';
+ DSP_HBG <= '1';
+ wait for 20 ns;
+ DSPDAT <= (others => 'Z');
+ wait on VIRT_CLK until DSP_HBR = '0';
+ wait for 8 ns;
+ DSP_HBG <= '0';
+ DSPDAT <= x"babeface";
+ wait for 10 ns;
+ DSP_ACK <= '1';
+ wait on VIRT_CLK until DSP_HBR = '1';
+ DSP_ACK <= '0';
+ DSP_HBG <= '1';
+ DSPDAT <= (others => 'Z');
+ wait on VIRT_CLK until test_synch_00 = '1';
+ wait on VIRT_CLK until DSP_HBR = '0';
+ wait for 8 ns;
+ DSP_HBG <= '0';
+ wait until DSP_HBR = '1';
+ DSP_HBG <= '1';
+ wait;
+ end process;
+ -----------------------------------------------------------------------
+ -- TLK
+ -----------------------------------------------------------------------
+ clock_tlk_clk : process
+ begin
+ TLK_CLK <= '0';
+ wait for 5 ns;
+ TLK_CLK <= '1';
+ wait for 5 ns;
+ end process;
+ clock_tlk_rx_clk : process
+ begin
+ TLK_RX_CLK <= '0';
+ wait for 5 ns;
+ TLK_RX_CLK <= '1';
+ wait for 5 ns;
+ end process;
+ RX_ER: process
+ begin
+ TLK_RX_ER <= '0';
+ wait for 2200 ns;
+ TLK_RX_ER <= '1';
+ wait for 120 ns;
+ end process;
+ TLK_RXD <= TLK_TXD;
+ --TLK_RX_ER <= '0';
+ TLK_RX_DV <= '1';
+ -----------------------------------------------------------------------
+ -- TDC
+ -----------------------------------------------------------------------
+ clock_tdcclk : process
+ begin
+ wait for 12 ns;
+ loop
+ REF_TDC_CLK <= '0';
+ REF_TDC_CLKB <= '1';
+ wait for 12.5 ns;
+ REF_TDC_CLK <= '1';
+ REF_TDC_CLKB <= '0';
+ wait for 12.5 ns;
+ end loop;
+ end process;
+ trigger_lvl1 : process
+ begin
+-- ADO_TTL(7) <= '0';
+ A_DATA_READY <= '0';
+ B_DATA_READY <= '0';
+ C_DATA_READY <= '0';
+ D_DATA_READY <= '0';
+ TOKEN_IN <= '0';
+ TDC_OUT <= x"bedebabe";
+-- A_TEMP <= '0';
+-- wait for 50 ns;
+-- A_TEMP <= '1';
+-- wait for 10 ns;
+-- A_TEMP <= '0';
+-- wait for 10 ns;
+ wait on REF_TDC_CLK until TOKEN_OUT = '1';
+ wait on REF_TDC_CLK until TOKEN_OUT = '0';
+ wait for 10 ns;
+-- ADO_TTL(7) <= '0';
+ A_DATA_READY <= '1';
+ wait for 50 ns;
+ A_DATA_READY <= '0';
+ B_DATA_READY <= '1';
+ wait for 50 ns;
+ B_DATA_READY <= '0';
+ C_DATA_READY <= '1';
+ wait for 50 ns;
+-- ADO_TTL(7) <= '0';
+ C_DATA_READY <= '0';
+ D_DATA_READY <= '1';
+ wait for 50 ns;
+ D_DATA_READY <= '0';
+ wait for 0 ns;
+-- ADO_TTL(6) <= '1';
+ TOKEN_IN <= '1';
+ wait for 25 ns;
+-- ADO_TTL(6) <= '0';
+ TOKEN_IN <= '0';
+ -- wait on REF_TDC_CLK until DBAD = '0';
+ end process;
+-- trigger_lvl2 : process
+-- begin
+-- B_TEMP <= '0';
+-- C_TEMP <= '0';
+-- wait until DBAD = '1';
+-- wait until DBAD = '0';
+-- wait for 30 ns;
+-- wait on VIRT_CLK until DGOOD = '0';
+-- B_TEMP <= '0';
+-- C_TEMP <= '1';
+-- wait for 30 ns;
+-- end process;
+
+ -----------------------------------------------------------------------
+ -- DTU
+ -----------------------------------------------------------------------
+ clock_dtu : process
+ begin
+ wait for 34 ns;
+
+ loop
+ dtu_clk <= '0';
+ wait for 50 ns;
+ dtu_clk <= '1';
+ wait for 50 ns;
+ end loop;
+ end process;
+ ADO_TTL(4) <= lvl1_trig;
+ ADO_TTL(10) <= lvl2_trig;
+
+ -- LVL1_TAG_COUNTER: process (dtu_clk,RESET_VIRT,lvl1_trig)
+ -- begin
+ -- if rising_edge(dtu_clk) then
+ -- if RESET_VIRT = '0' then
+ -- dtu_lvl1_tag <= x"00";
+ -- elsif ADO_TTL(17) = '1' then
+ -- dtu_lvl1_tag <= dtu_lvl1_tag +1;
+ -- end if;
+ -- end if;
+ -- end process LVL1_TAG_COUNTER;
+ LVL1_COUNT:process
+ begin
+ wait for 100 ns;
+ dtu_lvl1_tag <= x"00";
+ wait on dtu_clk until ADO_TTL(0) = '0';
+ wait on dtu_clk until lvl1_trig = '1';
+ wait for 500 ns;
+ dtu_lvl1_tag <= dtu_lvl1_tag +1;
+ loop
+ wait on dtu_clk until ADO_TTL(0) = '1';
+ -- wait for 1000 ns;
+ dtu_lvl1_tag <= dtu_lvl1_tag +1;
+ wait on dtu_clk until ADO_TTL(0) = '0';
+ end loop;
+ end process LVL1_COUNT;
+ LVL2_COUNT:process
+ begin
+ wait for 100 ns;
+ dtu_lvl2_tag <= x"00";
+ wait on dtu_clk until ADO_TTL(2) = '0';
+ loop
+ -- wait on dtu_clk until ADO_TTL(2) = '1';
+ wait on dtu_clk until lvl2_trig = '1';
+ -- wait for 1000 ns;
+ wait for 500 ns;
+ dtu_lvl2_tag <= dtu_lvl2_tag +1;
+ wait on dtu_clk until ADO_TTL(2) = '0';
+ end loop;
+ end process LVL2_COUNT;
+
+
+ -- LVL2_TAG_COUNTER: process (dtu_clk,RESET_VIRT,lvl2_trig)
+ -- begin
+ -- if rising_edge(dtu_clk) then
+ -- if RESET_VIRT = '0' then
+ -- dtu_lvl2_tag <= x"00";
+ -- elsif lvl2_trig = '1' then
+ -- dtu_lvl2_tag <= dtu_lvl2_tag +1;
+ -- end if;
+ -- end if;
+ -- end process LVL2_TAG_COUNTER;
+ -- ADO_TTL(20 downto 17) <= (others => 'Z');
+
+
+ ADO_TTL(4) <= lvl1_trig;
+ DTU_EMULATION_LVL1: process
+ begin
+ ADO_TTL(9) <= '0';
+ lvl1_trig <= '0';
+ wait for 1000 ns;
+ wait on dtu_clk until ADO_TTL(0) = '0' and dtu_clk = '1'; --busylvl1
+ lvl1_trig <= '1';
+ ADO_TTL(8 downto 5) <= x"d";
+ wait for 100 ns;
+ lvl1_trig <= '0';
+ wait for 100 ns;
+ ADO_TTL(9) <= '1';
+ ADO_TTL(8 downto 5) <= dtu_lvl1_tag(3 downto 0);
+ wait for 100 ns;
+ ADO_TTL(9) <= '0';
+ wait for 100 ns;
+ ADO_TTL(9) <= '1';
+ ADO_TTL(8 downto 5) <= dtu_lvl1_tag(7 downto 4);
+ loop
+ wait for 100 ns;
+ ADO_TTL(9) <= '0';
+ wait for 100 ns;
+ ADO_TTL(9) <= '1';
+ wait for 100 ns;
+ ADO_TTL(9) <= '0';
+ wait on dtu_clk until ADO_TTL(0) = '0' and dtu_clk = '1'; --busylvl1
+ wait for 300 ns;
+ lvl1_trig <= '1';
+ ADO_TTL(8 downto 5) <= x"1";
+ wait for 100 ns;
+ lvl1_trig <= '0';
+ wait for 100 ns;
+ ADO_TTL(9) <= '1';
+ ADO_TTL(8 downto 5) <= dtu_lvl1_tag(3 downto 0);
+ wait for 100 ns;
+ ADO_TTL(9) <= '0';
+ wait for 100 ns;
+ ADO_TTL(9) <= '1';
+ ADO_TTL(8 downto 5) <= dtu_lvl1_tag(7 downto 4);
+ end loop;
+ end process DTU_EMULATION_LVL1;
+
+ ADO_TTL(10) <= lvl2_trig;
+ DTU_EMULATION_LVL2:process
+ begin
+ ADO_TTL(15) <= '0';
+ lvl2_trig <= '0';
+ wait for 26000 ns;
+ loop
+ ADO_TTL(15) <= '0';
+ wait on dtu_clk until ADO_TTL(2) = '0'and dtu_clk = '1'; --busylvl2
+ -- wait on dtu_clk until dtu_lvl1_tag > dtu_lvl2_tag + 1;
+ wait on dtu_clk until dtu_lvl1_tag - dtu_lvl2_tag > x"01";
+ wait for 300 ns;
+ lvl2_trig <= '1';
+ ADO_TTL(14 downto 11) <= x"1";
+ wait for 100 ns;
+ lvl2_trig <= '0';
+ wait for 100 ns;
+ ADO_TTL(15) <= '1';
+ ADO_TTL(14 downto 11) <= dtu_lvl2_tag(3 downto 0);
+ wait for 100 ns;
+ ADO_TTL(15) <= '0';
+ wait for 100 ns;
+ ADO_TTL(15) <= '1';
+ ADO_TTL(14 downto 11) <= dtu_lvl2_tag(7 downto 4);
+ wait for 100 ns;
+ ADO_TTL(15) <= '0';
+ wait for 100 ns;
+ ADO_TTL(15) <= '1';
+ wait for 100 ns;
+ ADO_TTL(15) <= '0';
+
+ wait on dtu_clk until ADO_TTL(2) = '0'and dtu_clk = '1';
+ wait on dtu_clk until dtu_lvl1_tag - dtu_lvl2_tag > x"01";
+ wait for 100 ns;
+ lvl2_trig <= '1';
+ ADO_TTL(14 downto 11) <= x"9";
+ wait for 100 ns;
+ lvl2_trig <= '0';
+ wait for 100 ns;
+ ADO_TTL(15) <= '1';
+ ADO_TTL(14 downto 11) <= dtu_lvl2_tag(3 downto 0);
+ wait for 100 ns;
+ ADO_TTL(15) <= '0';
+ wait for 100 ns;
+ ADO_TTL(15) <= '1';
+ ADO_TTL(14 downto 11) <= dtu_lvl2_tag(7 downto 4);
+ wait for 100 ns;
+ ADO_TTL(15) <= '0';
+ wait for 100 ns;
+ ADO_TTL(15) <= '1';
+ wait for 100 ns;
+ ADO_TTL(15) <= '0';
+ end loop;
+ end process DTU_EMULATION_LVL2;
+
+-- ETRAX_RESPONSE: process
+-- begin
+-- FS_PC(16) <= '0';
+-- FS_PC(17) <= '0';
+-- wait for 10 ns;
+-- RESET_VIRT <= '0';
+
+-- wait for 10 ns;
+-- FS_PC(16) <= '1';
+-- FS_PC(17) <= '1';
+-- RESET_VIRT <= '1';
+-- wait for 10 ns;
+
+-- wait for 30 ns;
+-- FS_PC(16) <= '0';
+-- FS_PC(17) <= '0';
+-- wait for 10 ns;
+-- loop
+-- FS_PC(17) <= '0';
+-- wait on TLK_CLK until FS_PB(16) ='1';
+-- wait for 20 ns;
+-- FS_PC(17) <= '1';
+-- wait for 2000 ns;
+-- end loop;
+-- end process ETRAX_RESPONSE;
+-- EXTERNAL_TRIGG: process
+-- begin
+-- wait for 15 ns;
+-- loop
+-- ADO_TTL(0) <= '1';
+-- ADO_TTL(1) <= '0';
+-- wait for 74 ns;
+-- ADO_TTL(0) <= '0';
+-- ADO_TTL(1) <= '1';
+-- wait for 82 ns;
+-- end loop;
+-- end process EXTERNAL_TRIGG;
+END;
jspc29 / trbv2.git / commitdiff