async ram, IF

diff --git a/machxo3/flash/generic_flash_ctrl.vhd b/machxo3/flash/generic_flash_ctrl.vhd
index 70b86278df4264d2ec8430510f3951d1fa7a4b8e..3e8a27f80fa427b1b939b7d4a15fba1339f975f5 100644 (file)
--- a/machxo3/flash/generic_flash_ctrl.vhd
+++ b/machxo3/flash/generic_flash_ctrl.vhd
@@ -46,7 +46,8 @@ entity generic_flash_ctrl is
            DATA_BUS_WIDTH   : integer := 16\r
            );\r
   port(\r
-    CLK   : in  std_logic;\r
+    CLK_l : in  std_logic; --local clock\r
+    CLK_f : in  std_logic; --flash clock\r
     RESET : in  std_logic;\r
 \r
     -- SPI/UART in host direction\r
@@ -152,8 +153,8 @@ begin
       DataInB   => flashram_data_i,\r
       AddressA  => ram_addr_i,\r
       AddressB  => flashram_addr_i,\r
-      ClockA    => CLK,\r
-      ClockB    => CLK,\r
+      ClockA    => CLK_l,\r
+      ClockB    => CLK_f,\r
       ClockEnA  => '1',\r
       ClockEnB  => flashram_cen_i,\r
       WrA       => ram_write_i,\r
@@ -166,7 +167,7 @@ begin
 \r
   THE_FLASH : UFM_WB\r
     port map(\r
-      clk_i     => CLK,\r
+      clk_i     => CLK_f,\r
       rst_n     => not RESET,\r
       cmd       => flash_command,\r
       ufm_page  => flash_page,\r
@@ -191,7 +192,7 @@ begin
   LOC_BUSY_OUT  <= SPI_BUSY_IN;\r
   \r
 PROC_SELECTOR : process begin\r
-  wait until rising_edge(CLK);\r
+  wait until rising_edge(clk_l);\r
 \r
   reg_LOC_DATA_OUT  <= SPI_DATA_IN;\r
   reg_LOC_ADDR_OUT  <= SPI_ADDR_IN;\r
@@ -202,14 +203,19 @@ PROC_SELECTOR : process begin
     reg_SPI_READY_OUT <= LOC_READY_IN;\r
   end if;\r
   \r
-  \r
   ram_write_i <= '0';\r
   ram_data_i <= x"00";\r
-  if (burst_counter = "0000") then\r
+  if (burst_counter = "0000" and out_delay = "000") then\r
     spi_ram_addr_i <= x"0";\r
+  else\r
+    spi_ram_addr_i <= spi_ram_addr_i;\r
   end if;\r
-  spi_flash_go <= '0';\r
 \r
+  if (flash_busy = '1') then\r
+    spi_flash_go <= '0';\r
+  end if;\r
+  \r
+    \r
   if (clean_master_start_reg = '1') then\r
     master_start_reg <= '0';\r
   end if;\r
@@ -367,9 +373,9 @@ flash_go <= master_flash_go when master_running = '1' else spi_flash_go;
 flash_page <= master_flash_page when master_running = '1' else spi_flash_page;\r
 flash_command <= master_flash_command when master_running = '1' else spi_flash_command;\r
 \r
-state_machine :  process (CLK)\r
+state_machine :  process (clk_f)\r
 begin\r
-  if rising_edge(CLK) then\r
+  if rising_edge(clk_f) then\r
     master_flash_go  <= '0';\r
     master_WRITE_OUT <= '0';\r
     clean_master_start_reg <= '0';\r