fix readback of df35 register (mult logic 0)

diff --git a/base/code/input_to_trigger_logic_record.vhd b/base/code/input_to_trigger_logic_record.vhd
index 05f86f1eea088d9051468dbce0ae943bd4358413..de8c913240c3642e4938b8ff489e71165b0ac678 100644 (file)
--- a/base/code/input_to_trigger_logic_record.vhd
+++ b/base/code/input_to_trigger_logic_record.vhd
@@ -218,7 +218,7 @@ begin
     elsif BUS_RX.addr(6 downto 0) = "0110100" then
       BUS_TX.data <= edge_enable & set_output_coin & set_output_mult(0) & set_output_simplecoin;
     elsif BUS_RX.addr(6 downto 0) = "0110101" and INPUTS > 32 then
-      BUS_TX.data                 <= multiplicity_enable(1)(63 downto 32);
+      BUS_TX.data                 <= multiplicity_enable(0)(63 downto 32);
     elsif BUS_RX.addr(6 downto 0) = "0110110" then
       BUS_TX.data                 <= x"00000" & "000" & set_stretchedge & "00" & std_logic_vector(set_stretcher);
     elsif BUS_RX.addr(6 downto 0) = "0110111" then