constraint files are individual for each design

diff --git a/base/trb3_periph_padiwa.lpf b/base/trb3_periph_padiwa.lpf
index 7979fabc78b3104e6db176efe0c4f474010ba1f1..5b276cd0daf0c3f09a2f197b0c92db1953c36d2d 100644 (file)
--- a/base/trb3_periph_padiwa.lpf
+++ b/base/trb3_periph_padiwa.lpf
@@ -12,8 +12,8 @@ FREQUENCY PORT CLK_GPLL_LEFT  125 MHz;
 FREQUENCY PORT CLK_PCLK_LEFT  200 MHz;
 FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
 
-MULTICYCLE FROM CLKNET "clk_100_internal_c" TO CLKNET "CLK_PCLK_LEFT" 2 X ;
-MULTICYCLE FROM CLKNET "CLK_PCLK_LEFT" TO CLKNET "clk_100_internal_c" 2 X ;
+MULTICYCLE FROM CLKNET "clk_100_internal_c" TO CLKNET "CLK_PCLK_LEFT_c" 1 X ;
+MULTICYCLE FROM CLKNET "CLK_PCLK_LEFT_c" TO CLKNET "clk_100_internal_c" 2 X ;
 
 LOCATE COMP   "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;