small modifications.

diff --git a/trb_net_old_to_new.vhd b/trb_net_old_to_new.vhd
index 1cd80da2886a6633cd9ea7d2903dd6e50f394011..47474606810fa80333cf0128e2c755302df266d1 100644 (file)
--- a/trb_net_old_to_new.vhd
+++ b/trb_net_old_to_new.vhd
@@ -26,10 +26,6 @@ library IEEE;
 use IEEE.STD_LOGIC_1164.all;
 use IEEE.STD_LOGIC_ARITH.all;
 use IEEE.STD_LOGIC_UNSIGNED.all;
-use ieee.numeric_std.all;
-
-
---use work.trb_net_std.all;
 
 entity trb_net_old_to_new is
   generic (TRIGGER_LEVEL : integer := 1);  -- either 1 or 2
@@ -171,7 +167,7 @@ begin
   end generate GEN_L1;
 
   -- Register TRIGTAG
-  GEN_L1 : if TRIGGER_LEVEL = 2 generate
+  GEN_L2 : if TRIGGER_LEVEL = 2 generate
     process (CLK, RESET, CLK_EN, TRIGTAG_i)
     begin  -- process S
       if RESET = '1' then
@@ -180,7 +176,7 @@ begin
         TRIGTAG_ii <= TRIGTAG_i;
       end if;
     end process;
-  end generate GEN_L1;
+  end generate GEN_L2;
 
   -----------------------------------------------------------------------------
   -- FSM
@@ -247,9 +243,9 @@ begin
           do_send_cnt <= do_send_cnt+1;
         end if;
 
-        if do_send_cnt = X"01" then
+        if do_send_cnt = 1 then
           APL_SEND_OUT           <= '1';
-         elsif do_send_cnt="0011" or do_send_cnt="0100" then
+         elsif do_send_cnt=3 or do_send_cnt=4 then
              APL_READ_OUT           <= '1';
         end if;