]> jspc29.x-matter.uni-frankfurt.de Git - daqdocu.git/commitdiff
tdc slow control section is added.
authorhadaq <hadaq>
Wed, 11 Jul 2012 13:35:56 +0000 (13:35 +0000)
committerhadaq <hadaq>
Wed, 11 Jul 2012 13:35:56 +0000 (13:35 +0000)
trb3/TdcBuildingBlocks.tex
trb3/TdcDataFormat.tex
trb3/TdcSlowControl.tex
trb3/main.tex

index a96094bb04a75c4519cfadf5265f4b0a88d3fcda..9b7a84e54842edba146d91aa3458c7b8aa43118b 100644 (file)
@@ -36,7 +36,7 @@ In each TDC channel the measurement result of the fine time measurement block is
 \end{figure}
 
 \subsubsection{Fine Time Measurement}
-\label{sec:FineTime}
+\label{sec:tdcFineTime}
 
 For fine time measurements the Tapped Delay Line (TDL) method is used. This method is based on a delay path with delay elements, which have similar propagation delays. With the start signal the propagation along the delay line starts and with the stop signal the output of the each delay element is latched (Figure~\ref{fig:tdcTdl}). The location of the propagating signal along the delay line defines the fine time between start and stop signals.
 
index 7f68312057c1b1fb606c70e2587ecb594c26e329..90889e5ca03b729b43e8004b06849945384e8bf0 100644 (file)
@@ -6,7 +6,7 @@ The data format of the \textbf{\textit{header}} word is shown below:
 
 \begin{table}[h]
   \centering
-    \begin{tabular}{|C{1.2cm}|C{2cm}|C{3.2cm}|C{6.3cm}|}
+    \begin{tabular}{|W{1.2cm}|W{2cm}|W{3.2cm}|W{6.3cm}|}
       \hline
       3 bits   & 5 bits        & 8 bits        & 16 bits\\
       "001"    & reserved      & random code   & error bits\\
@@ -52,9 +52,9 @@ The data format of the \textbf{\textit{time data}} word is shown below:
 
 \begin{table}[h]
   \centering
-    \begin{tabular}{|C{0.7cm}|C{1.5cm}|C{1.98cm}|C{3.3cm}|C{0.73cm}|C{3.63cm}|}
+    \begin{tabular}{|W{0.7cm}|W{1.3cm}|W{2.18cm}|W{3.3cm}|W{0.73cm}|W{3.63cm}|}
       \hline
-      1 bit    & 3 bits        & 6 bits        & 10 bits       & 1 bit & 11 bits\\
+      1 bit    & 2 bits        & 7 bits        & 10 bits       & 1 bit & 11 bits\\
       "1"      & reserved      & channel no    & fine time     & edge  & coarse time\\
       \hline
     \end{tabular}
@@ -75,15 +75,16 @@ Any word starting with the bit "1" indicates a time data word from the TDC in th
 
 6 bits are reserved for indicating the channel number in the TDC (max. 63). The first channel \textendash\ channel "000000" \textendash\ is used to measure the reference time. All TDCs in the system measure the same reference time in this channel, so that they can be all synchronised.
 
-Two time informations are generated for each event detected by each channel. The coarse time information has the granularity of 5~ns (period of the system clock). The range of the coarse time is 10,24~us. The fine time has the range of 5~ns but doesn't have a fixed granularity. The fine time information has to be calibrated using the statistic collected by the individual channel (for details see \ref{sec:FineTime}).
+Two time informations are generated for each event detected by each channel. The coarse time information has the granularity of 5~ns (period of the system clock). The range of the coarse time is 10,24~us. The fine time has the range of 5~ns but doesn't have a fixed granularity. The fine time information has to be calibrated using the statistic collected by the individual channel (for details see \ref{sec:tdcFineTime}).
 
 \subsubsection{DEBUG}
+\label{sec:tdcDebug}
 
 The data format of the \textbf{\textit{debug}} word is shown below:
 
 \begin{table}[h]
   \centering
-    \begin{tabular}{|C{1.275cm}|C{2.125cm}|C{9.7cm}|}
+    \begin{tabular}{|W{1.275cm}|W{2.125cm}|W{9.7cm}|}
       \hline
       3 bits   & 5 bits        & 24 bits\\
       "010"    & debug mode    & debug bits\\
@@ -105,7 +106,7 @@ The data format of the \textbf{\textit{reserved}} word is shown below:
 
 \begin{table}[h]
   \centering
-    \begin{tabular}{|C{1.275cm}|C{12.325cm}|}
+    \begin{tabular}{|W{1.275cm}|W{12.325cm}|}
       \hline
       3 bits   & 29 bits\\
       "011"    & reserved\\
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..483e3c5ba5d1c89f873a2ee96926f6f32aacc68f 100644 (file)
@@ -0,0 +1,123 @@
+A set of control registers are assigned in order to access the basic controls, edit the features and debug information of the TDC. A detailed explanation of the control registers are given in Table \ref{tab:tdcControlReg}.
+
+\begin{table}[htbp]
+  \begin{center}
+    \begin{tabularx}{\textwidth}{|c|l|c|L|}
+      \hline
+      Address  & \multicolumn{1}{c|}{Name}     & Bits  & \multicolumn{1}{c|}{Explanation}\\
+      \hline \hline
+      \multirow{5}{*}{0xc0}    & \multirow{5}{*}{Basic controls}       & 3-0   & Enables different signals to the HPLA* output for debugging with logic analyser (For more details see Table \ref{tab:tdcControlRegBasicLA}).\\
+                               &                                       & 4     & Enables the \textit{Debug Mode}. Different statistics and debug words are sent after every trigger (see \ref{sec:tdcDebug}).\\
+                               &                                       & 11-5  & reserved.\\
+                               &                                       & 12    & Used to select the trigger mode. 1 - with trigger mode; 0 - triggerless mode (For more details see \ref{sec:tdcTrigWin}).\\
+                               &                                       & 31-13 & reserved.\\
+      \hline
+      \multirow{5}{*}{0xc1}    & \multirow{5}{*}{Trigger window}       & 10-0  & Defines the trigger window width before the trigger with granularity of 5~ns. Minimum value is x"000".\\
+                               &                                       & 15-11 & reserved.\\
+                               &                                       & 26-16 & Defines the trigger window width after the trigger with granularity of 5~ns. \textbf{ATTENTION! Minimum value can be set is x"00f".}\\
+                               &                                       & 30-27 & reserved.\\
+                               &                                       & 31    & Enables trigger window feature.\\
+      \hline
+
+      0xc2                     & Channel enable 1                      & 31-0  & Enable signals for the channels 1-32.\\
+      \hline
+      0xc3                     & Channel enable 2                      & 31-0  & Enable signals for the channels 33-64.\\
+      \hline
+    \end{tabularx}
+  \caption{The control registers of the TDC.}
+  \label{tab:tdcControlReg}
+  \end{center}
+\end{table}
+
+\begin{table}[htbp]
+  \begin{center}
+    \begin{tabularx}{\textwidth}{|c|c|L|}
+      \hline
+      Control Bits             & Bit   & \multicolumn{1}{c|}{Explanation}\\
+      \hline \hline
+      \multirow{9}{*}{x"1"}    & 7-0   & Debug word of the TDC readout FSM (see \ref{tab:tdcReadoutFsm})\\
+                               & 8     & REFERENCE\_TIME input\\
+                               & 9     & VALID\_TIMING\_TRG\_IN input\\
+                               & 10    & VALID\_NOTIMING\_TRG\_IN input\\
+                               & 11    & INVALID\_TRG\_IN input\\
+                               & 12    & TRG\_DATA\_VALID\_IN input\\
+                               & 13    & DATA\_WRITE\_OUT output\\
+                               & 14    & DATA\_FINISHED\_OUT output\\
+                               & 15    & TRG\_RELEASE\_OUT output\\
+      \hline
+      \multirow{7}{*}{x"2"}    & 3-0   & Debug word of the TDC reference channel FSM (see \ref{tab:tdcReferenceFsm})\\
+                               & 4     & is set when a trigger is received\\
+                               & 5     & encoder start pulse\\
+                               & 6     & encoder finished pulse\\
+                               & 7     & valid timing trigger pulse from the endpoint\\
+                               & 8     & fifo write pulse\\
+                               & 15-9  & fine time bits between 6-0\\
+      \hline
+      \multirow{4}{*}{x"2"}    & 7-0   & Debug word of the TDC readout FSM (see \ref{tab:tdcReadoutFsm})\\
+                               & 8     & REFERENCE\_TIME input\\
+                               & 9     & DATA\_WRITE\_OUT output\\
+                               & 15-9  & DATA\_OUT output bits 27-22\\
+      \hline
+    \end{tabularx}
+  \caption{HPLA* output bitmap for different debug modes.}
+  \label{tab:tdcControlRegBasicLA}
+  \end{center}  
+\end{table}
+
+
+
+\begin{table}[htbp]
+  \begin{center}
+    \begin{tabularx}{\textwidth}{|c|p{3.5cm}|c|L|}
+      \hline
+      Address  & \multicolumn{1}{c|}{Name}     & Bits  & \multicolumn{1}{c|}{Explanation}\\
+      \hline \hline
+      \multirow{2}{*}{0x80}    & \multirow{2}{3.5cm}{Basic controls}   & 7-0   & Debug word of the TDC readout FSM (see \ref{tab:tdcReadoutFsm})\\
+                               &                                       & 31-8  & reserved\\ \hline
+      0x81                     & Empty channels 1                      & 31-0  & Empty signals of the channels 32-1\\ \hline
+      0x82                     & Empty channels 2                      & 31-0  & Empty signals of the channels 64-33\\ \hline
+      \multirow{4}{*}{0x83}    & \multirow{4}{3.5cm}{Trigger window controls}  & 10-0  & Trigger window width before the trigger with granularity of 5~ns\\
+                               &                                       & 15-11 & reserved\\
+                               &                                       & 26-16 & Trigger window width after the trigger with granularity of 5~ns\\
+                               &                                       & 15-11 & reserved\\ \hline
+      \multirow{2}{*}{0x84}    & \multirow{2}{3.5cm}{Trigger number}   & 23-0  & Number of valid triggers received\\
+                               &                                       & 31-24 & reserved\\ \hline
+      \multirow{2}{*}{0x85}    & \multirow{2}{3.5cm}{Valid timing trigger number}      & 23-0  & Number of valid timing triggers received\\
+                               &                                       & 31-24 & reserved\\ \hline
+      \multirow{2}{*}{0x86}    & \multirow{2}{3.5cm}{Valid NOtiming trigger number}    & 23-0  & Number of valid triggers received which are not timing triggers\\
+                               &                                       & 31-24 & reserved\\ \hline
+      \multirow{2}{*}{0x87}    & \multirow{2}{3.5cm}{Invalid trigger number}   & 23-0  & Number of invalid triggers received\\
+                               &                                       & 31-24 & reserved\\ \hline
+      \multirow{2}{*}{0x88}    & \multirow{2}{3.5cm}{Multi timing trigger number}      & 23-0  & Number of multi timing triggers (triggers received before trigger is released) received\\
+                               &                                       & 31-24 & reserved\\ \hline
+      \multirow{2}{*}{0x89}    & \multirow{2}{3.5cm}{Spurious trigger number}  & 23-0  & Number of spurious triggers received (in case of timing trigger is validated although it was a timing-triggerless trigger)\\
+                               &                                       & 31-24 & reserved\\ \hline
+      \multirow{2}{*}{0x8a}    & \multirow{2}{3.5cm}{Wrong readout number}     & 23-0  & Number of wrong readouts due to spurious triggers\\
+                               &                                       & 31-24 & reserved\\ \hline
+      \multirow{2}{*}{0x8b}    & \multirow{2}{3.5cm}{Spike number}     & 23-0  & Number of spikes (pulses narrower than 40~ns) detected at the timing trigger input\\
+                               &                                       & 31-24 & reserved\\ \hline
+    \end{tabularx}
+  \caption{The status registers of the TDC.}
+  \label{tab:tdcStatusReg}
+  \end{center}
+\end{table}
+
+\begin{table}[htbp]
+  \begin{center}
+    \begin{tabularx}{\textwidth}{|c|p{3.5cm}|c|L|}
+      \hline
+      Address  & \multicolumn{1}{c|}{Name}     & Bits  & \multicolumn{1}{c|}{Explanation}\\
+      \hline \hline
+      \multirow{2}{*}{0x8c}    & \multirow{2}{3.5cm}{Idle time}        & 23-0  & Total time length, that the readout FSM waited in the idle state (with granularity of 10~ns)\\
+                               &                                       & 31-24 & reserved\\ \hline
+      \multirow{2}{*}{0x8d}    & \multirow{2}{3.5cm}{Wait time}        & 23-0  & Total time length, that the readout FSM waited in the wait states (with granularity of 10~ns)\\
+                               &                                       & 31-24 & reserved\\ \hline
+      \multirow{2}{*}{0x8e}    & \multirow{2}{3.5cm}{Total empty channels}     & 23-0  & Number of empty channels since the last reset signal\\
+                               &                                       & 31-24 & reserved\\ \hline
+    \end{tabularx}
+  \caption{The status registers of the TDC. (Continue)}
+  \label{tab:tdcStatusReg}
+  \end{center}
+\end{table}
+
+The status registers of the TDC are explained in Table Table \ref{tab:tdcStatusReg}. In these registers basic status of the TDC readout 
\ No newline at end of file
index 378b1d60104db1985de6bfc274a02fe3b5209bf6..c997ead79ee54e63f4b7e5168e333dfc02434902 100755 (executable)
@@ -40,8 +40,9 @@
             urlcolor=darkblue]{hyperref}
 \usepackage{cite}
 
-\newcolumntype{C}[1]{>{\centering\let\newline\\\arraybackslash\hspace{0pt}}m{#1}}
-% \newcolumntype{C}{>{\centering\arraybackslash}X}
+\newcolumntype{W}[1]{>{\centering\let\newline\\\arraybackslash\hspace{0pt}}m{#1}}
+\newcolumntype{L}{>{\arraybackslash}X}
+\newcolumntype{C}{>{\centering\arraybackslash}X}
 
 \usepackage{fancyhdr}
 \pagestyle{headings}%{fancy}
       \input{TdcDataFormat}
     \subsection{Slow Control Registers}
       \input{TdcSlowControl}
+    \newpage
     \subsection{DAC Programming}
       \input{DacProgramming}