ADC: More nxyter like CLK usage...not tested yet

diff --git a/ADC/trb3_periph_adc.vhd b/ADC/trb3_periph_adc.vhd
index d7c48cb8be25fd4c50c1285ff6150210727c88c9..a1d3b8a848993d702325cbe11e6b868371e84bec 100644 (file)
--- a/ADC/trb3_periph_adc.vhd
+++ b/ADC/trb3_periph_adc.vhd
@@ -225,7 +225,7 @@ begin
     port map(
       CLEAR_IN      => '0',              -- reset input (high active, async)
       CLEAR_N_IN    => '1',              -- reset input (low active, async)
-      CLK_IN        => clk_200_i,        -- raw master clock, NOT from PLL/DLL!
+      CLK_IN        => CLK_PCLK_RIGHT,   -- raw master clock, NOT from PLL/DLL!
       SYSCLK_IN     => clk_100_i,        -- PLL/DLL remastered clock
       PLL_LOCKED_IN => pll_lock,         -- master PLL lock signal (async)
       RESET_IN      => '0',              -- general reset signal (SYSCLK)
@@ -241,7 +241,8 @@ begin
 ---------------------------------------------------------------------------
   THE_MAIN_PLL : pll_in200_out100
     port map(
-      CLK   => CLK_GPLL_RIGHT,
+      CLK   => CLK_PCLK_RIGHT,
+      RESET => '0',
       CLKOP => clk_100_i,
       CLKOK => clk_200_i,
       LOCK  => pll_lock
@@ -262,7 +263,7 @@ begin
       USE_CTC     => c_NO
       )
     port map(
-      CLK                => clk_200_i,
+           CLK                => CLK_PCLK_RIGHT,
       SYSCLK             => clk_100_i,
       RESET              => reset_i,
       CLEAR              => clear_i,