small changes to fix data written to fifo in hub logic. Before, first word was writte...

diff --git a/src/cri_trbnet_dca_bridge.vhd b/src/cri_trbnet_dca_bridge.vhd
index 44f50cb456bdef706cb38923220dbe7b635cf8ec..4a34427851e019b4bd05cdf32320931d0109b984 100644 (file)
--- a/src/cri_trbnet_dca_bridge.vhd
+++ b/src/cri_trbnet_dca_bridge.vhd
@@ -108,11 +108,6 @@ attribute syn_preserve of rx_fifo_wr, rx_fifo_rd, dca_init_dataready, tx_fifo_wr
 
 signal rx_cnt, tx_cnt : std_logic_vector(15 downto 0);
 
--- needed for CRI:
--- FIFOs:
---   * fifo_2kx34x17_wcnt  (no output register)
-
-
 signal rx_data_wr, last_rx_data_wr, rx_data_wr_sync : std_logic;
 signal rx_data_dca, rx_data_dca_sync : std_logic_vector(33 downto 0);
 
@@ -257,29 +252,19 @@ begin
 end process SAVED_HDR_CTR_PROC;
 
 
---TODO: change to synchronous
-rx_fifo_rd  <= '1' when (dca_init_dataready = '1' and dissect_current_state = LOAD_TO_HUB and rx_fifo_q(16) = '0') or 
+rx_fifo_rd  <= '1' when (dca_init_dataready = '1' and dissect_current_state = LOAD_TO_HUB) or 
                         (dca_init_dataready = '1' and dissect_current_state = WAIT_FOR_HUB and DCA_INIT_READ_IN = '1') or
                         (dissect_current_state = GET_DCA_DATA and rx_data_dca_sync(16) = '1') or  -- end of data flag
                         (dissect_current_state = GET_DCA_DATA and rx_data_dca_sync(33) = '1')     -- end of data flag
                         else '0';  -- preload first word
 
-DCA_INIT_PREP_PROC : process
-begin
-  wait until rising_edge(CLK);
-  
-    DCA_INIT_DATA_OUT   <= rx_fifo_q(15 downto 0);
-
-    DCA_INIT_PACKET_NUM_OUT <= packet_num;
-    DCA_INIT_DATAREADY_OUT  <= dca_init_dataready;
-    if (DCA_INIT_READ_IN = '1' and dissect_current_state = LOAD_TO_HUB and rx_fifo_q(16) = '0') or
-       (dissect_current_state = WAIT_FOR_HUB)
-    then
-      dca_init_dataready <= '1';
-    else 
-      dca_init_dataready <= '0';
-    end if;
-end process;
+-- Is not synchd to clock as it is needed from hublogic simulation. Otherwise first word is double written to fifo in hub.
+DCA_INIT_DATAREADY_OUT  <= dca_init_dataready;
+DCA_INIT_PACKET_NUM_OUT <= packet_num;
+DCA_INIT_DATA_OUT       <= rx_fifo_q(15 downto 0);
+dca_init_dataready      <= '1' when (DCA_INIT_READ_IN = '1' and dissect_current_state = LOAD_TO_HUB) or
+                                    (dissect_current_state = WAIT_FOR_HUB)
+                                    else '0';
 
 PACKET_NUM_PROC : process(CLK)
 begin
@@ -295,42 +280,6 @@ begin
 end process PACKET_NUM_PROC;
 
 
--- DCA_INIT_PREP_PROC_NEW : process
--- begin
---   wait until rising_edge(CLK);
---     DCA_INIT_DATA_OUT   <= rx_fifo_q(15 downto 0);
---     rx_fifo_rd  <= '0';
---     
---     if  (dissect_current_state = GET_DCA_DATA and rx_data_dca_sync(16) = '1') or  -- end of data flag
---         (dissect_current_state = GET_DCA_DATA and rx_data_dca_sync(33) = '1')
---     then
---       rx_fifo_rd  <= '1';
---       
---     elsif (dca_init_dataready = '1' and dissect_current_state = LOAD_TO_HUB and rx_fifo_q(16) = '0') or 
---           (dca_init_dataready = '1' and dissect_current_state = WAIT_FOR_HUB and DCA_INIT_READ_IN = '1')
---     then
---       rx_fifo_rd  <= '1';
---     end if;
--- 
---     if (DCA_INIT_READ_IN = '1' and dissect_current_state = LOAD_TO_HUB and rx_fifo_q(16) = '0') or
---        (dissect_current_state = WAIT_FOR_HUB) -- for preloaded bits
---     then
---       dca_init_dataready <= '1';
---     else 
---       dca_init_dataready <= '0';
---     end if;
---     
---     if (dissect_current_state = IDLE) then
---       packet_num <= "100";
---     elsif (rx_fifo_rd = '1' and packet_num = "100") then
---       packet_num <= "000";
---     elsif (rx_fifo_rd = '1' and packet_num /= "100") then
---       packet_num <= packet_num + "1";
---     end if;
--- end process;
--- DCA_INIT_DATAREADY_OUT <= dca_init_dataready;
-
-
 tf_4k_gen : if SLOWCTRL_BUFFER_SIZE = 1 generate
   transmit_fifo : entity work.fifo_4kx16x32_wcnt
     port map (
@@ -482,27 +431,6 @@ begin
 end process TOO_MUCH_DATA_PROC;
 
 
-
--- PS_RESPONSE_SYNC : process(CLK)
--- begin
---   if rising_edge(CLK) then
---     if (too_much_data = '0') then
---       if (dissect_current_state = WAIT_FOR_LOAD or dissect_current_state = LOAD_FRAME or dissect_current_state = CLEANUP) then
---         WB_RESPONSE_READY <= '1';
---       else
---         WB_RESPONSE_READY <= '0';
---       end if;
---     end if;
--- 
--- --     if (dissect_current_state = IDLE or dissect_current_state = WAIT_FOR_RESPONSE) then
--- --       PS_BUSY_OUT <= '0';
--- --     else
--- --       PS_BUSY_OUT <= '1';
--- --     end if;
---   end if;   
--- end process PS_RESPONSE_SYNC;
-
-
 ---------------------------------------------------------------------
 -- State machine controlling the data handling with hub and DCA
 ---------------------------------------------------------------------