--- /dev/null
+Slave bus usage\r
+===============\r
+\r
+0x8000 - 0x8001 : test register\r
+\r
+0x8040 - 0x8040 X: I2C master for APV slow control\r
+\r
+0xa000 - 0xa07f : pedestal memory APV0\r
+0xa080 - 0xa0ff : pedestal memory APV1\r
+0xa100 - 0xa17f : pedestal memory APV2\r
+0xa180 - 0xa1ff : pedestal memory APV3\r
+0xa200 - 0xa27f : pedestal memory APV4\r
+0xa280 - 0xa2ff : pedestal memory APV5\r
+0xa300 - 0xa37f : pedestal memory APV6\r
+0xa380 - 0xa3ff : pedestal memory APV7\r
+0xa400 - 0xa47f : pedestal memory APV8\r
+0xa480 - 0xa4ff : pedestal memory APV9\r
+0xa500 - 0xa57f : pedestal memory APV10\r
+0xa580 - 0xa5ff : pedestal memory APV11\r
+0xa600 - 0xa67f : pedestal memory APV12\r
+0xa680 - 0xa6ff : pedestal memory APV13\r
+0xa700 - 0xa77f : pedestal memory APV14\r
+0xa780 - 0xa7ff : pedestal memory APV15\r
+\r
+0xa800 - 0xa87f : threshold memory APV0\r
+0xa880 - 0xa8ff : threshold memory APV1\r
+0xa900 - 0xa97f : threshold memory APV2\r
+0xa980 - 0xa9ff : threshold memory APV3\r
+0xaa00 - 0xaa7f : threshold memory APV4\r
+0xaa80 - 0xaaff : threshold memory APV5\r
+0xab00 - 0xab7f : threshold memory APV6\r
+0xab80 - 0xabff : threshold memory APV7\r
+0xac00 - 0xac7f : threshold memory APV8\r
+0xac80 - 0xacff : threshold memory APV9\r
+0xad00 - 0xad7f : threshold memory APV10\r
+0xad80 - 0xadff : threshold memory APV11\r
+0xae00 - 0xae7f : threshold memory APV12\r
+0xae80 - 0xaeff : threshold memory APV13\r
+0xaf00 - 0xaf7f : threshold memory APV14\r
+0xaf80 - 0xafff : threshold memory APV15\r
+\r
+0xb000 - 0xb00f X: APV control and status\r
+\r
+0xb010 - 0xb010 X: ADC level settings\r
+\r
+0xb020 - 0xb020 X: trigger settings\r
+\r
+0xb030 - 0xb030 X: PLL settings\r
+\r
+0xc000 - 0xc03f X: 1Wire master for APV and backplane\r
+\r
+0xd000 - 0xd001 X: SPI master for FlashROM\r
+\r
+0xd010 - 0xd010 X: ADC0 control and SPI\r
+\r
+0xd020 - 0xd020 X: ADC1 control and SPI\r
+\r
+0xd100 - 0xd03f X: SPI data memory (FlashROM)\r
+\r
+0xf000 - 0xf3ff : ADC 0 snooper\r
+\r
+0xf400 - 0xf7ff : ADC 1 snooper\r
+\r
+\r
+==========================================================================\r
+== Detailed description\r
+==========================================================================\r
+\r
+\r
+#################################################################################\r
+# #\r
+# SPI master for ADC slow control, ADC configuration bits, APV reset #\r
+# #\r
+#################################################################################\r
+\r
+0xd010 - 0xd010 : ADC0 control and SPI\r
+0xd020 - 0xd020 : ADC0 control and SPI\r
+---------------------------------------\r
+\r
+D[31:24] SPI command\r
+D[23:12] ADC channel 4 current data for testing\r
+D[11:9] reserved\r
+D[8] ADC PLL status 0 -> bad, 1 -> locked\r
+D[7:4] ADC input delay (0x6 is standard)\r
+D[3] SPI start 0 -> wait, 1 -> start\r
+D[2] APV reset 0 -> normal, 1 -> reset\r
+D[1] ADC power down 0 -> normal, 1 -> powerdown\r
+D[0] ADC reset 0 -> normal, 1 -> reset\r
+\r
+This register is 32bit wide with full read/write access. \r
+It controls a simple (one byte only) SPI master for configuring the ADC via SPI.\r
+Besides it allows to reset the ADC, power it down and also reset the connected \r
+APVs (eight modules).\r
+\r
+Take care not to change bits unintentionally when working with this register.\r
+A read-modify-write sequence is mandatory.\r
+\r
+\r
+SPI access to ADC is handled as following:\r
+\r
+(1) be sure that SPI start bit D[16] is zero\r
+(2) read register and set D[31:24] to the command to be sent\r
+(3) write back new value with SPI start bit set\r
+(4) clear the SPI start bit\r
+\r
+The SPI hardware access is 25MHz based and will be over before next TRBnet access\r
+to this register is possible. This SPI master can only transfer command to the ADC, \r
+and not read back (due to ADC constraints).\r
+\r
+\r
+Reset value of register is 0x00000060. \r
+\r
+#################################################################################\r
+# #\r
+# APV control and status register #\r
+# #\r
+#################################################################################\r
+\r
+0xb000 - 0xb00f : APV control and status\r
+-----------------------------------------\r
+\r
+D[31] buffer good 1 -> APV switched on and sync'ed\r
+D[30] buffer broken 1 -> APV switched on and off sync\r
+D[29] buffer ignore 1 -> APV not used\r
+D[28:24] number of events in buffer\r
+D[23:20] reserved\r
+D[19:16] hardware APV number before mapping([15:8] -> ADC1, [7:0] -> ADC0)\r
+D[15:1] reserved\r
+D[0] APV on 0 -> off, 1 -> on\r
+\r
+This register is divided into read only bits (D[31:16]) and read/write bits (D[15:0]).\r
+\r
+APV on bit (D[0]) is on by default.\r
+D[31] (buffer good) will only be set if the APV is switched on and a SYNC trigger has\r
+been sent.\r
+To activate an APV it is mandatory to set APV on bit (D[0]) and send a SYNC trigger.\r
+\r
+\r
+Reset value of register is 0xZZZZ0001 (Z depends on APV connections).\r
+\r
+#################################################################################\r
+# #\r
+# configuration register for ADC levels (bit recognition) #\r
+# #\r
+#################################################################################\r
+\r
+0xb010 - 0xb010 : ADC level settings\r
+-------------------------------------\r
+\r
+D[31:24] bit high D[11:4] setting, D[3:0] is fixed to 0x0\r
+D[23:16] bit low D[11:4] setting, D[3:0] is fixed to 0x0\r
+D[15:8] flat high D[11:4] setting, D[3:0] is fixed to 0x0\r
+D[7:0] flat low D[11:4] setting, D[3:0] is fixed to 0x0\r
+\r
+This register is 32bit wide with full read/write access. \r
+It is used to configure the APV digital header reconstruction. The ADCs use 12bit,\r
+with 0x000 as lowest value and 0xfff as highest value. There is no OutOfRange, UnderFlow \r
+or OverFlow bit in the ADC.\r
+"Flat low" and "Flat high" set the recognition limits for a missing ADC module: in this case\r
+the ADC will deliver a flat line around 0x800.\r
+"Bit low" is the upper limit for recognizing an ADC value as digital low bit.\r
+"Bit high" is the lower limit for recognizing an ADC value as digital high bit.\r
+\r
+This register must be initialized correctly before sending any triggers to the APVs.\r
+\r
+Recommended setting is 0xd0208878 at time of this writing, giving\r
+Flat Low = 0x780\r
+Flat High = 0x880\r
+Bit Low = 0x200\r
+Bit High = 0xd00\r
+\r
+\r
+Reset value of register is 0x00000000.\r
+\r
+#################################################################################\r
+# #\r
+# configuration register for triggers #\r
+# #\r
+#################################################################################\r
+\r
+0xb020 - 0xb020 : trigger settings\r
+-----------------------------------\r
+\r
+D[31:28] TRG3 number of triggers\r
+D[27:24] TRG3 delay\r
+D[23:20] TRG2 number of triggers\r
+D[19:16] TRG2 delay\r
+D[15:12] TRG1 number of triggers\r
+D[11:8] TRG1 delay\r
+D[7:4] TRG0 number of triggers\r
+D[3:0] TRG0 delay\r
+\r
+This register is 32bit wide with full read/write access. \r
+It sets up the APV readout functionality (per external trigger input)\r
+\r
+For all four trigger inputs (external and slow control) the number of APV readout \r
+triggers to be sent as well as the number of clock cycles between APV readout \r
+triggers can be set up.\r
+\r
+It is not recommended to take more than 8 APV readout triggers per external trigger.\r
+\r
+Take care: the data format may change with setting up more than one APV readout trigger.\r
+\r
+\r
+Reset value of register is 0x10101010.\r
+\r
+\r
+#################################################################################\r
+# #\r
+# configuration register for PLLs #\r
+# #\r
+#################################################################################\r
+\r
+0xb030 - 0xb030 : PLL settings\r
+-------------------------------\r
+\r
+D[31] 100MHZ DLL locked 0 -> bad, 1 -> locked\r
+D[30] 40MHZ PLL locked 0 -> bad, 1 -> locked\r
+D[29] ADC1 PLL locked 0 -> bad, 1 -> locked\r
+D[28] ADC0 PLL locked 0 -> bad, 1 -> locked\r
+D[27:24] reserved\r
+D[23] reserved\r
+D[22:20] sector ID as given by backplane switch\r
+D[19] reserved\r
+D[18:16] module ID as given by backplane switch\r
+D[15:8] external trigger setup\r
+-> D[15] EXT_IN[3] active\r
+-> D[14] EXT_IN[2] active\r
+-> D[13] EXT_IN[1] active\r
+-> D[12] EXT_IN[0] active\r
+-> D[11] invert external trigger 3\r
+-> D[10] invert external trigger 2\r
+-> D[9] invert external trigger 1\r
+-> D[8] invert external trigger 0\r
+D[7] 40MHz PLL reset\r
+D[6] ADC1 PLL reset\r
+D[5] ADC0 PLL reset\r
+D[4] reserved\r
+D[3:0] 40MHz clock phase setting\r
+\r
+This register is divided into read only bits (D[31:16]) and read/write bits (D[15:0]).\r
+It configures the ADCM hardware resource: setup of FPGA internal PLLs, clock phase between\r
+ADC and APV 40MHz clock and external trigger inputs.\r
+\r
+PLLs must not be in reset during normal operation.\r
+Please note that after reset the PLLs may take some 100ms to be stable again.\r
+\r
+The clock phase shift between ADC and APV clock must be adjusted to accommodate \r
+for delays on PCB and cables. It is mandatory to set this correctly to have the\r
+ADCs sampling the analog signal returning from APVs at the right point in time.\r
+\r
+To activate external trigger inputs set the corresponding bit to 1.\r
+If connected correctly to the CTS no signal inversion is needed.\r
+\r
+Reset value of register is 0x00000000.\r
+\r
+#################################################################################\r
+# #\r
+# 1Wire master for APVs and backplane #\r
+# #\r
+#################################################################################\r
+\r
+0xc000 - 0xc03f : 1Wire master for APV and backplane\r
+-----------------------------------------------------\r
+\r
+Writing the offset 0xc000 with any value starts one full 1Wire action.\r
+This takes about 1.0s - there is no busy locking for reading the memory.\r
+\r
+offset 0: lower 32bit of serial number \r
+offset 1: upper 32bit of serial number\r
+offset 2: D[15] 0 -> no 1Wire found, 1 -> 1Wire found\r
+ D[11:0] temperature of 1Wire IC\r
+offset 3: reserved\r
+\r
+\r
+#################################################################################\r
+# #\r
+# SPI master for FlashROM access #\r
+# #\r
+#################################################################################\r
+\r
+0xd000 - 0xd001 : SPI master for FlashROM\r
+------------------------------------------\r
+\r
+0xd000: SPI control register \r
+ \r
+D[31:24] SPI command\r
+D[23:16] address byte high (A[23:16])\r
+D[15:8] address byte mid (A[15:8])\r
+D[7:0] address byte low (A[7:0])\r
+\r
+Full read/write access; writing this register starts the SPI hardware access.\r
+This register is busy locked.\r
+\r
+Reset value of register is 0x00000000.\r
+\r
+\r
+0xd001: SPI status register\r
+\r
+D[31:24] number of data words to be transfered (0x00 -> 1, 0xff -> 256)\r
+D[23:8] reserved\r
+D[7:0] debug information (state machine bits)\r
+\r
+This register is divided into read only bits (D[7:0]) and read/write bits (D[31:24]).\r
+\r
+Reset value of register is 0x00000000.\r
+\r
+\r
+0xd100 - 0xd03f : SPI data memory (FlashROM)\r
+---------------------------------------------\r
+\r
+Memory bank for read / write data in SPI transfer. This memory block is not busy locked.\r
+\r
+D[7:0] first byte\r
+D[15:8] second byte\r
+D[23:16] third byte\r
+D[31:24] fourth byte\r
+....\r
+\r
+\r
+#################################################################################\r
+# #\r
+# I2C master for APV slowcontrol access #\r
+# #\r
+#################################################################################\r
+\r
+0x8040 - 0x8040 : I2C master for APV slow control\r
+--------------------------------------------------\r
+\r
+This I2C master is tailor made for APV25S1 ASICs. \r
+\r
+ write access \r
+D[31] I2C start bit \r
+D[30] I2C ???\r
+D[29:24] I2C speed\r
+D[23:16] I2C address\r
+D[15:8] I2C command\r
+D[7:0] I2C write data\r
+\r
+ read access\r
+D[31:24] status bits \r
+-> D[31] "running" or "busy" bit\r
+-> D[30] "access done" bit\r
+-> D[29] "e_ranak" -> I2C repeated address NAK\r
+-> D[28] "e_rsf" -> error generating repeated start condition\r
+-> D[27] "e_dnak" -> I2C data NAK\r
+-> D[26] "e_cnak" -> I2C command NAK\r
+-> D[25] "e_anak" -> I2C address NAK\r
+-> D[24] "e_sf" -> error generating start condition \r
+D[23:21] reserved\r
+D[20:16] debug\r
+D[15:8] reserved\r
+D[7:0] I2C read data\r
+\r
+\r
--- /dev/null
+Backplane 0\r
+===========\r
+\r
+ADC0/0 0 0/6 3 0xb000 0x20030001\r
+ADC0/1 1 0/7 5 0xb001 0x20050001\r
+ADC0/2 2 0/0 10 0xb002 0x200a0001\r
+ADC0/3 3 0/2 12 0xb003 0x200c0001\r
+ADC0/4 4 0/1 9 0xb004 0x20090001\r
+ADC0/5 5 0/3 7 0xb005 0x20070001\r
+ADC0/6 6 0/5 0 0xb006 0x20000001\r
+ADC0/7 7 -/- -- 0xb007 0x200f0001\r
+ \r
+ADC1/0 8 1/6 4 0xb008 0x20040001\r
+ADC1/1 9 1/7 6 0xb009 0x20060001\r
+ADC1/2 10 1/1 11 0xb00a 0x200b0001\r
+ADC1/3 11 1/0 8 0xb00b 0x20080001\r
+ADC1/4 12 1/3 14 0xb00c 0x200e0001\r
+ADC1/5 13 1/2 13 0xb00d 0x200d0001\r
+ADC1/6 14 1/5 2 0xb00e 0x20020001\r
+ADC1/7 15 1/4 1 0xb00f 0x20010001\r
+\r
+realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15\r
+mapAPV 3 5 10 12 9 7 0 - 4 6 11 8 14 13 2 1\r
+\r
+Backplane 1\r
+==========\r
+\r
+ADC0/0 0 0/6 12 0xb000 0x200c0001\r
+ADC0/1 1 0/7 11 0xb001 0x200b0001\r
+ADC0/2 2 0/0 10 0xb002 0x200a0001\r
+ADC0/3 3 0/2 9 0xb003 0x20090001\r
+ADC0/4 4 0/1 8 0xb004 0x20080001\r
+ADC0/5 5 0/3 7 0xb005 0x20070001\r
+ADC0/6 6 0/5 13 0xb006 0x200d0001\r
+ADC0/7 7 0/4 14 0xb007 0x200e0001\r
+ \r
+ADC1/0 8 1/6 3 0xb008 0x20030001\r
+ADC1/1 9 1/7 2 0xb009 0x20020001\r
+ADC1/2 10 1/1 1 0xb00a 0x20010001\r
+ADC1/3 11 1/0 0 0xb00b 0x20000001\r
+ADC1/4 12 1/3 6 0xb00c 0x20060001\r
+ADC1/5 13 1/2 5 0xb00d 0x20050001\r
+ADC1/6 14 1/5 4 0xb00e 0x20040001\r
+ADC1/7 15 -/- -- 0xb00f 0x200f0001\r
+\r
+realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15\r
+mapAPV 12 11 10 9 8 7 13 14 3 2 1 0 6 5 4 -\r
+\r
+Backplane 2\r
+===========\r
+\r
+ADC0/0 0 -/- -- 0xb000 0x200f0001 \r
+ADC0/1 1 0/7 4 0xb001 0x20040001\r
+ADC0/2 2 0/0 5 0xb002 0x20050001\r
+ADC0/3 3 0/2 6 0xb003 0x20060001\r
+ADC0/4 4 0/1 0 0xb004 0x20000001\r
+ADC0/5 5 0/3 1 0xb005 0x20010001\r
+ADC0/6 6 0/5 2 0xb006 0x20020001\r
+ADC0/7 7 0/4 3 0xb007 0x20030001\r
+ \r
+ADC1/0 8 1/6 14 0xb008 0x200e0001\r
+ADC1/1 9 1/7 13 0xb009 0x200d0001\r
+ADC1/2 10 1/1 7 0xb00a 0x20070001\r
+ADC1/3 11 1/0 8 0xb00b 0x20080001\r
+ADC1/4 12 1/3 9 0xb00c 0x20090001\r
+ADC1/5 13 1/2 10 0xb00d 0x200a0001\r
+ADC1/6 14 1/5 11 0xb00e 0x200b0001\r
+ADC1/7 15 1/4 12 0xb00f 0x200c0001\r
+\r
+realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15\r
+mapAPV - 4 5 6 0 1 2 3 14 13 7 8 9 10 11 12\r
+\r
+Backplane 3\r
+===========\r
+\r
+ADC0/0 0 0/6 10 0xb000 0x200a0001\r
+ADC0/1 1 0/7 9 0xb001 0x20090001\r
+ADC0/2 2 0/0 8 0xb002 0x20080001\r
+ADC0/3 3 0/2 7 0xb003 0x20070001\r
+ADC0/4 4 0/1 6 0xb004 0x20060001\r
+ADC0/5 5 0/3 5 0xb005 0x20050001\r
+ADC0/6 6 0/5 12 0xb006 0x200c0001\r
+ADC0/7 7 0/4 11 0xb007 0x200b0001\r
+ \r
+ADC1/0 8 1/6 4 0xb008 0x20040001\r
+ADC1/1 9 1/7 3 0xb009 0x20030001\r
+ADC1/2 10 1/1 0 0xb00a 0x20000001\r
+ADC1/3 11 1/0 2 0xb00b 0x20020001\r
+ADC1/4 12 1/3 1 0xb00c 0x20010001\r
+ADC1/5 13 -/- -- 0xb00d 0x200f0001\r
+ADC1/6 14 1/5 13 0xb00e 0x200d0001\r
+ADC1/7 15 1/4 14 0xb00f 0x200e0001\r
+\r
+realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15\r
+mapAPV 10 9 8 7 6 5 12 11 4 3 0 2 1 - 13 14\r
+\r
+Backplane 4\r
+===========\r
+\r
+ADC0/0 0 0/6 14 0xb000 0x200e0001\r
+ADC0/1 1 0/7 13 0xb001 0x200d0001\r
+ADC0/2 2 -/- -- 0xb002 0x200f0001\r
+ADC0/3 3 0/2 1 0xb003 0x20010001\r
+ADC0/4 4 0/1 2 0xb004 0x20020001\r
+ADC0/5 5 0/3 0 0xb005 0x20000001\r
+ADC0/6 6 0/5 3 0xb006 0x20030001\r
+ADC0/7 7 0/4 4 0xb007 0x20040001\r
+ \r
+ADC1/0 8 1/6 11 0xb008 0x200b0001\r
+ADC1/1 9 1/7 12 0xb009 0x200c0001\r
+ADC1/2 10 1/1 5 0xb00a 0x20050001\r
+ADC1/3 11 1/0 6 0xb00b 0x20060001\r
+ADC1/4 12 1/3 7 0xb00c 0x20070001\r
+ADC1/5 13 1/2 8 0xb00d 0x20080001\r
+ADC1/6 14 1/5 9 0xb00e 0x20090001\r
+ADC1/7 15 1/4 10 0xb00f 0x200a0001\r
+\r
+realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15\r
+mapAPV 14 13 - 1 2 0 3 4 11 12 5 6 7 8 9 10\r
--- /dev/null
+[Device]\r
+Family=latticeecp2m\r
+PartType=LFE2M100E\r
+PartName=LFE2M100E-6F900C\r
+SpeedGrade=-6\r
+Package=FPBGA900\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=Distributed_ROM\r
+CoreRevision=2.4\r
+ModuleName=adc_apv_map_mem\r
+SourceFormat=VHDL\r
+ParameterFileVersion=1.0\r
+Date=11/04/2009\r
+Time=16:11:12\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+Addresses=128\r
+Data=4\r
+LUT=0\r
+MemFile=i:/vhdl_pro/adcmv3/src/adc_apv_mapping.mem\r
+MemFormat=orca\r
--- /dev/null
+SCUBA, Version ispLever_v72_SP2_Build (23)
+Wed Nov 04 16:11:12 2009
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp. All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
+Copyright (c) 2001 Agere Systems All rights reserved.
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
+
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n adc_apv_map_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 7 -num_words 128 -data_width 4 -outdata UNREGISTERED -memfile i:/vhdl_pro/adcmv3/src/adc_apv_mapping.mem -memformat orca -e
+ Circuit name : adc_apv_map_mem
+ Module type : rom
+ Module Version : 2.4
+ Address width : 7
+ Ports :
+ Inputs : Address[6:0]
+ Outputs : Q[3:0]
+ I/O buffer : not inserted
+ Memory file : i:/vhdl_pro/adcmv3/src/adc_apv_mapping.mem
+ EDIF output : suppressed
+ VHDL output : adc_apv_map_mem.vhd
+ VHDL template : adc_apv_map_mem_tmpl.vhd
+ VHDL testbench : tb_adc_apv_map_mem_tmpl.vhd
+ VHDL purpose : for synthesis and simulation
+ Bus notation : big endian
+ Report output : adc_apv_map_mem.srp
+ Element Usage :
+ ROM128X1 : 4
+ Estimated Resource Usage:
+ LUT : 16
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23)
+-- Module Version: 2.4
+--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type rom -addr_width 7 -num_rows 128 -data_width 4 -outdata UNREGISTERED -memfile i:/vhdl_pro/adcmv3/src/adc_apv_mapping.mem -memformat orca -e
+
+-- Wed Nov 04 16:11:12 2009
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity adc_apv_map_mem is
+ port (
+ Address: in std_logic_vector(6 downto 0);
+ Q: out std_logic_vector(3 downto 0));
+end adc_apv_map_mem;
+
+architecture Structure of adc_apv_map_mem is
+
+ -- local component declarations
+ component ROM128X1
+ -- synopsys translate_off
+ generic (INITVAL : in String);
+ -- synopsys translate_on
+ port (AD6: in std_logic; AD5: in std_logic; AD4: in std_logic;
+ AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ attribute initval : string;
+ attribute initval of mem_0_3 : label is "0xFF00FF00FF00E307E0C7FB0180DF3C9C";
+ attribute initval of mem_0_2 : label is "0xF0F0F0F0F0F01E87E178870FF0E133AA";
+ attribute initval of mem_0_1 : label is "0xCCCCCCCCCCCC9955AA9965C993A656A5";
+ attribute initval of mem_0_0 : label is "0xAAAAAAAAAAAA554E72AA56A5A56AA4B3";
+
+begin
+ -- component instantiation statements
+ mem_0_3: ROM128X1
+ -- synopsys translate_off
+ generic map (initval=> "0xFF00FF00FF00E307E0C7FB0180DF3C9C")
+ -- synopsys translate_on
+ port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4),
+ AD3=>Address(3), AD2=>Address(2), AD1=>Address(1),
+ AD0=>Address(0), DO0=>Q(3));
+
+ mem_0_2: ROM128X1
+ -- synopsys translate_off
+ generic map (initval=> "0xF0F0F0F0F0F01E87E178870FF0E133AA")
+ -- synopsys translate_on
+ port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4),
+ AD3=>Address(3), AD2=>Address(2), AD1=>Address(1),
+ AD0=>Address(0), DO0=>Q(2));
+
+ mem_0_1: ROM128X1
+ -- synopsys translate_off
+ generic map (initval=> "0xCCCCCCCCCCCC9955AA9965C993A656A5")
+ -- synopsys translate_on
+ port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4),
+ AD3=>Address(3), AD2=>Address(2), AD1=>Address(1),
+ AD0=>Address(0), DO0=>Q(1));
+
+ mem_0_0: ROM128X1
+ -- synopsys translate_off
+ generic map (initval=> "0xAAAAAAAAAAAA554E72AA56A5A56AA4B3")
+ -- synopsys translate_on
+ port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4),
+ AD3=>Address(3), AD2=>Address(2), AD1=>Address(1),
+ AD0=>Address(0), DO0=>Q(0));
+
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of adc_apv_map_mem is
+ for Structure
+ for all:ROM128X1 use entity ecp2m.ROM128X1(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+Starting process: \r
+\r
+SCUBA, Version ispLever_v72_SP2_Build (23)\r
+Wed Nov 04 16:11:12 2009\r
+\r
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
+Copyright (c) 1995 AT&T Corp. All rights reserved.\r
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
+Copyright (c) 2001 Agere Systems All rights reserved.\r
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
+\r
+BEGIN SCUBA Module Synthesis\r
+\r
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n adc_apv_map_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 7 -num_words 128 -data_width 4 -outdata UNREGISTERED -memfile i:/vhdl_pro/adcmv3/src/adc_apv_mapping.mem -memformat orca -e \r
+ Circuit name : adc_apv_map_mem\r
+ Module type : rom\r
+ Module Version : 2.4\r
+ Address width : 7\r
+ Data width : 4\r
+ Ports : \r
+ Inputs : Address[6:0]\r
+ Outputs : Q[3:0]\r
+ I/O buffer : not inserted\r
+ Memory file : i:/vhdl_pro/adcmv3/src/adc_apv_mapping.mem\r
+ EDIF output : suppressed\r
+ VHDL output : adc_apv_map_mem.vhd\r
+ VHDL template : adc_apv_map_mem_tmpl.vhd\r
+ VHDL testbench : tb_adc_apv_map_mem_tmpl.vhd\r
+ VHDL purpose : for synthesis and simulation\r
+ Bus notation : big endian\r
+ Report output : adc_apv_map_mem.srp\r
+ Estimated Resource Usage:\r
+ LUT : 16\r
+\r
+END SCUBA Module Synthesis\r
+\r
+File: ..\src\adc_apv_map_mem.lpc created.\r
+\r
+\r
+End process: completed successfully.\r
+\r
+\r
+Total Warnings: 0\r
+\r
+Total Errors: 0\r
+\r
+\r
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23)
+-- Module Version: 2.4
+-- Wed Nov 04 16:11:12 2009
+
+-- parameterized module component declaration
+component adc_apv_map_mem
+ port (Address: in std_logic_vector(6 downto 0);
+ Q: out std_logic_vector(3 downto 0));
+end component;
+
+-- parameterized module component instance
+__ : adc_apv_map_mem
+ port map (Address(6 downto 0)=>__, Q(3 downto 0)=>__);
--- /dev/null
+#Format=Address-Hex\r
+#Depth=128\r
+#DataWidth=4\r
+#AddrRadix=3\r
+#DataRadix=3\r
+\r
+# Backplane 0\r
+# realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15\r
+# mapAPV 3 5 10 12 9 7 0 - 4 6 11 8 14 13 2 1\r
+00: 3\r
+01: 5\r
+02: a\r
+03: c\r
+04: 9\r
+05: 7\r
+06: 0\r
+07: f\r
+08: 4\r
+09: 6\r
+0a: b\r
+0b: 8\r
+0c: e\r
+0d: d\r
+0e: 2\r
+0f: 1\r
+# Backplane 1\r
+# realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15\r
+# mapAPV 12 11 10 9 8 7 13 14 3 2 1 0 6 5 4 -\r
+10: c\r
+11: b\r
+12: a\r
+13: 9\r
+14: 8\r
+15: 7\r
+16: d\r
+17: e\r
+18: 3\r
+19: 2\r
+1a: 1\r
+1b: 0\r
+1c: 6\r
+1d: 5\r
+1e: 4\r
+1f: f\r
+# Backplane 2\r
+# realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15\r
+# mapAPV - 4 5 6 0 1 2 3 14 13 7 8 9 10 11 12\r
+20: f \r
+21: 4\r
+22: 5\r
+23: 6\r
+24: 0\r
+25: 1\r
+26: 2\r
+27: 3\r
+28: e\r
+29: d\r
+2a: 7\r
+2b: 8\r
+2c: 9\r
+2d: a\r
+2e: b\r
+2f: c\r
+# Backplane 3\r
+# realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15\r
+# mapAPV 10 9 8 7 6 5 12 11 4 3 0 2 1 - 13 14\r
+30: a\r
+31: 9\r
+32: 8\r
+33: 7\r
+34: 6\r
+35: 5\r
+36: c\r
+37: b\r
+38: 4\r
+39: 3\r
+3a: 0\r
+3b: 2\r
+3c: 1\r
+3d: f\r
+3e: d\r
+3f: e\r
+# Backplane 4\r
+# realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15\r
+# mapAPV 14 13 - 1 2 0 3 4 11 12 5 6 7 8 9 10\r
+40: e\r
+41: d\r
+42: f\r
+43: 1\r
+44: 2\r
+45: 0\r
+46: 3\r
+47: 4\r
+48: b\r
+49: c\r
+4a: 5\r
+4b: 6\r
+4c: 7\r
+4d: 8\r
+4e: 9\r
+4f: a\r
+# unused (5) => 1:1\r
+50: 0\r
+51: 1\r
+52: 2\r
+53: 3\r
+54: 4\r
+55: 5\r
+56: 6\r
+57: 7\r
+58: 8\r
+59: 9\r
+5a: a\r
+5b: b\r
+5c: c\r
+5d: d\r
+5e: e\r
+5f: f\r
+# unused (6) => 1:1\r
+60: 0\r
+61: 1\r
+62: 2\r
+63: 3\r
+64: 4\r
+65: 5\r
+66: 6\r
+67: 7\r
+68: 8\r
+69: 9\r
+6a: a\r
+6b: b\r
+6c: c\r
+6d: d\r
+6e: e\r
+6f: f\r
+# unused (7) => 1:1\r
+70: 0\r
+71: 1\r
+72: 2\r
+73: 3\r
+74: 4\r
+75: 5\r
+76: 6\r
+77: 7\r
+78: 8\r
+79: 9\r
+7a: a\r
+7b: b\r
+7c: c\r
+7d: d\r
+7e: e\r
+7f: f\r
--- /dev/null
+[Device]\r
+Family=latticeecp2m\r
+PartType=LFE2M100E\r
+PartName=LFE2M100E-6F900C\r
+SpeedGrade=-6\r
+Package=FPBGA900\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=DDR_GENERIC\r
+CoreRevision=3.6\r
+ModuleName=adc_ch_in\r
+SourceFormat=VHDL\r
+ParameterFileVersion=1.0\r
+Date=04/24/2009\r
+Time=11:41:10\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+mode=Input\r
+width=1\r
+reg=DDR\r
+gear=1x\r
+rst=Edge\r
+del=Dynamic\r
+cdel=0\r
+fdel=0\r
+cdiv=1\r
+clk1x=0\r
+clk2x=0\r
+ail=0\r
+step=2\r
+ckedge=1\r
+swap=Off\r
+bf=Off\r
+AilAW=400\r
+val=0\r
--- /dev/null
+SCUBA, Version ispLever_v72_PROD_Build (44)
+Fri Apr 24 11:41:10 2009
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp. All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
+Copyright (c) 2001 Agere Systems All rights reserved.
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
+
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n adc_ch_in -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type iol -mode in -width 1 -gear 1 -del 16 -e
+ Circuit name : adc_ch_in
+ Module type : iol
+ Module Version : 3.6
+ Ports :
+ Inputs : Del[3:0], ECLK, SCLK, Rst, Data[0:0]
+ Outputs : Q[1:0]
+ I/O buffer : not inserted
+ EDIF output : suppressed
+ VHDL output : adc_ch_in.vhd
+ VHDL template : adc_ch_in_tmpl.vhd
+ VHDL purpose : for synthesis and simulation
+ Bus notation : big endian
+ Report output : adc_ch_in.srp
+ Element Usage :
+ IB : 1
+ IDDRFXA : 1
+ DELAYB : 1
+ Estimated Resource Usage:
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v72_SP1_Build (24)
+-- Module Version: 3.6
+--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n adc_ch_in -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type iol -mode in -width 1 -gear 1 -del 16 -e
+
+-- Fri Apr 24 11:41:10 2009
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity adc_ch_in is
+ port (
+ Del: in std_logic_vector(3 downto 0);
+ ECLK: in std_logic;
+ SCLK: in std_logic;
+ Rst: in std_logic;
+ Data: in std_logic_vector(0 downto 0);
+ Q: out std_logic_vector(1 downto 0));
+ attribute dont_touch : string;
+ attribute dont_touch of adc_ch_in : entity is "true";
+end adc_ch_in;
+
+architecture Structure of adc_ch_in is
+
+ -- internal signal declarations
+ signal scuba_vhi: std_logic;
+ signal Data_t0: std_logic;
+ signal buf_Data0: std_logic;
+
+ -- local component declarations
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component IB
+ port (I: in std_logic; O: out std_logic);
+ end component;
+ component IDDRFXA
+ port (D: in std_logic; CLK1: in std_logic; CLK2: in std_logic;
+ CE: in std_logic; RST: in std_logic; QA: out std_logic;
+ QB: out std_logic);
+ end component;
+ component DELAYB
+ port (A: in std_logic; DEL0: in std_logic; DEL1: in std_logic;
+ DEL2: in std_logic; DEL3: in std_logic; Z: out std_logic);
+ end component;
+ attribute syn_noprune : boolean;
+ attribute syn_noprune of Structure : architecture is true;
+
+begin
+ -- component instantiation statements
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ ud_0: IDDRFXA
+ port map (D=>Data_t0, CLK1=>ECLK, CLK2=>SCLK, CE=>scuba_vhi,
+ RST=>Rst, QA=>Q(0), QB=>Q(1));
+
+ udel_0: DELAYB
+ port map (A=>buf_Data0, DEL0=>Del(0), DEL1=>Del(1), DEL2=>Del(2),
+ DEL3=>Del(3), Z=>Data_t0);
+
+ buf_Data0_in_inst: IB
+ port map (I=>Data(0), O=>buf_Data0);
+
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of adc_ch_in is
+ for Structure
+ for all:VHI use entity ecp2m.VHI(V); end for;
+ for all:IB use entity ecp2m.IB(V); end for;
+ for all:IDDRFXA use entity ecp2m.IDDRFXA(V); end for;
+ for all:DELAYB use entity ecp2m.DELAYB(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_SP1_Build (24)
+-- Module Version: 3.6
+-- Fri Apr 24 11:41:10 2009
+
+-- parameterized module component declaration
+component adc_ch_in
+ port (Del: in std_logic_vector(3 downto 0); ECLK: in std_logic;
+ SCLK: in std_logic; Rst: in std_logic;
+ Data: in std_logic_vector(0 downto 0);
+ Q: out std_logic_vector(1 downto 0));
+end component;
+
+-- parameterized module component instance
+__ : adc_ch_in
+ port map (Del(3 downto 0)=>__, ECLK=>__, SCLK=>__, Rst=>__, Data(0 downto 0)=>__,
+ Q(1 downto 0)=>__);
--- /dev/null
+library ieee; \r
+use ieee.std_logic_1164.all; \r
+use ieee.std_logic_arith.all; \r
+use ieee.std_logic_unsigned.all;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+entity adc_channel_select is\r
+ port( RESET_IN : in std_logic;\r
+ ADC_CLK_IN : in std_logic;\r
+ ADC_SEL_IN : in std_logic_vector(2 downto 0);\r
+ ADC_7_IN : in std_logic_vector(11 downto 0);\r
+ ADC_6_IN : in std_logic_vector(11 downto 0);\r
+ ADC_5_IN : in std_logic_vector(11 downto 0);\r
+ ADC_4_IN : in std_logic_vector(11 downto 0);\r
+ ADC_3_IN : in std_logic_vector(11 downto 0);\r
+ ADC_2_IN : in std_logic_vector(11 downto 0);\r
+ ADC_1_IN : in std_logic_vector(11 downto 0);\r
+ ADC_0_IN : in std_logic_vector(11 downto 0);\r
+ ADC_CH_OUT : out std_logic_vector(11 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
+end;\r
+\r
+architecture behavioral of adc_channel_select is\r
+\r
+ -- Placer Directives\r
+\r
+ -- normal signals \r
+ signal adc_ch : std_logic_vector(11 downto 0);\r
+ signal adc_sel : std_logic_vector(2 downto 0);\r
+ signal reset : std_logic;\r
+\r
+ signal debug : std_logic_vector(15 downto 0);\r
+\r
+\r
+begin \r
+\r
+-- Reset synchronizer\r
+THE_RESET_SYNC: state_sync\r
+port map( STATE_A_IN => reset_in,\r
+ CLK_B_IN => adc_clk_in,\r
+ RESET_B_IN => '0',\r
+ STATE_B_OUT => reset\r
+ );\r
+\r
+-- select signals are from 100MHz clock domain!\r
+THE_SEL2_SYNC: state_sync\r
+port map( STATE_A_IN => adc_sel_in(2),\r
+ CLK_B_IN => adc_clk_in,\r
+ RESET_B_IN => reset,\r
+ STATE_B_OUT => adc_sel(2)\r
+ );\r
+THE_SEL1_SYNC: state_sync\r
+port map( STATE_A_IN => adc_sel_in(1),\r
+ CLK_B_IN => adc_clk_in,\r
+ RESET_B_IN => reset,\r
+ STATE_B_OUT => adc_sel(1)\r
+ );\r
+THE_SEL0_SYNC: state_sync\r
+port map( STATE_A_IN => adc_sel_in(0),\r
+ CLK_B_IN => adc_clk_in,\r
+ RESET_B_IN => reset,\r
+ STATE_B_OUT => adc_sel(0)\r
+ );\r
+\r
+ \r
+-- registered multiplexer\r
+THE_SEL_PROC: process( adc_clk_in )\r
+begin\r
+ if( rising_edge(adc_clk_in) ) then\r
+ if( reset = '1' ) then\r
+ adc_ch <= (others => '0');\r
+ else\r
+ case adc_sel is\r
+ when b"000" => adc_ch <= adc_0_in;\r
+ when b"001" => adc_ch <= adc_1_in;\r
+ when b"010" => adc_ch <= adc_2_in;\r
+ when b"011" => adc_ch <= adc_3_in;\r
+ when b"100" => adc_ch <= adc_4_in;\r
+ when b"101" => adc_ch <= adc_5_in;\r
+ when b"110" => adc_ch <= adc_6_in;\r
+ when b"111" => adc_ch <= adc_7_in;\r
+ when others => adc_ch <= x"000"; -- never\r
+ end case;\r
+ end if;\r
+ end if; \r
+end process THE_SEL_PROC;\r
+\r
+-- debug signals\r
+debug(15 downto 0) <= (others => '0');\r
+\r
+-- output signals\r
+adc_ch_out <= adc_ch;\r
+debug_out <= debug; \r
+\r
+end behavioral; \r
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.std_logic_arith.all;\r
+use ieee.std_logic_unsigned.all;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+entity adc_crossover is\r
+ port( CLK_APV_IN : in std_logic; -- APV 40MHz local clock\r
+ RESET_IN : in std_logic; -- general reset (100MHz)\r
+ -- ADC clock domain signals\r
+ ADC_CLK_IN : in std_logic;\r
+ ADC_CE_IN : in std_logic; -- in case we use 240MHz + write pulse...\r
+ ADC_DATA_VALID_IN : in std_logic;\r
+ ADC_DATA_7_IN : in std_logic_vector(11 downto 0);\r
+ ADC_DATA_6_IN : in std_logic_vector(11 downto 0);\r
+ ADC_DATA_5_IN : in std_logic_vector(11 downto 0);\r
+ ADC_DATA_4_IN : in std_logic_vector(11 downto 0);\r
+ ADC_DATA_3_IN : in std_logic_vector(11 downto 0);\r
+ ADC_DATA_2_IN : in std_logic_vector(11 downto 0);\r
+ ADC_DATA_1_IN : in std_logic_vector(11 downto 0);\r
+ ADC_DATA_0_IN : in std_logic_vector(11 downto 0);\r
+ LEVEL_WR_OUT : out std_logic_vector(4 downto 0);\r
+ -- APV clock domain signals\r
+ APV_DATA_7_OUT : out std_logic_vector(11 downto 0);\r
+ APV_DATA_6_OUT : out std_logic_vector(11 downto 0);\r
+ APV_DATA_5_OUT : out std_logic_vector(11 downto 0);\r
+ APV_DATA_4_OUT : out std_logic_vector(11 downto 0);\r
+ APV_DATA_3_OUT : out std_logic_vector(11 downto 0);\r
+ APV_DATA_2_OUT : out std_logic_vector(11 downto 0);\r
+ APV_DATA_1_OUT : out std_logic_vector(11 downto 0);\r
+ APV_DATA_0_OUT : out std_logic_vector(11 downto 0);\r
+ APV_DATA_VALID_OUT : out std_logic;\r
+ LEVEL_RD_OUT : out std_logic_vector(4 downto 0);\r
+ -- Debug signals\r
+ DEBUG_OUT : out std_logic_vector(31 downto 0)\r
+ );\r
+end;\r
+\r
+architecture behavioral of adc_crossover is\r
+\r
+ signal debug : std_logic_vector(31 downto 0);\r
+\r
+ signal fifo_rd_level : std_logic_vector(4 downto 0);\r
+ signal fifo_wr_level : std_logic_vector(4 downto 0);\r
+ signal next_fifo_rd_ena : std_logic;\r
+ signal fifo_rd_ena : std_logic;\r
+ signal next_fifo_wr_ena : std_logic;\r
+ signal fifo_wr_ena : std_logic;\r
+ signal next_reset : std_logic;\r
+ signal reset : std_logic;\r
+ signal apv_data_valid : std_logic_vector(2 downto 0);\r
+ \r
+begin\r
+\r
+---------------------------------------------------------------------------\r
+-- Debugging signals\r
+---------------------------------------------------------------------------\r
+debug(31 downto 0) <= (others => '0');\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- Reset: we keep the FIFO in reset as long as the PLL is not locked\r
+---------------------------------------------------------------------------\r
+next_reset <= reset_in or not adc_data_valid_in;\r
+\r
+THE_RESET_STATE_SYNC: state_sync\r
+port map( STATE_A_IN => next_reset,\r
+ CLK_B_IN => clk_apv_in,\r
+ RESET_B_IN => '0',\r
+ STATE_B_OUT => reset\r
+ );\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- Crossover fifo for ADC \r
+---------------------------------------------------------------------------\r
+next_fifo_wr_ena <= adc_ce_in and adc_data_valid_in;\r
+next_fifo_rd_ena <= '1' when ( fifo_rd_level > b"0_0101" ) else '0';\r
+\r
+SYNC_WRCLK_PROC: process( adc_clk_in ) \r
+begin\r
+ if( rising_edge(adc_clk_in) ) then\r
+ fifo_wr_ena <= next_fifo_wr_ena;\r
+ end if;\r
+end process SYNC_WRCLK_PROC;\r
+\r
+SYNC_RDCLK_PROC: process( clk_apv_in ) \r
+begin\r
+ if( rising_edge(clk_apv_in) ) then\r
+ fifo_rd_ena <= next_fifo_rd_ena;\r
+ apv_data_valid <= apv_data_valid(1 downto 0) & fifo_rd_ena;\r
+ end if;\r
+end process SYNC_RDCLK_PROC;\r
+\r
+THE_CROSSOVER: crossover\r
+port map( DATA(95 downto 84) => adc_data_7_in,\r
+ DATA(83 downto 72) => adc_data_6_in,\r
+ DATA(71 downto 60) => adc_data_5_in,\r
+ DATA(59 downto 48) => adc_data_4_in,\r
+ DATA(47 downto 36) => adc_data_3_in,\r
+ DATA(35 downto 24) => adc_data_2_in,\r
+ DATA(23 downto 12) => adc_data_1_in,\r
+ DATA(11 downto 0) => adc_data_0_in,\r
+ WRCLOCK => adc_clk_in,\r
+ RDCLOCK => clk_apv_in,\r
+ WREN => fifo_wr_ena,\r
+ RDEN => fifo_rd_ena,\r
+ RESET => reset, -- this is an async clear input!\r
+ RPRESET => '0', -- not needed, as OR'ed with RESET\r
+ Q(95 downto 84) => apv_data_7_out,\r
+ Q(83 downto 72) => apv_data_6_out,\r
+ Q(71 downto 60) => apv_data_5_out,\r
+ Q(59 downto 48) => apv_data_4_out,\r
+ Q(47 downto 36) => apv_data_3_out,\r
+ Q(35 downto 24) => apv_data_2_out,\r
+ Q(23 downto 12) => apv_data_1_out,\r
+ Q(11 downto 0) => apv_data_0_out,\r
+ WCNT => fifo_wr_level,\r
+ RCNT => fifo_rd_level,\r
+ EMPTY => open,\r
+ FULL => open\r
+ );\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- Output signals\r
+---------------------------------------------------------------------------\r
+level_rd_out <= fifo_rd_level;\r
+level_wr_out <= fifo_wr_level;\r
+apv_data_valid_out <= apv_data_valid(2);\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- DEBUG signals\r
+---------------------------------------------------------------------------\r
+debug_out <= debug;\r
+\r
+\r
+end behavioral;\r
--- /dev/null
+library ieee; \r
+use ieee.std_logic_1164.all; \r
+use ieee.std_logic_arith.all; \r
+use ieee.std_logic_unsigned.all;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+entity adc_data_handler_new is\r
+ port( RESET_IN : in std_logic;\r
+ ADC_LCLK_IN : in std_logic; -- LCLK from ADC\r
+ ADC_ADCLK_IN : in std_logic; -- ADCLK from ADC\r
+ ADC_CHNL_IN : in std_logic_vector(7 downto 0);\r
+ PLL_CTRL_IN : in std_logic_vector(3 downto 0);\r
+ ADC_DATA7_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_DATA6_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_DATA5_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_DATA4_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_DATA3_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_DATA2_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_DATA1_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_DATA0_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_CE_OUT : out std_logic;\r
+ ADC_VALID_OUT : out std_logic;\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
+end;\r
+\r
+architecture behavioral of adc_data_handler_new is\r
+\r
+ -- Placer Directives\r
+ attribute HGROUP : string;\r
+ -- for whole architecture\r
+ attribute HGROUP of behavioral : architecture is "ADC_DATA_HANDLER_group";\r
+\r
+ -- normal signals \r
+ signal adc_adclk_vec : std_logic_vector(0 downto 0);\r
+ signal adc_adclk : std_logic_vector(1 downto 0);\r
+ \r
+ signal adc_ch_7_mux : std_logic_vector(1 downto 0);\r
+ signal adc_ch_6_mux : std_logic_vector(1 downto 0);\r
+ signal adc_ch_5_mux : std_logic_vector(1 downto 0);\r
+ signal adc_ch_4_mux : std_logic_vector(1 downto 0);\r
+ signal adc_ch_3_mux : std_logic_vector(1 downto 0);\r
+ signal adc_ch_2_mux : std_logic_vector(1 downto 0);\r
+ signal adc_ch_1_mux : std_logic_vector(1 downto 0);\r
+ signal adc_ch_0_mux : std_logic_vector(1 downto 0);\r
+ \r
+ signal last_adc_7_ch : std_logic_vector(11 downto 0);\r
+ signal last_adc_6_ch : std_logic_vector(11 downto 0);\r
+ signal last_adc_5_ch : std_logic_vector(11 downto 0);\r
+ signal last_adc_4_ch : std_logic_vector(11 downto 0);\r
+ signal last_adc_3_ch : std_logic_vector(11 downto 0);\r
+ signal last_adc_2_ch : std_logic_vector(11 downto 0);\r
+ signal last_adc_1_ch : std_logic_vector(11 downto 0);\r
+ signal last_adc_0_ch : std_logic_vector(11 downto 0);\r
+\r
+ signal buf_adc_7_ch : std_logic_vector(11 downto 0);\r
+ signal buf_adc_6_ch : std_logic_vector(11 downto 0);\r
+ signal buf_adc_5_ch : std_logic_vector(11 downto 0);\r
+ signal buf_adc_4_ch : std_logic_vector(11 downto 0);\r
+ signal buf_adc_3_ch : std_logic_vector(11 downto 0);\r
+ signal buf_adc_2_ch : std_logic_vector(11 downto 0);\r
+ signal buf_adc_1_ch : std_logic_vector(11 downto 0);\r
+ signal buf_adc_0_ch : std_logic_vector(11 downto 0);\r
+\r
+ signal realstore : std_logic_vector(3 downto 0);\r
+ signal next_recstore : std_logic;\r
+ signal recstore : std_logic_vector(3 downto 0);\r
+\r
+ signal reset : std_logic; -- synchronized to 240MHz local clock\r
+\r
+ signal input_delay : std_logic_vector(3 downto 0);\r
+\r
+ signal bitcounter : std_logic_vector(2 downto 0);\r
+ signal synccounter : std_logic_vector(2 downto 0);\r
+ signal next_ce_inc : std_logic;\r
+ signal ce_inc : std_logic;\r
+ signal next_ce_dec : std_logic;\r
+ signal ce_dec : std_logic;\r
+ signal next_sync_low : std_logic;\r
+ signal sync_low : std_logic;\r
+ signal next_sync_high : std_logic;\r
+ signal sync_high : std_logic;\r
+\r
+ signal debug : std_logic_vector(15 downto 0);\r
+ \r
+begin \r
+\r
+-- input delay for IDDR, 50ps / unit\r
+input_delay <= pll_ctrl_in;\r
+\r
+-- Reset synchronizer \r
+THE_RESET_SYNC: state_sync\r
+port map( STATE_A_IN => reset_in,\r
+ CLK_B_IN => adc_lclk_in,\r
+ RESET_B_IN => '0',\r
+ STATE_B_OUT => reset\r
+ );\r
+\r
+-- We have to reconstruct the ADC word clock (ADCLK).\r
+-- Mind the vector! \r
+adc_adclk_vec(0) <= adc_adclk_in; \r
+ \r
+THE_ADC_ADCLK_IN: adc_ch_in \r
+port map( DEL => input_delay,\r
+ ECLK => adc_lclk_in, \r
+ SCLK => adc_lclk_in, \r
+ RST => '0', \r
+ DATA => adc_adclk_vec, \r
+ Q => adc_adclk \r
+ ); \r
+\r
+-- First group of channels (0 and 1)\r
+THE_DIN_0: adc_ch_in \r
+port map( DEL => input_delay,\r
+ ECLK => adc_lclk_in, \r
+ SCLK => adc_lclk_in, \r
+ RST => '0', \r
+ DATA => adc_chnl_in(0 downto 0), \r
+ Q => adc_ch_0_mux \r
+ ); \r
+THE_DIN_1: adc_ch_in \r
+port map( DEL => input_delay,\r
+ ECLK => adc_lclk_in, \r
+ SCLK => adc_lclk_in, \r
+ RST => '0', \r
+ DATA => adc_chnl_in(1 downto 1), \r
+ Q => adc_ch_1_mux \r
+ ); \r
+THE_ADC_0_1_CH: adc_twochannels\r
+port map( CLK_IN => adc_lclk_in,\r
+ RESET_IN => reset,\r
+ CLOCK_IN => adc_adclk,\r
+ DATA_0_IN => adc_ch_0_mux,\r
+ DATA_1_IN => adc_ch_1_mux,\r
+ DATA_0_OUT => last_adc_0_ch,\r
+ DATA_1_OUT => last_adc_1_ch,\r
+ STORE_OUT => realstore(0),\r
+ SWAP_OUT => open,\r
+ CLOCK_OUT => open,\r
+ DEBUG_OUT => open\r
+ );\r
+\r
+-- Second group of channels (2 and 3)\r
+THE_DIN_2: adc_ch_in \r
+port map( DEL => input_delay,\r
+ ECLK => adc_lclk_in, \r
+ SCLK => adc_lclk_in, \r
+ RST => '0', \r
+ DATA => adc_chnl_in(2 downto 2), \r
+ Q => adc_ch_2_mux \r
+ ); \r
+THE_DIN_3: adc_ch_in \r
+port map( DEL => input_delay,\r
+ ECLK => adc_lclk_in, \r
+ SCLK => adc_lclk_in, \r
+ RST => '0', \r
+ DATA => adc_chnl_in(3 downto 3), \r
+ Q => adc_ch_3_mux \r
+ ); \r
+THE_ADC_2_3_CH: adc_twochannels\r
+port map( CLK_IN => adc_lclk_in,\r
+ RESET_IN => reset,\r
+ CLOCK_IN => adc_adclk,\r
+ DATA_0_IN => adc_ch_2_mux,\r
+ DATA_1_IN => adc_ch_3_mux,\r
+ DATA_0_OUT => last_adc_2_ch,\r
+ DATA_1_OUT => last_adc_3_ch,\r
+ STORE_OUT => realstore(1),\r
+ SWAP_OUT => open,\r
+ CLOCK_OUT => open,\r
+ DEBUG_OUT => open\r
+ );\r
+\r
+-- Third group of channels (4 and 5)\r
+THE_DIN_4: adc_ch_in \r
+port map( DEL => input_delay,\r
+ ECLK => adc_lclk_in, \r
+ SCLK => adc_lclk_in, \r
+ RST => '0', \r
+ DATA => adc_chnl_in(4 downto 4), \r
+ Q => adc_ch_4_mux \r
+ ); \r
+THE_DIN_5: adc_ch_in \r
+port map( DEL => input_delay,\r
+ ECLK => adc_lclk_in, \r
+ SCLK => adc_lclk_in, \r
+ RST => '0', \r
+ DATA => adc_chnl_in(5 downto 5), \r
+ Q => adc_ch_5_mux \r
+ ); \r
+THE_ADC_4_5_CH: adc_twochannels\r
+port map( CLK_IN => adc_lclk_in,\r
+ RESET_IN => reset,\r
+ CLOCK_IN => adc_adclk,\r
+ DATA_0_IN => adc_ch_4_mux,\r
+ DATA_1_IN => adc_ch_5_mux,\r
+ DATA_0_OUT => last_adc_4_ch,\r
+ DATA_1_OUT => last_adc_5_ch,\r
+ STORE_OUT => realstore(2),\r
+ SWAP_OUT => open,\r
+ CLOCK_OUT => open,\r
+ DEBUG_OUT => open\r
+ );\r
+\r
+-- Fourth group of channels (6 and 7)\r
+THE_DIN_6: adc_ch_in \r
+port map( DEL => input_delay,\r
+ ECLK => adc_lclk_in, \r
+ SCLK => adc_lclk_in, \r
+ RST => '0', \r
+ DATA => adc_chnl_in(6 downto 6), \r
+ Q => adc_ch_6_mux \r
+ ); \r
+THE_DIN_7: adc_ch_in \r
+port map( DEL => input_delay,\r
+ ECLK => adc_lclk_in, \r
+ SCLK => adc_lclk_in, \r
+ RST => '0', \r
+ DATA => adc_chnl_in(7 downto 7), \r
+ Q => adc_ch_7_mux \r
+ ); \r
+THE_ADC_6_7_CH: adc_twochannels\r
+port map( CLK_IN => adc_lclk_in,\r
+ RESET_IN => reset,\r
+ CLOCK_IN => adc_adclk,\r
+ DATA_0_IN => adc_ch_6_mux,\r
+ DATA_1_IN => adc_ch_7_mux,\r
+ DATA_0_OUT => last_adc_6_ch,\r
+ DATA_1_OUT => last_adc_7_ch,\r
+ STORE_OUT => realstore(3),\r
+ SWAP_OUT => open,\r
+ CLOCK_OUT => open,\r
+ DEBUG_OUT => open\r
+ );\r
+\r
+-- Clock reconstruction (will only work if all four units work in perfect alignment)\r
+next_recstore <= '1' when ( realstore = b"1111" ) else '0';\r
+\r
+-- Synchronising stage\r
+THE_SYNC_PROC: process( adc_lclk_in )\r
+begin\r
+ if( rising_edge(adc_lclk_in) ) then\r
+ recstore(3 downto 0) <= recstore(2 downto 0) & next_recstore;\r
+ sync_low <= next_sync_low;\r
+ sync_high <= next_sync_high;\r
+ ce_inc <= next_ce_inc;\r
+ ce_dec <= next_ce_dec;\r
+ end if;\r
+end process THE_SYNC_PROC;\r
+\r
+THE_BIT_COUNTER: process( adc_lclk_in )\r
+begin\r
+ if( rising_edge(adc_lclk_in) ) then\r
+ if( recstore(0) = '1' ) then\r
+ bitcounter <= (others => '0');\r
+ else\r
+ bitcounter <= bitcounter + 1;\r
+ end if;\r
+ end if;\r
+end process THE_BIT_COUNTER;\r
+\r
+next_sync_low <= '1' when (synccounter = b"000") else '0';\r
+next_sync_high <= '1' when (synccounter = b"111") else '0';\r
+\r
+next_ce_inc <= '1' when ( (bitcounter = b"101") and (recstore(0) = '1') and (sync_high = '0') ) else '0';\r
+next_ce_dec <= '1' when ( (bitcounter = b"101") and (recstore(0) = '0') and (sync_low = '0') ) else '0';\r
+\r
+THE_SYNC_COUNTER: process( adc_lclk_in )\r
+begin\r
+ if( rising_edge(adc_lclk_in) ) then\r
+ if( reset = '1' ) then\r
+ synccounter <= (others => '0');\r
+ elsif( (ce_inc = '1') and (ce_dec = '0') ) then\r
+ synccounter <= synccounter + 1;\r
+ elsif( (ce_inc = '0') and (ce_dec = '1') ) then\r
+ synccounter <= synccounter - 1;\r
+ end if;\r
+ end if;\r
+end process THE_SYNC_COUNTER;\r
+\r
+debug(15 downto 11) <= (others => '0');\r
+debug(10 downto 8) <= synccounter;\r
+debug(7) <= sync_low;\r
+debug(6) <= sync_high;\r
+debug(5) <= ce_dec;\r
+debug(4) <= ce_inc;\r
+debug(3) <= '0';\r
+debug(2 downto 0) <= bitcounter;\r
+\r
+-----------------------------------------------------------------------\r
+-- generate 8 ADC channel inputs and clock transfer registers\r
+-----------------------------------------------------------------------\r
+THE_DATA_DELAY_PROC: process( adc_lclk_in )\r
+begin\r
+ if( rising_edge(adc_lclk_in) ) then\r
+ buf_adc_7_ch <= last_adc_7_ch;\r
+ buf_adc_6_ch <= last_adc_6_ch;\r
+ buf_adc_5_ch <= last_adc_5_ch;\r
+ buf_adc_4_ch <= last_adc_4_ch;\r
+ buf_adc_3_ch <= last_adc_3_ch;\r
+ buf_adc_2_ch <= last_adc_2_ch;\r
+ buf_adc_1_ch <= last_adc_1_ch;\r
+ buf_adc_0_ch <= last_adc_0_ch;\r
+ end if;\r
+end process THE_DATA_DELAY_PROC;\r
+\r
+\r
+-- output signals\r
+adc_data7_out <= buf_adc_7_ch; \r
+adc_data6_out <= buf_adc_6_ch; \r
+adc_data5_out <= buf_adc_5_ch; \r
+adc_data4_out <= buf_adc_4_ch; \r
+adc_data3_out <= buf_adc_3_ch; \r
+adc_data2_out <= buf_adc_2_ch; \r
+adc_data1_out <= buf_adc_1_ch; \r
+adc_data0_out <= buf_adc_0_ch; \r
+adc_ce_out <= recstore(3);\r
+adc_valid_out <= sync_high;\r
+ \r
+debug_out(15 downto 0) <= debug; \r
+ \r
+end behavioral; \r
+
\ No newline at end of file
--- /dev/null
+[Device]\r
+Family=latticeecp2m\r
+PartType=LFE2M100E\r
+PartName=LFE2M100E-6F900C\r
+SpeedGrade=-6\r
+Package=FPBGA900\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=Distributed_ROM\r
+CoreRevision=2.4\r
+ModuleName=adc_onewire_map_mem\r
+SourceFormat=VHDL\r
+ParameterFileVersion=1.0\r
+Date=11/05/2009\r
+Time=10:27:05\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+Addresses=128\r
+Data=4\r
+LUT=0\r
+MemFile=\\home\mboehmer\vhdl_pro\adcmv3\src\adc_onewire_mapping.mem\r
+MemFormat=orca\r
--- /dev/null
+SCUBA, Version ispLever_v72_SP2_Build (23)
+Thu Nov 05 10:27:05 2009
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp. All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
+Copyright (c) 2001 Agere Systems All rights reserved.
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
+
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n adc_onewire_map_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 7 -num_words 128 -data_width 4 -outdata UNREGISTERED -memfile \\home\mboehmer\vhdl_pro\adcmv3\src\adc_onewire_mapping.mem -memformat orca -e
+ Circuit name : adc_onewire_map_mem
+ Module type : rom
+ Module Version : 2.4
+ Address width : 7
+ Ports :
+ Inputs : Address[6:0]
+ Outputs : Q[3:0]
+ I/O buffer : not inserted
+ Memory file : \\home\mboehmer\vhdl_pro\adcmv3\src\adc_onewire_mapping.mem
+ EDIF output : suppressed
+ VHDL output : adc_onewire_map_mem.vhd
+ VHDL template : adc_onewire_map_mem_tmpl.vhd
+ VHDL testbench : tb_adc_onewire_map_mem_tmpl.vhd
+ VHDL purpose : for synthesis and simulation
+ Bus notation : big endian
+ Report output : adc_onewire_map_mem.srp
+ Element Usage :
+ ROM128X1 : 4
+ Estimated Resource Usage:
+ LUT : 16
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23)
+-- Module Version: 2.4
+--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type rom -addr_width 7 -num_rows 128 -data_width 4 -outdata UNREGISTERED -memfile \\home\mboehmer\vhdl_pro\adcmv3\src\adc_onewire_mapping.mem -memformat orca -e
+
+-- Thu Nov 05 10:27:05 2009
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity adc_onewire_map_mem is
+ port (
+ Address: in std_logic_vector(6 downto 0);
+ Q: out std_logic_vector(3 downto 0));
+end adc_onewire_map_mem;
+
+architecture Structure of adc_onewire_map_mem is
+
+ -- local component declarations
+ component ROM128X1
+ -- synopsys translate_off
+ generic (INITVAL : in String);
+ -- synopsys translate_on
+ port (AD6: in std_logic; AD5: in std_logic; AD4: in std_logic;
+ AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ attribute initval : string;
+ attribute initval of mem_0_3 : label is "0xFF00FF00FF001FE0E01F7F80807F6956";
+ attribute initval of mem_0_2 : label is "0xF0F0F0F0F0F07E187E18F81CF81C807F";
+ attribute initval of mem_0_1 : label is "0xCCCCCCCCCCCC798386BAE6521AEC70F8";
+ attribute initval of mem_0_0 : label is "0xAAAAAAAAAAAA32AD326B2A9729D64AE5";
+
+begin
+ -- component instantiation statements
+ mem_0_3: ROM128X1
+ -- synopsys translate_off
+ generic map (initval=> "0xFF00FF00FF001FE0E01F7F80807F6956")
+ -- synopsys translate_on
+ port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4),
+ AD3=>Address(3), AD2=>Address(2), AD1=>Address(1),
+ AD0=>Address(0), DO0=>Q(3));
+
+ mem_0_2: ROM128X1
+ -- synopsys translate_off
+ generic map (initval=> "0xF0F0F0F0F0F07E187E18F81CF81C807F")
+ -- synopsys translate_on
+ port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4),
+ AD3=>Address(3), AD2=>Address(2), AD1=>Address(1),
+ AD0=>Address(0), DO0=>Q(2));
+
+ mem_0_1: ROM128X1
+ -- synopsys translate_off
+ generic map (initval=> "0xCCCCCCCCCCCC798386BAE6521AEC70F8")
+ -- synopsys translate_on
+ port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4),
+ AD3=>Address(3), AD2=>Address(2), AD1=>Address(1),
+ AD0=>Address(0), DO0=>Q(1));
+
+ mem_0_0: ROM128X1
+ -- synopsys translate_off
+ generic map (initval=> "0xAAAAAAAAAAAA32AD326B2A9729D64AE5")
+ -- synopsys translate_on
+ port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4),
+ AD3=>Address(3), AD2=>Address(2), AD1=>Address(1),
+ AD0=>Address(0), DO0=>Q(0));
+
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of adc_onewire_map_mem is
+ for Structure
+ for all:ROM128X1 use entity ecp2m.ROM128X1(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+Starting process: \r
+\r
+SCUBA, Version ispLever_v72_SP2_Build (23)\r
+Thu Nov 05 10:27:05 2009\r
+\r
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
+Copyright (c) 1995 AT&T Corp. All rights reserved.\r
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
+Copyright (c) 2001 Agere Systems All rights reserved.\r
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
+\r
+BEGIN SCUBA Module Synthesis\r
+\r
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n adc_onewire_map_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 7 -num_words 128 -data_width 4 -outdata UNREGISTERED -memfile \\home\mboehmer\vhdl_pro\adcmv3\src\adc_onewire_mapping.mem -memformat orca -e \r
+ Circuit name : adc_onewire_map_mem\r
+ Module type : rom\r
+ Module Version : 2.4\r
+ Address width : 7\r
+ Data width : 4\r
+ Ports : \r
+ Inputs : Address[6:0]\r
+ Outputs : Q[3:0]\r
+ I/O buffer : not inserted\r
+ Memory file : \\home\mboehmer\vhdl_pro\adcmv3\src\adc_onewire_mapping.mem\r
+ EDIF output : suppressed\r
+ VHDL output : adc_onewire_map_mem.vhd\r
+ VHDL template : adc_onewire_map_mem_tmpl.vhd\r
+ VHDL testbench : tb_adc_onewire_map_mem_tmpl.vhd\r
+ VHDL purpose : for synthesis and simulation\r
+ Bus notation : big endian\r
+ Report output : adc_onewire_map_mem.srp\r
+ Estimated Resource Usage:\r
+ LUT : 16\r
+\r
+END SCUBA Module Synthesis\r
+\r
+File: adc_onewire_map_mem.lpc created.\r
+\r
+\r
+End process: completed successfully.\r
+\r
+\r
+Total Warnings: 0\r
+\r
+Total Errors: 0\r
+\r
+\r
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23)
+-- Module Version: 2.4
+-- Thu Nov 05 10:27:05 2009
+
+-- parameterized module component declaration
+component adc_onewire_map_mem
+ port (Address: in std_logic_vector(6 downto 0);
+ Q: out std_logic_vector(3 downto 0));
+end component;
+
+-- parameterized module component instance
+__ : adc_onewire_map_mem
+ port map (Address(6 downto 0)=>__, Q(3 downto 0)=>__);
--- /dev/null
+#Format=Address-Hex\r
+#Depth=128\r
+#DataWidth=4\r
+#AddrRadix=3\r
+#DataRadix=3\r
+\r
+# Backplane 0\r
+# mapAPV 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15\r
+# 1Wire 5 12 13 6 14 7 15 3 8 1 0 9 2 10 11 (4) \r
+00: 5\r
+01: c\r
+02: d\r
+03: 6\r
+04: e\r
+05: 7\r
+06: f\r
+07: 3\r
+08: 8\r
+09: 1\r
+0a: 0\r
+0b: 9\r
+0c: 2\r
+0d: a\r
+0e: b\r
+0f: 4\r
+# Backplane 1\r
+# mapAPV 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15\r
+# 1Wire 8 9 15 14 13 10 11 3 1 2 0 7 6 5 4 (12) \r
+10: 8\r
+11: 9\r
+12: f\r
+13: e\r
+14: d\r
+15: a\r
+16: b\r
+17: 3\r
+18: 1\r
+19: 2\r
+1a: 0\r
+1b: 7\r
+1c: 6\r
+1d: 5\r
+1e: 4\r
+1f: c\r
+# Backplane 2\r
+# mapAPV 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15\r
+# 1Wire 1 3 5 4 7 0 2 9 8 11 10 13 12 15 14 (6) \r
+20: 1 \r
+21: 3\r
+22: 5\r
+23: 4\r
+24: 7\r
+25: 0\r
+26: 2\r
+27: 9\r
+28: 8\r
+29: b\r
+2a: a\r
+2b: d\r
+2c: c\r
+2d: f\r
+2e: e\r
+2f: 6\r
+# Backplane 3\r
+# mapAPV 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15\r
+# 1Wire 9 11 8 15 14 3 1 2 0 7 6 4 5 13 12 (10) \r
+30: 9\r
+31: b\r
+32: 8\r
+33: f\r
+34: e\r
+35: 3\r
+36: 1\r
+37: 2\r
+38: 0\r
+39: 7\r
+3a: 6\r
+3b: 4\r
+3c: 5\r
+3d: d\r
+3e: c\r
+3f: a\r
+# Backplane 4\r
+# mapAPV 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15\r
+# 1Wire 3 2 1 5 4 9 8 11 10 13 12 14 15 7 6 (0) \r
+40: 3\r
+41: 2\r
+42: 1\r
+43: 5\r
+44: 4\r
+45: 9\r
+46: 8\r
+47: b\r
+48: a\r
+49: d\r
+4a: c\r
+4b: e\r
+4c: f\r
+4d: 7\r
+4e: 6\r
+4f: 0\r
+# unused (5) => 1:1\r
+50: 0\r
+51: 1\r
+52: 2\r
+53: 3\r
+54: 4\r
+55: 5\r
+56: 6\r
+57: 7\r
+58: 8\r
+59: 9\r
+5a: a\r
+5b: b\r
+5c: c\r
+5d: d\r
+5e: e\r
+5f: f\r
+# unused (6) => 1:1\r
+60: 0\r
+61: 1\r
+62: 2\r
+63: 3\r
+64: 4\r
+65: 5\r
+66: 6\r
+67: 7\r
+68: 8\r
+69: 9\r
+6a: a\r
+6b: b\r
+6c: c\r
+6d: d\r
+6e: e\r
+6f: f\r
+# unused (7) => 1:1\r
+70: 0\r
+71: 1\r
+72: 2\r
+73: 3\r
+74: 4\r
+75: 5\r
+76: 6\r
+77: 7\r
+78: 8\r
+79: 9\r
+7a: a\r
+7b: b\r
+7c: c\r
+7d: d\r
+7e: e\r
+7f: f\r
--- /dev/null
+[Device]\r
+Family=latticeecp2m\r
+PartType=LFE2M100E\r
+PartName=LFE2M100E-6F900C\r
+SpeedGrade=-6\r
+Package=FPBGA900\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=PLL\r
+CoreRevision=4.2\r
+ModuleName=adc_pll\r
+SourceFormat=VHDL\r
+ParameterFileVersion=1.0\r
+Date=04/16/2009\r
+Time=11:20:59\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=None\r
+Order=None\r
+IO=0\r
+Type=ehxpllb\r
+mode=normal\r
+IFrq=40\r
+OFrq=40.000000\r
+KFrq=\r
+U_OFrq=40\r
+U_KFrq=50\r
+OP_Tol=0.0\r
+OK_Tol=0.0\r
+Div=1\r
+Mult=1\r
+Post=32\r
+SecD=2\r
+fb_mode=CLKOP\r
+PhaseDuty=Static\r
+DelayControl=SPLL_NO_DELAY\r
+External=DISABLED\r
+PCDR=1\r
+ClkOPBp=0\r
+EnCLKOS=0\r
+ClkOSBp=0\r
+Phase=0.0\r
+Duty=8\r
+DPD=50% Duty\r
+EnCLKOK=0\r
+ClkOKBp=0\r
+ClkRst=0\r
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v72_SP1_Build (24)
+-- Module Version: 4.2
+--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n adc_pll -lang vhdl -synth synplify -arch ep5m00 -type pll -fin 40 -phase_cntl STATIC -fclkop 40 -fclkop_tol 0.0 -delay_cntl SPLL_NO_DELAY -fb_mode CLOCKTREE -extcap DISABLED -noclkos -noclkok -use_rst -e
+
+-- Thu Apr 16 11:20:59 2009
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity adc_pll is
+ port (
+ CLK: in std_logic;
+ RESET: in std_logic;
+ CLKOP: out std_logic;
+ LOCK: out std_logic);
+ attribute dont_touch : string;
+ attribute dont_touch of adc_pll : entity is "true";
+end adc_pll;
+
+architecture Structure of adc_pll is
+
+ -- internal signal declarations
+ signal CLKOP_t: std_logic;
+ signal scuba_vlo: std_logic;
+ signal CLK_t: std_logic;
+
+ -- local component declarations
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component EPLLD
+ -- synopsys translate_off
+ generic (PLLCAP : in String; CLKOK_BYPASS : in String;
+ CLKOS_BYPASS : in String; CLKOP_BYPASS : in String;
+ DUTY : in Integer; PHASEADJ : in String;
+ PHASE_CNTL : in String; CLKOK_DIV : in Integer;
+ CLKFB_DIV : in Integer; CLKOP_DIV : in Integer;
+ CLKI_DIV : in Integer);
+ -- synopsys translate_on
+ port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic;
+ RSTK: in std_logic; DPAMODE: in std_logic; DRPAI3: in std_logic;
+ DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic;
+ DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic;
+ DFPAI0: in std_logic; CLKOP: out std_logic; CLKOS: out std_logic;
+ CLKOK: out std_logic; LOCK: out std_logic; CLKINTFB: out std_logic);
+ end component;
+ attribute PLLCAP : string;
+ attribute PLLTYPE : string;
+ attribute CLKOK_BYPASS : string;
+ attribute FREQUENCY_PIN_CLKOK : string;
+ attribute CLKOK_DIV : string;
+ attribute CLKOS_BYPASS : string;
+ attribute FREQUENCY_PIN_CLKOP : string;
+ attribute CLKOP_BYPASS : string;
+ attribute PHASE_CNTL : string;
+ attribute FDEL : string;
+ attribute DUTY : string;
+ attribute PHASEADJ : string;
+ attribute FREQUENCY_PIN_CLKI : string;
+ attribute CLKOP_DIV : string;
+ attribute CLKFB_DIV : string;
+ attribute CLKI_DIV : string;
+ attribute FIN : string;
+ attribute PLLCAP of PLLDInst_0 : label is "DISABLED";
+ attribute PLLTYPE of PLLDInst_0 : label is "SPLL";
+ attribute CLKOK_BYPASS of PLLDInst_0 : label is "DISABLED";
+ attribute FREQUENCY_PIN_CLKOK of PLLDInst_0 : label is "50.000000";
+ attribute CLKOK_DIV of PLLDInst_0 : label is "2";
+ attribute CLKOS_BYPASS of PLLDInst_0 : label is "DISABLED";
+ attribute FREQUENCY_PIN_CLKOP of PLLDInst_0 : label is "40.000000";
+ attribute CLKOP_BYPASS of PLLDInst_0 : label is "DISABLED";
+ attribute PHASE_CNTL of PLLDInst_0 : label is "STATIC";
+ attribute FDEL of PLLDInst_0 : label is "0";
+ attribute DUTY of PLLDInst_0 : label is "8";
+ attribute PHASEADJ of PLLDInst_0 : label is "0.0";
+ attribute FREQUENCY_PIN_CLKI of PLLDInst_0 : label is "40.000000";
+ attribute CLKOP_DIV of PLLDInst_0 : label is "32";
+ attribute CLKFB_DIV of PLLDInst_0 : label is "1";
+ attribute CLKI_DIV of PLLDInst_0 : label is "1";
+ attribute FIN of PLLDInst_0 : label is "40.000000";
+ attribute syn_keep : boolean;
+ attribute syn_noprune : boolean;
+ attribute syn_noprune of Structure : architecture is true;
+
+begin
+ -- component instantiation statements
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ PLLDInst_0: EPLLD
+ -- synopsys translate_off
+ generic map (PLLCAP=> "DISABLED", CLKOK_BYPASS=> "DISABLED",
+ CLKOK_DIV=> 2, CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED",
+ PHASE_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0", CLKOP_DIV=> 32,
+ CLKFB_DIV=> 1, CLKI_DIV=> 1)
+ -- synopsys translate_on
+ port map (CLKI=>CLK_t, CLKFB=>CLKOP_t, RST=>RESET,
+ RSTK=>scuba_vlo, DPAMODE=>scuba_vlo, DRPAI3=>scuba_vlo,
+ DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo,
+ DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo,
+ DFPAI0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open, CLKOK=>open,
+ LOCK=>LOCK, CLKINTFB=>open);
+
+ CLKOP <= CLKOP_t;
+ CLK_t <= CLK;
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of adc_pll is
+ for Structure
+ for all:VLO use entity ecp2m.VLO(V); end for;
+ for all:EPLLD use entity ecp2m.EPLLD(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_SP1_Build (24)
+-- Module Version: 4.2
+-- Thu Apr 16 11:20:59 2009
+
+-- parameterized module component declaration
+component adc_pll
+ port (CLK: in std_logic; RESET: in std_logic; CLKOP: out std_logic;
+ LOCK: out std_logic);
+end component;
+
+-- parameterized module component instance
+__ : adc_pll
+ port map (CLK=>__, RESET=>__, CLKOP=>__, LOCK=>__);
--- /dev/null
+[Device]\r
+Family=latticeecp2m\r
+PartType=LFE2M100E\r
+PartName=LFE2M100E-6F900C\r
+SpeedGrade=-6\r
+Package=FPBGA900\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=RAM_DP\r
+CoreRevision=6.1\r
+ModuleName=adc_snoop_mem\r
+SourceFormat=VHDL\r
+ParameterFileVersion=1.0\r
+Date=10/13/2009\r
+Time=16:03:30\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+RAddress=1024\r
+RData=16\r
+WAddress=1024\r
+WData=16\r
+enByte=0\r
+ByteSize=9\r
+adPipeline=0\r
+inPipeline=0\r
+outPipeline=1\r
+MOR=0\r
+InData=Registered\r
+AdControl=Registered\r
+MemFile=\r
+MemFormat=bin\r
+Reset=Sync\r
+GSR=Enabled\r
+Pad=0\r
+EnECC=0\r
+Optimization=Speed\r
+EnSleep=ENABLED\r
+Pipeline=0\r
--- /dev/null
+SCUBA, Version ispLever_v72_SP2_Build (23)
+Tue Oct 13 16:03:30 2009
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp. All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
+Copyright (c) 2001 Agere Systems All rights reserved.
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
+
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n adc_snoop_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -device LFE2M100E -type ramdps -raddr_width 10 -rwidth 16 -waddr_width 10 -wwidth 16 -rnum_words 1024 -wnum_words 1024 -outdata REGISTERED -resetmode SYNC -cascade -1 -e
+ Circuit name : adc_snoop_mem
+ Module type : RAM_DP
+ Module Version : 6.1
+ Ports :
+ Inputs : WrAddress[9:0], RdAddress[9:0], Data[15:0], WE, RdClock, RdClockEn, Reset, WrClock, WrClockEn
+ Outputs : Q[15:0]
+ I/O buffer : not inserted
+ EDIF output : suppressed
+ VHDL output : adc_snoop_mem.vhd
+ VHDL template : adc_snoop_mem_tmpl.vhd
+ VHDL testbench : tb_adc_snoop_mem_tmpl.vhd
+ VHDL purpose : for synthesis and simulation
+ Bus notation : big endian
+ Report output : adc_snoop_mem.srp
+ Element Usage :
+ DP16KB : 1
+ Estimated Resource Usage:
+ EBR : 1
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23)
+-- Module Version: 6.1
+--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type bram -wp 10 -rp 0011 -rdata_width 16 -data_width 16 -num_rows 1024 -outdata REGISTERED -resetmode SYNC -cascade -1 -e
+
+-- Tue Oct 13 16:03:30 2009
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity adc_snoop_mem is
+ port (
+ WrAddress: in std_logic_vector(9 downto 0);
+ RdAddress: in std_logic_vector(9 downto 0);
+ Data: in std_logic_vector(15 downto 0);
+ WE: in std_logic;
+ RdClock: in std_logic;
+ RdClockEn: in std_logic;
+ Reset: in std_logic;
+ WrClock: in std_logic;
+ WrClockEn: in std_logic;
+ Q: out std_logic_vector(15 downto 0));
+end adc_snoop_mem;
+
+architecture Structure of adc_snoop_mem is
+
+ -- internal signal declarations
+ signal scuba_vhi: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component DP16KB
+ -- synopsys translate_off
+ generic (GSR : in String; WRITEMODE_B : in String;
+ CSDECODE_B : in std_logic_vector(2 downto 0);
+ CSDECODE_A : in std_logic_vector(2 downto 0);
+ WRITEMODE_A : in String; RESETMODE : in String;
+ REGMODE_B : in String; REGMODE_A : in String;
+ DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer);
+ -- synopsys translate_on
+ port (DIA0: in std_logic; DIA1: in std_logic;
+ DIA2: in std_logic; DIA3: in std_logic;
+ DIA4: in std_logic; DIA5: in std_logic;
+ DIA6: in std_logic; DIA7: in std_logic;
+ DIA8: in std_logic; DIA9: in std_logic;
+ DIA10: in std_logic; DIA11: in std_logic;
+ DIA12: in std_logic; DIA13: in std_logic;
+ DIA14: in std_logic; DIA15: in std_logic;
+ DIA16: in std_logic; DIA17: in std_logic;
+ ADA0: in std_logic; ADA1: in std_logic;
+ ADA2: in std_logic; ADA3: in std_logic;
+ ADA4: in std_logic; ADA5: in std_logic;
+ ADA6: in std_logic; ADA7: in std_logic;
+ ADA8: in std_logic; ADA9: in std_logic;
+ ADA10: in std_logic; ADA11: in std_logic;
+ ADA12: in std_logic; ADA13: in std_logic;
+ CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic;
+ CSA0: in std_logic; CSA1: in std_logic;
+ CSA2: in std_logic; RSTA: in std_logic;
+ DIB0: in std_logic; DIB1: in std_logic;
+ DIB2: in std_logic; DIB3: in std_logic;
+ DIB4: in std_logic; DIB5: in std_logic;
+ DIB6: in std_logic; DIB7: in std_logic;
+ DIB8: in std_logic; DIB9: in std_logic;
+ DIB10: in std_logic; DIB11: in std_logic;
+ DIB12: in std_logic; DIB13: in std_logic;
+ DIB14: in std_logic; DIB15: in std_logic;
+ DIB16: in std_logic; DIB17: in std_logic;
+ ADB0: in std_logic; ADB1: in std_logic;
+ ADB2: in std_logic; ADB3: in std_logic;
+ ADB4: in std_logic; ADB5: in std_logic;
+ ADB6: in std_logic; ADB7: in std_logic;
+ ADB8: in std_logic; ADB9: in std_logic;
+ ADB10: in std_logic; ADB11: in std_logic;
+ ADB12: in std_logic; ADB13: in std_logic;
+ CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic;
+ CSB0: in std_logic; CSB1: in std_logic;
+ CSB2: in std_logic; RSTB: in std_logic;
+ DOA0: out std_logic; DOA1: out std_logic;
+ DOA2: out std_logic; DOA3: out std_logic;
+ DOA4: out std_logic; DOA5: out std_logic;
+ DOA6: out std_logic; DOA7: out std_logic;
+ DOA8: out std_logic; DOA9: out std_logic;
+ DOA10: out std_logic; DOA11: out std_logic;
+ DOA12: out std_logic; DOA13: out std_logic;
+ DOA14: out std_logic; DOA15: out std_logic;
+ DOA16: out std_logic; DOA17: out std_logic;
+ DOB0: out std_logic; DOB1: out std_logic;
+ DOB2: out std_logic; DOB3: out std_logic;
+ DOB4: out std_logic; DOB5: out std_logic;
+ DOB6: out std_logic; DOB7: out std_logic;
+ DOB8: out std_logic; DOB9: out std_logic;
+ DOB10: out std_logic; DOB11: out std_logic;
+ DOB12: out std_logic; DOB13: out std_logic;
+ DOB14: out std_logic; DOB15: out std_logic;
+ DOB16: out std_logic; DOB17: out std_logic);
+ end component;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute CSDECODE_B : string;
+ attribute CSDECODE_A : string;
+ attribute WRITEMODE_B : string;
+ attribute WRITEMODE_A : string;
+ attribute GSR : string;
+ attribute RESETMODE : string;
+ attribute REGMODE_B : string;
+ attribute REGMODE_A : string;
+ attribute DATA_WIDTH_B : string;
+ attribute DATA_WIDTH_A : string;
+ attribute MEM_LPC_FILE of adc_snoop_mem_0_0_0 : label is "adc_snoop_mem.lpc";
+ attribute MEM_INIT_FILE of adc_snoop_mem_0_0_0 : label is "";
+ attribute CSDECODE_B of adc_snoop_mem_0_0_0 : label is "0b000";
+ attribute CSDECODE_A of adc_snoop_mem_0_0_0 : label is "0b000";
+ attribute WRITEMODE_B of adc_snoop_mem_0_0_0 : label is "NORMAL";
+ attribute WRITEMODE_A of adc_snoop_mem_0_0_0 : label is "NORMAL";
+ attribute GSR of adc_snoop_mem_0_0_0 : label is "DISABLED";
+ attribute RESETMODE of adc_snoop_mem_0_0_0 : label is "SYNC";
+ attribute REGMODE_B of adc_snoop_mem_0_0_0 : label is "OUTREG";
+ attribute REGMODE_A of adc_snoop_mem_0_0_0 : label is "OUTREG";
+ attribute DATA_WIDTH_B of adc_snoop_mem_0_0_0 : label is "18";
+ attribute DATA_WIDTH_A of adc_snoop_mem_0_0_0 : label is "18";
+
+begin
+ -- component instantiation statements
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ adc_snoop_mem_0_0_0: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 18,
+ DATA_WIDTH_A=> 18)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
+ DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
+ DIA14=>Data(14), DIA15=>Data(15), DIA16=>scuba_vlo,
+ DIA17=>scuba_vlo, ADA0=>scuba_vhi, ADA1=>scuba_vhi,
+ ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>WrAddress(0),
+ ADA5=>WrAddress(1), ADA6=>WrAddress(2), ADA7=>WrAddress(3),
+ ADA8=>WrAddress(4), ADA9=>WrAddress(5), ADA10=>WrAddress(6),
+ ADA11=>WrAddress(7), ADA12=>WrAddress(8),
+ ADA13=>WrAddress(9), CEA=>WrClockEn, CLKA=>WrClock, WEA=>WE,
+ CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>scuba_vlo, ADB4=>RdAddress(0),
+ ADB5=>RdAddress(1), ADB6=>RdAddress(2), ADB7=>RdAddress(3),
+ ADB8=>RdAddress(4), ADB9=>RdAddress(5), ADB10=>RdAddress(6),
+ ADB11=>RdAddress(7), ADB12=>RdAddress(8),
+ ADB13=>RdAddress(9), CEB=>RdClockEn, CLKB=>RdClock,
+ WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>Q(0), DOB1=>Q(1), DOB2=>Q(2),
+ DOB3=>Q(3), DOB4=>Q(4), DOB5=>Q(5), DOB6=>Q(6), DOB7=>Q(7),
+ DOB8=>Q(8), DOB9=>Q(9), DOB10=>Q(10), DOB11=>Q(11),
+ DOB12=>Q(12), DOB13=>Q(13), DOB14=>Q(14), DOB15=>Q(15),
+ DOB16=>open, DOB17=>open);
+
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of adc_snoop_mem is
+ for Structure
+ for all:VHI use entity ecp2m.VHI(V); end for;
+ for all:VLO use entity ecp2m.VLO(V); end for;
+ for all:DP16KB use entity ecp2m.DP16KB(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+Starting process: \r
+\r
+SCUBA, Version ispLever_v72_SP2_Build (23)\r
+Tue Oct 13 16:03:30 2009\r
+\r
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
+Copyright (c) 1995 AT&T Corp. All rights reserved.\r
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
+Copyright (c) 2001 Agere Systems All rights reserved.\r
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
+\r
+BEGIN SCUBA Module Synthesis\r
+\r
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n adc_snoop_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -device LFE2M100E -type ramdps -raddr_width 10 -rwidth 16 -waddr_width 10 -wwidth 16 -rnum_words 1024 -wnum_words 1024 -outdata REGISTERED -resetmode SYNC -cascade -1 -e \r
+ Circuit name : adc_snoop_mem\r
+ Module type : RAM_DP\r
+ Module Version : 6.1\r
+ Ports : \r
+ Inputs : WrAddress[9:0], RdAddress[9:0], Data[15:0], WE, RdClock, RdClockEn, Reset, WrClock, WrClockEn\r
+ Outputs : Q[15:0]\r
+ I/O buffer : not inserted\r
+ EDIF output : suppressed\r
+ VHDL output : adc_snoop_mem.vhd\r
+ VHDL template : adc_snoop_mem_tmpl.vhd\r
+ VHDL testbench : tb_adc_snoop_mem_tmpl.vhd\r
+ VHDL purpose : for synthesis and simulation\r
+ Bus notation : big endian\r
+ Report output : adc_snoop_mem.srp\r
+ Estimated Resource Usage:\r
+ EBR : 1\r
+\r
+END SCUBA Module Synthesis\r
+\r
+File: adc_snoop_mem.lpc created.\r
+\r
+\r
+End process: completed successfully.\r
+\r
+\r
+Total Warnings: 0\r
+\r
+Total Errors: 0\r
+\r
+\r
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23)
+-- Module Version: 6.1
+-- Tue Oct 13 16:03:30 2009
+
+-- parameterized module component declaration
+component adc_snoop_mem
+ port (WrAddress: in std_logic_vector(9 downto 0);
+ RdAddress: in std_logic_vector(9 downto 0);
+ Data: in std_logic_vector(15 downto 0); WE: in std_logic;
+ RdClock: in std_logic; RdClockEn: in std_logic;
+ Reset: in std_logic; WrClock: in std_logic;
+ WrClockEn: in std_logic; Q: out std_logic_vector(15 downto 0));
+end component;
+
+-- parameterized module component instance
+__ : adc_snoop_mem
+ port map (WrAddress(9 downto 0)=>__, RdAddress(9 downto 0)=>__, Data(15 downto 0)=>__,
+ WE=>__, RdClock=>__, RdClockEn=>__, Reset=>__, WrClock=>__,
+ WrClockEn=>__, Q(15 downto 0)=>__);
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.std_logic_arith.all;\r
+use ieee.std_logic_unsigned.all;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+entity adc_twochannels is\r
+ port( CLK_IN : in std_logic; -- DDR bit clock\r
+ RESET_IN : in std_logic;\r
+ CLOCK_IN : in std_logic_vector(1 downto 0); -- word clock\r
+ DATA_0_IN : in std_logic_vector(1 downto 0); -- ADC channel one\r
+ DATA_1_IN : in std_logic_vector(1 downto 0); -- ADC channel two\r
+ DATA_0_OUT : out std_logic_vector(11 downto 0); -- demultiplexed ADC channel one\r
+ DATA_1_OUT : out std_logic_vector(11 downto 0); -- demultiplexed ADC channel two\r
+ STORE_OUT : out std_logic;\r
+ SWAP_OUT : out std_logic;\r
+ CLOCK_OUT : out std_logic;\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
+end;\r
+\r
+architecture behaviour of adc_twochannels is\r
+\r
+ -- Placer Directives\r
+ attribute HGROUP : string;\r
+ -- for whole architecture\r
+ attribute HGROUP of behaviour : architecture is "TWOCHANNELS_group";\r
+\r
+ type half_data_t is array (0 to 1) of std_logic_vector(5 downto 0);\r
+ signal qda : half_data_t; -- serial input data, raising edge\r
+ signal qdb : half_data_t; -- serial input data, falling edge\r
+ signal parda : half_data_t; -- parallel input data, raising edge\r
+ signal pardb : half_data_t; -- parallel input data, falling edge\r
+ signal qc : half_data_t; -- serial ADCLK signal, (0) raising edge, (1) falling edge\r
+ type full_data_t is array (0 to 1) of std_logic_vector(11 downto 0);\r
+ signal muxed : full_data_t;\r
+ signal data : full_data_t;\r
+\r
+ signal next_store_a : std_logic;\r
+ signal store_a : std_logic; -- store serial data A to parallel temp register\r
+ signal next_store_b : std_logic;\r
+ signal store_b : std_logic; -- store serial data B to parallel temp register\r
+ signal check : std_logic; -- auxiliary signal for swapping\r
+ signal next_swap : std_logic;\r
+ signal swap : std_logic; -- swap half words before assembling\r
+ signal store : std_logic; -- assemble full word\r
+\r
+begin\r
+\r
+-------------------------------------------------------------------------\r
+-- Data reconstruction\r
+-------------------------------------------------------------------------\r
+-- Shift registers for both data streams from DDR input block\r
+THE_INSHIFT_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ qda(0) <= (others => '0');\r
+ qdb(0) <= (others => '0');\r
+ qda(1) <= (others => '0');\r
+ qdb(1) <= (others => '0');\r
+ qc(0) <= (others => '0');\r
+ qc(1) <= (others => '0');\r
+ else\r
+ -- first channel\r
+ qda(0) <= qda(0)(4 downto 0) & data_0_in(0);\r
+ qdb(0) <= qdb(0)(4 downto 0) & data_0_in(1);\r
+ -- second channel\r
+ qda(1) <= qda(1)(4 downto 0) & data_1_in(0);\r
+ qdb(1) <= qdb(1)(4 downto 0) & data_1_in(1);\r
+ -- clock channel\r
+ qc(0) <= qc(0)(4 downto 0) & clock_in(0);\r
+ qc(1) <= qc(1)(4 downto 0) & clock_in(1);\r
+ end if;\r
+ end if;\r
+end process THE_INSHIFT_PROC;\r
+\r
+-- parallel temp registers to store raw serial data for multiplexing\r
+THE_PARALLEL_STORE_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( store_a = '1' ) then\r
+ parda(0) <= qda(0);\r
+ parda(1) <= qda(1);\r
+ end if;\r
+ if( store_b = '1' ) then\r
+ pardb(0) <= qdb(0);\r
+ pardb(1) <= qdb(1);\r
+ end if;\r
+ end if;\r
+end process THE_PARALLEL_STORE_PROC;\r
+\r
+-- synchronize combinatorial signals\r
+THE_SYNC_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ store_a <= next_store_a;\r
+ store_b <= next_store_b;\r
+ check <= store_b;\r
+ swap <= next_swap;\r
+ store <= store_a;\r
+ end if;\r
+end process THE_SYNC_PROC;\r
+\r
+-- store signals for half words\r
+next_store_a <= '1' when (qc(0)(5 downto 2) = b"0111") else '0';\r
+next_store_b <= '1' when (qc(1)(5 downto 2) = b"0111") else '0';\r
+\r
+-- swap half words indicator (can be improved: 10 -> preswap, preswap 01 -> swap)\r
+next_swap <= '1' when ( (store_a = '1') and (store_b = '0') and (check = '1') ) else '0';\r
+\r
+-- halfword swapping\r
+THE_SWAP_PROC: process( parda, pardb, swap )\r
+begin\r
+ case swap is\r
+ when '1' => -- first channel\r
+ muxed(0)(0) <= pardb(0)(5);\r
+ muxed(0)(1) <= parda(0)(5);\r
+ muxed(0)(2) <= pardb(0)(4);\r
+ muxed(0)(3) <= parda(0)(4);\r
+ muxed(0)(4) <= pardb(0)(3);\r
+ muxed(0)(5) <= parda(0)(3);\r
+ muxed(0)(6) <= pardb(0)(2);\r
+ muxed(0)(7) <= parda(0)(2);\r
+ muxed(0)(8) <= pardb(0)(1);\r
+ muxed(0)(9) <= parda(0)(1);\r
+ muxed(0)(10) <= pardb(0)(0);\r
+ muxed(0)(11) <= parda(0)(0);\r
+ -- second channel\r
+ muxed(1)(0) <= pardb(1)(5);\r
+ muxed(1)(1) <= parda(1)(5);\r
+ muxed(1)(2) <= pardb(1)(4);\r
+ muxed(1)(3) <= parda(1)(4);\r
+ muxed(1)(4) <= pardb(1)(3);\r
+ muxed(1)(5) <= parda(1)(3);\r
+ muxed(1)(6) <= pardb(1)(2);\r
+ muxed(1)(7) <= parda(1)(2);\r
+ muxed(1)(8) <= pardb(1)(1);\r
+ muxed(1)(9) <= parda(1)(1);\r
+ muxed(1)(10) <= pardb(1)(0);\r
+ muxed(1)(11) <= parda(1)(0);\r
+ when '0' => -- first channel\r
+ muxed(0)(0) <= parda(0)(5);\r
+ muxed(0)(1) <= pardb(0)(5);\r
+ muxed(0)(2) <= parda(0)(4);\r
+ muxed(0)(3) <= pardb(0)(4);\r
+ muxed(0)(4) <= parda(0)(3);\r
+ muxed(0)(5) <= pardb(0)(3);\r
+ muxed(0)(6) <= parda(0)(2);\r
+ muxed(0)(7) <= pardb(0)(2);\r
+ muxed(0)(8) <= parda(0)(1);\r
+ muxed(0)(9) <= pardb(0)(1);\r
+ muxed(0)(10) <= parda(0)(0);\r
+ muxed(0)(11) <= pardb(0)(0);\r
+ -- second channel\r
+ muxed(1)(0) <= parda(1)(5);\r
+ muxed(1)(1) <= pardb(1)(5);\r
+ muxed(1)(2) <= parda(1)(4);\r
+ muxed(1)(3) <= pardb(1)(4);\r
+ muxed(1)(4) <= parda(1)(3);\r
+ muxed(1)(5) <= pardb(1)(3);\r
+ muxed(1)(6) <= parda(1)(2);\r
+ muxed(1)(7) <= pardb(1)(2);\r
+ muxed(1)(8) <= parda(1)(1);\r
+ muxed(1)(9) <= pardb(1)(1);\r
+ muxed(1)(10) <= parda(1)(0);\r
+ muxed(1)(11) <= pardb(1)(0);\r
+ when others =>\r
+ end case;\r
+end process THE_SWAP_PROC;\r
+\r
+-- store parallel data\r
+THE_STORE_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( store = '1' ) then\r
+ data(0) <= muxed(0);\r
+ data(1) <= muxed(1);\r
+ end if;\r
+ end if;\r
+end process THE_STORE_PROC;\r
+\r
+---- output signals\r
+data_0_out <= data(0);\r
+data_1_out <= data(1);\r
+\r
+store_out <= store;\r
+\r
+swap_out <= swap;\r
+\r
+clock_out <= qc(0)(3); -- timing adjustment\r
+\r
+-- debug signals\r
+debug_out(15) <= store;\r
+debug_out(14) <= swap;\r
+debug_out(13) <= store_b;\r
+debug_out(12) <= store_a;\r
+debug_out(11 downto 0) <= data(0);\r
+\r
+--debug_out(15 downto 15) <= (others => '0');\r
+--debug_out(14) <= swap;\r
+--debug_out(13) <= store_b;\r
+--debug_out(12) <= store_a;\r
+--debug_out(11 downto 6) <= parda(0);\r
+--debug_out(5 downto 0) <= pardb(0);\r
+\r
+\r
+end behaviour;\r
+\r
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.std_logic_unsigned.all;\r
+\r
+library work;\r
+use work.trb_net_std.all;\r
+use work.adcmv3_components.all;\r
+\r
+entity adcmv3 is\r
+ port( CLK100M : in std_logic; -- OK -- 100MHz LVDS clock \r
+ -- trigger inputs\r
+ EXT_IN : in std_logic_vector(3 downto 0); -- OK -- external triggers\r
+ -- APV stuff\r
+ APV0A_CLK : out std_logic; -- OK -- APV bank 0: 40MHz phase adjustable clock \r
+ APV0B_CLK : out std_logic; -- OK -- APV bank 0: 40MHz phase adjustable clock \r
+ APV0A_TRG : out std_logic; -- OK -- APV bank 0: trigger pulse out\r
+ APV0B_TRG : out std_logic; -- OK -- APV bank 0: trigger pulse out\r
+ APV0_RST : out std_logic; -- OK -- APV bank 0: reset signal, low active\r
+ APV0_SDA : inout std_logic; -- OK -- APV bank 0: I2C bus SDA\r
+ APV0_SCL : inout std_logic; -- OK -- APV bank 0: I2C bus SCL\r
+ ENA_LVDS : out std_logic_vector(7 downto 0); -- OK -- enable LVDS drivers\r
+ APV1A_CLK : out std_logic; -- OK -- APV bank 1: 40MHz phase adjustable clock\r
+ APV1B_CLK : out std_logic; -- OK -- APV bank 1: 40MHz phase adjustable clock\r
+ APV1A_TRG : out std_logic; -- OK -- APV bank 1: trigger pulse out\r
+ APV1B_TRG : out std_logic; -- OK -- APV bank 1: trigger pulse out\r
+ APV1_RST : out std_logic; -- OK -- APV bank 1: reset signal, low active\r
+ APV1_SDA : inout std_logic; -- OK -- APV bank 1: I2C bus SDA\r
+ APV1_SCL : inout std_logic; -- OK -- APV bank 1: I2C bus SCL\r
+ ENB_LVDS : out std_logic_vector(7 downto 0); -- OK -- enable LVDS drivers\r
+ -- ADC0 stuff\r
+ ADC0_CLK : out std_logic; -- OK -- ADC clock, 40MHz LVTTL\r
+ ADC0_RST : out std_logic; -- OK -- ADC reset signal\r
+ ADC0_PD : out std_logic; -- OK -- ADC powerdown signal\r
+ ADC0_CS : out std_logic; -- OK -- ADC /CS signal\r
+ ADC0_SDI : out std_logic; -- OK -- ADC serial data in\r
+ ADC0_SCK : out std_logic; -- OK -- ADC serial clock\r
+ ADC0_LCLK : in std_logic; -- OK -- ADC 240MHz DDR clock\r
+ ADC0_ADCLK : in std_logic; -- OK -- ADC 40MHz frame clock\r
+ ADC0_OUT : in std_logic_vector(7 downto 0); -- OK -- serial LVDS data streams\r
+ -- ADC1 stuff\r
+ ADC1_CLK : out std_logic; -- OK -- ADC clock, 40MHz LVTTL\r
+ ADC1_RST : out std_logic; -- OK -- ADC reset signal\r
+ ADC1_PD : out std_logic; -- OK -- ADC powerdown signal\r
+ ADC1_CS : out std_logic; -- OK -- ADC /CS signal\r
+ ADC1_SDI : out std_logic; -- OK -- ADC serial data in\r
+ ADC1_SCK : out std_logic; -- OK -- ADC serial clock\r
+ ADC1_LCLK : in std_logic; -- OK -- ADC 240MHz DDR clock\r
+ ADC1_ADCLK : in std_logic; -- OK -- ADC 40MHz frame clock\r
+ ADC1_OUT : in std_logic_vector(7 downto 0); -- OK -- serial LVDS data streams\r
+ -- uC connections\r
+ UC_RESET : in std_logic; -- OK -- uC reset, high active\r
+ UC_REBOOT : out std_logic; -- OK -- was UC_FPGA(3), requests FPGA reboot\r
+ -- SerDes pins \r
+ HDINN2 : in std_logic; -- highspeed INPUT\r
+ HDINP2 : in std_logic; --\r
+ HDOUTN2 : out std_logic; -- highspeed OUTPUT\r
+ HDOUTP2 : out std_logic; -- \r
+ SD_PRESENT : in std_logic; -- OK -- Present signal from SFP\r
+ SD_LOS : in std_logic; -- OK -- Loss Of Signal from SFP\r
+ SD_TXDIS : out std_logic; -- OK -- SFP transmitter disable\r
+ ADCM_ONEWIRE : inout std_logic; -- OK -- OneWire ID chip on ADCM\r
+ -- Backplane sense wires\r
+ BP_MODULE : in std_logic_vector(3 downto 0); -- OK -- module number input from backplane\r
+ BP_SECTOR : in std_logic_vector(3 downto 0); -- OK -- sector number input from backplane\r
+ BP_ONEWIRE : inout std_logic; -- OK -- OneWire ID chip on backplane \r
+ BP_LED : out std_logic; -- OK -- backplane LED \r
+ -- LEDs\r
+ FPGA_LED : out std_logic_vector(6 downto 3); -- OK -- general purpose LEDS\r
+ FPGA_LED_RXD : out std_logic; -- OK -- FPGA_LED(2)\r
+ FPGA_LED_TXD : out std_logic; -- OK -- FPGA_LED(1)\r
+ FPGA_LED_LINK : out std_logic; -- OK -- FPGA_LED(0)\r
+ FPGA_LED_PLL : out std_logic; -- OK -- PLL locked \r
+ FPGA_LED_ADC : out std_logic_vector(1 downto 0); -- OK -- ADCx OK LED \r
+ -- 1Wire chips on APV FEs\r
+ APV0_1W : inout std_logic_vector(7 downto 0);\r
+ APV1_1W : inout std_logic_vector(7 downto 0);\r
+ -- SPI FlashROM connections\r
+ U_SPI_CS : out std_logic; -- OK -- chip select for SPI boot FlashROM\r
+ U_SPI_SCK : out std_logic; -- OK -- clock\r
+ U_SPI_SDI : out std_logic; -- OK -- connects to SI on the FlashROM\r
+ U_SPI_SDO : in std_logic; -- OK -- connects to SO on the FlashROM\r
+ -- Debug connections\r
+ DBG_EXP : out std_logic_vector(43 downto 0) -- OK -- SMC50 debug header\r
+ );\r
+end;\r
+\r
+architecture adcmv3 of adcmv3 is\r
+\r
+-- Signals\r
+ -- Clock related signals\r
+ signal clk100m_locked : std_logic; -- not needed at the moment\r
+ signal sysclk : std_logic; -- clean 100MHz for distribution\r
+\r
+ signal adc0_ce : std_logic;\r
+ signal adc0_valid : std_logic;\r
+ signal adc0_reset : std_logic;\r
+ signal adc0_powerdown : std_logic;\r
+ signal adc1_ce : std_logic;\r
+ signal adc1_valid : std_logic;\r
+ signal adc1_reset : std_logic;\r
+ signal adc1_powerdown : std_logic;\r
+\r
+ signal clk_adc : std_logic; -- 40MHz for ADC operation\r
+ signal clk_apv : std_logic; -- 40MHz for APV operation (phase shiftable!)\r
+ signal clk40m_locked : std_logic;\r
+ signal clk40m_reset : std_logic;\r
+\r
+ signal async_reset : std_logic;\r
+\r
+ -- APV related signals\r
+ signal apv_sda_out : std_logic; -- APV SDA\r
+ signal apv_sda_in : std_logic;\r
+ signal apv_scl_out : std_logic; -- APV SCL\r
+ signal apv_scl_in : std_logic;\r
+ signal apv_trg : std_logic; -- real APV trigger signal\r
+ signal apv_sync : std_logic; -- artificial signal\r
+ signal apv_frame_reqd : std_logic; -- one 100MHz pulse per requested frame\r
+ signal apv0_reset : std_logic;\r
+ signal apv1_reset : std_logic;\r
+ signal apv_reset : std_logic;\r
+ signal adc_on : std_logic_vector(15 downto 0); -- ordered after ADC0[7:0] and ADC1[15:8]\r
+ signal lvds_on : std_logic_vector(15 downto 0); -- ordered after ADC0[7:0] and ADC1[15:8]\r
+\r
+ -- Control signals\r
+ signal ctrl_pll : std_logic_vector(15 downto 0); -- PLL control register\r
+ signal status_pll : std_logic_vector(15 downto 0); -- PLL status register\r
+ signal ctrl_trg : std_logic_vector(31 downto 0); -- TRG control register\r
+ signal ctrl_lvl : std_logic_vector(31 downto 0); -- LVL control register\r
+ \r
+ signal ctrl_bitlow : std_logic_vector(11 downto 0); -- BIT_LOW setting for APV digital header\r
+ signal ctrl_bithigh : std_logic_vector(11 downto 0); -- BIT_HIGH setting for APV digital header\r
+ signal ctrl_flatlow : std_logic_vector(11 downto 0); -- FLAT_LOW setting\r
+ signal ctrl_flathigh : std_logic_vector(11 downto 0); -- FLAT_HIGH setting\r
+\r
+ signal maximum_trg : std_logic_vector(3 downto 0);\r
+\r
+ signal raw_buf_full : std_logic;\r
+ signal eds_buf_full : std_logic;\r
+ signal eds_buf_level : std_logic_vector(4 downto 0);\r
+\r
+ -- regIO data bus\r
+ signal regio_addr : std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0);\r
+ signal regio_read_enable : std_logic;\r
+ signal regio_write_enable : std_logic;\r
+ signal regio_data_wr : std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0);\r
+ signal regio_data_rd : std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0);\r
+ signal regio_dataready : std_logic;\r
+ signal regio_no_more_data : std_logic;\r
+ signal regio_write_ack : std_logic;\r
+ signal regio_unknown_addr : std_logic;\r
+ signal regio_timeout : std_logic;\r
+\r
+ -- common status / control registers from RegIO\r
+ signal common_stat_reg : std_logic_vector(63 downto 0);\r
+ signal common_ctrl_reg : std_logic_vector(63 downto 0);\r
+\r
+ -- user defined "quick'n'dirty" registers\r
+ signal simple_status : std_logic_vector(127 downto 0);\r
+ signal simple_control : std_logic_vector(63 downto 0);\r
+\r
+ -- debug signals\r
+ signal test_reg : std_logic_vector(31 downto 0);\r
+ signal trbrich_debug : std_logic_vector(63 downto 0);\r
+ signal trgctrl_debug : std_logic_vector(63 downto 0);\r
+ signal slave_debug : std_logic_vector(63 downto 0);\r
+ signal fifo_debug : std_logic_vector(63 downto 0);\r
+ signal raw_buf_debug : std_logic_vector(63 downto 0);\r
+\r
+ -- EDS / BUFFER signals (raw buf -> ped corr)\r
+ signal eds_data : std_logic_vector(39 downto 0);\r
+ signal eds_avail : std_logic;\r
+ signal eds_done : std_logic;\r
+ signal buf_addr : std_logic_vector(6 downto 0);\r
+ signal buf_done : std_logic;\r
+ signal buf_tick : std_logic_vector(15 downto 0);\r
+ signal buf_start : std_logic_vector(15 downto 0);\r
+ signal buf_ready : std_logic_vector(15 downto 0); -- just for debugging!\r
+\r
+ type reg_38bit_t is array (0 to 15) of std_logic_vector(37 downto 0);\r
+ signal buf_data : reg_38bit_t;\r
+\r
+ signal thr_addr : std_logic_vector(6 downto 0);\r
+ type reg_18bit_t is array (0 to 15) of std_logic_vector(17 downto 0);\r
+ signal thr_data : reg_18bit_t;\r
+ signal ped_data : reg_18bit_t;\r
+\r
+ -- FIFO / DHDR signals (ped corr -> ipu stage)\r
+ signal dhdr_data : std_logic_vector(31 downto 0);\r
+ signal dhdr_length : std_logic_vector(15 downto 0);\r
+ signal dhdr_store : std_logic;\r
+ signal dhdr_buf_full : std_logic;\r
+\r
+ signal fifo_start : std_logic;\r
+ signal fifo_done : std_logic;\r
+ signal fifo_we : std_logic_vector(15 downto 0);\r
+ type reg_40bit_t is array (0 to 15) of std_logic_vector(39 downto 0);\r
+ signal fifo_data : reg_40bit_t;\r
+\r
+ -- APV control / status signals\r
+ type reg_16bit_t is array (0 to 15) of std_logic_vector(15 downto 0);\r
+ signal adc_ctrl_reg : reg_16bit_t;\r
+ signal adc_stat_reg : reg_16bit_t;\r
+\r
+ signal debug : std_logic_vector(42 downto 0);\r
+ signal debug_q : std_logic_vector(42 downto 0);\r
+ signal debug_qq : std_logic_vector(42 downto 0);\r
+ signal debug_clk : std_logic;\r
+ \r
+ -- LVL1 application interface\r
+ signal lvl1_trg_type : std_logic_vector(3 downto 0);\r
+ signal lvl1_trg_received : std_logic;\r
+ signal lvl1_trg_number : std_logic_vector(15 downto 0);\r
+ signal lvl1_trg_code : std_logic_vector(7 downto 0);\r
+ signal lvl1_trg_information : std_logic_vector(23 downto 0);\r
+ signal lvl1_error_pattern : std_logic_vector(31 downto 0);\r
+ signal lvl1_trg_release : std_logic;\r
+ signal lvl1_trg_missing : std_logic;\r
+ signal timing_trg_found : std_logic;\r
+\r
+ -- IPU application interface\r
+ signal ipu_number : std_logic_vector(15 downto 0);\r
+ signal ipu_information : std_logic_vector(7 downto 0);\r
+ signal ipu_start_readout : std_logic;\r
+ signal ipu_data : std_logic_vector(31 downto 0);\r
+ signal ipu_dataready : std_logic;\r
+ signal ipu_readout_finished : std_logic;\r
+ signal ipu_read : std_logic;\r
+ signal ipu_length : std_logic_vector(15 downto 0);\r
+ signal ipu_error_pattern : std_logic_vector(31 downto 0);\r
+\r
+ signal local_lvl1_counter : std_logic_vector(15 downto 0);\r
+ signal local_lvl2_counter : std_logic_vector(15 downto 0);\r
+\r
+ -- ADC signals\r
+ type reg_12bit_t is array (0 to 15) of std_logic_vector(11 downto 0);\r
+ signal adc_raw_data : reg_12bit_t; -- ADC specific clock domain\r
+ signal adc_data : reg_12bit_t; -- common APV clock domain\r
+\r
+ signal adc1_testdata : std_logic_vector(11 downto 0);\r
+ signal adc0_testdata : std_logic_vector(11 downto 0);\r
+ signal adc1_select : std_logic_vector(2 downto 0);\r
+ signal adc0_select : std_logic_vector(2 downto 0);\r
+\r
+ -- input synchronizing\r
+ signal bp_sector_q : std_logic_vector(3 downto 0);\r
+ signal bp_sector_qq : std_logic_vector(3 downto 0);\r
+ signal bp_module_q : std_logic_vector(3 downto 0);\r
+ signal bp_module_qq : std_logic_vector(3 downto 0);\r
+\r
+ signal lsm_state_bits : std_logic_vector(3 downto 0);\r
+ signal reset_by_trb : std_logic;\r
+ signal global_sync_reset : std_logic;\r
+\r
+ signal adc0_iodelay : std_logic_vector(3 downto 0);\r
+ signal adc1_iodelay : std_logic_vector(3 downto 0);\r
+\r
+\r
+\r
+-- Components\r
+ -- are now in adcmv2_components.vhd\r
+ \r
+begin\r
+\r
+----------------------------------------\r
+-- Async reset assignment --\r
+----------------------------------------\r
+--async_reset <= '0'; -- no async reset\r
+async_reset <= uc_reset; -- uC reset pin\r
+\r
+\r
+----------------------------------------\r
+-- Reset handler / spike surpression --\r
+----------------------------------------\r
+THE_RESET_HANDLER: reset_handler\r
+port map( CLEAR_IN => async_reset,\r
+ RESET_IN => '0',\r
+ CLK_IN => sysclk,\r
+ TRB_RESET_IN => reset_by_trb,\r
+ RESET_OUT => global_sync_reset,\r
+ DEBUG_OUT => open\r
+ );\r
+\r
+\r
+----------------------------------------\r
+-- 100MHz PLL -> 40MHz / 100MHz --\r
+----------------------------------------\r
+-- 100MHz PLL, generating 40MHz and phase shifted 40MHz\r
+THE_40M_PLL: PLL_40M\r
+port map( CLK => clk100m,\r
+ RESET => clk40m_reset,\r
+ DPAMODE => '1', -- dynamic control \r
+ DPHASE0 => ctrl_pll(0),\r
+ DPHASE1 => ctrl_pll(1),\r
+ DPHASE2 => ctrl_pll(2),\r
+ DPHASE3 => ctrl_pll(3),\r
+ CLKOP => clk_apv, -- fixed phase, used for logic \r
+ CLKOS => clk_adc, -- phase adjustable, for ODDRXC only\r
+ LOCK => clk40m_locked\r
+ );\r
+clk40m_reset <= ctrl_pll(7);\r
+\r
+-- 100MHz DLL, used for clock injection delay removal\r
+THE_100M_DLL: dll_100m\r
+port map( CLK => clk100m,\r
+ RESETN => '1',\r
+ ALUHOLD => '0',\r
+ CLKOP => sysclk,\r
+ CLKOS => open,\r
+ LOCK => clk100m_locked\r
+ );\r
+\r
+\r
+----------------------------------------\r
+-- TRB endpoint --\r
+----------------------------------------\r
+THE_RICH_TRB: rich_trb\r
+port map( CLK100M_IN => clk100m, -- SerDes exclusive clock\r
+ SYSCLK_IN => sysclk, -- fabric clock\r
+ RESET_IN => global_sync_reset,\r
+ SD_RXD_P_IN => hdinp2,\r
+ SD_RXD_N_IN => hdinn2,\r
+ SD_TXD_P_OUT => hdoutp2, \r
+ SD_TXD_N_OUT => hdoutn2,\r
+ SD_PRESENT_IN => sd_present,\r
+ SD_TXDIS_OUT => sd_txdis,\r
+ SD_LOS_IN => sd_los,\r
+ ONEWIRE_INOUT => adcm_onewire,\r
+ -- common regIO status / control registers\r
+ COMMON_STAT_REG_IN => common_stat_reg,\r
+ COMMON_CTRL_REG_OUT => common_ctrl_reg,\r
+ -- status register input to regIO / control register output from regIO\r
+ CONTROL_OUT => simple_control,\r
+ STATUS_IN => simple_status,\r
+ -- LVL1 signals\r
+ LVL1_TRG_TYPE_OUT => lvl1_trg_type,\r
+ LVL1_TRG_RECEIVED_OUT => lvl1_trg_received,\r
+ LVL1_TRG_NUMBER_OUT => lvl1_trg_number,\r
+ LVL1_TRG_CODE_OUT => lvl1_trg_code,\r
+ LVL1_TRG_INFORMATION_OUT => lvl1_trg_information,\r
+ LVL1_ERROR_PATTERN_IN => lvl1_error_pattern,\r
+ LVL1_TRG_RELEASE_IN => lvl1_trg_release,\r
+ TIMING_TRG_FOUND_IN => timing_trg_found,\r
+ -- IPU data channel signals (yes, we will use ComputeNodes (tm) (R) (C) one day... :-)\r
+ IPU_NUMBER_OUT => ipu_number,\r
+ IPU_INFORMATION_OUT => ipu_information,\r
+ IPU_START_READOUT_OUT => ipu_start_readout,\r
+ IPU_DATA_IN => ipu_data,\r
+ IPU_DATAREADY_IN => ipu_dataready,\r
+ IPU_READOUT_FINISHED_IN => ipu_readout_finished,\r
+ IPU_READ_OUT => ipu_read,\r
+ IPU_LENGTH_IN => ipu_length,\r
+ IPU_ERROR_PATTERN_IN => ipu_error_pattern,\r
+ -- regIO bus\r
+ REGIO_ADDR_OUT => regio_addr,\r
+ REGIO_READ_ENABLE_OUT => regio_read_enable,\r
+ REGIO_WRITE_ENABLE_OUT => regio_write_enable,\r
+ REGIO_DATA_OUT => regio_data_wr,\r
+ REGIO_DATA_IN => regio_data_rd,\r
+ REGIO_DATAREADY_IN => regio_dataready,\r
+ REGIO_NO_MORE_DATA_IN => regio_no_more_data,\r
+ REGIO_WRITE_ACK_IN => regio_write_ack,\r
+ REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr,\r
+ REGIO_TIMEOUT_OUT => regio_timeout,\r
+ -- status LEDs\r
+ LED_LINK_STAT => fpga_led_link,\r
+ LED_LINK_TXD => fpga_led_txd,\r
+ LED_LINK_RXD => fpga_led_rxd,\r
+ LINK_BSM_OUT => lsm_state_bits, -- LinkStateMachine bits\r
+ RESET_OUT => reset_by_trb,\r
+ DEBUG => trbrich_debug --open \r
+ );\r
+\r
+-- LVL1 error pattern, to be sent back to CTS with each trigger\r
+lvl1_error_pattern(31 downto 22) <= (others => '0');\r
+lvl1_error_pattern(21) <= '0'; -- buffers almost full\r
+lvl1_error_pattern(20) <= '0'; -- buffers half full\r
+lvl1_error_pattern(19 downto 18) <= (others => '0');\r
+lvl1_error_pattern(17) <= '0'; -- lvl1_trg_missing; -- missing timing trigger\r
+lvl1_error_pattern(16) <= '0'; -- LVL1 tag mismatch with local counters (done by Jan)\r
+lvl1_error_pattern(15 downto 0) <= (others => '0'); \r
+\r
+\r
+------------------------------------------------------------------\r
+-- DEBUG DEBUG DEBUG\r
+------------------------------------------------------------------\r
+debug_clk <= sysclk;\r
+\r
+--debug(42 downto 0) <= (others => '0');\r
+\r
+debug(42 downto 39) <= (others => '0'); \r
+-- IPU signals\r
+debug(38 downto 35) <= ipu_number(3 downto 0);\r
+debug(34) <= ipu_start_readout;\r
+debug(33) <= ipu_dataready;\r
+debug(32) <= ipu_read;\r
+debug(31) <= ipu_readout_finished;\r
+-- FIFO signals\r
+debug(30) <= fifo_start; -- ped_corr_ctrl -> ipu_stage => data procession starts (unused in ipu_stage)\r
+debug(29) <= fifo_we(0); -- ped_corr_ctrl -> ipu_stage => transfer processed data into data FIFO (0)\r
+debug(28) <= fifo_done; -- ped_corr_ctrl -> ipu_stage => store length count data in small FIFOs\r
+debug(27) <= dhdr_store; -- ped_corr_ctrl -> ipu_stage => store DHDR information for IPU\r
+debug(26) <= dhdr_buf_full; -- ipu_stage ->\r
+-- EventDataSheet / buffer signals\r
+debug(25) <= buf_done; -- ped_corr_ctrl -> raw_buf_stage => raw data has been processed\r
+debug(24) <= buf_tick(0); -- raw_buf_stage -> ped_corr_ctrl => synced tickmarks\r
+debug(23) <= buf_ready(0); -- raw_buf_stage => adc_last\r
+debug(22) <= buf_start(0); -- raw_buf_stage -> ped_corr_ctrl => adc_start\r
+debug(21 downto 17) <= buf_data(0)(34 downto 30);\r
+debug(16) <= raw_buf_full; -- raw_buf_stage -> apv_trgctrl => at least one raw buffer is full\r
+debug(15) <= eds_done; -- ped_corr_ctrl -> apv_trgctrl => EDS data has been transfered, release buffer entry\r
+debug(14) <= eds_avail; -- apv_trgctrl -> ped_corr_ctrl => at least one EDS is available\r
+debug(13) <= eds_buf_full; -- apv_trgctrl => EDS buffer is full\r
+debug(12 downto 8) <= eds_buf_level; \r
+-- timing trigger signals\r
+debug(7) <= timing_trg_found; -- apv_trgctrl -> endpoint => timing trigger has arrived\r
+debug(6) <= lvl1_trg_received; -- endpoint -> apv_trgctrl => LVL1 trigger packet has arrived\r
+debug(5) <= lvl1_trg_missing; -- apv_trgctrl -> endpoint => two consecutive timing triggers found\r
+debug(4) <= lvl1_trg_release; -- apv_trgctrl -> endpoint => release LVL1 busy \r
+debug(3 downto 0) <= lvl1_trg_number(3 downto 0);\r
+\r
+\r
+----------------------------------------------\r
+-- mixed status and control bit definitions --\r
+----------------------------------------------\r
+\r
+-- Common status register\r
+common_stat_reg(63 downto 48) <= (others => '0'); -- LVL2 counter\r
+common_stat_reg(47 downto 32) <= (others => '0'); -- LVL1 counter (doen by Jan)\r
+common_stat_reg(31 downto 20) <= x"000"; -- reserved for temp sensor\r
+common_stat_reg(19 downto 6) <= (others => '0');\r
+common_stat_reg(5) <= '0'; -- LVL2 counter mismatch\r
+common_stat_reg(4) <= '0'; -- LVL1 counter mismatch (done by Jan)\r
+common_stat_reg(3 downto 0) <= (others => '0');\r
+\r
+-- Control register bit padding\r
+ctrl_bithigh <= ctrl_lvl(31 downto 24) & x"0";\r
+ctrl_bitlow <= ctrl_lvl(23 downto 16) & x"0";\r
+ctrl_flathigh <= ctrl_lvl(15 downto 8) & x"0";\r
+ctrl_flatlow <= ctrl_lvl(7 downto 0) & x"0";\r
+\r
+-- LVDS driver enable\r
+ena_lvds(0) <= adc_on(4) or lvds_on(4); \r
+ena_lvds(1) <= adc_on(3) or lvds_on(3);\r
+ena_lvds(2) <= adc_on(5) or lvds_on(5);\r
+ena_lvds(3) <= adc_on(2) or lvds_on(2);\r
+ena_lvds(4) <= adc_on(6) or lvds_on(6);\r
+ena_lvds(5) <= adc_on(1) or lvds_on(1);\r
+ena_lvds(6) <= adc_on(7) or lvds_on(7);\r
+ena_lvds(7) <= adc_on(0) or lvds_on(0);\r
+ \r
+enb_lvds(0) <= adc_on(13) or lvds_on(13);\r
+enb_lvds(1) <= adc_on(10) or lvds_on(10);\r
+enb_lvds(2) <= adc_on(12) or lvds_on(12);\r
+enb_lvds(3) <= adc_on(11) or lvds_on(11);\r
+enb_lvds(4) <= adc_on(15) or lvds_on(15);\r
+enb_lvds(5) <= adc_on(8) or lvds_on(8);\r
+enb_lvds(6) <= adc_on(14) or lvds_on(14);\r
+enb_lvds(7) <= adc_on(9) or lvds_on(9);\r
+\r
+bp_led <= '1'; -- LED is against GND!\r
+\r
+\r
+----------------------------------------\r
+-- internal slave bus -> slow control --\r
+----------------------------------------\r
+THE_SLAVE_BUS: slave_bus\r
+port map( CLK_IN => sysclk,\r
+ RESET_IN => global_sync_reset,\r
+ -- RegIO signals\r
+ REGIO_ADDR_IN => regio_addr,\r
+ REGIO_DATA_IN => regio_data_wr,\r
+ REGIO_DATA_OUT => regio_data_rd,\r
+ REGIO_READ_ENABLE_IN => regio_read_enable,\r
+ REGIO_WRITE_ENABLE_IN => regio_write_enable,\r
+ REGIO_TIMEOUT_IN => regio_timeout,\r
+ REGIO_DATAREADY_OUT => regio_dataready,\r
+ REGIO_WRITE_ACK_OUT => regio_write_ack,\r
+ REGIO_NO_MORE_DATA_OUT => regio_no_more_data,\r
+ REGIO_UNKNOWN_ADDR_OUT => regio_unknown_addr,\r
+ -- I2C connections\r
+ SDA_IN => apv_sda_in,\r
+ SDA_OUT => apv_sda_out,\r
+ SCL_IN => apv_scl_in,\r
+ SCL_OUT => apv_scl_out,\r
+ -- 1Wire connections\r
+ ONEWIRE_START_IN => '0', -- not used yet\r
+ ONEWIRE_INOUT(15 downto 8) => apv1_1w(7 downto 0),\r
+ ONEWIRE_INOUT(7 downto 0) => apv0_1w(7 downto 0),\r
+ BP_ONEWIRE_INOUT => bp_onewire,\r
+ -- SPI connections\r
+ SPI_CS_OUT => u_spi_cs,\r
+ SPI_SCK_OUT => u_spi_sck,\r
+ SPI_SDI_IN => u_spi_sdo,\r
+ SPI_SDO_OUT => u_spi_sdi,\r
+ -- ADC 0 SPI connections\r
+ SPI_ADC0_CS_OUT => adc0_cs,\r
+ SPI_ADC0_SCK_OUT => adc0_sck,\r
+ SPI_ADC0_SDO_OUT => adc0_sdi,\r
+ ADC0_PLL_LOCKED_IN => adc0_valid,\r
+ ADC0_PD_OUT => adc0_powerdown,\r
+ ADC0_RST_OUT => adc0_reset,\r
+ ADC0_DEL_OUT => adc0_iodelay,\r
+ ADC0_CLK_IN => clk_apv,\r
+ ADC0_DATA_IN => adc0_testdata,\r
+ ADC0_SEL_OUT => adc0_select,\r
+ APV0_RST_OUT => apv0_reset,\r
+ -- ADC 0 SPI connections\r
+ SPI_ADC1_CS_OUT => adc1_cs,\r
+ SPI_ADC1_SCK_OUT => adc1_sck,\r
+ SPI_ADC1_SDO_OUT => adc1_sdi,\r
+ ADC1_PLL_LOCKED_IN => adc1_valid,\r
+ ADC1_PD_OUT => adc1_powerdown,\r
+ ADC1_RST_OUT => adc1_reset,\r
+ ADC1_DEL_OUT => adc1_iodelay,\r
+ ADC1_CLK_IN => clk_apv,\r
+ ADC1_DATA_IN => adc1_testdata,\r
+ ADC1_SEL_OUT => adc1_select,\r
+ APV1_RST_OUT => apv1_reset,\r
+ -- backplane identifier\r
+ BACKPLANE_IN => bp_module_qq(2 downto 0),\r
+ -- pedestal interface\r
+ PED_ADDR_IN => buf_addr,\r
+ PED_DATA_0_OUT => ped_data(0),\r
+ PED_DATA_1_OUT => ped_data(1),\r
+ PED_DATA_2_OUT => ped_data(2),\r
+ PED_DATA_3_OUT => ped_data(3),\r
+ PED_DATA_4_OUT => ped_data(4),\r
+ PED_DATA_5_OUT => ped_data(5),\r
+ PED_DATA_6_OUT => ped_data(6),\r
+ PED_DATA_7_OUT => ped_data(7),\r
+ PED_DATA_8_OUT => ped_data(8),\r
+ PED_DATA_9_OUT => ped_data(9),\r
+ PED_DATA_10_OUT => ped_data(10),\r
+ PED_DATA_11_OUT => ped_data(11),\r
+ PED_DATA_12_OUT => ped_data(12),\r
+ PED_DATA_13_OUT => ped_data(13),\r
+ PED_DATA_14_OUT => ped_data(14),\r
+ PED_DATA_15_OUT => ped_data(15),\r
+ -- threshold interface\r
+ THR_ADDR_IN => thr_addr,\r
+ THR_DATA_0_OUT => thr_data(0),\r
+ THR_DATA_1_OUT => thr_data(1),\r
+ THR_DATA_2_OUT => thr_data(2),\r
+ THR_DATA_3_OUT => thr_data(3),\r
+ THR_DATA_4_OUT => thr_data(4),\r
+ THR_DATA_5_OUT => thr_data(5),\r
+ THR_DATA_6_OUT => thr_data(6),\r
+ THR_DATA_7_OUT => thr_data(7),\r
+ THR_DATA_8_OUT => thr_data(8),\r
+ THR_DATA_9_OUT => thr_data(9),\r
+ THR_DATA_10_OUT => thr_data(10),\r
+ THR_DATA_11_OUT => thr_data(11),\r
+ THR_DATA_12_OUT => thr_data(12),\r
+ THR_DATA_13_OUT => thr_data(13),\r
+ THR_DATA_14_OUT => thr_data(14),\r
+ THR_DATA_15_OUT => thr_data(15),\r
+ -- APV control / status\r
+ CTRL_0_OUT => adc_ctrl_reg(0),\r
+ CTRL_1_OUT => adc_ctrl_reg(1),\r
+ CTRL_2_OUT => adc_ctrl_reg(2),\r
+ CTRL_3_OUT => adc_ctrl_reg(3),\r
+ CTRL_4_OUT => adc_ctrl_reg(4),\r
+ CTRL_5_OUT => adc_ctrl_reg(5),\r
+ CTRL_6_OUT => adc_ctrl_reg(6),\r
+ CTRL_7_OUT => adc_ctrl_reg(7),\r
+ CTRL_8_OUT => adc_ctrl_reg(8),\r
+ CTRL_9_OUT => adc_ctrl_reg(9),\r
+ CTRL_10_OUT => adc_ctrl_reg(10),\r
+ CTRL_11_OUT => adc_ctrl_reg(11),\r
+ CTRL_12_OUT => adc_ctrl_reg(12),\r
+ CTRL_13_OUT => adc_ctrl_reg(13),\r
+ CTRL_14_OUT => adc_ctrl_reg(14),\r
+ CTRL_15_OUT => adc_ctrl_reg(15),\r
+ STAT_0_IN => adc_stat_reg(0),\r
+ STAT_1_IN => adc_stat_reg(1),\r
+ STAT_2_IN => adc_stat_reg(2),\r
+ STAT_3_IN => adc_stat_reg(3),\r
+ STAT_4_IN => adc_stat_reg(4),\r
+ STAT_5_IN => adc_stat_reg(5),\r
+ STAT_6_IN => adc_stat_reg(6),\r
+ STAT_7_IN => adc_stat_reg(7),\r
+ STAT_8_IN => adc_stat_reg(8),\r
+ STAT_9_IN => adc_stat_reg(9),\r
+ STAT_10_IN => adc_stat_reg(10),\r
+ STAT_11_IN => adc_stat_reg(11),\r
+ STAT_12_IN => adc_stat_reg(12),\r
+ STAT_13_IN => adc_stat_reg(13),\r
+ STAT_14_IN => adc_stat_reg(14),\r
+ STAT_15_IN => adc_stat_reg(15),\r
+ -- some control signals\r
+ CTRL_LVL_OUT => ctrl_lvl,\r
+ CTRL_TRG_OUT => ctrl_trg,\r
+ CTRL_PLL_OUT => ctrl_pll,\r
+ STATUS_PLL_IN => status_pll,\r
+ -- temporary stuff \r
+ TEST_REG_IN => test_reg, -- short cut \r
+ TEST_REG_OUT => test_reg,\r
+ -- Debug \r
+ DEBUG_OUT => slave_debug, --open\r
+ STAT => open\r
+ ); \r
+\r
+-- PLL status register \r
+status_pll(15) <= clk100m_locked;\r
+status_pll(14) <= clk40m_locked;\r
+status_pll(13) <= adc1_valid;\r
+status_pll(12) <= adc0_valid;\r
+status_pll(11 downto 8) <= (others => '0');\r
+status_pll(7) <= '0'; -- make it human readable\r
+status_pll(6 downto 4) <= bp_sector_qq(2 downto 0); -- given by backplane DIP switch, for readback only\r
+status_pll(3) <= '0'; -- make it human readable\r
+status_pll(2 downto 0) <= bp_module_qq(2 downto 0); -- given by backplane DIP switch, for readback only\r
+\r
+-- Common status register, do not use.\r
+simple_status(127 downto 104) <= (others => '0');\r
+simple_status(103 downto 96) <= trgctrl_debug(39 downto 32);\r
+simple_status(95 downto 64) <= trgctrl_debug(31 downto 0);\r
+simple_status(63 downto 32) <= (others => '0');\r
+simple_status(31 downto 16) <= local_lvl2_counter;\r
+simple_status(15 downto 0) <= local_lvl1_counter;\r
+\r
+-- all APVs are reset together\r
+apv_reset <= apv0_reset or apv1_reset;\r
+\r
+-- APV status registers\r
+adc_stat_reg(15) <= buf_data(15)(37 downto 30) & raw_buf_debug(63 downto 60) & x"f";\r
+adc_stat_reg(14) <= buf_data(14)(37 downto 30) & raw_buf_debug(59 downto 56) & x"e";\r
+adc_stat_reg(13) <= buf_data(13)(37 downto 30) & raw_buf_debug(55 downto 52) & x"d";\r
+adc_stat_reg(12) <= buf_data(12)(37 downto 30) & raw_buf_debug(51 downto 48) & x"c";\r
+adc_stat_reg(11) <= buf_data(11)(37 downto 30) & raw_buf_debug(47 downto 44) & x"b";\r
+adc_stat_reg(10) <= buf_data(10)(37 downto 30) & raw_buf_debug(43 downto 40) & x"a";\r
+adc_stat_reg(9) <= buf_data(9)(37 downto 30) & raw_buf_debug(39 downto 36) & x"9";\r
+adc_stat_reg(8) <= buf_data(8)(37 downto 30) & raw_buf_debug(35 downto 32) & x"8";\r
+adc_stat_reg(7) <= buf_data(7)(37 downto 30) & raw_buf_debug(31 downto 28) & x"7";\r
+adc_stat_reg(6) <= buf_data(6)(37 downto 30) & raw_buf_debug(27 downto 24) & x"6";\r
+adc_stat_reg(5) <= buf_data(5)(37 downto 30) & raw_buf_debug(23 downto 20) & x"5";\r
+adc_stat_reg(4) <= buf_data(4)(37 downto 30) & raw_buf_debug(19 downto 16) & x"4";\r
+adc_stat_reg(3) <= buf_data(3)(37 downto 30) & raw_buf_debug(15 downto 12) & x"3";\r
+adc_stat_reg(2) <= buf_data(2)(37 downto 30) & raw_buf_debug(11 downto 8) & x"2";\r
+adc_stat_reg(1) <= buf_data(1)(37 downto 30) & raw_buf_debug(7 downto 4) & x"1";\r
+adc_stat_reg(0) <= buf_data(0)(37 downto 30) & raw_buf_debug(3 downto 0) & x"0";\r
+\r
+adc_on(15) <= adc_ctrl_reg(15)(0);\r
+adc_on(14) <= adc_ctrl_reg(14)(0);\r
+adc_on(13) <= adc_ctrl_reg(13)(0);\r
+adc_on(12) <= adc_ctrl_reg(12)(0);\r
+adc_on(11) <= adc_ctrl_reg(11)(0);\r
+adc_on(10) <= adc_ctrl_reg(10)(0);\r
+adc_on(9) <= adc_ctrl_reg(9)(0);\r
+adc_on(8) <= adc_ctrl_reg(8)(0);\r
+adc_on(7) <= adc_ctrl_reg(7)(0);\r
+adc_on(6) <= adc_ctrl_reg(6)(0);\r
+adc_on(5) <= adc_ctrl_reg(5)(0);\r
+adc_on(4) <= adc_ctrl_reg(4)(0);\r
+adc_on(3) <= adc_ctrl_reg(3)(0);\r
+adc_on(2) <= adc_ctrl_reg(2)(0);\r
+adc_on(1) <= adc_ctrl_reg(1)(0);\r
+adc_on(0) <= adc_ctrl_reg(0)(0);\r
+\r
+lvds_on(15) <= adc_ctrl_reg(15)(1);\r
+lvds_on(14) <= adc_ctrl_reg(14)(1);\r
+lvds_on(13) <= adc_ctrl_reg(13)(1);\r
+lvds_on(12) <= adc_ctrl_reg(12)(1);\r
+lvds_on(11) <= adc_ctrl_reg(11)(1);\r
+lvds_on(10) <= adc_ctrl_reg(10)(1);\r
+lvds_on(9) <= adc_ctrl_reg(9)(1);\r
+lvds_on(8) <= adc_ctrl_reg(8)(1);\r
+lvds_on(7) <= adc_ctrl_reg(7)(1);\r
+lvds_on(6) <= adc_ctrl_reg(6)(1);\r
+lvds_on(5) <= adc_ctrl_reg(5)(1);\r
+lvds_on(4) <= adc_ctrl_reg(4)(1);\r
+lvds_on(3) <= adc_ctrl_reg(3)(1);\r
+lvds_on(2) <= adc_ctrl_reg(2)(1);\r
+lvds_on(1) <= adc_ctrl_reg(1)(1);\r
+lvds_on(0) <= adc_ctrl_reg(0)(1);\r
+\r
+\r
+----------------------------------------\r
+-- IPU endpoint for data transport --\r
+----------------------------------------\r
+THE_IPU_STAGE: ipu_fifo_stage \r
+port map( CLK_IN => sysclk,\r
+ RESET_IN => global_sync_reset,\r
+ -- Slow control signals \r
+ SECTOR_IN => bp_sector_qq(2 downto 0), \r
+ MODULE_IN => bp_module_qq(2 downto 0), \r
+ -- IPU channel connections \r
+ IPU_NUMBER_IN => ipu_number,\r
+ IPU_INFORMATION_IN => ipu_information,\r
+ IPU_START_READOUT_IN => ipu_start_readout,\r
+ IPU_DATA_OUT => ipu_data,\r
+ IPU_DATAREADY_OUT => ipu_dataready,\r
+ IPU_READOUT_FINISHED_OUT => ipu_readout_finished,\r
+ IPU_READ_IN => ipu_read,\r
+ IPU_LENGTH_OUT => ipu_length,\r
+ IPU_ERROR_PATTERN_OUT => ipu_error_pattern,\r
+ LVL2_COUNTER_OUT => local_lvl2_counter,\r
+ -- DHDR buffer input \r
+ DHDR_DATA_IN => dhdr_data,\r
+ DHDR_LENGTH_IN => dhdr_length,\r
+ DHDR_STORE_IN => dhdr_store,\r
+ DHDR_BUF_FULL_OUT => dhdr_buf_full,\r
+ -- processed data input\r
+ FIFO_START_IN => fifo_start,\r
+ FIFO_0_DATA_IN => fifo_data(0),\r
+ FIFO_1_DATA_IN => fifo_data(1),\r
+ FIFO_2_DATA_IN => fifo_data(2),\r
+ FIFO_3_DATA_IN => fifo_data(3),\r
+ FIFO_4_DATA_IN => fifo_data(4),\r
+ FIFO_5_DATA_IN => fifo_data(5),\r
+ FIFO_6_DATA_IN => fifo_data(6),\r
+ FIFO_7_DATA_IN => fifo_data(7),\r
+ FIFO_8_DATA_IN => fifo_data(8),\r
+ FIFO_9_DATA_IN => fifo_data(9),\r
+ FIFO_10_DATA_IN => fifo_data(10),\r
+ FIFO_11_DATA_IN => fifo_data(11),\r
+ FIFO_12_DATA_IN => fifo_data(12),\r
+ FIFO_13_DATA_IN => fifo_data(13),\r
+ FIFO_14_DATA_IN => fifo_data(14),\r
+ FIFO_15_DATA_IN => fifo_data(15),\r
+ FIFO_WE_IN => fifo_we,\r
+ FIFO_DONE_IN => fifo_done,\r
+ -- Debug signals\r
+ DBG_BSM_OUT => open,\r
+ DBG_OUT => fifo_debug --open\r
+ );\r
+\r
+\r
+----------------------------------------\r
+-- Data processing unit --\r
+----------------------------------------\r
+THE_PED_CORR_STAGE: ped_corr_ctrl\r
+port map( CLK_IN => sysclk,\r
+ RESET_IN => global_sync_reset,\r
+ EDS_DATA_IN => eds_data,\r
+ EDS_AVAIL_IN => eds_avail,\r
+ EDS_DONE_OUT => eds_done,\r
+ EVT_TYPE_IN => b"000", -- BUG\r
+ -- DHDR information -- to next stage\r
+ DHDR_DATA_OUT => dhdr_data,\r
+ DHDR_LENGTH_OUT => dhdr_length,\r
+ DHDR_STORE_OUT => dhdr_store,\r
+ DHDR_BUF_FULL_IN => dhdr_buf_full,\r
+ -- data buffers -- from raw_buf_stage\r
+ BUF_ADDR_OUT => buf_addr,\r
+ BUF_DONE_OUT => buf_done,\r
+ BUF_TICK_IN => buf_tick,\r
+ BUF_START_IN => buf_start,\r
+ -- raw data\r
+ BUF_0_DATA_IN => buf_data(0),\r
+ BUF_1_DATA_IN => buf_data(1),\r
+ BUF_2_DATA_IN => buf_data(2),\r
+ BUF_3_DATA_IN => buf_data(3),\r
+ BUF_4_DATA_IN => buf_data(4),\r
+ BUF_5_DATA_IN => buf_data(5),\r
+ BUF_6_DATA_IN => buf_data(6),\r
+ BUF_7_DATA_IN => buf_data(7),\r
+ BUF_8_DATA_IN => buf_data(8),\r
+ BUF_9_DATA_IN => buf_data(9),\r
+ BUF_10_DATA_IN => buf_data(10),\r
+ BUF_11_DATA_IN => buf_data(11),\r
+ BUF_12_DATA_IN => buf_data(12),\r
+ BUF_13_DATA_IN => buf_data(13),\r
+ BUF_14_DATA_IN => buf_data(14),\r
+ BUF_15_DATA_IN => buf_data(15),\r
+ -- Pedestal data \r
+ PED_ADDR_OUT => open, -- BUGBUGBUG\r
+ PED_0_DATA_IN => ped_data(0),\r
+ PED_1_DATA_IN => ped_data(1),\r
+ PED_2_DATA_IN => ped_data(2),\r
+ PED_3_DATA_IN => ped_data(3),\r
+ PED_4_DATA_IN => ped_data(4),\r
+ PED_5_DATA_IN => ped_data(5),\r
+ PED_6_DATA_IN => ped_data(6),\r
+ PED_7_DATA_IN => ped_data(7),\r
+ PED_8_DATA_IN => ped_data(8),\r
+ PED_9_DATA_IN => ped_data(9),\r
+ PED_10_DATA_IN => ped_data(10),\r
+ PED_11_DATA_IN => ped_data(11),\r
+ PED_12_DATA_IN => ped_data(12),\r
+ PED_13_DATA_IN => ped_data(13),\r
+ PED_14_DATA_IN => ped_data(14),\r
+ PED_15_DATA_IN => ped_data(15),\r
+ -- Threshold data\r
+ THR_ADDR_OUT => thr_addr,\r
+ THR_0_DATA_IN => thr_data(0),\r
+ THR_1_DATA_IN => thr_data(1),\r
+ THR_2_DATA_IN => thr_data(2),\r
+ THR_3_DATA_IN => thr_data(3),\r
+ THR_4_DATA_IN => thr_data(4),\r
+ THR_5_DATA_IN => thr_data(5),\r
+ THR_6_DATA_IN => thr_data(6),\r
+ THR_7_DATA_IN => thr_data(7),\r
+ THR_8_DATA_IN => thr_data(8),\r
+ THR_9_DATA_IN => thr_data(9),\r
+ THR_10_DATA_IN => thr_data(10),\r
+ THR_11_DATA_IN => thr_data(11),\r
+ THR_12_DATA_IN => thr_data(12),\r
+ THR_13_DATA_IN => thr_data(13),\r
+ THR_14_DATA_IN => thr_data(14),\r
+ THR_15_DATA_IN => thr_data(15),\r
+ -- processed data\r
+ FIFO_START_OUT => fifo_start,\r
+ FIFO_0_DATA_OUT => fifo_data(0),\r
+ FIFO_1_DATA_OUT => fifo_data(1),\r
+ FIFO_2_DATA_OUT => fifo_data(2),\r
+ FIFO_3_DATA_OUT => fifo_data(3),\r
+ FIFO_4_DATA_OUT => fifo_data(4),\r
+ FIFO_5_DATA_OUT => fifo_data(5),\r
+ FIFO_6_DATA_OUT => fifo_data(6),\r
+ FIFO_7_DATA_OUT => fifo_data(7),\r
+ FIFO_8_DATA_OUT => fifo_data(8),\r
+ FIFO_9_DATA_OUT => fifo_data(9),\r
+ FIFO_10_DATA_OUT => fifo_data(10),\r
+ FIFO_11_DATA_OUT => fifo_data(11),\r
+ FIFO_12_DATA_OUT => fifo_data(12),\r
+ FIFO_13_DATA_OUT => fifo_data(13),\r
+ FIFO_14_DATA_OUT => fifo_data(14),\r
+ FIFO_15_DATA_OUT => fifo_data(15),\r
+ FIFO_WE_OUT => fifo_we,\r
+ FIFO_DONE_OUT => fifo_done,\r
+ -- Debug signals\r
+ DBG_BSM_OUT => open,\r
+ DBG_OUT => open\r
+ );\r
+\r
+\r
+------------------------------------------\r
+-- Raw data processing and storage unit --\r
+------------------------------------------\r
+THE_RAW_BUF_STAGE: raw_buf_stage_new\r
+port map( CLK_IN => sysclk,\r
+ CLK_APV_IN => clk_apv,\r
+ RESET_IN => reset_by_trb,\r
+ -- trigger related signals\r
+ APV_RESET_IN => apv_reset, -- (100MHz clock)\r
+ APV_SYNC_IN => apv_sync, -- (40MHz APV clock)\r
+ APV_FRAME_REQD_IN => apv_frame_reqd, -- (100MHz clock)\r
+ -- ADC0 signals\r
+ ADC0_VALID_IN => adc0_valid,\r
+ ADC0_0_DATA_IN => adc_data(0),\r
+ ADC0_1_DATA_IN => adc_data(1),\r
+ ADC0_2_DATA_IN => adc_data(2),\r
+ ADC0_3_DATA_IN => adc_data(3),\r
+ ADC0_4_DATA_IN => adc_data(4),\r
+ ADC0_5_DATA_IN => adc_data(5),\r
+ ADC0_6_DATA_IN => adc_data(6),\r
+ ADC0_7_DATA_IN => adc_data(7),\r
+ -- ADC1 signals\r
+ ADC1_VALID_IN => adc1_valid,\r
+ ADC1_0_DATA_IN => adc_data(8),\r
+ ADC1_1_DATA_IN => adc_data(9),\r
+ ADC1_2_DATA_IN => adc_data(10),\r
+ ADC1_3_DATA_IN => adc_data(11),\r
+ ADC1_4_DATA_IN => adc_data(12),\r
+ ADC1_5_DATA_IN => adc_data(13),\r
+ ADC1_6_DATA_IN => adc_data(14),\r
+ ADC1_7_DATA_IN => adc_data(15),\r
+ -- Slow control registers\r
+ MAX_TRG_NUM_IN => maximum_trg, -- automatically determined\r
+ BIT_LOW_IN => ctrl_bitlow, -- from slow control\r
+ BIT_HIGH_IN => ctrl_bithigh, -- from slow control\r
+ FL_LOW_IN => ctrl_flatlow, -- from slow control\r
+ FL_HIGH_IN => ctrl_flathigh, -- from slow control\r
+ APV_ON_IN => adc_on,\r
+ -- 100MHZ synchronous interface\r
+ -- APV raw buffers\r
+ BUF_FULL_OUT => raw_buf_full, -- NEW NEW NEW\r
+ BUF_ADDR_IN => buf_addr, -- from ped_corr_ctrl\r
+ BUF_DONE_IN => buf_done, -- from ped_corr_ctrl\r
+ BUF_TICK_OUT => buf_tick,\r
+ BUF_START_OUT => buf_start,\r
+ BUF_READY_OUT => buf_ready,\r
+ BUF_0_DATA_OUT => buf_data(0), -- to ped_corr_ctrl \r
+ BUF_1_DATA_OUT => buf_data(1), -- to ped_corr_ctrl\r
+ BUF_2_DATA_OUT => buf_data(2), -- to ped_corr_ctrl\r
+ BUF_3_DATA_OUT => buf_data(3), -- to ped_corr_ctrl\r
+ BUF_4_DATA_OUT => buf_data(4), -- to ped_corr_ctrl\r
+ BUF_5_DATA_OUT => buf_data(5), -- to ped_corr_ctrl\r
+ BUF_6_DATA_OUT => buf_data(6), -- to ped_corr_ctrl\r
+ BUF_7_DATA_OUT => buf_data(7), -- to ped_corr_ctrl\r
+ BUF_8_DATA_OUT => buf_data(8), -- to ped_corr_ctrl\r
+ BUF_9_DATA_OUT => buf_data(9), -- to ped_corr_ctrl\r
+ BUF_10_DATA_OUT => buf_data(10), -- to ped_corr_ctrl\r
+ BUF_11_DATA_OUT => buf_data(11), -- to ped_corr_ctrl\r
+ BUF_12_DATA_OUT => buf_data(12), -- to ped_corr_ctrl\r
+ BUF_13_DATA_OUT => buf_data(13), -- to ped_corr_ctrl\r
+ BUF_14_DATA_OUT => buf_data(14), -- to ped_corr_ctrl\r
+ BUF_15_DATA_OUT => buf_data(15), -- to ped_corr_ctrl\r
+ -- Debug signals\r
+ DEBUG_OUT => raw_buf_debug --open\r
+ );\r
+\r
+\r
+----------------------------------------\r
+-- ADC1 data handler --\r
+----------------------------------------\r
+THE_ADC1_HANDLER: adc_data_handler_new \r
+port map( RESET_IN => reset_by_trb,\r
+ ADC_LCLK_IN => adc1_lclk,\r
+ ADC_ADCLK_IN => adc1_adclk,\r
+ ADC_CHNL_IN => adc1_out,\r
+ PLL_CTRL_IN => adc1_iodelay,\r
+ ADC_DATA7_OUT => adc_raw_data(15),\r
+ ADC_DATA6_OUT => adc_raw_data(14),\r
+ ADC_DATA5_OUT => adc_raw_data(13),\r
+ ADC_DATA4_OUT => adc_raw_data(12),\r
+ ADC_DATA3_OUT => adc_raw_data(11),\r
+ ADC_DATA2_OUT => adc_raw_data(10),\r
+ ADC_DATA1_OUT => adc_raw_data(9),\r
+ ADC_DATA0_OUT => adc_raw_data(8),\r
+ ADC_CE_OUT => adc1_ce,\r
+ ADC_VALID_OUT => adc1_valid,\r
+ DEBUG_OUT => open\r
+ );\r
+\r
+\r
+----------------------------------------\r
+-- ADC1 clock domain crossover --\r
+----------------------------------------\r
+THE_ADC1_CROSSOVER: adc_crossover\r
+port map( CLK_APV_IN => clk_apv,\r
+ RESET_IN => global_sync_reset,\r
+ -- ADC clock domain signals\r
+ ADC_CLK_IN => adc1_lclk,\r
+ ADC_CE_IN => adc1_ce,\r
+ ADC_DATA_VALID_IN => adc1_valid,\r
+ ADC_DATA_7_IN => adc_raw_data(15),\r
+ ADC_DATA_6_IN => adc_raw_data(14),\r
+ ADC_DATA_5_IN => adc_raw_data(13),\r
+ ADC_DATA_4_IN => adc_raw_data(12),\r
+ ADC_DATA_3_IN => adc_raw_data(11),\r
+ ADC_DATA_2_IN => adc_raw_data(10),\r
+ ADC_DATA_1_IN => adc_raw_data(9),\r
+ ADC_DATA_0_IN => adc_raw_data(8),\r
+ LEVEL_WR_OUT => open,\r
+ -- APV clock domain signals\r
+ APV_DATA_7_OUT => adc_data(15),\r
+ APV_DATA_6_OUT => adc_data(14),\r
+ APV_DATA_5_OUT => adc_data(13),\r
+ APV_DATA_4_OUT => adc_data(12),\r
+ APV_DATA_3_OUT => adc_data(11),\r
+ APV_DATA_2_OUT => adc_data(10),\r
+ APV_DATA_1_OUT => adc_data(9),\r
+ APV_DATA_0_OUT => adc_data(8),\r
+ APV_DATA_VALID_OUT => open,\r
+ LEVEL_RD_OUT => open,\r
+ -- Debug signals\r
+ DEBUG_OUT => open\r
+ );\r
+\r
+\r
+----------------------------------------\r
+-- ADC1 test data multiplexer --\r
+----------------------------------------\r
+THE_ADC_1_SELECT: adc_channel_select\r
+port map( RESET_IN => reset_by_trb,\r
+ ADC_CLK_IN => clk_apv,\r
+ ADC_SEL_IN => adc1_select,\r
+ ADC_7_IN => adc_data(15),\r
+ ADC_6_IN => adc_data(14),\r
+ ADC_5_IN => adc_data(13),\r
+ ADC_4_IN => adc_data(12),\r
+ ADC_3_IN => adc_data(11),\r
+ ADC_2_IN => adc_data(10),\r
+ ADC_1_IN => adc_data(9),\r
+ ADC_0_IN => adc_data(8),\r
+ ADC_CH_OUT => adc1_testdata,\r
+ DEBUG_OUT => open\r
+ );\r
+\r
+\r
+----------------------------------------\r
+-- ADC0 data handler --\r
+----------------------------------------\r
+THE_ADC0_HANDLER: adc_data_handler_new \r
+port map( RESET_IN => reset_by_trb,\r
+ ADC_LCLK_IN => adc0_lclk,\r
+ ADC_ADCLK_IN => adc0_adclk,\r
+ ADC_CHNL_IN => adc0_out,\r
+ PLL_CTRL_IN => adc0_iodelay,\r
+ ADC_DATA7_OUT => adc_raw_data(7),\r
+ ADC_DATA6_OUT => adc_raw_data(6),\r
+ ADC_DATA5_OUT => adc_raw_data(5),\r
+ ADC_DATA4_OUT => adc_raw_data(4),\r
+ ADC_DATA3_OUT => adc_raw_data(3),\r
+ ADC_DATA2_OUT => adc_raw_data(2),\r
+ ADC_DATA1_OUT => adc_raw_data(1),\r
+ ADC_DATA0_OUT => adc_raw_data(0),\r
+ ADC_CE_OUT => adc0_ce,\r
+ ADC_VALID_OUT => adc0_valid,\r
+ DEBUG_OUT => open\r
+ );\r
+\r
+\r
+----------------------------------------\r
+-- ADC0 clock domain crossover --\r
+----------------------------------------\r
+THE_ADC0_CROSSOVER: adc_crossover\r
+port map( CLK_APV_IN => clk_apv,\r
+ RESET_IN => global_sync_reset,\r
+ -- ADC clock domain signals\r
+ ADC_CLK_IN => adc0_lclk,\r
+ ADC_CE_IN => adc0_ce,\r
+ ADC_DATA_VALID_IN => adc0_valid,\r
+ ADC_DATA_7_IN => adc_raw_data(7),\r
+ ADC_DATA_6_IN => adc_raw_data(6),\r
+ ADC_DATA_5_IN => adc_raw_data(5),\r
+ ADC_DATA_4_IN => adc_raw_data(4),\r
+ ADC_DATA_3_IN => adc_raw_data(3),\r
+ ADC_DATA_2_IN => adc_raw_data(2),\r
+ ADC_DATA_1_IN => adc_raw_data(1),\r
+ ADC_DATA_0_IN => adc_raw_data(0),\r
+ LEVEL_WR_OUT => open,\r
+ -- APV clock domain signals\r
+ APV_DATA_7_OUT => adc_data(7),\r
+ APV_DATA_6_OUT => adc_data(6),\r
+ APV_DATA_5_OUT => adc_data(5),\r
+ APV_DATA_4_OUT => adc_data(4),\r
+ APV_DATA_3_OUT => adc_data(3),\r
+ APV_DATA_2_OUT => adc_data(2),\r
+ APV_DATA_1_OUT => adc_data(1),\r
+ APV_DATA_0_OUT => adc_data(0),\r
+ APV_DATA_VALID_OUT => open,\r
+ LEVEL_RD_OUT => open,\r
+ -- Debug signals\r
+ DEBUG_OUT => open\r
+ );\r
+\r
+ \r
+----------------------------------------\r
+-- ADC0 test data multiplexer --\r
+----------------------------------------\r
+THE_ADC_0_SELECT: adc_channel_select\r
+port map( RESET_IN => reset_by_trb,\r
+ ADC_CLK_IN => clk_apv,\r
+ ADC_SEL_IN => adc0_select,\r
+ ADC_7_IN => adc_data(7),\r
+ ADC_6_IN => adc_data(6),\r
+ ADC_5_IN => adc_data(5),\r
+ ADC_4_IN => adc_data(4),\r
+ ADC_3_IN => adc_data(3),\r
+ ADC_2_IN => adc_data(2),\r
+ ADC_1_IN => adc_data(1),\r
+ ADC_0_IN => adc_data(0),\r
+ ADC_CH_OUT => adc0_testdata,\r
+ DEBUG_OUT => open\r
+ );\r
+\r
+\r
+----------------------------------------\r
+-- Trigger handler (APV specific) --\r
+----------------------------------------\r
+THE_APV_TRGCTRL: apv_trgctrl\r
+port map( CLK_IN => sysclk,\r
+ RESET_IN => global_sync_reset,\r
+ CLK_APV_IN => clk_apv,\r
+ -- Triggers\r
+ SYNC_TRG_IN => common_ctrl_reg(31), -- slow control pulse\r
+ TIME_TRG_IN => ext_in, -- external trigger inputs\r
+ TRB_TRG_IN => common_ctrl_reg(19 downto 16), -- slow control triggers\r
+ STILL_BUSY_IN => raw_buf_full, -- if no more frames are free in first stage buffer we must cease triggers.\r
+ TRG_FOUND_OUT => timing_trg_found, -- to TRB LVL1 endpoint\r
+ -- slow control settings\r
+ TRG_MAX_OUT => maximum_trg,\r
+ TRG_3_TODO_IN => ctrl_trg(31 downto 28), -- from slow control\r
+ TRG_3_DELAY_IN => ctrl_trg(27 downto 24), -- from slow control\r
+ TRG_2_TODO_IN => ctrl_trg(23 downto 20), -- from slow control\r
+ TRG_2_DELAY_IN => ctrl_trg(19 downto 16), -- from slow control\r
+ TRG_1_TODO_IN => ctrl_trg(15 downto 12), -- from slow control\r
+ TRG_1_DELAY_IN => ctrl_trg(11 downto 8), -- from slow control\r
+ TRG_0_TODO_IN => ctrl_trg(7 downto 4), -- from slow control\r
+ TRG_0_DELAY_IN => ctrl_trg(3 downto 0), -- from slow control\r
+ TRG_SETUP_IN => ctrl_pll(15 downto 8), -- from slow control\r
+ -- TRB LVL1 signals\r
+ TRB_TTAG_IN => lvl1_trg_number, -- from TRB LVL1 endpoint\r
+ TRB_TRND_IN => lvl1_trg_code, -- from TRB LVL1 endpoint\r
+ TRB_TTYPE_IN => lvl1_trg_type, -- from TRB LVL1 endpoint\r
+ TRB_TRGRCVD_IN => lvl1_trg_received, -- from TRB LVL1 endpoint\r
+ TRB_MISSING_OUT => lvl1_trg_missing,\r
+ TRB_RELEASE_OUT => lvl1_trg_release, -- to TRB LVL1 endpoint\r
+ TRB_RST_COUNTER_IN => common_ctrl_reg(30), -- depreciated!\r
+ TRB_COUNTER_OUT => local_lvl1_counter,\r
+ -- EDS signals\r
+ EDS_DATA_OUT => eds_data, -- to ped_corr_stage\r
+ EDS_AVAIL_OUT => eds_avail, -- to ped_corr_stage\r
+ EDS_DONE_IN => eds_done, -- from ped_corr_stage\r
+ EDS_FULL_OUT => eds_buf_full,\r
+ EDS_LEVEL_OUT => eds_buf_level,\r
+ FRM_REQD_OUT => apv_frame_reqd, -- to raw_buf_stage (100MHz clock)\r
+ -- APV signals \r
+ APV_TRG_OUT => apv_trg, -- to APV frontends (40MHz APV clock)\r
+ APV_SYNC_OUT => apv_sync, -- to raw_buf_stage (40MHz APV clock)\r
+ DEBUG_OUT => trgctrl_debug\r
+ );\r
+\r
+\r
+----------------------------------------\r
+-- ADC signals --\r
+----------------------------------------\r
+adc1_rst <= adc1_reset;\r
+adc1_pd <= adc1_powerdown;\r
+\r
+THE_ADC1CLK_OUT: ODDRXC\r
+port map( DA => '1',\r
+ DB => '0',\r
+ CLK => clk_adc,\r
+ RST => '0',\r
+ Q => adc1_clk\r
+ );\r
+\r
+adc0_rst <= adc0_reset;\r
+adc0_pd <= adc0_powerdown;\r
+\r
+THE_ADC0CLK_OUT: ODDRXC\r
+port map( DA => '1',\r
+ DB => '0',\r
+ CLK => clk_adc,\r
+ RST => '0',\r
+ Q => adc0_clk\r
+ );\r
+\r
+\r
+----------------------------------------\r
+-- APV signals --\r
+----------------------------------------\r
+-- SDA line output\r
+apv0_sda <= '0' when (apv_sda_out = '0') else 'Z';\r
+apv1_sda <= '0' when (apv_sda_out = '0') else 'Z';\r
+-- SDA line input (wired OR negative logic)\r
+apv_sda_in <= apv0_sda and apv1_sda;\r
+\r
+-- SCL line output\r
+apv0_scl <= '0' when (apv_scl_out = '0') else 'Z';\r
+apv1_scl <= '0' when (apv_scl_out = '0') else 'Z';\r
+-- SCL line input (wired OR negative logic)\r
+apv_scl_in <= apv0_scl and apv1_scl;\r
+\r
+-- Reset signal with correct polarity\r
+apv0_rst <= not apv_reset;\r
+apv1_rst <= not apv_reset;\r
+\r
+-- CLK and TRG signal\r
+-- CLK is shifted to meet timing constraints of APV\r
+THE_APV0ACLK_OUT: ODDRXC\r
+port map( DA => '0', \r
+ DB => '1', \r
+ CLK => clk_apv,\r
+ RST => '0',\r
+ Q => apv0a_clk\r
+ );\r
+\r
+THE_APV0BCLK_OUT: ODDRXC\r
+port map( DA => '0',\r
+ DB => '1',\r
+ CLK => clk_apv,\r
+ RST => '0',\r
+ Q => apv0b_clk\r
+ );\r
+\r
+THE_APV1ACLK_OUT: ODDRXC\r
+port map( DA => '0',\r
+ DB => '1',\r
+ CLK => clk_apv,\r
+ RST => '0',\r
+ Q => apv1a_clk\r
+ );\r
+\r
+THE_APV1BCLK_OUT: ODDRXC\r
+port map( DA => '0',\r
+ DB => '1',\r
+ CLK => clk_apv,\r
+ RST => '0',\r
+ Q => apv1b_clk\r
+ );\r
+\r
+THE_APV0ATRG_OUT: ODDRXC\r
+port map( DA => apv_trg,\r
+ DB => apv_trg,\r
+ CLK => clk_apv,\r
+ RST => '0',\r
+ Q => apv0a_trg\r
+ );\r
+THE_APV0BTRG_OUT: ODDRXC\r
+port map( DA => apv_trg,\r
+ DB => apv_trg,\r
+ CLK => clk_apv,\r
+ RST => '0',\r
+ Q => apv0b_trg\r
+ );\r
+THE_APV1ATRG_OUT: ODDRXC\r
+port map( DA => apv_trg,\r
+ DB => apv_trg,\r
+ CLK => clk_apv,\r
+ RST => '0',\r
+ Q => apv1a_trg\r
+ );\r
+THE_APV1BTRG_OUT: ODDRXC\r
+port map( DA => apv_trg,\r
+ DB => apv_trg,\r
+ CLK => clk_apv,\r
+ RST => '0',\r
+ Q => apv1b_trg\r
+ );\r
+\r
+\r
+----------------------------------------\r
+-- DIP switch input registers --\r
+----------------------------------------\r
+-- switch "OFF" => '1', switch "ON" => '0'; so invert it\r
+THE_BP_SYNC_PROC: process( sysclk )\r
+begin\r
+ if( rising_edge(sysclk) ) then\r
+ bp_module_qq <= bp_module_q;\r
+ bp_module_q <= not bp_module;\r
+ bp_sector_qq <= bp_sector_q;\r
+ bp_sector_q <= not bp_sector;\r
+ end if;\r
+end process THE_BP_SYNC_PROC;\r
+\r
+\r
+----------------------------------------\r
+-- Reboot handler (pulse triggered) --\r
+----------------------------------------\r
+THE_REBOOT_HANDLER: reboot_handler\r
+port map( RESET_IN => reset_by_trb,\r
+ CLK_IN => sysclk,\r
+ START_IN => common_ctrl_reg(15),\r
+ REBOOT_OUT => uc_reboot,\r
+ DEBUG_OUT => open\r
+ );\r
+\r
+\r
+----------------------------------------\r
+-- FPGA debug header driver --\r
+----------------------------------------\r
+THE_DBG_CLK_OUT: ODDRXC\r
+port map( DA => '1',\r
+ DB => '0',\r
+ CLK => debug_clk,\r
+ RST => '0',\r
+ Q => dbg_exp(43)\r
+ );\r
+ \r
+THE_DEBUG_REG_PROC: process( debug_clk )\r
+begin\r
+ if( rising_edge(debug_clk) ) then\r
+ dbg_exp(42 downto 0) <= debug_qq(42 downto 0);\r
+ debug_qq(42 downto 0) <= debug_q(42 downto 0);\r
+ debug_q(42 downto 0) <= debug(42 downto 0);\r
+ end if;\r
+end process THE_DEBUG_REG_PROC;\r
+\r
+\r
+----------------------------------------\r
+-- LED drivers --\r
+----------------------------------------\r
+fpga_led_adc(1) <= not adc1_valid; \r
+fpga_led_adc(0) <= not adc0_valid;\r
+fpga_led(6) <= not lsm_state_bits(0); -- LED "0"\r
+fpga_led(5) <= not lsm_state_bits(1); -- LED "1"\r
+fpga_led(4) <= not lsm_state_bits(2); -- LED "2"\r
+fpga_led(3) <= not lsm_state_bits(3); -- LED "3"\r
+fpga_led_pll <= not clk40m_locked;\r
+\r
+\r
+----------------------------------------\r
+-- "unused" pins --\r
+----------------------------------------\r
+\r
+end adcmv3;\r
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use IEEE.numeric_std.ALL;\r
+use IEEE.std_logic_UNSIGNED.ALL;\r
+\r
+--library work;\r
+--use work.trb_net_std.all;\r
+\r
+package adcmv3_components is\r
+\r
+ component raw_buf_stage_new is\r
+ port( CLK_IN : in std_logic; -- 100MHz local clock\r
+ CLK_APV_IN : in std_logic; -- 40MHz APV clock\r
+ RESET_IN : in std_logic; -- general reset (100MHz)\r
+ -- trigger related signals\r
+ APV_RESET_IN : in std_logic; -- APV reset signal (100MHz)\r
+ APV_SYNC_IN : in std_logic; -- APV sync trigger has been sent (40MHz)\r
+ APV_FRAME_REQD_IN : in std_logic; -- one APV frame has been requested (100MHz)\r
+ -- ADC0 signals\r
+ ADC0_VALID_IN : in std_logic; -- 40M reconstructed clock is valid\r
+ ADC0_0_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 0\r
+ ADC0_1_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 1\r
+ ADC0_2_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 2\r
+ ADC0_3_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 3\r
+ ADC0_4_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 4\r
+ ADC0_5_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 5\r
+ ADC0_6_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 6\r
+ ADC0_7_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 7\r
+ -- ADC1 signals\r
+ ADC1_VALID_IN : in std_logic; -- 40M reconstructed clock is valid\r
+ ADC1_0_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 0\r
+ ADC1_1_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 1\r
+ ADC1_2_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 2\r
+ ADC1_3_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 3\r
+ ADC1_4_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 4\r
+ ADC1_5_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 5\r
+ ADC1_6_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 6\r
+ ADC1_7_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 7\r
+ -- Slow control registers\r
+ MAX_TRG_NUM_IN : in std_logic_vector(3 downto 0); -- maximum number of triggers / event\r
+ BIT_LOW_IN : in std_logic_vector(11 downto 0); -- "bit low" threshold\r
+ BIT_HIGH_IN : in std_logic_vector(11 downto 0); -- "bit high" threshold\r
+ FL_LOW_IN : in std_logic_vector(11 downto 0); -- "flatline low" threshold\r
+ FL_HIGH_IN : in std_logic_vector(11 downto 0); -- "flatline high" threshold\r
+ APV_ON_IN : in std_logic_vector(15 downto 0); -- APV on/off bits from slow control\r
+ -- 100MHZ synchronous interface\r
+ -- APV raw buffers\r
+ BUF_FULL_OUT : out std_logic;\r
+ BUF_ADDR_IN : in std_logic_vector(6 downto 0);\r
+ BUF_DONE_IN : in std_logic;\r
+ BUF_TICK_OUT : out std_logic_vector(15 downto 0);\r
+ BUF_START_OUT : out std_logic_vector(15 downto 0);\r
+ BUF_READY_OUT : out std_logic_vector(15 downto 0);\r
+ BUF_0_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_1_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_2_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_3_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_4_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_5_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_6_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_7_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_8_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_9_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_10_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_11_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_12_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_13_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_14_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_15_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ -- Debug signals\r
+ DEBUG_OUT : out std_logic_vector(63 downto 0)\r
+ );\r
+ end component raw_buf_stage_new;\r
+ \r
+ component adc_data_handler_new is\r
+ port( RESET_IN : in std_logic;\r
+ ADC_LCLK_IN : in std_logic; -- LCLK from ADC\r
+ ADC_ADCLK_IN : in std_logic; -- ADCLK from ADC\r
+ ADC_CHNL_IN : in std_logic_vector(7 downto 0);\r
+ PLL_CTRL_IN : in std_logic_vector(3 downto 0);\r
+ ADC_DATA7_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_DATA6_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_DATA5_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_DATA4_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_DATA3_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_DATA2_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_DATA1_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_DATA0_OUT : out std_logic_vector(11 downto 0);\r
+ ADC_CE_OUT : out std_logic;\r
+ ADC_VALID_OUT : out std_logic;\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
+ end component adc_data_handler_new;\r
+\r
+ component adc_crossover is\r
+ port( CLK_APV_IN : in std_logic; -- APV 40MHz local clock\r
+ RESET_IN : in std_logic; -- general reset (100MHz)\r
+ -- ADC clock domain signals\r
+ ADC_CLK_IN : in std_logic;\r
+ ADC_CE_IN : in std_logic; -- in case we use 240MHz + write pulse...\r
+ ADC_DATA_VALID_IN : in std_logic;\r
+ ADC_DATA_7_IN : in std_logic_vector(11 downto 0);\r
+ ADC_DATA_6_IN : in std_logic_vector(11 downto 0);\r
+ ADC_DATA_5_IN : in std_logic_vector(11 downto 0);\r
+ ADC_DATA_4_IN : in std_logic_vector(11 downto 0);\r
+ ADC_DATA_3_IN : in std_logic_vector(11 downto 0);\r
+ ADC_DATA_2_IN : in std_logic_vector(11 downto 0);\r
+ ADC_DATA_1_IN : in std_logic_vector(11 downto 0);\r
+ ADC_DATA_0_IN : in std_logic_vector(11 downto 0);\r
+ LEVEL_WR_OUT : out std_logic_vector(4 downto 0);\r
+ -- APV clock domain signals\r
+ APV_DATA_7_OUT : out std_logic_vector(11 downto 0);\r
+ APV_DATA_6_OUT : out std_logic_vector(11 downto 0);\r
+ APV_DATA_5_OUT : out std_logic_vector(11 downto 0);\r
+ APV_DATA_4_OUT : out std_logic_vector(11 downto 0);\r
+ APV_DATA_3_OUT : out std_logic_vector(11 downto 0);\r
+ APV_DATA_2_OUT : out std_logic_vector(11 downto 0);\r
+ APV_DATA_1_OUT : out std_logic_vector(11 downto 0);\r
+ APV_DATA_0_OUT : out std_logic_vector(11 downto 0);\r
+ APV_DATA_VALID_OUT : out std_logic;\r
+ LEVEL_RD_OUT : out std_logic_vector(4 downto 0);\r
+ -- Debug signals\r
+ DEBUG_OUT : out std_logic_vector(31 downto 0)\r
+ );\r
+ end component adc_crossover;\r
+ \r
+ component crossover is\r
+ port( DATA : in std_logic_vector(95 downto 0);\r
+ WRCLOCK : in std_logic;\r
+ RDCLOCK : in std_logic;\r
+ WREN : in std_logic;\r
+ RDEN : in std_logic;\r
+ RESET : in std_logic; -- asynchronous reset! \r
+ RPRESET : in std_logic;\r
+ Q : out std_logic_vector(95 downto 0);\r
+ WCNT : out std_logic_vector(4 downto 0);\r
+ RCNT : out std_logic_vector(4 downto 0);\r
+ EMPTY : out std_logic;\r
+ FULL : out std_logic\r
+ );\r
+ end component crossover;\r
+\r
+ component slv_adc_la is\r
+ port( CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_ADDR_IN : in std_logic_vector(9 downto 0);\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- I/O to the backend\r
+ ADC_SEL_OUT : out std_logic_vector(2 downto 0); -- selects the ADC channel to snoop from\r
+ ADC_CLK_IN : in std_logic; -- ADC reconstructed clock\r
+ ADC_DATA_IN : in std_logic_vector(11 downto 0); -- ADC selected channel data\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+ );\r
+ end component slv_adc_la;\r
+\r
+-- NOT USED YET\r
+ component logic_analyzer is\r
+ port( CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- control signals\r
+ ARM_IN : in std_logic; -- arm the machine\r
+ TRG_IN : in std_logic; -- trigger the data acquisition\r
+ MAX_SAMPLE_IN : in std_logic_vector(9 downto 0); \r
+ -- status signals\r
+ SM_ADDR_OUT : out std_logic_vector(9 downto 0); -- sample RAM addresses\r
+ SM_CE_OUT : out std_logic;\r
+ SM_WE_OUT : out std_logic; -- write enable for sample RAM\r
+ CLEAR_OUT : out std_logic; -- sample memory is being cleared\r
+ RUN_OUT : out std_logic; -- ready for trigger\r
+ SAMPLE_OUT : out std_logic; -- data acquisition running\r
+ READY_OUT : out std_logic; -- data acquisition is finished\r
+ LAST_OUT : out std_logic; -- last data word of sampling\r
+ -- Status lines\r
+ BSM_OUT : out std_logic_vector(3 downto 0);\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+ );\r
+ end component logic_analyzer;\r
+\r
+ component onewire_spare_one is\r
+ port( ADDRESS : in std_logic_vector(2 downto 0); \r
+ Q : out std_logic_vector(3 downto 0)\r
+ );\r
+ end component onewire_spare_one;\r
+\r
+ component adc_onewire_map_mem is\r
+ port( ADDRESS : in std_logic_vector(6 downto 0); \r
+ Q : out std_logic_vector(3 downto 0)\r
+ );\r
+ end component adc_onewire_map_mem;\r
+\r
+ component adc_channel_select is\r
+ port( RESET_IN : in std_logic;\r
+ ADC_CLK_IN : in std_logic;\r
+ ADC_SEL_IN : in std_logic_vector(2 downto 0);\r
+ ADC_7_IN : in std_logic_vector(11 downto 0);\r
+ ADC_6_IN : in std_logic_vector(11 downto 0);\r
+ ADC_5_IN : in std_logic_vector(11 downto 0);\r
+ ADC_4_IN : in std_logic_vector(11 downto 0);\r
+ ADC_3_IN : in std_logic_vector(11 downto 0);\r
+ ADC_2_IN : in std_logic_vector(11 downto 0);\r
+ ADC_1_IN : in std_logic_vector(11 downto 0);\r
+ ADC_0_IN : in std_logic_vector(11 downto 0);\r
+ ADC_CH_OUT : out std_logic_vector(11 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
+ end component;\r
+\r
+ component slv_adc_snoop is\r
+ port( CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_ADDR_IN : in std_logic_vector(9 downto 0);\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- I/O to the backend\r
+ ADC_SEL_OUT : out std_logic_vector(2 downto 0); -- selects the ADC channel to snoop from\r
+ ADC_CLK_IN : in std_logic; -- ADC reconstructed clock\r
+ ADC_DATA_IN : in std_logic_vector(11 downto 0); -- ADC selected channel data\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+ );\r
+ end component;\r
+\r
+ component adc_snoop_mem is\r
+ port( WRADDRESS : in std_logic_vector(9 downto 0); \r
+ RDADDRESS : in std_logic_vector(9 downto 0); \r
+ DATA : in std_logic_vector(15 downto 0); \r
+ WE : in std_logic; \r
+ RDCLOCK : in std_logic; \r
+ RDCLOCKEN : in std_logic; \r
+ RESET : in std_logic; \r
+ WRCLOCK : in std_logic; \r
+ WRCLOCKEN : in std_logic; \r
+ Q : out std_logic_vector(15 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+ component max_data is\r
+ port( CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ TODO_3_IN : in std_logic_vector(3 downto 0);\r
+ TODO_2_IN : in std_logic_vector(3 downto 0);\r
+ TODO_1_IN : in std_logic_vector(3 downto 0);\r
+ TODO_0_IN : in std_logic_vector(3 downto 0);\r
+ TODO_MAX_OUT : out std_logic_vector(3 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
+ end component;\r
+\r
+ component comp4bit is\r
+ port( DATAA : in std_logic_vector(3 downto 0); \r
+ DATAB : in std_logic_vector(3 downto 0); \r
+ AGTB : out std_logic\r
+ );\r
+ end component;\r
+\r
+ component slv_register_bank is\r
+ generic( RESET_VALUE : std_logic_vector(15 downto 0) := x"0001" );\r
+ port( CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_ADDR_IN : in std_logic_vector(3 downto 0);\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- I/O to the backend\r
+ BACKPLANE_IN : in std_logic_vector(2 downto 0);\r
+ CTRL_0_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_1_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_2_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_3_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_4_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_5_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_6_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_7_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_8_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_9_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_10_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_11_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_12_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_13_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_14_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_15_OUT : out std_logic_vector(15 downto 0);\r
+ STAT_0_IN : in std_logic_vector(15 downto 0);\r
+ STAT_1_IN : in std_logic_vector(15 downto 0);\r
+ STAT_2_IN : in std_logic_vector(15 downto 0);\r
+ STAT_3_IN : in std_logic_vector(15 downto 0);\r
+ STAT_4_IN : in std_logic_vector(15 downto 0);\r
+ STAT_5_IN : in std_logic_vector(15 downto 0);\r
+ STAT_6_IN : in std_logic_vector(15 downto 0);\r
+ STAT_7_IN : in std_logic_vector(15 downto 0);\r
+ STAT_8_IN : in std_logic_vector(15 downto 0);\r
+ STAT_9_IN : in std_logic_vector(15 downto 0);\r
+ STAT_10_IN : in std_logic_vector(15 downto 0);\r
+ STAT_11_IN : in std_logic_vector(15 downto 0);\r
+ STAT_12_IN : in std_logic_vector(15 downto 0);\r
+ STAT_13_IN : in std_logic_vector(15 downto 0);\r
+ STAT_14_IN : in std_logic_vector(15 downto 0);\r
+ STAT_15_IN : in std_logic_vector(15 downto 0);\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+ );\r
+ end component;\r
+\r
+ component pulse_stretch is\r
+ port( CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ START_IN : in std_logic;\r
+ PULSE_OUT : out std_logic;\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
+ end component;\r
+\r
+ component apv_adc_map_mem is\r
+ port( ADDRESS : in std_logic_vector(6 downto 0); \r
+ Q : out std_logic_vector(3 downto 0)\r
+ );\r
+ end component;\r
+\r
+ component adc_apv_map_mem is\r
+ port( ADDRESS : in std_logic_vector(6 downto 0); \r
+ Q : out std_logic_vector(3 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+ component ped_thr_true is\r
+ port( DATAINA : in std_logic_vector(17 downto 0); \r
+ DATAINB : in std_logic_vector(17 downto 0); \r
+ ADDRESSA : in std_logic_vector(6 downto 0); \r
+ ADDRESSB : in std_logic_vector(6 downto 0); \r
+ CLOCKA : in std_logic; \r
+ CLOCKB : in std_logic; \r
+ CLOCKENA : in std_logic; \r
+ CLOCKENB : in std_logic; \r
+ WRA : in std_logic; \r
+ WRB : in std_logic; \r
+ RESETA : in std_logic; \r
+ RESETB : in std_logic; \r
+ QA : out std_logic_vector(17 downto 0); \r
+ QB : out std_logic_vector(17 downto 0)\r
+ );\r
+ end component;\r
+\r
+ component slv_ped_thr_mem is\r
+ port( CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_ADDR_IN : in std_logic_vector(10 downto 0);\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- backplane identifier\r
+ BACKPLANE_IN : in std_logic_vector(2 downto 0);\r
+ -- I/O to the backend\r
+ MEM_CLK_IN : in std_logic;\r
+ MEM_ADDR_IN : in std_logic_vector(6 downto 0);\r
+ MEM_0_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_1_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_2_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_3_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_4_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_5_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_6_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_7_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_8_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_9_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_10_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_11_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_12_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_13_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_14_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_15_D_OUT : out std_logic_vector(17 downto 0);\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+ );\r
+ end component;\r
+\r
+ component reset_handler is\r
+ port( CLEAR_IN : in std_logic; -- async reset from outside, if available (otherwise '0')\r
+ RESET_IN : in std_logic; -- for testing, if not needed, set to '0'\r
+ CLK_IN : in std_logic;\r
+ TRB_RESET_IN : in std_logic;\r
+ RESET_OUT : out std_logic;\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
+ end component;\r
+\r
+ component pll_40m is\r
+ port( CLK : in std_logic;\r
+ RESET : in std_logic; \r
+ DPAMODE : in std_logic;\r
+ DPHASE0 : in std_logic;\r
+ DPHASE1 : in std_logic;\r
+ DPHASE2 : in std_logic;\r
+ DPHASE3 : in std_logic;\r
+ CLKOP : out std_logic;\r
+ CLKOS : out std_logic;\r
+ LOCK : out std_logic\r
+ );\r
+ end component;\r
+\r
+ component dll_100m is\r
+ port( CLK : in std_logic; \r
+ RESETN : in std_logic; \r
+ ALUHOLD : in std_logic; \r
+ CLKOP : out std_logic; \r
+ CLKOS : out std_logic; \r
+ LOCK : out std_logic\r
+ );\r
+ end component;\r
+\r
+ component state_sync is\r
+ port( STATE_A_IN : in std_logic;\r
+ CLK_B_IN : in std_logic;\r
+ RESET_B_IN : in std_logic;\r
+ STATE_B_OUT : out std_logic\r
+ );\r
+ end component;\r
+\r
+ component pulse_sync is\r
+ port( CLK_A_IN : in std_logic;\r
+ RESET_A_IN : in std_logic;\r
+ PULSE_A_IN : in std_logic;\r
+ CLK_B_IN : in std_logic;\r
+ RESET_B_IN : in std_logic;\r
+ PULSE_B_OUT : out std_logic\r
+ );\r
+ end component; \r
+\r
+ component rich_trb is\r
+ port( CLK100M_IN : in std_logic;\r
+ SYSCLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ SD_RXD_P_IN : in std_logic;\r
+ SD_RXD_N_IN : in std_logic;\r
+ SD_TXD_P_OUT : out std_logic; \r
+ SD_TXD_N_OUT : out std_logic;\r
+ SD_PRESENT_IN : in std_logic;\r
+ SD_TXDIS_OUT : out std_logic;\r
+ SD_LOS_IN : in std_logic;\r
+ ONEWIRE_INOUT : inout std_logic;\r
+ -- common regIO status / control registers\r
+-- COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REGISTER_WIDTH-1 downto 0); -- common status register, bit definitions like in WIKI\r
+ COMMON_STAT_REG_IN : in std_logic_vector(2*32-1 downto 0); -- common status register, bit definitions like in WIKI\r
+-- COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*c_REGIO_REGISTER_WIDTH-1 downto 0); -- common control register, bit definitions like in WIKI\r
+ COMMON_CTRL_REG_OUT : out std_logic_vector(2*32-1 downto 0); -- common control register, bit definitions like in WIKI\r
+ -- status register input to regIO / control register output from regIO\r
+ CONTROL_OUT : out std_logic_vector(63 downto 0);\r
+ STATUS_IN : in std_logic_vector(127 downto 0); \r
+ -- LVL1 signals\r
+ LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0);\r
+ LVL1_TRG_RECEIVED_OUT : out std_logic;\r
+ LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0);\r
+ LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0);\r
+ LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0);\r
+ LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0);\r
+ LVL1_TRG_RELEASE_IN : in std_logic;\r
+ TIMING_TRG_FOUND_IN : in std_logic;\r
+ -- IPU data channel signals (yes, we will use ComputeNodes (tm) (R) (C) one day... :-)\r
+ IPU_NUMBER_OUT : out std_logic_vector(15 downto 0); -- trigger tag\r
+ IPU_INFORMATION_OUT : out std_logic_vector(7 downto 0); -- trigger information\r
+ IPU_START_READOUT_OUT : out std_logic; -- gimme data!\r
+ IPU_DATA_IN : in std_logic_vector(31 downto 0); -- detector data, equipped with DHDR\r
+ IPU_DATAREADY_IN : in std_logic; -- data is valid\r
+ IPU_READOUT_FINISHED_IN : in std_logic; -- no more data, end transfer, send TRM\r
+ IPU_READ_OUT : out std_logic; -- read strobe, low every second cycle \r
+ IPU_LENGTH_IN : in std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?)\r
+ IPU_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); -- error pattern\r
+ -- regIO bus\r
+-- REGIO_ADDR_OUT : out std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0);\r
+ REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0);\r
+ REGIO_READ_ENABLE_OUT : out std_logic;\r
+ REGIO_WRITE_ENABLE_OUT : out std_logic;\r
+-- REGIO_DATA_OUT : out std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0);\r
+ REGIO_DATA_OUT : out std_logic_vector(32-1 downto 0);\r
+-- REGIO_DATA_IN : in std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0);\r
+ REGIO_DATA_IN : in std_logic_vector(32-1 downto 0);\r
+ REGIO_DATAREADY_IN : in std_logic;\r
+ REGIO_NO_MORE_DATA_IN : in std_logic;\r
+ REGIO_WRITE_ACK_IN : in std_logic;\r
+ REGIO_UNKNOWN_ADDR_IN : in std_logic;\r
+ REGIO_TIMEOUT_OUT : out std_logic;\r
+ -- status LEDs\r
+ LED_LINK_STAT : out std_logic;\r
+ LED_LINK_TXD : out std_logic;\r
+ LED_LINK_RXD : out std_logic;\r
+ LINK_BSM_OUT : out std_logic_vector(3 downto 0);\r
+ RESET_OUT : out std_logic;\r
+ -- Debug\r
+ DEBUG : out std_logic_vector(63 downto 0)\r
+ );\r
+ end component;\r
+\r
+ component slave_bus is\r
+ port( CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- RegIO signals\r
+ REGIO_ADDR_IN : in std_logic_vector(15 downto 0); -- address bus \r
+ REGIO_DATA_IN : in std_logic_vector(31 downto 0); -- data from TRB endpoint\r
+ REGIO_DATA_OUT : out std_logic_vector(31 downto 0); -- data to TRB endpoint\r
+ REGIO_READ_ENABLE_IN : in std_logic; -- read pulse\r
+ REGIO_WRITE_ENABLE_IN : in std_logic; -- write pulse\r
+ REGIO_TIMEOUT_IN : in std_logic; -- access timed out\r
+ REGIO_DATAREADY_OUT : out std_logic; -- your data, master, as requested\r
+ REGIO_WRITE_ACK_OUT : out std_logic; -- data accepted\r
+ REGIO_NO_MORE_DATA_OUT : out std_logic; -- don't disturb me now\r
+ REGIO_UNKNOWN_ADDR_OUT : out std_logic; -- noone here to answer your request\r
+ -- I2C connections\r
+ SDA_IN : in std_logic;\r
+ SDA_OUT : out std_logic;\r
+ SCL_IN : in std_logic;\r
+ SCL_OUT : out std_logic;\r
+ -- 1Wire connections\r
+ ONEWIRE_START_IN : in std_logic; -- start 1Wire scan (pulse)\r
+ ONEWIRE_INOUT : inout std_logic_vector(15 downto 0); -- 1Wire ID on APV FEs\r
+ BP_ONEWIRE_INOUT : inout std_logic; -- 1Wire ID on backplane\r
+ -- SPI connections\r
+ SPI_CS_OUT : out std_logic;\r
+ SPI_SCK_OUT : out std_logic;\r
+ SPI_SDI_IN : in std_logic;\r
+ SPI_SDO_OUT : out std_logic;\r
+ -- ADC 0 SPI connections\r
+ SPI_ADC0_CS_OUT : out std_logic;\r
+ SPI_ADC0_SCK_OUT : out std_logic;\r
+ SPI_ADC0_SDO_OUT : out std_logic;\r
+ ADC0_PLL_LOCKED_IN : in std_logic;\r
+ ADC0_PD_OUT : out std_logic;\r
+ ADC0_RST_OUT : out std_logic;\r
+ ADC0_DEL_OUT : out std_logic_vector(3 downto 0);\r
+ ADC0_CLK_IN : in std_logic;\r
+ ADC0_DATA_IN : in std_logic_vector(11 downto 0);\r
+ ADC0_SEL_OUT : out std_logic_vector(2 downto 0);\r
+ APV0_RST_OUT : out std_logic;\r
+ -- ADC 0 SPI connections\r
+ SPI_ADC1_CS_OUT : out std_logic;\r
+ SPI_ADC1_SCK_OUT : out std_logic;\r
+ SPI_ADC1_SDO_OUT : out std_logic;\r
+ ADC1_PLL_LOCKED_IN : in std_logic;\r
+ ADC1_PD_OUT : out std_logic;\r
+ ADC1_RST_OUT : out std_logic;\r
+ ADC1_DEL_OUT : out std_logic_vector(3 downto 0);\r
+ ADC1_CLK_IN : in std_logic;\r
+ ADC1_DATA_IN : in std_logic_vector(11 downto 0);\r
+ ADC1_SEL_OUT : out std_logic_vector(2 downto 0);\r
+ APV1_RST_OUT : out std_logic;\r
+ -- User specific inputs / outputs\r
+ BACKPLANE_IN : in std_logic_vector(2 downto 0);\r
+ -- pedestal interface\r
+ PED_ADDR_IN : in std_logic_vector(6 downto 0); -- pedestal addressing from data handlers\r
+ PED_DATA_0_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_1_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_2_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_3_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_4_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_5_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_6_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_7_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_8_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_9_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_10_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_11_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_12_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_13_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_14_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_15_OUT : out std_logic_vector(17 downto 0);\r
+ -- threshold interface\r
+ THR_ADDR_IN : in std_logic_vector(6 downto 0); -- threshold addressing from data handlers\r
+ THR_DATA_0_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_1_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_2_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_3_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_4_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_5_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_6_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_7_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_8_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_9_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_10_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_11_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_12_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_13_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_14_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_15_OUT : out std_logic_vector(17 downto 0);\r
+ -- APV control / status\r
+ CTRL_0_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_1_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_2_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_3_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_4_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_5_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_6_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_7_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_8_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_9_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_10_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_11_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_12_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_13_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_14_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_15_OUT : out std_logic_vector(15 downto 0);\r
+ STAT_0_IN : in std_logic_vector(15 downto 0);\r
+ STAT_1_IN : in std_logic_vector(15 downto 0);\r
+ STAT_2_IN : in std_logic_vector(15 downto 0);\r
+ STAT_3_IN : in std_logic_vector(15 downto 0);\r
+ STAT_4_IN : in std_logic_vector(15 downto 0);\r
+ STAT_5_IN : in std_logic_vector(15 downto 0);\r
+ STAT_6_IN : in std_logic_vector(15 downto 0);\r
+ STAT_7_IN : in std_logic_vector(15 downto 0);\r
+ STAT_8_IN : in std_logic_vector(15 downto 0);\r
+ STAT_9_IN : in std_logic_vector(15 downto 0);\r
+ STAT_10_IN : in std_logic_vector(15 downto 0);\r
+ STAT_11_IN : in std_logic_vector(15 downto 0);\r
+ STAT_12_IN : in std_logic_vector(15 downto 0);\r
+ STAT_13_IN : in std_logic_vector(15 downto 0);\r
+ STAT_14_IN : in std_logic_vector(15 downto 0);\r
+ STAT_15_IN : in std_logic_vector(15 downto 0);\r
+ -- some control signals\r
+ CTRL_LVL_OUT : out std_logic_vector(31 downto 0);\r
+ CTRL_TRG_OUT : out std_logic_vector(31 downto 0);\r
+ CTRL_PLL_OUT : out std_logic_vector(15 downto 0);\r
+ STATUS_PLL_IN : in std_logic_vector(15 downto 0);\r
+ -- temporary stuff\r
+ TEST_REG_IN : in std_logic_vector(31 downto 0); -- just for testing!\r
+ TEST_REG_OUT : out std_logic_vector(31 downto 0); -- just for testing!\r
+ -- Debug\r
+ DEBUG_OUT : out std_logic_vector(63 downto 0);\r
+ STAT : out std_logic_vector(31 downto 0)\r
+ );\r
+ end component;\r
+\r
+ component oddrxc is\r
+ port( DA : in std_logic;\r
+ DB : in std_logic;\r
+ CLK : in std_logic;\r
+ RST : in std_logic;\r
+ Q : out std_logic\r
+ );\r
+ end component;\r
+\r
+ component apv_trgctrl is\r
+ port( CLK_IN : in std_logic; -- 100MHz master clock\r
+ RESET_IN : in std_logic; \r
+ CLK_APV_IN : in std_logic; -- 40MHz phase shifted clock\r
+ -- Triggers\r
+ SYNC_TRG_IN : in std_logic; -- 100MHz signal to SYNC APVs\r
+ TIME_TRG_IN : in std_logic_vector(3 downto 0); -- timing trigger inputs\r
+ TRB_TRG_IN : in std_logic_vector(3 downto 0); -- TRB trigger inputs\r
+ STILL_BUSY_IN : in std_logic; -- set to '1' if any buffer is in danger of overflow\r
+ TRG_FOUND_OUT : out std_logic; -- trigger found\r
+ -- slow control settings\r
+ TRG_MAX_OUT : out std_logic_vector(3 downto 0); -- maximum number of triggers/event\r
+ TRG_3_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 3\r
+ TRG_3_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers\r
+ TRG_2_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 2\r
+ TRG_2_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers\r
+ TRG_1_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 1\r
+ TRG_1_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers\r
+ TRG_0_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 0\r
+ TRG_0_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers\r
+ TRG_SETUP_IN : in std_logic_vector(7 downto 0); -- setup of external triggers\r
+ -- TRB LVL1 signals\r
+ TRB_TTAG_IN : in std_logic_vector(15 downto 0); -- TRB LVL1 trigger tag\r
+ TRB_TRND_IN : in std_logic_vector(7 downto 0); -- TRB LVL1 random tag\r
+ TRB_TTYPE_IN : in std_logic_vector(3 downto 0); -- TRB LVL1 trigger type\r
+ TRB_TRGRCVD_IN : in std_logic; -- TRB LVL1 trigger received\r
+ TRB_MISSING_OUT : out std_logic; -- TRB LVL1 trigger arrived, but has no corresponding timing trigger\r
+ TRB_RELEASE_OUT : out std_logic; -- release TRB LVL1 channel\r
+ TRB_RST_COUNTER_IN : in std_logic; -- reset timing trigger counter\r
+ TRB_COUNTER_OUT : out std_logic_vector(15 downto 0);\r
+ -- EDS signals\r
+ EDS_DATA_OUT : out std_logic_vector(39 downto 0); -- EventDataSheet (tm) data word\r
+ EDS_AVAIL_OUT : out std_logic; -- EDS valid, APV trigger done\r
+ EDS_DONE_IN : in std_logic; -- release current EDS buffer\r
+ EDS_FULL_OUT : out std_logic; -- EDS buffer is full\r
+ EDS_LEVEL_OUT : out std_logic_vector(4 downto 0);\r
+ FRM_REQD_OUT : out std_logic; -- frame requested, (level counter decrement)\r
+ -- APV signals \r
+ APV_TRG_OUT : out std_logic;\r
+ APV_SYNC_OUT : out std_logic;\r
+ DEBUG_OUT : out std_logic_vector(63 downto 0)\r
+ );\r
+ end component;\r
+\r
+ component ped_corr_ctrl is\r
+ port( CLK_IN : in std_logic; -- 100MHz local clock\r
+ RESET_IN : in std_logic; -- synchronous reset\r
+ -- Slow control registers\r
+ -- EDS buffer -- back to previous source stage\r
+ EDS_DATA_IN : in std_logic_vector(39 downto 0);\r
+ EDS_AVAIL_IN : in std_logic;\r
+ EDS_DONE_OUT : out std_logic;\r
+ EVT_TYPE_IN : in std_logic_vector(2 downto 0);\r
+ -- DHDR information -- to next stage\r
+ DHDR_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ DHDR_LENGTH_OUT : out std_logic_vector(15 downto 0);\r
+ DHDR_STORE_OUT : out std_logic;\r
+ DHDR_BUF_FULL_IN : in std_logic;\r
+ -- data buffers -- from raw_buf_stage\r
+ BUF_ADDR_OUT : out std_logic_vector(6 downto 0);\r
+ BUF_DONE_OUT : out std_logic;\r
+ BUF_TICK_IN : in std_logic_vector(15 downto 0);\r
+ BUF_START_IN : in std_logic_vector(15 downto 0);\r
+ -- raw data\r
+ BUF_0_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_1_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_2_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_3_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_4_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_5_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_6_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_7_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_8_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_9_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_10_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_11_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_12_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_13_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_14_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_15_DATA_IN : in std_logic_vector(37 downto 0);\r
+ -- Pedestal data \r
+ PED_ADDR_OUT : out std_logic_vector(6 downto 0);\r
+ PED_0_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_1_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_2_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_3_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_4_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_5_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_6_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_7_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_8_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_9_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_10_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_11_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_12_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_13_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_14_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_15_DATA_IN : in std_logic_vector(17 downto 0);\r
+ -- Threshold data\r
+ THR_ADDR_OUT : out std_logic_vector(6 downto 0);\r
+ THR_0_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_1_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_2_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_3_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_4_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_5_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_6_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_7_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_8_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_9_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_10_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_11_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_12_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_13_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_14_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_15_DATA_IN : in std_logic_vector(17 downto 0);\r
+ -- processed data\r
+ FIFO_START_OUT : out std_logic;\r
+ FIFO_0_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_1_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_2_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_3_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_4_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_5_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_6_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_7_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_8_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_9_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_10_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_11_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_12_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_13_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_14_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_15_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_WE_OUT : out std_logic_vector(15 downto 0);\r
+ FIFO_DONE_OUT : out std_logic; -- write level information into small FIFOs\r
+ -- Debug signals\r
+ DBG_BSM_OUT : out std_logic_vector(7 downto 0);\r
+ DBG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
+ end component;\r
+\r
+ component ipu_fifo_stage is\r
+ port( CLK_IN : in std_logic; -- 100MHz local clock\r
+ RESET_IN : in std_logic; -- synchronous reset\r
+ -- Slow control signals \r
+ SECTOR_IN : in std_logic_vector(2 downto 0);\r
+ MODULE_IN : in std_logic_vector(2 downto 0);\r
+ -- IPU channel connections\r
+ IPU_NUMBER_IN : in std_logic_vector(15 downto 0); -- trigger tag\r
+ IPU_INFORMATION_IN : in std_logic_vector(7 downto 0); -- trigger information\r
+ IPU_START_READOUT_IN : in std_logic; -- gimme data!\r
+ IPU_DATA_OUT : out std_logic_vector(31 downto 0); -- detector data, equipped with DHDR\r
+ IPU_DATAREADY_OUT : out std_logic; -- data is valid\r
+ IPU_READOUT_FINISHED_OUT : out std_logic; -- no more data, end transfer, send TRM\r
+ IPU_READ_IN : in std_logic; -- read strobe, low every second cycle \r
+ IPU_LENGTH_OUT : out std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?)\r
+ IPU_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); -- error pattern\r
+ LVL2_COUNTER_OUT : out std_logic_vector(15 downto 0); -- local IPU cycle counter\r
+ -- DHDR buffer input\r
+ DHDR_DATA_IN : in std_logic_vector(31 downto 0);\r
+ DHDR_LENGTH_IN : in std_logic_vector(15 downto 0);\r
+ DHDR_STORE_IN : in std_logic;\r
+ DHDR_BUF_FULL_OUT : out std_logic;\r
+ -- processed data input\r
+ FIFO_START_IN : in std_logic;\r
+ FIFO_0_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_1_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_2_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_3_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_4_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_5_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_6_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_7_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_8_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_9_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_10_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_11_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_12_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_13_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_14_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_15_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_WE_IN : in std_logic_vector(15 downto 0);\r
+ FIFO_DONE_IN : in std_logic; -- write level information into small FIFOs\r
+ -- Debug signals\r
+ DBG_BSM_OUT : out std_logic_vector(7 downto 0);\r
+ DBG_OUT : out std_logic_vector(63 downto 0)\r
+ );\r
+ end component;\r
+\r
+ component ipu_dummy is\r
+ port( CLK_IN : in std_logic; -- 100MHz local clock\r
+ RESET_IN : in std_logic; -- synchronous reset\r
+ -- Slow control signals \r
+ MIN_COUNT_IN : in std_logic_vector(15 downto 0); -- minimum counter value\r
+ MAX_COUNT_IN : in std_logic_vector(15 downto 0); -- maximum counter value\r
+ CTRL_IN : in std_logic_vector(7 downto 0); -- control bits from slow control\r
+ -- IPU channel connections\r
+ IPU_NUMBER_IN : in std_logic_vector(15 downto 0); -- trigger tag\r
+ IPU_INFORMATION_IN : in std_logic_vector(7 downto 0); -- trigger information\r
+ IPU_START_READOUT_IN : in std_logic; -- gimme data!\r
+ IPU_DATA_OUT : out std_logic_vector(31 downto 0); -- detector data, equipped with DHDR\r
+ IPU_DATAREADY_OUT : out std_logic; -- data is valid\r
+ IPU_READOUT_FINISHED_OUT : out std_logic; -- no more data, end transfer, send TRM\r
+ IPU_READ_IN : in std_logic; -- read strobe, low every second cycle \r
+ IPU_LENGTH_OUT : out std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?)\r
+ IPU_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); -- error pattern\r
+ -- DHDR buffer\r
+ LVL1_FIFO_RD_OUT : out std_logic;\r
+ LVL1_FIFO_EMPTY_IN : in std_logic;\r
+ LVL1_FIFO_NUMBER_IN : in std_logic_vector(15 downto 0);\r
+ LVL1_FIFO_CODE_IN : in std_logic_vector(7 downto 0);\r
+ LVL1_FIFO_INFORMATION_IN : in std_logic_vector(7 downto 0);\r
+ LVL1_FIFO_TYPE_IN : in std_logic_vector(3 downto 0);\r
+ -- Debug signals\r
+ DBG_BSM_OUT : out std_logic_vector(7 downto 0);\r
+ DBG_OUT : out std_logic_vector(63 downto 0)\r
+ );\r
+ end component;\r
+\r
+ component reboot_handler is\r
+ port( RESET_IN : in std_logic;\r
+ CLK_IN : in std_logic;\r
+ START_IN : in std_logic;\r
+ REBOOT_OUT : out std_logic;\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
+ end component;\r
+\r
+ component real_trg_handler is\r
+ port( CLK_IN : in std_logic; -- 100MHz master clock\r
+ RESET_IN : in std_logic; \r
+ TIME_TRG_IN : in std_logic_vector(3 downto 0); -- timing trigger inputs\r
+ TRB_TRG_IN : in std_logic_vector(3 downto 0); -- TRB trigger inputs\r
+ APV_TRGDONE_IN : in std_logic; -- APV trigger statemachine finished (one pulse)\r
+ TRG_3_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 3\r
+ TRG_2_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 2\r
+ TRG_1_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 1\r
+ TRG_0_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 0\r
+ TRG_SETUP_IN : in std_logic_vector(7 downto 0); -- setup of external triggers\r
+ TRG_FOUND_OUT : out std_logic; -- single pulse for endpoint\r
+ TRB_TTAG_IN : in std_logic_vector(15 downto 0); -- LVL1 16bit trigger tag \r
+ TRB_TRND_IN : in std_logic_vector(7 downto 0); -- LVL1 8bit random number \r
+ TRB_TTYPE_IN : in std_logic_vector(3 downto 0); -- LVL1 trigger type\r
+ TRB_TRGRCVD_IN : in std_logic; -- LVL1 trigger has been received on TRB\r
+ TRB_MISSING_OUT : out std_logic; -- LVL1 trigger without timing trigger\r
+ RST_LVL1_COUNTER_IN : in std_logic; -- reset LVL1 counter\r
+ LVL1_COUNTER_OUT : out std_logic_vector(15 downto 0); -- LVL1 counter\r
+ BUSY_RELEASE_IN : in std_logic; -- common signal from busy calculator\r
+ APV_TRGSEL_OUT : out std_logic_vector(3 downto 0); -- select one APV trigger state machine\r
+ APV_TRGSTART_OUT : out std_logic; -- start one APV trigger state machine\r
+ EDS_DATA_OUT : out std_logic_vector(39 downto 0); -- EDS data\r
+ EDS_WE_OUT : out std_logic; -- EDS write enable (general interface)\r
+ EDS_START_OUT : out std_logic; -- separate increment signal for EDS buffer level\r
+ EDS_READY_OUT : out std_logic; -- APV trigger sequence done, TERMinate the TRB LVL1 trigger\r
+ DBG_FRMCTR_OUT : out std_logic_vector(3 downto 0); -- framecounter itself\r
+ BSM_OUT : out std_logic_vector(7 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(63 downto 0)\r
+ );\r
+ end component;\r
+\r
+ component apv_trg_handler is\r
+ port( CLK_APV_IN : in std_logic; -- 40MHz phase shifted clock\r
+ RESET_APV_IN : in std_logic; -- synced reset signal (40MHz APV)\r
+ CLK_IN : in std_logic; -- 100MHz master clock\r
+ RESET_IN : in std_logic; -- synced reset signal (100MHz)\r
+ APV_TRGSTART_IN : in std_logic; -- start signal for one sequence\r
+ APV_TRGSEL_IN : in std_logic; -- select signal for one sequence\r
+ APV_TRG_TODO_IN : in std_logic_vector(3 downto 0); -- number of APV triggers\r
+ APV_TRG_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between APV triggers\r
+ APV_TRGDONE_OUT : out std_logic; -- APV trigger statemachine finished\r
+ APV_TRG_OUT : out std_logic;\r
+ APV_TRGSENT_OUT : out std_logic;\r
+ BSM_OUT : out std_logic_vector(3 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
+ end component;\r
+\r
+ component apv_sync_handler is\r
+ port( CLK_APV_IN : in std_logic; -- 40MHz phase shifted clock\r
+ RESET_APV_IN : in std_logic; -- synced reset signal (40MHz APV)\r
+ CLK_IN : in std_logic; -- 100MHz master clock\r
+ RESET_IN : in std_logic; -- synced reset signal (100MHz)\r
+ APV_TRGSTART_IN : in std_logic; -- start signal for one sequence\r
+ APV_TRGSEL_IN : in std_logic; -- select signal for one sequence\r
+ APV_TRGDONE_OUT : out std_logic; -- APV trigger statemachine finished\r
+ APV_TRG_OUT : out std_logic;\r
+ APV_SYNC_OUT : out std_logic; -- signal for statemachines\r
+ BSM_OUT : out std_logic_vector(3 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
+ end component;\r
+\r
+ component eds_buf is\r
+ port( CLK_IN : in std_logic; -- 100MHz master clock\r
+ RESET_IN : in std_logic; \r
+ -- EDS input, all synced to CLK_IN\r
+ EDS_DATA_IN : in std_logic_vector(39 downto 0); -- EDS data input\r
+ EDS_WE_IN : in std_logic; -- EDS write enable\r
+ EDS_DONE_IN : in std_logic; -- release EDS \r
+ EDS_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ EDS_AVAILABLE_OUT : out std_logic;\r
+ -- trigger busy information\r
+ BUF_FULL_OUT : out std_logic;\r
+ BUF_LEVEL_OUT : out std_logic_vector(4 downto 0);\r
+ -- Debug signals\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
+ end component;\r
+\r
+ component adc_pll is\r
+ port( CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLKOP : out std_logic; \r
+ LOCK : out std_logic\r
+ );\r
+ end component;\r
+ \r
+ component adc_ch_in is \r
+ port( DEL : in std_logic_vector(3 downto 0);\r
+ ECLK : in std_logic; \r
+ SCLK : in std_logic; \r
+ RST : in std_logic; \r
+ DATA : in std_logic_vector(0 downto 0); \r
+ Q : out std_logic_vector(1 downto 0)\r
+ ); \r
+ end component; \r
+\r
+ component adc_twochannels is\r
+ port( CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ CLOCK_IN : in std_logic_vector(1 downto 0); -- DDR bit clock\r
+ DATA_0_IN : in std_logic_vector(1 downto 0); -- ADC channel one\r
+ DATA_1_IN : in std_logic_vector(1 downto 0); -- ADC channel two\r
+ DATA_0_OUT : out std_logic_vector(11 downto 0); -- demultiplexed ADC channel one\r
+ DATA_1_OUT : out std_logic_vector(11 downto 0); -- demultiplexed ADC channel two\r
+ STORE_OUT : out std_logic;\r
+ SWAP_OUT : out std_logic;\r
+ CLOCK_OUT : out std_logic;\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
+ end component;\r
+\r
+ component apv_locker is\r
+ port( CLK_APV_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ ADC_RAW_IN : in std_logic_vector(11 downto 0); -- ADC: raw data, synchronous to ADC_CLK_IN\r
+ ADC_VALID_IN : in std_logic; -- ADC: ser2par data is valid\r
+ SYNC_IN : in std_logic; -- sync trigger input \r
+ APV_ON_IN : in std_logic; -- this APV channel is switched on\r
+ BIT_LOW_IN : in std_logic_vector(11 downto 0); -- slow control: threshold for digital '0'\r
+ BIT_HIGH_IN : in std_logic_vector(11 downto 0); -- slow control: threshold for digital '1'\r
+ FL_LOW_IN : in std_logic_vector(11 downto 0); -- lower threshold for ADC flatline\r
+ FL_HIGH_IN : in std_logic_vector(11 downto 0); -- upper threshold for ADC flatline\r
+ STATUS_IGNORE_OUT : out std_logic; -- APV is to be ignored (effectively => switched off)\r
+ STATUS_UNKNOWN_OUT : out std_logic; -- APV is not initialized yet\r
+ STATUS_BADADC_OUT : out std_logic; -- ADC ser2par data is invalid\r
+ STATUS_LOCKED_OUT : out std_logic; -- APV locked successfully\r
+ STATUS_LOST_OUT : out std_logic; -- APV tickmark missing or wrong\r
+ STATUS_NOSYNC_OUT : out std_logic; -- APV did not lock successfully\r
+ STATUS_MISSING_OUT : out std_logic; -- APV is missing, ADC flatline detected\r
+ STATUS_TICKMARK_OUT : out std_logic;\r
+ FRAME_ROW_OUT : out std_logic_vector(7 downto 0); -- decoded row from APV header\r
+ FRAME_ERROR_OUT : out std_logic; -- decoded error bit from APV header\r
+ FRAME_FLAT_OUT : out std_logic; -- APV sends a flat line (analog dead?)\r
+ FRAME_OVF_OUT : out std_logic; -- at least one channel in frame was overflow\r
+ FRAME_UDF_OUT : out std_logic; -- at least one channel in frame was underflow\r
+ FRAME_CTR_OUT : out std_logic_vector(3 downto 0); -- frame counter for incoming data frames\r
+ APV_CHANNEL_OUT : out std_logic_vector(6 downto 0); -- physical channel ID\r
+ APV_OVERFLOW_OUT : out std_logic; -- channel is truncated high\r
+ APV_UNDERFLOW_OUT : out std_logic; -- channel is truncated low\r
+ APV_RAW_OUT : out std_logic_vector(11 downto 0); -- APV raw data\r
+ APV_ANALOG_OUT : out std_logic; -- APV analog data is valid\r
+ APV_START_OUT : out std_logic; -- valid data frame found, reserve one buffer \r
+ APV_LAST_OUT : out std_logic; -- last APV channel of dataframe\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
+ end component;\r
+\r
+ component apv_raw_buffer is\r
+ port( CLK_APV_IN : in std_logic; -- write clock from APV handling stage\r
+ RESET_IN : in std_logic;\r
+ FRM_REQD_IN : in std_logic; -- one data frame has been requested from APV\r
+ MAX_TRG_NUM_IN : in std_logic_vector(3 downto 0); -- maximum number of triggers per event\r
+ ADC_ANALOG_IN : in std_logic; -- write enable for ADC data\r
+ ADC_START_IN : in std_logic; -- data frame detected, block the buffer page\r
+ ADC_LAST_IN : in std_logic; -- last channel signal\r
+ ADC_CHANNEL_IN : in std_logic_vector(6 downto 0); -- physical channel ID\r
+ ADC_RAW_IN : in std_logic_vector(17 downto 0); -- raw ADC data, UDF, OVF, ERROR\r
+ ADC_STATUS_IN : in std_logic_vector(7 downto 0); -- status information for APV\r
+ ADC_FRAME_IN : in std_logic_vector(11 downto 0); -- status information for frame\r
+ BUF_CLK_IN : in std_logic; -- read clock\r
+ BUF_RESET_IN : in std_logic; -- 100MHz reset\r
+ BUF_START_OUT : out std_logic; -- one block starts writing\r
+ BUF_READY_OUT : out std_logic; -- one block has been written\r
+ BUF_ADDR_IN : in std_logic_vector(6 downto 0); -- address inside current buffer\r
+ BUF_DONE_IN : in std_logic; -- buffer has been read (discard buffer)\r
+ BUF_DATA_OUT : out std_logic_vector(17 downto 0); -- data from buffer\r
+ BUF_STATUS_OUT : out std_logic_vector(7 downto 0); -- generic APV status output\r
+ BUF_FRAME_OUT : out std_logic_vector(11 downto 0); -- current frame status output\r
+ BUF_GOOD_OUT : out std_logic; -- APV is active and synced -> GOOD situation\r
+ BUF_BROKEN_OUT : out std_logic; -- APV is active, but not synced -> BAD situation\r
+ BUF_IGNORE_OUT : out std_logic; -- APV is switched off -> switched off\r
+ BUF_LEVEL_OUT : out std_logic_vector(4 downto 0); -- number of stored frames inside buffer\r
+ BUF_TICKMARK_OUT : out std_logic; -- tickmark signal for timeouts in the EDS handler\r
+ BUF_FULL_OUT : out std_logic; -- inhibit any next trigger if set!\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
+ end component;\r
+\r
+ component slv_register is\r
+ generic( RESET_VALUE : std_logic_vector(31 downto 0) := x"0000_0000" );\r
+ port( CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ BUSY_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_BUSY_OUT : out std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- I/O to the backend\r
+ REG_DATA_IN : in std_logic_vector(31 downto 0);\r
+ REG_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+ );\r
+ end component;\r
+\r
+ component slv_half_register is\r
+ generic( RESET_VALUE : std_logic_vector(15 downto 0) := x"0000" );\r
+ port( CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- I/O to the backend\r
+ STATUS_REG_IN : in std_logic_vector(15 downto 0);\r
+ CTRL_REG_OUT : out std_logic_vector(15 downto 0);\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+ );\r
+ end component;\r
+\r
+ component i2c_master is\r
+ port( CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_BUSY_OUT : out std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- I2C connections\r
+ SDA_IN : in std_logic;\r
+ SDA_OUT : out std_logic;\r
+ SCL_IN : in std_logic;\r
+ SCL_OUT : out std_logic;\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+ );\r
+ end component;\r
+\r
+ component slv_onewire_memory is\r
+ port( CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_ADDR_IN : in std_logic_vector(5 downto 0);\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_BUSY_OUT : out std_logic;\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- backplane identifier\r
+ BACKPLANE_IN : in std_logic_vector(2 downto 0);\r
+ -- 1Wire lines\r
+ ONEWIRE_START_IN : in std_logic;\r
+ ONEWIRE_INOUT : inout std_logic_vector(15 downto 0);\r
+ BP_ONEWIRE_INOUT : inout std_logic;\r
+ -- Status lines\r
+ STAT : out std_logic_vector(63 downto 0) -- DEBUG\r
+ );\r
+ end component;\r
+\r
+ component spi_real_slim is\r
+ port( SYSCLK : in std_logic; -- 100MHz sysclock\r
+ RESET : in std_logic; -- synchronous reset\r
+ -- Command interface\r
+ START_IN : in std_logic; -- one start pulse\r
+ BUSY_OUT : out std_logic; -- SPI transactions are ongoing\r
+ CMD_IN : in std_logic_vector(7 downto 0); -- SPI command byte\r
+ -- SPI interface\r
+ SPI_SCK_OUT : out std_logic;\r
+ SPI_CS_OUT : out std_logic;\r
+ SPI_SDO_OUT : out std_logic;\r
+ -- DEBUG\r
+ CLK_EN_OUT : out std_logic;\r
+ BSM_OUT : out std_logic_vector(7 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(31 downto 0)\r
+ );\r
+ end component;\r
+\r
+ component spi_adc_master is\r
+ generic( RESET_VALUE_CTRL : std_logic_vector(7 downto 0) := x"60" );\r
+ port( CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_BUSY_OUT : out std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- SPI connections\r
+ SPI_CS_OUT : out std_logic;\r
+ SPI_SDO_OUT : out std_logic;\r
+ SPI_SCK_OUT : out std_logic;\r
+ -- ADC connections\r
+ ADC_LOCKED_IN : in std_logic;\r
+ ADC_PD_OUT : out std_logic;\r
+ ADC_RST_OUT : out std_logic;\r
+ ADC_DEL_OUT : out std_logic_vector(3 downto 0);\r
+ -- APV connections\r
+ APV_RST_OUT : out std_logic;\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+ );\r
+ end component;\r
+\r
+ component i2c_slim is\r
+ port( CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic; \r
+ -- I2C command / setup\r
+ I2C_GO_IN : in std_logic; -- startbit to trigger I2C actions\r
+ ACTION_IN : in std_logic; -- '0' -> write, '1' -> read\r
+ I2C_SPEED_IN : in std_logic_vector( 5 downto 0 ); -- speed adjustment (to be defined)\r
+ I2C_ADR_IN : in std_logic_vector( 7 downto 0 ); -- I2C address byte (R/W bit is ignored)\r
+ I2C_CMD_IN : in std_logic_vector( 7 downto 0 ); -- I2C command byte (sent after address byte)\r
+ I2C_DW_IN : in std_logic_vector( 7 downto 0 ); -- data word for write command\r
+ I2C_DR_OUT : out std_logic_vector( 7 downto 0 ); -- data word from read command\r
+ STATUS_OUT : out std_logic_vector( 7 downto 0 ); -- status and error bits\r
+ I2C_BUSY_OUT : out std_logic;\r
+ -- I2C connections\r
+ SDA_IN : in std_logic;\r
+ SDA_OUT : out std_logic;\r
+ SCL_IN : in std_logic;\r
+ SCL_OUT : out std_logic;\r
+ -- Debug\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+ );\r
+ end component;\r
+ \r
+ component i2c_gstart is\r
+ port( CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ START_IN : in std_logic; \r
+ DOSTART_IN : in std_logic; \r
+ I2C_SPEED_IN : in std_logic_vector(7 downto 0);\r
+ SDONE_OUT : out std_logic;\r
+ SOK_OUT : out std_logic;\r
+ SDA_IN : in std_logic;\r
+ SCL_IN : in std_logic;\r
+ R_SCL_OUT : out std_logic;\r
+ S_SCL_OUT : out std_logic;\r
+ R_SDA_OUT : out std_logic;\r
+ S_SDA_OUT : out std_logic;\r
+ BSM_OUT : out std_logic_vector(3 downto 0)\r
+ );\r
+ end component;\r
+\r
+ component i2c_sendb is\r
+ port( CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ DOBYTE_IN : in std_logic; \r
+ I2C_SPEED_IN : in std_logic_vector(7 downto 0);\r
+ I2C_BYTE_IN : in std_logic_vector(8 downto 0); \r
+ I2C_BACK_OUT : out std_logic_vector(8 downto 0);\r
+ SDA_IN : in std_logic;\r
+ R_SDA_OUT : out std_logic;\r
+ S_SDA_OUT : out std_logic;\r
+-- SCL_IN : in std_logic;\r
+ R_SCL_OUT : out std_logic;\r
+ S_SCL_OUT : out std_logic;\r
+ BDONE_OUT : out std_logic;\r
+ BOK_OUT : out std_logic;\r
+ BSM_OUT : out std_logic_vector(3 downto 0)\r
+ );\r
+ end component;\r
+\r
+ component onewire_master is\r
+ generic( CLK_PERIOD : integer := 10 ); -- clock perion in nanoseconds\r
+ port( CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ READOUT_ENABLE_IN : in std_logic;\r
+ -- connection to 1-wire interface (16 APV FEs)\r
+ ONEWIRE : inout std_logic_vector(15 downto 0);\r
+ BP_ONEWIRE : inout std_logic;\r
+ -- connection to external DPRAM for slow control readout\r
+ BP_DATA_OUT : out std_logic_vector(15 downto 0);\r
+ DATA_OUT : out std_logic_vector(15 downto 0);\r
+ ADDR_OUT : out std_logic_vector(6 downto 0);\r
+ WRITE_OUT : out std_logic;\r
+ BUSY_OUT : out std_logic;\r
+ -- debug\r
+ BSM_OUT : out std_logic_vector(7 downto 0);\r
+ STAT : out std_logic_vector(15 downto 0)\r
+ );\r
+ end component;\r
+\r
+ component slv_onewire_dpram\r
+ port( WRADDRESS : in std_logic_vector(6 downto 0); \r
+ RDADDRESS : in std_logic_vector(5 downto 0); \r
+ DATA : in std_logic_vector(15 downto 0);\r
+ WE : in std_logic; \r
+ RDCLOCK : in std_logic;\r
+ RDCLOCKEN : in std_logic; \r
+ RESET : in std_logic;\r
+ WRCLOCK : in std_logic; \r
+ WRCLOCKEN : in std_logic;\r
+ Q : out std_logic_vector(31 downto 0)\r
+ );\r
+ end component;\r
+\r
+ component dhdr_buf is\r
+ port( CLK_IN : in std_logic; -- 100MHz master clock\r
+ RESET_IN : in std_logic; \r
+ -- DHDR information block\r
+ DHDR_DATA_IN : in std_logic_vector(47 downto 0); -- EDS data input\r
+ DHDR_WE_IN : in std_logic; -- EDS write enable\r
+ DHDR_DONE_IN : in std_logic; -- release EDS \r
+ DHDR_DATA_OUT : out std_logic_vector(47 downto 0);\r
+ DHDR_AVAILABLE_OUT : out std_logic;\r
+ -- trigger busy information\r
+ BUF_FULL_OUT : out std_logic;\r
+ BUF_LEVEL_OUT : out std_logic_vector(4 downto 0);\r
+ -- Debug signals\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
+ end component;\r
+\r
+ component fifo_2kx27 is\r
+ port( DATA : in std_logic_vector(26 downto 0); \r
+ CLOCK : in std_logic; \r
+ WREN : in std_logic; \r
+ RDEN : in std_logic; \r
+ RESET : in std_logic; \r
+ Q : out std_logic_vector(26 downto 0); \r
+ WCNT : out std_logic_vector(11 downto 0); \r
+ EMPTY : out std_logic; \r
+ FULL : out std_logic\r
+ );\r
+ end component fifo_2kx27;\r
+\r
+ component fifo_16x11 is\r
+ port( DATA : in std_logic_vector(10 downto 0); \r
+ CLOCK : in std_logic; \r
+ WREN : in std_logic; \r
+ RDEN : in std_logic; \r
+ RESET : in std_logic; \r
+ Q : out std_logic_vector(10 downto 0); \r
+ WCNT : out std_logic_vector(4 downto 0); \r
+ EMPTY : out std_logic; \r
+ FULL : out std_logic\r
+ );\r
+ end component fifo_16x11;\r
+\r
+ component dhdr_buffer_dpram is\r
+ port( WRADDRESS : in std_logic_vector(3 downto 0); \r
+ DATA : in std_logic_vector(47 downto 0); \r
+ WRCLOCK : in std_logic; \r
+ WE : in std_logic; \r
+ WRCLOCKEN : in std_logic; \r
+ RDADDRESS : in std_logic_vector(3 downto 0); \r
+ RDCLOCK : in std_logic; \r
+ RDCLOCKEN : in std_logic; \r
+ RESET : in std_logic; \r
+ Q : out std_logic_vector(47 downto 0)\r
+ );\r
+ end component;\r
+\r
+ component decoder_8bit is\r
+ port( ADDRESS : in std_logic_vector(7 downto 0); \r
+ Q : out std_logic_vector(3 downto 0)\r
+ );\r
+ end component decoder_8bit;\r
+\r
+ component adder_5bit is\r
+ port( DATAA : in std_logic_vector(4 downto 0); \r
+ DATAB : in std_logic_vector(4 downto 0); \r
+ CLOCK : in std_logic; \r
+ RESET : in std_logic; \r
+ CLOCKEN : in std_logic; \r
+ RESULT : out std_logic_vector(4 downto 0)\r
+ );\r
+ end component adder_5bit;\r
+\r
+ component adder_16bit is\r
+ port( DATAA : in std_logic_vector(15 downto 0); \r
+ DATAB : in std_logic_vector(15 downto 0); \r
+ CLOCK : in std_logic; \r
+ RESET : in std_logic; \r
+ CLOCKEN : in std_logic; \r
+ RESULT : out std_logic_vector(15 downto 0)\r
+ );\r
+ end component adder_16bit;\r
+\r
+ component suber_12bit is\r
+ port( DATAA : in std_logic_vector(11 downto 0); \r
+ DATAB : in std_logic_vector(11 downto 0); \r
+ CLOCK : in std_logic; \r
+ RESET : in std_logic; \r
+ CLOCKEN : in std_logic; \r
+ RESULT : out std_logic_vector(11 downto 0)\r
+ );\r
+ end component suber_12bit;\r
+\r
+\r
+ component buf_toc is\r
+ port( CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ BUF_TICK_IN : in std_logic; -- tickmark from raw buffer\r
+ BUF_START_IN : in std_logic; -- start of frame from raw buffer\r
+ WAITFRAME_IN : in std_logic; -- statemachine is in "wait for frame" mode\r
+ FRAMES_REQD_IN : in std_logic_vector(3 downto 0); -- number of frames requested from EDS\r
+ BUF_LVL_IN : in std_logic_vector(7 downto 0);\r
+ GOODDATA_OUT : out std_logic;\r
+ BADDATA_OUT : out std_logic;\r
+ NODATA_OUT : out std_logic;\r
+ READY_OUT : out std_logic;\r
+ BSM_OUT : out std_logic_vector(7 downto 0);\r
+ DBG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
+ end component buf_toc;\r
+\r
+ component ref_row_sel is\r
+ port( CLK_IN : in std_logic;\r
+ READY_IN : in std_logic_vector(15 downto 0);\r
+ GOODDATA_IN : in std_logic_vector(15 downto 0);\r
+ FRAME_0_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_1_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_2_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_3_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_4_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_5_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_6_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_7_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_8_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_9_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_10_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_11_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_12_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_13_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_14_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_15_IN : in std_logic_vector(11 downto 0);\r
+ VALID_BUFS_OUT : out std_logic;\r
+ READY_OUT : out std_logic;\r
+ ROW_ERROR_OUT : out std_logic; -- at least one row number is wrong\r
+ APV_ERROR_OUT : out std_logic; -- at least one APV sent ERROR bit\r
+ APV_ERROR_BITS_OUT : out std_logic_vector(15 downto 0);\r
+ REF_ROW_OUT : out std_logic_vector(7 downto 0); -- selected reference row\r
+ DBG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
+ end component ref_row_sel;\r
+\r
+ component frmctr_check is\r
+ port( CLK_IN : in std_logic;\r
+ GOODDATA_IN : in std_logic_vector(15 downto 0);\r
+ FRAMECOUNTER_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_0_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_1_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_2_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_3_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_4_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_5_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_6_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_7_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_8_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_9_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_10_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_11_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_12_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_13_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_14_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_15_IN : in std_logic_vector(3 downto 0);\r
+ FRC_ERROR_OUT : out std_logic; -- at least one framecounter is wrong\r
+ DBG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
+ end component frmctr_check;\r
+\r
+ component apv_pc_nc_alu is\r
+ port( CLK_IN : in std_logic; -- 100MHz master clock\r
+ RESET_IN : in std_logic;\r
+ START_IN : in std_logic;\r
+ MAX_FRAMES_IN : in std_logic_vector(3 downto 0); -- number of frames requested\r
+ CURR_FRAME_IN : in std_logic_vector(3 downto 0); -- current frame number\r
+ LOC_FRM_CTR_IN : in std_logic_vector(3 downto 0); -- DEBUG\r
+ EDS_FRM_CTR_IN : in std_logic_vector(3 downto 0); -- DEBUG\r
+ BUF_GOOD_IN : in std_logic;\r
+ BUF_BAD_IN : in std_logic;\r
+ BUF_IGNORE_IN : in std_logic;\r
+ ERROR_IN : in std_logic_vector(3 downto 0); -- buffer status, errors from checkers\r
+ DO_HEADER_IN : in std_logic;\r
+ DO_ERROR_IN : in std_logic;\r
+ EVT_TYPE_IN : in std_logic_vector(2 downto 0);\r
+ RAW_ADDR_IN : in std_logic_vector(6 downto 0);\r
+ RAW_DATA_IN : in std_logic_vector(37 downto 0);\r
+ PED_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_DATA_IN : in std_logic_vector(17 downto 0);\r
+ FRAME_IN : in std_logic;\r
+ FIFO_DATA_OUT : out std_logic_vector(26 downto 0); -- [21] -> [31], [20:0] -> [20:0]\r
+ WE_OUT : out std_logic;\r
+ COUNT_OUT : out std_logic_vector(9 downto 0);\r
+ ANYDATA_OUT : out std_logic; -- this FIFO needs attention during readout\r
+ DBG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
+ end component apv_pc_nc_alu;\r
+\r
+ component comp14bit is\r
+ port( DATAA : in std_logic_vector(13 downto 0); \r
+ DATAB : in std_logic_vector(13 downto 0); \r
+ CLOCK : in std_logic; \r
+ CLOCKEN : in std_logic; \r
+ ACLR : in std_logic; \r
+ AGEB : out std_logic\r
+ );\r
+ end component;\r
+\r
+ component input_bram is\r
+ port( WRADDRESS : in std_logic_vector(10 downto 0); \r
+ RDADDRESS : in std_logic_vector(10 downto 0); \r
+ DATA : in std_logic_vector(17 downto 0); \r
+ WE : in std_logic;\r
+ RDCLOCK : in std_logic; \r
+ RDCLOCKEN : in std_logic; \r
+ RESET : in std_logic; \r
+ WRCLOCK : in std_logic; \r
+ WRCLOCKEN : in std_logic; \r
+ Q : out std_logic_vector(17 downto 0)\r
+ );\r
+ end component;\r
+\r
+ component frame_status_mem is\r
+ port( WRADDRESS : in std_logic_vector(3 downto 0); \r
+ DATA : in std_logic_vector(11 downto 0);\r
+ WRCLOCK : in std_logic;\r
+ WE : in std_logic;\r
+ WRCLOCKEN : in std_logic;\r
+ RDADDRESS : in std_logic_vector(3 downto 0);\r
+ RDCLOCK : in std_logic;\r
+ RDCLOCKEN : in std_logic;\r
+ RESET : in std_logic;\r
+ Q : out std_logic_vector(11 downto 0)\r
+ );\r
+ end component;\r
+\r
+ component adder_6bit is\r
+ port( DATAA : in std_logic_vector(5 downto 0); \r
+ DATAB : in std_logic_vector(5 downto 0); \r
+ CLOCK : in std_logic; \r
+ RESET : in std_logic; \r
+ CLOCKEN : in std_logic; \r
+ RESULT : out std_logic_vector(5 downto 0)\r
+ );\r
+ end component;\r
+\r
+ component apv_lock_sm is\r
+ port( CLK_APV_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ SYNC_IN : in std_logic; -- start APV synchronisation\r
+ ADC_VALID_IN : in std_logic; -- ADC delivers valid data\r
+ TIMED_IN : in std_logic; -- synchronisation timeout\r
+ MATCH_IN : in std_logic; -- artifical tickmark from synchronized counter\r
+ LOCKED_IN : in std_logic; -- enough good tickmarks\r
+ TICK_IN : in std_logic; -- tickmark from digital parser\r
+ HEADER_IN : in std_logic; -- header from digital parser\r
+ FLATLINE_IN : in std_logic; -- flatline from digital parser\r
+ RST_PC_OUT : out std_logic; -- reset period counter\r
+ RST_TC_OUT : out std_logic; -- reset timeout counter\r
+ INC_TC_OUT : out std_logic;\r
+ RST_LC_OUT : out std_logic; -- reset lock counter\r
+ INC_LC_OUT : out std_logic;\r
+ UNKNOWN_OUT : out std_logic;\r
+ BADADC_OUT : out std_logic; -- ADC data invalid\r
+ LOCKED_OUT : out std_logic;\r
+ LOST_OUT : out std_logic;\r
+ NOSYNC_OUT : out std_logic;\r
+ NOAPV_OUT : out std_logic;\r
+ BSM_OUT : out std_logic_vector(7 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
+ end component;\r
+\r
+ component apv_digital is\r
+ port( CLK_APV_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ ADC_RAW_IN : in std_logic_vector(11 downto 0);\r
+ BIT_LOW_IN : in std_logic_vector(11 downto 0);\r
+ BIT_HIGH_IN : in std_logic_vector(11 downto 0);\r
+ FL_LOW_IN : in std_logic_vector(11 downto 0);\r
+ FL_HIGH_IN : in std_logic_vector(11 downto 0);\r
+ BIT_DATA_OUT : out std_logic_vector(11 downto 0);\r
+ BIT_VALID_OUT : out std_logic_vector(11 downto 0);\r
+ BIT_HIGH_OUT : out std_logic;\r
+ BIT_LOW_OUT : out std_logic;\r
+ TICKMARK_OUT : out std_logic;\r
+ HEADER_OUT : out std_logic;\r
+ FLAT_LINE_OUT : out std_logic\r
+ );\r
+ end component;\r
+\r
+ component eds_buffer_dpram is\r
+ port( WRADDRESS : in std_logic_vector(3 downto 0); \r
+ DATA : in std_logic_vector(39 downto 0); \r
+ WRCLOCK : in std_logic; \r
+ WE : in std_logic; \r
+ WRCLOCKEN : in std_logic; \r
+ RDADDRESS : in std_logic_vector(3 downto 0); \r
+ RDCLOCK : in std_logic; \r
+ RDCLOCKEN : in std_logic; \r
+ RESET : in std_logic; \r
+ Q : out std_logic_vector(39 downto 0)\r
+ );\r
+ end component;\r
+\r
+end package;\r
+\r
+-- Down in the Dumps...\r
+\r
--- /dev/null
+[Device]\r
+Family=latticeecp2m\r
+PartType=LFE2M100E\r
+PartName=LFE2M100E-6F900C\r
+SpeedGrade=-6\r
+Package=FPBGA900\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=Adder\r
+CoreRevision=3.1\r
+ModuleName=adder_16bit\r
+SourceFormat=VHDL\r
+ParameterFileVersion=1.0\r
+Date=03/03/2009\r
+Time=10:27:46\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+InputWidth=16\r
+Representation=Unsigned\r
+UseCIport=0\r
+COport=None\r
+OutReg=1\r
+Complex=0\r
+Stage=0\r
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v72_SP1_Build (24)
+-- Module Version: 3.1
+--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type add -width 16 -unsigned -output_reg -enable -pipeline 0 -e
+
+-- Tue Mar 03 10:27:46 2009
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity adder_16bit is
+ port (
+ DataA: in std_logic_vector(15 downto 0);
+ DataB: in std_logic_vector(15 downto 0);
+ Clock: in std_logic;
+ Reset: in std_logic;
+ ClockEn: in std_logic;
+ Result: out std_logic_vector(15 downto 0));
+end adder_16bit;
+
+architecture Structure of adder_16bit is
+
+ -- internal signal declarations
+ signal scuba_vhi: std_logic;
+ signal r0_sum15: std_logic;
+ signal r0_sum14: std_logic;
+ signal r0_sum13: std_logic;
+ signal r0_sum12: std_logic;
+ signal r0_sum11: std_logic;
+ signal r0_sum10: std_logic;
+ signal r0_sum9: std_logic;
+ signal r0_sum8: std_logic;
+ signal r0_sum7: std_logic;
+ signal r0_sum6: std_logic;
+ signal r0_sum5: std_logic;
+ signal r0_sum4: std_logic;
+ signal r0_sum3: std_logic;
+ signal r0_sum2: std_logic;
+ signal r0_sum1: std_logic;
+ signal r0_sum0: std_logic;
+ signal addsub_cod_0: std_logic;
+ signal tsum0: std_logic;
+ signal tsum1: std_logic;
+ signal tsum2: std_logic;
+ signal tsum3: std_logic;
+ signal co0: std_logic;
+ signal tsum4: std_logic;
+ signal tsum5: std_logic;
+ signal co1: std_logic;
+ signal tsum6: std_logic;
+ signal tsum7: std_logic;
+ signal co2: std_logic;
+ signal tsum8: std_logic;
+ signal tsum9: std_logic;
+ signal co3: std_logic;
+ signal tsum10: std_logic;
+ signal tsum11: std_logic;
+ signal co4: std_logic;
+ signal tsum12: std_logic;
+ signal tsum13: std_logic;
+ signal co5: std_logic;
+ signal tsum14: std_logic;
+ signal tsum15: std_logic;
+ signal co6: std_logic;
+ signal co7d: std_logic;
+ signal co7: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component FADD2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; COUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FD1P3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ attribute GSR : string;
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ FF_16: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>tsum15, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>r0_sum15);
+
+ FF_15: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>tsum14, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>r0_sum14);
+
+ FF_14: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>tsum13, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>r0_sum13);
+
+ FF_13: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>tsum12, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>r0_sum12);
+
+ FF_12: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>tsum11, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>r0_sum11);
+
+ FF_11: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>tsum10, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>r0_sum10);
+
+ FF_10: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>tsum9, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>r0_sum9);
+
+ FF_9: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>tsum8, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>r0_sum8);
+
+ FF_8: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>tsum7, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>r0_sum7);
+
+ FF_7: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>tsum6, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>r0_sum6);
+
+ FF_6: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>tsum5, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>r0_sum5);
+
+ FF_5: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>tsum4, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>r0_sum4);
+
+ FF_4: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>tsum3, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>r0_sum3);
+
+ FF_3: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>tsum2, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>r0_sum2);
+
+ FF_2: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>tsum1, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>r0_sum1);
+
+ FF_1: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>tsum0, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>r0_sum0);
+
+ FF_0: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>co7d, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>addsub_cod_0);
+
+ addsub_0: FADD2B
+ port map (A0=>DataA(0), A1=>DataA(1), B0=>DataB(0), B1=>DataB(1),
+ CI=>scuba_vlo, COUT=>co0, S0=>tsum0, S1=>tsum1);
+
+ addsub_1: FADD2B
+ port map (A0=>DataA(2), A1=>DataA(3), B0=>DataB(2), B1=>DataB(3),
+ CI=>co0, COUT=>co1, S0=>tsum2, S1=>tsum3);
+
+ addsub_2: FADD2B
+ port map (A0=>DataA(4), A1=>DataA(5), B0=>DataB(4), B1=>DataB(5),
+ CI=>co1, COUT=>co2, S0=>tsum4, S1=>tsum5);
+
+ addsub_3: FADD2B
+ port map (A0=>DataA(6), A1=>DataA(7), B0=>DataB(6), B1=>DataB(7),
+ CI=>co2, COUT=>co3, S0=>tsum6, S1=>tsum7);
+
+ addsub_4: FADD2B
+ port map (A0=>DataA(8), A1=>DataA(9), B0=>DataB(8), B1=>DataB(9),
+ CI=>co3, COUT=>co4, S0=>tsum8, S1=>tsum9);
+
+ addsub_5: FADD2B
+ port map (A0=>DataA(10), A1=>DataA(11), B0=>DataB(10),
+ B1=>DataB(11), CI=>co4, COUT=>co5, S0=>tsum10, S1=>tsum11);
+
+ addsub_6: FADD2B
+ port map (A0=>DataA(12), A1=>DataA(13), B0=>DataB(12),
+ B1=>DataB(13), CI=>co5, COUT=>co6, S0=>tsum12, S1=>tsum13);
+
+ addsub_7: FADD2B
+ port map (A0=>DataA(14), A1=>DataA(15), B0=>DataB(14),
+ B1=>DataB(15), CI=>co6, COUT=>co7, S0=>tsum14, S1=>tsum15);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ addsubd: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co7, COUT=>open, S0=>co7d, S1=>open);
+
+ Result(15) <= r0_sum15;
+ Result(14) <= r0_sum14;
+ Result(13) <= r0_sum13;
+ Result(12) <= r0_sum12;
+ Result(11) <= r0_sum11;
+ Result(10) <= r0_sum10;
+ Result(9) <= r0_sum9;
+ Result(8) <= r0_sum8;
+ Result(7) <= r0_sum7;
+ Result(6) <= r0_sum6;
+ Result(5) <= r0_sum5;
+ Result(4) <= r0_sum4;
+ Result(3) <= r0_sum3;
+ Result(2) <= r0_sum2;
+ Result(1) <= r0_sum1;
+ Result(0) <= r0_sum0;
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of adder_16bit is
+ for Structure
+ for all:FADD2B use entity ecp2m.FADD2B(V); end for;
+ for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
+ for all:VHI use entity ecp2m.VHI(V); end for;
+ for all:VLO use entity ecp2m.VLO(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_SP1_Build (24)
+-- Module Version: 3.1
+-- Tue Mar 03 10:27:46 2009
+
+-- parameterized module component declaration
+component adder_16bit
+ port (DataA: in std_logic_vector(15 downto 0);
+ DataB: in std_logic_vector(15 downto 0); Clock: in std_logic;
+ Reset: in std_logic; ClockEn: in std_logic;
+ Result: out std_logic_vector(15 downto 0));
+end component;
+
+-- parameterized module component instance
+__ : adder_16bit
+ port map (DataA(15 downto 0)=>__, DataB(15 downto 0)=>__, Clock=>__,
+ Reset=>__, ClockEn=>__, Result(15 downto 0)=>__);
--- /dev/null
+[Device]\r
+Family=latticeecp2m\r
+PartType=LFE2M100E\r
+PartName=LFE2M100E-6F900C\r
+SpeedGrade=-6\r
+Package=FPBGA900\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=Adder\r
+CoreRevision=3.1\r
+ModuleName=adder_5bit\r
+SourceFormat=VHDL\r
+ParameterFileVersion=1.0\r
+Date=03/03/2009\r
+Time=10:10:12\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+InputWidth=5\r
+Representation=Unsigned\r
+UseCIport=0\r
+COport=None\r
+OutReg=1\r
+Complex=0\r
+Stage=0\r
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v72_SP1_Build (24)
+-- Module Version: 3.1
+--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type add -width 5 -unsigned -output_reg -enable -e
+
+-- Tue Mar 03 10:10:12 2009
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity adder_5bit is
+ port (
+ DataA: in std_logic_vector(4 downto 0);
+ DataB: in std_logic_vector(4 downto 0);
+ Clock: in std_logic;
+ Reset: in std_logic;
+ ClockEn: in std_logic;
+ Result: out std_logic_vector(4 downto 0));
+end adder_5bit;
+
+architecture Structure of adder_5bit is
+
+ -- internal signal declarations
+ signal scuba_vhi: std_logic;
+ signal r0_sum4: std_logic;
+ signal r0_sum3: std_logic;
+ signal r0_sum2: std_logic;
+ signal r0_sum1: std_logic;
+ signal r0_sum0: std_logic;
+ signal tsum0: std_logic;
+ signal tsum1: std_logic;
+ signal tsum2: std_logic;
+ signal tsum3: std_logic;
+ signal co0: std_logic;
+ signal tsum4: std_logic;
+ signal co1: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component FADD2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; COUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FD1P3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ attribute GSR : string;
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ FF_4: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>tsum4, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>r0_sum4);
+
+ FF_3: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>tsum3, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>r0_sum3);
+
+ FF_2: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>tsum2, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>r0_sum2);
+
+ FF_1: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>tsum1, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>r0_sum1);
+
+ FF_0: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>tsum0, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>r0_sum0);
+
+ addsub_0: FADD2B
+ port map (A0=>DataA(0), A1=>DataA(1), B0=>DataB(0), B1=>DataB(1),
+ CI=>scuba_vlo, COUT=>co0, S0=>tsum0, S1=>tsum1);
+
+ addsub_1: FADD2B
+ port map (A0=>DataA(2), A1=>DataA(3), B0=>DataB(2), B1=>DataB(3),
+ CI=>co0, COUT=>co1, S0=>tsum2, S1=>tsum3);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ addsub_2: FADD2B
+ port map (A0=>DataA(4), A1=>scuba_vlo, B0=>DataB(4),
+ B1=>scuba_vlo, CI=>co1, COUT=>open, S0=>tsum4, S1=>open);
+
+ Result(4) <= r0_sum4;
+ Result(3) <= r0_sum3;
+ Result(2) <= r0_sum2;
+ Result(1) <= r0_sum1;
+ Result(0) <= r0_sum0;
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of adder_5bit is
+ for Structure
+ for all:FADD2B use entity ecp2m.FADD2B(V); end for;
+ for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
+ for all:VHI use entity ecp2m.VHI(V); end for;
+ for all:VLO use entity ecp2m.VLO(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_SP1_Build (24)
+-- Module Version: 3.1
+-- Tue Mar 03 10:10:12 2009
+
+-- parameterized module component declaration
+component adder_5bit
+ port (DataA: in std_logic_vector(4 downto 0);
+ DataB: in std_logic_vector(4 downto 0); Clock: in std_logic;
+ Reset: in std_logic; ClockEn: in std_logic;
+ Result: out std_logic_vector(4 downto 0));
+end component;
+
+-- parameterized module component instance
+__ : adder_5bit
+ port map (DataA(4 downto 0)=>__, DataB(4 downto 0)=>__, Clock=>__,
+ Reset=>__, ClockEn=>__, Result(4 downto 0)=>__);
--- /dev/null
+[Device]\r
+Family=latticeecp2m\r
+PartType=LFE2M35E\r
+PartName=LFE2M35E-6F672C\r
+SpeedGrade=-6\r
+Package=FPBGA672\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=Adder\r
+CoreRevision=3.1\r
+ModuleName=adder_6bit\r
+SourceFormat=VHDL\r
+ParameterFileVersion=1.0\r
+Date=08/27/2008\r
+Time=11:31:51\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+InputWidth=6\r
+Representation=Unsigned\r
+UseCIport=0\r
+COport=None\r
+OutReg=1\r
+Complex=0\r
+Stage=0\r
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v71_PROD_Build (58)
+-- Module Version: 3.1
+--X:\Programme\ispTOOLS_71\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type add -width 6 -unsigned -output_reg -enable -e
+
+-- Wed Aug 27 11:31:51 2008
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity adder_6bit is
+ port (
+ DataA: in std_logic_vector(5 downto 0);
+ DataB: in std_logic_vector(5 downto 0);
+ Clock: in std_logic;
+ Reset: in std_logic;
+ ClockEn: in std_logic;
+ Result: out std_logic_vector(5 downto 0));
+end adder_6bit;
+
+architecture Structure of adder_6bit is
+
+ -- internal signal declarations
+ signal scuba_vhi: std_logic;
+ signal r0_sum5: std_logic;
+ signal r0_sum4: std_logic;
+ signal r0_sum3: std_logic;
+ signal r0_sum2: std_logic;
+ signal r0_sum1: std_logic;
+ signal r0_sum0: std_logic;
+ signal addsub_cod_0: std_logic;
+ signal tsum0: std_logic;
+ signal tsum1: std_logic;
+ signal tsum2: std_logic;
+ signal tsum3: std_logic;
+ signal co0: std_logic;
+ signal tsum4: std_logic;
+ signal tsum5: std_logic;
+ signal co1: std_logic;
+ signal co2d: std_logic;
+ signal co2: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component FADD2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; COUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FD1P3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ attribute GSR : string;
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ FF_6: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>tsum5, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>r0_sum5);
+
+ FF_5: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>tsum4, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>r0_sum4);
+
+ FF_4: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>tsum3, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>r0_sum3);
+
+ FF_3: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>tsum2, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>r0_sum2);
+
+ FF_2: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>tsum1, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>r0_sum1);
+
+ FF_1: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>tsum0, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>r0_sum0);
+
+ FF_0: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>co2d, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>addsub_cod_0);
+
+ addsub_0: FADD2B
+ port map (A0=>DataA(0), A1=>DataA(1), B0=>DataB(0), B1=>DataB(1),
+ CI=>scuba_vlo, COUT=>co0, S0=>tsum0, S1=>tsum1);
+
+ addsub_1: FADD2B
+ port map (A0=>DataA(2), A1=>DataA(3), B0=>DataB(2), B1=>DataB(3),
+ CI=>co0, COUT=>co1, S0=>tsum2, S1=>tsum3);
+
+ addsub_2: FADD2B
+ port map (A0=>DataA(4), A1=>DataA(5), B0=>DataB(4), B1=>DataB(5),
+ CI=>co1, COUT=>co2, S0=>tsum4, S1=>tsum5);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ addsubd: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co2, COUT=>open, S0=>co2d, S1=>open);
+
+ Result(5) <= r0_sum5;
+ Result(4) <= r0_sum4;
+ Result(3) <= r0_sum3;
+ Result(2) <= r0_sum2;
+ Result(1) <= r0_sum1;
+ Result(0) <= r0_sum0;
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of adder_6bit is
+ for Structure
+ for all:FADD2B use entity ecp2m.FADD2B(V); end for;
+ for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
+ for all:VHI use entity ecp2m.VHI(V); end for;
+ for all:VLO use entity ecp2m.VLO(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v71_PROD_Build (58)
+-- Module Version: 3.1
+-- Wed Aug 27 11:31:51 2008
+
+-- parameterized module component declaration
+component adder_6bit
+ port (DataA: in std_logic_vector(5 downto 0);
+ DataB: in std_logic_vector(5 downto 0); Clock: in std_logic;
+ Reset: in std_logic; ClockEn: in std_logic;
+ Result: out std_logic_vector(5 downto 0));
+end component;
+
+-- parameterized module component instance
+__ : adder_6bit
+ port map (DataA(5 downto 0)=>__, DataB(5 downto 0)=>__, Clock=>__,
+ Reset=>__, ClockEn=>__, Result(5 downto 0)=>__);
--- /dev/null
+[Device]\r
+Family=latticeecp2m\r
+PartType=LFE2M100E\r
+PartName=LFE2M100E-6F900C\r
+SpeedGrade=-6\r
+Package=FPBGA900\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=Distributed_ROM\r
+CoreRevision=2.4\r
+ModuleName=apv_adc_map_mem\r
+SourceFormat=VHDL\r
+ParameterFileVersion=1.0\r
+Date=11/04/2009\r
+Time=16:10:56\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+Addresses=128\r
+Data=4\r
+LUT=0\r
+MemFile=i:/vhdl_pro/adcmv3/src/apv_adc_mapping.mem\r
+MemFormat=orca\r
--- /dev/null
+SCUBA, Version ispLever_v72_SP2_Build (23)
+Wed Nov 04 16:10:56 2009
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp. All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
+Copyright (c) 2001 Agere Systems All rights reserved.
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
+
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n apv_adc_map_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 7 -num_words 128 -data_width 4 -outdata UNREGISTERED -memfile i:/vhdl_pro/adcmv3/src/apv_adc_mapping.mem -memformat orca -e
+ Circuit name : apv_adc_map_mem
+ Module type : rom
+ Module Version : 2.4
+ Address width : 7
+ Ports :
+ Inputs : Address[6:0]
+ Outputs : Q[3:0]
+ I/O buffer : not inserted
+ Memory file : i:/vhdl_pro/adcmv3/src/apv_adc_mapping.mem
+ EDIF output : suppressed
+ VHDL output : apv_adc_map_mem.vhd
+ VHDL template : apv_adc_map_mem_tmpl.vhd
+ VHDL testbench : tb_apv_adc_map_mem_tmpl.vhd
+ VHDL purpose : for synthesis and simulation
+ Bus notation : big endian
+ Report output : apv_adc_map_mem.srp
+ Element Usage :
+ ROM128X1 : 4
+ Estimated Resource Usage:
+ LUT : 16
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23)
+-- Module Version: 2.4
+--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type rom -addr_width 7 -num_rows 128 -data_width 4 -outdata UNREGISTERED -memfile i:/vhdl_pro/adcmv3/src/apv_adc_mapping.mem -memformat orca -e
+
+-- Wed Nov 04 16:10:56 2009
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity apv_adc_map_mem is
+ port (
+ Address: in std_logic_vector(6 downto 0);
+ Q: out std_logic_vector(3 downto 0));
+end apv_adc_map_mem;
+
+architecture Structure of apv_adc_map_mem is
+
+ -- local component declarations
+ component ROM128X1
+ -- synopsys translate_off
+ generic (INITVAL : in String);
+ -- synopsys translate_on
+ port (AD6: in std_logic; AD5: in std_logic; AD4: in std_logic;
+ AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ attribute initval : string;
+ attribute initval of mem_0_3 : label is "0xFF00FF00FF001FE0E01F7F80807F6956";
+ attribute initval of mem_0_2 : label is "0xF0F0F0F0F0F0079DF8621E0FE1F0E287";
+ attribute initval of mem_0_1 : label is "0xCCCCCCCCCCCC867A798519ECE6139D07";
+ attribute initval of mem_0_0 : label is "0xAAAAAAAAAAAA3553CAAC355ACAA5B1E2";
+
+begin
+ -- component instantiation statements
+ mem_0_3: ROM128X1
+ -- synopsys translate_off
+ generic map (initval=> "0xFF00FF00FF001FE0E01F7F80807F6956")
+ -- synopsys translate_on
+ port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4),
+ AD3=>Address(3), AD2=>Address(2), AD1=>Address(1),
+ AD0=>Address(0), DO0=>Q(3));
+
+ mem_0_2: ROM128X1
+ -- synopsys translate_off
+ generic map (initval=> "0xF0F0F0F0F0F0079DF8621E0FE1F0E287")
+ -- synopsys translate_on
+ port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4),
+ AD3=>Address(3), AD2=>Address(2), AD1=>Address(1),
+ AD0=>Address(0), DO0=>Q(2));
+
+ mem_0_1: ROM128X1
+ -- synopsys translate_off
+ generic map (initval=> "0xCCCCCCCCCCCC867A798519ECE6139D07")
+ -- synopsys translate_on
+ port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4),
+ AD3=>Address(3), AD2=>Address(2), AD1=>Address(1),
+ AD0=>Address(0), DO0=>Q(1));
+
+ mem_0_0: ROM128X1
+ -- synopsys translate_off
+ generic map (initval=> "0xAAAAAAAAAAAA3553CAAC355ACAA5B1E2")
+ -- synopsys translate_on
+ port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4),
+ AD3=>Address(3), AD2=>Address(2), AD1=>Address(1),
+ AD0=>Address(0), DO0=>Q(0));
+
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of apv_adc_map_mem is
+ for Structure
+ for all:ROM128X1 use entity ecp2m.ROM128X1(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+Starting process: \r
+\r
+SCUBA, Version ispLever_v72_SP2_Build (23)\r
+Wed Nov 04 16:10:56 2009\r
+\r
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
+Copyright (c) 1995 AT&T Corp. All rights reserved.\r
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
+Copyright (c) 2001 Agere Systems All rights reserved.\r
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
+\r
+BEGIN SCUBA Module Synthesis\r
+\r
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n apv_adc_map_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 7 -num_words 128 -data_width 4 -outdata UNREGISTERED -memfile i:/vhdl_pro/adcmv3/src/apv_adc_mapping.mem -memformat orca -e \r
+ Circuit name : apv_adc_map_mem\r
+ Module type : rom\r
+ Module Version : 2.4\r
+ Address width : 7\r
+ Data width : 4\r
+ Ports : \r
+ Inputs : Address[6:0]\r
+ Outputs : Q[3:0]\r
+ I/O buffer : not inserted\r
+ Memory file : i:/vhdl_pro/adcmv3/src/apv_adc_mapping.mem\r
+ EDIF output : suppressed\r
+ VHDL output : apv_adc_map_mem.vhd\r
+ VHDL template : apv_adc_map_mem_tmpl.vhd\r
+ VHDL testbench : tb_apv_adc_map_mem_tmpl.vhd\r
+ VHDL purpose : for synthesis and simulation\r
+ Bus notation : big endian\r
+ Report output : apv_adc_map_mem.srp\r
+ Estimated Resource Usage:\r
+ LUT : 16\r
+\r
+END SCUBA Module Synthesis\r
+\r
+File: ..\src\apv_adc_map_mem.lpc created.\r
+\r
+\r
+End process: completed successfully.\r
+\r
+\r
+Total Warnings: 0\r
+\r
+Total Errors: 0\r
+\r
+\r
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23)
+-- Module Version: 2.4
+-- Wed Nov 04 16:10:56 2009
+
+-- parameterized module component declaration
+component apv_adc_map_mem
+ port (Address: in std_logic_vector(6 downto 0);
+ Q: out std_logic_vector(3 downto 0));
+end component;
+
+-- parameterized module component instance
+__ : apv_adc_map_mem
+ port map (Address(6 downto 0)=>__, Q(3 downto 0)=>__);
--- /dev/null
+#Format=Address-Hex\r
+#Depth=128\r
+#DataWidth=4\r
+#AddrRadix=3\r
+#DataRadix=3\r
+\r
+# Backplane 0\r
+# realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15\r
+# mapAPV 3 5 10 12 9 7 0 - 4 6 11 8 14 13 2 1\r
+#\r
+# mapAPV 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15\r
+# realADC 6 15 14 0 8 1 9 5 b 4 2 a 3 d c 7\r
+00: 6\r
+01: f\r
+02: e\r
+03: 0\r
+04: 8\r
+05: 1\r
+06: 9\r
+07: 5\r
+08: b\r
+09: 4\r
+0a: 2\r
+0b: a\r
+0c: 3\r
+0d: d\r
+0e: c\r
+0f: 7\r
+# Backplane 1\r
+# realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15\r
+# mapAPV 12 11 10 9 8 7 13 14 3 2 1 0 6 5 4 -\r
+10: b\r
+11: a\r
+12: 9\r
+13: 8\r
+14: e\r
+15: d\r
+16: c\r
+17: 5\r
+18: 4\r
+19: 3\r
+1a: 2\r
+1b: 1\r
+1c: 0\r
+1d: 6\r
+1e: 7\r
+1f: f\r
+# Backplane 2\r
+# realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15\r
+# mapAPV - 4 5 6 0 1 2 3 14 13 7 8 9 10 11 12\r
+20: 4 \r
+21: 5\r
+22: 6\r
+23: 7\r
+24: 1\r
+25: 2\r
+26: 3\r
+27: a\r
+28: b\r
+29: c\r
+2a: d\r
+2b: e\r
+2c: f\r
+2d: 9\r
+2e: 8\r
+2f: 0\r
+# Backplane 3\r
+# realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15\r
+# mapAPV 10 9 8 7 6 5 12 11 4 3 0 2 1 - 13 14\r
+30: a\r
+31: c\r
+32: b\r
+33: 9\r
+34: 8\r
+35: 5\r
+36: 4\r
+37: 3\r
+38: 2\r
+39: 1\r
+3a: 0\r
+3b: 7\r
+3c: 6\r
+3d: e\r
+3e: f\r
+3f: d\r
+# Backplane 4\r
+# realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15\r
+# mapAPV 14 13 - 1 2 0 3 4 11 12 5 6 7 8 9 10\r
+40: 5\r
+41: 3\r
+42: 4\r
+43: 6\r
+44: 7\r
+45: a\r
+46: b\r
+47: c\r
+48: d\r
+49: e\r
+4a: f\r
+4b: 8\r
+4c: 9\r
+4d: 1\r
+4e: 0\r
+4f: 2\r
+# unused (5) => 1:1\r
+50: 0\r
+51: 1\r
+52: 2\r
+53: 3\r
+54: 4\r
+55: 5\r
+56: 6\r
+57: 7\r
+58: 8\r
+59: 9\r
+5a: a\r
+5b: b\r
+5c: c\r
+5d: d\r
+5e: e\r
+5f: f\r
+# unused (6) => 1:1\r
+60: 0\r
+61: 1\r
+62: 2\r
+63: 3\r
+64: 4\r
+65: 5\r
+66: 6\r
+67: 7\r
+68: 8\r
+69: 9\r
+6a: a\r
+6b: b\r
+6c: c\r
+6d: d\r
+6e: e\r
+6f: f\r
+# unused (7) => 1:1\r
+70: 0\r
+71: 1\r
+72: 2\r
+73: 3\r
+74: 4\r
+75: 5\r
+76: 6\r
+77: 7\r
+78: 8\r
+79: 9\r
+7a: a\r
+7b: b\r
+7c: c\r
+7d: d\r
+7e: e\r
+7f: f\r
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.std_logic_arith.all;\r
+use ieee.std_logic_unsigned.all;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+entity apv_digital is\r
+ port( CLK_APV_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ ADC_RAW_IN : in std_logic_vector(11 downto 0);\r
+ BIT_LOW_IN : in std_logic_vector(11 downto 0);\r
+ BIT_HIGH_IN : in std_logic_vector(11 downto 0);\r
+ FL_LOW_IN : in std_logic_vector(11 downto 0);\r
+ FL_HIGH_IN : in std_logic_vector(11 downto 0);\r
+ BIT_DATA_OUT : out std_logic_vector(11 downto 0);\r
+ BIT_VALID_OUT : out std_logic_vector(11 downto 0);\r
+ BIT_HIGH_OUT : out std_logic;\r
+ BIT_LOW_OUT : out std_logic;\r
+ TICKMARK_OUT : out std_logic;\r
+ HEADER_OUT : out std_logic;\r
+ FLAT_LINE_OUT : out std_logic\r
+ );\r
+end;\r
+\r
+architecture behavioral of apv_digital is\r
+\r
+ signal next_bit_low : std_logic;\r
+ signal bit_low : std_logic;\r
+ signal next_bit_high : std_logic;\r
+ signal bit_high : std_logic;\r
+ signal next_bit_data : std_logic;\r
+ signal bit_data : std_logic_vector(11 downto 0);\r
+ signal next_bit_valid : std_logic;\r
+ signal bit_valid : std_logic_vector(11 downto 0);\r
+ signal next_fl_low : std_logic;\r
+ signal fl_low : std_logic;\r
+ signal next_fl_high : std_logic;\r
+ signal fl_high : std_logic;\r
+ signal next_fl_found : std_logic;\r
+ signal fl_found : std_logic_vector(2 downto 0);\r
+ signal next_flat_line : std_logic;\r
+ signal flat_line : std_logic;\r
+ signal next_tickmark : std_logic;\r
+ signal tickmark : std_logic;\r
+ signal next_header : std_logic;\r
+ signal header : std_logic;\r
+ \r
+begin\r
+\r
+-- ADC data is registered already, so we can operate on the inputs directly.\r
+\r
+--------------------------------------------------------------------------------------\r
+-- compare ADC raw data against "bit low" threshold, \r
+-- generate combinatorial "low" bit\r
+THE_BL_COMP: process( adc_raw_in, bit_low_in )\r
+begin\r
+ if( adc_raw_in < bit_low_in ) then\r
+ next_bit_low <= '1';\r
+ else\r
+ next_bit_low <= '0';\r
+ end if;\r
+end process THE_BL_COMP;\r
+\r
+-- compare ADC raw data against "bit high" threshold, \r
+--generate combinatorial "high" bit\r
+THE_BH_COMP: process( adc_raw_in, bit_high_in )\r
+begin\r
+ if( adc_raw_in > bit_high_in ) then\r
+ next_bit_high <= '1';\r
+ else\r
+ next_bit_high <= '0';\r
+ end if;\r
+end process THE_BH_COMP;\r
+\r
+-- store comparator result, enable pipelining\r
+THE_BIT_STORE_ONE: process( clk_apv_in )\r
+begin\r
+ if( rising_edge(clk_apv_in) ) then\r
+ if( reset_in = '1' ) then\r
+ bit_high <= '0';\r
+ bit_low <= '0';\r
+ else\r
+ bit_high <= next_bit_high;\r
+ bit_low <= next_bit_low;\r
+ end if;\r
+ end if;\r
+end process THE_BIT_STORE_ONE;\r
+\r
+-- decode real bits with valid signal (10 => '1', 01 => '0', rest invalid)\r
+next_bit_data <= bit_high and not bit_low;\r
+next_bit_valid <= bit_high xor bit_low;\r
+\r
+THE_BIT_SHIFT: process( clk_apv_in )\r
+begin\r
+ if( rising_edge(clk_apv_in) ) then\r
+ if( reset_in = '1' ) then\r
+ bit_valid <= (others => '0');\r
+ bit_data <= (others => '0');\r
+ else\r
+ bit_valid(11 downto 1) <= bit_valid(10 downto 0);\r
+ bit_valid(0) <= next_bit_valid;\r
+ bit_data(11 downto 1 ) <= bit_data(10 downto 0);\r
+ bit_data(0) <= next_bit_data;\r
+ end if;\r
+ end if;\r
+end process THE_BIT_SHIFT;\r
+\r
+-- tickmark recognition: as stupid as possible, as easy as possible\r
+next_tickmark <= '1' when (bit_data(2 downto 0) = "100") else '0';\r
+\r
+-- header recognition: as stupid as possible, as easy as possible\r
+next_header <= '1' when (bit_data(2 downto 0) = "111") else '0';\r
+\r
+-- store tickmark and header result, enable pipelining\r
+THE_BIT_STORE_TWO: process( clk_apv_in )\r
+begin\r
+ if( rising_edge(clk_apv_in) ) then\r
+ if( reset_in = '1' ) then\r
+ tickmark <= '0';\r
+ header <= '0';\r
+ else\r
+ tickmark <= next_tickmark;\r
+ header <= next_header;\r
+ end if;\r
+ end if;\r
+end process THE_BIT_STORE_TWO;\r
+\r
+\r
+--------------------------------------------------------------------------------------\r
+-- flatline recognition: in case of missing APV the ADC amplifier stage is\r
+-- "shortcut" by 100Ohm and will give a flat line on half on the ADC range.\r
+THE_FLL_COMP: process( adc_raw_in, fl_low_in )\r
+begin\r
+ if( adc_raw_in > fl_low_in ) then\r
+ next_fl_low <= '1';\r
+ else\r
+ next_fl_low <= '0';\r
+ end if;\r
+end process THE_FLL_COMP;\r
+\r
+THE_FLH_COMP: process( adc_raw_in, fl_high_in )\r
+begin\r
+ if( adc_raw_in < fl_high_in ) then\r
+ next_fl_high <= '1';\r
+ else\r
+ next_fl_high <= '0';\r
+ end if;\r
+end process THE_FLH_COMP;\r
+\r
+-- register stage one: avoid long combinatorial delays\r
+THE_FL_REG_STAGE_ONE: process( clk_apv_in )\r
+begin\r
+ if( rising_edge(clk_apv_in) ) then\r
+ if( reset_in = '1' ) then\r
+ fl_high <= '0';\r
+ fl_low <= '0';\r
+ else\r
+ fl_high <= next_fl_high;\r
+ fl_low <= next_fl_low;\r
+ end if;\r
+ end if;\r
+end process THE_FL_REG_STAGE_ONE;\r
+\r
+-- ADC signal must between lower and upper range\r
+next_fl_found <= fl_high and fl_low;\r
+\r
+-- flatline shift register\r
+THE_FL_SHIFTER: process( clk_apv_in )\r
+begin\r
+ if( rising_edge(clk_apv_in) ) then\r
+ if( reset_in = '1' ) then\r
+ fl_found <= (others => '0');\r
+ else\r
+ fl_found(2 downto 0) <= fl_found(1 downto 0) & next_fl_found;\r
+ end if;\r
+ end if;\r
+end process THE_FL_SHIFTER;\r
+\r
+-- majority decision\r
+next_flat_line <= ( fl_found(2) and fl_found(1) and fl_found(0)) or\r
+ (not fl_found(2) and fl_found(1) and fl_found(0)) or\r
+ ( fl_found(2) and fl_found(1) and not fl_found(0));\r
+\r
+-- register stage two: avoid long combinatorial delays\r
+THE_FL_REG_STAGE_TWO: process( clk_apv_in )\r
+begin\r
+ if( rising_edge(clk_apv_in) ) then\r
+ if( reset_in = '1' ) then\r
+ flat_line <= '0';\r
+ else\r
+ flat_line <= next_flat_line;\r
+ end if;\r
+ end if;\r
+end process THE_FL_REG_STAGE_TWO;\r
+\r
+-- output signals\r
+bit_data_out <= bit_data;\r
+bit_valid_out <= bit_valid;\r
+flat_line_out <= flat_line;\r
+tickmark_out <= tickmark;\r
+header_out <= header;\r
+bit_high_out <= bit_high;\r
+bit_low_out <= bit_low;\r
+\r
+end behavioral;\r
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.std_logic_arith.all;\r
+use ieee.std_logic_unsigned.all;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+entity apv_lock_sm is\r
+ port( CLK_APV_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ SYNC_IN : in std_logic; -- start APV synchronisation\r
+ ADC_VALID_IN : in std_logic; -- ADC delivers valid data\r
+ TIMED_IN : in std_logic; -- synchronisation timeout\r
+ MATCH_IN : in std_logic; -- artifical tickmark from synchronized counter\r
+ LOCKED_IN : in std_logic; -- enough good tickmarks\r
+ TICK_IN : in std_logic; -- tickmark from digital parser\r
+ HEADER_IN : in std_logic; -- header from digital parser\r
+ FLATLINE_IN : in std_logic; -- flatline from digital parser\r
+ RST_PC_OUT : out std_logic; -- reset period counter\r
+ RST_TC_OUT : out std_logic; -- reset timeout counter\r
+ INC_TC_OUT : out std_logic;\r
+ RST_LC_OUT : out std_logic; -- reset lock counter\r
+ INC_LC_OUT : out std_logic;\r
+ UNKNOWN_OUT : out std_logic; -- status unknown\r
+ BADADC_OUT : out std_logic; -- ADC data invalid\r
+ LOCKED_OUT : out std_logic; -- APV locked successfully\r
+ LOST_OUT : out std_logic; -- APV sync is lost\r
+ NOSYNC_OUT : out std_logic; -- APV sync failed\r
+ NOAPV_OUT : out std_logic; -- no APV connected\r
+ BSM_OUT : out std_logic_vector(7 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
+end;\r
+\r
+architecture behavioral of apv_lock_sm is\r
+\r
+ -- State definition\r
+ -- SLEEP : initial reset state\r
+ -- CLEAR : clear counters and registers\r
+ -- UWSYNC : wait for SYNC_IN to deassert\r
+ -- USYNC : teaching phase, not synchronized yet\r
+ -- U_BADM : tickmark found, but local counter mismatch\r
+ -- U_BADP : local counter match, but no tickmark found\r
+ -- U_GOOD : local counter and tickmark match\r
+ -- U_TIME : locking timed out\r
+ -- U_FLAT : no APV connected (open input)\r
+ -- U_ADC : ADC data is marked invaled (ser2par failed)\r
+ -- SYNCED : APV is locked, normal operation state\r
+ -- S_BADM : spurious tickmark found => fatal\r
+ -- S_BADM : missing tickmark => fatal\r
+ -- S_BADD : spurious data frame found, or bad tickmark after dataframe => fatal\r
+ -- S_GOOD : local counter and tickmark match\r
+ -- S_DATA : data frame header found at correct position\r
+ -- S_FR0 : first tickmark period of data frame\r
+ -- S_FR1 : second tickmark period of data frame\r
+ -- S_FR2 : third tickmark period of data frame\r
+ -- S_FR3 : fourth tickmark period of data frame\r
+ -- S_ADC : ADC data is marked invalid (ser2par failed)\r
+ -- S_LOST : lock lost in normal operation => fatal\r
+\r
+ -- state machine signals\r
+ type STATES is (SLEEP, CLEAR, USYNC, UWSYNC, U_BADM, U_BADP, U_GOOD, U_TIME, U_FLAT, U_ADC,\r
+ SYNCED, S_BADP, S_BADM, S_GOOD, S_DATA, S_FR0, S_FR1, S_FR2, S_FR3,\r
+ S_BADD, S_LOST, S_ADC);\r
+ signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+ -- normal signals\r
+ signal bsm : std_logic_vector(7 downto 0);\r
+ signal debug : std_logic_vector(15 downto 0);\r
+ signal next_rst_tc : std_logic;\r
+ signal rst_tc : std_logic;\r
+ signal next_inc_tc : std_logic;\r
+ signal inc_tc : std_logic;\r
+ signal next_rst_lc : std_logic;\r
+ signal rst_lc : std_logic;\r
+ signal next_inc_lc : std_logic;\r
+ signal inc_lc : std_logic;\r
+ signal next_rst_pc : std_logic;\r
+ signal rst_pc : std_logic;\r
+ signal next_unknown : std_logic;\r
+ signal unknown : std_logic;\r
+ signal next_badadc : std_logic;\r
+ signal badadc : std_logic;\r
+ signal next_locked : std_logic;\r
+ signal locked : std_logic;\r
+ signal next_lost : std_logic;\r
+ signal lost : std_logic;\r
+ signal next_nosync : std_logic;\r
+ signal nosync : std_logic;\r
+ signal next_noapv : std_logic;\r
+ signal noapv : std_logic; \r
+ signal next_dataframe : std_logic;\r
+ signal dataframe : std_logic;\r
+ \r
+begin\r
+\r
+debug <= (others => '0');\r
+\r
+-- state machine for handling synchronisation\r
+-- state registers\r
+STATE_MEM: process( clk_apv_in ) \r
+begin\r
+ if( rising_edge(clk_apv_in) ) then\r
+ if( reset_in = '1' ) then\r
+ CURRENT_STATE <= SLEEP;\r
+ rst_pc <= '0';\r
+ rst_lc <= '0';\r
+ inc_lc <= '0';\r
+ rst_tc <= '0';\r
+ inc_tc <= '0';\r
+ unknown <= '1';\r
+ badadc <= '0';\r
+ locked <= '0';\r
+ lost <= '0';\r
+ nosync <= '0';\r
+ noapv <= '0';\r
+ dataframe <= '0';\r
+ else\r
+ CURRENT_STATE <= NEXT_STATE;\r
+ rst_pc <= next_rst_pc;\r
+ rst_lc <= next_rst_lc;\r
+ inc_lc <= next_inc_lc;\r
+ rst_tc <= next_rst_tc;\r
+ inc_tc <= next_inc_tc;\r
+ unknown <= next_unknown;\r
+ badadc <= next_badadc;\r
+ locked <= next_locked;\r
+ lost <= next_lost;\r
+ nosync <= next_nosync;\r
+ noapv <= next_noapv;\r
+ dataframe <= next_dataframe;\r
+ end if;\r
+ end if;\r
+end process STATE_MEM;\r
+\r
+-- state transitions\r
+STATE_TRANSFORM: process( CURRENT_STATE, sync_in, match_in, tick_in, header_in, timed_in, locked_in, flatline_in, adc_valid_in )\r
+begin\r
+ NEXT_STATE <= SLEEP; -- avoid latches\r
+ next_rst_pc <= '0'; \r
+ next_rst_lc <= '0'; \r
+ next_inc_lc <= '0';\r
+ next_rst_tc <= '0'; \r
+ next_inc_tc <= '0';\r
+ next_unknown <= '0';\r
+ next_badadc <= '0';\r
+ next_locked <= '0';\r
+ next_lost <= '0';\r
+ next_nosync <= '0';\r
+ next_noapv <= '0';\r
+ next_dataframe <= '0';\r
+ case CURRENT_STATE is\r
+ when SLEEP => if( sync_in = '1' ) then\r
+ NEXT_STATE <= CLEAR; -- start synchronisation\r
+ next_rst_pc <= '1';\r
+ next_rst_lc <= '1';\r
+ next_rst_tc <= '1';\r
+ next_unknown <= '1';\r
+ else\r
+ NEXT_STATE <= SLEEP;\r
+ next_unknown <= '1';\r
+ end if;\r
+ when CLEAR => NEXT_STATE <= UWSYNC;\r
+ next_unknown <= '1';\r
+ when UWSYNC => if ( (sync_in = '0') and (adc_valid_in = '1') ) then\r
+ NEXT_STATE <= USYNC;\r
+ next_unknown <= '1';\r
+ elsif( (sync_in = '0') and (adc_valid_in = '0') ) then\r
+ NEXT_STATE <= U_ADC;\r
+ next_badadc <= '1';\r
+ else\r
+ NEXT_STATE <= UWSYNC;\r
+ next_unknown <= '1';\r
+ end if;\r
+ when USYNC => if ( (timed_in = '0') and (tick_in = '1') and (match_in = '0') ) then\r
+ NEXT_STATE <= U_BADM; -- local timer not correct\r
+ next_rst_pc <= '1';\r
+ next_inc_tc <= '1';\r
+ next_rst_lc <= '1';\r
+ next_unknown <= '1';\r
+ elsif( (timed_in = '0') and (tick_in = '0') and (match_in = '1') ) then\r
+ NEXT_STATE <= U_BADP; -- tickmark position not correct\r
+ next_rst_lc <= '1';\r
+ next_inc_tc <= '1';\r
+ next_unknown <= '1';\r
+ elsif( (timed_in = '1') and (flatline_in = '0') ) then\r
+ NEXT_STATE <= U_TIME; -- timeout\r
+ next_nosync <= '1';\r
+ elsif( (timed_in = '1') and (flatline_in = '1') ) then\r
+ NEXT_STATE <= U_FLAT; -- no APV connected\r
+ next_noapv <= '1';\r
+ elsif( (timed_in = '0') and (tick_in = '1') and (locked_in = '0') ) then\r
+ NEXT_STATE <= U_GOOD; -- tickmark and counter match\r
+ next_inc_lc <= '1';\r
+ next_inc_tc <= '1';\r
+ next_unknown <= '1';\r
+ elsif( (timed_in = '0') and (tick_in = '1') and (locked_in = '1') ) then\r
+ NEXT_STATE <= SYNCED; -- finally locked\r
+ next_locked <= '1';\r
+ else\r
+ NEXT_STATE <= USYNC; -- wait for events\r
+ next_unknown <= '1';\r
+ end if;\r
+ when U_BADM => NEXT_STATE <= USYNC;\r
+ next_unknown <= '1';\r
+ when U_BADP => NEXT_STATE <= USYNC;\r
+ next_unknown <= '1';\r
+ when U_GOOD => NEXT_STATE <= USYNC;\r
+ next_unknown <= '1';\r
+ when U_FLAT => if( sync_in = '1' ) then\r
+ NEXT_STATE <= CLEAR; -- next try\r
+ next_rst_pc <= '1';\r
+ next_rst_lc <= '1';\r
+ next_rst_tc <= '1';\r
+ next_unknown <= '1';\r
+ next_locked <= '0';\r
+ next_lost <= '0';\r
+ next_nosync <= '0';\r
+ next_noapv <= '0';\r
+ else\r
+ NEXT_STATE <= U_FLAT;\r
+ next_noapv <= '1';\r
+ end if;\r
+ when U_TIME => if( sync_in = '1' ) then\r
+ NEXT_STATE <= CLEAR; -- next try\r
+ next_rst_pc <= '1';\r
+ next_rst_lc <= '1';\r
+ next_rst_tc <= '1';\r
+ next_unknown <= '1';\r
+ next_locked <= '0';\r
+ next_lost <= '0';\r
+ next_nosync <= '0';\r
+ next_noapv <= '0';\r
+ else\r
+ NEXT_STATE <= U_TIME;\r
+ next_nosync <= '1';\r
+ end if;\r
+ when U_ADC => if( sync_in = '1' ) then\r
+ NEXT_STATE <= CLEAR; -- next try\r
+ next_rst_pc <= '1';\r
+ next_rst_lc <= '1';\r
+ next_rst_tc <= '1';\r
+ next_unknown <= '1';\r
+ next_locked <= '0';\r
+ next_lost <= '0';\r
+ next_nosync <= '0';\r
+ next_noapv <= '0';\r
+ else\r
+ NEXT_STATE <= U_ADC;\r
+ next_badadc <= '1';\r
+ end if;\r
+ when SYNCED => if ( sync_in = '1' ) then\r
+ NEXT_STATE <= CLEAR;\r
+ next_rst_pc <= '1';\r
+ next_rst_lc <= '1';\r
+ next_rst_tc <= '1';\r
+ next_unknown <= '1';\r
+ next_locked <= '0';\r
+ next_lost <= '0';\r
+ next_nosync <= '0';\r
+ next_noapv <= '0';\r
+ elsif( (sync_in = '0') and (adc_valid_in = '0') ) then\r
+ NEXT_STATE <= S_ADC;\r
+ next_badadc <= '1';\r
+ elsif( (sync_in = '0') and (adc_valid_in = '1') and (match_in = '0') and (tick_in = '1') and (header_in = '0') ) then\r
+ NEXT_STATE <= S_BADM;\r
+ next_lost <= '1';\r
+ elsif( (sync_in = '0') and (adc_valid_in = '1') and (match_in = '0') and (tick_in = '0') and (header_in = '1') ) then\r
+ NEXT_STATE <= S_BADD;\r
+ next_lost <= '1';\r
+ elsif( (sync_in = '0') and (adc_valid_in = '1') and (match_in = '1') and (tick_in = '0') and (header_in = '0') ) then\r
+ NEXT_STATE <= S_BADP;\r
+ next_lost <= '1';\r
+ elsif( (sync_in = '0') and (adc_valid_in = '1') and (match_in = '1') and (tick_in = '1') ) then\r
+ NEXT_STATE <= S_GOOD;\r
+ next_locked <= '1';\r
+ elsif( (sync_in = '0') and (adc_valid_in = '1') and (match_in = '1') and (header_in = '1') ) then\r
+ NEXT_STATE <= S_DATA;\r
+ next_locked <= '1';\r
+ else\r
+ NEXT_STATE <= SYNCED;\r
+ next_locked <= '1';\r
+ end if;\r
+ when S_GOOD => NEXT_STATE <= SYNCED;\r
+ next_locked <= '1';\r
+ when S_DATA => if( sync_in = '1' ) then\r
+ NEXT_STATE <= CLEAR;\r
+ next_rst_pc <= '1';\r
+ next_rst_lc <= '1';\r
+ next_rst_tc <= '1';\r
+ next_unknown <= '1';\r
+ next_locked <= '0';\r
+ next_lost <= '0';\r
+ next_nosync <= '0';\r
+ next_noapv <= '0';\r
+ else\r
+ NEXT_STATE <= S_FR0;\r
+ next_dataframe <= '1';\r
+ next_locked <= '1';\r
+ end if;\r
+ when S_FR0 => if ( sync_in = '1' ) then\r
+ NEXT_STATE <= CLEAR;\r
+ next_rst_pc <= '1';\r
+ next_rst_lc <= '1';\r
+ next_rst_tc <= '1';\r
+ next_unknown <= '1';\r
+ next_locked <= '0';\r
+ next_lost <= '0';\r
+ next_nosync <= '0';\r
+ next_noapv <= '0';\r
+ elsif( (sync_in = '0') and (match_in = '1') ) then\r
+ NEXT_STATE <= S_FR1;\r
+ next_dataframe <= '1';\r
+ next_locked <= '1';\r
+ else\r
+ NEXT_STATE <= S_FR0;\r
+ next_dataframe <= '1';\r
+ next_locked <= '1';\r
+ end if;\r
+ when S_FR1 => if ( sync_in = '1' ) then\r
+ NEXT_STATE <= CLEAR;\r
+ next_rst_pc <= '1';\r
+ next_rst_lc <= '1';\r
+ next_rst_tc <= '1';\r
+ next_unknown <= '1';\r
+ next_locked <= '0';\r
+ next_lost <= '0';\r
+ next_nosync <= '0';\r
+ next_noapv <= '0';\r
+ elsif( (sync_in = '0') and (match_in = '1') ) then\r
+ NEXT_STATE <= S_FR2;\r
+ next_dataframe <= '1';\r
+ next_locked <= '1';\r
+ else\r
+ NEXT_STATE <= S_FR1;\r
+ next_dataframe <= '1';\r
+ next_locked <= '1';\r
+ end if;\r
+ when S_FR2 => if ( sync_in = '1' ) then\r
+ NEXT_STATE <= CLEAR;\r
+ next_rst_pc <= '1';\r
+ next_rst_lc <= '1';\r
+ next_rst_tc <= '1';\r
+ next_unknown <= '1';\r
+ next_locked <= '0';\r
+ next_lost <= '0';\r
+ next_nosync <= '0';\r
+ next_noapv <= '0';\r
+ elsif( (sync_in = '0') and (match_in = '1') ) then\r
+ NEXT_STATE <= S_FR3;\r
+ next_dataframe <= '1';\r
+ next_locked <= '1';\r
+ else\r
+ NEXT_STATE <= S_FR2;\r
+ next_dataframe <= '1';\r
+ next_locked <= '1';\r
+ end if;\r
+ when S_FR3 => if ( sync_in = '1' ) then\r
+ NEXT_STATE <= CLEAR;\r
+ next_rst_pc <= '1';\r
+ next_rst_lc <= '1';\r
+ next_rst_tc <= '1';\r
+ next_unknown <= '1';\r
+ next_locked <= '0';\r
+ next_lost <= '0';\r
+ next_nosync <= '0';\r
+ next_noapv <= '0';\r
+ elsif( (sync_in = '0') and (match_in = '1') and (tick_in = '1') ) then\r
+ NEXT_STATE <= SYNCED;\r
+ next_locked <= '1';\r
+ elsif( (sync_in = '0') and (match_in = '1') and (header_in = '1') ) then\r
+ NEXT_STATE <= S_DATA;\r
+ next_locked <= '1';\r
+ elsif( (sync_in = '0') and (match_in = '1') and (header_in = '0') and (tick_in = '0') ) then\r
+ NEXT_STATE <= S_BADD;\r
+ else\r
+ NEXT_STATE <= S_FR3;\r
+ next_dataframe <= '1';\r
+ next_locked <= '1';\r
+ end if;\r
+ when S_BADD => NEXT_STATE <= S_LOST;\r
+ next_lost <= '1';\r
+ when S_BADM => NEXT_STATE <= S_LOST;\r
+ next_lost <= '1';\r
+ when S_BADP => NEXT_STATE <= S_LOST;\r
+ next_lost <= '1';\r
+ when S_ADC => NEXT_STATE <= S_LOST;\r
+ next_lost <= '1';\r
+ when S_LOST => if( sync_in = '1' ) then\r
+ NEXT_STATE <= CLEAR; -- next try\r
+ next_rst_pc <= '1';\r
+ next_rst_lc <= '1';\r
+ next_rst_tc <= '1';\r
+ next_unknown <= '1';\r
+ next_locked <= '0';\r
+ next_lost <= '0';\r
+ next_nosync <= '0';\r
+ next_noapv <= '0';\r
+ else\r
+ NEXT_STATE <= S_LOST;\r
+ next_lost <= '1';\r
+ end if;\r
+ when others => NEXT_STATE <= SLEEP;\r
+ next_unknown <= '1';\r
+ end case;\r
+end process STATE_TRANSFORM;\r
+\r
+-- state decoding\r
+STATE_DECODE: process( CURRENT_STATE )\r
+begin\r
+ case CURRENT_STATE is\r
+ when SLEEP => bsm <= x"00";\r
+ when CLEAR => bsm <= x"01";\r
+ when UWSYNC => bsm <= x"20"; \r
+ when USYNC => bsm <= x"02";\r
+ when U_BADM => bsm <= x"03";\r
+ when U_BADP => bsm <= x"04";\r
+ when U_FLAT => bsm <= x"05";\r
+ when U_GOOD => bsm <= x"06";\r
+ when U_TIME => bsm <= x"07";\r
+ when U_ADC => bsm <= x"08";\r
+ when SYNCED => bsm <= x"09";\r
+ when S_BADP => bsm <= x"0a";\r
+ when S_BADM => bsm <= x"0b";\r
+ when S_GOOD => bsm <= x"0c";\r
+ when S_DATA => bsm <= x"0d";\r
+ when S_FR0 => bsm <= x"0e";\r
+ when S_FR1 => bsm <= x"0f";\r
+ when S_FR2 => bsm <= x"10";\r
+ when S_FR3 => bsm <= x"11";\r
+ when S_BADD => bsm <= x"12";\r
+ when S_ADC => bsm <= x"13";\r
+ when S_LOST => bsm <= x"14";\r
+ when others => bsm <= x"ff";\r
+ end case;\r
+end process STATE_DECODE;\r
+\r
+-- output signals\r
+debug_out <= debug;\r
+bsm_out <= bsm;\r
+unknown_out <= unknown;\r
+badadc_out <= badadc;\r
+locked_out <= locked;\r
+lost_out <= lost;\r
+nosync_out <= nosync;\r
+noapv_out <= noapv;\r
+rst_pc_out <= rst_pc;\r
+rst_lc_out <= rst_lc;\r
+rst_tc_out <= rst_tc;\r
+inc_lc_out <= inc_lc;\r
+inc_tc_out <= inc_tc;\r
+\r
+end behavioral;\r
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.std_logic_arith.all;\r
+use ieee.std_logic_unsigned.all;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+-- This block takes care of syncing in the APVs. Only "synced" APVs are allowed to deliver data streams \r
+-- to the processing units. \r
+\r
+entity apv_locker is\r
+ port( CLK_APV_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ ADC_RAW_IN : in std_logic_vector(11 downto 0); -- ADC: raw data, synchronous to CLK_APV_IN\r
+ ADC_VALID_IN : in std_logic; -- ADC: ser2par data is valid\r
+ -- Slow control input, mainly digital thresholds here\r
+ SYNC_IN : in std_logic; -- sync pulse input \r
+ APV_ON_IN : in std_logic; -- this APV channel is switched on\r
+ BIT_LOW_IN : in std_logic_vector(11 downto 0); -- slow control: threshold for digital '0'\r
+ BIT_HIGH_IN : in std_logic_vector(11 downto 0); -- slow control: threshold for digital '1'\r
+ FL_LOW_IN : in std_logic_vector(11 downto 0); -- lower threshold for ADC flatline\r
+ FL_HIGH_IN : in std_logic_vector(11 downto 0); -- upper threshold for ADC flatline\r
+ -- Generic APV status outputs (valid only if ADC_CLK_IN is working!)\r
+ STATUS_IGNORE_OUT : out std_logic; -- APV is to be ignored (effectively => switched off)\r
+ STATUS_BADADC_OUT : out std_logic; -- ADC ser2par data is invalid\r
+ STATUS_UNKNOWN_OUT : out std_logic; -- APV is not initialized yet\r
+ STATUS_LOCKED_OUT : out std_logic; -- APV locked successfully\r
+ STATUS_LOST_OUT : out std_logic; -- APV tickmark missing or wrong\r
+ STATUS_NOSYNC_OUT : out std_logic; -- APV did not lock successfully\r
+ STATUS_MISSING_OUT : out std_logic; -- APV is missing, ADC flatline detected\r
+ STATUS_TICKMARK_OUT : out std_logic;\r
+ -- Frame related status, to be stored in the raw status buffer\r
+ -- Information is valid with APV_LAST_OUT, except FRAME_ERROR_OUT, FRAME_ROW_OUT and \r
+ -- FRAME_CTR_OUT which are valid with beginning of APV_ANALOG_OUT.\r
+ FRAME_ROW_OUT : out std_logic_vector(7 downto 0); -- decoded row from APV header\r
+ FRAME_ERROR_OUT : out std_logic; -- decoded error bit from APV header\r
+ FRAME_FLAT_OUT : out std_logic; -- APV sends a flat line (analog dead?)\r
+ FRAME_OVF_OUT : out std_logic; -- at least one channel in frame was overflow\r
+ FRAME_UDF_OUT : out std_logic; -- at least one channel in frame was underflow\r
+ FRAME_CTR_OUT : out std_logic_vector(3 downto 0); -- frame counter for incoming data frames\r
+ -- Channel related information, to be stored in the raw data buffer\r
+ APV_CHANNEL_OUT : out std_logic_vector(6 downto 0); -- physical channel ID\r
+ APV_OVERFLOW_OUT : out std_logic; -- channel is truncated high\r
+ APV_UNDERFLOW_OUT : out std_logic; -- channel is truncated low\r
+ APV_RAW_OUT : out std_logic_vector(11 downto 0); -- APV raw data\r
+ APV_ANALOG_OUT : out std_logic; -- APV analog data is valid\r
+ APV_START_OUT : out std_logic; -- valid data frame found, reserve one buffer \r
+ APV_LAST_OUT : out std_logic; -- last APV channel of dataframe\r
+ -- Debug information\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
+end;\r
+\r
+architecture behavioral of apv_locker is\r
+\r
+ -- normal signals\r
+ signal lock_bsm : std_logic_vector(7 downto 0);\r
+ signal tickmark_found : std_logic;\r
+ signal header_found : std_logic;\r
+ signal flatline_found : std_logic;\r
+ signal status_unknown : std_logic;\r
+ signal status_badadc : std_logic;\r
+ signal status_locked : std_logic;\r
+ signal status_lost : std_logic;\r
+ signal status_nosync : std_logic;\r
+ signal status_missing : std_logic;\r
+ signal next_status_ignore : std_logic;\r
+ signal status_ignore : std_logic;\r
+ signal frame_flat : std_logic;\r
+ signal next_frame_ovf : std_logic;\r
+ signal frame_ovf : std_logic;\r
+ signal next_frame_udf : std_logic;\r
+ signal frame_udf : std_logic;\r
+ signal frame_row : std_logic_vector(7 downto 0);\r
+ signal frame_error : std_logic;\r
+ signal bit_data : std_logic_vector(11 downto 0);\r
+ signal bit_valid : std_logic_vector(11 downto 0);\r
+\r
+ signal rst_pc_sm : std_logic;\r
+ signal rst_pc_ctr : std_logic;\r
+ signal pc_ctr : std_logic_vector(5 downto 0);\r
+ signal next_pc_match : std_logic;\r
+ signal pc_match : std_logic;\r
+\r
+ signal rst_tc_sm : std_logic;\r
+ signal inc_tc_sm : std_logic;\r
+ signal tc_ctr : std_logic_vector(3 downto 0);\r
+ signal next_sync_timeout : std_logic;\r
+ signal sync_timeout : std_logic;\r
+\r
+ signal rst_lc_sm : std_logic;\r
+ signal inc_lc_sm : std_logic;\r
+ signal lc_ctr : std_logic_vector(3 downto 0);\r
+ signal next_sync_success : std_logic;\r
+ signal sync_success : std_logic;\r
+ \r
+ signal delay_store : std_logic_vector(7 downto 0);\r
+ signal store_header : std_logic;\r
+ \r
+ signal apv_channel : std_logic_vector(6 downto 0);\r
+ signal ce_chnl_ctr : std_logic;\r
+ signal frame_analog : std_logic;\r
+ signal set_frame_analog : std_logic;\r
+ signal rst_frame_analog : std_logic;\r
+ signal next_apv_last : std_logic;\r
+ signal apv_last : std_logic;\r
+ signal apv_start : std_logic;\r
+ \r
+ signal adc_raw_one : std_logic_vector(11 downto 0);\r
+ signal adc_raw_two : std_logic_vector(11 downto 0);\r
+ \r
+ signal bit_high : std_logic;\r
+ signal bit_low : std_logic;\r
+ signal apv_overflow : std_logic;\r
+ signal apv_underflow : std_logic;\r
+ \r
+ signal next_ce_underflow : std_logic;\r
+ signal next_ce_overflow : std_logic;\r
+\r
+ signal sum_ovf : std_logic_vector(7 downto 0);\r
+ signal sum_udf : std_logic_vector(7 downto 0);\r
+\r
+ signal frame_ctr : std_logic_vector(3 downto 0);\r
+ signal comb_ce_frame_ctr : std_logic;\r
+ \r
+ signal debug : std_logic_vector(15 downto 0);\r
+ \r
+ signal apv_on : std_logic; -- 40MHz clock domain register\r
+ \r
+begin\r
+\r
+-- Debug signals\r
+debug <= (others => '0');\r
+\r
+-- Clock domain crossing\r
+THE_APVON_SYNCER: state_sync\r
+port map( STATE_A_IN => apv_on_in,\r
+ CLK_B_IN => clk_apv_in,\r
+ RESET_B_IN => reset_in,\r
+ STATE_B_OUT => apv_on\r
+ );\r
+\r
+-- Input stage, for tickmark and header recognition, and bit decoding.\r
+-- Also detects missing APVs by flatline.\r
+THE_APV_DIGITAL: apv_digital\r
+port map( CLK_APV_IN => clk_apv_in,\r
+ RESET_IN => reset_in,\r
+ ADC_RAW_IN => adc_raw_in,\r
+ BIT_LOW_IN => bit_low_in,\r
+ BIT_HIGH_IN => bit_high_in,\r
+ FL_LOW_IN => fl_low_in,\r
+ FL_HIGH_IN => fl_high_in,\r
+ BIT_DATA_OUT => bit_data,\r
+ BIT_VALID_OUT => bit_valid, -- for testing!\r
+ BIT_HIGH_OUT => bit_high, -- for analog off recognition, one cycle earlier\r
+ BIT_LOW_OUT => bit_low, -- for analog off recognition, one cycle earlier\r
+ TICKMARK_OUT => tickmark_found,\r
+ HEADER_OUT => header_found,\r
+ FLAT_LINE_OUT => flatline_found\r
+ );\r
+\r
+-- Count enables for the underflow / overflow counters\r
+next_ce_underflow <= '1' when (bit_high = '0' and bit_low = '1' and frame_analog = '1') else '0';\r
+next_ce_overflow <= '1' when (bit_high = '1' and bit_low = '0' and frame_analog = '1') else '0';\r
+\r
+-- Counter for underflow channels\r
+THE_UNDERFLOW_CTR_PROC: process( clk_apv_in )\r
+begin \r
+ if( rising_edge(clk_apv_in) ) then\r
+ if( (reset_in = '1') or (delay_store(1) = '1') ) then\r
+ sum_udf <= (others => '0');\r
+ elsif( next_ce_underflow = '1' ) then\r
+ sum_udf <= sum_udf + 1; \r
+ end if;\r
+ end if;\r
+end process THE_UNDERFLOW_CTR_PROC;\r
+\r
+-- Reduced information: at least one channel was underflow\r
+next_frame_udf <= '1' when (sum_udf /= x"00") else '0';\r
+-- Reduced information: all channels in a frame were underflow\r
+frame_flat <= sum_udf(7);\r
+\r
+-- Counter for Overflow channels\r
+THE_OVERFLOW_CTR_PROC: process( clk_apv_in )\r
+begin \r
+ if( rising_edge(clk_apv_in) ) then\r
+ if( (reset_in = '1') or (delay_store(1) = '1') ) then\r
+ sum_ovf <= (others => '0');\r
+ elsif( next_ce_overflow = '1' ) then\r
+ sum_ovf <= sum_ovf + 1; \r
+ end if;\r
+ end if;\r
+end process THE_OVERFLOW_CTR_PROC;\r
+\r
+-- Reduced information: at least one channel was underflow\r
+next_frame_ovf <= '1' when (sum_ovf /= x"00") else '0';\r
+\r
+THE_SYNC_PROC: process( clk_apv_in )\r
+begin\r
+ if( rising_edge(clk_apv_in) ) then\r
+ apv_overflow <= next_ce_overflow;\r
+ apv_underflow <= next_ce_underflow;\r
+ frame_ovf <= next_frame_ovf;\r
+ frame_udf <= next_frame_udf;\r
+ status_ignore <= next_status_ignore;\r
+ end if;\r
+end process THE_SYNC_PROC;\r
+\r
+-- locking state machine\r
+THE_APV_LOCK_SM: apv_lock_sm\r
+port map( CLK_APV_IN => clk_apv_in,\r
+ RESET_IN => reset_in,\r
+ SYNC_IN => sync_in, -- 40 MHz signal!\r
+ ADC_VALID_IN => adc_valid_in,\r
+ TIMED_IN => sync_timeout,\r
+ MATCH_IN => pc_match,\r
+ LOCKED_IN => sync_success,\r
+ TICK_IN => tickmark_found,\r
+ HEADER_IN => header_found,\r
+ FLATLINE_IN => flatline_found,\r
+ RST_PC_OUT => rst_pc_sm,\r
+ RST_TC_OUT => rst_tc_sm,\r
+ INC_TC_OUT => inc_tc_sm,\r
+ RST_LC_OUT => rst_lc_sm,\r
+ INC_LC_OUT => inc_lc_sm,\r
+ UNKNOWN_OUT => status_unknown,\r
+ BADADC_OUT => status_badadc,\r
+ LOCKED_OUT => status_locked,\r
+ LOST_OUT => status_lost,\r
+ NOSYNC_OUT => status_nosync,\r
+ NOAPV_OUT => status_missing,\r
+ BSM_OUT => lock_bsm,\r
+ DEBUG_OUT => open\r
+ );\r
+\r
+next_status_ignore <= not apv_on;\r
+\r
+\r
+-- synchronous reset for period counter (either by counter, or by state machine)\r
+next_pc_match <= '1' when ( pc_ctr = "100000" ) else '0'; -- "100001"\r
+\r
+-- period counter (0..34) for one tickmark period\r
+THE_PERIOD_COUNTER: process( clk_apv_in )\r
+begin\r
+ if( rising_edge(clk_apv_in) ) then\r
+ if ( (reset_in = '1') or (rst_pc_sm = '1') or (rst_pc_ctr = '1')) then\r
+ pc_ctr <= (others => '0');\r
+ pc_match <= '0';\r
+ rst_pc_ctr <= '0';\r
+ else\r
+ pc_ctr <= pc_ctr + 1;\r
+ pc_match <= next_pc_match;\r
+ rst_pc_ctr <= pc_match;\r
+ end if; \r
+ end if;\r
+end process THE_PERIOD_COUNTER;\r
+\r
+-- watermark for the synchronisation timeout\r
+next_sync_timeout <= '1' when ( tc_ctr = x"f" ) else '0';\r
+\r
+-- timeout counter for the lock process\r
+THE_TIMEOUT_COUNTER: process( clk_apv_in )\r
+begin\r
+ if( rising_edge(clk_apv_in) ) then\r
+ if ( (reset_in = '1') or (rst_tc_sm = '1') ) then\r
+ tc_ctr <= (others => '0');\r
+ sync_timeout <= '0';\r
+ elsif( inc_tc_sm = '1' ) then\r
+ tc_ctr <= tc_ctr + 1;\r
+ sync_timeout <= next_sync_timeout;\r
+ end if;\r
+ end if;\r
+end process THE_TIMEOUT_COUNTER;\r
+\r
+-- watermark for the successful synchronisation \r
+next_sync_success <= '1' when ( lc_ctr = x"8" ) else '0';\r
+\r
+-- lock counter for the lock process\r
+THE_LOCK_COUNTER: process( clk_apv_in )\r
+begin\r
+ if( rising_edge(clk_apv_in) ) then\r
+ if ( (reset_in = '1') or (rst_lc_sm = '1') ) then\r
+ lc_ctr <= (others => '0');\r
+ sync_success <= '0';\r
+ elsif( inc_lc_sm = '1' ) then\r
+ lc_ctr <= lc_ctr + 1;\r
+ sync_success <= next_sync_success;\r
+ end if;\r
+ end if;\r
+end process THE_LOCK_COUNTER;\r
+\r
+-- registering the APV header needs some delay for header_found\r
+THE_DELAY_LINE: process( clk_apv_in )\r
+begin\r
+ if( rising_edge(clk_apv_in) ) then\r
+ if( reset_in = '1' ) then\r
+ delay_store <= (others => '0');\r
+ else\r
+ delay_store(7 downto 1) <= delay_store(6 downto 0);\r
+ -- we only accept data frames when they arrive at a well defined tickmark place, \r
+ -- when the APV is really switched on, and it is in locked state.\r
+ delay_store(0) <= header_found and pc_match and apv_on and status_locked;\r
+ end if;\r
+ end if;\r
+end process THE_DELAY_LINE;\r
+\r
+-- frame start signal for early blocking of the buffer page\r
+apv_start <= delay_store(0);\r
+\r
+-- here we can adjust the correct delay for the pipelining\r
+store_header <= delay_store(7);\r
+\r
+-- enable signal for underflow / overflow counters\r
+next_apv_last <= '1' when (apv_channel = "1111110") else '0';\r
+set_frame_analog <= '1' when (delay_store(6) = '1') else '0';\r
+rst_frame_analog <= '1' when (next_apv_last = '1') else '0';\r
+\r
+-- frame counter clock enable\r
+comb_ce_frame_ctr <= apv_last;\r
+\r
+-- analog frame, one cycle before output data.\r
+THE_FRAME_ANALOG_PROC: process( clk_apv_in )\r
+begin\r
+ if( rising_edge(clk_apv_in) ) then\r
+ if( reset_in = '1' ) then\r
+ frame_analog <= '0';\r
+ elsif( set_frame_analog = '1' ) then\r
+ frame_analog <= '1';\r
+ elsif( rst_frame_analog = '1' ) then\r
+ frame_analog <= '0';\r
+ end if;\r
+ end if;\r
+end process THE_FRAME_ANALOG_PROC;\r
+\r
+-- real counter for channels is one cycle later\r
+THE_CE_CHNL_CTR_PROC: process( clk_apv_in )\r
+begin\r
+ if( rising_edge(clk_apv_in) ) then\r
+ if( reset_in = '1' ) then\r
+ ce_chnl_ctr <= '0';\r
+ else\r
+ ce_chnl_ctr <= frame_analog;\r
+ end if;\r
+ end if;\r
+end process THE_CE_CHNL_CTR_PROC;\r
+\r
+-- Channel counter, used for timing and PID generation\r
+THE_CHANNEL_CTR: process( clk_apv_in )\r
+begin\r
+ if( rising_edge(clk_apv_in) ) then\r
+ if ( reset_in = '1' ) then\r
+ apv_channel <= (others => '0');\r
+ apv_last <= '0';\r
+ elsif( ce_chnl_ctr = '1' ) then\r
+ apv_channel <= apv_channel + 1;\r
+ apv_last <= next_apv_last;\r
+ end if;\r
+ end if;\r
+end process THE_CHANNEL_CTR;\r
+\r
+THE_APV_RAW_DELAY: process( clk_apv_in )\r
+begin\r
+ if( rising_edge(clk_apv_in) ) then\r
+ adc_raw_two <= adc_raw_one;\r
+ adc_raw_one <= adc_raw_in;\r
+ end if;\r
+end process THE_APV_RAW_DELAY;\r
+\r
+-- storage registers\r
+THE_HEADER_STORAGE_PROC: process( clk_apv_in )\r
+begin\r
+ if( rising_edge(clk_apv_in) ) then\r
+ if ( reset_in = '1' ) then\r
+ frame_error <= '0'; -- bit is inverted!\r
+ frame_row <= (others => '0'); \r
+ elsif( store_header = '1' ) then\r
+ frame_error <= not bit_data(0); -- bit is inverted!\r
+ frame_row <= bit_data(8 downto 1);\r
+ end if;\r
+ end if;\r
+end process THE_HEADER_STORAGE_PROC;\r
+\r
+-- frame counter logic\r
+THE_FRAME_CTR_PROC: process( clk_apv_in )\r
+begin\r
+ if( rising_edge(clk_apv_in) ) then\r
+ if ( reset_in = '1' ) then\r
+ frame_ctr <= (others => '0');\r
+ elsif( comb_ce_frame_ctr = '1' ) then\r
+ frame_ctr <= frame_ctr + 1;\r
+ end if;\r
+ end if;\r
+end process THE_FRAME_CTR_PROC;\r
+\r
+\r
+-- output signals\r
+status_ignore_out <= status_ignore;\r
+status_unknown_out <= status_unknown;\r
+status_badadc_out <= status_badadc;\r
+status_locked_out <= status_locked;\r
+status_lost_out <= status_lost;\r
+status_nosync_out <= status_nosync;\r
+status_missing_out <= status_missing;\r
+status_tickmark_out <= pc_match;\r
+\r
+-- Changing SID to PID on the fly for free\r
+-- Keep in mind: 1- 0- 3- 2- 6- 5- 4\r
+apv_channel_out(6) <= apv_channel(1);\r
+apv_channel_out(5) <= apv_channel(0);\r
+apv_channel_out(4) <= apv_channel(3);\r
+apv_channel_out(3) <= apv_channel(2);\r
+apv_channel_out(2) <= apv_channel(6);\r
+apv_channel_out(1) <= apv_channel(5);\r
+apv_channel_out(0) <= apv_channel(4);\r
+\r
+apv_raw_out <= adc_raw_two;\r
+apv_overflow_out <= apv_overflow;\r
+apv_underflow_out <= apv_underflow;\r
+apv_analog_out <= ce_chnl_ctr;\r
+apv_start_out <= apv_start;\r
+apv_last_out <= apv_last;\r
+\r
+frame_flat_out <= frame_flat;\r
+frame_ovf_out <= frame_ovf;\r
+frame_udf_out <= frame_udf;\r
+frame_ctr_out <= frame_ctr;\r
+frame_error_out <= frame_error;\r
+frame_row_out <= frame_row;\r
+\r
+-- Debug signals, do not use!\r
+debug_out <= debug;\r
+\r
+end behavioral;\r
--- /dev/null
+[Device]\r
+Family=latticeecp2m\r
+PartType=LFE2M100E\r
+PartName=LFE2M100E-6F900C\r
+SpeedGrade=-6\r
+Package=FPBGA900\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=Distributed_ROM\r
+CoreRevision=2.4\r
+ModuleName=apv_map_mem\r
+SourceFormat=VHDL\r
+ParameterFileVersion=1.0\r
+Date=10/14/2009\r
+Time=17:47:59\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+Addresses=128\r
+Data=4\r
+LUT=0\r
+MemFile=i:/vhdl_pro/adcmv3/src/apv_mapping.mem\r
+MemFormat=orca\r
--- /dev/null
+SCUBA, Version ispLever_v72_SP2_Build (23)
+Wed Oct 14 17:47:59 2009
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp. All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
+Copyright (c) 2001 Agere Systems All rights reserved.
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
+
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n apv_map_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 7 -num_words 128 -data_width 4 -outdata UNREGISTERED -memfile i:/vhdl_pro/adcmv2/src/apv_mapping.mem -memformat orca -e
+ Circuit name : apv_map_mem
+ Module type : rom
+ Module Version : 2.4
+ Address width : 7
+ Ports :
+ Inputs : Address[6:0]
+ Outputs : Q[3:0]
+ I/O buffer : not inserted
+ Memory file : i:/vhdl_pro/adcmv2/src/apv_mapping.mem
+ EDIF output : suppressed
+ VHDL output : apv_map_mem.vhd
+ VHDL template : apv_map_mem_tmpl.vhd
+ VHDL testbench : tb_apv_map_mem_tmpl.vhd
+ VHDL purpose : for synthesis and simulation
+ Bus notation : big endian
+ Report output : apv_map_mem.srp
+ Element Usage :
+ ROM128X1 : 4
+ Estimated Resource Usage:
+ LUT : 16
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23)
+-- Module Version: 2.4
+--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type rom -addr_width 7 -num_rows 128 -data_width 4 -outdata UNREGISTERED -memfile i:/vhdl_pro/adcmv2/src/apv_mapping.mem -memformat orca -e
+
+-- Wed Oct 14 17:47:59 2009
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity apv_map_mem is
+ port (
+ Address: in std_logic_vector(6 downto 0);
+ Q: out std_logic_vector(3 downto 0));
+end apv_map_mem;
+
+architecture Structure of apv_map_mem is
+
+ -- local component declarations
+ component ROM128X1
+ -- synopsys translate_off
+ generic (INITVAL : in String);
+ -- synopsys translate_on
+ port (AD6: in std_logic; AD5: in std_logic; AD4: in std_logic;
+ AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ attribute initval : string;
+ attribute initval of mem_0_3 : label is "0xFF00FF00FF001FE0E01F7F80807F6956";
+ attribute initval of mem_0_2 : label is "0xF0F0F0F0F0F0079DF8621E0FE1F0E287";
+ attribute initval of mem_0_1 : label is "0xCCCCCCCCCCCC867A798519ECE6139D07";
+ attribute initval of mem_0_0 : label is "0xAAAAAAAAAAAA3553CAAC355ACAA5B1E2";
+
+begin
+ -- component instantiation statements
+ mem_0_3: ROM128X1
+ -- synopsys translate_off
+ generic map (initval=> "0xFF00FF00FF001FE0E01F7F80807F6956")
+ -- synopsys translate_on
+ port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4),
+ AD3=>Address(3), AD2=>Address(2), AD1=>Address(1),
+ AD0=>Address(0), DO0=>Q(3));
+
+ mem_0_2: ROM128X1
+ -- synopsys translate_off
+ generic map (initval=> "0xF0F0F0F0F0F0079DF8621E0FE1F0E287")
+ -- synopsys translate_on
+ port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4),
+ AD3=>Address(3), AD2=>Address(2), AD1=>Address(1),
+ AD0=>Address(0), DO0=>Q(2));
+
+ mem_0_1: ROM128X1
+ -- synopsys translate_off
+ generic map (initval=> "0xCCCCCCCCCCCC867A798519ECE6139D07")
+ -- synopsys translate_on
+ port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4),
+ AD3=>Address(3), AD2=>Address(2), AD1=>Address(1),
+ AD0=>Address(0), DO0=>Q(1));
+
+ mem_0_0: ROM128X1
+ -- synopsys translate_off
+ generic map (initval=> "0xAAAAAAAAAAAA3553CAAC355ACAA5B1E2")
+ -- synopsys translate_on
+ port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4),
+ AD3=>Address(3), AD2=>Address(2), AD1=>Address(1),
+ AD0=>Address(0), DO0=>Q(0));
+
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of apv_map_mem is
+ for Structure
+ for all:ROM128X1 use entity ecp2m.ROM128X1(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+Starting process: \r
+\r
+SCUBA, Version ispLever_v72_SP2_Build (23)\r
+Wed Oct 14 17:47:59 2009\r
+\r
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
+Copyright (c) 1995 AT&T Corp. All rights reserved.\r
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
+Copyright (c) 2001 Agere Systems All rights reserved.\r
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
+\r
+BEGIN SCUBA Module Synthesis\r
+\r
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n apv_map_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 7 -num_words 128 -data_width 4 -outdata UNREGISTERED -memfile i:/vhdl_pro/adcmv2/src/apv_mapping.mem -memformat orca -e \r
+ Circuit name : apv_map_mem\r
+ Module type : rom\r
+ Module Version : 2.4\r
+ Address width : 7\r
+ Data width : 4\r
+ Ports : \r
+ Inputs : Address[6:0]\r
+ Outputs : Q[3:0]\r
+ I/O buffer : not inserted\r
+ Memory file : i:/vhdl_pro/adcmv2/src/apv_mapping.mem\r
+ EDIF output : suppressed\r
+ VHDL output : apv_map_mem.vhd\r
+ VHDL template : apv_map_mem_tmpl.vhd\r
+ VHDL testbench : tb_apv_map_mem_tmpl.vhd\r
+ VHDL purpose : for synthesis and simulation\r
+ Bus notation : big endian\r
+ Report output : apv_map_mem.srp\r
+ Estimated Resource Usage:\r
+ LUT : 16\r
+\r
+END SCUBA Module Synthesis\r
+\r
+File: ..\src\apv_map_mem.lpc created.\r
+\r
+\r
+End process: completed successfully.\r
+\r
+\r
+Total Warnings: 0\r
+\r
+Total Errors: 0\r
+\r
+\r
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23)
+-- Module Version: 2.4
+-- Wed Oct 14 17:47:59 2009
+
+-- parameterized module component declaration
+component apv_map_mem
+ port (Address: in std_logic_vector(6 downto 0);
+ Q: out std_logic_vector(3 downto 0));
+end component;
+
+-- parameterized module component instance
+__ : apv_map_mem
+ port map (Address(6 downto 0)=>__, Q(3 downto 0)=>__);
--- /dev/null
+#Format=Address-Hex\r
+#Depth=128\r
+#DataWidth=4\r
+#AddrRadix=3\r
+#DataRadix=3\r
+\r
+# Backplane 0\r
+# realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15\r
+# mapAPV 3 5 10 12 9 7 0 - 4 6 11 8 14 13 2 1\r
+#\r
+# mapAPV 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15\r
+# realADC 6 15 14 0 8 1 9 5 b 4 2 a 3 d c 7\r
+00: 6\r
+01: f\r
+02: e\r
+03: 0\r
+04: 8\r
+05: 1\r
+06: 9\r
+07: 5\r
+08: b\r
+09: 4\r
+0a: 2\r
+0b: a\r
+0c: 3\r
+0d: d\r
+0e: c\r
+0f: 7\r
+# Backplane 1\r
+# realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15\r
+# mapAPV 12 11 10 9 8 7 13 14 3 2 1 0 6 5 4 -\r
+10: b\r
+11: a\r
+12: 9\r
+13: 8\r
+14: e\r
+15: d\r
+16: c\r
+17: 5\r
+18: 4\r
+19: 3\r
+1a: 2\r
+1b: 1\r
+1c: 0\r
+1d: 6\r
+1e: 7\r
+1f: f\r
+# Backplane 2\r
+# realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15\r
+# mapAPV - 4 5 6 0 1 2 3 14 13 7 8 9 10 11 12\r
+20: 4 \r
+21: 5\r
+22: 6\r
+23: 7\r
+24: 1\r
+25: 2\r
+26: 3\r
+27: a\r
+28: b\r
+29: c\r
+2a: d\r
+2b: e\r
+2c: f\r
+2d: 9\r
+2e: 8\r
+2f: 0\r
+# Backplane 3\r
+# realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15\r
+# mapAPV 10 9 8 7 6 5 12 11 4 3 0 2 1 - 13 14\r
+30: a\r
+31: c\r
+32: b\r
+33: 9\r
+34: 8\r
+35: 5\r
+36: 4\r
+37: 3\r
+38: 2\r
+39: 1\r
+3a: 0\r
+3b: 7\r
+3c: 6\r
+3d: e\r
+3e: f\r
+3f: d\r
+# Backplane 4\r
+# realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15\r
+# mapAPV 14 13 - 1 2 0 3 4 11 12 5 6 7 8 9 10\r
+40: 5\r
+41: 3\r
+42: 4\r
+43: 6\r
+44: 7\r
+45: a\r
+46: b\r
+47: c\r
+48: d\r
+49: e\r
+4a: f\r
+4b: 8\r
+4c: 9\r
+4d: 1\r
+4e: 0\r
+4f: 2\r
+# unused (5) => 1:1\r
+50: 0\r
+51: 1\r
+52: 2\r
+53: 3\r
+54: 4\r
+55: 5\r
+56: 6\r
+57: 7\r
+58: 8\r
+59: 9\r
+5a: a\r
+5b: b\r
+5c: c\r
+5d: d\r
+5e: e\r
+5f: f\r
+# unused (6) => 1:1\r
+60: 0\r
+61: 1\r
+62: 2\r
+63: 3\r
+64: 4\r
+65: 5\r
+66: 6\r
+67: 7\r
+68: 8\r
+69: 9\r
+6a: a\r
+6b: b\r
+6c: c\r
+6d: d\r
+6e: e\r
+6f: f\r
+# unused (7) => 1:1\r
+70: 0\r
+71: 1\r
+72: 2\r
+73: 3\r
+74: 4\r
+75: 5\r
+76: 6\r
+77: 7\r
+78: 8\r
+79: 9\r
+7a: a\r
+7b: b\r
+7c: c\r
+7d: d\r
+7e: e\r
+7f: f\r
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.std_logic_arith.all;\r
+use ieee.std_logic_unsigned.all;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+-- IMPORTANT: 0,2,4,...,126 => physics channels\r
+-- 1,3,5,...,127 => empty channels\r
+\r
+-- This unit takes frame data (channel order is fixed) and\r
+-- applies different steps of analysis depening on evt_type_in.\r
+-- Data is piped out directly.\r
+\r
+entity apv_pc_nc_alu is\r
+ port( CLK_IN : in std_logic; -- 100MHz master clock\r
+ RESET_IN : in std_logic;\r
+ START_IN : in std_logic; -- start signal, used for initialisation of counters\r
+ MAX_FRAMES_IN : in std_logic_vector(3 downto 0); -- number of frames requested\r
+ CURR_FRAME_IN : in std_logic_vector(3 downto 0); -- current frame number\r
+ LOC_FRM_CTR_IN : in std_logic_vector(3 downto 0); -- DEBUG\r
+ EDS_FRM_CTR_IN : in std_logic_vector(3 downto 0); -- DEBUG\r
+ BUF_GOOD_IN : in std_logic; -- process buffer\r
+ BUF_BAD_IN : in std_logic; -- write only error header\r
+ BUF_IGNORE_IN : in std_logic; -- do not write anything\r
+ ERROR_IN : in std_logic_vector(3 downto 0); -- buffer status, errors from checkers\r
+ DO_HEADER_IN : in std_logic;\r
+ DO_ERROR_IN : in std_logic;\r
+ EVT_TYPE_IN : in std_logic_vector(2 downto 0);\r
+ RAW_ADDR_IN : in std_logic_vector(6 downto 0);\r
+ RAW_DATA_IN : in std_logic_vector(37 downto 0);\r
+ PED_DATA_IN : in std_logic_vector(17 downto 0); \r
+ THR_DATA_IN : in std_logic_vector(17 downto 0);\r
+ FRAME_IN : in std_logic;\r
+ FIFO_DATA_OUT : out std_logic_vector(26 downto 0); -- [21] -> [31], [20:0] -> [20:0]\r
+ WE_OUT : out std_logic;\r
+ COUNT_OUT : out std_logic_vector(9 downto 0);\r
+ ANYDATA_OUT : out std_logic; -- this FIFO needs attention during readout\r
+ DBG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
+end;\r
+\r
+----------------------------------------------------------------------\r
+-- LIMITATION: 4 frames with 128 channels each => 512\r
+-- + debug words <= 1023!!!!\r
+----------------------------------------------------------------------\r
+\r
+architecture behavioral of apv_pc_nc_alu is\r
+\r
+ -- normal signals\r
+ signal raw_data_q : std_logic_vector(12 downto 0); -- input register\r
+ signal ped_data_q : std_logic_vector(12 downto 0); -- input register\r
+ signal ped_corr_data_q : std_logic_vector(12 downto 0); -- registered pedestal corrected value\r
+ signal ped_corr_data_qq : std_logic_vector(12 downto 0); -- registered pedestal corrected value\r
+ signal ped_corr_data_qqq : std_logic_vector(12 downto 0); -- registered pedestal corrected value\r
+ signal loc_baseline_q : std_logic_vector(13 downto 0);\r
+ signal nc_corr_data_q : std_logic_vector(13 downto 0);\r
+ signal nc_corr_data_qq : std_logic_vector(13 downto 0);\r
+ signal nc_corr_data_qqq : std_logic_vector(21 downto 0);\r
+ signal thr_data_q : std_logic_vector(13 downto 0);\r
+ signal udf_int : std_logic_vector(6 downto 0);\r
+ signal ovf_int : std_logic_vector(6 downto 0); \r
+ signal frame_int : std_logic_vector(6 downto 0);\r
+ signal off_int : std_logic_vector(6 downto 0);\r
+ signal next_data_we : std_logic;\r
+ signal data_we : std_logic;\r
+\r
+ signal thr_pass : std_logic;\r
+\r
+ -- data steering signals\r
+ signal next_ped_off : std_logic;\r
+ signal ped_off : std_logic; -- switch off pedestals\r
+ signal next_lcb_off : std_logic;\r
+ signal lcb_off : std_logic; -- switch off local baseline correction\r
+ signal next_clip_max : std_logic;\r
+ signal clip_max : std_logic; -- clip OVF values to maximum \r
+ signal next_clip_min : std_logic;\r
+ signal clip_min : std_logic; -- clip UDF values to minimum\r
+ signal next_bad_corr : std_logic_vector(6 downto 2);\r
+ signal bad_corr : std_logic_vector(6 downto 2);\r
+ signal toggle : std_logic_vector(6 downto 0);\r
+ \r
+ -- Channel counter\r
+ signal channel : std_logic_vector(6 downto 0);\r
+\r
+ signal count : std_logic_vector(9 downto 0);\r
+\r
+ signal anydata : std_logic;\r
+\r
+ -- Debug signals\r
+ signal debug : std_logic_vector(15 downto 0);\r
+ \r
+begin\r
+\r
+---------------------------------------------------------------------------------\r
+-- Data steering signals: they decide, which stages of the calculation are taken.\r
+--\r
+-- evt_type mnemonic channels actions\r
+-- 000 RAW128 128 raw data (+ 4096 + 8192)\r
+-- 001 PED128 128 pedestal data (+ 4096 - pedestal)\r
+-- 010 PED128THR <=128 pedestal data above threshold\r
+-- 011 --- --- ---\r
+-- 100 NC64PED64 128 do NC on physic channels, corr. channels pedestal corrected\r
+-- 101 NC64 64 only NC physic channels\r
+-- 110 NC64GOOD <=64 only good NC channels\r
+-- 111 NC64THR <=64 only good NC channels above threshold\r
+---------------------------------------------------------------------------------\r
+\r
+-- Switch off pedestals (RAW128 mode)\r
+next_ped_off <= '1' when ( evt_type_in = "000" ) else '0';\r
+\r
+-- Switch off local baseline (RAW128, PED128, PED128THR modes)\r
+next_lcb_off <= '1' when ( (evt_type_in = "000") or (evt_type_in = "001") or (evt_type_in = "010") ) else '0';\r
+\r
+-- Clipping function for neighbour corrected values (all modes except RAW128)\r
+next_clip_min <= '1' when ( ((evt_type_in = "001") or (evt_type_in = "010") or (evt_type_in = "011") or \r
+ (evt_type_in(2) = '1') ) and (udf_int(2) = '1') ) \r
+ else '0';\r
+next_clip_max <= '1' when ( ((evt_type_in = "001") or (evt_type_in = "010") or (evt_type_in = "011") or \r
+ (evt_type_in(2) = '1') ) and (ovf_int(2) = '1') ) \r
+ else '0';\r
+\r
+-- Neighbour correction: handle broken or switched off correction channels.\r
+-- A broken (UDF/OVF) or switched off (OFF) correction channel kills its two physical neighbour channels.\r
+next_bad_corr(2) <= '1' when ( (udf_int(0) = '1') or (udf_int(2) = '1') or\r
+ (ovf_int(0) = '1') or (ovf_int(2) = '1') or\r
+ (off_int(0) = '1') or (off_int(2) = '1') ) \r
+ else '0';\r
+\r
+next_bad_corr(3) <= '1' when ( (bad_corr(2) = '1') and (evt_type_in(2) = '1') ) else '0';\r
+\r
+next_bad_corr(4) <= '1' when ( ((bad_corr(3) = '1') and (toggle(3) = '1') and (frame_int(3) = '1')) or \r
+ (off_int(3) = '1') ) \r
+ else '0';\r
+next_bad_corr(5) <= bad_corr(4);\r
+next_bad_corr(6) <= bad_corr(5);\r
+\r
+-- We carry the OVF/UDF/OFF information all through the chain!\r
+THE_SYNC_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ ped_off <= next_ped_off;\r
+ lcb_off <= next_lcb_off;\r
+ clip_min <= next_clip_min;\r
+ clip_max <= next_clip_max;\r
+ bad_corr(6 downto 2) <= next_bad_corr(6 downto 2); -- combinatorial feed\r
+ toggle(6 downto 0) <= toggle(5 downto 0) & raw_addr_in(0);\r
+ udf_int(6 downto 0) <= udf_int(5 downto 0) & raw_data_in(12);\r
+ ovf_int(6 downto 0) <= ovf_int(5 downto 0) & raw_data_in(13);\r
+ frame_int(6 downto 0) <= frame_int(5 downto 0) & frame_in;\r
+ off_int(6 downto 0) <= off_int(5 downto 0) & ped_data_in(16);\r
+ data_we <= next_data_we;\r
+ end if;\r
+end process THE_SYNC_PROC;\r
+\r
+-- Input register, add 4096 to raw ADC values\r
+THE_RAW_INPUT_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ raw_data_q <= '1' & raw_data_in(11 downto 0); \r
+ end if;\r
+end process THE_RAW_INPUT_PROC;\r
+\r
+-- Input register, either pipe in the pedestal value, or set it to zero\r
+THE_PED_INPUT_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( (reset_in = '1') or (ped_off = '1') ) then\r
+ ped_data_q <= (others => '0');\r
+ else\r
+ ped_data_q <= '0' & ped_data_in(11 downto 0); \r
+ end if;\r
+ end if;\r
+end process THE_PED_INPUT_PROC;\r
+\r
+-- Pedestal correction, store PC value, shift it for NC\r
+THE_PED_CORR_STORE_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ ped_corr_data_q <= raw_data_q - ped_data_q;\r
+ end if;\r
+end process THE_PED_CORR_STORE_PROC;\r
+\r
+-- Delay the pedestal corrected values by two clock cycles\r
+THE_PED_CORR_DELAY_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ ped_corr_data_qqq <= ped_corr_data_qq;\r
+ ped_corr_data_qq <= ped_corr_data_q;\r
+ end if;\r
+end process THE_PED_CORR_DELAY_PROC;\r
+\r
+-- Mean value calculation for local baseline correction\r
+THE_MEAN_CALC_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( (reset_in = '1') or (lcb_off = '1') ) then\r
+ loc_baseline_q <= (others => '0'); \r
+ else\r
+ loc_baseline_q <= ('0' & ped_corr_data_q) + ('0' & ped_corr_data_qqq);\r
+ end if;\r
+ end if;\r
+end process THE_MEAN_CALC_PROC;\r
+\r
+-- Do the neighbour correction\r
+THE_NC_CORR_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( (reset_in = '1') or (clip_min = '1') ) then\r
+ nc_corr_data_q <= (others => '0'); -- channel is underflow\r
+ elsif( clip_max = '1' ) then\r
+ nc_corr_data_q <= (others => '1'); -- channel is overflow\r
+ else\r
+ nc_corr_data_q <= ('1' & ped_corr_data_qqq) - ('0' & loc_baseline_q(13 downto 1)); \r
+ end if;\r
+ end if;\r
+end process THE_NC_CORR_PROC;\r
+\r
+-- One caveat: in PED128 our artificial baseline is 4096, in NC64THR it is 8192.\r
+thr_data_q(13) <= '1'; --'1' when (evt_type_in = "111") else '0';\r
+thr_data_q(12) <= '0' when (evt_type_in = "111") else '1';\r
+\r
+-- Threshold comparison\r
+THE_THR_COMP: comp14bit\r
+port map( DATAA => nc_corr_data_q,\r
+ DATAB => thr_data_q,\r
+ CLOCK => clk_in, \r
+ CLOCKEN => '1', \r
+ ACLR => reset_in, -- BUG 10092009 \r
+ AGEB => thr_pass\r
+ );\r
+\r
+-- Delay NCD by one cycle, store THR data\r
+THE_NC_DELAY_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ nc_corr_data_qqq <= (others => '0');\r
+ nc_corr_data_qq <= (others => '0');\r
+ thr_data_q(11 downto 0) <= (others => '0');\r
+ else\r
+ if ( (do_header_in = '0') and (do_error_in = '0') ) then\r
+ nc_corr_data_qqq(21) <= '0'; -- DATA\r
+ nc_corr_data_qqq(20 downto 14) <= channel;\r
+ nc_corr_data_qqq(13 downto 0) <= nc_corr_data_qq;\r
+ elsif( (do_header_in = '1') ) then \r
+ nc_corr_data_qqq(21) <= '1'; -- HEADER\r
+ nc_corr_data_qqq(20) <= buf_bad_in;\r
+ nc_corr_data_qqq(19 downto 16) <= error_in;\r
+ nc_corr_data_qqq(15 downto 12) <= max_frames_in;\r
+ nc_corr_data_qqq(11 downto 8) <= curr_frame_in;\r
+ nc_corr_data_qqq(7 downto 0) <= raw_data_in(25 downto 18);\r
+ elsif( (do_error_in = '1') ) then \r
+ nc_corr_data_qqq(21) <= '1'; -- HEADER\r
+ nc_corr_data_qqq(20) <= raw_data_in(26); -- error\r
+ nc_corr_data_qqq(19 downto 16) <= eds_frm_ctr_in; -- EDS start frame\r
+ nc_corr_data_qqq(15 downto 12) <= loc_frm_ctr_in; -- local frame counter value\r
+ nc_corr_data_qqq(11 downto 8) <= raw_data_in(17 downto 14); -- frame counter\r
+ nc_corr_data_qqq(7 downto 0) <= raw_data_in(25 downto 18); -- row\r
+ end if;\r
+ nc_corr_data_qq <= nc_corr_data_q;\r
+ thr_data_q(11 downto 0) <= thr_data_in(11 downto 0);\r
+ end if;\r
+ end if;\r
+end process THE_NC_DELAY_PROC;\r
+\r
+-- Judgement day: will data survive?\r
+next_data_we <= '1' when ( ((buf_good_in = '1') and (evt_type_in = "000") and (frame_int(5) = '1')) or \r
+ ((buf_good_in = '1') and (evt_type_in = "001") and (frame_int(5) = '1')) or\r
+ ((buf_good_in = '1') and (evt_type_in = "010") and (frame_int(5) = '1') and (thr_pass = '1') and (bad_corr(5) = '0')) or\r
+ ((buf_good_in = '1') and (evt_type_in = "100") and (frame_int(5) = '1')) or\r
+ ((buf_good_in = '1') and (evt_type_in = "101") and (frame_int(5) = '1') and (toggle(5) = '1')) or\r
+ ((buf_good_in = '1') and (evt_type_in = "110") and (frame_int(5) = '1') and (toggle(5) = '1') and (bad_corr(5) = '0')) or\r
+ ((buf_good_in = '1') and (evt_type_in = "111") and (frame_int(5) = '1') and (toggle(5) = '1') and (bad_corr(5) = '0') and (thr_pass = '1')) or\r
+ (((buf_good_in = '1') or (buf_bad_in = '1')) and (do_header_in = '1')) or\r
+-- ((buf_bad_in = '1') and (do_error_in = '1'))\r
+ ((do_error_in = '1'))\r
+ ) \r
+ else '0';\r
+\r
+-- Channel counter for outgoing data\r
+THE_CHANNEL_CTR_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( (reset_in = '1') or (start_in = '1') ) then\r
+ channel <= (others => '0');\r
+ elsif( frame_int(5) = '1' ) then\r
+ channel <= channel + 1;\r
+ end if;\r
+ end if;\r
+end process THE_CHANNEL_CTR_PROC;\r
+\r
+-- Channel counter for outgoing data\r
+THE_DATA_CTR_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( (reset_in = '1') or (start_in = '1') ) then\r
+ count <= (others => '0');\r
+ anydata <= '0';\r
+ elsif( (data_we = '1') and (anydata = '0') ) then\r
+ anydata <= '1';\r
+ elsif( (data_we = '1') and (anydata = '1') ) then\r
+ count <= count + 1;\r
+ end if;\r
+ end if;\r
+end process THE_DATA_CTR_PROC;\r
+\r
+-- output signals (most of them are only needed for simulation!)\r
+we_out <= data_we; \r
+count_out <= count;\r
+anydata_out <= anydata;\r
+\r
+-- Real FIFO input. We use a 2kx27 FIFO, with only 22bit carrying real information.\r
+-- [26:22] are used for debugging information\r
+-- [21] will become D[31] in data (flag for data/header)\r
+-- [20:14] gives channel number\r
+-- [13:0] ADC data\r
+fifo_data_out(26) <= frame_int(6);\r
+fifo_data_out(25) <= data_we;\r
+fifo_data_out(24) <= bad_corr(6);\r
+fifo_data_out(23) <= ovf_int(6);\r
+fifo_data_out(22) <= udf_int(6);\r
+fifo_data_out(21 downto 0) <= nc_corr_data_qqq; \r
+\r
+-- Debug signals\r
+--debug(31 downto 16) <= (others => '0');\r
+debug(15) <= thr_pass;\r
+debug(14) <= '0';\r
+debug(13 downto 0) <= thr_data_q;\r
+\r
+dbg_out <= debug;\r
+\r
+end behavioral;\r
+\r
+--THE_NC_DELAY_PROC: process( clk_in )\r
+--begin\r
+-- if( rising_edge(clk_in) ) then\r
+-- if( reset_in = '1' ) then\r
+-- nc_corr_data_qqq <= (others => '0');\r
+-- nc_corr_data_qq <= (others => '0');\r
+-- thr_data_q(11 downto 0) <= (others => '0');\r
+-- else\r
+-- if( (do_header_in = '0') and (do_error_in = '0') ) then\r
+-- nc_corr_data_qqq(21) <= '0'; -- DATA\r
+-- nc_corr_data_qqq(20 downto 14) <= channel;\r
+-- nc_corr_data_qqq(13 downto 0) <= nc_corr_data_qq;\r
+-- else\r
+-- nc_corr_data_qqq(21) <= '1'; -- HEADER\r
+-- nc_corr_data_qqq(20) <= buf_bad_in;\r
+-- nc_corr_data_qqq(19 downto 16) <= error_in;\r
+-- nc_corr_data_qqq(15 downto 12) <= max_frames_in;\r
+-- nc_corr_data_qqq(11 downto 8) <= curr_frame_in;\r
+-- nc_corr_data_qqq(7 downto 0) <= raw_data_in(25 downto 18);\r
+-- end if;\r
+-- nc_corr_data_qq <= nc_corr_data_q;\r
+-- thr_data_q(11 downto 0) <= thr_data_in(11 downto 0);\r
+-- end if;\r
+-- end if;\r
+--end process THE_NC_DELAY_PROC;\r
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.std_logic_arith.all;\r
+use ieee.std_logic_unsigned.all;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+-- This entity is used to decouple the ADC/APV part (with 40MHz) from the data \r
+-- handling part (which runs with 100MHz).\r
+-- Signals:\r
+-- - all signals starting with ADC_* are synchronous to CLK_APV_IN\r
+-- - all signals starting with BUF_* are synchronous to BUF_CLK_IN\r
+-- - BUF_GOOD_OUT, BUF_BROKEN_OUT and BUF_IGNORE_OUT are to be checked if BUF_LEVEL_OUT[4:0] = 0\r
+-- - otherwise BUF_LEVEL_OUT[4:0] tells you how many frames are in the buffer\r
+-- - take care of the one clock delay between BUF_ADDR_IN and BUF_DATA_OUT.\r
+\r
+entity apv_raw_buffer is\r
+ port( CLK_APV_IN : in std_logic; -- write clock from APV handling stage\r
+ RESET_IN : in std_logic;\r
+ -- buffer level control signals\r
+ FRM_REQD_IN : in std_logic; -- one data frame has been requested from APV\r
+ MAX_TRG_NUM_IN : in std_logic_vector(3 downto 0); -- maximum number of triggers per event\r
+ -- CLK_APV_IN sync'ed signals from APV_LOCKER\r
+ ADC_ANALOG_IN : in std_logic; -- write enable for ADC data\r
+ ADC_START_IN : in std_logic; -- data frame detected, block the buffer page\r
+ ADC_LAST_IN : in std_logic; -- last channel signal\r
+ ADC_CHANNEL_IN : in std_logic_vector(6 downto 0); -- physical channel ID\r
+ ADC_RAW_IN : in std_logic_vector(17 downto 0); -- raw ADC data, UDF, OVF, ERROR\r
+ ADC_STATUS_IN : in std_logic_vector(7 downto 0); -- status information for APV\r
+ ADC_FRAME_IN : in std_logic_vector(11 downto 0); -- status information for frame\r
+ -- BUF_CLK_IN sync'ed signals from back side logic \r
+ BUF_CLK_IN : in std_logic; -- read clock\r
+ BUF_RESET_IN : in std_logic; -- 100MHz reset\r
+ BUF_START_OUT : out std_logic; -- one block starts writing (aka ADC_START)\r
+ BUF_READY_OUT : out std_logic; -- one block has been written (aka ADC_LAST)\r
+ BUF_ADDR_IN : in std_logic_vector(6 downto 0); -- address inside current buffer\r
+ BUF_DONE_IN : in std_logic; -- buffer has been read (discard buffer)\r
+ BUF_DATA_OUT : out std_logic_vector(17 downto 0); -- data from buffer\r
+ BUF_STATUS_OUT : out std_logic_vector(7 downto 0); -- generic APV status output\r
+ BUF_FRAME_OUT : out std_logic_vector(11 downto 0); -- current frame status output\r
+ BUF_GOOD_OUT : out std_logic; -- APV is active and synced -> GOOD situation\r
+ BUF_BROKEN_OUT : out std_logic; -- APV is active, but not synced -> BAD situation\r
+ BUF_IGNORE_OUT : out std_logic; -- APV is switched off -> switched off\r
+ BUF_LEVEL_OUT : out std_logic_vector(4 downto 0); -- number of stored frames inside buffer\r
+ BUF_TICKMARK_OUT : out std_logic; -- tickmark signal for timeouts in the EDS handler+\r
+ BUF_FULL_OUT : out std_logic; -- inhibit any next trigger if set!\r
+ -- Debug signals\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
+end;\r
+\r
+architecture behavioral of apv_raw_buffer is\r
+\r
+ -- Placer Directives\r
+ attribute HGROUP : string;\r
+ -- for whole architecture\r
+ attribute HGROUP of behavioral : architecture is "APV_RAW_BUF_group";\r
+\r
+ -- normal signals\r
+ signal adc_status_q : std_logic_vector(7 downto 0);\r
+ signal adc_status_qq : std_logic_vector(7 downto 0);\r
+\r
+ signal adc_start_x : std_logic;\r
+ signal adc_start : std_logic;\r
+ signal adc_last_x : std_logic;\r
+ signal adc_last : std_logic;\r
+\r
+ signal ce_wr_pointer : std_logic;\r
+ signal wr_pointer : std_logic_vector(3 downto 0);\r
+ signal ce_rd_pointer : std_logic;\r
+ signal rd_pointer : std_logic_vector(3 downto 0);\r
+ \r
+ signal buf_good_x : std_logic;\r
+ signal buf_good : std_logic;\r
+ signal buf_broken_x : std_logic;\r
+ signal buf_broken : std_logic;\r
+ signal buf_ignore_x : std_logic;\r
+ signal buf_ignore : std_logic;\r
+ \r
+ signal buf_level : std_logic_vector(4 downto 0);\r
+ signal buf_level_up_x : std_logic;\r
+ signal buf_level_down_x : std_logic;\r
+ \r
+ signal wr_data_addr : std_logic_vector(10 downto 0);\r
+ signal wr_data_d : std_logic_vector(17 downto 0);\r
+ signal wr_data_ena : std_logic;\r
+ signal rd_data_addr : std_logic_vector(10 downto 0);\r
+ signal rd_data_d : std_logic_vector(17 downto 0);\r
+ signal rd_data_ena : std_logic;\r
+\r
+ signal buf_frame : std_logic_vector(11 downto 0);\r
+ \r
+ signal adc_tickmark : std_logic;\r
+ signal buf_tickmark : std_logic;\r
+\r
+ -- Alias names for status bits\r
+ signal apv_on_x : std_logic; -- 40MHz clock domain signal\r
+ signal apv_on : std_logic;\r
+ signal apv_adcok_x : std_logic; -- 40MHz clock domain signal\r
+ signal apv_adcok : std_logic;\r
+ signal apv_locked_x : std_logic; -- 40MHz clock domain signal\r
+ signal apv_locked : std_logic;\r
+\r
+ -- from old APV_BUFHANDLER block\r
+ signal apv_free_ctr : std_logic_vector(4 downto 0);\r
+ signal apv_free_up : std_logic;\r
+ signal apv_free_down : std_logic;\r
+ signal buf_free_ctr : std_logic_vector(4 downto 0);\r
+ signal buf_free_up : std_logic;\r
+ signal buf_free_down : std_logic;\r
+ \r
+ signal sum_apv_buf : std_logic_vector(5 downto 0);\r
+ signal sum_apv : std_logic_vector(5 downto 0);\r
+ signal sum_buf : std_logic_vector(5 downto 0);\r
+ signal trg_limit : std_logic_vector(5 downto 0);\r
+ \r
+ signal debug : std_logic_vector(15 downto 0);\r
+ \r
+ signal apv_or_buf_full_x : std_logic;\r
+ signal apv_or_buf_full : std_logic;\r
+ \r
+begin\r
+\r
+-- Debugging signals\r
+debug <= (others => '0');\r
+\r
+-- Aliasing of status bits from APV_LOCKER (40MHz domain)\r
+apv_adcok_x <= not adc_status_in(7); -- '0' = good ADC, '1' = bad ADC\r
+apv_locked_x <= adc_status_in(5); -- '0' = not locked, '1' = locked\r
+apv_on_x <= not adc_status_in(1); -- '0' = "off" means "ignore", '1' = "on" means "look at me"\r
+\r
+THE_APV_ON_SYNC: state_sync\r
+port map( STATE_A_IN => apv_on_x,\r
+ CLK_B_IN => buf_clk_in,\r
+ RESET_B_IN => buf_reset_in,\r
+ STATE_B_OUT => apv_on\r
+ );\r
+\r
+THE_APV_LOCKED_SYNC: state_sync\r
+port map( STATE_A_IN => apv_locked_x,\r
+ CLK_B_IN => buf_clk_in,\r
+ RESET_B_IN => buf_reset_in,\r
+ STATE_B_OUT => apv_locked\r
+ );\r
+\r
+THE_APV_ADCOK_SYNC: state_sync\r
+port map( STATE_A_IN => apv_adcok_x,\r
+ CLK_B_IN => buf_clk_in,\r
+ RESET_B_IN => buf_reset_in,\r
+ STATE_B_OUT => apv_adcok\r
+ );\r
+\r
+-- We deliver three status signals to the data handler:\r
+-- BUF_GOOD_OUT : APV is switched on and alive, so data packets can be expected in case of triggers.\r
+-- Timeouts should be handled on this particular APV.\r
+-- BUF_BROKEN_OUT: APV is switched on and in trouble, so data packets will not come in here.\r
+-- The data handler must take care of this situation.\r
+-- Data frames already stored in the buffer may still be read out until LVL[4:0] = 0.\r
+-- BUF_IGNORE_OUT: APV is switched off, no matter if it is attached or nor, we don't accept any data frames\r
+-- here.\r
+\r
+-- CLOCK DOMAINS!\r
+buf_good_x <= '1' when ((apv_on = '1') and (apv_adcok = '1') and (apv_locked = '1')) else '0';\r
+buf_broken_x <= '1' when ((apv_on = '1') and (apv_adcok = '0' or apv_locked = '0')) else '0'; \r
+buf_ignore_x <= '1' when ( apv_on = '0' ) else '0';\r
+\r
+THE_BUF_SYNCER_PROC: process( buf_clk_in ) \r
+begin\r
+ if( rising_edge(buf_clk_in) ) then\r
+ buf_good <= buf_good_x;\r
+ buf_broken <= buf_broken_x;\r
+ buf_ignore <= buf_ignore_x;\r
+ -- not nicely done!!!\r
+ adc_status_qq <= adc_status_q;\r
+ adc_status_q <= adc_status_in; -- BUG: just a quick hack\r
+ end if;\r
+end process THE_BUF_SYNCER_PROC;\r
+\r
+-- Transfer both start and stop signals to the other clock domain\r
+adc_start_x <= (adc_start_in and buf_good_x);\r
+\r
+THE_ADC_START_SYNCER: pulse_sync\r
+port map( CLK_A_IN => clk_apv_in,\r
+ RESET_A_IN => reset_in,\r
+ PULSE_A_IN => adc_start_x,\r
+ CLK_B_IN => buf_clk_in,\r
+ RESET_B_IN => buf_reset_in,\r
+ PULSE_B_OUT => adc_start\r
+ );\r
+\r
+adc_last_x <= (adc_last_in and buf_good_x);\r
+\r
+THE_ADC_LAST_SYNCER: pulse_sync\r
+port map( CLK_A_IN => clk_apv_in,\r
+ RESET_A_IN => reset_in,\r
+ PULSE_A_IN => adc_last_x,\r
+ CLK_B_IN => buf_clk_in,\r
+ RESET_B_IN => buf_reset_in,\r
+ PULSE_B_OUT => adc_last\r
+ );\r
+\r
+-- The tickmark signal is also transfered from 40M to 100M clock domain\r
+adc_tickmark <= adc_status_in(0); -- alias\r
+THE_TICKMARK_SYNCER: pulse_sync\r
+port map( CLK_A_IN => clk_apv_in,\r
+ RESET_A_IN => reset_in,\r
+ PULSE_A_IN => adc_tickmark,\r
+ CLK_B_IN => buf_clk_in,\r
+ RESET_B_IN => buf_reset_in,\r
+ PULSE_B_OUT => buf_tickmark\r
+ );\r
+\r
+\r
+-- Control signals for the write pointer counter\r
+ce_wr_pointer <= adc_last_x;\r
+\r
+-- Write pointer counter\r
+THE_WR_POINTER: process( clk_apv_in )\r
+begin\r
+ if( rising_edge(clk_apv_in) ) then\r
+ if ( reset_in = '1' ) then\r
+ wr_pointer <= (others => '0');\r
+ elsif( ce_wr_pointer = '1' ) then\r
+ wr_pointer <= wr_pointer + 1;\r
+ end if;\r
+ end if;\r
+end process THE_WR_POINTER;\r
+\r
+-- Control signals for the read pointer counter\r
+ce_rd_pointer <= buf_done_in and apv_on;\r
+\r
+-- Read pointer counter\r
+THE_RD_POINTER: process( buf_clk_in )\r
+begin\r
+ if( rising_edge(buf_clk_in) ) then\r
+ if ( buf_reset_in = '1' ) then\r
+ rd_pointer <= (others => '0');\r
+ elsif( ce_rd_pointer = '1' ) then\r
+ rd_pointer <= rd_pointer + 1;\r
+ end if;\r
+ end if;\r
+end process THE_RD_POINTER;\r
+\r
+-- We need a level counter for the EDS handler, anyhow\r
+buf_level_up_x <= adc_last; \r
+buf_level_down_x <= (buf_done_in and buf_good);\r
+\r
+THE_BUF_LEVEL_COUNTER_PROC: process( buf_clk_in )\r
+begin\r
+ if( rising_edge(buf_clk_in) ) then\r
+ if ( buf_reset_in = '1' ) then\r
+ buf_level <= (others => '0');\r
+ elsif( (buf_level_up_x = '1') and (buf_level_down_x = '0') ) then\r
+ buf_level <= buf_level + 1;\r
+ elsif( (buf_level_up_x = '0') and (buf_level_down_x = '1') ) then\r
+ buf_level <= buf_level - 1;\r
+ end if;\r
+ end if;\r
+end process THE_BUF_LEVEL_COUNTER_PROC;\r
+\r
+-- Control signals for the data EBRs\r
+wr_data_ena <= adc_analog_in;\r
+rd_data_ena <= '1';\r
+wr_data_addr <= wr_pointer & adc_channel_in;\r
+rd_data_addr <= rd_pointer & buf_addr_in;\r
+wr_data_d <= adc_raw_in;\r
+\r
+-- We have two EBRs to implement a 2kx18 ring buffer\r
+THE_INPUT_BRAM: input_bram\r
+port map( WRADDRESS => wr_data_addr,\r
+ RDADDRESS => rd_data_addr,\r
+ DATA => wr_data_d, \r
+ WE => wr_data_ena,\r
+ RDCLOCK => buf_clk_in,\r
+ RDCLOCKEN => rd_data_ena,\r
+ RESET => reset_in,\r
+ WRCLOCK => clk_apv_in,\r
+ WRCLOCKEN => '1',\r
+ Q => rd_data_d\r
+ );\r
+\r
+-- We use a LUT based DPRAM for the 16x12b status memory\r
+THE_FRAME_STATUS_MEM: frame_status_mem\r
+port map( WRADDRESS => wr_pointer, \r
+ DATA => adc_frame_in,\r
+ WRCLOCK => clk_apv_in,\r
+ WE => ce_wr_pointer, -- we store the frame status with the last ADC word\r
+ WRCLOCKEN => '1',\r
+ RDADDRESS => rd_pointer,\r
+ RDCLOCK => buf_clk_in,\r
+ RDCLOCKEN => '1',\r
+ RESET => reset_in,\r
+ Q => buf_frame\r
+ );\r
+\r
+------------------------------------------------------------------------------------------\r
+-- Buffer fill levels, busy generation\r
+------------------------------------------------------------------------------------------\r
+\r
+-- We need to keep track of the APV analog fifo fill level.\r
+-- Two signals are used: \r
+-- - an early "FRAME_REQD" to decrement to number of free entries,\r
+-- - a late "FRAME_RCVD" to notify that a requested frame has been transfered \r
+-- from APV to the raw buffer.\r
+\r
+apv_free_down <= frm_reqd_in;\r
+apv_free_up <= adc_last; \r
+\r
+THE_APV_FREE_COUNTER_PROC: process( buf_clk_in )\r
+begin\r
+ if( rising_edge(buf_clk_in) ) then\r
+ if ( buf_reset_in = '1' ) then\r
+ apv_free_ctr <= "10000";\r
+ elsif( apv_free_down = '1' and apv_free_up = '0' ) then\r
+ apv_free_ctr <= apv_free_ctr - 1; \r
+ elsif( apv_free_down = '0' and apv_free_up = '1' ) then\r
+ apv_free_ctr <= apv_free_ctr + 1;\r
+ end if;\r
+ end if;\r
+end process THE_APV_FREE_COUNTER_PROC;\r
+\r
+-- The raw data buffer is also to be watched carefully. \r
+-- An early signal reserved on raw buffer page, while a late one releases one\r
+-- page to the buffer pool again.\r
+\r
+buf_free_down <= adc_start;\r
+buf_free_up <= buf_done_in;\r
+\r
+THE_BUF_FREE_COUNTER_PROC: process( buf_clk_in )\r
+begin\r
+ if( rising_edge(buf_clk_in) ) then\r
+ if ( buf_reset_in = '1' ) then\r
+ buf_free_ctr <= "10000";\r
+ elsif( buf_free_down = '1' and buf_free_up = '0' ) then\r
+ buf_free_ctr <= buf_free_ctr - 1; \r
+ elsif( buf_free_down = '0' and buf_free_up = '1' ) then\r
+ buf_free_ctr <= buf_free_ctr + 1;\r
+ end if;\r
+ end if;\r
+end process THE_BUF_FREE_COUNTER_PROC;\r
+\r
+-- We need to sum up and check if there is always enough space in the buffers\r
+-- (both APV and RAW_BUF) to store one full sized event, as given by MAX_TRG_NUM_IN.\r
+\r
+sum_apv <= '0' & apv_free_ctr;\r
+sum_buf <= '0' & buf_free_ctr;\r
+\r
+-- Balance the frames requested from APV and already present in raw buffers\r
+THE_APV_BUF_ADDER: adder_6bit\r
+port map( DATAA => sum_apv,\r
+ DATAB => sum_buf,\r
+ CLOCK => buf_clk_in,\r
+ RESET => buf_reset_in, \r
+ CLOCKEN => '1', \r
+ RESULT => sum_apv_buf\r
+ );\r
+\r
+-- We have a minimum number of buffer pages to keep:\r
+-- this construct makes 16 + (max_trg_num)\r
+trg_limit <= "01" & max_trg_num_in;\r
+\r
+apv_or_buf_full_x <= '1' when (sum_apv_buf < trg_limit) else '0';\r
+\r
+THE_SYNC_PROC: process( buf_clk_in )\r
+begin\r
+ if( rising_edge(buf_clk_in) ) then\r
+ apv_or_buf_full <= apv_or_buf_full_x;\r
+ end if;\r
+end process THE_SYNC_PROC;\r
+------------------------------------------------------------------------------------------\r
+------------------------------------------------------------------------------------------\r
+\r
+\r
+-- Output signals\r
+buf_data_out <= rd_data_d;\r
+buf_start_out <= adc_start;\r
+buf_ready_out <= adc_last;\r
+buf_status_out <= adc_status_qq;\r
+buf_frame_out <= buf_frame;\r
+\r
+buf_good_out <= buf_good;\r
+buf_broken_out <= buf_broken;\r
+buf_ignore_out <= buf_ignore;\r
+buf_level_out <= buf_level;\r
+buf_full_out <= apv_or_buf_full;\r
+\r
+buf_tickmark_out <= buf_tickmark;\r
+\r
+-- Debug signals\r
+debug_out <= debug;\r
+\r
+end behavioral;\r
+\r
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.std_logic_arith.all;\r
+use ieee.std_logic_unsigned.all;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+entity apv_sync_handler is\r
+ port( CLK_APV_IN : in std_logic; -- 40MHz phase shifted clock\r
+ RESET_APV_IN : in std_logic; -- synced reset signal (40MHz APV)\r
+ CLK_IN : in std_logic; -- 100MHz master clock\r
+ RESET_IN : in std_logic; \r
+ APV_TRGSTART_IN : in std_logic; -- start signal for one sequence\r
+ APV_TRGSEL_IN : in std_logic; -- select signal for one sequence\r
+ APV_TRGDONE_OUT : out std_logic; -- APV trigger statemachine finished (100MHz)\r
+ APV_TRG_OUT : out std_logic; -- TRG line signal (40MHz APV)\r
+ APV_SYNC_OUT : out std_logic; -- signal for statemachines (40MHz APV)\r
+ BSM_OUT : out std_logic_vector(3 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
+end;\r
+\r
+architecture behavioral of apv_sync_handler is\r
+\r
+ -- state machine signals\r
+ type STATES is (SLEEP,START,T2,T1,T0,DLY0,DLY1,DLY2,DLY3,DONE);\r
+ signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+ -- normal signals\r
+ signal apv_trgdone : std_logic;\r
+ signal apv_trgstart : std_logic;\r
+ signal comb_apv_trgstart : std_logic;\r
+ -- state machine generated signals\r
+ signal next_apv_done : std_logic;\r
+ signal apv_done : std_logic;\r
+ signal next_apv_trg : std_logic;\r
+ signal apv_trg : std_logic;\r
+ signal next_apv_sync : std_logic;\r
+ signal apv_sync : std_logic;\r
+\r
+\r
+begin\r
+\r
+-- APV_TRGSTART_IN crosses a clock domain (100M -> 40M).\r
+comb_apv_trgstart <= apv_trgstart_in and apv_trgsel_in; \r
+\r
+THE_APVTRGSTART_SYNC: pulse_sync\r
+port map( CLK_A_IN => clk_in,\r
+ RESET_A_IN => reset_in,\r
+ PULSE_A_IN => comb_apv_trgstart,\r
+ CLK_B_IN => clk_apv_in,\r
+ RESET_B_IN => reset_apv_in,\r
+ PULSE_B_OUT => apv_trgstart\r
+ );\r
+\r
+-- A statemachine handles all actions for creating the trigger sequence\r
+-- state registers\r
+STATE_MEM: process( clk_apv_in ) \r
+begin\r
+ if( rising_edge(clk_apv_in) ) then\r
+ if( reset_apv_in = '1' ) then\r
+ CURRENT_STATE <= SLEEP;\r
+ apv_done <= '0';\r
+ apv_trg <= '0';\r
+ apv_sync <= '0';\r
+ else\r
+ CURRENT_STATE <= NEXT_STATE;\r
+ apv_done <= next_apv_done;\r
+ apv_trg <= next_apv_trg;\r
+ apv_sync <= next_apv_sync;\r
+ end if;\r
+ end if;\r
+end process STATE_MEM;\r
+\r
+-- state transitions\r
+STATE_TRANSFORM: process( CURRENT_STATE, apv_trgstart )\r
+begin\r
+ NEXT_STATE <= SLEEP; -- avoid latches\r
+ next_apv_done <= '0';\r
+ next_apv_trg <= '0';\r
+ next_apv_sync <= '0';\r
+ case CURRENT_STATE is\r
+ when SLEEP => if( apv_trgstart = '1' ) then\r
+ NEXT_STATE <= START;\r
+ else\r
+ NEXT_STATE <= SLEEP;\r
+ end if;\r
+ when START => NEXT_STATE <= T2;\r
+ next_apv_trg <= '1';\r
+ when T2 => NEXT_STATE <= T1;\r
+ when T1 => NEXT_STATE <= T0;\r
+ next_apv_trg <= '1';\r
+ when T0 => NEXT_STATE <= DLY0;\r
+ next_apv_sync <= '1';\r
+ when DLY0 => NEXT_STATE <= DLY1;\r
+ next_apv_sync <= '1';\r
+ when DLY1 => NEXT_STATE <= DLY2;\r
+ next_apv_sync <= '1';\r
+ when DLY2 => NEXT_STATE <= DLY3;\r
+ next_apv_sync <= '1';\r
+ when DLY3 => NEXT_STATE <= DONE;\r
+ next_apv_done <= '1';\r
+ next_apv_sync <= '1';\r
+ when DONE => NEXT_STATE <= SLEEP;\r
+ when others => NEXT_STATE <= SLEEP;\r
+ end case;\r
+end process STATE_TRANSFORM;\r
+\r
+-- state decoding\r
+STATE_DECODE: process( CURRENT_STATE )\r
+begin\r
+ case CURRENT_STATE is\r
+ when SLEEP => bsm_out <= x"0";\r
+ when START => bsm_out <= x"1";\r
+ when T2 => bsm_out <= x"2";\r
+ when T1 => bsm_out <= x"3";\r
+ when T0 => bsm_out <= x"4";\r
+ when DLY0 => bsm_out <= x"5";\r
+ when DLY1 => bsm_out <= x"6";\r
+ when DLY2 => bsm_out <= x"7";\r
+ when DLY3 => bsm_out <= x"8";\r
+ when DONE => bsm_out <= x"9";\r
+ when others => bsm_out <= x"f";\r
+ end case;\r
+end process STATE_DECODE;\r
+\r
+-- APV_TRGDONE_OUT crosses a clock domain (40M -> 100M).\r
+THE_APVTRGDONE_SYNC: pulse_sync\r
+port map( CLK_A_IN => clk_apv_in,\r
+ RESET_A_IN => reset_apv_in,\r
+ PULSE_A_IN => apv_done,\r
+ CLK_B_IN => clk_in,\r
+ RESET_B_IN => reset_in,\r
+ PULSE_B_OUT => apv_trgdone\r
+ );\r
+\r
+-- output signals\r
+apv_trgdone_out <= apv_trgdone;\r
+apv_trg_out <= apv_trg;\r
+apv_sync_out <= apv_sync;\r
+\r
+debug_out(15 downto 0) <= (others => '0'); \r
+\r
+end behavioral;\r
+\r
+\r
+\r
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.std_logic_arith.all;\r
+use ieee.std_logic_unsigned.all;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+entity apv_trg_handler is\r
+ port( CLK_APV_IN : in std_logic; -- 40MHz phase shifted clock\r
+ RESET_APV_IN : in std_logic; -- synced reset signal (40MHz APV)\r
+ CLK_IN : in std_logic; -- 100MHz master clock\r
+ RESET_IN : in std_logic; -- synced reset signal (100MHz master clock)\r
+ APV_TRGSTART_IN : in std_logic; -- start signal for one sequence\r
+ APV_TRGSEL_IN : in std_logic; -- select signal for one sequence\r
+ APV_TRG_TODO_IN : in std_logic_vector(3 downto 0); -- number of APV triggers\r
+ APV_TRG_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between APV triggers\r
+ APV_TRGDONE_OUT : out std_logic; -- APV trigger statemachine finished\r
+ APV_TRG_OUT : out std_logic;\r
+ APV_TRGSENT_OUT : out std_logic;\r
+ BSM_OUT : out std_logic_vector(3 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
+end;\r
+\r
+architecture behavioral of apv_trg_handler is\r
+\r
+ -- state machine signals\r
+ type STATES is (SLEEP,START,T2,T1,T0,DEL,DONE);\r
+ signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+ -- normal signals\r
+ signal apv_trgstart : std_logic;\r
+ signal next_apv_trgstart : std_logic;\r
+ signal todo_ctr : std_logic_vector(3 downto 0);\r
+ signal comb_todo_done : std_logic;\r
+ signal delay_ctr : std_logic_vector(3 downto 0);\r
+ signal comb_delay_done : std_logic;\r
+ signal apv_trgsent : std_logic;\r
+ signal apv_trgdone : std_logic;\r
+\r
+ -- State machine generates signals\r
+ signal next_todo_ctr_ce : std_logic;\r
+ signal todo_ctr_ce : std_logic;\r
+ signal next_delay_ctr_ce : std_logic;\r
+ signal delay_ctr_ce : std_logic;\r
+ signal next_delay_ctr_ld : std_logic;\r
+ signal delay_ctr_ld : std_logic;\r
+ signal next_apv_done : std_logic;\r
+ signal apv_done : std_logic;\r
+ signal next_apv_trgcnt : std_logic;\r
+ signal apv_trgcnt : std_logic;\r
+ signal next_apv_trg : std_logic;\r
+ signal apv_trg : std_logic;\r
+\r
+begin\r
+\r
+-- APV_TRGSTART_IN crosses a clock domain (100M -> 40M).\r
+next_apv_trgstart <= apv_trgstart_in and apv_trgsel_in; \r
+\r
+THE_APVTRGSTART_SYNC: pulse_sync\r
+port map( CLK_A_IN => clk_in,\r
+ RESET_A_IN => reset_in,\r
+ PULSE_A_IN => next_apv_trgstart,\r
+ CLK_B_IN => clk_apv_in,\r
+ RESET_B_IN => reset_apv_in,\r
+ PULSE_B_OUT => apv_trgstart\r
+ );\r
+\r
+-- A statemachine handles all actions for creating the trigger sequence (40MHz domain)\r
+-- state registers\r
+STATE_MEM: process( clk_apv_in ) \r
+begin\r
+ if( rising_edge(clk_apv_in) ) then\r
+ if( reset_apv_in = '1' ) then\r
+ CURRENT_STATE <= SLEEP;\r
+ todo_ctr_ce <= '0';\r
+ delay_ctr_ce <= '0';\r
+ delay_ctr_ld <= '0';\r
+ apv_done <= '0';\r
+ apv_trgcnt <= '0';\r
+ apv_trg <= '0';\r
+ else\r
+ CURRENT_STATE <= NEXT_STATE;\r
+ todo_ctr_ce <= next_todo_ctr_ce;\r
+ delay_ctr_ce <= next_delay_ctr_ce;\r
+ delay_ctr_ld <= next_delay_ctr_ld;\r
+ apv_done <= next_apv_done;\r
+ apv_trgcnt <= next_apv_trgcnt;\r
+ apv_trg <= next_apv_trg;\r
+ end if;\r
+ end if;\r
+end process STATE_MEM;\r
+\r
+-- state transitions\r
+STATE_TRANSFORM: process( CURRENT_STATE, apv_trgstart, comb_todo_done, comb_delay_done )\r
+begin\r
+ NEXT_STATE <= SLEEP; -- avoid latches\r
+ next_todo_ctr_ce <= '0';\r
+ next_delay_ctr_ce <= '0';\r
+ next_delay_ctr_ld <= '0';\r
+ next_apv_done <= '0';\r
+ next_apv_trg <= '0';\r
+ next_apv_trgcnt <= '0';\r
+ case CURRENT_STATE is\r
+ when SLEEP => if( apv_trgstart = '1' ) then\r
+ NEXT_STATE <= START;\r
+ else\r
+ NEXT_STATE <= SLEEP;\r
+ end if;\r
+ when START => if( comb_todo_done = '1' ) then\r
+ NEXT_STATE <= DONE;\r
+ next_apv_done <= '1';\r
+ else\r
+ NEXT_STATE <= T2;\r
+ next_delay_ctr_ld <= '1';\r
+ next_apv_trg <= '1';\r
+ end if;\r
+ when T2 => NEXT_STATE <= T1;\r
+ next_todo_ctr_ce <= '1';\r
+ next_apv_trgcnt <= '1';\r
+ when T1 => NEXT_STATE <= T0;\r
+ next_delay_ctr_ce <= '1';\r
+ when T0 => if ( (comb_todo_done = '1') ) then\r
+ NEXT_STATE <= DONE;\r
+ next_apv_done <= '1';\r
+ elsif( (comb_todo_done = '0') and (comb_delay_done = '0') ) then\r
+ NEXT_STATE <= DEL;\r
+ next_delay_ctr_ce <= '1';\r
+ elsif( (comb_todo_done = '0') and (comb_delay_done = '1') ) then\r
+ NEXT_STATE <= T2;\r
+ next_delay_ctr_ld <= '1';\r
+ next_apv_trg <= '1';\r
+ end if;\r
+ when DEL => if( comb_delay_done = '1' ) then\r
+ NEXT_STATE <= T2;\r
+ next_delay_ctr_ld <= '1';\r
+ next_apv_trg <= '1';\r
+ else\r
+ NEXT_STATE <= DEL;\r
+ next_delay_ctr_ce <= '1';\r
+ end if;\r
+ when DONE => NEXT_STATE <= SLEEP;\r
+ when others => NEXT_STATE <= SLEEP;\r
+ end case;\r
+end process STATE_TRANSFORM;\r
+\r
+-- state decoding\r
+STATE_DECODE: process( CURRENT_STATE )\r
+begin\r
+ case CURRENT_STATE is\r
+ when SLEEP => bsm_out <= x"0";\r
+ when START => bsm_out <= x"1";\r
+ when T2 => bsm_out <= x"2";\r
+ when T1 => bsm_out <= x"3";\r
+ when T0 => bsm_out <= x"4";\r
+ when DEL => bsm_out <= x"5";\r
+ when DONE => bsm_out <= x"6";\r
+ when others => bsm_out <= x"f";\r
+ end case;\r
+end process STATE_DECODE;\r
+\r
+-- ToDo counter\r
+THE_TODO_CTR_PROC: process( clk_apv_in )\r
+begin\r
+ if( rising_edge(clk_apv_in) ) then\r
+ if ( reset_apv_in = '1' ) then\r
+ todo_ctr <= (others => '0');\r
+ elsif( apv_trgstart = '1' ) then\r
+ todo_ctr <= apv_trg_todo_in;\r
+ elsif( todo_ctr_ce = '1' ) then\r
+ todo_ctr <= todo_ctr - 1;\r
+ end if;\r
+ end if;\r
+end process THE_TODO_CTR_PROC;\r
+comb_todo_done <= '1' when (todo_ctr = x"0") else '0';\r
+\r
+-- Delay counter\r
+THE_DELAY_CTR_PROC: process( clk_apv_in )\r
+begin\r
+ if( rising_edge(clk_apv_in) ) then\r
+ if ( reset_apv_in = '1' ) then\r
+ delay_ctr <= (others => '0');\r
+ elsif( delay_ctr_ld = '1' ) then\r
+ delay_ctr <= apv_trg_delay_in;\r
+ elsif( delay_ctr_ce = '1' ) then\r
+ delay_ctr <= delay_ctr - 1;\r
+ end if;\r
+ end if;\r
+end process THE_DELAY_CTR_PROC;\r
+comb_delay_done <= '1' when (delay_ctr = x"0") else '0';\r
+\r
+-- APV_TRGSENT_OUT crosses a clock domain (40M -> 100M).\r
+THE_APVTRGSENT_SYNC: pulse_sync\r
+port map( CLK_A_IN => clk_apv_in,\r
+ RESET_A_IN => reset_apv_in, \r
+ PULSE_A_IN => apv_trgcnt,\r
+ CLK_B_IN => clk_in,\r
+ RESET_B_IN => reset_in,\r
+ PULSE_B_OUT => apv_trgsent\r
+ );\r
+\r
+-- APV_TRGDONE_OUT crosses a clock domain (40M -> 100M).\r
+THE_APVTRGDONE_SYNC: pulse_sync\r
+port map( CLK_A_IN => clk_apv_in,\r
+ RESET_A_IN => reset_apv_in,\r
+ PULSE_A_IN => apv_done,\r
+ CLK_B_IN => clk_in,\r
+ RESET_B_IN => reset_in,\r
+ PULSE_B_OUT => apv_trgdone\r
+ );\r
+\r
+-- output signals\r
+apv_trgdone_out <= apv_trgdone;\r
+apv_trg_out <= apv_trg;\r
+apv_trgsent_out <= apv_trgsent;\r
+\r
+debug_out(15 downto 12) <= todo_ctr; \r
+debug_out(11 downto 8) <= delay_ctr; \r
+debug_out(7) <= delay_ctr_ld;\r
+debug_out(6) <= '0';\r
+debug_out(5) <= comb_delay_done;\r
+debug_out(4) <= delay_ctr_ce;\r
+debug_out(3) <= apv_trgstart;\r
+debug_out(2) <= '0';\r
+debug_out(1) <= comb_todo_done;\r
+debug_out(0) <= todo_ctr_ce;\r
+\r
+end behavioral;\r
+\r
+\r
+\r
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.std_logic_arith.all;\r
+use ieee.std_logic_unsigned.all;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+entity apv_trgctrl is\r
+ port( CLK_IN : in std_logic; -- 100MHz master clock\r
+ RESET_IN : in std_logic; -- 100MHz clock domain reset\r
+ CLK_APV_IN : in std_logic; -- 40MHz phase shifted clock\r
+ -- Triggers\r
+ SYNC_TRG_IN : in std_logic; -- 100MHz signal to SYNC APVs\r
+ TIME_TRG_IN : in std_logic_vector(3 downto 0); -- timing trigger inputs\r
+ TRB_TRG_IN : in std_logic_vector(3 downto 0); -- TRB trigger inputs\r
+ STILL_BUSY_IN : in std_logic; -- set to '1' if any buffer is in danger of overflow\r
+ TRG_FOUND_OUT : out std_logic; \r
+ -- slow control settings\r
+ TRG_MAX_OUT : out std_logic_vector(3 downto 0); -- maximum number of triggers/event\r
+ TRG_3_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 3\r
+ TRG_3_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers\r
+ TRG_2_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 2\r
+ TRG_2_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers\r
+ TRG_1_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 1\r
+ TRG_1_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers\r
+ TRG_0_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 0\r
+ TRG_0_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers\r
+ TRG_SETUP_IN : in std_logic_vector(7 downto 0); -- setup of external triggers\r
+ -- TRB LVL1 signals\r
+ TRB_TTAG_IN : in std_logic_vector(15 downto 0); -- TRB LVL1 trigger tag\r
+ TRB_TRND_IN : in std_logic_vector(7 downto 0); -- TRB LVL1 random tag\r
+ TRB_TTYPE_IN : in std_logic_vector(3 downto 0); -- TRB LVL1 trigger type\r
+ TRB_TRGRCVD_IN : in std_logic; -- TRB LVL1 trigger received\r
+ TRB_MISSING_OUT : out std_logic; -- TRB LVL1 trigger arrived, but has no corresponding timing trigger\r
+ TRB_RELEASE_OUT : out std_logic; -- release TRB LVL1 channel\r
+ TRB_RST_COUNTER_IN : in std_logic; -- reset timing trigger counter\r
+ TRB_COUNTER_OUT : out std_logic_vector(15 downto 0); -- timing trigger counter\r
+ -- EDS signals\r
+ EDS_DATA_OUT : out std_logic_vector(39 downto 0); -- EventDataSheet (tm) data word\r
+ EDS_AVAIL_OUT : out std_logic; -- EDS valid, APV trigger done\r
+ EDS_DONE_IN : in std_logic; -- release current EDS buffer\r
+ EDS_FULL_OUT : out std_logic; -- EDS buffer is full\r
+ EDS_LEVEL_OUT : out std_logic_vector(4 downto 0);\r
+ FRM_REQD_OUT : out std_logic; -- frame requested, (level counter decrement)\r
+ -- APV signals \r
+ APV_TRG_OUT : out std_logic;\r
+ APV_SYNC_OUT : out std_logic;\r
+ DEBUG_OUT : out std_logic_vector(63 downto 0)\r
+ );\r
+end;\r
+\r
+architecture behavioral of apv_trgctrl is\r
+\r
+ -- Placer Directives\r
+ attribute HGROUP : string;\r
+ -- for whole architecture\r
+ attribute HGROUP of behavioral : architecture is "APV_TRG_CTRL_group";\r
+\r
+ -- normal signals\r
+ signal apv_trgsel : std_logic_vector(3 downto 0);\r
+ signal apv_trgstart : std_logic;\r
+ signal apv_trgdone : std_logic_vector(3 downto 0);\r
+ signal next_apv_trgdone_all : std_logic;\r
+ signal apv_trgdone_all : std_logic;\r
+ signal apv_trg : std_logic_vector(3 downto 0);\r
+ signal next_apv_trg_all : std_logic;\r
+ signal apv_trg_all : std_logic;\r
+ signal apv_clk_rst : std_logic; -- 40MHz sync'ed reset signal\r
+\r
+ signal sc_trg_stretch : std_logic_vector(3 downto 0);\r
+ signal maximum_trg : std_logic_vector(3 downto 0);\r
+\r
+ -- EDS fill signals\r
+ signal atc_eds_data : std_logic_vector(39 downto 0);\r
+ signal atc_eds_start : std_logic;\r
+ signal atc_eds_we : std_logic;\r
+ signal eds_data : std_logic_vector(39 downto 0);\r
+ signal eds_full : std_logic;\r
+ signal eds_avail : std_logic;\r
+ signal eds_level : std_logic_vector(4 downto 0);\r
+ signal trb_release : std_logic;\r
+ signal trb_missing : std_logic;\r
+ signal trg_found : std_logic;\r
+\r
+ signal test_eds_data : std_logic_vector(39 downto 0);\r
+\r
+ -- APV signals \r
+ signal apv_trgsent : std_logic_vector(3 downto 0);\r
+ signal next_apv_trgsent_all : std_logic;\r
+ signal apv_trgsent_all : std_logic;\r
+ signal apv_sync : std_logic;\r
+ signal apv_sync_signal : std_logic;\r
+ \r
+ signal trb_counter : std_logic_vector(15 downto 0);\r
+ signal busy_release : std_logic;\r
+\r
+ signal debug : std_logic_vector(63 downto 0);\r
+ signal bsm : std_logic_vector(7 downto 0);\r
+ \r
+begin\r
+\r
+---------------------------------------------------------------------------\r
+-- Debug\r
+---------------------------------------------------------------------------\r
+debug(63 downto 40) <= (others => '0');\r
+debug(39 downto 0) <= test_eds_data;\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- RESET signal clock domain crossing (100MHz sysclk -> 40MHz APV clock)\r
+---------------------------------------------------------------------------\r
+THE_RESET_SYNC: state_sync\r
+port map( STATE_A_IN => reset_in,\r
+ CLK_B_IN => clk_apv_in,\r
+ RESET_B_IN => '0',\r
+ STATE_B_OUT => apv_clk_rst\r
+ );\r
+ \r
+---------------------------------------------------------------------------\r
+-- TRB trigger (one clock pulse) stretchers\r
+---------------------------------------------------------------------------\r
+SC_TRG0_STRECH: pulse_stretch\r
+port map( CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ START_IN => trb_trg_in(0),\r
+ PULSE_OUT => sc_trg_stretch(0),\r
+ DEBUG_OUT => open\r
+ );\r
+SC_TRG1_STRECH: pulse_stretch\r
+port map( CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ START_IN => trb_trg_in(1),\r
+ PULSE_OUT => sc_trg_stretch(1),\r
+ DEBUG_OUT => open\r
+ );\r
+SC_TRG2_STRECH: pulse_stretch\r
+port map( CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ START_IN => trb_trg_in(2),\r
+ PULSE_OUT => sc_trg_stretch(2),\r
+ DEBUG_OUT => open\r
+ );\r
+SC_TRG3_STRECH: pulse_stretch\r
+port map( CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ START_IN => trb_trg_in(3),\r
+ PULSE_OUT => sc_trg_stretch(3),\r
+ DEBUG_OUT => open\r
+ );\r
+\r
+---------------------------------------------------------------------------\r
+-- Busy handling\r
+---------------------------------------------------------------------------\r
+THE_SYNC_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ busy_release <= not still_busy_in and not eds_full;\r
+ end if;\r
+end process THE_SYNC_PROC;\r
+\r
+---------------------------------------------------------------------------\r
+-- Triggers can either be sourced from hardware inputs (four LVDS signals), or by slow control accesses.\r
+-- Each trigger input has its own settings (# triggers, delay inbetween), and can control an own state machine\r
+-- for generation of APV TRG pulse sequences (like 1-0-0, or 1-0-1, etc.)\r
+---------------------------------------------------------------------------\r
+THE_REAL_TRG_HANDLER: real_trg_handler\r
+port map( CLK_IN => clk_in,\r
+ RESET_IN => reset_in, \r
+ TIME_TRG_IN => time_trg_in,\r
+ TRB_TRG_IN => sc_trg_stretch,\r
+ APV_TRGDONE_IN => apv_trgdone_all,\r
+ TRG_3_TODO_IN => trg_3_todo_in,\r
+ TRG_2_TODO_IN => trg_2_todo_in,\r
+ TRG_1_TODO_IN => trg_1_todo_in,\r
+ TRG_0_TODO_IN => trg_0_todo_in,\r
+ TRG_SETUP_IN => trg_setup_in,\r
+ TRG_FOUND_OUT => trg_found,\r
+ TRB_TTAG_IN => trb_ttag_in,\r
+ TRB_TRND_IN => trb_trnd_in,\r
+ TRB_TTYPE_IN => trb_ttype_in,\r
+ TRB_TRGRCVD_IN => trb_trgrcvd_in,\r
+ TRB_MISSING_OUT => trb_missing,\r
+ BUSY_RELEASE_IN => busy_release,\r
+ RST_LVL1_COUNTER_IN => trb_rst_counter_in,\r
+ LVL1_COUNTER_OUT => trb_counter,\r
+ APV_TRGSEL_OUT => apv_trgsel,\r
+ APV_TRGSTART_OUT => apv_trgstart,\r
+ EDS_DATA_OUT => atc_eds_data,\r
+ EDS_START_OUT => atc_eds_start, -- just for debugging\r
+ EDS_WE_OUT => atc_eds_we,\r
+ EDS_READY_OUT => trb_release,\r
+ DBG_FRMCTR_OUT => open,\r
+ BSM_OUT => bsm, --open,\r
+ DEBUG_OUT => open --debug\r
+ );\r
+\r
+-- automatically determine the maximum amount of APV frames per trigger\r
+-- mind the delay in this block!\r
+THE_MAX_TRG: max_data\r
+port map( CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ TODO_3_IN => trg_3_todo_in,\r
+ TODO_2_IN => trg_2_todo_in,\r
+ TODO_1_IN => trg_1_todo_in,\r
+ TODO_0_IN => trg_0_todo_in,\r
+ TODO_MAX_OUT => maximum_trg,\r
+ DEBUG_OUT => open\r
+ );\r
+\r
+-- Only for storing last EDS for debugging!\r
+THE_TEST_EDS_DATA_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( atc_eds_we = '1' ) then\r
+ test_eds_data <= atc_eds_data;\r
+ end if;\r
+ end if;\r
+end process THE_TEST_EDS_DATA_PROC;\r
+\r
+---------------------------------------------------------------------------\r
+-- EDS buffer with fill level information\r
+---------------------------------------------------------------------------\r
+THE_EDS_BUF: eds_buf\r
+port map( CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ EDS_DATA_IN => atc_eds_data, -- data from trigger handler\r
+ EDS_WE_IN => atc_eds_we, -- write enable from trigger handler\r
+ EDS_DONE_IN => eds_done_in, -- release current EDS page\r
+ EDS_DATA_OUT => eds_data, -- current EDS data out\r
+ EDS_AVAILABLE_OUT => eds_avail, -- current EDS is valid\r
+ BUF_FULL_OUT => eds_full, -- EDS buffer is full\r
+ BUF_LEVEL_OUT => eds_level, -- for debugging\r
+ DEBUG_OUT => open\r
+ );\r
+\r
+---------------------------------------------------------------------------\r
+-- Trigger input 3: normal trigger\r
+---------------------------------------------------------------------------\r
+THE_APV_TRG_HANDLER_3: apv_trg_handler\r
+port map( CLK_APV_IN => clk_apv_in,\r
+ RESET_APV_IN => apv_clk_rst,\r
+ CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ APV_TRGSTART_IN => apv_trgstart,\r
+ APV_TRGSEL_IN => apv_trgsel(3),\r
+ APV_TRG_TODO_IN => trg_3_todo_in,\r
+ APV_TRG_DELAY_IN => trg_3_delay_in,\r
+ APV_TRGDONE_OUT => apv_trgdone(3),\r
+ APV_TRG_OUT => apv_trg(3),\r
+ APV_TRGSENT_OUT => apv_trgsent(3),\r
+ BSM_OUT => open,\r
+ DEBUG_OUT => open\r
+ );\r
+\r
+---------------------------------------------------------------------------\r
+-- Trigger input 2: normal trigger\r
+---------------------------------------------------------------------------\r
+THE_APV_TRG_HANDLER_2: apv_trg_handler\r
+port map( CLK_APV_IN => clk_apv_in,\r
+ RESET_APV_IN => apv_clk_rst,\r
+ CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ APV_TRGSTART_IN => apv_trgstart,\r
+ APV_TRGSEL_IN => apv_trgsel(2),\r
+ APV_TRG_TODO_IN => trg_2_todo_in,\r
+ APV_TRG_DELAY_IN => trg_2_delay_in,\r
+ APV_TRGDONE_OUT => apv_trgdone(2),\r
+ APV_TRG_OUT => apv_trg(2),\r
+ APV_TRGSENT_OUT => apv_trgsent(2),\r
+ BSM_OUT => open,\r
+ DEBUG_OUT => open\r
+ );\r
+\r
+---------------------------------------------------------------------------\r
+-- Trigger input 1: normal trigger\r
+---------------------------------------------------------------------------\r
+THE_APV_TRG_HANDLER_1: apv_trg_handler\r
+port map( CLK_APV_IN => clk_apv_in,\r
+ RESET_APV_IN => apv_clk_rst,\r
+ CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ APV_TRGSTART_IN => apv_trgstart,\r
+ APV_TRGSEL_IN => apv_trgsel(1),\r
+ APV_TRG_TODO_IN => trg_1_todo_in,\r
+ APV_TRG_DELAY_IN => trg_1_delay_in,\r
+ APV_TRGDONE_OUT => apv_trgdone(1),\r
+ APV_TRG_OUT => apv_trg(1),\r
+ APV_TRGSENT_OUT => apv_trgsent(1),\r
+ BSM_OUT => open,\r
+ DEBUG_OUT => open\r
+ );\r
+\r
+---------------------------------------------------------------------------\r
+-- Trigger input 0: normal trigger\r
+---------------------------------------------------------------------------\r
+THE_APV_TRG_HANDLER_0: apv_trg_handler\r
+port map( CLK_APV_IN => clk_apv_in,\r
+ RESET_APV_IN => apv_clk_rst,\r
+ CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ APV_TRGSTART_IN => apv_trgstart,\r
+ APV_TRGSEL_IN => apv_trgsel(0),\r
+ APV_TRG_TODO_IN => trg_0_todo_in,\r
+ APV_TRG_DELAY_IN => trg_0_delay_in,\r
+ APV_TRGDONE_OUT => apv_trgdone(0),\r
+ APV_TRG_OUT => apv_trg(0),\r
+ APV_TRGSENT_OUT => apv_trgsent(0),\r
+ BSM_OUT => open,\r
+ DEBUG_OUT => open\r
+ );\r
+\r
+---------------------------------------------------------------------------\r
+-- APV SYNC trigger signal -- NOT CLEAN, outside trigger logic!\r
+---------------------------------------------------------------------------\r
+THE_APV_SYNC_HANDLER: apv_sync_handler\r
+port map( CLK_APV_IN => clk_apv_in,\r
+ RESET_APV_IN => apv_clk_rst,\r
+ CLK_IN => clk_in,\r
+ RESET_IN => reset_in, \r
+ APV_TRGSTART_IN => sync_trg_in,\r
+ APV_TRGSEL_IN => '1',\r
+ APV_TRGDONE_OUT => open,\r
+ APV_TRG_OUT => apv_sync_signal,\r
+ APV_SYNC_OUT => apv_sync,\r
+ BSM_OUT => open,\r
+ DEBUG_OUT => open\r
+ );\r
+\r
+-- combine all DONE and SENT signals for feedback\r
+next_apv_trgdone_all <= apv_trgdone(3) or apv_trgdone(2) or apv_trgdone(1) or apv_trgdone(0);\r
+next_apv_trgsent_all <= apv_trgsent(3) or apv_trgsent(2) or apv_trgsent(1) or apv_trgsent(0);\r
+\r
+THE_SYNC_AVP_HOUSEKEEPING_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ apv_trgdone_all <= next_apv_trgdone_all;\r
+ apv_trgsent_all <= next_apv_trgsent_all;\r
+ end if;\r
+end process THE_SYNC_AVP_HOUSEKEEPING_PROC;\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- APV triggering\r
+---------------------------------------------------------------------------\r
+-- we combine all four trigger sources, and the sync source\r
+next_apv_trg_all <= apv_trg(3) or apv_trg(2) or apv_trg(1) or apv_trg(0) or apv_sync_signal;\r
+\r
+THE_SYNC_AVP_TRG_PROC: process( clk_apv_in )\r
+begin\r
+ if( rising_edge(clk_apv_in) ) then\r
+ apv_trg_all <= next_apv_trg_all;\r
+ end if;\r
+end process THE_SYNC_AVP_TRG_PROC;\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- output signals\r
+---------------------------------------------------------------------------\r
+eds_data_out <= eds_data;\r
+eds_avail_out <= eds_avail;\r
+eds_full_out <= eds_full;\r
+eds_level_out <= eds_level;\r
+frm_reqd_out <= apv_trgsent_all;\r
+trb_release_out <= trb_release;\r
+trb_missing_out <= trb_missing;\r
+trb_counter_out <= trb_counter;\r
+\r
+apv_trg_out <= apv_trg_all;\r
+apv_sync_out <= apv_sync;\r
+\r
+trg_found_out <= trg_found;\r
+trg_max_out <= maximum_trg;\r
+\r
+---------------------------------------------------------------------------\r
+-- Debug signals\r
+---------------------------------------------------------------------------\r
+debug_out <= debug;\r
+\r
+end behavioral;\r
+\r
+\r
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.std_logic_arith.all;\r
+use ieee.std_logic_unsigned.all;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+-- bugfixing:\r
+-- ddmmyy - blafasel\r
+\r
+entity buf_toc is\r
+ port( CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ BUF_TICK_IN : in std_logic; -- tickmark from raw buffer\r
+ BUF_START_IN : in std_logic; -- start of frame from raw buffer\r
+ WAITFRAME_IN : in std_logic; -- statemachine is in "wait for frame" mode\r
+ FRAMES_REQD_IN : in std_logic_vector(3 downto 0); -- number of frames requested from EDS\r
+ BUF_LVL_IN : in std_logic_vector(7 downto 0);\r
+ GOODDATA_OUT : out std_logic; -- APV is on, sent data, process it\r
+ BADDATA_OUT : out std_logic; -- APV is on, broken buffer, NO processing, only ERROR HDR\r
+ NODATA_OUT : out std_logic; -- APV is off, do not send anything!\r
+ READY_OUT : out std_logic;\r
+ BSM_OUT : out std_logic_vector(7 downto 0);\r
+ DBG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
+end;\r
+\r
+architecture behavioral of buf_toc is\r
+\r
+ -- components\r
+\r
+ -- state machine signals\r
+ type STATES is (SLEEP,CLEAR,RSTTOC,WATCH,COUNT,GDATA,BDATA,IDATA,DONE);\r
+ signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+ -- normal signals\r
+ signal bsm_x : std_logic_vector(7 downto 0);\r
+ signal debug_x : std_logic_vector(15 downto 0);\r
+\r
+ signal buf_lvl : std_logic_vector(4 downto 0);\r
+ signal buf_good : std_logic;\r
+ signal buf_broken : std_logic;\r
+ signal buf_ignore : std_logic;\r
+ \r
+ signal next_gooddata : std_logic;\r
+ signal gooddata : std_logic;\r
+ signal next_baddata : std_logic;\r
+ signal baddata : std_logic;\r
+ signal next_nodata : std_logic;\r
+ signal nodata : std_logic;\r
+ signal next_ready : std_logic;\r
+ signal ready : std_logic;\r
+\r
+ signal frames_needed : std_logic_vector(4 downto 0);\r
+\r
+ signal next_frames_avail : std_logic;\r
+ signal frames_avail : std_logic;\r
+\r
+ signal toc_ctr : std_logic_vector(3 downto 0);\r
+ signal next_toc_rst : std_logic;\r
+ signal toc_rst : std_logic;\r
+ signal next_toc_ce : std_logic;\r
+ signal toc_ce : std_logic;\r
+ signal next_toc_hit : std_logic;\r
+ signal toc_hit : std_logic;\r
+ \r
+ signal next_stat_clr : std_logic;\r
+ signal stat_clr : std_logic;\r
+ \r
+ signal stat_good : std_logic;\r
+ signal stat_bad : std_logic;\r
+ signal stat_ignore : std_logic;\r
+ \r
+begin\r
+\r
+-- Aliasing\r
+buf_good <= buf_lvl_in(7);\r
+buf_broken <= buf_lvl_in(6);\r
+buf_ignore <= buf_lvl_in(5);\r
+buf_lvl <= buf_lvl_in(4 downto 0);\r
+\r
+-- Timeout counter\r
+THE_TIMEOUT_COUNTER_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( (reset_in = '1') or (toc_rst = '1') ) then\r
+ toc_ctr <= (others => '0');\r
+ elsif( toc_ce = '1' ) then\r
+ toc_ctr <= toc_ctr + 1;\r
+ end if;\r
+ end if;\r
+end process THE_TIMEOUT_COUNTER_PROC;\r
+\r
+next_toc_hit <= '1' when (toc_ctr = x"f") else '0';\r
+\r
+-- Check for the number of available frames\r
+frames_needed <= '0' & frames_reqd_in;\r
+next_frames_avail <= '1' when ( buf_lvl >= frames_needed ) else '0';\r
+\r
+-- Synchronization process\r
+THE_SYNC_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ toc_hit <= next_toc_hit;\r
+ frames_avail <= next_frames_avail;\r
+ end if;\r
+end process THE_SYNC_PROC;\r
+\r
+-- state machine for handling synchronisation\r
+-- state registers\r
+STATE_MEM: process( clk_in ) \r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ CURRENT_STATE <= SLEEP;\r
+ gooddata <= '0';\r
+ baddata <= '0';\r
+ nodata <= '0';\r
+ toc_ce <= '0';\r
+ toc_rst <= '0';\r
+ ready <= '0';\r
+ stat_clr <= '0';\r
+ else\r
+ CURRENT_STATE <= NEXT_STATE;\r
+ gooddata <= next_gooddata;\r
+ baddata <= next_baddata;\r
+ nodata <= next_nodata;\r
+ toc_ce <= next_toc_ce;\r
+ toc_rst <= next_toc_rst;\r
+ ready <= next_ready;\r
+ stat_clr <= next_stat_clr;\r
+ end if;\r
+ end if;\r
+end process STATE_MEM;\r
+\r
+\r
+-- state transitions\r
+STATE_TRANSFORM: process( CURRENT_STATE, waitframe_in, buf_good, buf_ignore, \r
+ buf_start_in, buf_tick_in, frames_avail, toc_hit )\r
+begin\r
+ NEXT_STATE <= SLEEP; -- avoid latches\r
+ next_gooddata <= '0';\r
+ next_baddata <= '0';\r
+ next_nodata <= '0';\r
+ next_toc_ce <= '0';\r
+ next_toc_rst <= '0';\r
+ next_ready <= '0';\r
+ next_stat_clr <= '0';\r
+ case CURRENT_STATE is\r
+ when SLEEP => if( waitframe_in = '1' ) then\r
+ NEXT_STATE <= CLEAR;\r
+ next_stat_clr <= '1';\r
+ else\r
+ NEXT_STATE <= SLEEP;\r
+ end if;\r
+ when CLEAR => if ( buf_ignore = '1' ) then\r
+ NEXT_STATE <= IDATA; -- switched off buffer, ignore it\r
+ next_nodata <= '1';\r
+ elsif( buf_good = '1' ) then\r
+ NEXT_STATE <= RSTTOC; -- good buffer, start of wait\r
+ next_toc_rst <= '1';\r
+ else\r
+ NEXT_STATE <= BDATA; -- bad buffer, so we skip it immediatly\r
+ next_baddata <= '1';\r
+ end if;\r
+ when RSTTOC => NEXT_STATE <= WATCH;\r
+ when WATCH => if ( frames_avail = '1' ) then\r
+ NEXT_STATE <= GDATA; -- all frames did arrive\r
+ next_gooddata <= '1';\r
+ elsif( (toc_hit = '1') or (buf_good = '0') ) then\r
+ NEXT_STATE <= BDATA; -- timeout or broken buffer\r
+ next_baddata <= '1';\r
+ elsif( (frames_avail = '0') and (buf_start_in = '1') ) then\r
+ NEXT_STATE <= RSTTOC; -- buffer arrived, reset TOC\r
+ next_toc_rst <= '1';\r
+ elsif( (frames_avail = '0') and (buf_tick_in = '1') ) then\r
+ NEXT_STATE <= COUNT;\r
+ next_toc_ce <= '1';\r
+ else\r
+ NEXT_STATE <= WATCH;\r
+ end if;\r
+ when COUNT => NEXT_STATE <= WATCH;\r
+ when GDATA => NEXT_STATE <= DONE;\r
+ next_ready <= '1';\r
+ when BDATA => NEXT_STATE <= DONE;\r
+ next_ready <= '1';\r
+ when IDATA => NEXT_STATE <= DONE;\r
+ next_ready <= '1';\r
+ when DONE => if( waitframe_in = '1' ) then\r
+ NEXT_STATE <= DONE;\r
+ next_ready <= '1';\r
+ else\r
+ NEXT_STATE <= SLEEP;\r
+ end if;\r
+ \r
+ when others => NEXT_STATE <= SLEEP;\r
+ end case;\r
+end process STATE_TRANSFORM;\r
+\r
+-- state decoding\r
+STATE_DECODE: process( CURRENT_STATE )\r
+begin\r
+ case CURRENT_STATE is\r
+ when SLEEP => bsm_x <= x"00";\r
+ when CLEAR => bsm_x <= x"01"; \r
+ when RSTTOC => bsm_x <= x"02"; \r
+ when WATCH => bsm_x <= x"03";\r
+ when COUNT => bsm_x <= x"04";\r
+ when GDATA => bsm_x <= x"05";\r
+ when BDATA => bsm_x <= x"06";\r
+ when IDATA => bsm_x <= x"07";\r
+ when DONE => bsm_x <= x"08";\r
+ when others => bsm_x <= x"ff";\r
+ end case;\r
+end process STATE_DECODE;\r
+\r
+-- We store the GOODDATA and BADDATA result for the following data transfer\r
+-- stat_good and stat_bad are valid for the whole buffer processing phase!\r
+THE_GOODDATA_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( (reset_in = '1') or (stat_clr = '1') ) then\r
+ stat_good <= '0';\r
+ elsif( gooddata = '1' ) then\r
+ stat_good <= '1';\r
+ end if;\r
+ end if;\r
+end process THE_GOODDATA_PROC;\r
+THE_BADDATA_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( (reset_in = '1') or (stat_clr = '1') ) then\r
+ stat_bad <= '0';\r
+ elsif( baddata = '1' ) then\r
+ stat_bad <= '1';\r
+ end if;\r
+ end if;\r
+end process THE_BADDATA_PROC;\r
+THE_IGNOREDATA_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( (reset_in = '1') or (stat_clr = '1') ) then\r
+ stat_ignore <= '0';\r
+ elsif( nodata = '1' ) then\r
+ stat_ignore <= '1';\r
+ end if;\r
+ end if;\r
+end process THE_IGNOREDATA_PROC;\r
+\r
+-- output signals\r
+gooddata_out <= stat_good;\r
+baddata_out <= stat_bad;\r
+nodata_out <= stat_ignore;\r
+ready_out <= ready;\r
+\r
+-- debug signals\r
+debug_x(15 downto 9) <= (others => '0');\r
+debug_x(8) <= toc_hit;\r
+debug_x(7) <= frames_avail;\r
+debug_x(6) <= gooddata;\r
+debug_x(5) <= baddata;\r
+debug_x(4) <= ready;\r
+debug_x(3 downto 0) <= toc_ctr;\r
+\r
+dbg_out <= debug_x;\r
+bsm_out <= bsm_x;\r
+\r
+end behavioral;\r
--- /dev/null
+[Device]\r
+Family=latticeecp2m\r
+PartType=LFE2M100E\r
+PartName=LFE2M100E-6F900C\r
+SpeedGrade=-6\r
+Package=FPBGA900\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=Comparator\r
+CoreRevision=3.1\r
+ModuleName=comp14bit\r
+SourceFormat=VHDL\r
+ParameterFileVersion=1.0\r
+Date=02/26/2009\r
+Time=14:35:12\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+InputWidth=14\r
+FuncComparator= A >= B\r
+ReprComparator=Unsigned\r
+Lut=0\r
+OutReg=1\r
+Stage=0\r
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v72_PROD_Build (44)
+-- Module Version: 3.1
+--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n comp14bit -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type comp -width 14 -unsigned -port ageb -output_reg -enable -pipeline 0 -e
+
+-- Thu Feb 26 14:35:13 2009
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity comp14bit is
+ port (
+ DataA: in std_logic_vector(13 downto 0);
+ DataB: in std_logic_vector(13 downto 0);
+ Clock: in std_logic;
+ ClockEn: in std_logic;
+ Aclr: in std_logic;
+ AGEB: out std_logic);
+end comp14bit;
+
+architecture Structure of comp14bit is
+
+ -- internal signal declarations
+ signal scuba_vhi: std_logic;
+ signal cmp_ci: std_logic;
+ signal co0: std_logic;
+ signal co1: std_logic;
+ signal co2: std_logic;
+ signal co3: std_logic;
+ signal co4: std_logic;
+ signal co5: std_logic;
+ signal ageb_out: std_logic;
+ signal ageb_out_c: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component AGEB2
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; GE: out std_logic);
+ end component;
+ component FADD2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; COUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FD1P3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ attribute GSR : string;
+ attribute GSR of FF_0 : label is "ENABLED";
+
+begin
+ -- component instantiation statements
+ FF_0: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ageb_out, SP=>ClockEn, CK=>Clock, CD=>Aclr, Q=>AGEB);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ cmp_ci_a: FADD2B
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open,
+ S1=>open);
+
+ cmp_0: AGEB2
+ port map (A0=>DataA(0), A1=>DataA(1), B0=>DataB(0), B1=>DataB(1),
+ CI=>cmp_ci, GE=>co0);
+
+ cmp_1: AGEB2
+ port map (A0=>DataA(2), A1=>DataA(3), B0=>DataB(2), B1=>DataB(3),
+ CI=>co0, GE=>co1);
+
+ cmp_2: AGEB2
+ port map (A0=>DataA(4), A1=>DataA(5), B0=>DataB(4), B1=>DataB(5),
+ CI=>co1, GE=>co2);
+
+ cmp_3: AGEB2
+ port map (A0=>DataA(6), A1=>DataA(7), B0=>DataB(6), B1=>DataB(7),
+ CI=>co2, GE=>co3);
+
+ cmp_4: AGEB2
+ port map (A0=>DataA(8), A1=>DataA(9), B0=>DataB(8), B1=>DataB(9),
+ CI=>co3, GE=>co4);
+
+ cmp_5: AGEB2
+ port map (A0=>DataA(10), A1=>DataA(11), B0=>DataB(10),
+ B1=>DataB(11), CI=>co4, GE=>co5);
+
+ cmp_6: AGEB2
+ port map (A0=>DataA(12), A1=>DataA(13), B0=>DataB(12),
+ B1=>DataB(13), CI=>co5, GE=>ageb_out_c);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a0: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>ageb_out_c, COUT=>open, S0=>ageb_out,
+ S1=>open);
+
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of comp14bit is
+ for Structure
+ for all:AGEB2 use entity ecp2m.AGEB2(V); end for;
+ for all:FADD2B use entity ecp2m.FADD2B(V); end for;
+ for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
+ for all:VHI use entity ecp2m.VHI(V); end for;
+ for all:VLO use entity ecp2m.VLO(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_PROD_Build (44)
+-- Module Version: 3.1
+-- Thu Feb 26 14:35:13 2009
+
+-- parameterized module component declaration
+component comp14bit
+ port (DataA: in std_logic_vector(13 downto 0);
+ DataB: in std_logic_vector(13 downto 0); Clock: in std_logic;
+ ClockEn: in std_logic; Aclr: in std_logic;
+ AGEB: out std_logic);
+end component;
+
+-- parameterized module component instance
+__ : comp14bit
+ port map (DataA(13 downto 0)=>__, DataB(13 downto 0)=>__, Clock=>__,
+ ClockEn=>__, Aclr=>__, AGEB=>__);
--- /dev/null
+[Device]\r
+Family=latticeecp2m\r
+PartType=LFE2M100E\r
+PartName=LFE2M100E-6F900C\r
+SpeedGrade=-6\r
+Package=FPBGA900\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=Comparator\r
+CoreRevision=3.1\r
+ModuleName=comp4bit\r
+SourceFormat=VHDL\r
+ParameterFileVersion=1.0\r
+Date=10/09/2009\r
+Time=16:19:24\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+InputWidth=4\r
+FuncComparator= A > B\r
+ReprComparator=Unsigned\r
+Lut=0\r
+OutReg=0\r
+Stage=0\r
--- /dev/null
+SCUBA, Version ispLever_v72_SP2_Build (23)
+Fri Oct 09 16:19:24 2009
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp. All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
+Copyright (c) 2001 Agere Systems All rights reserved.
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
+
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n comp4bit -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type comp -width 4 -unsigned -port agtb -e
+ Circuit name : comp4bit
+ Module type : comp
+ Module Version : 3.1
+ Width : 4
+ Ports :
+ Inputs : DataA[3:0], DataB[3:0]
+ Outputs : AGTB
+ I/O buffer : not inserted
+ Representation : unsigned number
+ EDIF output : suppressed
+ VHDL output : comp4bit.vhd
+ VHDL template : comp4bit_tmpl.vhd
+ VHDL testbench : tb_comp4bit_tmpl.vhd
+ VHDL purpose : for synthesis and simulation
+ Bus notation : big endian
+ Report output : comp4bit.srp
+ Element Usage :
+ ALEB2 : 2
+ FADD2B : 2
+ INV : 1
+ Estimated Resource Usage:
+ LUT : 8
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23)
+-- Module Version: 3.1
+--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n comp4bit -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type comp -width 4 -unsigned -port agtb -e
+
+-- Fri Oct 09 16:19:24 2009
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity comp4bit is
+ port (
+ DataA: in std_logic_vector(3 downto 0);
+ DataB: in std_logic_vector(3 downto 0);
+ AGTB: out std_logic);
+end comp4bit;
+
+architecture Structure of comp4bit is
+
+ -- internal signal declarations
+ signal co1_inv: std_logic;
+ signal scuba_vhi: std_logic;
+ signal cmp_ci: std_logic;
+ signal co0: std_logic;
+ signal co1: std_logic;
+ signal agtb_out_c: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component ALEB2
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; LE: out std_logic);
+ end component;
+ component FADD2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; COUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ INV_0: INV
+ port map (A=>co1, Z=>co1_inv);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ cmp_ci_a: FADD2B
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open,
+ S1=>open);
+
+ cmp_0: ALEB2
+ port map (A0=>DataA(0), A1=>DataA(1), B0=>DataB(0), B1=>DataB(1),
+ CI=>cmp_ci, LE=>co0);
+
+ cmp_1: ALEB2
+ port map (A0=>DataA(2), A1=>DataA(3), B0=>DataB(2), B1=>DataB(3),
+ CI=>co0, LE=>agtb_out_c);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a0: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>agtb_out_c, COUT=>open, S0=>co1, S1=>open);
+
+ AGTB <= co1_inv;
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of comp4bit is
+ for Structure
+ for all:ALEB2 use entity ecp2m.ALEB2(V); end for;
+ for all:FADD2B use entity ecp2m.FADD2B(V); end for;
+ for all:INV use entity ecp2m.INV(V); end for;
+ for all:VHI use entity ecp2m.VHI(V); end for;
+ for all:VLO use entity ecp2m.VLO(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+Starting process: \r
+\r
+SCUBA, Version ispLever_v72_SP2_Build (23)\r
+Fri Oct 09 16:19:24 2009\r
+\r
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
+Copyright (c) 1995 AT&T Corp. All rights reserved.\r
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
+Copyright (c) 2001 Agere Systems All rights reserved.\r
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
+\r
+BEGIN SCUBA Module Synthesis\r
+\r
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n comp4bit -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type comp -width 4 -unsigned -port agtb -e \r
+ Circuit name : comp4bit\r
+ Module type : comp\r
+ Module Version : 3.1\r
+ Width : 4\r
+ Ports : \r
+ Inputs : DataA[3:0], DataB[3:0]\r
+ Outputs : AGTB\r
+ I/O buffer : not inserted\r
+ Representation : unsigned number\r
+ EDIF output : suppressed\r
+ VHDL output : comp4bit.vhd\r
+ VHDL template : comp4bit_tmpl.vhd\r
+ VHDL testbench : tb_comp4bit_tmpl.vhd\r
+ VHDL purpose : for synthesis and simulation\r
+ Bus notation : big endian\r
+ Report output : comp4bit.srp\r
+ Estimated Resource Usage:\r
+ LUT : 8\r
+\r
+END SCUBA Module Synthesis\r
+\r
+File: comp4bit.lpc created.\r
+\r
+\r
+End process: completed successfully.\r
+\r
+\r
+Total Warnings: 0\r
+\r
+Total Errors: 0\r
+\r
+\r
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23)
+-- Module Version: 3.1
+-- Fri Oct 09 16:19:24 2009
+
+-- parameterized module component declaration
+component comp4bit
+ port (DataA: in std_logic_vector(3 downto 0);
+ DataB: in std_logic_vector(3 downto 0); AGTB: out std_logic);
+end component;
+
+-- parameterized module component instance
+__ : comp4bit
+ port map (DataA(3 downto 0)=>__, DataB(3 downto 0)=>__, AGTB=>__);
--- /dev/null
+[Device]\r
+Family=latticeecp2m\r
+PartType=LFE2M100E\r
+PartName=LFE2M100E-6F900C\r
+SpeedGrade=-6\r
+Package=FPBGA900\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=FIFO_DC\r
+CoreRevision=5.0\r
+ModuleName=crossover\r
+SourceFormat=VHDL\r
+ParameterFileVersion=1.0\r
+Date=11/20/2009\r
+Time=11:16:47\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+FIFOImp=LUT Based\r
+Depth=16\r
+Width=96\r
+RDepth=16\r
+RWidth=96\r
+regout=0\r
+CtrlByRdEn=0\r
+EmpFlg=0\r
+PeMode=Static - Single Threshold\r
+PeAssert=4\r
+PeDeassert=12\r
+FullFlg=0\r
+PfMode=Static - Single Threshold\r
+PfAssert=12\r
+PfDeassert=506\r
+RDataCount=1\r
+WDataCount=1\r
+EnECC=0\r
--- /dev/null
+SCUBA, Version ispLever_v72_PROD_Build (44)
+Fri Nov 20 11:16:48 2009
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp. All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
+Copyright (c) 2001 Agere Systems All rights reserved.
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
+
+ Issued command : F:\Programme\ispTOOLS7_2\ispfpga\bin\nt\scuba.exe -w -n crossover -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -pfu_fifo -addr_width 4 -data_width 96 -num_words 16 -rdata_width 96 -no_enable -pe -1 -pf -1 -rfill -fill -e
+ Circuit name : crossover
+ Module type : ebfifo
+ Module Version : 5.0
+ Ports :
+ Inputs : Data[95:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
+ Outputs : Q[95:0], WCNT[4:0], RCNT[4:0], Empty, Full
+ I/O buffer : not inserted
+ EDIF output : suppressed
+ VHDL output : crossover.vhd
+ VHDL template : crossover_tmpl.vhd
+ VHDL testbench : tb_crossover_tmpl.vhd
+ VHDL purpose : for synthesis and simulation
+ Bus notation : big endian
+ Report output : crossover.srp
+ Element Usage :
+ AGEB2 : 6
+ AND2 : 2
+ CU2 : 6
+ FADD2B : 8
+ FSUB2B : 6
+ FD1P3BX : 2
+ FD1P3DX : 124
+ FD1S3BX : 1
+ FD1S3DX : 31
+ INV : 2
+ OR2 : 1
+ ROM16X1 : 13
+ DPR16X4A : 24
+ XOR2 : 10
+ Estimated Resource Usage:
+ LUT : 78
+ DRAM : 24
+ Reg : 158
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v72_PROD_Build (44)
+-- Module Version: 5.0
+--F:\Programme\ispTOOLS7_2\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -pfu_fifo -depth 16 -width 96 -depth 16 -rdata_width 96 -no_enable -pe -1 -pf -1 -rfill -fill -e
+
+-- Fri Nov 20 11:16:48 2009
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity crossover is
+ port (
+ Data: in std_logic_vector(95 downto 0);
+ WrClock: in std_logic;
+ RdClock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ RPReset: in std_logic;
+ Q: out std_logic_vector(95 downto 0);
+ WCNT: out std_logic_vector(4 downto 0);
+ RCNT: out std_logic_vector(4 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic);
+end crossover;
+
+architecture Structure of crossover is
+
+ -- internal signal declarations
+ signal invout_1: std_logic;
+ signal invout_0: std_logic;
+ signal w_gdata_0: std_logic;
+ signal w_gdata_1: std_logic;
+ signal w_gdata_2: std_logic;
+ signal w_gdata_3: std_logic;
+ signal wptr_4: std_logic;
+ signal r_gdata_0: std_logic;
+ signal r_gdata_1: std_logic;
+ signal r_gdata_2: std_logic;
+ signal r_gdata_3: std_logic;
+ signal rptr_4: std_logic;
+ signal w_gcount_0: std_logic;
+ signal w_gcount_1: std_logic;
+ signal w_gcount_2: std_logic;
+ signal w_gcount_3: std_logic;
+ signal w_gcount_4: std_logic;
+ signal r_gcount_0: std_logic;
+ signal r_gcount_1: std_logic;
+ signal r_gcount_2: std_logic;
+ signal r_gcount_3: std_logic;
+ signal r_gcount_4: std_logic;
+ signal w_gcount_r20: std_logic;
+ signal w_gcount_r0: std_logic;
+ signal w_gcount_r21: std_logic;
+ signal w_gcount_r1: std_logic;
+ signal w_gcount_r22: std_logic;
+ signal w_gcount_r2: std_logic;
+ signal w_gcount_r23: std_logic;
+ signal w_gcount_r3: std_logic;
+ signal w_gcount_r24: std_logic;
+ signal w_gcount_r4: std_logic;
+ signal r_gcount_w20: std_logic;
+ signal r_gcount_w0: std_logic;
+ signal r_gcount_w21: std_logic;
+ signal r_gcount_w1: std_logic;
+ signal r_gcount_w22: std_logic;
+ signal r_gcount_w2: std_logic;
+ signal r_gcount_w23: std_logic;
+ signal r_gcount_w3: std_logic;
+ signal r_gcount_w24: std_logic;
+ signal r_gcount_w4: std_logic;
+ signal empty_i: std_logic;
+ signal rRst: std_logic;
+ signal full_i: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal w_gctr_ci: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal co0: std_logic;
+ signal iwcount_4: std_logic;
+ signal co2: std_logic;
+ signal wcount_4: std_logic;
+ signal co1: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal r_gctr_ci: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal co0_1: std_logic;
+ signal ircount_4: std_logic;
+ signal co2_1: std_logic;
+ signal rcount_4: std_logic;
+ signal co1_1: std_logic;
+ signal wfill_sub_0: std_logic;
+ signal wfill_sub_1: std_logic;
+ signal wfill_sub_2: std_logic;
+ signal co0_2: std_logic;
+ signal wfill_sub_3: std_logic;
+ signal wfill_sub_4: std_logic;
+ signal co1_2: std_logic;
+ signal wfill_sub_msb: std_logic;
+ signal co2_2d: std_logic;
+ signal co2_2: std_logic;
+ signal rfill_sub_0: std_logic;
+ signal scuba_vhi: std_logic;
+ signal rfill_sub_1: std_logic;
+ signal rfill_sub_2: std_logic;
+ signal co0_3: std_logic;
+ signal rfill_sub_3: std_logic;
+ signal rfill_sub_4: std_logic;
+ signal co1_3: std_logic;
+ signal rfill_sub_msb: std_logic;
+ signal co2_3d: std_logic;
+ signal co2_3: std_logic;
+ signal rden_i: std_logic;
+ signal cmp_ci: std_logic;
+ signal wcount_r0: std_logic;
+ signal w_g2b_xor_cluster_0: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal co0_4: std_logic;
+ signal wcount_r2: std_logic;
+ signal wcount_r3: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal co1_4: std_logic;
+ signal empty_cmp_clr: std_logic;
+ signal empty_cmp_set: std_logic;
+ signal empty_d: std_logic;
+ signal empty_d_c: std_logic;
+ signal wren_i: std_logic;
+ signal cmp_ci_1: std_logic;
+ signal rcount_w0: std_logic;
+ signal r_g2b_xor_cluster_0: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal co0_5: std_logic;
+ signal rcount_w2: std_logic;
+ signal rcount_w3: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_3: std_logic;
+ signal co1_5: std_logic;
+ signal full_cmp_clr: std_logic;
+ signal full_cmp_set: std_logic;
+ signal full_d: std_logic;
+ signal full_d_c: std_logic;
+ signal scuba_vlo: std_logic;
+ signal rdataout95: std_logic;
+ signal rdataout94: std_logic;
+ signal rdataout93: std_logic;
+ signal rdataout92: std_logic;
+ signal rdataout91: std_logic;
+ signal rdataout90: std_logic;
+ signal rdataout89: std_logic;
+ signal rdataout88: std_logic;
+ signal rdataout87: std_logic;
+ signal rdataout86: std_logic;
+ signal rdataout85: std_logic;
+ signal rdataout84: std_logic;
+ signal rdataout83: std_logic;
+ signal rdataout82: std_logic;
+ signal rdataout81: std_logic;
+ signal rdataout80: std_logic;
+ signal rdataout79: std_logic;
+ signal rdataout78: std_logic;
+ signal rdataout77: std_logic;
+ signal rdataout76: std_logic;
+ signal rdataout75: std_logic;
+ signal rdataout74: std_logic;
+ signal rdataout73: std_logic;
+ signal rdataout72: std_logic;
+ signal rdataout71: std_logic;
+ signal rdataout70: std_logic;
+ signal rdataout69: std_logic;
+ signal rdataout68: std_logic;
+ signal rdataout67: std_logic;
+ signal rdataout66: std_logic;
+ signal rdataout65: std_logic;
+ signal rdataout64: std_logic;
+ signal rdataout63: std_logic;
+ signal rdataout62: std_logic;
+ signal rdataout61: std_logic;
+ signal rdataout60: std_logic;
+ signal rdataout59: std_logic;
+ signal rdataout58: std_logic;
+ signal rdataout57: std_logic;
+ signal rdataout56: std_logic;
+ signal rdataout55: std_logic;
+ signal rdataout54: std_logic;
+ signal rdataout53: std_logic;
+ signal rdataout52: std_logic;
+ signal rdataout51: std_logic;
+ signal rdataout50: std_logic;
+ signal rdataout49: std_logic;
+ signal rdataout48: std_logic;
+ signal rdataout47: std_logic;
+ signal rdataout46: std_logic;
+ signal rdataout45: std_logic;
+ signal rdataout44: std_logic;
+ signal rdataout43: std_logic;
+ signal rdataout42: std_logic;
+ signal rdataout41: std_logic;
+ signal rdataout40: std_logic;
+ signal rdataout39: std_logic;
+ signal rdataout38: std_logic;
+ signal rdataout37: std_logic;
+ signal rdataout36: std_logic;
+ signal rdataout35: std_logic;
+ signal rdataout34: std_logic;
+ signal rdataout33: std_logic;
+ signal rdataout32: std_logic;
+ signal rdataout31: std_logic;
+ signal rdataout30: std_logic;
+ signal rdataout29: std_logic;
+ signal rdataout28: std_logic;
+ signal rdataout27: std_logic;
+ signal rdataout26: std_logic;
+ signal rdataout25: std_logic;
+ signal rdataout24: std_logic;
+ signal rdataout23: std_logic;
+ signal rdataout22: std_logic;
+ signal rdataout21: std_logic;
+ signal rdataout20: std_logic;
+ signal rdataout19: std_logic;
+ signal rdataout18: std_logic;
+ signal rdataout17: std_logic;
+ signal rdataout16: std_logic;
+ signal rdataout15: std_logic;
+ signal rdataout14: std_logic;
+ signal rdataout13: std_logic;
+ signal rdataout12: std_logic;
+ signal rdataout11: std_logic;
+ signal rdataout10: std_logic;
+ signal rdataout9: std_logic;
+ signal rdataout8: std_logic;
+ signal rdataout7: std_logic;
+ signal rdataout6: std_logic;
+ signal rdataout5: std_logic;
+ signal rdataout4: std_logic;
+ signal rdataout3: std_logic;
+ signal rdataout2: std_logic;
+ signal rdataout1: std_logic;
+ signal rdataout0: std_logic;
+ signal rptr_3: std_logic;
+ signal rptr_2: std_logic;
+ signal rptr_1: std_logic;
+ signal rptr_0: std_logic;
+ signal dec0_wre3: std_logic;
+ signal wptr_3: std_logic;
+ signal wptr_2: std_logic;
+ signal wptr_1: std_logic;
+ signal wptr_0: std_logic;
+
+ -- local component declarations
+ component AGEB2
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; GE: out std_logic);
+ end component;
+ component AND2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component CU2
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
+ end component;
+ component FADD2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; COUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FSUB2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; BI: in std_logic; BOUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FD1P3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ PD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1P3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1S3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component FD1S3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component OR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component ROM16X1
+ -- synopsys translate_off
+ generic (initval : in String);
+ -- synopsys translate_on
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component DPR16X4A
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; WCK: in std_logic; WRE: in std_logic;
+ RAD0: in std_logic; RAD1: in std_logic;
+ RAD2: in std_logic; RAD3: in std_logic;
+ WAD0: in std_logic; WAD1: in std_logic;
+ WAD2: in std_logic; WAD3: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component XOR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ attribute initval : string;
+ attribute GSR : string;
+ attribute initval of LUT4_12 : label is "0x8000";
+ attribute initval of LUT4_11 : label is "0x6996";
+ attribute initval of LUT4_10 : label is "0x6996";
+ attribute initval of LUT4_9 : label is "0x6996";
+ attribute initval of LUT4_8 : label is "0x6996";
+ attribute initval of LUT4_7 : label is "0x6996";
+ attribute initval of LUT4_6 : label is "0x6996";
+ attribute initval of LUT4_5 : label is "0x6996";
+ attribute initval of LUT4_4 : label is "0x6996";
+ attribute initval of LUT4_3 : label is "0x0410";
+ attribute initval of LUT4_2 : label is "0x1004";
+ attribute initval of LUT4_1 : label is "0x0140";
+ attribute initval of LUT4_0 : label is "0x4001";
+ attribute GSR of FF_157 : label is "ENABLED";
+ attribute GSR of FF_156 : label is "ENABLED";
+ attribute GSR of FF_155 : label is "ENABLED";
+ attribute GSR of FF_154 : label is "ENABLED";
+ attribute GSR of FF_153 : label is "ENABLED";
+ attribute GSR of FF_152 : label is "ENABLED";
+ attribute GSR of FF_151 : label is "ENABLED";
+ attribute GSR of FF_150 : label is "ENABLED";
+ attribute GSR of FF_149 : label is "ENABLED";
+ attribute GSR of FF_148 : label is "ENABLED";
+ attribute GSR of FF_147 : label is "ENABLED";
+ attribute GSR of FF_146 : label is "ENABLED";
+ attribute GSR of FF_145 : label is "ENABLED";
+ attribute GSR of FF_144 : label is "ENABLED";
+ attribute GSR of FF_143 : label is "ENABLED";
+ attribute GSR of FF_142 : label is "ENABLED";
+ attribute GSR of FF_141 : label is "ENABLED";
+ attribute GSR of FF_140 : label is "ENABLED";
+ attribute GSR of FF_139 : label is "ENABLED";
+ attribute GSR of FF_138 : label is "ENABLED";
+ attribute GSR of FF_137 : label is "ENABLED";
+ attribute GSR of FF_136 : label is "ENABLED";
+ attribute GSR of FF_135 : label is "ENABLED";
+ attribute GSR of FF_134 : label is "ENABLED";
+ attribute GSR of FF_133 : label is "ENABLED";
+ attribute GSR of FF_132 : label is "ENABLED";
+ attribute GSR of FF_131 : label is "ENABLED";
+ attribute GSR of FF_130 : label is "ENABLED";
+ attribute GSR of FF_129 : label is "ENABLED";
+ attribute GSR of FF_128 : label is "ENABLED";
+ attribute GSR of FF_127 : label is "ENABLED";
+ attribute GSR of FF_126 : label is "ENABLED";
+ attribute GSR of FF_125 : label is "ENABLED";
+ attribute GSR of FF_124 : label is "ENABLED";
+ attribute GSR of FF_123 : label is "ENABLED";
+ attribute GSR of FF_122 : label is "ENABLED";
+ attribute GSR of FF_121 : label is "ENABLED";
+ attribute GSR of FF_120 : label is "ENABLED";
+ attribute GSR of FF_119 : label is "ENABLED";
+ attribute GSR of FF_118 : label is "ENABLED";
+ attribute GSR of FF_117 : label is "ENABLED";
+ attribute GSR of FF_116 : label is "ENABLED";
+ attribute GSR of FF_115 : label is "ENABLED";
+ attribute GSR of FF_114 : label is "ENABLED";
+ attribute GSR of FF_113 : label is "ENABLED";
+ attribute GSR of FF_112 : label is "ENABLED";
+ attribute GSR of FF_111 : label is "ENABLED";
+ attribute GSR of FF_110 : label is "ENABLED";
+ attribute GSR of FF_109 : label is "ENABLED";
+ attribute GSR of FF_108 : label is "ENABLED";
+ attribute GSR of FF_107 : label is "ENABLED";
+ attribute GSR of FF_106 : label is "ENABLED";
+ attribute GSR of FF_105 : label is "ENABLED";
+ attribute GSR of FF_104 : label is "ENABLED";
+ attribute GSR of FF_103 : label is "ENABLED";
+ attribute GSR of FF_102 : label is "ENABLED";
+ attribute GSR of FF_101 : label is "ENABLED";
+ attribute GSR of FF_100 : label is "ENABLED";
+ attribute GSR of FF_99 : label is "ENABLED";
+ attribute GSR of FF_98 : label is "ENABLED";
+ attribute GSR of FF_97 : label is "ENABLED";
+ attribute GSR of FF_96 : label is "ENABLED";
+ attribute GSR of FF_95 : label is "ENABLED";
+ attribute GSR of FF_94 : label is "ENABLED";
+ attribute GSR of FF_93 : label is "ENABLED";
+ attribute GSR of FF_92 : label is "ENABLED";
+ attribute GSR of FF_91 : label is "ENABLED";
+ attribute GSR of FF_90 : label is "ENABLED";
+ attribute GSR of FF_89 : label is "ENABLED";
+ attribute GSR of FF_88 : label is "ENABLED";
+ attribute GSR of FF_87 : label is "ENABLED";
+ attribute GSR of FF_86 : label is "ENABLED";
+ attribute GSR of FF_85 : label is "ENABLED";
+ attribute GSR of FF_84 : label is "ENABLED";
+ attribute GSR of FF_83 : label is "ENABLED";
+ attribute GSR of FF_82 : label is "ENABLED";
+ attribute GSR of FF_81 : label is "ENABLED";
+ attribute GSR of FF_80 : label is "ENABLED";
+ attribute GSR of FF_79 : label is "ENABLED";
+ attribute GSR of FF_78 : label is "ENABLED";
+ attribute GSR of FF_77 : label is "ENABLED";
+ attribute GSR of FF_76 : label is "ENABLED";
+ attribute GSR of FF_75 : label is "ENABLED";
+ attribute GSR of FF_74 : label is "ENABLED";
+ attribute GSR of FF_73 : label is "ENABLED";
+ attribute GSR of FF_72 : label is "ENABLED";
+ attribute GSR of FF_71 : label is "ENABLED";
+ attribute GSR of FF_70 : label is "ENABLED";
+ attribute GSR of FF_69 : label is "ENABLED";
+ attribute GSR of FF_68 : label is "ENABLED";
+ attribute GSR of FF_67 : label is "ENABLED";
+ attribute GSR of FF_66 : label is "ENABLED";
+ attribute GSR of FF_65 : label is "ENABLED";
+ attribute GSR of FF_64 : label is "ENABLED";
+ attribute GSR of FF_63 : label is "ENABLED";
+ attribute GSR of FF_62 : label is "ENABLED";
+ attribute GSR of FF_61 : label is "ENABLED";
+ attribute GSR of FF_60 : label is "ENABLED";
+ attribute GSR of FF_59 : label is "ENABLED";
+ attribute GSR of FF_58 : label is "ENABLED";
+ attribute GSR of FF_57 : label is "ENABLED";
+ attribute GSR of FF_56 : label is "ENABLED";
+ attribute GSR of FF_55 : label is "ENABLED";
+ attribute GSR of FF_54 : label is "ENABLED";
+ attribute GSR of FF_53 : label is "ENABLED";
+ attribute GSR of FF_52 : label is "ENABLED";
+ attribute GSR of FF_51 : label is "ENABLED";
+ attribute GSR of FF_50 : label is "ENABLED";
+ attribute GSR of FF_49 : label is "ENABLED";
+ attribute GSR of FF_48 : label is "ENABLED";
+ attribute GSR of FF_47 : label is "ENABLED";
+ attribute GSR of FF_46 : label is "ENABLED";
+ attribute GSR of FF_45 : label is "ENABLED";
+ attribute GSR of FF_44 : label is "ENABLED";
+ attribute GSR of FF_43 : label is "ENABLED";
+ attribute GSR of FF_42 : label is "ENABLED";
+ attribute GSR of FF_41 : label is "ENABLED";
+ attribute GSR of FF_40 : label is "ENABLED";
+ attribute GSR of FF_39 : label is "ENABLED";
+ attribute GSR of FF_38 : label is "ENABLED";
+ attribute GSR of FF_37 : label is "ENABLED";
+ attribute GSR of FF_36 : label is "ENABLED";
+ attribute GSR of FF_35 : label is "ENABLED";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ AND2_t12: AND2
+ port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+ INV_1: INV
+ port map (A=>full_i, Z=>invout_1);
+
+ AND2_t11: AND2
+ port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+ INV_0: INV
+ port map (A=>empty_i, Z=>invout_0);
+
+ OR2_t10: OR2
+ port map (A=>Reset, B=>RPReset, Z=>rRst);
+
+ XOR2_t9: XOR2
+ port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
+
+ XOR2_t8: XOR2
+ port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
+
+ XOR2_t7: XOR2
+ port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
+
+ XOR2_t6: XOR2
+ port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
+
+ XOR2_t5: XOR2
+ port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
+
+ XOR2_t4: XOR2
+ port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
+
+ XOR2_t3: XOR2
+ port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
+
+ XOR2_t2: XOR2
+ port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
+
+ LUT4_12: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vhi, AD2=>wren_i, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec0_wre3);
+
+ LUT4_11: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
+ AD1=>w_gcount_r23, AD0=>w_gcount_r24,
+ DO0=>w_g2b_xor_cluster_0);
+
+ LUT4_10: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>wcount_r3);
+
+ LUT4_9: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23,
+ AD1=>w_gcount_r24, AD0=>scuba_vlo, DO0=>wcount_r2);
+
+ LUT4_8: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
+ AD1=>w_gcount_r22, AD0=>wcount_r3, DO0=>wcount_r0);
+
+ LUT4_7: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
+ AD1=>r_gcount_w23, AD0=>r_gcount_w24,
+ DO0=>r_g2b_xor_cluster_0);
+
+ LUT4_6: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>rcount_w3);
+
+ LUT4_5: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
+ AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>rcount_w2);
+
+ LUT4_4: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
+ AD1=>r_gcount_w22, AD0=>rcount_w3, DO0=>rcount_w0);
+
+ XOR2_t1: XOR2
+ port map (A=>wptr_4, B=>r_gcount_w24, Z=>wfill_sub_msb);
+
+ XOR2_t0: XOR2
+ port map (A=>w_gcount_r24, B=>rptr_4, Z=>rfill_sub_msb);
+
+ LUT4_3: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x0410")
+ -- synopsys translate_on
+ port map (AD3=>rptr_4, AD2=>rcount_4, AD1=>w_gcount_r24,
+ AD0=>scuba_vlo, DO0=>empty_cmp_set);
+
+ LUT4_2: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x1004")
+ -- synopsys translate_on
+ port map (AD3=>rptr_4, AD2=>rcount_4, AD1=>w_gcount_r24,
+ AD0=>scuba_vlo, DO0=>empty_cmp_clr);
+
+ LUT4_1: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x0140")
+ -- synopsys translate_on
+ port map (AD3=>wptr_4, AD2=>wcount_4, AD1=>r_gcount_w24,
+ AD0=>scuba_vlo, DO0=>full_cmp_set);
+
+ LUT4_0: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x4001")
+ -- synopsys translate_on
+ port map (AD3=>wptr_4, AD2=>wcount_4, AD1=>r_gcount_w24,
+ AD0=>scuba_vlo, DO0=>full_cmp_clr);
+
+ FF_157: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
+ Q=>wcount_0);
+
+ FF_156: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_155: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_154: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_153: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_152: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_0);
+
+ FF_151: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_1);
+
+ FF_150: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_2);
+
+ FF_149: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_3);
+
+ FF_148: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_4);
+
+ FF_147: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_0);
+
+ FF_146: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_1);
+
+ FF_145: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_2);
+
+ FF_144: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_3);
+
+ FF_143: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_4);
+
+ FF_142: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
+ Q=>rcount_0);
+
+ FF_141: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_1);
+
+ FF_140: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_2);
+
+ FF_139: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_3);
+
+ FF_138: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_4);
+
+ FF_137: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_0);
+
+ FF_136: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_1);
+
+ FF_135: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_2);
+
+ FF_134: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_3);
+
+ FF_133: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_4);
+
+ FF_132: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_0);
+
+ FF_131: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_1);
+
+ FF_130: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_2);
+
+ FF_129: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_3);
+
+ FF_128: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_4);
+
+ FF_127: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(0));
+
+ FF_126: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(1));
+
+ FF_125: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(2));
+
+ FF_124: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(3));
+
+ FF_123: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(4));
+
+ FF_122: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(5));
+
+ FF_121: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(6));
+
+ FF_120: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout7, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(7));
+
+ FF_119: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout8, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(8));
+
+ FF_118: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout9, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(9));
+
+ FF_117: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout10, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(10));
+
+ FF_116: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout11, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(11));
+
+ FF_115: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout12, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(12));
+
+ FF_114: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout13, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(13));
+
+ FF_113: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout14, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(14));
+
+ FF_112: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout15, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(15));
+
+ FF_111: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout16, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(16));
+
+ FF_110: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout17, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(17));
+
+ FF_109: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout18, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(18));
+
+ FF_108: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout19, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(19));
+
+ FF_107: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout20, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(20));
+
+ FF_106: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout21, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(21));
+
+ FF_105: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout22, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(22));
+
+ FF_104: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout23, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(23));
+
+ FF_103: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout24, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(24));
+
+ FF_102: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout25, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(25));
+
+ FF_101: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout26, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(26));
+
+ FF_100: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout27, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(27));
+
+ FF_99: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout28, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(28));
+
+ FF_98: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout29, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(29));
+
+ FF_97: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout30, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(30));
+
+ FF_96: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout31, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(31));
+
+ FF_95: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout32, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(32));
+
+ FF_94: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout33, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(33));
+
+ FF_93: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout34, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(34));
+
+ FF_92: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout35, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(35));
+
+ FF_91: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout36, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(36));
+
+ FF_90: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout37, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(37));
+
+ FF_89: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout38, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(38));
+
+ FF_88: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout39, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(39));
+
+ FF_87: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout40, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(40));
+
+ FF_86: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout41, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(41));
+
+ FF_85: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout42, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(42));
+
+ FF_84: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout43, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(43));
+
+ FF_83: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout44, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(44));
+
+ FF_82: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout45, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(45));
+
+ FF_81: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout46, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(46));
+
+ FF_80: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout47, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(47));
+
+ FF_79: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout48, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(48));
+
+ FF_78: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout49, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(49));
+
+ FF_77: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout50, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(50));
+
+ FF_76: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout51, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(51));
+
+ FF_75: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout52, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(52));
+
+ FF_74: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout53, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(53));
+
+ FF_73: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout54, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(54));
+
+ FF_72: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout55, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(55));
+
+ FF_71: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout56, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(56));
+
+ FF_70: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout57, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(57));
+
+ FF_69: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout58, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(58));
+
+ FF_68: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout59, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(59));
+
+ FF_67: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout60, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(60));
+
+ FF_66: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout61, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(61));
+
+ FF_65: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout62, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(62));
+
+ FF_64: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout63, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(63));
+
+ FF_63: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout64, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(64));
+
+ FF_62: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout65, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(65));
+
+ FF_61: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout66, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(66));
+
+ FF_60: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout67, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(67));
+
+ FF_59: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout68, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(68));
+
+ FF_58: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout69, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(69));
+
+ FF_57: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout70, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(70));
+
+ FF_56: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout71, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(71));
+
+ FF_55: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout72, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(72));
+
+ FF_54: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout73, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(73));
+
+ FF_53: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout74, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(74));
+
+ FF_52: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout75, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(75));
+
+ FF_51: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout76, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(76));
+
+ FF_50: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout77, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(77));
+
+ FF_49: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout78, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(78));
+
+ FF_48: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout79, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(79));
+
+ FF_47: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout80, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(80));
+
+ FF_46: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout81, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(81));
+
+ FF_45: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout82, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(82));
+
+ FF_44: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout83, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(83));
+
+ FF_43: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout84, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(84));
+
+ FF_42: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout85, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(85));
+
+ FF_41: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout86, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(86));
+
+ FF_40: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout87, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(87));
+
+ FF_39: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout88, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(88));
+
+ FF_38: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout89, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(89));
+
+ FF_37: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout90, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(90));
+
+ FF_36: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout91, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(91));
+
+ FF_35: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout92, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(92));
+
+ FF_34: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout93, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(93));
+
+ FF_33: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout94, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(94));
+
+ FF_32: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout95, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(95));
+
+ FF_31: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
+
+ FF_30: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
+
+ FF_29: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
+
+ FF_28: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
+
+ FF_27: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
+
+ FF_26: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
+
+ FF_25: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
+
+ FF_24: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
+
+ FF_23: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
+
+ FF_22: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
+
+ FF_21: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r20);
+
+ FF_20: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r21);
+
+ FF_19: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r22);
+
+ FF_18: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r23);
+
+ FF_17: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r24);
+
+ FF_16: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
+
+ FF_15: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
+
+ FF_14: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
+
+ FF_13: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
+
+ FF_12: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
+
+ FF_11: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wfill_sub_0, CK=>WrClock, CD=>Reset, Q=>WCNT(0));
+
+ FF_10: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wfill_sub_1, CK=>WrClock, CD=>Reset, Q=>WCNT(1));
+
+ FF_9: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wfill_sub_2, CK=>WrClock, CD=>Reset, Q=>WCNT(2));
+
+ FF_8: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wfill_sub_3, CK=>WrClock, CD=>Reset, Q=>WCNT(3));
+
+ FF_7: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wfill_sub_4, CK=>WrClock, CD=>Reset, Q=>WCNT(4));
+
+ FF_6: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_0, CK=>RdClock, CD=>rRst, Q=>RCNT(0));
+
+ FF_5: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_1, CK=>RdClock, CD=>rRst, Q=>RCNT(1));
+
+ FF_4: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_2, CK=>RdClock, CD=>rRst, Q=>RCNT(2));
+
+ FF_3: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_3, CK=>RdClock, CD=>rRst, Q=>RCNT(3));
+
+ FF_2: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_4, CK=>RdClock, CD=>rRst, Q=>RCNT(4));
+
+ FF_1: FD1S3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
+
+ FF_0: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
+
+ w_gctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
+ S1=>open);
+
+ w_gctr_0: CU2
+ port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
+ NC0=>iwcount_0, NC1=>iwcount_1);
+
+ w_gctr_1: CU2
+ port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
+ NC0=>iwcount_2, NC1=>iwcount_3);
+
+ w_gctr_2: CU2
+ port map (CI=>co1, PC0=>wcount_4, PC1=>scuba_vlo, CO=>co2,
+ NC0=>iwcount_4, NC1=>open);
+
+ r_gctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
+ S1=>open);
+
+ r_gctr_0: CU2
+ port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
+ NC0=>ircount_0, NC1=>ircount_1);
+
+ r_gctr_1: CU2
+ port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
+ NC0=>ircount_2, NC1=>ircount_3);
+
+ r_gctr_2: CU2
+ port map (CI=>co1_1, PC0=>rcount_4, PC1=>scuba_vlo, CO=>co2_1,
+ NC0=>ircount_4, NC1=>open);
+
+ wfill_0: FSUB2B
+ port map (A0=>scuba_vhi, A1=>wptr_0, B0=>scuba_vlo,
+ B1=>rcount_w0, BI=>scuba_vlo, BOUT=>co0_2, S0=>open,
+ S1=>wfill_sub_0);
+
+ wfill_1: FSUB2B
+ port map (A0=>wptr_1, A1=>wptr_2, B0=>r_g2b_xor_cluster_0,
+ B1=>rcount_w2, BI=>co0_2, BOUT=>co1_2, S0=>wfill_sub_1,
+ S1=>wfill_sub_2);
+
+ wfill_2: FSUB2B
+ port map (A0=>wptr_3, A1=>wfill_sub_msb, B0=>rcount_w3,
+ B1=>scuba_vlo, BI=>co1_2, BOUT=>co2_2, S0=>wfill_sub_3,
+ S1=>wfill_sub_4);
+
+ wfilld: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co2_2, COUT=>open, S0=>co2_2d, S1=>open);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ rfill_0: FSUB2B
+ port map (A0=>scuba_vhi, A1=>wcount_r0, B0=>scuba_vlo,
+ B1=>rptr_0, BI=>scuba_vlo, BOUT=>co0_3, S0=>open,
+ S1=>rfill_sub_0);
+
+ rfill_1: FSUB2B
+ port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r2, B0=>rptr_1,
+ B1=>rptr_2, BI=>co0_3, BOUT=>co1_3, S0=>rfill_sub_1,
+ S1=>rfill_sub_2);
+
+ rfill_2: FSUB2B
+ port map (A0=>wcount_r3, A1=>rfill_sub_msb, B0=>rptr_3,
+ B1=>scuba_vlo, BI=>co1_3, BOUT=>co2_3, S0=>rfill_sub_3,
+ S1=>rfill_sub_4);
+
+ rfilld: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co2_3, COUT=>open, S0=>co2_3d, S1=>open);
+
+ empty_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
+ CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
+
+ empty_cmp_0: AGEB2
+ port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0,
+ B1=>w_g2b_xor_cluster_0, CI=>cmp_ci, GE=>co0_4);
+
+ empty_cmp_1: AGEB2
+ port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2,
+ B1=>wcount_r3, CI=>co0_4, GE=>co1_4);
+
+ empty_cmp_2: AGEB2
+ port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr,
+ B1=>scuba_vlo, CI=>co1_4, GE=>empty_d_c);
+
+ a0: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
+ S1=>open);
+
+ full_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
+ CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
+
+ full_cmp_0: AGEB2
+ port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0,
+ B1=>r_g2b_xor_cluster_0, CI=>cmp_ci_1, GE=>co0_5);
+
+ full_cmp_1: AGEB2
+ port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2,
+ B1=>rcount_w3, CI=>co0_5, GE=>co1_5);
+
+ full_cmp_2: AGEB2
+ port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr,
+ B1=>scuba_vlo, CI=>co1_5, GE=>full_d_c);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a1: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
+ S1=>open);
+
+ fifo_pfu_0_0: DPR16X4A
+ port map (DI0=>Data(92), DI1=>Data(93), DI2=>Data(94),
+ DI3=>Data(95), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0,
+ RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0,
+ WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout92,
+ DO1=>rdataout93, DO2=>rdataout94, DO3=>rdataout95);
+
+ fifo_pfu_0_1: DPR16X4A
+ port map (DI0=>Data(88), DI1=>Data(89), DI2=>Data(90),
+ DI3=>Data(91), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0,
+ RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0,
+ WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout88,
+ DO1=>rdataout89, DO2=>rdataout90, DO3=>rdataout91);
+
+ fifo_pfu_0_2: DPR16X4A
+ port map (DI0=>Data(84), DI1=>Data(85), DI2=>Data(86),
+ DI3=>Data(87), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0,
+ RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0,
+ WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout84,
+ DO1=>rdataout85, DO2=>rdataout86, DO3=>rdataout87);
+
+ fifo_pfu_0_3: DPR16X4A
+ port map (DI0=>Data(80), DI1=>Data(81), DI2=>Data(82),
+ DI3=>Data(83), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0,
+ RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0,
+ WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout80,
+ DO1=>rdataout81, DO2=>rdataout82, DO3=>rdataout83);
+
+ fifo_pfu_0_4: DPR16X4A
+ port map (DI0=>Data(76), DI1=>Data(77), DI2=>Data(78),
+ DI3=>Data(79), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0,
+ RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0,
+ WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout76,
+ DO1=>rdataout77, DO2=>rdataout78, DO3=>rdataout79);
+
+ fifo_pfu_0_5: DPR16X4A
+ port map (DI0=>Data(72), DI1=>Data(73), DI2=>Data(74),
+ DI3=>Data(75), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0,
+ RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0,
+ WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout72,
+ DO1=>rdataout73, DO2=>rdataout74, DO3=>rdataout75);
+
+ fifo_pfu_0_6: DPR16X4A
+ port map (DI0=>Data(68), DI1=>Data(69), DI2=>Data(70),
+ DI3=>Data(71), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0,
+ RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0,
+ WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout68,
+ DO1=>rdataout69, DO2=>rdataout70, DO3=>rdataout71);
+
+ fifo_pfu_0_7: DPR16X4A
+ port map (DI0=>Data(64), DI1=>Data(65), DI2=>Data(66),
+ DI3=>Data(67), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0,
+ RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0,
+ WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout64,
+ DO1=>rdataout65, DO2=>rdataout66, DO3=>rdataout67);
+
+ fifo_pfu_0_8: DPR16X4A
+ port map (DI0=>Data(60), DI1=>Data(61), DI2=>Data(62),
+ DI3=>Data(63), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0,
+ RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0,
+ WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout60,
+ DO1=>rdataout61, DO2=>rdataout62, DO3=>rdataout63);
+
+ fifo_pfu_0_9: DPR16X4A
+ port map (DI0=>Data(56), DI1=>Data(57), DI2=>Data(58),
+ DI3=>Data(59), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0,
+ RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0,
+ WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout56,
+ DO1=>rdataout57, DO2=>rdataout58, DO3=>rdataout59);
+
+ fifo_pfu_0_10: DPR16X4A
+ port map (DI0=>Data(52), DI1=>Data(53), DI2=>Data(54),
+ DI3=>Data(55), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0,
+ RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0,
+ WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout52,
+ DO1=>rdataout53, DO2=>rdataout54, DO3=>rdataout55);
+
+ fifo_pfu_0_11: DPR16X4A
+ port map (DI0=>Data(48), DI1=>Data(49), DI2=>Data(50),
+ DI3=>Data(51), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0,
+ RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0,
+ WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout48,
+ DO1=>rdataout49, DO2=>rdataout50, DO3=>rdataout51);
+
+ fifo_pfu_0_12: DPR16X4A
+ port map (DI0=>Data(44), DI1=>Data(45), DI2=>Data(46),
+ DI3=>Data(47), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0,
+ RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0,
+ WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout44,
+ DO1=>rdataout45, DO2=>rdataout46, DO3=>rdataout47);
+
+ fifo_pfu_0_13: DPR16X4A
+ port map (DI0=>Data(40), DI1=>Data(41), DI2=>Data(42),
+ DI3=>Data(43), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0,
+ RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0,
+ WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout40,
+ DO1=>rdataout41, DO2=>rdataout42, DO3=>rdataout43);
+
+ fifo_pfu_0_14: DPR16X4A
+ port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38),
+ DI3=>Data(39), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0,
+ RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0,
+ WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout36,
+ DO1=>rdataout37, DO2=>rdataout38, DO3=>rdataout39);
+
+ fifo_pfu_0_15: DPR16X4A
+ port map (DI0=>Data(32), DI1=>Data(33), DI2=>Data(34),
+ DI3=>Data(35), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0,
+ RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0,
+ WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout32,
+ DO1=>rdataout33, DO2=>rdataout34, DO3=>rdataout35);
+
+ fifo_pfu_0_16: DPR16X4A
+ port map (DI0=>Data(28), DI1=>Data(29), DI2=>Data(30),
+ DI3=>Data(31), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0,
+ RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0,
+ WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout28,
+ DO1=>rdataout29, DO2=>rdataout30, DO3=>rdataout31);
+
+ fifo_pfu_0_17: DPR16X4A
+ port map (DI0=>Data(24), DI1=>Data(25), DI2=>Data(26),
+ DI3=>Data(27), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0,
+ RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0,
+ WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout24,
+ DO1=>rdataout25, DO2=>rdataout26, DO3=>rdataout27);
+
+ fifo_pfu_0_18: DPR16X4A
+ port map (DI0=>Data(20), DI1=>Data(21), DI2=>Data(22),
+ DI3=>Data(23), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0,
+ RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0,
+ WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout20,
+ DO1=>rdataout21, DO2=>rdataout22, DO3=>rdataout23);
+
+ fifo_pfu_0_19: DPR16X4A
+ port map (DI0=>Data(16), DI1=>Data(17), DI2=>Data(18),
+ DI3=>Data(19), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0,
+ RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0,
+ WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout16,
+ DO1=>rdataout17, DO2=>rdataout18, DO3=>rdataout19);
+
+ fifo_pfu_0_20: DPR16X4A
+ port map (DI0=>Data(12), DI1=>Data(13), DI2=>Data(14),
+ DI3=>Data(15), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0,
+ RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0,
+ WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout12,
+ DO1=>rdataout13, DO2=>rdataout14, DO3=>rdataout15);
+
+ fifo_pfu_0_21: DPR16X4A
+ port map (DI0=>Data(8), DI1=>Data(9), DI2=>Data(10),
+ DI3=>Data(11), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0,
+ RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0,
+ WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout8,
+ DO1=>rdataout9, DO2=>rdataout10, DO3=>rdataout11);
+
+ fifo_pfu_0_22: DPR16X4A
+ port map (DI0=>Data(4), DI1=>Data(5), DI2=>Data(6), DI3=>Data(7),
+ WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, RAD1=>rptr_1,
+ RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, WAD1=>wptr_1,
+ WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout4, DO1=>rdataout5,
+ DO2=>rdataout6, DO3=>rdataout7);
+
+ fifo_pfu_0_23: DPR16X4A
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, RAD1=>rptr_1,
+ RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, WAD1=>wptr_1,
+ WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout0, DO1=>rdataout1,
+ DO2=>rdataout2, DO3=>rdataout3);
+
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of crossover is
+ for Structure
+ for all:AGEB2 use entity ecp2m.AGEB2(V); end for;
+ for all:AND2 use entity ecp2m.AND2(V); end for;
+ for all:CU2 use entity ecp2m.CU2(V); end for;
+ for all:FADD2B use entity ecp2m.FADD2B(V); end for;
+ for all:FSUB2B use entity ecp2m.FSUB2B(V); end for;
+ for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for;
+ for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
+ for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for;
+ for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for;
+ for all:INV use entity ecp2m.INV(V); end for;
+ for all:OR2 use entity ecp2m.OR2(V); end for;
+ for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for;
+ for all:DPR16X4A use entity ecp2m.DPR16X4A(V); end for;
+ for all:VHI use entity ecp2m.VHI(V); end for;
+ for all:VLO use entity ecp2m.VLO(V); end for;
+ for all:XOR2 use entity ecp2m.XOR2(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+Starting process: \r
+\r
+SCUBA, Version ispLever_v72_PROD_Build (44)\r
+Fri Nov 20 11:16:48 2009\r
+\r
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
+Copyright (c) 1995 AT&T Corp. All rights reserved.\r
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
+Copyright (c) 2001 Agere Systems All rights reserved.\r
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
+\r
+BEGIN SCUBA Module Synthesis\r
+\r
+ Issued command : F:\Programme\ispTOOLS7_2\ispfpga\bin\nt\scuba.exe -w -n crossover -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -pfu_fifo -addr_width 4 -data_width 96 -num_words 16 -rdata_width 96 -no_enable -pe -1 -pf -1 -rfill -fill -e \r
+ Circuit name : crossover\r
+ Module type : ebfifo\r
+ Module Version : 5.0\r
+ Ports : \r
+ Inputs : Data[95:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset\r
+ Outputs : Q[95:0], WCNT[4:0], RCNT[4:0], Empty, Full\r
+ I/O buffer : not inserted\r
+ EDIF output : suppressed\r
+ VHDL output : crossover.vhd\r
+ VHDL template : crossover_tmpl.vhd\r
+ VHDL testbench : tb_crossover_tmpl.vhd\r
+ VHDL purpose : for synthesis and simulation\r
+ Bus notation : big endian\r
+ Report output : crossover.srp\r
+ Estimated Resource Usage:\r
+ LUT : 78\r
+ DRAM : 24\r
+ Reg : 158\r
+\r
+END SCUBA Module Synthesis\r
+\r
+File: ..\src\crossover.lpc created.\r
+\r
+\r
+End process: completed successfully.\r
+\r
+\r
+Total Warnings: 0\r
+\r
+Total Errors: 0\r
+\r
+\r
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_PROD_Build (44)
+-- Module Version: 5.0
+-- Fri Nov 20 11:16:48 2009
+
+-- parameterized module component declaration
+component crossover
+ port (Data: in std_logic_vector(95 downto 0);
+ WrClock: in std_logic; RdClock: in std_logic;
+ WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic;
+ RPReset: in std_logic; Q: out std_logic_vector(95 downto 0);
+ WCNT: out std_logic_vector(4 downto 0);
+ RCNT: out std_logic_vector(4 downto 0); Empty: out std_logic;
+ Full: out std_logic);
+end component;
+
+-- parameterized module component instance
+__ : crossover
+ port map (Data(95 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__,
+ RdEn=>__, Reset=>__, RPReset=>__, Q(95 downto 0)=>__, WCNT(4 downto 0)=>__,
+ RCNT(4 downto 0)=>__, Empty=>__, Full=>__);
--- /dev/null
+[Device]\r
+Family=latticeecp2m\r
+PartType=LFE2M100E\r
+PartName=LFE2M100E-6F900C\r
+SpeedGrade=-6\r
+Package=FPBGA900\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=Distributed_ROM\r
+CoreRevision=2.4\r
+ModuleName=decoder_8bit\r
+SourceFormat=VHDL\r
+ParameterFileVersion=1.0\r
+Date=03/03/2009\r
+Time=09:38:59\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+Addresses=256\r
+Data=4\r
+LUT=0\r
+MemFile=z:/vhdl_pro/adcm_v2/decoder_8bit.mem\r
+MemFormat=orca\r
--- /dev/null
+#Format=AddrHex
+#Depth=256
+#Width=4
+#AddrRadix=3
+#DataRadix=3
+#Data
+00: 0 1 1 2 1 2 2 3
+08: 1 2 2 3 2 3 3 4
+10: 1 2 2 3 2 3 3 4
+18: 2 3 3 4 3 4 4 5
+20: 1 2 2 3 2 3 3 4
+28: 2 3 3 4 3 4 4 5
+30: 2 3 3 4 3 4 4 5
+38: 3 4 4 5 4 5 5 6
+40: 1 2 2 3 2 3 3 4
+48: 2 3 3 4 3 4 4 5
+50: 2 3 3 4 3 4 4 5
+58: 3 4 4 5 4 5 5 6
+60: 2 3 3 4 3 4 4 5
+68: 3 4 4 5 4 5 5 6
+70: 3 4 4 5 4 5 5 6
+78: 4 5 5 6 5 6 6 7
+80: 1 2 2 3 2 3 3 4
+88: 2 3 3 4 3 4 4 5
+90: 2 3 3 4 3 4 4 5
+98: 3 4 4 5 4 5 5 6
+a0: 2 3 3 4 3 4 4 5
+a8: 3 4 4 5 4 5 5 6
+b0: 3 4 4 5 4 5 5 6
+b8: 4 5 5 6 5 6 6 7
+c0: 2 3 3 4 3 4 4 5
+c8: 3 4 4 5 4 5 5 6
+d0: 3 4 4 5 4 5 5 6
+d8: 4 5 5 6 5 6 6 7
+e0: 3 4 4 5 4 5 5 6
+e8: 4 5 5 6 5 6 6 7
+f0: 4 5 5 6 5 6 6 7
+f8: 5 6 6 7 6 7 7 8
\ No newline at end of file
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v72_SP1_Build (24)
+-- Module Version: 2.4
+--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type rom -addr_width 8 -num_rows 256 -data_width 4 -outdata UNREGISTERED -memfile z:/vhdl_pro/adcm_v2/decoder_8bit.mem -memformat orca -e
+
+-- Tue Mar 03 09:38:59 2009
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity decoder_8bit is
+ port (
+ Address: in std_logic_vector(7 downto 0);
+ Q: out std_logic_vector(3 downto 0));
+end decoder_8bit;
+
+architecture Structure of decoder_8bit is
+
+ -- local component declarations
+ component ROM256X1
+ -- synopsys translate_off
+ generic (INITVAL : in String);
+ -- synopsys translate_on
+ port (AD7: in std_logic; AD6: in std_logic; AD5: in std_logic;
+ AD4: in std_logic; AD3: in std_logic; AD2: in std_logic;
+ AD1: in std_logic; AD0: in std_logic; DO0: out std_logic);
+ end component;
+ attribute initval : string;
+ attribute initval of mem_0_3 : label is "0x8000000000000000000000000000000000000000000000000000000000000000";
+ attribute initval of mem_0_2 : label is "0x7FFFFFFEFFFEFEE8FFFEFEE8FEE8E880FFFEFEE8FEE8E880FEE8E880E8808000";
+ attribute initval of mem_0_1 : label is "0x7EE8E881E8818117E88181178117177EE88181178117177E8117177E177E7EE8";
+ attribute initval of mem_0_0 : label is "0x6996966996696996966969966996966996696996699696696996966996696996";
+
+begin
+ -- component instantiation statements
+ mem_0_3: ROM256X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000000000000000000000000000000000000000000000000000000000000000")
+ -- synopsys translate_on
+ port map (AD7=>Address(7), AD6=>Address(6), AD5=>Address(5),
+ AD4=>Address(4), AD3=>Address(3), AD2=>Address(2),
+ AD1=>Address(1), AD0=>Address(0), DO0=>Q(3));
+
+ mem_0_2: ROM256X1
+ -- synopsys translate_off
+ generic map (initval=> "0x7FFFFFFEFFFEFEE8FFFEFEE8FEE8E880FFFEFEE8FEE8E880FEE8E880E8808000")
+ -- synopsys translate_on
+ port map (AD7=>Address(7), AD6=>Address(6), AD5=>Address(5),
+ AD4=>Address(4), AD3=>Address(3), AD2=>Address(2),
+ AD1=>Address(1), AD0=>Address(0), DO0=>Q(2));
+
+ mem_0_1: ROM256X1
+ -- synopsys translate_off
+ generic map (initval=> "0x7EE8E881E8818117E88181178117177EE88181178117177E8117177E177E7EE8")
+ -- synopsys translate_on
+ port map (AD7=>Address(7), AD6=>Address(6), AD5=>Address(5),
+ AD4=>Address(4), AD3=>Address(3), AD2=>Address(2),
+ AD1=>Address(1), AD0=>Address(0), DO0=>Q(1));
+
+ mem_0_0: ROM256X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996966996696996966969966996966996696996699696696996966996696996")
+ -- synopsys translate_on
+ port map (AD7=>Address(7), AD6=>Address(6), AD5=>Address(5),
+ AD4=>Address(4), AD3=>Address(3), AD2=>Address(2),
+ AD1=>Address(1), AD0=>Address(0), DO0=>Q(0));
+
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of decoder_8bit is
+ for Structure
+ for all:ROM256X1 use entity ecp2m.ROM256X1(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_SP1_Build (24)
+-- Module Version: 2.4
+-- Tue Mar 03 09:38:59 2009
+
+-- parameterized module component declaration
+component decoder_8bit
+ port (Address: in std_logic_vector(7 downto 0);
+ Q: out std_logic_vector(3 downto 0));
+end component;
+
+-- parameterized module component instance
+__ : decoder_8bit
+ port map (Address(7 downto 0)=>__, Q(3 downto 0)=>__);
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.std_logic_arith.all;\r
+use ieee.std_logic_unsigned.all;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+entity dhdr_buf is\r
+ port( CLK_IN : in std_logic; -- 100MHz master clock\r
+ RESET_IN : in std_logic; \r
+ -- DHDR information block\r
+ DHDR_DATA_IN : in std_logic_vector(47 downto 0); -- EDS data input\r
+ DHDR_WE_IN : in std_logic; -- EDS write enable\r
+ DHDR_DONE_IN : in std_logic; -- release EDS \r
+ DHDR_DATA_OUT : out std_logic_vector(47 downto 0);\r
+ DHDR_AVAILABLE_OUT : out std_logic;\r
+ -- trigger busy information\r
+ BUF_FULL_OUT : out std_logic;\r
+ BUF_LEVEL_OUT : out std_logic_vector(4 downto 0);\r
+ -- Debug signals\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
+end;\r
+\r
+architecture behavioral of dhdr_buf is\r
+\r
+ -- normal signals\r
+ signal debug : std_logic_vector(15 downto 0);\r
+\r
+ -- Signals for controlling the DHDR buffer memory\r
+ signal dhdr_data : std_logic_vector(47 downto 0);\r
+ signal dhdr_rd_addr : std_logic_vector(3 downto 0);\r
+ signal dhdr_wr_addr : std_logic_vector(3 downto 0);\r
+ signal dhdr_wr : std_logic;\r
+ signal dhdr_rd : std_logic;\r
+ signal dhdr_free_ctr : std_logic_vector(4 downto 0); -- fill level counter\r
+ signal dhdr_free_up : std_logic;\r
+ signal dhdr_free_down : std_logic;\r
+ signal dhdr_available_x : std_logic; \r
+ signal dhdr_available : std_logic; -- at least one valid EDS entry is available\r
+ signal dhdr_full_x : std_logic;\r
+ signal dhdr_full : std_logic;\r
+ \r
+begin\r
+\r
+-- General process for syncing combinatorial signals\r
+THE_SYNC_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ dhdr_available <= dhdr_available_x;\r
+ dhdr_full <= dhdr_full_x;\r
+ end if;\r
+end process THE_SYNC_PROC;\r
+\r
+-- Write address pointer for EDS buffer\r
+dhdr_wr <= dhdr_we_in;\r
+\r
+THE_WR_ADDR_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( reset_in = '1' ) then\r
+ dhdr_wr_addr <= (others => '0');\r
+ elsif( dhdr_wr = '1' ) then\r
+ dhdr_wr_addr <= dhdr_wr_addr + 1;\r
+ end if;\r
+ end if;\r
+end process THE_WR_ADDR_PROC;\r
+\r
+-- Read address pointer for EDS buffer\r
+dhdr_rd <= dhdr_done_in;\r
+\r
+THE_RD_ADDR_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( reset_in = '1' ) then\r
+ dhdr_rd_addr <= (others => '0');\r
+ elsif( dhdr_rd = '1' ) then\r
+ dhdr_rd_addr <= dhdr_rd_addr + 1;\r
+ end if;\r
+ end if;\r
+end process THE_RD_ADDR_PROC;\r
+\r
+-- Buffer fill level counter\r
+dhdr_free_down <= dhdr_we_in;\r
+dhdr_free_up <= dhdr_done_in;\r
+\r
+THE_DHDR_FREE_COUNTER_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( reset_in = '1' ) then\r
+ dhdr_free_ctr <= "10000";\r
+ elsif( (dhdr_free_down = '1') and (dhdr_free_up = '0') ) then\r
+ dhdr_free_ctr <= dhdr_free_ctr - 1; \r
+ elsif( (dhdr_free_down = '0') and (dhdr_free_up = '1') ) then\r
+ dhdr_free_ctr <= dhdr_free_ctr + 1;\r
+ end if;\r
+ end if;\r
+end process THE_DHDR_FREE_COUNTER_PROC;\r
+\r
+dhdr_full_x <= '1' when (dhdr_free_ctr = "00000") else '0';\r
+\r
+-- A 16x32b DPRAM is used for buffering the DataHeaDeR (DHDR)\r
+THE_DHDR_BUFFER: dhdr_buffer_dpram\r
+port map( WRADDRESS => dhdr_wr_addr,\r
+ DATA => dhdr_data_in,\r
+ WRCLOCK => clk_in, \r
+ WE => dhdr_we_in, \r
+ WRCLOCKEN => '1', \r
+ RDADDRESS => dhdr_rd_addr, \r
+ RDCLOCK => clk_in, \r
+ RDCLOCKEN => '1', \r
+ RESET => reset_in, \r
+ Q => dhdr_data\r
+ );\r
+\r
+-- Are there any EDS to work on?\r
+dhdr_available_x <= '1' when (dhdr_wr_addr /= dhdr_rd_addr) else '0';\r
+\r
+-- Debug signals\r
+debug(15 downto 0) <= (others => '0');\r
+\r
+-- Output signals\r
+dhdr_data_out <= dhdr_data;\r
+dhdr_available_out <= dhdr_available;\r
+buf_full_out <= dhdr_full;\r
+buf_level_out <= dhdr_free_ctr;\r
+debug_out <= debug;\r
+\r
+end behavioral;\r
--- /dev/null
+[Device]\r
+Family=latticeecp2m\r
+PartType=LFE2M100E\r
+PartName=LFE2M100E-6F900C\r
+SpeedGrade=-6\r
+Package=FPBGA900\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=Distributed_DPRAM\r
+CoreRevision=3.4\r
+ModuleName=dhdr_buffer_dpram\r
+SourceFormat=VHDL\r
+ParameterFileVersion=1.0\r
+Date=03/03/2009\r
+Time=16:49:44\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+Addresses=16\r
+Data=48\r
+LUT=1\r
+MemFile=\r
+MemFormat=orca\r
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v72_SP1_Build (24)
+-- Module Version: 3.4
+--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type sdpram -rdata_width 48 -data_width 48 -num_rows 16 -outData REGISTERED -e
+
+-- Tue Mar 03 16:49:44 2009
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity dhdr_buffer_dpram is
+ port (
+ WrAddress: in std_logic_vector(3 downto 0);
+ Data: in std_logic_vector(47 downto 0);
+ WrClock: in std_logic;
+ WE: in std_logic;
+ WrClockEn: in std_logic;
+ RdAddress: in std_logic_vector(3 downto 0);
+ RdClock: in std_logic;
+ RdClockEn: in std_logic;
+ Reset: in std_logic;
+ Q: out std_logic_vector(47 downto 0));
+end dhdr_buffer_dpram;
+
+architecture Structure of dhdr_buffer_dpram is
+
+ -- internal signal declarations
+ signal scuba_vlo: std_logic;
+ signal scuba_vhi: std_logic;
+ signal dataout47_ffin: std_logic;
+ signal dataout46_ffin: std_logic;
+ signal dataout45_ffin: std_logic;
+ signal dataout44_ffin: std_logic;
+ signal dataout43_ffin: std_logic;
+ signal dataout42_ffin: std_logic;
+ signal dataout41_ffin: std_logic;
+ signal dataout40_ffin: std_logic;
+ signal dataout39_ffin: std_logic;
+ signal dataout38_ffin: std_logic;
+ signal dataout37_ffin: std_logic;
+ signal dataout36_ffin: std_logic;
+ signal dataout35_ffin: std_logic;
+ signal dataout34_ffin: std_logic;
+ signal dataout33_ffin: std_logic;
+ signal dataout32_ffin: std_logic;
+ signal dataout31_ffin: std_logic;
+ signal dataout30_ffin: std_logic;
+ signal dataout29_ffin: std_logic;
+ signal dataout28_ffin: std_logic;
+ signal dataout27_ffin: std_logic;
+ signal dataout26_ffin: std_logic;
+ signal dataout25_ffin: std_logic;
+ signal dataout24_ffin: std_logic;
+ signal dataout23_ffin: std_logic;
+ signal dataout22_ffin: std_logic;
+ signal dataout21_ffin: std_logic;
+ signal dataout20_ffin: std_logic;
+ signal dataout19_ffin: std_logic;
+ signal dataout18_ffin: std_logic;
+ signal dataout17_ffin: std_logic;
+ signal dataout16_ffin: std_logic;
+ signal dataout15_ffin: std_logic;
+ signal dataout14_ffin: std_logic;
+ signal dataout13_ffin: std_logic;
+ signal dataout12_ffin: std_logic;
+ signal dataout11_ffin: std_logic;
+ signal dataout10_ffin: std_logic;
+ signal dataout9_ffin: std_logic;
+ signal dataout8_ffin: std_logic;
+ signal dataout7_ffin: std_logic;
+ signal dataout6_ffin: std_logic;
+ signal dataout5_ffin: std_logic;
+ signal dataout4_ffin: std_logic;
+ signal dataout3_ffin: std_logic;
+ signal dataout2_ffin: std_logic;
+ signal dataout1_ffin: std_logic;
+ signal dataout0_ffin: std_logic;
+ signal dec0_wre3: std_logic;
+
+ -- local component declarations
+ component FD1P3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component ROM16X1
+ -- synopsys translate_off
+ generic (initval : in String);
+ -- synopsys translate_on
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component DPR16X4A
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; WCK: in std_logic; WRE: in std_logic;
+ RAD0: in std_logic; RAD1: in std_logic;
+ RAD2: in std_logic; RAD3: in std_logic;
+ WAD0: in std_logic; WAD1: in std_logic;
+ WAD2: in std_logic; WAD3: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ attribute initval : string;
+ attribute GSR : string;
+ attribute initval of LUT4_0 : label is "0x8000";
+ attribute GSR of FF_47 : label is "ENABLED";
+ attribute GSR of FF_46 : label is "ENABLED";
+ attribute GSR of FF_45 : label is "ENABLED";
+ attribute GSR of FF_44 : label is "ENABLED";
+ attribute GSR of FF_43 : label is "ENABLED";
+ attribute GSR of FF_42 : label is "ENABLED";
+ attribute GSR of FF_41 : label is "ENABLED";
+ attribute GSR of FF_40 : label is "ENABLED";
+ attribute GSR of FF_39 : label is "ENABLED";
+ attribute GSR of FF_38 : label is "ENABLED";
+ attribute GSR of FF_37 : label is "ENABLED";
+ attribute GSR of FF_36 : label is "ENABLED";
+ attribute GSR of FF_35 : label is "ENABLED";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+
+begin
+ -- component instantiation statements
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ LUT4_0: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>WE, AD2=>WrClockEn, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec0_wre3);
+
+ FF_47: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout47_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(47));
+
+ FF_46: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout46_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(46));
+
+ FF_45: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout45_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(45));
+
+ FF_44: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout44_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(44));
+
+ FF_43: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout43_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(43));
+
+ FF_42: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout42_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(42));
+
+ FF_41: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout41_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(41));
+
+ FF_40: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout40_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(40));
+
+ FF_39: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout39_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(39));
+
+ FF_38: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout38_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(38));
+
+ FF_37: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout37_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(37));
+
+ FF_36: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout36_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(36));
+
+ FF_35: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout35_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(35));
+
+ FF_34: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout34_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(34));
+
+ FF_33: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout33_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(33));
+
+ FF_32: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout32_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(32));
+
+ FF_31: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout31_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(31));
+
+ FF_30: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout30_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(30));
+
+ FF_29: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout29_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(29));
+
+ FF_28: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout28_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(28));
+
+ FF_27: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout27_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(27));
+
+ FF_26: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout26_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(26));
+
+ FF_25: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout25_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(25));
+
+ FF_24: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout24_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(24));
+
+ FF_23: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout23_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(23));
+
+ FF_22: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout22_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(22));
+
+ FF_21: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout21_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(21));
+
+ FF_20: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout20_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(20));
+
+ FF_19: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout19_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(19));
+
+ FF_18: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout18_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(18));
+
+ FF_17: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout17_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(17));
+
+ FF_16: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout16_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(16));
+
+ FF_15: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout15_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(15));
+
+ FF_14: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout14_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(14));
+
+ FF_13: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout13_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(13));
+
+ FF_12: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout12_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(12));
+
+ FF_11: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout11_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(11));
+
+ FF_10: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout10_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(10));
+
+ FF_9: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout9_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(9));
+
+ FF_8: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout8_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(8));
+
+ FF_7: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout7_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(7));
+
+ FF_6: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout6_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(6));
+
+ FF_5: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout5_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(5));
+
+ FF_4: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout4_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(4));
+
+ FF_3: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout3_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(3));
+
+ FF_2: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout2_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(2));
+
+ FF_1: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout1_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(1));
+
+ FF_0: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout0_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(0));
+
+ mem_0_0: DPR16X4A
+ port map (DI0=>Data(44), DI1=>Data(45), DI2=>Data(46),
+ DI3=>Data(47), WCK=>WrClock, WRE=>dec0_wre3,
+ RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2),
+ RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1),
+ WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout44_ffin,
+ DO1=>dataout45_ffin, DO2=>dataout46_ffin,
+ DO3=>dataout47_ffin);
+
+ mem_0_1: DPR16X4A
+ port map (DI0=>Data(40), DI1=>Data(41), DI2=>Data(42),
+ DI3=>Data(43), WCK=>WrClock, WRE=>dec0_wre3,
+ RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2),
+ RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1),
+ WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout40_ffin,
+ DO1=>dataout41_ffin, DO2=>dataout42_ffin,
+ DO3=>dataout43_ffin);
+
+ mem_0_2: DPR16X4A
+ port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38),
+ DI3=>Data(39), WCK=>WrClock, WRE=>dec0_wre3,
+ RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2),
+ RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1),
+ WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout36_ffin,
+ DO1=>dataout37_ffin, DO2=>dataout38_ffin,
+ DO3=>dataout39_ffin);
+
+ mem_0_3: DPR16X4A
+ port map (DI0=>Data(32), DI1=>Data(33), DI2=>Data(34),
+ DI3=>Data(35), WCK=>WrClock, WRE=>dec0_wre3,
+ RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2),
+ RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1),
+ WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout32_ffin,
+ DO1=>dataout33_ffin, DO2=>dataout34_ffin,
+ DO3=>dataout35_ffin);
+
+ mem_0_4: DPR16X4A
+ port map (DI0=>Data(28), DI1=>Data(29), DI2=>Data(30),
+ DI3=>Data(31), WCK=>WrClock, WRE=>dec0_wre3,
+ RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2),
+ RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1),
+ WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout28_ffin,
+ DO1=>dataout29_ffin, DO2=>dataout30_ffin,
+ DO3=>dataout31_ffin);
+
+ mem_0_5: DPR16X4A
+ port map (DI0=>Data(24), DI1=>Data(25), DI2=>Data(26),
+ DI3=>Data(27), WCK=>WrClock, WRE=>dec0_wre3,
+ RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2),
+ RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1),
+ WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout24_ffin,
+ DO1=>dataout25_ffin, DO2=>dataout26_ffin,
+ DO3=>dataout27_ffin);
+
+ mem_0_6: DPR16X4A
+ port map (DI0=>Data(20), DI1=>Data(21), DI2=>Data(22),
+ DI3=>Data(23), WCK=>WrClock, WRE=>dec0_wre3,
+ RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2),
+ RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1),
+ WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout20_ffin,
+ DO1=>dataout21_ffin, DO2=>dataout22_ffin,
+ DO3=>dataout23_ffin);
+
+ mem_0_7: DPR16X4A
+ port map (DI0=>Data(16), DI1=>Data(17), DI2=>Data(18),
+ DI3=>Data(19), WCK=>WrClock, WRE=>dec0_wre3,
+ RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2),
+ RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1),
+ WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout16_ffin,
+ DO1=>dataout17_ffin, DO2=>dataout18_ffin,
+ DO3=>dataout19_ffin);
+
+ mem_0_8: DPR16X4A
+ port map (DI0=>Data(12), DI1=>Data(13), DI2=>Data(14),
+ DI3=>Data(15), WCK=>WrClock, WRE=>dec0_wre3,
+ RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2),
+ RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1),
+ WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout12_ffin,
+ DO1=>dataout13_ffin, DO2=>dataout14_ffin,
+ DO3=>dataout15_ffin);
+
+ mem_0_9: DPR16X4A
+ port map (DI0=>Data(8), DI1=>Data(9), DI2=>Data(10),
+ DI3=>Data(11), WCK=>WrClock, WRE=>dec0_wre3,
+ RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2),
+ RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1),
+ WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout8_ffin,
+ DO1=>dataout9_ffin, DO2=>dataout10_ffin, DO3=>dataout11_ffin);
+
+ mem_0_10: DPR16X4A
+ port map (DI0=>Data(4), DI1=>Data(5), DI2=>Data(6), DI3=>Data(7),
+ WCK=>WrClock, WRE=>dec0_wre3, RAD0=>RdAddress(0),
+ RAD1=>RdAddress(1), RAD2=>RdAddress(2), RAD3=>RdAddress(3),
+ WAD0=>WrAddress(0), WAD1=>WrAddress(1), WAD2=>WrAddress(2),
+ WAD3=>WrAddress(3), DO0=>dataout4_ffin, DO1=>dataout5_ffin,
+ DO2=>dataout6_ffin, DO3=>dataout7_ffin);
+
+ mem_0_11: DPR16X4A
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ WCK=>WrClock, WRE=>dec0_wre3, RAD0=>RdAddress(0),
+ RAD1=>RdAddress(1), RAD2=>RdAddress(2), RAD3=>RdAddress(3),
+ WAD0=>WrAddress(0), WAD1=>WrAddress(1), WAD2=>WrAddress(2),
+ WAD3=>WrAddress(3), DO0=>dataout0_ffin, DO1=>dataout1_ffin,
+ DO2=>dataout2_ffin, DO3=>dataout3_ffin);
+
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of dhdr_buffer_dpram is
+ for Structure
+ for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
+ for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for;
+ for all:DPR16X4A use entity ecp2m.DPR16X4A(V); end for;
+ for all:VHI use entity ecp2m.VHI(V); end for;
+ for all:VLO use entity ecp2m.VLO(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_SP1_Build (24)
+-- Module Version: 3.4
+-- Tue Mar 03 16:49:44 2009
+
+-- parameterized module component declaration
+component dhdr_buffer_dpram
+ port (WrAddress: in std_logic_vector(3 downto 0);
+ Data: in std_logic_vector(47 downto 0); WrClock: in std_logic;
+ WE: in std_logic; WrClockEn: in std_logic;
+ RdAddress: in std_logic_vector(3 downto 0);
+ RdClock: in std_logic; RdClockEn: in std_logic;
+ Reset: in std_logic; Q: out std_logic_vector(47 downto 0));
+end component;
+
+-- parameterized module component instance
+__ : dhdr_buffer_dpram
+ port map (WrAddress(3 downto 0)=>__, Data(47 downto 0)=>__, WrClock=>__,
+ WE=>__, WrClockEn=>__, RdAddress(3 downto 0)=>__, RdClock=>__,
+ RdClockEn=>__, Reset=>__, Q(47 downto 0)=>__);
--- /dev/null
+[Device]\r
+Family=latticeecp2m\r
+PartType=LFE2M100E\r
+PartName=LFE2M100E-6F900C\r
+SpeedGrade=-6\r
+Package=FPBGA900\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=DLL\r
+CoreRevision=3.2\r
+ModuleName=dll_100m\r
+SourceFormat=VHDL\r
+ParameterFileVersion=1.0\r
+Date=01/29/2009\r
+Time=18:49:16\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+dlltype=Clock Injection Delay Removal\r
+fin=100\r
+clkos_div=1\r
+clkos_ph=0\r
+Mode=CLKOP\r
+Freq=CLKI\r
+Smiports=0\r
+RSTNport=1\r
+reset_en=0\r
+DCNTL=0\r
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v72_PROD_Build (44)
+-- Module Version: 3.2
+--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n dll_100m -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type dll -dll_type cid -fin 100 -clkos_div 1 -fb_mode 0 -use_rstn -e
+
+-- Thu Jan 29 18:49:16 2009
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity dll_100m is
+ port (
+ clk: in std_logic;
+ resetn: in std_logic;
+ aluhold: in std_logic;
+ clkop: out std_logic;
+ clkos: out std_logic;
+ lock: out std_logic);
+ attribute dont_touch : string;
+ attribute dont_touch of dll_100m : entity is "true";
+end dll_100m;
+
+architecture Structure of dll_100m is
+
+ -- internal signal declarations
+ signal scuba_vlo: std_logic;
+ signal clkos_t: std_logic;
+ signal clkop_t: std_logic;
+ signal clk_t: std_logic;
+
+ -- local component declarations
+ component CIDDLLA
+ -- synopsys translate_off
+ generic (ALU_INIT_CNTVAL : in Integer;
+ ALU_UNLOCK_CNT : in Integer; ALU_LOCK_CNT : in Integer;
+ GSR : in String; CLKOS_DIV : in Integer;
+ CLKI_DIV : in Integer; CLKOS_FPHASE : in Integer;
+ CLKOS_PHASE : in Integer; CLKOP_PHASE : in Integer);
+ -- synopsys translate_on
+ port (CLKI: in std_logic; CLKFB: in std_logic;
+ RSTN: in std_logic; ALUHOLD: in std_logic;
+ SMIADDR9: in std_logic; SMIADDR8: in std_logic;
+ SMIADDR7: in std_logic; SMIADDR6: in std_logic;
+ SMIADDR5: in std_logic; SMIADDR4: in std_logic;
+ SMIADDR3: in std_logic; SMIADDR2: in std_logic;
+ SMIADDR1: in std_logic; SMIADDR0: in std_logic;
+ SMIRD: in std_logic; SMIWR: in std_logic;
+ SMICLK: in std_logic; SMIWDATA: in std_logic;
+ SMIRSTN: in std_logic; CLKOP: out std_logic;
+ CLKOS: out std_logic; LOCK: out std_logic;
+ SMIRDATA: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ attribute FREQUENCY_PIN_CLKOS : string;
+ attribute FREQUENCY_PIN_CLKOP : string;
+ attribute FREQUENCY_PIN_CLKI : string;
+ attribute GSR : string;
+ attribute CLKFB_PDEL : string;
+ attribute CLKI_PDEL : string;
+ attribute ALU_INIT_CNTVAL : string;
+ attribute ALU_UNLOCK_CNT : string;
+ attribute ALU_LOCK_CNT : string;
+ attribute CLKI_DIV : string;
+ attribute CLKOS_DIV : string;
+ attribute CLKOS_FPHASE : string;
+ attribute CLKOS_PHASE : string;
+ attribute CLKOP_PHASE : string;
+ attribute FREQUENCY_PIN_CLKOS of dll_100m_0_0 : label is "100.000000";
+ attribute FREQUENCY_PIN_CLKOP of dll_100m_0_0 : label is "100.000000";
+ attribute FREQUENCY_PIN_CLKI of dll_100m_0_0 : label is "100.000000";
+ attribute GSR of dll_100m_0_0 : label is "DISABLED";
+ attribute CLKFB_PDEL of dll_100m_0_0 : label is "DEL0";
+ attribute CLKI_PDEL of dll_100m_0_0 : label is "DEL0";
+ attribute ALU_INIT_CNTVAL of dll_100m_0_0 : label is "0";
+ attribute ALU_UNLOCK_CNT of dll_100m_0_0 : label is "3";
+ attribute ALU_LOCK_CNT of dll_100m_0_0 : label is "3";
+ attribute CLKI_DIV of dll_100m_0_0 : label is "1";
+ attribute CLKOS_DIV of dll_100m_0_0 : label is "1";
+ attribute CLKOS_FPHASE of dll_100m_0_0 : label is "0";
+ attribute CLKOS_PHASE of dll_100m_0_0 : label is "270";
+ attribute CLKOP_PHASE of dll_100m_0_0 : label is "270";
+ attribute syn_keep : boolean;
+ attribute syn_noprune : boolean;
+ attribute syn_noprune of Structure : architecture is true;
+
+begin
+ -- component instantiation statements
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ dll_100m_0_0: CIDDLLA
+ -- synopsys translate_off
+ generic map (GSR=> "DISABLED", ALU_INIT_CNTVAL=> 0,
+ ALU_UNLOCK_CNT=> 3, ALU_LOCK_CNT=> 3, CLKI_DIV=> 1, CLKOS_DIV=> 1,
+ CLKOS_FPHASE=> 0, CLKOS_PHASE=> 270, CLKOP_PHASE=> 270)
+ -- synopsys translate_on
+ port map (CLKI=>clk_t, CLKFB=>clkop_t, RSTN=>resetn,
+ ALUHOLD=>aluhold, SMIADDR9=>scuba_vlo, SMIADDR8=>scuba_vlo,
+ SMIADDR7=>scuba_vlo, SMIADDR6=>scuba_vlo,
+ SMIADDR5=>scuba_vlo, SMIADDR4=>scuba_vlo,
+ SMIADDR3=>scuba_vlo, SMIADDR2=>scuba_vlo,
+ SMIADDR1=>scuba_vlo, SMIADDR0=>scuba_vlo, SMIRD=>scuba_vlo,
+ SMIWR=>scuba_vlo, SMICLK=>scuba_vlo, SMIWDATA=>scuba_vlo,
+ SMIRSTN=>scuba_vlo, CLKOP=>clkop_t, CLKOS=>clkos_t,
+ LOCK=>lock, SMIRDATA=>open);
+
+ clkos <= clkos_t;
+ clkop <= clkop_t;
+ clk_t <= clk;
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of dll_100m is
+ for Structure
+ for all:CIDDLLA use entity ecp2m.CIDDLLA(V); end for;
+ for all:VLO use entity ecp2m.VLO(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_PROD_Build (44)
+-- Module Version: 3.2
+-- Thu Jan 29 18:49:16 2009
+
+-- parameterized module component declaration
+component dll_100m
+ port (clk: in std_logic; resetn: in std_logic;
+ aluhold: in std_logic; clkop: out std_logic;
+ clkos: out std_logic; lock: out std_logic);
+end component;
+
+-- parameterized module component instance
+__ : dll_100m
+ port map (clk=>__, resetn=>__, aluhold=>__, clkop=>__, clkos=>__,
+ lock=>__);
--- /dev/null
+[Device]\r
+Family=latticeecp2m\r
+PartType=LFE2M100E\r
+PartName=LFE2M100E-6F900C\r
+SpeedGrade=-6\r
+Package=FPBGA900\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=Distributed_DPRAM\r
+CoreRevision=3.4\r
+ModuleName=dpram_8x19\r
+SourceFormat=VHDL\r
+ParameterFileVersion=1.0\r
+Date=11/20/2009\r
+Time=19:14:27\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+Addresses=16\r
+Data=19\r
+LUT=0\r
+MemFile=\r
+MemFormat=orca\r
--- /dev/null
+SCUBA, Version ispLever_v72_PROD_Build (44)
+Fri Nov 20 19:14:28 2009
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp. All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
+Copyright (c) 2001 Agere Systems All rights reserved.
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
+
+ Issued command : F:\Programme\ispTOOLS7_2\ispfpga\bin\nt\scuba.exe -w -n dpram_8x19 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type ramdps -raddr_width 4 -rwidth 19 -waddr_width 4 -wwidth 19 -rnum_words 16 -wnum_words 16 -outData UNREGISTERED -e
+ Circuit name : dpram_8x19
+ Module type : sdpram
+ Module Version : 3.4
+ Address width : 4
+ Ports :
+ Inputs : WrAddress[3:0], Data[18:0], WrClock, WE, WrClockEn, RdAddress[3:0]
+ Outputs : Q[18:0]
+ I/O buffer : not inserted
+ Clock edge : rising edge
+ EDIF output : suppressed
+ VHDL output : dpram_8x19.vhd
+ VHDL template : dpram_8x19_tmpl.vhd
+ VHDL testbench : tb_dpram_8x19_tmpl.vhd
+ VHDL purpose : for synthesis and simulation
+ Bus notation : big endian
+ Report output : dpram_8x19.srp
+ Element Usage :
+ ROM16X1 : 1
+ DPR16X4A : 5
+ Estimated Resource Usage:
+ LUT : 1
+ DRAM : 5
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v72_PROD_Build (44)
+-- Module Version: 3.4
+--F:\Programme\ispTOOLS7_2\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type sdpram -rdata_width 19 -data_width 19 -num_rows 16 -outData UNREGISTERED -e
+
+-- Fri Nov 20 19:14:28 2009
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity dpram_8x19 is
+ port (
+ WrAddress: in std_logic_vector(3 downto 0);
+ Data: in std_logic_vector(18 downto 0);
+ WrClock: in std_logic;
+ WE: in std_logic;
+ WrClockEn: in std_logic;
+ RdAddress: in std_logic_vector(3 downto 0);
+ Q: out std_logic_vector(18 downto 0));
+end dpram_8x19;
+
+architecture Structure of dpram_8x19 is
+
+ -- internal signal declarations
+ signal scuba_vhi: std_logic;
+ signal scuba_vlo: std_logic;
+ signal dec0_wre3: std_logic;
+
+ -- local component declarations
+ component ROM16X1
+ -- synopsys translate_off
+ generic (initval : in String);
+ -- synopsys translate_on
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component DPR16X4A
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; WCK: in std_logic; WRE: in std_logic;
+ RAD0: in std_logic; RAD1: in std_logic;
+ RAD2: in std_logic; RAD3: in std_logic;
+ WAD0: in std_logic; WAD1: in std_logic;
+ WAD2: in std_logic; WAD3: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ attribute initval : string;
+ attribute initval of LUT4_0 : label is "0x8000";
+
+begin
+ -- component instantiation statements
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ LUT4_0: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>WE, AD2=>WrClockEn, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec0_wre3);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ mem_0_0: DPR16X4A
+ port map (DI0=>Data(16), DI1=>Data(17), DI2=>Data(18),
+ DI3=>scuba_vlo, WCK=>WrClock, WRE=>dec0_wre3,
+ RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2),
+ RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1),
+ WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>Q(16),
+ DO1=>Q(17), DO2=>Q(18), DO3=>open);
+
+ mem_0_1: DPR16X4A
+ port map (DI0=>Data(12), DI1=>Data(13), DI2=>Data(14),
+ DI3=>Data(15), WCK=>WrClock, WRE=>dec0_wre3,
+ RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2),
+ RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1),
+ WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>Q(12),
+ DO1=>Q(13), DO2=>Q(14), DO3=>Q(15));
+
+ mem_0_2: DPR16X4A
+ port map (DI0=>Data(8), DI1=>Data(9), DI2=>Data(10),
+ DI3=>Data(11), WCK=>WrClock, WRE=>dec0_wre3,
+ RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2),
+ RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1),
+ WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>Q(8), DO1=>Q(9),
+ DO2=>Q(10), DO3=>Q(11));
+
+ mem_0_3: DPR16X4A
+ port map (DI0=>Data(4), DI1=>Data(5), DI2=>Data(6), DI3=>Data(7),
+ WCK=>WrClock, WRE=>dec0_wre3, RAD0=>RdAddress(0),
+ RAD1=>RdAddress(1), RAD2=>RdAddress(2), RAD3=>RdAddress(3),
+ WAD0=>WrAddress(0), WAD1=>WrAddress(1), WAD2=>WrAddress(2),
+ WAD3=>WrAddress(3), DO0=>Q(4), DO1=>Q(5), DO2=>Q(6),
+ DO3=>Q(7));
+
+ mem_0_4: DPR16X4A
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ WCK=>WrClock, WRE=>dec0_wre3, RAD0=>RdAddress(0),
+ RAD1=>RdAddress(1), RAD2=>RdAddress(2), RAD3=>RdAddress(3),
+ WAD0=>WrAddress(0), WAD1=>WrAddress(1), WAD2=>WrAddress(2),
+ WAD3=>WrAddress(3), DO0=>Q(0), DO1=>Q(1), DO2=>Q(2),
+ DO3=>Q(3));
+
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of dpram_8x19 is
+ for Structure
+ for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for;
+ for all:DPR16X4A use entity ecp2m.DPR16X4A(V); end for;
+ for all:VHI use entity ecp2m.VHI(V); end for;
+ for all:VLO use entity ecp2m.VLO(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+Starting process: \r
+\r
+SCUBA, Version ispLever_v72_PROD_Build (44)\r
+Fri Nov 20 19:14:28 2009\r
+\r
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
+Copyright (c) 1995 AT&T Corp. All rights reserved.\r
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
+Copyright (c) 2001 Agere Systems All rights reserved.\r
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
+\r
+BEGIN SCUBA Module Synthesis\r
+\r
+ Issued command : F:\Programme\ispTOOLS7_2\ispfpga\bin\nt\scuba.exe -w -n dpram_8x19 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type ramdps -raddr_width 4 -rwidth 19 -waddr_width 4 -wwidth 19 -rnum_words 16 -wnum_words 16 -outData UNREGISTERED -e \r
+ Circuit name : dpram_8x19\r
+ Module type : sdpram\r
+ Module Version : 3.4\r
+ Address width : 4\r
+ Data width : 19\r
+ Ports : \r
+ Inputs : WrAddress[3:0], Data[18:0], WrClock, WE, WrClockEn, RdAddress[3:0]\r
+ Outputs : Q[18:0]\r
+ I/O buffer : not inserted\r
+ Clock edge : rising edge\r
+ EDIF output : suppressed\r
+ VHDL output : dpram_8x19.vhd\r
+ VHDL template : dpram_8x19_tmpl.vhd\r
+ VHDL testbench : tb_dpram_8x19_tmpl.vhd\r
+ VHDL purpose : for synthesis and simulation\r
+ Bus notation : big endian\r
+ Report output : dpram_8x19.srp\r
+ Estimated Resource Usage:\r
+ LUT : 1\r
+ DRAM : 5\r
+\r
+END SCUBA Module Synthesis\r
+\r
+File: ..\src\dpram_8x19.lpc created.\r
+\r
+\r
+End process: completed successfully.\r
+\r
+\r
+Total Warnings: 0\r
+\r
+Total Errors: 0\r
+\r
+\r
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_PROD_Build (44)
+-- Module Version: 3.4
+-- Fri Nov 20 19:14:28 2009
+
+-- parameterized module component declaration
+component dpram_8x19
+ port (WrAddress: in std_logic_vector(3 downto 0);
+ Data: in std_logic_vector(18 downto 0); WrClock: in std_logic;
+ WE: in std_logic; WrClockEn: in std_logic;
+ RdAddress: in std_logic_vector(3 downto 0);
+ Q: out std_logic_vector(18 downto 0));
+end component;
+
+-- parameterized module component instance
+__ : dpram_8x19
+ port map (WrAddress(3 downto 0)=>__, Data(18 downto 0)=>__, WrClock=>__,
+ WE=>__, WrClockEn=>__, RdAddress(3 downto 0)=>__, Q(18 downto 0)=>__);
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.std_logic_arith.all;\r
+use ieee.std_logic_unsigned.all;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+entity eds_buf is\r
+ port( CLK_IN : in std_logic; -- 100MHz master clock\r
+ RESET_IN : in std_logic; \r
+ -- EDS input, all synced to CLK_IN\r
+ EDS_DATA_IN : in std_logic_vector(39 downto 0); -- EDS data input\r
+ EDS_WE_IN : in std_logic; -- EDS write enable\r
+ EDS_DONE_IN : in std_logic; -- release EDS \r
+ EDS_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ EDS_AVAILABLE_OUT : out std_logic;\r
+ -- trigger busy information\r
+ BUF_FULL_OUT : out std_logic;\r
+ BUF_LEVEL_OUT : out std_logic_vector(4 downto 0);\r
+ -- Debug signals\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
+end;\r
+\r
+architecture behavioral of eds_buf is\r
+\r
+ -- normal signals\r
+ signal debug : std_logic_vector(15 downto 0);\r
+\r
+ -- Signals for controlling the EDS buffer memory\r
+ signal eds_data : std_logic_vector(39 downto 0);\r
+ signal eds_rd_addr : std_logic_vector(3 downto 0);\r
+ signal eds_wr_addr : std_logic_vector(3 downto 0);\r
+ signal eds_wr : std_logic;\r
+ signal eds_rd : std_logic;\r
+ signal eds_free_ctr : std_logic_vector(4 downto 0); -- fill level counter\r
+ signal eds_free_up : std_logic;\r
+ signal eds_free_down : std_logic;\r
+ signal eds_available_x : std_logic; \r
+ signal eds_available : std_logic; -- at least one valid EDS entry is available\r
+ signal eds_full_x : std_logic;\r
+ signal eds_full : std_logic;\r
+ \r
+begin\r
+\r
+-- General process for syncing combinatorial signals\r
+THE_SYNC_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ eds_available <= eds_available_x;\r
+ eds_full <= eds_full_x;\r
+ end if;\r
+end process THE_SYNC_PROC;\r
+\r
+-- Write address pointer for EDS buffer\r
+eds_wr <= eds_we_in;\r
+\r
+THE_WR_ADDR_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( reset_in = '1' ) then\r
+ eds_wr_addr <= (others => '0');\r
+ elsif( eds_wr = '1' ) then\r
+ eds_wr_addr <= eds_wr_addr + 1;\r
+ end if;\r
+ end if;\r
+end process THE_WR_ADDR_PROC;\r
+\r
+-- Read address pointer for EDS buffer\r
+eds_rd <= eds_done_in;\r
+\r
+THE_RD_ADDR_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( reset_in = '1' ) then\r
+ eds_rd_addr <= (others => '0');\r
+ elsif( eds_rd = '1' ) then\r
+ eds_rd_addr <= eds_rd_addr + 1;\r
+ end if;\r
+ end if;\r
+end process THE_RD_ADDR_PROC;\r
+\r
+-- Buffer fill level counter\r
+eds_free_down <= eds_we_in;\r
+eds_free_up <= eds_done_in;\r
+\r
+THE_EDS_FREE_COUNTER_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( reset_in = '1' ) then\r
+ eds_free_ctr <= "10000";\r
+ elsif( eds_free_down = '1' and eds_free_up = '0' ) then\r
+ eds_free_ctr <= eds_free_ctr - 1; \r
+ elsif( eds_free_down = '0' and eds_free_up = '1' ) then\r
+ eds_free_ctr <= eds_free_ctr + 1;\r
+ end if;\r
+ end if;\r
+end process THE_EDS_FREE_COUNTER_PROC;\r
+\r
+eds_full_x <= '1' when (eds_free_ctr = "00000") else '0';\r
+\r
+-- A 16x40b DPRAM is used for buffering the EventDataSheets (EDS)\r
+THE_EDS_BUFFER: eds_buffer_dpram\r
+port map( WRADDRESS => eds_wr_addr,\r
+ DATA => eds_data_in,\r
+ WRCLOCK => clk_in, \r
+ WE => eds_we_in, \r
+ WRCLOCKEN => '1', \r
+ RDADDRESS => eds_rd_addr, \r
+ RDCLOCK => clk_in, \r
+ RDCLOCKEN => '1', \r
+ RESET => reset_in, \r
+ Q => eds_data\r
+ );\r
+\r
+-- Are there any EDS to work on?\r
+eds_available_x <= '1' when (eds_wr_addr /= eds_rd_addr) else '0';\r
+\r
+-- Debug signals\r
+debug(15 downto 0) <= (others => '0');\r
+\r
+-- Output signals\r
+eds_data_out <= eds_data;\r
+eds_available_out <= eds_available;\r
+buf_full_out <= eds_full;\r
+buf_level_out <= eds_free_ctr;\r
+debug_out <= debug;\r
+\r
+end behavioral;\r
--- /dev/null
+[Device]\r
+Family=latticeecp2m\r
+PartType=LFE2M35E\r
+PartName=LFE2M35E-6F672C\r
+SpeedGrade=-6\r
+Package=FPBGA672\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=Distributed_DPRAM\r
+CoreRevision=3.3\r
+ModuleName=eds_buffer_dpram\r
+SourceFormat=VHDL\r
+ParameterFileVersion=1.0\r
+Date=08/29/2008\r
+Time=14:24:36\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+Addresses=16\r
+Data=40\r
+LUT=1\r
+MemFile=\r
+MemFormat=orca\r
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v71_PROD_Build (58)
+-- Module Version: 3.3
+--X:\Programme\ispTOOLS_71\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type sdpram -rdata_width 40 -data_width 40 -num_rows 16 -outData REGISTERED -e
+
+-- Fri Aug 29 14:24:36 2008
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity eds_buffer_dpram is
+ port (
+ WrAddress: in std_logic_vector(3 downto 0);
+ Data: in std_logic_vector(39 downto 0);
+ WrClock: in std_logic;
+ WE: in std_logic;
+ WrClockEn: in std_logic;
+ RdAddress: in std_logic_vector(3 downto 0);
+ RdClock: in std_logic;
+ RdClockEn: in std_logic;
+ Reset: in std_logic;
+ Q: out std_logic_vector(39 downto 0));
+end eds_buffer_dpram;
+
+architecture Structure of eds_buffer_dpram is
+
+ -- internal signal declarations
+ signal scuba_vlo: std_logic;
+ signal scuba_vhi: std_logic;
+ signal dataout39_ffin: std_logic;
+ signal dataout38_ffin: std_logic;
+ signal dataout37_ffin: std_logic;
+ signal dataout36_ffin: std_logic;
+ signal dataout35_ffin: std_logic;
+ signal dataout34_ffin: std_logic;
+ signal dataout33_ffin: std_logic;
+ signal dataout32_ffin: std_logic;
+ signal dataout31_ffin: std_logic;
+ signal dataout30_ffin: std_logic;
+ signal dataout29_ffin: std_logic;
+ signal dataout28_ffin: std_logic;
+ signal dataout27_ffin: std_logic;
+ signal dataout26_ffin: std_logic;
+ signal dataout25_ffin: std_logic;
+ signal dataout24_ffin: std_logic;
+ signal dataout23_ffin: std_logic;
+ signal dataout22_ffin: std_logic;
+ signal dataout21_ffin: std_logic;
+ signal dataout20_ffin: std_logic;
+ signal dataout19_ffin: std_logic;
+ signal dataout18_ffin: std_logic;
+ signal dataout17_ffin: std_logic;
+ signal dataout16_ffin: std_logic;
+ signal dataout15_ffin: std_logic;
+ signal dataout14_ffin: std_logic;
+ signal dataout13_ffin: std_logic;
+ signal dataout12_ffin: std_logic;
+ signal dataout11_ffin: std_logic;
+ signal dataout10_ffin: std_logic;
+ signal dataout9_ffin: std_logic;
+ signal dataout8_ffin: std_logic;
+ signal dataout7_ffin: std_logic;
+ signal dataout6_ffin: std_logic;
+ signal dataout5_ffin: std_logic;
+ signal dataout4_ffin: std_logic;
+ signal dataout3_ffin: std_logic;
+ signal dataout2_ffin: std_logic;
+ signal dataout1_ffin: std_logic;
+ signal dataout0_ffin: std_logic;
+ signal dec_wre3: std_logic;
+
+ -- local component declarations
+ component FD1P3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component ROM16X1
+ -- synopsys translate_off
+ generic (initval : in String);
+ -- synopsys translate_on
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component DPR16X4A
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; WCK: in std_logic; WRE: in std_logic;
+ RAD0: in std_logic; RAD1: in std_logic;
+ RAD2: in std_logic; RAD3: in std_logic;
+ WAD0: in std_logic; WAD1: in std_logic;
+ WAD2: in std_logic; WAD3: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ attribute initval : string;
+ attribute GSR : string;
+ attribute initval of LUT4_0 : label is "0x8000";
+ attribute GSR of FF_39 : label is "ENABLED";
+ attribute GSR of FF_38 : label is "ENABLED";
+ attribute GSR of FF_37 : label is "ENABLED";
+ attribute GSR of FF_36 : label is "ENABLED";
+ attribute GSR of FF_35 : label is "ENABLED";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+
+begin
+ -- component instantiation statements
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ LUT4_0: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>WE, AD2=>WrClockEn, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec_wre3);
+
+ FF_39: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout39_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(39));
+
+ FF_38: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout38_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(38));
+
+ FF_37: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout37_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(37));
+
+ FF_36: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout36_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(36));
+
+ FF_35: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout35_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(35));
+
+ FF_34: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout34_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(34));
+
+ FF_33: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout33_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(33));
+
+ FF_32: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout32_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(32));
+
+ FF_31: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout31_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(31));
+
+ FF_30: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout30_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(30));
+
+ FF_29: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout29_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(29));
+
+ FF_28: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout28_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(28));
+
+ FF_27: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout27_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(27));
+
+ FF_26: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout26_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(26));
+
+ FF_25: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout25_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(25));
+
+ FF_24: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout24_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(24));
+
+ FF_23: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout23_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(23));
+
+ FF_22: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout22_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(22));
+
+ FF_21: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout21_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(21));
+
+ FF_20: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout20_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(20));
+
+ FF_19: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout19_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(19));
+
+ FF_18: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout18_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(18));
+
+ FF_17: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout17_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(17));
+
+ FF_16: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout16_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(16));
+
+ FF_15: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout15_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(15));
+
+ FF_14: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout14_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(14));
+
+ FF_13: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout13_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(13));
+
+ FF_12: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout12_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(12));
+
+ FF_11: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout11_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(11));
+
+ FF_10: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout10_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(10));
+
+ FF_9: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout9_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(9));
+
+ FF_8: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout8_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(8));
+
+ FF_7: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout7_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(7));
+
+ FF_6: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout6_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(6));
+
+ FF_5: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout5_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(5));
+
+ FF_4: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout4_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(4));
+
+ FF_3: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout3_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(3));
+
+ FF_2: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout2_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(2));
+
+ FF_1: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout1_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(1));
+
+ FF_0: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout0_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(0));
+
+ mem_0_0: DPR16X4A
+ port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38),
+ DI3=>Data(39), WCK=>WrClock, WRE=>dec_wre3,
+ RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2),
+ RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1),
+ WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout36_ffin,
+ DO1=>dataout37_ffin, DO2=>dataout38_ffin,
+ DO3=>dataout39_ffin);
+
+ mem_0_1: DPR16X4A
+ port map (DI0=>Data(32), DI1=>Data(33), DI2=>Data(34),
+ DI3=>Data(35), WCK=>WrClock, WRE=>dec_wre3,
+ RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2),
+ RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1),
+ WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout32_ffin,
+ DO1=>dataout33_ffin, DO2=>dataout34_ffin,
+ DO3=>dataout35_ffin);
+
+ mem_0_2: DPR16X4A
+ port map (DI0=>Data(28), DI1=>Data(29), DI2=>Data(30),
+ DI3=>Data(31), WCK=>WrClock, WRE=>dec_wre3,
+ RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2),
+ RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1),
+ WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout28_ffin,
+ DO1=>dataout29_ffin, DO2=>dataout30_ffin,
+ DO3=>dataout31_ffin);
+
+ mem_0_3: DPR16X4A
+ port map (DI0=>Data(24), DI1=>Data(25), DI2=>Data(26),
+ DI3=>Data(27), WCK=>WrClock, WRE=>dec_wre3,
+ RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2),
+ RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1),
+ WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout24_ffin,
+ DO1=>dataout25_ffin, DO2=>dataout26_ffin,
+ DO3=>dataout27_ffin);
+
+ mem_0_4: DPR16X4A
+ port map (DI0=>Data(20), DI1=>Data(21), DI2=>Data(22),
+ DI3=>Data(23), WCK=>WrClock, WRE=>dec_wre3,
+ RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2),
+ RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1),
+ WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout20_ffin,
+ DO1=>dataout21_ffin, DO2=>dataout22_ffin,
+ DO3=>dataout23_ffin);
+
+ mem_0_5: DPR16X4A
+ port map (DI0=>Data(16), DI1=>Data(17), DI2=>Data(18),
+ DI3=>Data(19), WCK=>WrClock, WRE=>dec_wre3,
+ RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2),
+ RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1),
+ WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout16_ffin,
+ DO1=>dataout17_ffin, DO2=>dataout18_ffin,
+ DO3=>dataout19_ffin);
+
+ mem_0_6: DPR16X4A
+ port map (DI0=>Data(12), DI1=>Data(13), DI2=>Data(14),
+ DI3=>Data(15), WCK=>WrClock, WRE=>dec_wre3,
+ RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2),
+ RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1),
+ WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout12_ffin,
+ DO1=>dataout13_ffin, DO2=>dataout14_ffin,
+ DO3=>dataout15_ffin);
+
+ mem_0_7: DPR16X4A
+ port map (DI0=>Data(8), DI1=>Data(9), DI2=>Data(10),
+ DI3=>Data(11), WCK=>WrClock, WRE=>dec_wre3,
+ RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2),
+ RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1),
+ WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout8_ffin,
+ DO1=>dataout9_ffin, DO2=>dataout10_ffin, DO3=>dataout11_ffin);
+
+ mem_0_8: DPR16X4A
+ port map (DI0=>Data(4), DI1=>Data(5), DI2=>Data(6), DI3=>Data(7),
+ WCK=>WrClock, WRE=>dec_wre3, RAD0=>RdAddress(0),
+ RAD1=>RdAddress(1), RAD2=>RdAddress(2), RAD3=>RdAddress(3),
+ WAD0=>WrAddress(0), WAD1=>WrAddress(1), WAD2=>WrAddress(2),
+ WAD3=>WrAddress(3), DO0=>dataout4_ffin, DO1=>dataout5_ffin,
+ DO2=>dataout6_ffin, DO3=>dataout7_ffin);
+
+ mem_0_9: DPR16X4A
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ WCK=>WrClock, WRE=>dec_wre3, RAD0=>RdAddress(0),
+ RAD1=>RdAddress(1), RAD2=>RdAddress(2), RAD3=>RdAddress(3),
+ WAD0=>WrAddress(0), WAD1=>WrAddress(1), WAD2=>WrAddress(2),
+ WAD3=>WrAddress(3), DO0=>dataout0_ffin, DO1=>dataout1_ffin,
+ DO2=>dataout2_ffin, DO3=>dataout3_ffin);
+
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of eds_buffer_dpram is
+ for Structure
+ for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
+ for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for;
+ for all:DPR16X4A use entity ecp2m.DPR16X4A(V); end for;
+ for all:VHI use entity ecp2m.VHI(V); end for;
+ for all:VLO use entity ecp2m.VLO(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v71_PROD_Build (58)
+-- Module Version: 3.3
+-- Fri Aug 29 14:24:36 2008
+
+-- parameterized module component declaration
+component eds_buffer_dpram
+ port (WrAddress: in std_logic_vector(3 downto 0);
+ Data: in std_logic_vector(39 downto 0); WrClock: in std_logic;
+ WE: in std_logic; WrClockEn: in std_logic;
+ RdAddress: in std_logic_vector(3 downto 0);
+ RdClock: in std_logic; RdClockEn: in std_logic;
+ Reset: in std_logic; Q: out std_logic_vector(39 downto 0));
+end component;
+
+-- parameterized module component instance
+__ : eds_buffer_dpram
+ port map (WrAddress(3 downto 0)=>__, Data(39 downto 0)=>__, WrClock=>__,
+ WE=>__, WrClockEn=>__, RdAddress(3 downto 0)=>__, RdClock=>__,
+ RdClockEn=>__, Reset=>__, Q(39 downto 0)=>__);
--- /dev/null
+[Device]\r
+Family=latticeecp2m\r
+PartType=LFE2M100E\r
+PartName=LFE2M100E-6F900C\r
+SpeedGrade=-6\r
+Package=FPBGA900\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=FIFO\r
+CoreRevision=4.5\r
+ModuleName=fifo_16x11\r
+SourceFormat=VHDL\r
+ParameterFileVersion=1.0\r
+Date=03/03/2009\r
+Time=16:26:00\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+FIFOImp=LUT Based\r
+Depth=16\r
+Width=11\r
+regout=0\r
+CtrlByRdEn=0\r
+EmpFlg=0\r
+PeMode=Static - Single Threshold\r
+PeAssert=10\r
+PeDeassert=12\r
+FullFlg=0\r
+PfMode=Static - Single Threshold\r
+PfAssert=508\r
+PfDeassert=506\r
+RDataCount=1\r
+EnECC=0\r
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v72_SP1_Build (24)
+-- Module Version: 4.5
+--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -pfu_fifo -depth 16 -width 11 -depth 16 -no_enable -pe -1 -pf -1 -fill -e
+
+-- Tue Mar 03 16:26:00 2009
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity fifo_16x11 is
+ port (
+ Data: in std_logic_vector(10 downto 0);
+ Clock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ Q: out std_logic_vector(10 downto 0);
+ WCNT: out std_logic_vector(4 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic);
+end fifo_16x11;
+
+architecture Structure of fifo_16x11 is
+
+ -- internal signal declarations
+ signal invout_1: std_logic;
+ signal invout_0: std_logic;
+ signal rden_i_inv: std_logic;
+ signal fcnt_en: std_logic;
+ signal empty_i: std_logic;
+ signal empty_d: std_logic;
+ signal full_i: std_logic;
+ signal full_d: std_logic;
+ signal ifcount_0: std_logic;
+ signal ifcount_1: std_logic;
+ signal bdcnt_bctr_ci: std_logic;
+ signal ifcount_2: std_logic;
+ signal ifcount_3: std_logic;
+ signal co0: std_logic;
+ signal ifcount_4: std_logic;
+ signal co2: std_logic;
+ signal cnt_con: std_logic;
+ signal co1: std_logic;
+ signal cmp_ci: std_logic;
+ signal rden_i: std_logic;
+ signal co0_1: std_logic;
+ signal co1_1: std_logic;
+ signal cmp_le_1: std_logic;
+ signal cmp_le_1_c: std_logic;
+ signal cmp_ci_1: std_logic;
+ signal fcount_0: std_logic;
+ signal fcount_1: std_logic;
+ signal co0_2: std_logic;
+ signal wren_i: std_logic;
+ signal fcount_2: std_logic;
+ signal fcount_3: std_logic;
+ signal co1_2: std_logic;
+ signal wren_i_inv: std_logic;
+ signal fcount_4: std_logic;
+ signal cmp_ge_d1: std_logic;
+ signal cmp_ge_d1_c: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal w_ctr_ci: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal co0_3: std_logic;
+ signal iwcount_4: std_logic;
+ signal co2_1: std_logic;
+ signal wcount_4: std_logic;
+ signal co1_3: std_logic;
+ signal scuba_vhi: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal r_ctr_ci: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal co0_4: std_logic;
+ signal ircount_4: std_logic;
+ signal co2_2: std_logic;
+ signal rcount_4: std_logic;
+ signal co1_4: std_logic;
+ signal rdataout10: std_logic;
+ signal rdataout9: std_logic;
+ signal rdataout8: std_logic;
+ signal scuba_vlo: std_logic;
+ signal rdataout7: std_logic;
+ signal rdataout6: std_logic;
+ signal rdataout5: std_logic;
+ signal rdataout4: std_logic;
+ signal rdataout3: std_logic;
+ signal rdataout2: std_logic;
+ signal rdataout1: std_logic;
+ signal rdataout0: std_logic;
+ signal rcount_3: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_1: std_logic;
+ signal rcount_0: std_logic;
+ signal dec0_wre3: std_logic;
+ signal wcount_3: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_1: std_logic;
+ signal wcount_0: std_logic;
+
+ -- local component declarations
+ component AGEB2
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; GE: out std_logic);
+ end component;
+ component ALEB2
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; LE: out std_logic);
+ end component;
+ component AND2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component CU2
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
+ end component;
+ component CB2
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ CON: in std_logic; CO: out std_logic; NC0: out std_logic;
+ NC1: out std_logic);
+ end component;
+ component FADD2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; COUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FD1P3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1S3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component FD1S3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component ROM16X1
+ -- synopsys translate_off
+ generic (initval : in String);
+ -- synopsys translate_on
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component DPR16X4A
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; WCK: in std_logic; WRE: in std_logic;
+ RAD0: in std_logic; RAD1: in std_logic;
+ RAD2: in std_logic; RAD3: in std_logic;
+ WAD0: in std_logic; WAD1: in std_logic;
+ WAD2: in std_logic; WAD3: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component XOR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ attribute initval : string;
+ attribute GSR : string;
+ attribute initval of LUT4_2 : label is "0x3232";
+ attribute initval of LUT4_1 : label is "0x3232";
+ attribute initval of LUT4_0 : label is "0x8000";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ AND2_t3: AND2
+ port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+ INV_3: INV
+ port map (A=>full_i, Z=>invout_1);
+
+ AND2_t2: AND2
+ port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+ INV_2: INV
+ port map (A=>empty_i, Z=>invout_0);
+
+ AND2_t1: AND2
+ port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
+
+ XOR2_t0: XOR2
+ port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
+
+ INV_1: INV
+ port map (A=>rden_i, Z=>rden_i_inv);
+
+ INV_0: INV
+ port map (A=>wren_i, Z=>wren_i_inv);
+
+ LUT4_2: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x3232")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i,
+ AD0=>empty_i, DO0=>empty_d);
+
+ LUT4_1: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x3232")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
+ AD0=>full_i, DO0=>full_d);
+
+ LUT4_0: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vhi, AD2=>wren_i, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec0_wre3);
+
+ FF_27: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_0);
+
+ FF_26: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_1);
+
+ FF_25: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_2);
+
+ FF_24: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_3);
+
+ FF_23: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_4);
+
+ FF_22: FD1S3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
+
+ FF_21: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
+
+ FF_20: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_0);
+
+ FF_19: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_18: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_17: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_16: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_15: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_0);
+
+ FF_14: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_1);
+
+ FF_13: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_2);
+
+ FF_12: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_3);
+
+ FF_11: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_4);
+
+ FF_10: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout0, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>Q(0));
+
+ FF_9: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>Q(1));
+
+ FF_8: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>Q(2));
+
+ FF_7: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>Q(3));
+
+ FF_6: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>Q(4));
+
+ FF_5: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>Q(5));
+
+ FF_4: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>Q(6));
+
+ FF_3: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>Q(7));
+
+ FF_2: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>Q(8));
+
+ FF_1: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>Q(9));
+
+ FF_0: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout10, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>Q(10));
+
+ bdcnt_bctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con,
+ CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open);
+
+ bdcnt_bctr_0: CB2
+ port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1,
+ CON=>cnt_con, CO=>co0, NC0=>ifcount_0, NC1=>ifcount_1);
+
+ bdcnt_bctr_1: CB2
+ port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con,
+ CO=>co1, NC0=>ifcount_2, NC1=>ifcount_3);
+
+ bdcnt_bctr_2: CB2
+ port map (CI=>co1, PC0=>fcount_4, PC1=>scuba_vlo, CON=>cnt_con,
+ CO=>co2, NC0=>ifcount_4, NC1=>open);
+
+ e_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open,
+ S1=>open);
+
+ e_cmp_0: ALEB2
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo,
+ CI=>cmp_ci, LE=>co0_1);
+
+ e_cmp_1: ALEB2
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co0_1, LE=>co1_1);
+
+ e_cmp_2: ALEB2
+ port map (A0=>fcount_4, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co1_1, LE=>cmp_le_1_c);
+
+ a0: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1,
+ S1=>open);
+
+ g_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open,
+ S1=>open);
+
+ g_cmp_0: AGEB2
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i,
+ CI=>cmp_ci_1, GE=>co0_2);
+
+ g_cmp_1: AGEB2
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i,
+ CI=>co0_2, GE=>co1_2);
+
+ g_cmp_2: AGEB2
+ port map (A0=>fcount_4, A1=>scuba_vlo, B0=>wren_i_inv,
+ B1=>scuba_vlo, CI=>co1_2, GE=>cmp_ge_d1_c);
+
+ a1: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1,
+ S1=>open);
+
+ w_ctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open,
+ S1=>open);
+
+ w_ctr_0: CU2
+ port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3,
+ NC0=>iwcount_0, NC1=>iwcount_1);
+
+ w_ctr_1: CU2
+ port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_3,
+ NC0=>iwcount_2, NC1=>iwcount_3);
+
+ w_ctr_2: CU2
+ port map (CI=>co1_3, PC0=>wcount_4, PC1=>scuba_vlo, CO=>co2_1,
+ NC0=>iwcount_4, NC1=>open);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ r_ctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open,
+ S1=>open);
+
+ r_ctr_0: CU2
+ port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4,
+ NC0=>ircount_0, NC1=>ircount_1);
+
+ r_ctr_1: CU2
+ port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_4,
+ NC0=>ircount_2, NC1=>ircount_3);
+
+ r_ctr_2: CU2
+ port map (CI=>co1_4, PC0=>rcount_4, PC1=>scuba_vlo, CO=>co2_2,
+ NC0=>ircount_4, NC1=>open);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ fifo_pfu_0_0: DPR16X4A
+ port map (DI0=>Data(8), DI1=>Data(9), DI2=>Data(10),
+ DI3=>scuba_vlo, WCK=>Clock, WRE=>dec0_wre3, RAD0=>rcount_0,
+ RAD1=>rcount_1, RAD2=>rcount_2, RAD3=>rcount_3,
+ WAD0=>wcount_0, WAD1=>wcount_1, WAD2=>wcount_2,
+ WAD3=>wcount_3, DO0=>rdataout8, DO1=>rdataout9,
+ DO2=>rdataout10, DO3=>open);
+
+ fifo_pfu_0_1: DPR16X4A
+ port map (DI0=>Data(4), DI1=>Data(5), DI2=>Data(6), DI3=>Data(7),
+ WCK=>Clock, WRE=>dec0_wre3, RAD0=>rcount_0, RAD1=>rcount_1,
+ RAD2=>rcount_2, RAD3=>rcount_3, WAD0=>wcount_0,
+ WAD1=>wcount_1, WAD2=>wcount_2, WAD3=>wcount_3,
+ DO0=>rdataout4, DO1=>rdataout5, DO2=>rdataout6,
+ DO3=>rdataout7);
+
+ fifo_pfu_0_2: DPR16X4A
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ WCK=>Clock, WRE=>dec0_wre3, RAD0=>rcount_0, RAD1=>rcount_1,
+ RAD2=>rcount_2, RAD3=>rcount_3, WAD0=>wcount_0,
+ WAD1=>wcount_1, WAD2=>wcount_2, WAD3=>wcount_3,
+ DO0=>rdataout0, DO1=>rdataout1, DO2=>rdataout2,
+ DO3=>rdataout3);
+
+ WCNT(0) <= fcount_0;
+ WCNT(1) <= fcount_1;
+ WCNT(2) <= fcount_2;
+ WCNT(3) <= fcount_3;
+ WCNT(4) <= fcount_4;
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of fifo_16x11 is
+ for Structure
+ for all:AGEB2 use entity ecp2m.AGEB2(V); end for;
+ for all:ALEB2 use entity ecp2m.ALEB2(V); end for;
+ for all:AND2 use entity ecp2m.AND2(V); end for;
+ for all:CU2 use entity ecp2m.CU2(V); end for;
+ for all:CB2 use entity ecp2m.CB2(V); end for;
+ for all:FADD2B use entity ecp2m.FADD2B(V); end for;
+ for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
+ for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for;
+ for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for;
+ for all:INV use entity ecp2m.INV(V); end for;
+ for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for;
+ for all:DPR16X4A use entity ecp2m.DPR16X4A(V); end for;
+ for all:VHI use entity ecp2m.VHI(V); end for;
+ for all:VLO use entity ecp2m.VLO(V); end for;
+ for all:XOR2 use entity ecp2m.XOR2(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_SP1_Build (24)
+-- Module Version: 4.5
+-- Tue Mar 03 16:26:00 2009
+
+-- parameterized module component declaration
+component fifo_16x11
+ port (Data: in std_logic_vector(10 downto 0); Clock: in std_logic;
+ WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic;
+ Q: out std_logic_vector(10 downto 0);
+ WCNT: out std_logic_vector(4 downto 0); Empty: out std_logic;
+ Full: out std_logic);
+end component;
+
+-- parameterized module component instance
+__ : fifo_16x11
+ port map (Data(10 downto 0)=>__, Clock=>__, WrEn=>__, RdEn=>__,
+ Reset=>__, Q(10 downto 0)=>__, WCNT(4 downto 0)=>__, Empty=>__,
+ Full=>__);
--- /dev/null
+[Device]\r
+Family=latticeecp2m\r
+PartType=LFE2M100E\r
+PartName=LFE2M100E-6F900C\r
+SpeedGrade=-6\r
+Package=FPBGA900\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=FIFO\r
+CoreRevision=4.5\r
+ModuleName=fifo_2kx27\r
+SourceFormat=VHDL\r
+ParameterFileVersion=1.0\r
+Date=02/27/2009\r
+Time=12:01:58\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+FIFOImp=EBR Based\r
+Depth=2048\r
+Width=27\r
+regout=0\r
+CtrlByRdEn=0\r
+EmpFlg=0\r
+PeMode=Static - Single Threshold\r
+PeAssert=10\r
+PeDeassert=12\r
+FullFlg=0\r
+PfMode=Static - Single Threshold\r
+PfAssert=508\r
+PfDeassert=506\r
+RDataCount=1\r
+EnECC=0\r
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v72_SP1_Build (24)
+-- Module Version: 4.5
+--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 2048 -width 27 -depth 2048 -no_enable -pe -1 -pf -1 -fill -e
+
+-- Fri Feb 27 12:01:58 2009
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity fifo_2kx27 is
+ port (
+ Data: in std_logic_vector(26 downto 0);
+ Clock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ Q: out std_logic_vector(26 downto 0);
+ WCNT: out std_logic_vector(11 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic);
+end fifo_2kx27;
+
+architecture Structure of fifo_2kx27 is
+
+ -- internal signal declarations
+ signal invout_1: std_logic;
+ signal invout_0: std_logic;
+ signal rden_i_inv: std_logic;
+ signal fcnt_en: std_logic;
+ signal empty_i: std_logic;
+ signal empty_d: std_logic;
+ signal full_i: std_logic;
+ signal full_d: std_logic;
+ signal ifcount_0: std_logic;
+ signal ifcount_1: std_logic;
+ signal bdcnt_bctr_ci: std_logic;
+ signal ifcount_2: std_logic;
+ signal ifcount_3: std_logic;
+ signal co0: std_logic;
+ signal ifcount_4: std_logic;
+ signal ifcount_5: std_logic;
+ signal co1: std_logic;
+ signal ifcount_6: std_logic;
+ signal ifcount_7: std_logic;
+ signal co2: std_logic;
+ signal ifcount_8: std_logic;
+ signal ifcount_9: std_logic;
+ signal co3: std_logic;
+ signal ifcount_10: std_logic;
+ signal ifcount_11: std_logic;
+ signal co5: std_logic;
+ signal cnt_con: std_logic;
+ signal co4: std_logic;
+ signal cmp_ci: std_logic;
+ signal rden_i: std_logic;
+ signal co0_1: std_logic;
+ signal co1_1: std_logic;
+ signal co2_1: std_logic;
+ signal co3_1: std_logic;
+ signal co4_1: std_logic;
+ signal cmp_le_1: std_logic;
+ signal cmp_le_1_c: std_logic;
+ signal cmp_ci_1: std_logic;
+ signal fcount_0: std_logic;
+ signal fcount_1: std_logic;
+ signal co0_2: std_logic;
+ signal fcount_2: std_logic;
+ signal fcount_3: std_logic;
+ signal co1_2: std_logic;
+ signal fcount_4: std_logic;
+ signal fcount_5: std_logic;
+ signal co2_2: std_logic;
+ signal fcount_6: std_logic;
+ signal fcount_7: std_logic;
+ signal co3_2: std_logic;
+ signal fcount_8: std_logic;
+ signal fcount_9: std_logic;
+ signal co4_2: std_logic;
+ signal wren_i: std_logic;
+ signal wren_i_inv: std_logic;
+ signal fcount_10: std_logic;
+ signal fcount_11: std_logic;
+ signal cmp_ge_d1: std_logic;
+ signal cmp_ge_d1_c: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal w_ctr_ci: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_3: std_logic;
+ signal co0_3: std_logic;
+ signal iwcount_4: std_logic;
+ signal iwcount_5: std_logic;
+ signal wcount_4: std_logic;
+ signal wcount_5: std_logic;
+ signal co1_3: std_logic;
+ signal iwcount_6: std_logic;
+ signal iwcount_7: std_logic;
+ signal wcount_6: std_logic;
+ signal wcount_7: std_logic;
+ signal co2_3: std_logic;
+ signal iwcount_8: std_logic;
+ signal iwcount_9: std_logic;
+ signal wcount_8: std_logic;
+ signal wcount_9: std_logic;
+ signal co3_3: std_logic;
+ signal iwcount_10: std_logic;
+ signal iwcount_11: std_logic;
+ signal co5_1: std_logic;
+ signal wcount_10: std_logic;
+ signal wcount_11: std_logic;
+ signal co4_3: std_logic;
+ signal scuba_vlo: std_logic;
+ signal scuba_vhi: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal r_ctr_ci: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal co0_4: std_logic;
+ signal ircount_4: std_logic;
+ signal ircount_5: std_logic;
+ signal rcount_4: std_logic;
+ signal rcount_5: std_logic;
+ signal co1_4: std_logic;
+ signal ircount_6: std_logic;
+ signal ircount_7: std_logic;
+ signal rcount_6: std_logic;
+ signal rcount_7: std_logic;
+ signal co2_4: std_logic;
+ signal ircount_8: std_logic;
+ signal ircount_9: std_logic;
+ signal rcount_8: std_logic;
+ signal rcount_9: std_logic;
+ signal co3_4: std_logic;
+ signal ircount_10: std_logic;
+ signal ircount_11: std_logic;
+ signal co5_2: std_logic;
+ signal rcount_10: std_logic;
+ signal rcount_11: std_logic;
+ signal co4_4: std_logic;
+
+ -- local component declarations
+ component AGEB2
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; GE: out std_logic);
+ end component;
+ component ALEB2
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; LE: out std_logic);
+ end component;
+ component AND2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component CU2
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
+ end component;
+ component CB2
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ CON: in std_logic; CO: out std_logic; NC0: out std_logic;
+ NC1: out std_logic);
+ end component;
+ component FADD2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; COUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FD1P3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1S3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component FD1S3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component ROM16X1
+ -- synopsys translate_off
+ generic (initval : in String);
+ -- synopsys translate_on
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component XOR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component DP16KB
+ -- synopsys translate_off
+ generic (GSR : in String; WRITEMODE_B : in String;
+ CSDECODE_B : in std_logic_vector(2 downto 0);
+ CSDECODE_A : in std_logic_vector(2 downto 0);
+ WRITEMODE_A : in String; RESETMODE : in String;
+ REGMODE_B : in String; REGMODE_A : in String;
+ DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer);
+ -- synopsys translate_on
+ port (DIA0: in std_logic; DIA1: in std_logic;
+ DIA2: in std_logic; DIA3: in std_logic;
+ DIA4: in std_logic; DIA5: in std_logic;
+ DIA6: in std_logic; DIA7: in std_logic;
+ DIA8: in std_logic; DIA9: in std_logic;
+ DIA10: in std_logic; DIA11: in std_logic;
+ DIA12: in std_logic; DIA13: in std_logic;
+ DIA14: in std_logic; DIA15: in std_logic;
+ DIA16: in std_logic; DIA17: in std_logic;
+ ADA0: in std_logic; ADA1: in std_logic;
+ ADA2: in std_logic; ADA3: in std_logic;
+ ADA4: in std_logic; ADA5: in std_logic;
+ ADA6: in std_logic; ADA7: in std_logic;
+ ADA8: in std_logic; ADA9: in std_logic;
+ ADA10: in std_logic; ADA11: in std_logic;
+ ADA12: in std_logic; ADA13: in std_logic;
+ CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic;
+ CSA0: in std_logic; CSA1: in std_logic;
+ CSA2: in std_logic; RSTA: in std_logic;
+ DIB0: in std_logic; DIB1: in std_logic;
+ DIB2: in std_logic; DIB3: in std_logic;
+ DIB4: in std_logic; DIB5: in std_logic;
+ DIB6: in std_logic; DIB7: in std_logic;
+ DIB8: in std_logic; DIB9: in std_logic;
+ DIB10: in std_logic; DIB11: in std_logic;
+ DIB12: in std_logic; DIB13: in std_logic;
+ DIB14: in std_logic; DIB15: in std_logic;
+ DIB16: in std_logic; DIB17: in std_logic;
+ ADB0: in std_logic; ADB1: in std_logic;
+ ADB2: in std_logic; ADB3: in std_logic;
+ ADB4: in std_logic; ADB5: in std_logic;
+ ADB6: in std_logic; ADB7: in std_logic;
+ ADB8: in std_logic; ADB9: in std_logic;
+ ADB10: in std_logic; ADB11: in std_logic;
+ ADB12: in std_logic; ADB13: in std_logic;
+ CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic;
+ CSB0: in std_logic; CSB1: in std_logic;
+ CSB2: in std_logic; RSTB: in std_logic;
+ DOA0: out std_logic; DOA1: out std_logic;
+ DOA2: out std_logic; DOA3: out std_logic;
+ DOA4: out std_logic; DOA5: out std_logic;
+ DOA6: out std_logic; DOA7: out std_logic;
+ DOA8: out std_logic; DOA9: out std_logic;
+ DOA10: out std_logic; DOA11: out std_logic;
+ DOA12: out std_logic; DOA13: out std_logic;
+ DOA14: out std_logic; DOA15: out std_logic;
+ DOA16: out std_logic; DOA17: out std_logic;
+ DOB0: out std_logic; DOB1: out std_logic;
+ DOB2: out std_logic; DOB3: out std_logic;
+ DOB4: out std_logic; DOB5: out std_logic;
+ DOB6: out std_logic; DOB7: out std_logic;
+ DOB8: out std_logic; DOB9: out std_logic;
+ DOB10: out std_logic; DOB11: out std_logic;
+ DOB12: out std_logic; DOB13: out std_logic;
+ DOB14: out std_logic; DOB15: out std_logic;
+ DOB16: out std_logic; DOB17: out std_logic);
+ end component;
+ attribute initval : string;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute CSDECODE_B : string;
+ attribute CSDECODE_A : string;
+ attribute WRITEMODE_B : string;
+ attribute WRITEMODE_A : string;
+ attribute RESETMODE : string;
+ attribute REGMODE_B : string;
+ attribute REGMODE_A : string;
+ attribute DATA_WIDTH_B : string;
+ attribute DATA_WIDTH_A : string;
+ attribute GSR : string;
+ attribute initval of LUT4_1 : label is "0x3232";
+ attribute initval of LUT4_0 : label is "0x3232";
+ attribute MEM_LPC_FILE of pdp_ram_0_0_2 : label is "fifo_2kx27.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_2 : label is "";
+ attribute CSDECODE_B of pdp_ram_0_0_2 : label is "0b000";
+ attribute CSDECODE_A of pdp_ram_0_0_2 : label is "0b000";
+ attribute WRITEMODE_B of pdp_ram_0_0_2 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_0_0_2 : label is "NORMAL";
+ attribute GSR of pdp_ram_0_0_2 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_0_2 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_0_0_2 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_0_0_2 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_0_0_2 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_0_0_2 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_0_1_1 : label is "fifo_2kx27.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_1_1 : label is "";
+ attribute CSDECODE_B of pdp_ram_0_1_1 : label is "0b000";
+ attribute CSDECODE_A of pdp_ram_0_1_1 : label is "0b000";
+ attribute WRITEMODE_B of pdp_ram_0_1_1 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_0_1_1 : label is "NORMAL";
+ attribute GSR of pdp_ram_0_1_1 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_1_1 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_0_1_1 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_0_1_1 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_0_1_1 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_0_1_1 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_0_2_0 : label is "fifo_2kx27.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_2_0 : label is "";
+ attribute CSDECODE_B of pdp_ram_0_2_0 : label is "0b000";
+ attribute CSDECODE_A of pdp_ram_0_2_0 : label is "0b000";
+ attribute WRITEMODE_B of pdp_ram_0_2_0 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_0_2_0 : label is "NORMAL";
+ attribute GSR of pdp_ram_0_2_0 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_2_0 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_0_2_0 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_0_2_0 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_0_2_0 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_0_2_0 : label is "9";
+ attribute GSR of FF_37 : label is "ENABLED";
+ attribute GSR of FF_36 : label is "ENABLED";
+ attribute GSR of FF_35 : label is "ENABLED";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ AND2_t3: AND2
+ port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+ INV_3: INV
+ port map (A=>full_i, Z=>invout_1);
+
+ AND2_t2: AND2
+ port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+ INV_2: INV
+ port map (A=>empty_i, Z=>invout_0);
+
+ AND2_t1: AND2
+ port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
+
+ XOR2_t0: XOR2
+ port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
+
+ INV_1: INV
+ port map (A=>rden_i, Z=>rden_i_inv);
+
+ INV_0: INV
+ port map (A=>wren_i, Z=>wren_i_inv);
+
+ LUT4_1: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x3232")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i,
+ AD0=>empty_i, DO0=>empty_d);
+
+ LUT4_0: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x3232")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
+ AD0=>full_i, DO0=>full_d);
+
+ pdp_ram_0_0_2: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wcount_0,
+ ADA4=>wcount_1, ADA5=>wcount_2, ADA6=>wcount_3,
+ ADA7=>wcount_4, ADA8=>wcount_5, ADA9=>wcount_6,
+ ADA10=>wcount_7, ADA11=>wcount_8, ADA12=>wcount_9,
+ ADA13=>wcount_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
+ CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rcount_0, ADB4=>rcount_1,
+ ADB5=>rcount_2, ADB6=>rcount_3, ADB7=>rcount_4,
+ ADB8=>rcount_5, ADB9=>rcount_6, ADB10=>rcount_7,
+ ADB11=>rcount_8, ADB12=>rcount_9, ADB13=>rcount_10,
+ CEB=>rden_i, CLKB=>Clock, WEB=>scuba_vlo, CSB0=>scuba_vlo,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(0),
+ DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), DOB4=>Q(4), DOB5=>Q(5),
+ DOB6=>Q(6), DOB7=>Q(7), DOB8=>Q(8), DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_0_1_1: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
+ DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
+ DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wcount_0, ADA4=>wcount_1, ADA5=>wcount_2,
+ ADA6=>wcount_3, ADA7=>wcount_4, ADA8=>wcount_5,
+ ADA9=>wcount_6, ADA10=>wcount_7, ADA11=>wcount_8,
+ ADA12=>wcount_9, ADA13=>wcount_10, CEA=>wren_i, CLKA=>Clock,
+ WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo,
+ CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
+ DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
+ DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
+ DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
+ DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
+ DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
+ DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
+ ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rcount_0,
+ ADB4=>rcount_1, ADB5=>rcount_2, ADB6=>rcount_3,
+ ADB7=>rcount_4, ADB8=>rcount_5, ADB9=>rcount_6,
+ ADB10=>rcount_7, ADB11=>rcount_8, ADB12=>rcount_9,
+ ADB13=>rcount_10, CEB=>rden_i, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
+ RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
+ DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
+ DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
+ DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
+ DOA17=>open, DOB0=>Q(9), DOB1=>Q(10), DOB2=>Q(11),
+ DOB3=>Q(12), DOB4=>Q(13), DOB5=>Q(14), DOB6=>Q(15),
+ DOB7=>Q(16), DOB8=>Q(17), DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_0_2_0: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
+ DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
+ DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wcount_0, ADA4=>wcount_1, ADA5=>wcount_2,
+ ADA6=>wcount_3, ADA7=>wcount_4, ADA8=>wcount_5,
+ ADA9=>wcount_6, ADA10=>wcount_7, ADA11=>wcount_8,
+ ADA12=>wcount_9, ADA13=>wcount_10, CEA=>wren_i, CLKA=>Clock,
+ WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo,
+ CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
+ DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
+ DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
+ DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
+ DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
+ DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
+ DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
+ ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rcount_0,
+ ADB4=>rcount_1, ADB5=>rcount_2, ADB6=>rcount_3,
+ ADB7=>rcount_4, ADB8=>rcount_5, ADB9=>rcount_6,
+ ADB10=>rcount_7, ADB11=>rcount_8, ADB12=>rcount_9,
+ ADB13=>rcount_10, CEB=>rden_i, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
+ RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
+ DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
+ DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
+ DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
+ DOA17=>open, DOB0=>Q(18), DOB1=>Q(19), DOB2=>Q(20),
+ DOB3=>Q(21), DOB4=>Q(22), DOB5=>Q(23), DOB6=>Q(24),
+ DOB7=>Q(25), DOB8=>Q(26), DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ DOB15=>open, DOB16=>open, DOB17=>open);
+
+ FF_37: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_0);
+
+ FF_36: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_1);
+
+ FF_35: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_2);
+
+ FF_34: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_3);
+
+ FF_33: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_4);
+
+ FF_32: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_5);
+
+ FF_31: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_6);
+
+ FF_30: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_7);
+
+ FF_29: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_8);
+
+ FF_28: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_9);
+
+ FF_27: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_10);
+
+ FF_26: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_11, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_11);
+
+ FF_25: FD1S3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
+
+ FF_24: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
+
+ FF_23: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_0);
+
+ FF_22: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_21: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_20: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_19: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_18: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_5);
+
+ FF_17: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_6);
+
+ FF_16: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_7);
+
+ FF_15: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_8);
+
+ FF_14: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_9);
+
+ FF_13: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_10);
+
+ FF_12: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_11, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_11);
+
+ FF_11: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_0);
+
+ FF_10: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_1);
+
+ FF_9: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_2);
+
+ FF_8: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_3);
+
+ FF_7: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_4);
+
+ FF_6: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_5);
+
+ FF_5: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_6);
+
+ FF_4: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_7);
+
+ FF_3: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_8);
+
+ FF_2: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_9);
+
+ FF_1: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_10);
+
+ FF_0: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_11, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_11);
+
+ bdcnt_bctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con,
+ CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open);
+
+ bdcnt_bctr_0: CB2
+ port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1,
+ CON=>cnt_con, CO=>co0, NC0=>ifcount_0, NC1=>ifcount_1);
+
+ bdcnt_bctr_1: CB2
+ port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con,
+ CO=>co1, NC0=>ifcount_2, NC1=>ifcount_3);
+
+ bdcnt_bctr_2: CB2
+ port map (CI=>co1, PC0=>fcount_4, PC1=>fcount_5, CON=>cnt_con,
+ CO=>co2, NC0=>ifcount_4, NC1=>ifcount_5);
+
+ bdcnt_bctr_3: CB2
+ port map (CI=>co2, PC0=>fcount_6, PC1=>fcount_7, CON=>cnt_con,
+ CO=>co3, NC0=>ifcount_6, NC1=>ifcount_7);
+
+ bdcnt_bctr_4: CB2
+ port map (CI=>co3, PC0=>fcount_8, PC1=>fcount_9, CON=>cnt_con,
+ CO=>co4, NC0=>ifcount_8, NC1=>ifcount_9);
+
+ bdcnt_bctr_5: CB2
+ port map (CI=>co4, PC0=>fcount_10, PC1=>fcount_11, CON=>cnt_con,
+ CO=>co5, NC0=>ifcount_10, NC1=>ifcount_11);
+
+ e_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open,
+ S1=>open);
+
+ e_cmp_0: ALEB2
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo,
+ CI=>cmp_ci, LE=>co0_1);
+
+ e_cmp_1: ALEB2
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co0_1, LE=>co1_1);
+
+ e_cmp_2: ALEB2
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co1_1, LE=>co2_1);
+
+ e_cmp_3: ALEB2
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co2_1, LE=>co3_1);
+
+ e_cmp_4: ALEB2
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co3_1, LE=>co4_1);
+
+ e_cmp_5: ALEB2
+ port map (A0=>fcount_10, A1=>fcount_11, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co4_1, LE=>cmp_le_1_c);
+
+ a0: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1,
+ S1=>open);
+
+ g_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open,
+ S1=>open);
+
+ g_cmp_0: AGEB2
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i,
+ CI=>cmp_ci_1, GE=>co0_2);
+
+ g_cmp_1: AGEB2
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i,
+ CI=>co0_2, GE=>co1_2);
+
+ g_cmp_2: AGEB2
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i,
+ CI=>co1_2, GE=>co2_2);
+
+ g_cmp_3: AGEB2
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i,
+ CI=>co2_2, GE=>co3_2);
+
+ g_cmp_4: AGEB2
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i,
+ CI=>co3_2, GE=>co4_2);
+
+ g_cmp_5: AGEB2
+ port map (A0=>fcount_10, A1=>fcount_11, B0=>wren_i,
+ B1=>wren_i_inv, CI=>co4_2, GE=>cmp_ge_d1_c);
+
+ a1: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1,
+ S1=>open);
+
+ w_ctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open,
+ S1=>open);
+
+ w_ctr_0: CU2
+ port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3,
+ NC0=>iwcount_0, NC1=>iwcount_1);
+
+ w_ctr_1: CU2
+ port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_3,
+ NC0=>iwcount_2, NC1=>iwcount_3);
+
+ w_ctr_2: CU2
+ port map (CI=>co1_3, PC0=>wcount_4, PC1=>wcount_5, CO=>co2_3,
+ NC0=>iwcount_4, NC1=>iwcount_5);
+
+ w_ctr_3: CU2
+ port map (CI=>co2_3, PC0=>wcount_6, PC1=>wcount_7, CO=>co3_3,
+ NC0=>iwcount_6, NC1=>iwcount_7);
+
+ w_ctr_4: CU2
+ port map (CI=>co3_3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4_3,
+ NC0=>iwcount_8, NC1=>iwcount_9);
+
+ w_ctr_5: CU2
+ port map (CI=>co4_3, PC0=>wcount_10, PC1=>wcount_11, CO=>co5_1,
+ NC0=>iwcount_10, NC1=>iwcount_11);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ r_ctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open,
+ S1=>open);
+
+ r_ctr_0: CU2
+ port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4,
+ NC0=>ircount_0, NC1=>ircount_1);
+
+ r_ctr_1: CU2
+ port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_4,
+ NC0=>ircount_2, NC1=>ircount_3);
+
+ r_ctr_2: CU2
+ port map (CI=>co1_4, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_4,
+ NC0=>ircount_4, NC1=>ircount_5);
+
+ r_ctr_3: CU2
+ port map (CI=>co2_4, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_4,
+ NC0=>ircount_6, NC1=>ircount_7);
+
+ r_ctr_4: CU2
+ port map (CI=>co3_4, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_4,
+ NC0=>ircount_8, NC1=>ircount_9);
+
+ r_ctr_5: CU2
+ port map (CI=>co4_4, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_2,
+ NC0=>ircount_10, NC1=>ircount_11);
+
+ WCNT(0) <= fcount_0;
+ WCNT(1) <= fcount_1;
+ WCNT(2) <= fcount_2;
+ WCNT(3) <= fcount_3;
+ WCNT(4) <= fcount_4;
+ WCNT(5) <= fcount_5;
+ WCNT(6) <= fcount_6;
+ WCNT(7) <= fcount_7;
+ WCNT(8) <= fcount_8;
+ WCNT(9) <= fcount_9;
+ WCNT(10) <= fcount_10;
+ WCNT(11) <= fcount_11;
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of fifo_2kx27 is
+ for Structure
+ for all:AGEB2 use entity ecp2m.AGEB2(V); end for;
+ for all:ALEB2 use entity ecp2m.ALEB2(V); end for;
+ for all:AND2 use entity ecp2m.AND2(V); end for;
+ for all:CU2 use entity ecp2m.CU2(V); end for;
+ for all:CB2 use entity ecp2m.CB2(V); end for;
+ for all:FADD2B use entity ecp2m.FADD2B(V); end for;
+ for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
+ for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for;
+ for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for;
+ for all:INV use entity ecp2m.INV(V); end for;
+ for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for;
+ for all:VHI use entity ecp2m.VHI(V); end for;
+ for all:VLO use entity ecp2m.VLO(V); end for;
+ for all:XOR2 use entity ecp2m.XOR2(V); end for;
+ for all:DP16KB use entity ecp2m.DP16KB(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_SP1_Build (24)
+-- Module Version: 4.5
+-- Fri Feb 27 12:01:58 2009
+
+-- parameterized module component declaration
+component fifo_2kx27
+ port (Data: in std_logic_vector(26 downto 0); Clock: in std_logic;
+ WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic;
+ Q: out std_logic_vector(26 downto 0);
+ WCNT: out std_logic_vector(11 downto 0); Empty: out std_logic;
+ Full: out std_logic);
+end component;
+
+-- parameterized module component instance
+__ : fifo_2kx27
+ port map (Data(26 downto 0)=>__, Clock=>__, WrEn=>__, RdEn=>__,
+ Reset=>__, Q(26 downto 0)=>__, WCNT(11 downto 0)=>__, Empty=>__,
+ Full=>__);
--- /dev/null
+[Device]\r
+Family=latticeecp2m\r
+PartType=LFE2M100E\r
+PartName=LFE2M100E-6F900C\r
+SpeedGrade=-6\r
+Package=FPBGA900\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=Distributed_DPRAM\r
+CoreRevision=3.5\r
+ModuleName=frame_status_mem\r
+SourceFormat=VHDL\r
+ParameterFileVersion=1.0\r
+Date=09/14/2009\r
+Time=13:08:21\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+Addresses=16\r
+Data=12\r
+LUT=1\r
+MemFile=\r
+MemFormat=orca\r
--- /dev/null
+SCUBA, Version ispLever_v72_SP2_Build (23)
+Mon Sep 14 13:08:21 2009
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp. All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
+Copyright (c) 2001 Agere Systems All rights reserved.
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
+
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n frame_status_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type ramdps -raddr_width 4 -rwidth 12 -waddr_width 4 -wwidth 12 -rnum_words 16 -wnum_words 16 -outData REGISTERED -e
+ Circuit name : frame_status_mem
+ Module type : sdpram
+ Module Version : 3.5
+ Address width : 4
+ Ports :
+ Inputs : WrAddress[3:0], Data[11:0], WrClock, WE, WrClockEn, RdAddress[3:0], RdClock, RdClockEn, Reset
+ Outputs : Q[11:0]
+ I/O buffer : not inserted
+ Clock edge : rising edge
+ EDIF output : suppressed
+ VHDL output : frame_status_mem.vhd
+ VHDL template : frame_status_mem_tmpl.vhd
+ VHDL testbench : tb_frame_status_mem_tmpl.vhd
+ VHDL purpose : for synthesis and simulation
+ Bus notation : big endian
+ Report output : frame_status_mem.srp
+ Element Usage :
+ FD1P3DX : 12
+ ROM16X1 : 1
+ DPR16X4A : 3
+ Estimated Resource Usage:
+ LUT : 1
+ DRAM : 3
+ Reg : 12
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23)
+-- Module Version: 3.5
+--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type sdpram -rdata_width 12 -data_width 12 -num_rows 16 -outData REGISTERED -e
+
+-- Mon Sep 14 13:08:21 2009
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity frame_status_mem is
+ port (
+ WrAddress: in std_logic_vector(3 downto 0);
+ Data: in std_logic_vector(11 downto 0);
+ WrClock: in std_logic;
+ WE: in std_logic;
+ WrClockEn: in std_logic;
+ RdAddress: in std_logic_vector(3 downto 0);
+ RdClock: in std_logic;
+ RdClockEn: in std_logic;
+ Reset: in std_logic;
+ Q: out std_logic_vector(11 downto 0));
+end frame_status_mem;
+
+architecture Structure of frame_status_mem is
+
+ -- internal signal declarations
+ signal scuba_vlo: std_logic;
+ signal scuba_vhi: std_logic;
+ signal dataout11_ffin: std_logic;
+ signal dataout10_ffin: std_logic;
+ signal dataout9_ffin: std_logic;
+ signal dataout8_ffin: std_logic;
+ signal dataout7_ffin: std_logic;
+ signal dataout6_ffin: std_logic;
+ signal dataout5_ffin: std_logic;
+ signal dataout4_ffin: std_logic;
+ signal dataout3_ffin: std_logic;
+ signal dataout2_ffin: std_logic;
+ signal dataout1_ffin: std_logic;
+ signal dataout0_ffin: std_logic;
+ signal dec0_wre3: std_logic;
+
+ -- local component declarations
+ component FD1P3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component ROM16X1
+ -- synopsys translate_off
+ generic (initval : in String);
+ -- synopsys translate_on
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component DPR16X4A
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; WCK: in std_logic; WRE: in std_logic;
+ RAD0: in std_logic; RAD1: in std_logic;
+ RAD2: in std_logic; RAD3: in std_logic;
+ WAD0: in std_logic; WAD1: in std_logic;
+ WAD2: in std_logic; WAD3: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ attribute initval : string;
+ attribute GSR : string;
+ attribute initval of LUT4_0 : label is "0x8000";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+
+begin
+ -- component instantiation statements
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ LUT4_0: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>WE, AD2=>WrClockEn, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec0_wre3);
+
+ FF_11: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout11_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(11));
+
+ FF_10: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout10_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(10));
+
+ FF_9: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout9_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(9));
+
+ FF_8: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout8_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(8));
+
+ FF_7: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout7_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(7));
+
+ FF_6: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout6_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(6));
+
+ FF_5: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout5_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(5));
+
+ FF_4: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout4_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(4));
+
+ FF_3: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout3_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(3));
+
+ FF_2: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout2_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(2));
+
+ FF_1: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout1_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(1));
+
+ FF_0: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>dataout0_ffin, SP=>RdClockEn, CK=>RdClock,
+ CD=>Reset, Q=>Q(0));
+
+ mem_0_0: DPR16X4A
+ port map (DI0=>Data(8), DI1=>Data(9), DI2=>Data(10),
+ DI3=>Data(11), WCK=>WrClock, WRE=>dec0_wre3,
+ RAD0=>RdAddress(0), RAD1=>RdAddress(1), RAD2=>RdAddress(2),
+ RAD3=>RdAddress(3), WAD0=>WrAddress(0), WAD1=>WrAddress(1),
+ WAD2=>WrAddress(2), WAD3=>WrAddress(3), DO0=>dataout8_ffin,
+ DO1=>dataout9_ffin, DO2=>dataout10_ffin, DO3=>dataout11_ffin);
+
+ mem_0_1: DPR16X4A
+ port map (DI0=>Data(4), DI1=>Data(5), DI2=>Data(6), DI3=>Data(7),
+ WCK=>WrClock, WRE=>dec0_wre3, RAD0=>RdAddress(0),
+ RAD1=>RdAddress(1), RAD2=>RdAddress(2), RAD3=>RdAddress(3),
+ WAD0=>WrAddress(0), WAD1=>WrAddress(1), WAD2=>WrAddress(2),
+ WAD3=>WrAddress(3), DO0=>dataout4_ffin, DO1=>dataout5_ffin,
+ DO2=>dataout6_ffin, DO3=>dataout7_ffin);
+
+ mem_0_2: DPR16X4A
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ WCK=>WrClock, WRE=>dec0_wre3, RAD0=>RdAddress(0),
+ RAD1=>RdAddress(1), RAD2=>RdAddress(2), RAD3=>RdAddress(3),
+ WAD0=>WrAddress(0), WAD1=>WrAddress(1), WAD2=>WrAddress(2),
+ WAD3=>WrAddress(3), DO0=>dataout0_ffin, DO1=>dataout1_ffin,
+ DO2=>dataout2_ffin, DO3=>dataout3_ffin);
+
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of frame_status_mem is
+ for Structure
+ for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
+ for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for;
+ for all:DPR16X4A use entity ecp2m.DPR16X4A(V); end for;
+ for all:VHI use entity ecp2m.VHI(V); end for;
+ for all:VLO use entity ecp2m.VLO(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+Starting process: \r
+\r
+SCUBA, Version ispLever_v72_SP2_Build (23)\r
+Mon Sep 14 13:08:21 2009\r
+\r
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
+Copyright (c) 1995 AT&T Corp. All rights reserved.\r
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
+Copyright (c) 2001 Agere Systems All rights reserved.\r
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
+\r
+BEGIN SCUBA Module Synthesis\r
+\r
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n frame_status_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type ramdps -raddr_width 4 -rwidth 12 -waddr_width 4 -wwidth 12 -rnum_words 16 -wnum_words 16 -outData REGISTERED -e \r
+ Circuit name : frame_status_mem\r
+ Module type : sdpram\r
+ Module Version : 3.5\r
+ Address width : 4\r
+ Data width : 12\r
+ Ports : \r
+ Inputs : WrAddress[3:0], Data[11:0], WrClock, WE, WrClockEn, RdAddress[3:0], RdClock, RdClockEn, Reset\r
+ Outputs : Q[11:0]\r
+ I/O buffer : not inserted\r
+ Clock edge : rising edge\r
+ EDIF output : suppressed\r
+ VHDL output : frame_status_mem.vhd\r
+ VHDL template : frame_status_mem_tmpl.vhd\r
+ VHDL testbench : tb_frame_status_mem_tmpl.vhd\r
+ VHDL purpose : for synthesis and simulation\r
+ Bus notation : big endian\r
+ Report output : frame_status_mem.srp\r
+ Estimated Resource Usage:\r
+ LUT : 1\r
+ DRAM : 3\r
+ Reg : 12\r
+\r
+END SCUBA Module Synthesis\r
+\r
+File: frame_status_mem.lpc created.\r
+\r
+\r
+End process: completed successfully.\r
+\r
+\r
+Total Warnings: 0\r
+\r
+Total Errors: 0\r
+\r
+\r
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23)
+-- Module Version: 3.5
+-- Mon Sep 14 13:08:21 2009
+
+-- parameterized module component declaration
+component frame_status_mem
+ port (WrAddress: in std_logic_vector(3 downto 0);
+ Data: in std_logic_vector(11 downto 0); WrClock: in std_logic;
+ WE: in std_logic; WrClockEn: in std_logic;
+ RdAddress: in std_logic_vector(3 downto 0);
+ RdClock: in std_logic; RdClockEn: in std_logic;
+ Reset: in std_logic; Q: out std_logic_vector(11 downto 0));
+end component;
+
+-- parameterized module component instance
+__ : frame_status_mem
+ port map (WrAddress(3 downto 0)=>__, Data(11 downto 0)=>__, WrClock=>__,
+ WE=>__, WrClockEn=>__, RdAddress(3 downto 0)=>__, RdClock=>__,
+ RdClockEn=>__, Reset=>__, Q(11 downto 0)=>__);
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.std_logic_arith.all;\r
+use ieee.std_logic_unsigned.all;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+-- This module checks the framecounter setting embedded inside the APV raw data.\r
+-- Only channels with GOODDATA are taken into account.\r
+\r
+entity frmctr_check is\r
+ port( CLK_IN : in std_logic;\r
+ GOODDATA_IN : in std_logic_vector(15 downto 0);\r
+ FRAMECOUNTER_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_0_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_1_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_2_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_3_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_4_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_5_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_6_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_7_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_8_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_9_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_10_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_11_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_12_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_13_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_14_IN : in std_logic_vector(3 downto 0);\r
+ FRM_NR_15_IN : in std_logic_vector(3 downto 0);\r
+ FRC_ERROR_OUT : out std_logic; -- at least one framecounter is wrong\r
+ DBG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
+end;\r
+\r
+architecture behavioral of frmctr_check is\r
+\r
+ -- normal signals\r
+ signal debug_x : std_logic_vector(15 downto 0);\r
+\r
+ signal next_frc_match : std_logic_vector(15 downto 0); \r
+ signal frc_match : std_logic_vector(15 downto 0); \r
+ signal next_frc_error : std_logic;\r
+ signal frc_error : std_logic;\r
+ \r
+begin\r
+\r
+-- Sync process\r
+THE_SYNC_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ frc_match <= next_frc_match;\r
+ frc_error <= next_frc_error;\r
+ end if;\r
+end process THE_SYNC_PROC;\r
+\r
+-- Check the individual buffers\r
+-- If an APV is "not good" (i.e. broken or switched off) we assume a match.\r
+-- In case all APVs are switched off we get a match, this situation should be reconsidered...\r
+next_frc_match(0) <= '1' when ( (frm_nr_0_in = framecounter_in) or (gooddata_in(0) = '0') ) else '0';\r
+next_frc_match(1) <= '1' when ( (frm_nr_1_in = framecounter_in) or (gooddata_in(1) = '0') ) else '0';\r
+next_frc_match(2) <= '1' when ( (frm_nr_2_in = framecounter_in) or (gooddata_in(2) = '0') ) else '0';\r
+next_frc_match(3) <= '1' when ( (frm_nr_3_in = framecounter_in) or (gooddata_in(3) = '0') ) else '0';\r
+next_frc_match(4) <= '1' when ( (frm_nr_4_in = framecounter_in) or (gooddata_in(4) = '0') ) else '0';\r
+next_frc_match(5) <= '1' when ( (frm_nr_5_in = framecounter_in) or (gooddata_in(5) = '0') ) else '0';\r
+next_frc_match(6) <= '1' when ( (frm_nr_6_in = framecounter_in) or (gooddata_in(6) = '0') ) else '0';\r
+next_frc_match(7) <= '1' when ( (frm_nr_7_in = framecounter_in) or (gooddata_in(7) = '0') ) else '0';\r
+next_frc_match(8) <= '1' when ( (frm_nr_8_in = framecounter_in) or (gooddata_in(8) = '0') ) else '0';\r
+next_frc_match(9) <= '1' when ( (frm_nr_9_in = framecounter_in) or (gooddata_in(9) = '0') ) else '0';\r
+next_frc_match(10) <= '1' when ( (frm_nr_10_in = framecounter_in) or (gooddata_in(10) = '0') ) else '0';\r
+next_frc_match(11) <= '1' when ( (frm_nr_11_in = framecounter_in) or (gooddata_in(11) = '0') ) else '0';\r
+next_frc_match(12) <= '1' when ( (frm_nr_12_in = framecounter_in) or (gooddata_in(12) = '0') ) else '0';\r
+next_frc_match(13) <= '1' when ( (frm_nr_13_in = framecounter_in) or (gooddata_in(13) = '0') ) else '0';\r
+next_frc_match(14) <= '1' when ( (frm_nr_14_in = framecounter_in) or (gooddata_in(14) = '0') ) else '0';\r
+next_frc_match(15) <= '1' when ( (frm_nr_15_in = framecounter_in) or (gooddata_in(15) = '0') ) else '0';\r
+\r
+-- Combine all signals\r
+next_frc_error <= '1' when ( frc_match /= x"ffff" ) else '0';\r
+\r
+-- output signals\r
+frc_error_out <= frc_error;\r
+\r
+-- debug signals\r
+debug_x(15 downto 0) <= (others => '0');\r
+\r
+dbg_out <= debug_x;\r
+\r
+end behavioral;\r
--- /dev/null
+library IEEE;\r
+use IEEE.STD_LOGIC_1164.ALL;\r
+use IEEE.STD_LOGIC_ARITH.ALL;\r
+use IEEE.STD_LOGIC_UNSIGNED.ALL;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+entity I2C_GSTART is\r
+port( CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ START_IN : in std_logic; \r
+ DOSTART_IN : in std_logic; \r
+ I2C_SPEED_IN : in std_logic_vector(7 downto 0);\r
+ SDONE_OUT : out std_logic;\r
+ SOK_OUT : out std_logic;\r
+ SDA_IN : in std_logic;\r
+ SCL_IN : in std_logic;\r
+ R_SCL_OUT : out std_logic;\r
+ S_SCL_OUT : out std_logic;\r
+ R_SDA_OUT : out std_logic;\r
+ S_SDA_OUT : out std_logic;\r
+ BSM_OUT : out std_logic_vector(3 downto 0)\r
+ );\r
+end entity;\r
+\r
+architecture Behavioral of I2C_GSTART is\r
+\r
+-- Signals\r
+ type STATES is (SLEEP,P_SCL,WCTR0,P_SDA,WCTR1,P_CHK,S_CHK0,RS_SDA,S_CHK1,ERROR,DONE);\r
+ signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+ signal bsm : std_logic_vector(3 downto 0);\r
+ signal cctr : std_logic_vector(7 downto 0); -- counter for bit length\r
+\r
+ signal cycdone_x : std_logic;\r
+ signal cycdone : std_logic; -- one counter period done\r
+\r
+ signal load_cyc_x : std_logic;\r
+ signal load_cyc : std_logic;\r
+ signal dec_cyc_x : std_logic;\r
+ signal dec_cyc : std_logic; \r
+ signal sdone_x : std_logic;\r
+ signal sdone : std_logic; -- Start/Stop done\r
+ signal sok_x : std_logic;\r
+ signal sok : std_logic; -- Start/Stop OK\r
+\r
+ signal r_scl : std_logic;\r
+ signal s_scl : std_logic;\r
+ signal r_sda : std_logic;\r
+ signal s_sda : std_logic;\r
+\r
+-- Moduls\r
+\r
+begin\r
+\r
+-- Countdown for one half of SCL (adjustable clock width)\r
+THE_CYC_CTR_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ cctr <= (others => '0');\r
+ elsif( load_cyc = '1' ) then \r
+ cctr <= i2c_speed_in;\r
+ elsif( dec_cyc = '1' ) then\r
+ cctr <= cctr - 1;\r
+ end if;\r
+ end if;\r
+end process THE_CYC_CTR_PROC;\r
+\r
+-- end of cycle recognition\r
+cycdone_x <= '1' when (cctr = x"00") else '0';\r
+\r
+-- The main state machine\r
+-- State memory process\r
+STATE_MEM: process( clk_in )\r
+begin\r
+ if ( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ CURRENT_STATE <= SLEEP;\r
+ load_cyc <= '0';\r
+ dec_cyc <= '0';\r
+ sdone <= '0';\r
+ sok <= '0';\r
+ cycdone <= '0';\r
+ else\r
+ CURRENT_STATE <= NEXT_STATE;\r
+ load_cyc <= load_cyc_x;\r
+ dec_cyc <= dec_cyc_x;\r
+ sdone <= sdone_x;\r
+ sok <= sok_x;\r
+ cycdone <= cycdone_x;\r
+ end if;\r
+ end if;\r
+end process STATE_MEM;\r
+\r
+-- Transition matrix\r
+TRANSFORM: process(CURRENT_STATE, dostart_in, start_in, sda_in, scl_in, cycdone)\r
+begin\r
+ NEXT_STATE <= SLEEP;\r
+ load_cyc_x <= '0';\r
+ dec_cyc_x <= '0';\r
+ sdone_x <= '0';\r
+ sok_x <= '1';\r
+ case CURRENT_STATE is\r
+ when SLEEP => if ( (dostart_in = '1') and (start_in = '1') ) then\r
+ NEXT_STATE <= S_CHK0; -- generate a start condition\r
+ load_cyc_x <= '1';\r
+ elsif( (dostart_in = '1') and (start_in = '0') ) then\r
+ NEXT_STATE <= P_SCL; -- generate a stop condition\r
+ load_cyc_x <= '1';\r
+ else\r
+ NEXT_STATE <= SLEEP;\r
+ end if;\r
+ when P_SCL => NEXT_STATE <= WCTR0;\r
+ dec_cyc_x <= '1';\r
+ when S_CHK0 => if( (sda_in = '1') and (scl_in = '1') ) then\r
+ NEXT_STATE <= RS_SDA;\r
+ else\r
+ NEXT_STATE <= ERROR;\r
+ sok_x <= '0';\r
+ end if;\r
+ when RS_SDA => NEXT_STATE <= WCTR0;\r
+ dec_cyc_x <= '1';\r
+ when WCTR0 => if ( (cycdone = '1') and (start_in = '1') ) then\r
+ NEXT_STATE <= S_CHK1;\r
+ elsif( (cycdone = '1') and (start_in = '0') ) then\r
+ NEXT_STATE <= P_SDA;\r
+ load_cyc_x <= '1';\r
+ else\r
+ NEXT_STATE <= WCTR0;\r
+ dec_cyc_x <= '1';\r
+ end if;\r
+ when S_CHK1 => if( (sda_in = '0') and (scl_in = '1') ) then\r
+ NEXT_STATE <= DONE;\r
+ else\r
+ NEXT_STATE <= ERROR;\r
+ sok_x <= '0';\r
+ end if;\r
+ when P_SDA => NEXT_STATE <= WCTR1;\r
+ dec_cyc_x <= '1';\r
+ when WCTR1 => if( (cycdone = '1') ) then\r
+ NEXT_STATE <= P_CHK;\r
+ else\r
+ NEXT_STATE <= WCTR1;\r
+ dec_cyc_x <= '1';\r
+ end if;\r
+ when P_CHK => if( (sda_in = '1') and (scl_in = '1') ) then\r
+ NEXT_STATE <= DONE;\r
+ sdone_x <= '1';\r
+ else\r
+ NEXT_STATE <= ERROR;\r
+ sok_x <= '0';\r
+ end if;\r
+ when ERROR => if( dostart_in = '0' ) then\r
+ NEXT_STATE <= SLEEP;\r
+ else\r
+ NEXT_STATE <= ERROR;\r
+ sdone_x <= '1';\r
+ sok_x <= '0';\r
+ end if;\r
+ when DONE => if( dostart_in = '0' ) then\r
+ NEXT_STATE <= SLEEP;\r
+ else\r
+ NEXT_STATE <= DONE;\r
+ sdone_x <= '1';\r
+ end if;\r
+ when others => NEXT_STATE <= SLEEP;\r
+ end case;\r
+end process TRANSFORM;\r
+\r
+-- Output decoding\r
+DECODE: process(CURRENT_STATE)\r
+begin\r
+ case CURRENT_STATE is\r
+ when SLEEP => bsm <= x"0";\r
+ when S_CHK0 => bsm <= x"1";\r
+ when RS_SDA => bsm <= x"2";\r
+ when P_SCL => bsm <= x"3";\r
+ when WCTR0 => bsm <= x"4";\r
+ when S_CHK1 => bsm <= x"5";\r
+ when P_SDA => bsm <= x"6";\r
+ when WCTR1 => bsm <= x"7";\r
+ when P_CHK => bsm <= x"8";\r
+ when DONE => bsm <= x"9";\r
+ when ERROR => bsm <= x"e";\r
+ when others => bsm <= x"f";\r
+ end case;\r
+end process DECODE;\r
+\r
+S_R_GEN: process(CURRENT_STATE)\r
+begin\r
+ if ( CURRENT_STATE = P_SCL ) then\r
+ r_scl <= '0';\r
+ s_scl <= '1';\r
+ r_sda <= '0';\r
+ s_sda <= '0';\r
+ elsif( CURRENT_STATE = RS_SDA ) then\r
+ r_scl <= '0';\r
+ s_scl <= '0';\r
+ r_sda <= '1';\r
+ s_sda <= '0';\r
+ elsif( CURRENT_STATE = P_SDA ) then\r
+ r_scl <= '0';\r
+ s_scl <= '0';\r
+ r_sda <= '0';\r
+ s_sda <= '1';\r
+ else\r
+ r_scl <= '0';\r
+ s_scl <= '0';\r
+ r_sda <= '0';\r
+ s_sda <= '0';\r
+ end if;\r
+end process S_R_GEN;\r
+\r
+-- Outputs\r
+r_scl_out <= r_scl;\r
+s_scl_out <= s_scl;\r
+r_sda_out <= r_sda;\r
+s_sda_out <= s_sda;\r
+sdone_out <= sdone;\r
+sok_out <= sok;\r
+\r
+-- Debug\r
+bsm_out <= bsm;\r
+\r
+end Behavioral;\r
--- /dev/null
+library IEEE;\r
+use IEEE.STD_LOGIC_1164.ALL;\r
+use IEEE.STD_LOGIC_ARITH.ALL;\r
+use IEEE.STD_LOGIC_UNSIGNED.ALL;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+entity i2c_master is\r
+port( CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_BUSY_OUT : out std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- I2C connections\r
+ SDA_IN : in std_logic;\r
+ SDA_OUT : out std_logic;\r
+ SCL_IN : in std_logic;\r
+ SCL_OUT : out std_logic;\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+ );\r
+end entity;\r
+\r
+architecture Behavioral of i2c_master is\r
+\r
+-- Signals\r
+ type STATES is (SLEEP,RD_BSY,WR_BSY,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE);\r
+ signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+ -- slave bus signals\r
+ signal slv_busy_x : std_logic;\r
+ signal slv_busy : std_logic;\r
+ signal slv_ack_x : std_logic;\r
+ signal slv_ack : std_logic;\r
+ signal store_wr_x : std_logic;\r
+ signal store_wr : std_logic;\r
+ signal store_rd_x : std_logic;\r
+ signal store_rd : std_logic;\r
+\r
+ signal reg_slv_data_in : std_logic_vector(31 downto 0); -- registered data input\r
+ signal reg_slv_data_out : std_logic_vector(31 downto 0); -- read back data\r
+ signal reg_busy : std_logic;\r
+\r
+ signal status_data : std_logic_vector(31 downto 0);\r
+ signal i2c_debug : std_logic_vector(31 downto 0);\r
+\r
+begin\r
+\r
+---------------------------------------------------------\r
+-- I2C master --\r
+---------------------------------------------------------\r
+\r
+THE_I2C_SLIM: i2c_slim\r
+port map( CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ -- I2C command / setup\r
+ I2C_GO_IN => reg_slv_data_in(31),\r
+ ACTION_IN => reg_slv_data_in(30),\r
+ I2C_SPEED_IN => reg_slv_data_in(29 downto 24),\r
+ I2C_ADR_IN => reg_slv_data_in(23 downto 16),\r
+ I2C_CMD_IN => reg_slv_data_in(15 downto 8),\r
+ I2C_DW_IN => reg_slv_data_in(7 downto 0),\r
+ I2C_DR_OUT => status_data(7 downto 0),\r
+ STATUS_OUT => status_data(31 downto 24),\r
+ I2C_BUSY_OUT => reg_busy,\r
+ -- I2C connections\r
+ SDA_IN => sda_in,\r
+ SDA_OUT => sda_out,\r
+ SCL_IN => scl_in,\r
+ SCL_OUT => scl_out,\r
+ -- Debug\r
+ STAT => i2c_debug\r
+ );\r
+\r
+status_data(23 downto 21) <= (others => '0');\r
+status_data(20 downto 16) <= i2c_debug(4 downto 0);\r
+status_data(15 downto 8) <= (others => '0');\r
+\r
+-- Fake\r
+stat <= i2c_debug;\r
+\r
+---------------------------------------------------------\r
+-- Statemachine --\r
+---------------------------------------------------------\r
+-- State memory process\r
+STATE_MEM: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ CURRENT_STATE <= SLEEP;\r
+ slv_busy <= '0';\r
+ slv_ack <= '0';\r
+ store_wr <= '0';\r
+ store_rd <= '0';\r
+ else\r
+ CURRENT_STATE <= NEXT_STATE;\r
+ slv_busy <= slv_busy_x;\r
+ slv_ack <= slv_ack_x;\r
+ store_wr <= store_wr_x;\r
+ store_rd <= store_rd_x;\r
+ end if;\r
+ end if;\r
+end process STATE_MEM;\r
+\r
+-- Transition matrix\r
+TRANSFORM: process(CURRENT_STATE, slv_read_in, slv_write_in, reg_busy )\r
+begin\r
+ NEXT_STATE <= SLEEP;\r
+ slv_busy_x <= '0';\r
+ slv_ack_x <= '0';\r
+ store_wr_x <= '0';\r
+ store_rd_x <= '0';\r
+ case CURRENT_STATE is\r
+ when SLEEP => if ( (reg_busy = '0') and (slv_read_in = '1') ) then\r
+ NEXT_STATE <= RD_RDY;\r
+ store_rd_x <= '1';\r
+ elsif( (reg_busy = '0') and (slv_write_in = '1') ) then\r
+ NEXT_STATE <= WR_RDY;\r
+ store_wr_x <= '1';\r
+ elsif( (reg_busy = '1') and (slv_read_in = '1') ) then\r
+ NEXT_STATE <= RD_BSY;\r
+ slv_busy_x <= '1';\r
+ elsif( (reg_busy = '1') and (slv_write_in = '1') ) then\r
+ NEXT_STATE <= WR_BSY;\r
+ slv_busy_x <= '1';\r
+ else \r
+ NEXT_STATE <= SLEEP;\r
+ end if;\r
+ when RD_RDY => NEXT_STATE <= RD_ACK;\r
+ slv_ack_x <= '1';\r
+ when WR_RDY => NEXT_STATE <= WR_ACK;\r
+ slv_ack_x <= '1';\r
+ when RD_ACK => if( slv_read_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ else\r
+ NEXT_STATE <= RD_ACK;\r
+ slv_ack_x <= '1';\r
+ end if;\r
+ when WR_ACK => if( slv_write_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ else\r
+ NEXT_STATE <= WR_ACK;\r
+ slv_ack_x <= '1';\r
+ end if;\r
+ when RD_BSY => if( slv_read_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ else\r
+ NEXT_STATE <= RD_BSY;\r
+ slv_busy_x <= '1';\r
+ end if;\r
+ when WR_BSY => if( slv_write_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ else\r
+ NEXT_STATE <= WR_BSY;\r
+ slv_busy_x <= '1';\r
+ end if;\r
+ when DONE => NEXT_STATE <= SLEEP;\r
+ \r
+ when others => NEXT_STATE <= SLEEP;\r
+ end case;\r
+end process TRANSFORM;\r
+\r
+---------------------------------------------------------\r
+-- data handling --\r
+---------------------------------------------------------\r
+\r
+-- register write\r
+THE_WRITE_REG_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( reset_in = '1' ) then\r
+ reg_slv_data_in <= (others => '0');\r
+ elsif( store_wr = '1' ) then\r
+ reg_slv_data_in <= slv_data_in;\r
+ end if;\r
+ end if;\r
+end process THE_WRITE_REG_PROC;\r
+\r
+-- register read\r
+THE_READ_REG_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( reset_in = '1' ) then\r
+ reg_slv_data_out <= (others => '0');\r
+ elsif( store_rd = '1' ) then\r
+ reg_slv_data_out <= status_data;\r
+ end if;\r
+ end if;\r
+end process THE_READ_REG_PROC;\r
+\r
+-- output signals\r
+slv_ack_out <= slv_ack;\r
+slv_busy_out <= slv_busy;\r
+slv_data_out <= reg_slv_data_out;\r
+\r
+end Behavioral;\r
--- /dev/null
+library IEEE;\r
+use IEEE.STD_LOGIC_1164.ALL;\r
+use IEEE.STD_LOGIC_ARITH.ALL;\r
+use IEEE.STD_LOGIC_UNSIGNED.ALL;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+entity I2C_SENDB is\r
+port( CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ DOBYTE_IN : in std_logic; \r
+ I2C_SPEED_IN : in std_logic_vector( 7 downto 0 );\r
+ I2C_BYTE_IN : in std_logic_vector( 8 downto 0 ); \r
+ I2C_BACK_OUT : out std_logic_vector( 8 downto 0 );\r
+ SDA_IN : in std_logic;\r
+ R_SDA_OUT : out std_logic;\r
+ S_SDA_OUT : out std_logic;\r
+-- SCL_IN : in std_logic;\r
+ R_SCL_OUT : out std_logic;\r
+ S_SCL_OUT : out std_logic;\r
+ BDONE_OUT : out std_logic;\r
+ BOK_OUT : out std_logic;\r
+ BSM_OUT : out std_logic_vector( 3 downto 0 )\r
+ );\r
+end entity;\r
+\r
+architecture Behavioral of I2C_SENDB is\r
+\r
+-- Signals\r
+ type STATES is (SLEEP,LCL,WCL,LCH,WCH,FREE,DONE);\r
+ signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+ signal bsm : std_logic_vector( 3 downto 0 );\r
+\r
+ signal inc_bit_x : std_logic;\r
+ signal inc_bit : std_logic; -- increment bit counter for byte to send\r
+ signal rst_bit_x : std_logic;\r
+ signal rst_bit : std_logic; -- reset bit counter for byte to send\r
+ signal load_cyc_x : std_logic;\r
+ signal load_cyc : std_logic; -- load cycle counter (SCL length)\r
+ signal dec_cyc_x : std_logic;\r
+ signal dec_cyc : std_logic; -- decrement cycle counter (SCL length)\r
+ signal load_sr_x : std_logic;\r
+ signal load_sr : std_logic; -- load output shift register\r
+ signal shift_o_x : std_logic;\r
+ signal shift_o : std_logic; -- output shift register control\r
+ signal shift_i_x : std_logic;\r
+ signal shift_i : std_logic; -- input shift register control\r
+ signal bdone_x : std_logic;\r
+ signal bdone : std_logic;\r
+ signal r_scl_x : std_logic;\r
+ signal r_scl : std_logic; -- output for SCL \r
+ signal s_scl_x : std_logic;\r
+ signal s_scl : std_logic; -- output for SCL\r
+\r
+ signal bctr : std_logic_vector( 3 downto 0 ); -- bit counter (1...9)\r
+ signal cctr : std_logic_vector( 7 downto 0 ); -- counter for bit length\r
+ signal bok : std_logic;\r
+ signal cycdone : std_logic; -- one counter period done\r
+ signal bytedone : std_logic; -- all bits sents\r
+ signal in_sr : std_logic_vector( 8 downto 0 ); -- shift register for byte in\r
+ signal out_sr : std_logic_vector( 8 downto 0 ); -- shift register for byte out\r
+ signal i2c_back : std_logic_vector( 8 downto 0 ); -- shift register for byte in\r
+ signal r_sda : std_logic; -- output for SDA\r
+ signal s_sda : std_logic; -- output for SDA\r
+ signal load : std_logic; -- delay register\r
+ signal i2c_d : std_logic; -- auxiliary register\r
+\r
+-- Moduls\r
+\r
+begin\r
+\r
+-- Bit counter (for byte to send)\r
+THE_BIT_CTR_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ bctr <= (others => '0');\r
+ elsif( rst_bit = '1' ) then\r
+ bctr <= (others => '0');\r
+ elsif( inc_bit = '1' ) then\r
+ bctr <= bctr + 1;\r
+ end if;\r
+ end if;\r
+end process THE_BIT_CTR_PROC;\r
+\r
+-- end of byte recognition\r
+bytedone <= '1' when (bctr = x"9") else '0';\r
+\r
+-- Countdown for one half of SCL (adjustable clock width)\r
+THE_CYC_CTR_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ cctr <= (others => '0');\r
+ elsif( load_cyc = '1' ) then \r
+ cctr <= i2c_speed_in;\r
+ elsif( dec_cyc = '1' ) then\r
+ cctr <= cctr - 1;\r
+ end if;\r
+ end if;\r
+end process THE_CYC_CTR_PROC;\r
+\r
+-- end of cycle recognition\r
+cycdone <= '1' when (cctr = x"00") else '0';\r
+ \r
+-- Bit output\r
+THE_BIT_OUT_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ out_sr <= (others => '0');\r
+ i2c_d <= '1';\r
+ elsif( load_sr = '1' ) then\r
+ out_sr <= i2c_byte_in;\r
+ i2c_d <= '1';\r
+ elsif( shift_o = '1' ) then\r
+ i2c_d <= out_sr(8);\r
+ out_sr(8 downto 0) <= out_sr(7 downto 0) & '0';\r
+ end if;\r
+ end if;\r
+end process THE_BIT_OUT_PROC;\r
+\r
+-- Bit input\r
+THE_BIT_IN_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then \r
+ if ( reset_in = '1' ) then\r
+ in_sr <= (others => '1');\r
+ elsif( shift_o = '1' ) then\r
+ in_sr(8 downto 1) <= in_sr(7 downto 0);\r
+ in_sr(0) <= sda_in;\r
+ end if;\r
+ end if;\r
+end process THE_BIT_IN_PROC;\r
+\r
+-- Output register for readback data (could be reduced to SR_IN_INT)\r
+THE_I2C_BACK_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ i2c_back <= (others => '1');\r
+ elsif( shift_i = '1' ) then\r
+ i2c_back(8 downto 1) <= in_sr(7 downto 0);\r
+ i2c_back(0) <= sda_in;\r
+ end if;\r
+ end if;\r
+end process THE_I2C_BACK_PROC;\r
+\r
+-- ByteOK is the inverted ACK bit from readback data.\r
+bok <= not i2c_back(0); -- BUG\r
+\r
+-- The main state machine\r
+-- State memory process\r
+STATE_MEM: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1') then\r
+ CURRENT_STATE <= SLEEP;\r
+ inc_bit <= '0';\r
+ rst_bit <= '0';\r
+ load_cyc <= '0';\r
+ dec_cyc <= '0';\r
+ load_sr <= '0';\r
+ shift_o <= '0';\r
+ shift_i <= '0';\r
+ bdone <= '0';\r
+ r_scl <= '0';\r
+ s_scl <= '0';\r
+ else\r
+ CURRENT_STATE <= NEXT_STATE;\r
+ inc_bit <= inc_bit_x;\r
+ rst_bit <= rst_bit_x;\r
+ load_cyc <= load_cyc_x;\r
+ dec_cyc <= dec_cyc_x;\r
+ load_sr <= load_sr_x;\r
+ shift_o <= shift_o_x;\r
+ shift_i <= shift_i_x;\r
+ bdone <= bdone_x;\r
+ r_scl <= r_scl_x;\r
+ s_scl <= s_scl_x;\r
+ end if;\r
+ end if;\r
+end process STATE_MEM;\r
+\r
+-- Transition matrix\r
+TRANSFORM: process(CURRENT_STATE, dobyte_in, cycdone, bytedone)\r
+begin\r
+ NEXT_STATE <= SLEEP;\r
+ inc_bit_x <= '0';\r
+ rst_bit_x <= '0';\r
+ load_cyc_x <= '0';\r
+ dec_cyc_x <= '0';\r
+ load_sr_x <= '0';\r
+ shift_o_x <= '0';\r
+ shift_i_x <= '0';\r
+ bdone_x <= '0';\r
+ r_scl_x <= '0';\r
+ s_scl_x <= '0';\r
+ case CURRENT_STATE is\r
+ when SLEEP => if( dobyte_in = '1' ) then\r
+ NEXT_STATE <= LCL;\r
+ inc_bit_x <= '1';\r
+ load_cyc_x <= '1';\r
+ shift_o_x <= '1';\r
+ r_scl_x <= '1';\r
+ else\r
+ NEXT_STATE <= SLEEP;\r
+ load_sr_x <= '1';\r
+ end if;\r
+ when LCL => NEXT_STATE <= WCL;\r
+ dec_cyc_x <= '1';\r
+ when WCL => if( cycdone = '1' ) then\r
+ NEXT_STATE <= LCH;\r
+ load_cyc_x <= '1';\r
+ s_scl_x <= '1';\r
+ else\r
+ NEXT_STATE <= WCL;\r
+ dec_cyc_x <= '1';\r
+ end if;\r
+ when LCH => NEXT_STATE <= WCH;\r
+ dec_cyc_x <= '1';\r
+ when WCH => if ( (cycdone = '1') and (bytedone = '0') ) then\r
+ NEXT_STATE <= LCL;\r
+ inc_bit_x <= '1';\r
+ load_cyc_x <= '1';\r
+ shift_o_x <= '1';\r
+ r_scl_x <= '1';\r
+ elsif( (cycdone = '1') and (bytedone = '1') ) then\r
+ NEXT_STATE <= FREE;\r
+ shift_o_x <= '1';\r
+ shift_i_x <= '1';\r
+ r_scl_x <= '1';\r
+ else\r
+ NEXT_STATE <= WCH;\r
+ dec_cyc_x <= '1';\r
+ end if;\r
+ when FREE => NEXT_STATE <= DONE;\r
+ rst_bit_x <= '1';\r
+ bdone_x <= '1';\r
+ when DONE => if( dobyte_in = '0' ) then\r
+ NEXT_STATE <= SLEEP;\r
+ else\r
+ NEXT_STATE <= DONE;\r
+ rst_bit_x <= '1';\r
+ bdone_x <= '1';\r
+ end if;\r
+ -- Just in case...\r
+ when others => NEXT_STATE <= SLEEP; \r
+ end case;\r
+end process TRANSFORM;\r
+\r
+-- Output decoding\r
+DECODE: process(CURRENT_STATE)\r
+begin\r
+ case CURRENT_STATE is\r
+ when SLEEP => bsm <= x"0";\r
+ when LCL => bsm <= x"1";\r
+ when WCL => bsm <= x"2";\r
+ when LCH => bsm <= x"3";\r
+ when WCH => bsm <= x"4";\r
+ when FREE => bsm <= x"5";\r
+ when DONE => bsm <= x"6";\r
+ when others => bsm <= x"f";\r
+ end case; \r
+end process DECODE;\r
+\r
+-- SCL and SDA output pulses\r
+THE_SDA_OUT_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ load <= '0'; -- was a bug, found 081008\r
+ r_sda <= '0';\r
+ s_sda <= '0';\r
+ else\r
+ load <= shift_o; \r
+ r_sda <= load and not i2c_d;\r
+ s_sda <= load and i2c_d;\r
+ end if;\r
+ end if;\r
+end process THE_SDA_OUT_PROC;\r
+\r
+-- Outputs\r
+r_scl_out <= r_scl;\r
+s_scl_out <= s_scl;\r
+r_sda_out <= r_sda;\r
+s_sda_out <= s_sda;\r
+\r
+i2c_back_out <= i2c_back;\r
+\r
+bdone_out <= bdone;\r
+bok_out <= bok;\r
+\r
+-- Debugging \r
+bsm_out <= bsm;\r
+\r
+end Behavioral;\r
--- /dev/null
+library IEEE;\r
+use IEEE.STD_LOGIC_1164.ALL;\r
+use IEEE.STD_LOGIC_ARITH.ALL;\r
+use IEEE.STD_LOGIC_UNSIGNED.ALL;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+-- BUG: does alway set bit 0 of address byte to zero !!!!\r
+-- REMARK: this is not a bug, but a feature....\r
+\r
+entity i2c_slim is\r
+port( CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- I2C command / setup\r
+ I2C_GO_IN : in std_logic; -- startbit to trigger I2C actions\r
+ ACTION_IN : in std_logic; -- '0' -> write, '1' -> read\r
+ I2C_SPEED_IN : in std_logic_vector( 5 downto 0 ); -- speed adjustment (to be defined)\r
+ I2C_ADR_IN : in std_logic_vector( 7 downto 0 ); -- I2C address byte (R/W bit is ignored)\r
+ I2C_CMD_IN : in std_logic_vector( 7 downto 0 ); -- I2C command byte (sent after address byte)\r
+ I2C_DW_IN : in std_logic_vector( 7 downto 0 ); -- data word for write command\r
+ I2C_DR_OUT : out std_logic_vector( 7 downto 0 ); -- data word from read command\r
+ STATUS_OUT : out std_logic_vector( 7 downto 0 ); -- status and error bits\r
+ I2C_BUSY_OUT : out std_logic;\r
+ -- I2C connections\r
+ SDA_IN : in std_logic;\r
+ SDA_OUT : out std_logic;\r
+ SCL_IN : in std_logic;\r
+ SCL_OUT : out std_logic;\r
+ -- Debug\r
+ STAT : out std_logic_vector(31 downto 0)\r
+ );\r
+end i2c_slim;\r
+\r
+architecture Behavioral of i2c_slim is\r
+\r
+-- Signals\r
+ type STATES is (SLEEP,LOADA,GSTART,SENDA,LOADC,SENDC,LOADD,SENDD,GSTOP,INC,\r
+ E_START,E_ADDR,E_CMD,E_WD,E_RSTART,E_RADDR,DONE,FAILED,CLRERR);\r
+ signal CURRENT_STATE, NEXT_STATE: STATES;\r
+ \r
+ signal bsm : std_logic_vector( 4 downto 0 );\r
+ signal phase : std_logic; -- '0' => first phase, '1' => second phase of read cycle\r
+\r
+ signal start_x : std_logic;\r
+ signal start : std_logic; -- '0' => generate STOP, '1' => generate START\r
+ signal dostart_x : std_logic;\r
+ signal dostart : std_logic; -- trigger the GenStart module\r
+ signal dobyte_x : std_logic;\r
+ signal dobyte : std_logic; -- trigger the ByteSend module\r
+ signal i2c_done_x : std_logic;\r
+ signal i2c_done : std_logic; -- acknowledge signal to the outside world\r
+ signal running_x : std_logic;\r
+ signal running : std_logic; -- legacy\r
+\r
+ signal load_a_x : std_logic;\r
+ signal load_a : std_logic;\r
+ signal load_c_x : std_logic;\r
+ signal load_c : std_logic;\r
+ signal load_d_x : std_logic;\r
+ signal load_d : std_logic;\r
+\r
+ signal sdone : std_logic; -- acknowledge signal from GenStart module\r
+ signal sok : std_logic; -- status signal from GenStart module\r
+ signal bdone : std_logic; -- acknowledge signal from SendByte module\r
+ signal bok : std_logic; -- status signal from SendByte module\r
+ signal e_sf : std_logic; -- Start failed\r
+ signal e_anak : std_logic; -- Adress byte NAK\r
+ signal e_cnak : std_logic; -- Command byte NAK\r
+ signal e_dnak : std_logic; -- Data byte NAK\r
+ signal e_rsf : std_logic; -- Repeated Start failed\r
+ signal e_ranak : std_logic; -- Repeated Adress NAK\r
+ signal i2c_byte : std_logic_vector( 8 downto 0 );\r
+ signal i2c_dr : std_logic_vector( 8 downto 0 );\r
+\r
+ signal s_scl : std_logic;\r
+ signal r_scl : std_logic;\r
+ signal s_sda : std_logic;\r
+ signal r_sda : std_logic;\r
+ signal r_scl_gs : std_logic;\r
+ signal s_scl_gs : std_logic;\r
+ signal r_sda_gs : std_logic;\r
+ signal s_sda_gs : std_logic;\r
+ signal r_scl_sb : std_logic;\r
+ signal s_scl_sb : std_logic;\r
+ signal r_sda_sb : std_logic;\r
+ signal s_sda_sb : std_logic;\r
+\r
+ signal gs_debug : std_logic_vector(3 downto 0);\r
+\r
+ signal i2c_speed : std_logic_vector(7 downto 0);\r
+\r
+begin\r
+\r
+i2c_speed <= i2c_speed_in & "00";\r
+\r
+-- Read phase indicator\r
+THE_PHASE_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ phase <= '0';\r
+ elsif( CURRENT_STATE = INC ) then\r
+ phase <= '1';\r
+ elsif( (CURRENT_STATE = DONE) or (CURRENT_STATE = SLEEP) ) then\r
+ phase <= '0';\r
+ end if;\r
+ end if;\r
+end process THE_PHASE_PROC;\r
+\r
+-- The main state machine\r
+-- State memory process\r
+STATE_MEM: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ CURRENT_STATE <= SLEEP;\r
+ start <= '0';\r
+ dostart <= '0';\r
+ dobyte <= '0';\r
+ i2c_done <= '0';\r
+ running <= '0';\r
+ load_a <= '0';\r
+ load_c <= '0';\r
+ load_d <= '0';\r
+ else\r
+ CURRENT_STATE <= NEXT_STATE;\r
+ start <= start_x;\r
+ dostart <= dostart_x;\r
+ dobyte <= dobyte_x;\r
+ i2c_done <= i2c_done_x;\r
+ running <= running_x;\r
+ load_a <= load_a_x;\r
+ load_c <= load_c_x;\r
+ load_d <= load_d_x;\r
+ end if;\r
+ end if;\r
+end process STATE_MEM;\r
+\r
+-- Transition matrix\r
+TRANSFORM: process(CURRENT_STATE, i2c_go_in, sdone, sok, phase, bdone, bok, action_in)\r
+begin\r
+ NEXT_STATE <= SLEEP;\r
+ start_x <= '0';\r
+ dostart_x <= '0';\r
+ dobyte_x <= '0';\r
+ i2c_done_x <= '0';\r
+ running_x <= '1';\r
+ load_a_x <= '0';\r
+ load_c_x <= '0';\r
+ load_d_x <= '0';\r
+ case CURRENT_STATE is\r
+ when SLEEP => if( i2c_go_in = '1' ) then\r
+ NEXT_STATE <= CLRERR;\r
+ else\r
+ NEXT_STATE <= SLEEP;\r
+ running_x <= '0';\r
+ end if;\r
+ when CLRERR => NEXT_STATE <= LOADA;\r
+ load_a_x <= '1';\r
+ when LOADA => NEXT_STATE <= GSTART;\r
+ start_x <= '1';\r
+ dostart_x <= '1';\r
+ when GSTART => if ( (sdone = '1') and (sok = '1') ) then\r
+ NEXT_STATE <= SENDA;\r
+ dobyte_x <= '1';\r
+ elsif( (sdone = '1') and (sok = '0') and (phase = '0') ) then\r
+ NEXT_STATE <= E_START; -- first START condition failed\r
+ elsif( (sdone = '1') and (sok = '0') and (phase = '1') ) then\r
+ NEXT_STATE <= E_RSTART; -- second START condition failed\r
+ else\r
+ NEXT_STATE <= GSTART;\r
+ start_x <= '1';\r
+ dostart_x <= '1';\r
+ end if;\r
+ when E_START => NEXT_STATE <= FAILED;\r
+ dostart_x <= '1';\r
+ when E_RSTART => NEXT_STATE <= FAILED;\r
+ dostart_x <= '1';\r
+ when SENDA => if ( (bdone = '1') and (bok = '1') and (action_in = '0') ) then\r
+ NEXT_STATE <= LOADC; -- I2C write\r
+ load_c_x <= '1'; \r
+ elsif( (bdone = '1') and (bok = '1') and (action_in = '1') and (phase = '0') ) then\r
+ NEXT_STATE <= LOADC; -- I2C read, send register address\r
+ load_c_x <= '1';\r
+ elsif( (bdone = '1') and (bok = '1') and (action_in = '1') and (phase = '1') ) then\r
+ NEXT_STATE <= LOADD; -- I2C read, send 0xff dummy byte\r
+ load_d_x <= '1';\r
+ elsif( (bdone = '1') and (bok = '0') and (phase = '0') ) then\r
+ NEXT_STATE <= E_ADDR; -- first address phase failed\r
+ elsif( (bdone = '1') and (bok = '0') and (phase = '1') ) then\r
+ NEXT_STATE <= E_RADDR; -- second address phase failed\r
+ else\r
+ NEXT_STATE <= SENDA;\r
+ dobyte_x <= '1';\r
+ end if;\r
+ when E_ADDR => NEXT_STATE <= FAILED;\r
+ dostart_x <= '1';\r
+ when E_RADDR => NEXT_STATE <= FAILED;\r
+ dostart_x <= '1';\r
+ when LOADC => NEXT_STATE <= SENDC;\r
+-- dobyte_x <= '1';\r
+ when SENDC => if ( (bdone = '1') and (bok = '1') and (action_in = '0') ) then\r
+ NEXT_STATE <= LOADD; -- I2C write, prepare data\r
+ load_d_x <= '1';\r
+ elsif( (bdone = '1') and (bok = '1') and (action_in = '1') ) then\r
+ NEXT_STATE <= GSTOP; -- I2C read, first phase ends\r
+ dostart_x <= '1';\r
+ elsif( (bdone = '1') and (bok = '0') ) then\r
+ NEXT_STATE <= E_CMD; -- command phase failed\r
+ else\r
+ NEXT_STATE <= SENDC;\r
+ dobyte_x <= '1';\r
+ end if; \r
+ when E_CMD => NEXT_STATE <= FAILED;\r
+ dostart_x <= '1';\r
+ when LOADD => NEXT_STATE <= SENDD;\r
+ when SENDD => if ( (bdone = '1') and (bok = '1') and (action_in = '0') ) then\r
+ NEXT_STATE <= GSTOP; -- I2C write, data phase failed\r
+ dostart_x <= '1';\r
+ elsif( (bdone = '1') and (action_in = '1') ) then\r
+ NEXT_STATE <= GSTOP; -- I2C read, data phase\r
+ dostart_x <= '1'; \r
+ elsif( (bdone = '1') and (bok = '0') and (action_in = '0') ) then\r
+ NEXT_STATE <= E_WD; -- I2C write, data phase failed\r
+ else\r
+ NEXT_STATE <= SENDD;\r
+ dobyte_x <= '1';\r
+ end if;\r
+ when E_WD => NEXT_STATE <= FAILED;\r
+ dostart_x <= '1';\r
+ when GSTOP => if ( (sdone = '1') and (action_in = '0') ) then\r
+ NEXT_STATE <= DONE;\r
+ elsif( (sdone = '1') and (action_in = '1') and (phase = '1') ) then\r
+ NEXT_STATE <= DONE;\r
+ elsif( (sdone = '1') and (action_in = '1') and (phase = '0') ) then\r
+ NEXT_STATE <= INC;\r
+ else\r
+ NEXT_STATE <= GSTOP;\r
+ dostart_x <= '1';\r
+ end if;\r
+ when INC => NEXT_STATE <= LOADA;\r
+ load_a_x <= '1';\r
+ when FAILED => if( sdone = '1' ) then\r
+ NEXT_STATE <= DONE;\r
+ i2c_done_x <= '1';\r
+ running_x <= '0';\r
+ else\r
+ NEXT_STATE <= FAILED;\r
+ dostart_x <= '1';\r
+ end if;\r
+ when DONE => if( i2c_go_in = '1' ) then\r
+ NEXT_STATE <= DONE;\r
+ i2c_done_x <= '1';\r
+ running_x <= '0';\r
+ else\r
+ NEXT_STATE <= SLEEP;\r
+ end if;\r
+ -- Just in case...\r
+ when others => NEXT_STATE <= SLEEP; \r
+ end case;\r
+end process TRANSFORM;\r
+\r
+-- Output decoding\r
+DECODE: process(CURRENT_STATE)\r
+begin\r
+ case CURRENT_STATE is\r
+ when SLEEP => bsm <= b"00000"; -- 00\r
+ when CLRERR => bsm <= b"01100"; -- 0c\r
+ when LOADA => bsm <= b"00001"; -- 01\r
+ when GSTART => bsm <= b"00010"; -- 02\r
+ when SENDA => bsm <= b"00011"; -- 03\r
+ when LOADC => bsm <= b"00100"; -- 04\r
+ when SENDC => bsm <= b"00101"; -- 05\r
+ when LOADD => bsm <= b"00110"; -- 06\r
+ when SENDD => bsm <= b"00111"; -- 07\r
+ when GSTOP => bsm <= b"01000"; -- 08\r
+ when INC => bsm <= b"01001"; -- 09\r
+ when FAILED => bsm <= b"01010"; -- 0a\r
+ when DONE => bsm <= b"01011"; -- 0b\r
+ when E_START => bsm <= b"10000"; -- 10\r
+ when E_RSTART => bsm <= b"10001"; -- 11\r
+ when E_ADDR => bsm <= b"10010"; -- 12\r
+ when E_RADDR => bsm <= b"10011"; -- 13\r
+ when E_CMD => bsm <= b"10100"; -- 14\r
+ when E_WD => bsm <= b"10101"; -- 15\r
+ when others => bsm <= b"11111"; -- 1f\r
+ end case; \r
+end process DECODE;\r
+\r
+-- We need to load different data sets\r
+--LOAD_DATA_PROC: process( clk_in, reset_in, CURRENT_STATE, action_in, phase)\r
+LOAD_DATA_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( reset_in = '1' ) then\r
+ i2c_byte <= (others => '1');\r
+ elsif( (CURRENT_STATE = LOADA) and (phase = '0') ) then\r
+ i2c_byte <= i2c_adr_in(6 downto 0) & '0' & '1'; -- send write address, receive ACK\r
+ elsif( (CURRENT_STATE = LOADA) and (phase = '1') ) then\r
+ i2c_byte <= i2c_adr_in(6 downto 0) & '1' & '1'; -- send read address, receive ACK\r
+ elsif( (CURRENT_STATE = LOADC) and (action_in = '0') ) then\r
+ i2c_byte <= i2c_cmd_in(7 downto 1) & '0' & '1'; -- send command byte (WRITE), receive ACK\r
+ elsif( (CURRENT_STATE = LOADC) and (action_in = '1') ) then\r
+ i2c_byte <= i2c_cmd_in(7 downto 1) & '1' & '1'; -- send command byte (READ), receive ACK\r
+ elsif( (CURRENT_STATE = LOADD) and (action_in = '0') ) then\r
+ i2c_byte <= i2c_dw_in & '1'; -- send data byte, receive ACK\r
+ elsif( (CURRENT_STATE = LOADD) and (action_in = '1') ) then\r
+ i2c_byte <= x"ff" & '1'; -- send 0xff byte, send NACK\r
+ end if;\r
+ end if;\r
+end process LOAD_DATA_PROC;\r
+\r
+-- The SendByte module\r
+THE_I2C_SENDB: I2C_SENDB\r
+port map( CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ DOBYTE_IN => dobyte,\r
+ I2C_SPEED_IN => i2c_speed,\r
+ I2C_BYTE_IN => i2c_byte,\r
+ I2C_BACK_OUT => i2c_dr,\r
+ SDA_IN => sda_in,\r
+ R_SDA_OUT => r_sda_sb,\r
+ S_SDA_OUT => s_sda_sb,\r
+-- SCL_IN => scl_in,\r
+ R_SCL_OUT => r_scl_sb,\r
+ S_SCL_OUT => s_scl_sb,\r
+ BDONE_OUT => bdone,\r
+ BOK_OUT => bok,\r
+ BSM_OUT => open\r
+ );\r
+\r
+-- The GenStart module\r
+THE_I2C_GSTART: I2C_GSTART\r
+port map( CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ START_IN => start,\r
+ DOSTART_IN => dostart,\r
+ I2C_SPEED_IN => i2c_speed,\r
+ SDONE_OUT => sdone,\r
+ SOK_OUT => sok,\r
+ SDA_IN => sda_in,\r
+ SCL_IN => scl_in,\r
+ R_SCL_OUT => r_scl_gs,\r
+ S_SCL_OUT => s_scl_gs,\r
+ R_SDA_OUT => r_sda_gs,\r
+ S_SDA_OUT => s_sda_gs,\r
+ BSM_OUT => gs_debug --open\r
+ );\r
+\r
+r_scl <= r_scl_gs or r_scl_sb;\r
+s_scl <= s_scl_gs or s_scl_sb;\r
+r_sda <= r_sda_gs or r_sda_sb;\r
+s_sda <= s_sda_gs or s_sda_sb;\r
+\r
+-- Output flipflops for SCL and SDA lines\r
+THE_SCL_SDA_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ scl_out <= '1';\r
+ sda_out <= '1';\r
+ elsif( (r_scl = '1') and (s_scl = '0') ) then\r
+ scl_out <= '0';\r
+ elsif( (r_scl = '0') and (s_scl = '1') ) then\r
+ scl_out <= '1';\r
+ elsif( (r_sda = '1') and (s_sda = '0') ) then\r
+ sda_out <= '0';\r
+ elsif( (r_sda = '0') and (s_sda = '1') ) then\r
+ sda_out <= '1';\r
+ end if;\r
+ end if;\r
+end process THE_SCL_SDA_PROC;\r
+\r
+-- Error bits\r
+THE_ERR_REG_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ e_sf <= '0';\r
+ e_anak <= '0';\r
+ e_cnak <= '0';\r
+ e_dnak <= '0';\r
+ e_rsf <= '0';\r
+ e_ranak <= '0';\r
+ elsif( CURRENT_STATE = CLRERR ) then\r
+ e_sf <= '0';\r
+ e_anak <= '0';\r
+ e_cnak <= '0';\r
+ e_dnak <= '0';\r
+ e_rsf <= '0';\r
+ e_ranak <= '0';\r
+ elsif( CURRENT_STATE = E_START ) then\r
+ e_sf <= '1';\r
+ elsif( CURRENT_STATE = E_RSTART ) then\r
+ e_rsf <= '1';\r
+ elsif( CURRENT_STATE = E_ADDR ) then\r
+ e_anak <= '1';\r
+ elsif( CURRENT_STATE = E_RADDR ) then\r
+ e_ranak <= '1';\r
+ elsif( CURRENT_STATE = E_CMD ) then\r
+ e_cnak <= '1';\r
+ elsif( CURRENT_STATE = E_WD ) then\r
+ e_dnak <= '1';\r
+ end if;\r
+ end if;\r
+end process THE_ERR_REG_PROC;\r
+\r
+status_out(7) <= running;\r
+status_out(6) <= i2c_done;\r
+status_out(5) <= e_ranak;\r
+status_out(4) <= e_rsf;\r
+status_out(3) <= e_dnak;\r
+status_out(2) <= e_cnak;\r
+status_out(1) <= e_anak;\r
+status_out(0) <= e_sf;\r
+\r
+-- Outputs \r
+i2c_dr_out <= i2c_dr(8 downto 1);\r
+i2c_busy_out <= running;\r
+\r
+-- Debug stuff\r
+stat(31 downto 28) <= (others => '0');\r
+stat(27) <= s_sda;\r
+stat(26) <= r_sda;\r
+stat(25) <= s_scl;\r
+stat(24) <= r_scl;\r
+stat(23) <= s_sda_sb;\r
+stat(22) <= r_sda_sb;\r
+stat(21) <= s_scl_sb;\r
+stat(20) <= r_scl_sb;\r
+stat(19) <= s_sda_gs;\r
+stat(18) <= r_sda_gs;\r
+stat(17) <= s_scl_gs;\r
+stat(16) <= r_scl_gs;\r
+stat(15 downto 12) <= gs_debug;\r
+stat(11) <= bok;\r
+stat(10) <= bdone;\r
+stat(9) <= dobyte;\r
+stat(8) <= sok;\r
+stat(7) <= dobyte;\r
+stat(6) <= s_sda_sb;\r
+stat(5) <= r_sda_sb;\r
+stat(4 downto 0) <= bsm;\r
+\r
+\r
+end Behavioral;\r
--- /dev/null
+[Device]\r
+Family=latticeecp2m\r
+PartType=LFE2M100E\r
+PartName=LFE2M100E-6F900C\r
+SpeedGrade=-6\r
+Package=FPBGA900\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=RAM_DP\r
+CoreRevision=6.1\r
+ModuleName=input_bram\r
+SourceFormat=VHDL\r
+ParameterFileVersion=1.0\r
+Date=09/14/2009\r
+Time=12:58:01\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+RAddress=2048\r
+RData=18\r
+WAddress=2048\r
+WData=18\r
+enByte=0\r
+ByteSize=9\r
+adPipeline=0\r
+inPipeline=0\r
+outPipeline=1\r
+MOR=0\r
+InData=Registered\r
+AdControl=Registered\r
+MemFile=\r
+MemFormat=hex\r
+Reset=Sync\r
+GSR=Enabled\r
+Pad=0\r
+EnECC=0\r
+Optimization=Speed\r
+EnSleep=ENABLED\r
+Pipeline=0\r
--- /dev/null
+SCUBA, Version ispLever_v72_SP2_Build (23)
+Mon Sep 14 12:58:01 2009
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp. All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
+Copyright (c) 2001 Agere Systems All rights reserved.
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
+
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n input_bram -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -device LFE2M100E -type ramdps -raddr_width 11 -rwidth 18 -waddr_width 11 -wwidth 18 -rnum_words 2048 -wnum_words 2048 -outdata REGISTERED -resetmode SYNC -cascade -1 -e
+ Circuit name : input_bram
+ Module type : RAM_DP
+ Module Version : 6.1
+ Ports :
+ Inputs : WrAddress[10:0], RdAddress[10:0], Data[17:0], WE, RdClock, RdClockEn, Reset, WrClock, WrClockEn
+ Outputs : Q[17:0]
+ I/O buffer : not inserted
+ EDIF output : suppressed
+ VHDL output : input_bram.vhd
+ VHDL template : input_bram_tmpl.vhd
+ VHDL testbench : tb_input_bram_tmpl.vhd
+ VHDL purpose : for synthesis and simulation
+ Bus notation : big endian
+ Report output : input_bram.srp
+ Element Usage :
+ DP16KB : 2
+ Estimated Resource Usage:
+ EBR : 2
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23)
+-- Module Version: 6.1
+--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type bram -wp 10 -rp 0011 -rdata_width 18 -data_width 18 -num_rows 2048 -outdata REGISTERED -resetmode SYNC -cascade -1 -e
+
+-- Mon Sep 14 12:58:01 2009
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity input_bram is
+ port (
+ WrAddress: in std_logic_vector(10 downto 0);
+ RdAddress: in std_logic_vector(10 downto 0);
+ Data: in std_logic_vector(17 downto 0);
+ WE: in std_logic;
+ RdClock: in std_logic;
+ RdClockEn: in std_logic;
+ Reset: in std_logic;
+ WrClock: in std_logic;
+ WrClockEn: in std_logic;
+ Q: out std_logic_vector(17 downto 0));
+end input_bram;
+
+architecture Structure of input_bram is
+
+ -- internal signal declarations
+ signal scuba_vhi: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component DP16KB
+ -- synopsys translate_off
+ generic (GSR : in String; WRITEMODE_B : in String;
+ CSDECODE_B : in std_logic_vector(2 downto 0);
+ CSDECODE_A : in std_logic_vector(2 downto 0);
+ WRITEMODE_A : in String; RESETMODE : in String;
+ REGMODE_B : in String; REGMODE_A : in String;
+ DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer);
+ -- synopsys translate_on
+ port (DIA0: in std_logic; DIA1: in std_logic;
+ DIA2: in std_logic; DIA3: in std_logic;
+ DIA4: in std_logic; DIA5: in std_logic;
+ DIA6: in std_logic; DIA7: in std_logic;
+ DIA8: in std_logic; DIA9: in std_logic;
+ DIA10: in std_logic; DIA11: in std_logic;
+ DIA12: in std_logic; DIA13: in std_logic;
+ DIA14: in std_logic; DIA15: in std_logic;
+ DIA16: in std_logic; DIA17: in std_logic;
+ ADA0: in std_logic; ADA1: in std_logic;
+ ADA2: in std_logic; ADA3: in std_logic;
+ ADA4: in std_logic; ADA5: in std_logic;
+ ADA6: in std_logic; ADA7: in std_logic;
+ ADA8: in std_logic; ADA9: in std_logic;
+ ADA10: in std_logic; ADA11: in std_logic;
+ ADA12: in std_logic; ADA13: in std_logic;
+ CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic;
+ CSA0: in std_logic; CSA1: in std_logic;
+ CSA2: in std_logic; RSTA: in std_logic;
+ DIB0: in std_logic; DIB1: in std_logic;
+ DIB2: in std_logic; DIB3: in std_logic;
+ DIB4: in std_logic; DIB5: in std_logic;
+ DIB6: in std_logic; DIB7: in std_logic;
+ DIB8: in std_logic; DIB9: in std_logic;
+ DIB10: in std_logic; DIB11: in std_logic;
+ DIB12: in std_logic; DIB13: in std_logic;
+ DIB14: in std_logic; DIB15: in std_logic;
+ DIB16: in std_logic; DIB17: in std_logic;
+ ADB0: in std_logic; ADB1: in std_logic;
+ ADB2: in std_logic; ADB3: in std_logic;
+ ADB4: in std_logic; ADB5: in std_logic;
+ ADB6: in std_logic; ADB7: in std_logic;
+ ADB8: in std_logic; ADB9: in std_logic;
+ ADB10: in std_logic; ADB11: in std_logic;
+ ADB12: in std_logic; ADB13: in std_logic;
+ CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic;
+ CSB0: in std_logic; CSB1: in std_logic;
+ CSB2: in std_logic; RSTB: in std_logic;
+ DOA0: out std_logic; DOA1: out std_logic;
+ DOA2: out std_logic; DOA3: out std_logic;
+ DOA4: out std_logic; DOA5: out std_logic;
+ DOA6: out std_logic; DOA7: out std_logic;
+ DOA8: out std_logic; DOA9: out std_logic;
+ DOA10: out std_logic; DOA11: out std_logic;
+ DOA12: out std_logic; DOA13: out std_logic;
+ DOA14: out std_logic; DOA15: out std_logic;
+ DOA16: out std_logic; DOA17: out std_logic;
+ DOB0: out std_logic; DOB1: out std_logic;
+ DOB2: out std_logic; DOB3: out std_logic;
+ DOB4: out std_logic; DOB5: out std_logic;
+ DOB6: out std_logic; DOB7: out std_logic;
+ DOB8: out std_logic; DOB9: out std_logic;
+ DOB10: out std_logic; DOB11: out std_logic;
+ DOB12: out std_logic; DOB13: out std_logic;
+ DOB14: out std_logic; DOB15: out std_logic;
+ DOB16: out std_logic; DOB17: out std_logic);
+ end component;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute CSDECODE_B : string;
+ attribute CSDECODE_A : string;
+ attribute WRITEMODE_B : string;
+ attribute WRITEMODE_A : string;
+ attribute GSR : string;
+ attribute RESETMODE : string;
+ attribute REGMODE_B : string;
+ attribute REGMODE_A : string;
+ attribute DATA_WIDTH_B : string;
+ attribute DATA_WIDTH_A : string;
+ attribute MEM_LPC_FILE of input_bram_0_0_1 : label is "input_bram.lpc";
+ attribute MEM_INIT_FILE of input_bram_0_0_1 : label is "";
+ attribute CSDECODE_B of input_bram_0_0_1 : label is "0b000";
+ attribute CSDECODE_A of input_bram_0_0_1 : label is "0b000";
+ attribute WRITEMODE_B of input_bram_0_0_1 : label is "NORMAL";
+ attribute WRITEMODE_A of input_bram_0_0_1 : label is "NORMAL";
+ attribute GSR of input_bram_0_0_1 : label is "DISABLED";
+ attribute RESETMODE of input_bram_0_0_1 : label is "SYNC";
+ attribute REGMODE_B of input_bram_0_0_1 : label is "OUTREG";
+ attribute REGMODE_A of input_bram_0_0_1 : label is "OUTREG";
+ attribute DATA_WIDTH_B of input_bram_0_0_1 : label is "9";
+ attribute DATA_WIDTH_A of input_bram_0_0_1 : label is "9";
+ attribute MEM_LPC_FILE of input_bram_0_1_0 : label is "input_bram.lpc";
+ attribute MEM_INIT_FILE of input_bram_0_1_0 : label is "";
+ attribute CSDECODE_B of input_bram_0_1_0 : label is "0b000";
+ attribute CSDECODE_A of input_bram_0_1_0 : label is "0b000";
+ attribute WRITEMODE_B of input_bram_0_1_0 : label is "NORMAL";
+ attribute WRITEMODE_A of input_bram_0_1_0 : label is "NORMAL";
+ attribute GSR of input_bram_0_1_0 : label is "DISABLED";
+ attribute RESETMODE of input_bram_0_1_0 : label is "SYNC";
+ attribute REGMODE_B of input_bram_0_1_0 : label is "OUTREG";
+ attribute REGMODE_A of input_bram_0_1_0 : label is "OUTREG";
+ attribute DATA_WIDTH_B of input_bram_0_1_0 : label is "9";
+ attribute DATA_WIDTH_A of input_bram_0_1_0 : label is "9";
+
+begin
+ -- component instantiation statements
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ input_bram_0_0_1: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>WrAddress(0),
+ ADA4=>WrAddress(1), ADA5=>WrAddress(2), ADA6=>WrAddress(3),
+ ADA7=>WrAddress(4), ADA8=>WrAddress(5), ADA9=>WrAddress(6),
+ ADA10=>WrAddress(7), ADA11=>WrAddress(8),
+ ADA12=>WrAddress(9), ADA13=>WrAddress(10), CEA=>WrClockEn,
+ CLKA=>WrClock, WEA=>WE, CSA0=>scuba_vlo, CSA1=>scuba_vlo,
+ CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
+ DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
+ DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
+ DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
+ DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
+ DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
+ DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
+ ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>RdAddress(0),
+ ADB4=>RdAddress(1), ADB5=>RdAddress(2), ADB6=>RdAddress(3),
+ ADB7=>RdAddress(4), ADB8=>RdAddress(5), ADB9=>RdAddress(6),
+ ADB10=>RdAddress(7), ADB11=>RdAddress(8),
+ ADB12=>RdAddress(9), ADB13=>RdAddress(10), CEB=>RdClockEn,
+ CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>scuba_vlo,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(0),
+ DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), DOB4=>Q(4), DOB5=>Q(5),
+ DOB6=>Q(6), DOB7=>Q(7), DOB8=>Q(8), DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ DOB15=>open, DOB16=>open, DOB17=>open);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ input_bram_0_1_0: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
+ DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
+ DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>WrAddress(0), ADA4=>WrAddress(1), ADA5=>WrAddress(2),
+ ADA6=>WrAddress(3), ADA7=>WrAddress(4), ADA8=>WrAddress(5),
+ ADA9=>WrAddress(6), ADA10=>WrAddress(7), ADA11=>WrAddress(8),
+ ADA12=>WrAddress(9), ADA13=>WrAddress(10), CEA=>WrClockEn,
+ CLKA=>WrClock, WEA=>WE, CSA0=>scuba_vlo, CSA1=>scuba_vlo,
+ CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
+ DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
+ DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
+ DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
+ DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
+ DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
+ DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
+ ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>RdAddress(0),
+ ADB4=>RdAddress(1), ADB5=>RdAddress(2), ADB6=>RdAddress(3),
+ ADB7=>RdAddress(4), ADB8=>RdAddress(5), ADB9=>RdAddress(6),
+ ADB10=>RdAddress(7), ADB11=>RdAddress(8),
+ ADB12=>RdAddress(9), ADB13=>RdAddress(10), CEB=>RdClockEn,
+ CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>scuba_vlo,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(9),
+ DOB1=>Q(10), DOB2=>Q(11), DOB3=>Q(12), DOB4=>Q(13),
+ DOB5=>Q(14), DOB6=>Q(15), DOB7=>Q(16), DOB8=>Q(17),
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ DOB17=>open);
+
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of input_bram is
+ for Structure
+ for all:VHI use entity ecp2m.VHI(V); end for;
+ for all:VLO use entity ecp2m.VLO(V); end for;
+ for all:DP16KB use entity ecp2m.DP16KB(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+Starting process: \r
+\r
+SCUBA, Version ispLever_v72_SP2_Build (23)\r
+Mon Sep 14 12:58:01 2009\r
+\r
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
+Copyright (c) 1995 AT&T Corp. All rights reserved.\r
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
+Copyright (c) 2001 Agere Systems All rights reserved.\r
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
+\r
+BEGIN SCUBA Module Synthesis\r
+\r
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n input_bram -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -device LFE2M100E -type ramdps -raddr_width 11 -rwidth 18 -waddr_width 11 -wwidth 18 -rnum_words 2048 -wnum_words 2048 -outdata REGISTERED -resetmode SYNC -cascade -1 -e \r
+ Circuit name : input_bram\r
+ Module type : RAM_DP\r
+ Module Version : 6.1\r
+ Ports : \r
+ Inputs : WrAddress[10:0], RdAddress[10:0], Data[17:0], WE, RdClock, RdClockEn, Reset, WrClock, WrClockEn\r
+ Outputs : Q[17:0]\r
+ I/O buffer : not inserted\r
+ EDIF output : suppressed\r
+ VHDL output : input_bram.vhd\r
+ VHDL template : input_bram_tmpl.vhd\r
+ VHDL testbench : tb_input_bram_tmpl.vhd\r
+ VHDL purpose : for synthesis and simulation\r
+ Bus notation : big endian\r
+ Report output : input_bram.srp\r
+ Estimated Resource Usage:\r
+ EBR : 2\r
+\r
+END SCUBA Module Synthesis\r
+\r
+File: ..\src\input_bram.lpc created.\r
+\r
+\r
+End process: completed successfully.\r
+\r
+\r
+Total Warnings: 0\r
+\r
+Total Errors: 0\r
+\r
+\r
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23)
+-- Module Version: 6.1
+-- Mon Sep 14 12:58:01 2009
+
+-- parameterized module component declaration
+component input_bram
+ port (WrAddress: in std_logic_vector(10 downto 0);
+ RdAddress: in std_logic_vector(10 downto 0);
+ Data: in std_logic_vector(17 downto 0); WE: in std_logic;
+ RdClock: in std_logic; RdClockEn: in std_logic;
+ Reset: in std_logic; WrClock: in std_logic;
+ WrClockEn: in std_logic; Q: out std_logic_vector(17 downto 0));
+end component;
+
+-- parameterized module component instance
+__ : input_bram
+ port map (WrAddress(10 downto 0)=>__, RdAddress(10 downto 0)=>__,
+ Data(17 downto 0)=>__, WE=>__, RdClock=>__, RdClockEn=>__, Reset=>__,
+ WrClock=>__, WrClockEn=>__, Q(17 downto 0)=>__);
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.std_logic_arith.all;\r
+use ieee.std_logic_unsigned.all;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+-- Missing: FIFO buffer handling, full / empty checks\r
+\r
+entity ipu_fifo_stage is\r
+ port( CLK_IN : in std_logic; -- 100MHz local clock\r
+ RESET_IN : in std_logic; -- synchronous reset\r
+ -- Slow control signals \r
+ SECTOR_IN : in std_logic_vector(2 downto 0);\r
+ MODULE_IN : in std_logic_vector(2 downto 0);\r
+ -- IPU channel connections\r
+ IPU_NUMBER_IN : in std_logic_vector(15 downto 0); -- trigger tag\r
+ IPU_INFORMATION_IN : in std_logic_vector(7 downto 0); -- trigger information\r
+ IPU_START_READOUT_IN : in std_logic; -- gimme data!\r
+ IPU_DATA_OUT : out std_logic_vector(31 downto 0); -- detector data, equipped with DHDR\r
+ IPU_DATAREADY_OUT : out std_logic; -- data is valid\r
+ IPU_READOUT_FINISHED_OUT : out std_logic; -- no more data, end transfer, send TRM\r
+ IPU_READ_IN : in std_logic; -- read strobe, low every second cycle \r
+ IPU_LENGTH_OUT : out std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?)\r
+ IPU_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); -- error pattern\r
+ LVL2_COUNTER_OUT : out std_logic_vector(15 downto 0); -- local IPU cycle counter\r
+ -- DHDR buffer input\r
+ DHDR_DATA_IN : in std_logic_vector(31 downto 0);\r
+ DHDR_LENGTH_IN : in std_logic_vector(15 downto 0);\r
+ DHDR_STORE_IN : in std_logic;\r
+ DHDR_BUF_FULL_OUT : out std_logic;\r
+ -- processed data input\r
+ FIFO_START_IN : in std_logic;\r
+ FIFO_0_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_1_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_2_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_3_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_4_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_5_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_6_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_7_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_8_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_9_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_10_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_11_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_12_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_13_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_14_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_15_DATA_IN : in std_logic_vector(39 downto 0);\r
+ FIFO_WE_IN : in std_logic_vector(15 downto 0);\r
+ FIFO_DONE_IN : in std_logic; -- write level information into small FIFOs\r
+ -- Debug signals\r
+ DBG_BSM_OUT : out std_logic_vector(7 downto 0);\r
+ DBG_OUT : out std_logic_vector(63 downto 0)\r
+ );\r
+end;\r
+\r
+architecture behavioral of ipu_fifo_stage is\r
+\r
+ -- Placer Directives\r
+ attribute HGROUP : string;\r
+ -- for whole architecture\r
+ attribute HGROUP of behavioral : architecture is "IPU_FIFO_STAGE_group";\r
+\r
+ -- state machine definitions\r
+ type STATES is (SLEEP,RDLF,GETFD,DELH,WHDR,GETD,WAITD,WAITDL,DEL0,DONE); \r
+ signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+ -- signals\r
+ signal debug : std_logic_vector(63 downto 0);\r
+ signal bsm_x : std_logic_vector(7 downto 0);\r
+ signal next_trgnum_match : std_logic;\r
+ signal trgnum_match : std_logic;\r
+\r
+ signal dhdr_fifo_in : std_logic_vector(47 downto 0);\r
+ signal dhdr_fifo_out : std_logic_vector(47 downto 0);\r
+ signal dhdr_avail : std_logic;\r
+ signal next_todo_list : std_logic_vector(15 downto 0);\r
+ signal todo_list : std_logic_vector(15 downto 0);\r
+ signal next_fifo_sel : std_logic_vector(4 downto 0);\r
+ signal fifo_sel : std_logic_vector(4 downto 0);\r
+ signal next_sel_fifo : std_logic_vector(15 downto 0);\r
+ signal sel_fifo : std_logic_vector(15 downto 0);\r
+\r
+ signal comb_rd_dfifo : std_logic_vector(15 downto 0);\r
+ signal comb_st_data : std_logic_vector(15 downto 0);\r
+ signal comb_ack_todo : std_logic;\r
+\r
+ signal ipu_out_data : std_logic_vector(31 downto 0);\r
+\r
+ -- state machine signals\r
+ signal next_rd_lfifo : std_logic;\r
+ signal rd_lfifo : std_logic; -- read current LENGTH_FIFO information (as well as LockAtMe bit)\r
+ signal next_dataready : std_logic;\r
+ signal dataready : std_logic; -- data word is available\r
+ signal next_set_hdr : std_logic;\r
+ signal set_hdr : std_logic; -- store DHDR in output register\r
+ signal next_set_data : std_logic;\r
+ signal set_data : std_logic; -- store DATA from current DATA FIFO in output register\r
+ signal next_ld_todo : std_logic;\r
+ signal ld_todo : std_logic; -- load initial TODO list\r
+ signal next_ack_todo : std_logic;\r
+ signal ack_todo : std_logic; -- remove current entry from TODO list\r
+ signal next_finished : std_logic;\r
+ signal finished : std_logic; -- readout is finished\r
+\r
+ -- generate needs arrays...\r
+ type fifo_data_t is array (0 to 15) of std_logic_vector(26 downto 0);\r
+ signal fifo_in_data : fifo_data_t;\r
+ signal fifo_out_data : fifo_data_t;\r
+ type fifo_count_t is array (0 to 15) of std_logic_vector(10 downto 0);\r
+ signal fifo_in_count : fifo_count_t;\r
+ type fifo_todo_t is array (0 to 15) of std_logic_vector(9 downto 0);\r
+ signal fifo_todo : fifo_todo_t;\r
+ type fifo_ldata_t is array (0 to 15) of std_logic_vector(10 downto 0);\r
+ signal fifo_ldata : fifo_ldata_t;\r
+ type fifo_wcnt_t is array (0 to 15) of std_logic_vector(11 downto 0);\r
+ signal fifo_wcnt : fifo_wcnt_t;\r
+ signal fifo_data_free : fifo_wcnt_t;\r
+\r
+ \r
+ signal next_fifo_done : std_logic_vector(15 downto 0);\r
+ signal fifo_done : std_logic_vector(15 downto 0);\r
+ signal next_fifo_last : std_logic;\r
+ signal fifo_last : std_logic;\r
+ \r
+ signal my_trg_number : std_logic_vector(31 downto 0); -- just for checking!\r
+ \r
+ signal old_apv_num : std_logic_vector(3 downto 0);\r
+ signal new_apv_num : std_logic_vector(3 downto 0);\r
+\r
+ signal cyclectr : std_logic_vector(15 downto 0); -- cycle counter\r
+\r
+ signal dhdr_buf_full : std_logic;\r
+ \r
+begin\r
+---------------------------------------------------------------------------\r
+-- Statemachine\r
+---------------------------------------------------------------------------\r
+\r
+-- state registers\r
+STATE_MEM: process( clk_in ) \r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ CURRENT_STATE <= SLEEP;\r
+ rd_lfifo <= '0';\r
+ dataready <= '0';\r
+ set_hdr <= '0';\r
+ set_data <= '0';\r
+ ld_todo <= '0';\r
+ ack_todo <= '0';\r
+ finished <= '0';\r
+ else\r
+ CURRENT_STATE <= NEXT_STATE;\r
+ rd_lfifo <= next_rd_lfifo;\r
+ dataready <= next_dataready;\r
+ set_hdr <= next_set_hdr;\r
+ set_data <= next_set_data;\r
+ ld_todo <= next_ld_todo;\r
+ ack_todo <= next_ack_todo;\r
+ finished <= next_finished;\r
+ end if;\r
+ end if;\r
+end process STATE_MEM;\r
+\r
+-- state transitions\r
+STATE_TRANSFORM: process( CURRENT_STATE, dhdr_avail, ipu_start_readout_in, ipu_read_in, fifo_last, fifo_sel(4) )\r
+begin\r
+ NEXT_STATE <= SLEEP; -- avoid latches\r
+ next_rd_lfifo <= '0';\r
+ next_dataready <= '0';\r
+ next_set_hdr <= '0';\r
+ next_set_data <= '0';\r
+ next_ld_todo <= '0';\r
+ next_ack_todo <= '0';\r
+ next_finished <= '0';\r
+ case CURRENT_STATE is\r
+ when SLEEP => if( (dhdr_avail = '1') and (ipu_start_readout_in = '1') ) then\r
+ NEXT_STATE <= RDLF;\r
+ next_rd_lfifo <= '1';\r
+ else\r
+ NEXT_STATE <= SLEEP;\r
+ end if;\r
+ when RDLF => NEXT_STATE <= GETFD;\r
+ next_set_hdr <= '1';\r
+ next_ld_todo <= '1';\r
+ when GETFD => NEXT_STATE <= DELH;\r
+ when DELH => NEXT_STATE <= WHDR;\r
+ next_dataready <= '1';\r
+ when WHDR => if ( (ipu_read_in = '1') and (fifo_sel(4) = '0') ) then\r
+ NEXT_STATE <= GETD; -- there are datawords to send\r
+ next_set_data <= '1';\r
+ next_ack_todo <= '1';\r
+ elsif( (ipu_read_in = '1') and (fifo_sel(4) = '1') ) then\r
+ NEXT_STATE <= DONE; -- only DHDR, no data words\r
+ next_finished <= '1';\r
+ else\r
+ NEXT_STATE <= WHDR;\r
+ next_dataready <= '1';\r
+ end if;\r
+ when GETD => if( fifo_last = '1' ) then\r
+ NEXT_STATE <= DEL0;\r
+ else \r
+ NEXT_STATE <= WAITD;\r
+ next_dataready <= '1';\r
+ end if;\r
+ when WAITD => if( ipu_read_in = '1' ) then\r
+ NEXT_STATE <= GETD;\r
+ next_set_data <= '1';\r
+ else\r
+ NEXT_STATE <= WAITD;\r
+ next_dataready <= '1';\r
+ end if;\r
+ when DEL0 => NEXT_STATE <= WAITDL;\r
+ next_dataready <= '1';\r
+ when WAITDL => if ( (ipu_read_in = '1') and (fifo_sel(4) = '0') ) then\r
+ NEXT_STATE <= GETD;\r
+ next_set_data <= '1';\r
+ next_ack_todo <= '1';\r
+ elsif( (ipu_read_in = '1') and (fifo_sel(4) = '1') ) then\r
+ NEXT_STATE <= DONE;\r
+ next_finished <= '1';\r
+ else\r
+ NEXT_STATE <= WAITDL;\r
+ next_dataready <= '1';\r
+ end if;\r
+ when DONE => if( ipu_start_readout_in = '0' ) then\r
+ NEXT_STATE <= SLEEP;\r
+ else\r
+ NEXT_STATE <= DONE;\r
+ end if;\r
+\r
+ when others => NEXT_STATE <= SLEEP;\r
+ end case;\r
+end process STATE_TRANSFORM;\r
+\r
+-- Handshaking to IPU data channel\r
+ipu_dataready_out <= dataready;\r
+ipu_readout_finished_out <= finished;\r
+\r
+-- length information can be simply copied\r
+ipu_length_out <= dhdr_fifo_out(47 downto 32);\r
+\r
+-- IPU error pattern: [24] => trigger tag mismatch\r
+ipu_error_pattern_out(31 downto 25) <= (others => '0');\r
+ipu_error_pattern_out(24) <= not trgnum_match;\r
+ipu_error_pattern_out(23 downto 0) <= (others => '0');\r
+\r
+-- state decoding (ONLY FOR DEBUGGING!)\r
+STATE_DECODE: process( CURRENT_STATE )\r
+begin\r
+ case CURRENT_STATE is\r
+ when SLEEP => bsm_x <= x"00";\r
+ when RDLF => bsm_x <= x"01";\r
+ when GETFD => bsm_x <= x"02";\r
+ when DELH => bsm_x <= x"03";\r
+ when WHDR => bsm_x <= x"04";\r
+ when GETD => bsm_x <= x"05";\r
+ when WAITD => bsm_x <= x"06";\r
+ when WAITDL => bsm_x <= x"07";\r
+ when DEL0 => bsm_x <= x"08";\r
+ when DONE => bsm_x <= x"09";\r
+ when others => bsm_x <= x"ff";\r
+ end case;\r
+end process STATE_DECODE;\r
+\r
+---------------------------------------------------------------------------\r
+-- Aliasing the data streams\r
+---------------------------------------------------------------------------\r
+fifo_in_data(0) <= fifo_0_data_in(26 downto 0); fifo_in_count(0) <= fifo_0_data_in(37 downto 27);\r
+fifo_in_data(1) <= fifo_1_data_in(26 downto 0); fifo_in_count(1) <= fifo_1_data_in(37 downto 27);\r
+fifo_in_data(2) <= fifo_2_data_in(26 downto 0); fifo_in_count(2) <= fifo_2_data_in(37 downto 27);\r
+fifo_in_data(3) <= fifo_3_data_in(26 downto 0); fifo_in_count(3) <= fifo_3_data_in(37 downto 27);\r
+fifo_in_data(4) <= fifo_4_data_in(26 downto 0); fifo_in_count(4) <= fifo_4_data_in(37 downto 27);\r
+fifo_in_data(5) <= fifo_5_data_in(26 downto 0); fifo_in_count(5) <= fifo_5_data_in(37 downto 27);\r
+fifo_in_data(6) <= fifo_6_data_in(26 downto 0); fifo_in_count(6) <= fifo_6_data_in(37 downto 27);\r
+fifo_in_data(7) <= fifo_7_data_in(26 downto 0); fifo_in_count(7) <= fifo_7_data_in(37 downto 27);\r
+fifo_in_data(8) <= fifo_8_data_in(26 downto 0); fifo_in_count(8) <= fifo_8_data_in(37 downto 27);\r
+fifo_in_data(9) <= fifo_9_data_in(26 downto 0); fifo_in_count(9) <= fifo_9_data_in(37 downto 27);\r
+fifo_in_data(10) <= fifo_10_data_in(26 downto 0); fifo_in_count(10) <= fifo_10_data_in(37 downto 27);\r
+fifo_in_data(11) <= fifo_11_data_in(26 downto 0); fifo_in_count(11) <= fifo_11_data_in(37 downto 27);\r
+fifo_in_data(12) <= fifo_12_data_in(26 downto 0); fifo_in_count(12) <= fifo_12_data_in(37 downto 27);\r
+fifo_in_data(13) <= fifo_13_data_in(26 downto 0); fifo_in_count(13) <= fifo_13_data_in(37 downto 27);\r
+fifo_in_data(14) <= fifo_14_data_in(26 downto 0); fifo_in_count(14) <= fifo_14_data_in(37 downto 27);\r
+fifo_in_data(15) <= fifo_15_data_in(26 downto 0); fifo_in_count(15) <= fifo_15_data_in(37 downto 27);\r
+\r
+---------------------------------------------------------------------------\r
+-- DATA and LENGTH FIFO for the APV data streams\r
+---------------------------------------------------------------------------\r
+\r
+GEN_FIFO: for i in 0 to 15 generate\r
+ THE_DFIFO: fifo_2kx27\r
+ port map( DATA => fifo_in_data(i),\r
+ CLOCK => clk_in, \r
+ WREN => fifo_we_in(i), \r
+ RDEN => comb_rd_dfifo(i), -- BUG\r
+ RESET => reset_in, \r
+ Q => fifo_out_data(i), -- BUG\r
+ WCNT => fifo_wcnt(i), -- BUG\r
+ EMPTY => open, -- BUG\r
+ FULL => open -- BUG\r
+ );\r
+\r
+ -- Combinatorial read pulse for FIFOs\r
+ comb_rd_dfifo(i) <= (not fifo_done(i) and sel_fifo(i) and ipu_read_in and dataready) or (ld_todo and fifo_ldata(i)(10)); \r
+\r
+ -- Combinatorial store pulse for data (last data word need to be transfered also!)\r
+ comb_st_data(i) <= (sel_fifo(i) and ipu_read_in and dataready);\r
+ -- BUGBUGBUG: one clock cycle too late when changing FIFOs....\r
+\r
+ -- getting the number of free entries in the data fifo by subtracting [size] - [used entries]\r
+ THE_SUBTRACTOR: suber_12bit\r
+ port map( DATAA => x"800",\r
+ DATAB => fifo_wcnt(i),\r
+ CLOCK => clk_in,\r
+ RESET => reset_in,\r
+ CLOCKEN => '1',\r
+ RESULT => fifo_data_free(i)\r
+ );\r
+\r
+ -- length fifo - stores the number of words to fetch from dfifo\r
+ THE_LFIFO: fifo_16x11\r
+ port map( DATA => fifo_in_count(i), \r
+ CLOCK => clk_in,\r
+ WREN => fifo_done_in, \r
+ RDEN => rd_lfifo,\r
+ RESET => reset_in, \r
+ Q => fifo_ldata(i), \r
+ WCNT => open, -- BUG\r
+ EMPTY => open, -- BUG\r
+ FULL => open -- BUG\r
+ );\r
+ next_todo_list(i) <= fifo_ldata(i)(10);\r
+\r
+ THE_TODO_CTR_PROC: process( clk_in )\r
+ begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( (reset_in = '1') or (rd_lfifo = '1') ) then\r
+ fifo_todo(i) <= (others => '0');\r
+ elsif( ld_todo = '1' ) then\r
+ fifo_todo(i) <= fifo_ldata(i)(9 downto 0);\r
+ elsif( comb_rd_dfifo(i) = '1' ) then\r
+ fifo_todo(i) <= fifo_todo(i) - 1;\r
+ end if;\r
+ end if;\r
+ end process THE_TODO_CTR_PROC;\r
+\r
+ next_fifo_done(i) <= '1' when ( fifo_todo(i) = b"00_0000_0000" ) else '0';\r
+\r
+end generate GEN_FIFO;\r
+\r
+comb_ack_todo <= fifo_last and set_data;\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- DHDR buffer - delivers all information\r
+---------------------------------------------------------------------------\r
+dhdr_fifo_in <= dhdr_length_in & dhdr_data_in;\r
+\r
+THE_DHDR_BUF: dhdr_buf\r
+port map( CLK_IN => clk_in,\r
+ RESET_IN => reset_in, \r
+ DHDR_DATA_IN => dhdr_fifo_in,\r
+ DHDR_WE_IN => dhdr_store_in,\r
+ DHDR_DONE_IN => finished,\r
+ DHDR_DATA_OUT => dhdr_fifo_out,\r
+ DHDR_AVAILABLE_OUT => dhdr_avail,\r
+ BUF_FULL_OUT => dhdr_buf_full,\r
+ BUF_LEVEL_OUT => open,\r
+ DEBUG_OUT => open\r
+ );\r
+\r
+-- compare incoming trigger number with stored DHDR information\r
+next_trgnum_match <= '1' when ( ipu_number_in = dhdr_fifo_out(15 downto 0) ) else '0';\r
+\r
+THE_TRGNUM_MATCH_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ trgnum_match <= '0';\r
+ my_trg_number <= (others => '0');\r
+ elsif( set_hdr = '1' ) then\r
+ trgnum_match <= next_trgnum_match;\r
+ my_trg_number <= ipu_number_in & dhdr_fifo_out(15 downto 0);\r
+ end if;\r
+ end if;\r
+end process THE_TRGNUM_MATCH_PROC;\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- priority encoding is used to select the next buffer for readout\r
+---------------------------------------------------------------------------\r
+--THE_PRI_ENCODER_PROC: process( todo_list, fifo_sel, fifo_done )\r
+THE_PRI_ENCODER_PROC: process( todo_list, fifo_done )\r
+begin\r
+ if ( todo_list(15 downto 15) = "1" ) then\r
+ next_fifo_sel <= "01111"; next_sel_fifo <= b"1000_0000_0000_0000"; next_fifo_last <= fifo_done(15);\r
+ elsif( todo_list(15 downto 14) = "01" ) then\r
+ next_fifo_sel <= "01110"; next_sel_fifo <= b"0100_0000_0000_0000"; next_fifo_last <= fifo_done(14);\r
+ elsif( todo_list(15 downto 13) = "001" ) then\r
+ next_fifo_sel <= "01101"; next_sel_fifo <= b"0010_0000_0000_0000"; next_fifo_last <= fifo_done(13);\r
+ elsif( todo_list(15 downto 12) = "0001" ) then\r
+ next_fifo_sel <= "01100"; next_sel_fifo <= b"0001_0000_0000_0000"; next_fifo_last <= fifo_done(12);\r
+ elsif( todo_list(15 downto 11) = "00001" ) then\r
+ next_fifo_sel <= "01011"; next_sel_fifo <= b"0000_1000_0000_0000"; next_fifo_last <= fifo_done(11);\r
+ elsif( todo_list(15 downto 10) = "000001" ) then\r
+ next_fifo_sel <= "01010"; next_sel_fifo <= b"0000_0100_0000_0000"; next_fifo_last <= fifo_done(10);\r
+ elsif( todo_list(15 downto 9) = "0000001" ) then\r
+ next_fifo_sel <= "01001"; next_sel_fifo <= b"0000_0010_0000_0000"; next_fifo_last <= fifo_done(9);\r
+ elsif( todo_list(15 downto 8) = "00000001" ) then\r
+ next_fifo_sel <= "01000"; next_sel_fifo <= b"0000_0001_0000_0000"; next_fifo_last <= fifo_done(8);\r
+ elsif( todo_list(15 downto 7) = "000000001" ) then\r
+ next_fifo_sel <= "00111"; next_sel_fifo <= b"0000_0000_1000_0000"; next_fifo_last <= fifo_done(7);\r
+ elsif( todo_list(15 downto 6) = "0000000001" ) then\r
+ next_fifo_sel <= "00110"; next_sel_fifo <= b"0000_0000_0100_0000"; next_fifo_last <= fifo_done(6);\r
+ elsif( todo_list(15 downto 5) = "00000000001" ) then\r
+ next_fifo_sel <= "00101"; next_sel_fifo <= b"0000_0000_0010_0000"; next_fifo_last <= fifo_done(5);\r
+ elsif( todo_list(15 downto 4) = "000000000001" ) then\r
+ next_fifo_sel <= "00100"; next_sel_fifo <= b"0000_0000_0001_0000"; next_fifo_last <= fifo_done(4);\r
+ elsif( todo_list(15 downto 3) = "0000000000001" ) then\r
+ next_fifo_sel <= "00011"; next_sel_fifo <= b"0000_0000_0000_1000"; next_fifo_last <= fifo_done(3);\r
+ elsif( todo_list(15 downto 2) = "00000000000001" ) then\r
+ next_fifo_sel <= "00010"; next_sel_fifo <= b"0000_0000_0000_0100"; next_fifo_last <= fifo_done(2);\r
+ elsif( todo_list(15 downto 1) = "000000000000001" ) then\r
+ next_fifo_sel <= "00001"; next_sel_fifo <= b"0000_0000_0000_0010"; next_fifo_last <= fifo_done(1);\r
+ elsif( todo_list(15 downto 0) = "0000000000000001" ) then\r
+ next_fifo_sel <= "00000"; next_sel_fifo <= b"0000_0000_0000_0001"; next_fifo_last <= fifo_done(0);\r
+ else\r
+ next_fifo_sel <= "10000"; next_sel_fifo <= b"0000_0000_0000_0000"; next_fifo_last <= '0';\r
+ end if;\r
+end process THE_PRI_ENCODER_PROC;\r
+\r
+-- We need to clear single bits during readout here!!!\r
+THE_TODO_LIST_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ todo_list <= (others => '0');\r
+ elsif( ld_todo = '1' ) then\r
+ todo_list <= next_todo_list; -- store initial todo list\r
+ elsif( comb_ack_todo = '1' ) then\r
+ todo_list <= todo_list and not sel_fifo; -- does this work?!?\r
+ end if;\r
+ end if;\r
+end process THE_TODO_LIST_PROC;\r
+\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- synchronizing process\r
+---------------------------------------------------------------------------\r
+THE_SYNC_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ fifo_sel <= next_fifo_sel;\r
+ sel_fifo <= next_sel_fifo;\r
+ fifo_done <= next_fifo_done;\r
+ fifo_last <= next_fifo_last;\r
+ end if;\r
+end process THE_SYNC_PROC;\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- backplane wise APV mapping \r
+---------------------------------------------------------------------------\r
+old_apv_num <= fifo_sel(3 downto 0); \r
+\r
+THE_ADC_APV_MAP_MEM: adc_apv_map_mem\r
+port map( ADDRESS(6 downto 4) => module_in(2 downto 0),\r
+ ADDRESS(3 downto 0) => old_apv_num, \r
+ Q => new_apv_num\r
+ );\r
+\r
+---------------------------------------------------------------------------\r
+-- Data multiplexer\r
+---------------------------------------------------------------------------\r
+THE_DATA_MUX_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( set_hdr = '1' ) then\r
+ ipu_out_data <= dhdr_fifo_out(31 downto 0);\r
+ elsif( comb_st_data(0) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(0)(21) & sector_in(2 downto 0) & module_in(2 downto 0) & new_apv_num & fifo_out_data(0)(20 downto 0);\r
+ elsif( comb_st_data(1) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(1)(21) & sector_in(2 downto 0) & module_in(2 downto 0) & new_apv_num & fifo_out_data(1)(20 downto 0);\r
+ elsif( comb_st_data(2) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(2)(21) & sector_in(2 downto 0) & module_in(2 downto 0) & new_apv_num & fifo_out_data(2)(20 downto 0);\r
+ elsif( comb_st_data(3) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(3)(21) & sector_in(2 downto 0) & module_in(2 downto 0) & new_apv_num & fifo_out_data(3)(20 downto 0);\r
+ elsif( comb_st_data(4) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(4)(21) & sector_in(2 downto 0) & module_in(2 downto 0) & new_apv_num & fifo_out_data(4)(20 downto 0);\r
+ elsif( comb_st_data(5) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(5)(21) & sector_in(2 downto 0) & module_in(2 downto 0) & new_apv_num & fifo_out_data(5)(20 downto 0);\r
+ elsif( comb_st_data(6) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(6)(21) & sector_in(2 downto 0) & module_in(2 downto 0) & new_apv_num & fifo_out_data(6)(20 downto 0);\r
+ elsif( comb_st_data(7) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(7)(21) & sector_in(2 downto 0) & module_in(2 downto 0) & new_apv_num & fifo_out_data(7)(20 downto 0);\r
+ elsif( comb_st_data(8) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(8)(21) & sector_in(2 downto 0) & module_in(2 downto 0) & new_apv_num & fifo_out_data(8)(20 downto 0);\r
+ elsif( comb_st_data(9) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(9)(21) & sector_in(2 downto 0) & module_in(2 downto 0) & new_apv_num & fifo_out_data(9)(20 downto 0);\r
+ elsif( comb_st_data(10) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(10)(21) & sector_in(2 downto 0) & module_in(2 downto 0) & new_apv_num & fifo_out_data(10)(20 downto 0);\r
+ elsif( comb_st_data(11) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(11)(21) & sector_in(2 downto 0) & module_in(2 downto 0) & new_apv_num & fifo_out_data(11)(20 downto 0);\r
+ elsif( comb_st_data(12) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(12)(21) & sector_in(2 downto 0) & module_in(2 downto 0) & new_apv_num & fifo_out_data(12)(20 downto 0);\r
+ elsif( comb_st_data(13) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(13)(21) & sector_in(2 downto 0) & module_in(2 downto 0) & new_apv_num & fifo_out_data(13)(20 downto 0);\r
+ elsif( comb_st_data(14) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(14)(21) & sector_in(2 downto 0) & module_in(2 downto 0) & new_apv_num & fifo_out_data(14)(20 downto 0);\r
+ elsif( comb_st_data(15) = '1' ) then\r
+ ipu_out_data <= fifo_out_data(15)(21) & sector_in(2 downto 0) & module_in(2 downto 0) & new_apv_num & fifo_out_data(15)(20 downto 0);\r
+ end if;\r
+ end if;\r
+end process THE_DATA_MUX_PROC;\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- IPU cycle counter... just to be sure\r
+---------------------------------------------------------------------------\r
+THE_CYCLE_COUNTER_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ cyclectr <= (others => '0');\r
+ elsif( finished = '1' ) then\r
+ cyclectr <= cyclectr + 1;\r
+ end if;\r
+ end if;\r
+end process THE_CYCLE_COUNTER_PROC;\r
+\r
+---------------------------------------------------------------------------\r
+-- debug information\r
+---------------------------------------------------------------------------\r
+debug(63 downto 28) <= (others => '0');\r
+debug(27 downto 16) <= fifo_data_free(13);\r
+debug(15 downto 12) <= (others => '0');\r
+debug(11 downto 0) <= fifo_wcnt(13);\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- Output signals\r
+---------------------------------------------------------------------------\r
+ipu_data_out <= ipu_out_data;\r
+lvl2_counter_out <= cyclectr;\r
+dhdr_buf_full_out <= dhdr_buf_full;\r
+\r
+---------------------------------------------------------------------------\r
+-- DEBUG signals\r
+---------------------------------------------------------------------------\r
+dbg_bsm_out <= bsm_x;\r
+dbg_out <= debug;\r
+\r
+end behavioral;\r
+\r
+\r
+ \r
+\r
+\r
--- /dev/null
+library IEEE;\r
+use IEEE.STD_LOGIC_1164.ALL;\r
+use IEEE.STD_LOGIC_ARITH.ALL;\r
+use IEEE.STD_LOGIC_UNSIGNED.ALL;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+entity logic_analyzer is\r
+port( CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- control signals\r
+ ARM_IN : in std_logic; -- arm the machine\r
+ TRG_IN : in std_logic; -- trigger the data acquisition\r
+ MAX_SAMPLE_IN : in std_logic_vector(9 downto 0); \r
+ -- status signals\r
+ SM_ADDR_OUT : out std_logic_vector(9 downto 0); -- sample RAM addresses\r
+ SM_CE_OUT : out std_logic;\r
+ SM_WE_OUT : out std_logic; -- write enable for sample RAM\r
+ CLEAR_OUT : out std_logic; -- sample memory is being cleared\r
+ RUN_OUT : out std_logic; -- ready for trigger\r
+ SAMPLE_OUT : out std_logic; -- data acquisition running\r
+ READY_OUT : out std_logic; -- data acquisition is finished\r
+ LAST_OUT : out std_logic; -- last data word of sampling\r
+ -- Status lines\r
+ BSM_OUT : out std_logic_vector(3 downto 0);\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+ );\r
+end entity;\r
+\r
+architecture Behavioral of logic_analyzer is\r
+\r
+-- Signals\r
+\r
+ type STATES is (SM_SLEEP,SM_CLEAR,SM_RUN,SM_SAMPLE,SM_READY);\r
+ signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+ signal sm_addr : std_logic_vector(9 downto 0);\r
+ signal sm_counter : std_logic_vector(9 downto 0);\r
+\r
+ signal sm_we_x : std_logic;\r
+ signal sm_we : std_logic;\r
+ signal sm_ce_x : std_logic;\r
+ signal sm_ce : std_logic;\r
+ signal sm_rst_x : std_logic;\r
+ signal sm_rst : std_logic;\r
+ signal sm_acq_x : std_logic;\r
+ signal sm_acq : std_logic;\r
+ signal sm_done_x : std_logic;\r
+ signal sm_done : std_logic;\r
+\r
+ signal sm_clear_done_x : std_logic;\r
+ signal sm_clear_done : std_logic;\r
+ signal sm_sample_done_x : std_logic;\r
+ signal sm_sample_done : std_logic;\r
+\r
+ signal data_available : std_logic;\r
+\r
+-- signal debug : std_logic_vector(31 downto 0);\r
+\r
+begin\r
+\r
+-- Fake\r
+stat(31 downto 17) <= (others => '0');\r
+stat(16) <= sm_sample_done;\r
+stat(15 downto 10) <= (others => '0');\r
+stat(9 downto 0) <= sm_counter;\r
+\r
+-- address counter\r
+THE_ADDR_CTR_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( (reset_in = '1') or (sm_rst = '1') ) then\r
+ sm_addr <= (others => '0');\r
+ elsif( sm_ce = '1' ) then\r
+ sm_addr <= sm_addr + 1;\r
+ end if;\r
+ end if;\r
+end process THE_ADDR_CTR_PROC;\r
+\r
+sm_clear_done_x <= '1' when (sm_addr = b"11_1111_1110") else '0';\r
+\r
+THE_SAMPLE_CTR_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( (reset_in = '1') or (sm_rst = '1') ) then\r
+ sm_counter <= (others => '0');\r
+ elsif( sm_acq = '1' ) then\r
+ sm_counter <= sm_counter + 1;\r
+ end if;\r
+ end if;\r
+end process THE_SAMPLE_CTR_PROC;\r
+\r
+sm_sample_done_x <= '1' when (sm_counter = max_sample_in) else '0';\r
+\r
+THE_SYNC_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ sm_clear_done <= sm_clear_done_x;\r
+ sm_sample_done <= sm_sample_done_x;\r
+ end if;\r
+end process THE_SYNC_PROC;\r
+\r
+THE_READY_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( (reset_in = '1') or (sm_rst = '1') ) then\r
+ data_available <= '0';\r
+ elsif( sm_sample_done = '1' ) then\r
+ data_available <= '1';\r
+ end if;\r
+ end if;\r
+end process THE_READY_PROC;\r
+\r
+---------------------------------------------------------\r
+-- Statemachine --\r
+---------------------------------------------------------\r
+-- State memory process\r
+STATE_MEM: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ CURRENT_STATE <= SM_SLEEP;\r
+ sm_rst <= '0';\r
+ sm_ce <= '0';\r
+ sm_we <= '0';\r
+ sm_acq <= '0';\r
+ sm_done <= '0';\r
+ else\r
+ CURRENT_STATE <= NEXT_STATE;\r
+ sm_rst <= sm_rst_x;\r
+ sm_ce <= sm_ce_x;\r
+ sm_we <= sm_we_x;\r
+ sm_acq <= sm_acq_x;\r
+ sm_done <= sm_done_x;\r
+ end if;\r
+ end if;\r
+end process STATE_MEM;\r
+\r
+-- Transition matrix\r
+TRANSFORM: process( CURRENT_STATE, arm_in, trg_in, sm_clear_done, sm_sample_done )\r
+begin\r
+ NEXT_STATE <= SM_SLEEP;\r
+ sm_rst_x <= '0';\r
+ sm_ce_x <= '0';\r
+ sm_we_x <= '0';\r
+ sm_acq_x <= '0';\r
+ sm_done_x <= '0';\r
+ case CURRENT_STATE is\r
+ when SM_SLEEP => if( arm_in = '1' ) then\r
+ NEXT_STATE <= SM_CLEAR;\r
+ sm_rst_x <= '1';\r
+ else \r
+ NEXT_STATE <= SM_SLEEP;\r
+ end if;\r
+ when SM_CLEAR => if( sm_clear_done = '1' ) then\r
+ NEXT_STATE <= SM_RUN;\r
+ sm_ce_x <= '1';\r
+ sm_we_x <= '1';\r
+ else\r
+ NEXT_STATE <= SM_CLEAR;\r
+ sm_ce_x <= '1';\r
+ sm_we_x <= '1';\r
+ end if;\r
+ when SM_RUN => if( trg_in = '1' ) then\r
+ NEXT_STATE <= SM_SAMPLE;\r
+ sm_ce_x <= '1';\r
+ sm_we_x <= '1';\r
+ sm_acq_x <= '1';\r
+ else\r
+ NEXT_STATE <= SM_RUN;\r
+ sm_ce_x <= '1';\r
+ sm_we_x <= '1';\r
+ end if;\r
+ when SM_SAMPLE => if( sm_sample_done = '1' ) then\r
+ NEXT_STATE <= SM_READY;\r
+ sm_done_x <= '1';\r
+ else\r
+ NEXT_STATE <= SM_SAMPLE;\r
+ sm_ce_x <= '1';\r
+ sm_we_x <= '1';\r
+ sm_acq_x <= '1';\r
+ end if;\r
+ when SM_READY => NEXT_STATE <= SM_SLEEP;\r
+\r
+ when others => NEXT_STATE <= SM_SLEEP;\r
+ end case;\r
+end process TRANSFORM;\r
+\r
+-- state decoding\r
+STATE_DECODE: process( CURRENT_STATE )\r
+begin\r
+ case CURRENT_STATE is\r
+ when SM_SLEEP => bsm_out <= x"0";\r
+ clear_out <= '0';\r
+ run_out <= '0';\r
+ when SM_CLEAR => bsm_out <= x"1";\r
+ clear_out <= '1';\r
+ run_out <= '0';\r
+ when SM_RUN => bsm_out <= x"2";\r
+ clear_out <= '0';\r
+ run_out <= '1';\r
+ when SM_SAMPLE => bsm_out <= x"3";\r
+ clear_out <= '0';\r
+ run_out <= '0';\r
+ when SM_READY => bsm_out <= x"4";\r
+ clear_out <= '0';\r
+ run_out <= '0';\r
+ when others => bsm_out <= x"f";\r
+ clear_out <= '0';\r
+ run_out <= '0';\r
+ end case;\r
+end process STATE_DECODE;\r
+\r
+---------------------------------------------------------\r
+-- output signals --\r
+---------------------------------------------------------\r
+sm_addr_out <= sm_addr;\r
+sm_we_out <= sm_we;\r
+sm_ce_out <= sm_ce;\r
+ready_out <= data_available;\r
+sample_out <= sm_acq;\r
+last_out <= sm_sample_done;\r
+\r
+end Behavioral;\r
--- /dev/null
+library ieee; \r
+use ieee.std_logic_1164.all; \r
+use ieee.std_logic_arith.all; \r
+use ieee.std_logic_unsigned.all;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+entity max_data is\r
+ port( CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ TODO_3_IN : in std_logic_vector(3 downto 0);\r
+ TODO_2_IN : in std_logic_vector(3 downto 0);\r
+ TODO_1_IN : in std_logic_vector(3 downto 0);\r
+ TODO_0_IN : in std_logic_vector(3 downto 0);\r
+ TODO_MAX_OUT : out std_logic_vector(3 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
+end;\r
+\r
+architecture behavioral of max_data is\r
+\r
+ -- Placer Directives\r
+\r
+ -- normal signals \r
+ -- first comparatopr step\r
+ signal max_32_data : std_logic_vector(3 downto 0);\r
+ signal max_21_data : std_logic_vector(3 downto 0);\r
+ signal max_10_data : std_logic_vector(3 downto 0);\r
+ signal comb_3_gt_2 : std_logic;\r
+ signal comb_2_gt_1 : std_logic;\r
+ signal comb_1_gt_0 : std_logic;\r
+ -- second comparator step\r
+ signal max_321_data : std_logic_vector(3 downto 0);\r
+ signal max_210_data : std_logic_vector(3 downto 0);\r
+ signal comb_32_gt_21 : std_logic;\r
+ signal comb_21_gt_10 : std_logic;\r
+ -- third comparator step\r
+ signal max_final_data : std_logic_vector(3 downto 0);\r
+ signal comb_final : std_logic;\r
+\r
+ signal debug : std_logic_vector(15 downto 0);\r
+\r
+begin \r
+\r
+-- FIRST COMPARATOR STEP\r
+-- compare MAX_3 against MAX_2, store the bigger one\r
+THE_COMP_3_2: comp4bit\r
+port map( DATAA => todo_3_in,\r
+ DATAB => todo_2_in,\r
+ AGTB => comb_3_gt_2\r
+ );\r
+\r
+THE_3_2_STORE_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( reset_in = '1' ) then\r
+ max_32_data <= (others => '0');\r
+ elsif( comb_3_gt_2 = '1' ) then\r
+ max_32_data <= todo_3_in;\r
+ else\r
+ max_32_data <= todo_2_in;\r
+ end if;\r
+ end if;\r
+end process THE_3_2_STORE_PROC;\r
+\r
+\r
+-- compare MAX_2 against MAX_1, store the bigger one\r
+THE_COMP_2_1: comp4bit\r
+port map( DATAA => todo_2_in,\r
+ DATAB => todo_1_in,\r
+ AGTB => comb_2_gt_1\r
+ );\r
+\r
+THE_2_1_STORE_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( reset_in = '1' ) then\r
+ max_21_data <= (others => '0');\r
+ elsif( comb_2_gt_1 = '1' ) then\r
+ max_21_data <= todo_2_in;\r
+ else\r
+ max_21_data <= todo_1_in;\r
+ end if;\r
+ end if;\r
+end process THE_2_1_STORE_PROC;\r
+\r
+-- compare MAX_1 against MAX_0, store the bigger one\r
+THE_COMP_1_0: comp4bit\r
+port map( DATAA => todo_1_in,\r
+ DATAB => todo_0_in,\r
+ AGTB => comb_1_gt_0\r
+ );\r
+\r
+THE_1_0_STORE_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( reset_in = '1' ) then\r
+ max_10_data <= (others => '0');\r
+ elsif( comb_1_gt_0 = '1' ) then\r
+ max_10_data <= todo_1_in;\r
+ else\r
+ max_10_data <= todo_0_in;\r
+ end if;\r
+ end if;\r
+end process THE_1_0_STORE_PROC;\r
+\r
+\r
+-- SECOND COMPARATOR STEP\r
+-- compare MAX_32 against MAX_21, store the bigger one\r
+THE_COMP_32_21: comp4bit\r
+port map( DATAA => max_32_data,\r
+ DATAB => max_21_data,\r
+ AGTB => comb_32_gt_21\r
+ );\r
+\r
+THE_32_21_STORE_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( reset_in = '1' ) then\r
+ max_321_data <= (others => '0');\r
+ elsif( comb_32_gt_21 = '1' ) then\r
+ max_321_data <= max_32_data;\r
+ else\r
+ max_321_data <= max_21_data;\r
+ end if;\r
+ end if;\r
+end process THE_32_21_STORE_PROC;\r
+\r
+-- compare MAX_21 against MAX_10, store the bigger one\r
+THE_COMP_21_10: comp4bit\r
+port map( DATAA => max_21_data,\r
+ DATAB => max_10_data,\r
+ AGTB => comb_21_gt_10\r
+ );\r
+\r
+THE_21_10_STORE_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( reset_in = '1' ) then\r
+ max_210_data <= (others => '0');\r
+ elsif( comb_21_gt_10 = '1' ) then\r
+ max_210_data <= max_21_data;\r
+ else\r
+ max_210_data <= max_10_data;\r
+ end if;\r
+ end if;\r
+end process THE_21_10_STORE_PROC;\r
+\r
+-- FINAL COMPARATOR STEP\r
+THE_COMP_FINAL: comp4bit\r
+port map( DATAA => max_321_data,\r
+ DATAB => max_210_data,\r
+ AGTB => comb_final\r
+ );\r
+\r
+THE_FINAL_STORE_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( reset_in = '1' ) then\r
+ max_final_data <= (others => '0');\r
+ elsif( comb_final = '1' ) then\r
+ max_final_data <= max_321_data;\r
+ else\r
+ max_final_data <= max_210_data;\r
+ end if;\r
+ end if;\r
+end process THE_FINAL_STORE_PROC;\r
+\r
+-- debug signals\r
+debug(15 downto 0) <= (others => '0');\r
+\r
+-- output signals\r
+todo_max_out <= max_final_data;\r
+debug_out <= debug; \r
+ \r
+end behavioral; \r
+
\ No newline at end of file
--- /dev/null
+SCUBA, Version ispLever_v72_PROD_Build (44)\r
+Fri Nov 20 19:14:28 2009\r
+ \r
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
+Copyright (c) 1995 AT&T Corp. All rights reserved.\r
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
+Copyright (c) 2001 Agere Systems All rights reserved.\r
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
+ \r
+BEGIN SCUBA Module Synthesis\r
+ \r
+ Issued command : F:\Programme\ispTOOLS7_2\ispfpga\bin\nt\scuba.exe -w -n dpram_8x19 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type ramdps -raddr_width 4 -rwidth 19 -waddr_width 4 -wwidth 19 -rnum_words 16 -wnum_words 16 -outData UNREGISTERED -e \r
+ Circuit name : dpram_8x19\r
+ Module type : sdpram\r
+ Module Version : 3.4\r
+ Address width : 4\r
+ Data width : 19\r
+ Ports : \r
+ Inputs : WrAddress[3:0], Data[18:0], WrClock, WE, WrClockEn, RdAddress[3:0]\r
+ Outputs : Q[18:0]\r
+ I/O buffer : not inserted\r
+ Clock edge : rising edge\r
+ EDIF output : suppressed\r
+ VHDL output : dpram_8x19.vhd\r
+ VHDL template : dpram_8x19_tmpl.vhd\r
+ VHDL testbench : tb_dpram_8x19_tmpl.vhd\r
+ VHDL purpose : for synthesis and simulation\r
+ Bus notation : big endian\r
+ Report output : dpram_8x19.srp\r
+ Estimated Resource Usage:\r
+ LUT : 1\r
+ DRAM : 5\r
+ \r
+END SCUBA Module Synthesis\r
+\r
--- /dev/null
+[Device]\r
+Family=latticeecp2m\r
+PartType=LFE2M100E\r
+PartName=LFE2M100E-6F900C\r
+SpeedGrade=-6\r
+Package=FPBGA900\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=Multiplier\r
+CoreRevision=4.3\r
+ModuleName=mult_3x8\r
+SourceFormat=VHDL\r
+ParameterFileVersion=1.0\r
+Date=10/29/2009\r
+Time=11:23:02\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+pmi_implemenntation=LUT\r
+pmi_const_coeff=No\r
+pmi_coeff_value=2\r
+pmi_ram_mult=No\r
+pmi_dataa_width=3\r
+pmi_datab_width=8\r
+pmi_datap_width=11\r
+pmi_signa=Unsigned\r
+pmi_signb=Unsigned\r
+pmi_additional_pipeline=0\r
+pmi_input_reg=No\r
+pmi_output_reg=Yes\r
--- /dev/null
+SCUBA, Version ispLever_v72_SP2_Build (23)
+Thu Oct 29 11:23:03 2009
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp. All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
+Copyright (c) 2001 Agere Systems All rights reserved.
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
+
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n mult_3x8 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type dspmult -simple_portname -pfu_mult -widtha 3 -widthb 8 -widthp 11 -PL_stages 0 -output_reg -clk0 -ce0 -rst0 -e
+ Circuit name : mult_3x8
+ Module type : dspmult_a
+ Module Version : 4.3
+ Ports :
+ Inputs : Clock, ClkEn, Aclr, DataA[2:0], DataB[7:0]
+ Outputs : Result[10:0]
+ I/O buffer : not inserted
+ EDIF output : suppressed
+ VHDL output : mult_3x8.vhd
+ VHDL template : mult_3x8_tmpl.vhd
+ VHDL testbench : tb_mult_3x8_tmpl.vhd
+ VHDL purpose : for synthesis and simulation
+ Bus notation : big endian
+ Report output : mult_3x8.srp
+ Element Usage :
+ AND2 : 9
+ FADD2B : 6
+ FD1P3DX : 11
+ MULT2 : 4
+ Estimated Resource Usage:
+ LUT : 29
+ Reg : 11
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23)
+-- Module Version: 4.3
+--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n mult_3x8 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type dspmult -simple_portname -pfu_mult -widtha 3 -widthb 8 -widthp 11 -PL_stages 0 -output_reg -clk0 -ce0 -rst0 -e
+
+-- Thu Oct 29 11:23:03 2009
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity mult_3x8 is
+ port (
+ Clock: in std_logic;
+ ClkEn: in std_logic;
+ Aclr: in std_logic;
+ DataA: in std_logic_vector(2 downto 0);
+ DataB: in std_logic_vector(7 downto 0);
+ Result: out std_logic_vector(10 downto 0));
+end mult_3x8;
+
+architecture Structure of mult_3x8 is
+
+ -- internal signal declarations
+ signal scuba_vhi: std_logic;
+ signal mult_3x8_0_pp_0_0: std_logic;
+ signal rego_o_0: std_logic;
+ signal rego_o_1: std_logic;
+ signal rego_o_2: std_logic;
+ signal rego_o_3: std_logic;
+ signal mult_3x8_0_pp_1_2: std_logic;
+ signal mult_3x8_0_pp_1_3: std_logic;
+ signal rego_o_4: std_logic;
+ signal rego_o_5: std_logic;
+ signal co_t_mult_3x8_0_0_1: std_logic;
+ signal mult_3x8_0_pp_1_4: std_logic;
+ signal mult_3x8_0_pp_1_5: std_logic;
+ signal rego_o_6: std_logic;
+ signal rego_o_7: std_logic;
+ signal co_t_mult_3x8_0_0_2: std_logic;
+ signal mult_3x8_0_pp_1_6: std_logic;
+ signal mult_3x8_0_pp_1_7: std_logic;
+ signal rego_o_8: std_logic;
+ signal rego_o_9: std_logic;
+ signal co_t_mult_3x8_0_0_3: std_logic;
+ signal mult_3x8_0_pp_1_8: std_logic;
+ signal mult_3x8_0_pp_1_9: std_logic;
+ signal mult_3x8_0_pp_0_9: std_logic;
+ signal rego_o_10: std_logic;
+ signal co_t_mult_3x8_0_0_4: std_logic;
+ signal mult_3x8_0_pp_0_2: std_logic;
+ signal mult_3x8_0_pp_0_1: std_logic;
+ signal mult_3x8_0_pp_0_4: std_logic;
+ signal mult_3x8_0_pp_0_3: std_logic;
+ signal mco: std_logic;
+ signal mult_3x8_0_pp_0_6: std_logic;
+ signal mult_3x8_0_pp_0_5: std_logic;
+ signal mco_1: std_logic;
+ signal mfco: std_logic;
+ signal mult_3x8_0_pp_0_8: std_logic;
+ signal mult_3x8_0_pp_0_7: std_logic;
+ signal mco_2: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component AND2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component FADD2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; COUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FD1P3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component MULT2
+ port (A0: in std_logic; A1: in std_logic; A2: in std_logic;
+ A3: in std_logic; B0: in std_logic; B1: in std_logic;
+ B2: in std_logic; B3: in std_logic; CI: in std_logic;
+ P0: out std_logic; P1: out std_logic; CO: out std_logic);
+ end component;
+ attribute GSR : string;
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ AND2_t8: AND2
+ port map (A=>DataB(0), B=>DataA(0), Z=>mult_3x8_0_pp_0_0);
+
+ AND2_t7: AND2
+ port map (A=>DataB(0), B=>DataA(2), Z=>mult_3x8_0_pp_1_2);
+
+ AND2_t6: AND2
+ port map (A=>DataB(1), B=>DataA(2), Z=>mult_3x8_0_pp_1_3);
+
+ AND2_t5: AND2
+ port map (A=>DataB(2), B=>DataA(2), Z=>mult_3x8_0_pp_1_4);
+
+ AND2_t4: AND2
+ port map (A=>DataB(3), B=>DataA(2), Z=>mult_3x8_0_pp_1_5);
+
+ AND2_t3: AND2
+ port map (A=>DataB(4), B=>DataA(2), Z=>mult_3x8_0_pp_1_6);
+
+ AND2_t2: AND2
+ port map (A=>DataB(5), B=>DataA(2), Z=>mult_3x8_0_pp_1_7);
+
+ AND2_t1: AND2
+ port map (A=>DataB(6), B=>DataA(2), Z=>mult_3x8_0_pp_1_8);
+
+ AND2_t0: AND2
+ port map (A=>DataB(7), B=>DataA(2), Z=>mult_3x8_0_pp_1_9);
+
+ FF_10: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rego_o_0, SP=>ClkEn, CK=>Clock, CD=>Aclr,
+ Q=>Result(0));
+
+ FF_9: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rego_o_1, SP=>ClkEn, CK=>Clock, CD=>Aclr,
+ Q=>Result(1));
+
+ FF_8: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rego_o_2, SP=>ClkEn, CK=>Clock, CD=>Aclr,
+ Q=>Result(2));
+
+ FF_7: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rego_o_3, SP=>ClkEn, CK=>Clock, CD=>Aclr,
+ Q=>Result(3));
+
+ FF_6: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rego_o_4, SP=>ClkEn, CK=>Clock, CD=>Aclr,
+ Q=>Result(4));
+
+ FF_5: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rego_o_5, SP=>ClkEn, CK=>Clock, CD=>Aclr,
+ Q=>Result(5));
+
+ FF_4: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rego_o_6, SP=>ClkEn, CK=>Clock, CD=>Aclr,
+ Q=>Result(6));
+
+ FF_3: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rego_o_7, SP=>ClkEn, CK=>Clock, CD=>Aclr,
+ Q=>Result(7));
+
+ FF_2: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rego_o_8, SP=>ClkEn, CK=>Clock, CD=>Aclr,
+ Q=>Result(8));
+
+ FF_1: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rego_o_9, SP=>ClkEn, CK=>Clock, CD=>Aclr,
+ Q=>Result(9));
+
+ FF_0: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rego_o_10, SP=>ClkEn, CK=>Clock, CD=>Aclr,
+ Q=>Result(10));
+
+ mult_3x8_0_Cadd_0_4: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>mfco, COUT=>open, S0=>mult_3x8_0_pp_0_9,
+ S1=>open);
+
+ t_mult_3x8_0_add_0_1: FADD2B
+ port map (A0=>mult_3x8_0_pp_0_2, A1=>mult_3x8_0_pp_0_3,
+ B0=>mult_3x8_0_pp_1_2, B1=>mult_3x8_0_pp_1_3, CI=>scuba_vlo,
+ COUT=>co_t_mult_3x8_0_0_1, S0=>rego_o_2, S1=>rego_o_3);
+
+ t_mult_3x8_0_add_0_2: FADD2B
+ port map (A0=>mult_3x8_0_pp_0_4, A1=>mult_3x8_0_pp_0_5,
+ B0=>mult_3x8_0_pp_1_4, B1=>mult_3x8_0_pp_1_5,
+ CI=>co_t_mult_3x8_0_0_1, COUT=>co_t_mult_3x8_0_0_2,
+ S0=>rego_o_4, S1=>rego_o_5);
+
+ t_mult_3x8_0_add_0_3: FADD2B
+ port map (A0=>mult_3x8_0_pp_0_6, A1=>mult_3x8_0_pp_0_7,
+ B0=>mult_3x8_0_pp_1_6, B1=>mult_3x8_0_pp_1_7,
+ CI=>co_t_mult_3x8_0_0_2, COUT=>co_t_mult_3x8_0_0_3,
+ S0=>rego_o_6, S1=>rego_o_7);
+
+ t_mult_3x8_0_add_0_4: FADD2B
+ port map (A0=>mult_3x8_0_pp_0_8, A1=>mult_3x8_0_pp_0_9,
+ B0=>mult_3x8_0_pp_1_8, B1=>mult_3x8_0_pp_1_9,
+ CI=>co_t_mult_3x8_0_0_3, COUT=>co_t_mult_3x8_0_0_4,
+ S0=>rego_o_8, S1=>rego_o_9);
+
+ Cadd_t_mult_3x8_0_0_5: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co_t_mult_3x8_0_0_4, COUT=>open,
+ S0=>rego_o_10, S1=>open);
+
+ mult_3x8_0_mult_0_0: MULT2
+ port map (A0=>DataB(0), A1=>DataB(1), A2=>DataB(1), A3=>DataB(2),
+ B0=>DataA(1), B1=>DataA(0), B2=>DataA(1), B3=>DataA(0),
+ CI=>scuba_vlo, P0=>mult_3x8_0_pp_0_1, P1=>mult_3x8_0_pp_0_2,
+ CO=>mco);
+
+ mult_3x8_0_mult_0_1: MULT2
+ port map (A0=>DataB(2), A1=>DataB(3), A2=>DataB(3), A3=>DataB(4),
+ B0=>DataA(1), B1=>DataA(0), B2=>DataA(1), B3=>DataA(0),
+ CI=>mco, P0=>mult_3x8_0_pp_0_3, P1=>mult_3x8_0_pp_0_4,
+ CO=>mco_1);
+
+ mult_3x8_0_mult_0_2: MULT2
+ port map (A0=>DataB(4), A1=>DataB(5), A2=>DataB(5), A3=>DataB(6),
+ B0=>DataA(1), B1=>DataA(0), B2=>DataA(1), B3=>DataA(0),
+ CI=>mco_1, P0=>mult_3x8_0_pp_0_5, P1=>mult_3x8_0_pp_0_6,
+ CO=>mco_2);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ mult_3x8_0_mult_0_3: MULT2
+ port map (A0=>DataB(6), A1=>DataB(7), A2=>DataB(7),
+ A3=>scuba_vlo, B0=>DataA(1), B1=>DataA(0), B2=>DataA(1),
+ B3=>DataA(0), CI=>mco_2, P0=>mult_3x8_0_pp_0_7,
+ P1=>mult_3x8_0_pp_0_8, CO=>mfco);
+
+ rego_o_0 <= mult_3x8_0_pp_0_0;
+ rego_o_1 <= mult_3x8_0_pp_0_1;
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of mult_3x8 is
+ for Structure
+ for all:AND2 use entity ecp2m.AND2(V); end for;
+ for all:FADD2B use entity ecp2m.FADD2B(V); end for;
+ for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
+ for all:VHI use entity ecp2m.VHI(V); end for;
+ for all:VLO use entity ecp2m.VLO(V); end for;
+ for all:MULT2 use entity ecp2m.MULT2(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+Starting process: \r
+\r
+SCUBA, Version ispLever_v72_SP2_Build (23)\r
+Thu Oct 29 11:23:03 2009\r
+\r
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
+Copyright (c) 1995 AT&T Corp. All rights reserved.\r
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
+Copyright (c) 2001 Agere Systems All rights reserved.\r
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
+\r
+BEGIN SCUBA Module Synthesis\r
+\r
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n mult_3x8 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type dspmult -simple_portname -pfu_mult -widtha 3 -widthb 8 -widthp 11 -PL_stages 0 -output_reg -clk0 -ce0 -rst0 -e \r
+ Circuit name : mult_3x8\r
+ Module type : dspmult_a\r
+ Module Version : 4.3\r
+ Ports : \r
+ Inputs : Clock, ClkEn, Aclr, DataA[2:0], DataB[7:0]\r
+ Outputs : Result[10:0]\r
+ I/O buffer : not inserted\r
+ EDIF output : suppressed\r
+ VHDL output : mult_3x8.vhd\r
+ VHDL template : mult_3x8_tmpl.vhd\r
+ VHDL testbench : tb_mult_3x8_tmpl.vhd\r
+ VHDL purpose : for synthesis and simulation\r
+ Bus notation : big endian\r
+ Report output : mult_3x8.srp\r
+ Estimated Resource Usage:\r
+ LUT : 29\r
+ Reg : 11\r
+\r
+END SCUBA Module Synthesis\r
+\r
+File: ..\src\mult_3x8.lpc created.\r
+\r
+\r
+End process: completed successfully.\r
+\r
+\r
+Total Warnings: 0\r
+\r
+Total Errors: 0\r
+\r
+\r
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23)
+-- Module Version: 4.3
+-- Thu Oct 29 11:23:03 2009
+
+-- parameterized module component declaration
+component mult_3x8
+ port (Clock: in std_logic; ClkEn: in std_logic;
+ Aclr: in std_logic; DataA: in std_logic_vector(2 downto 0);
+ DataB: in std_logic_vector(7 downto 0);
+ Result: out std_logic_vector(10 downto 0));
+end component;
+
+-- parameterized module component instance
+__ : mult_3x8
+ port map (Clock=>__, ClkEn=>__, Aclr=>__, DataA(2 downto 0)=>__,
+ DataB(7 downto 0)=>__, Result(10 downto 0)=>__);
--- /dev/null
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity my_sbuf is
+ port( CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- connections to data source A
+ COMB_DATAREADY_IN : in std_logic;
+ COMB_NEXT_READ_OUT : out std_logic;
+ COMB_READ_IN : in std_logic;
+ COMB_DATA_IN : in std_logic_vector (18 downto 0);
+ -- connections to data sink B
+ SYN_DATAREADY_OUT : out std_logic;
+ SYN_DATA_OUT : out std_logic_vector (18 downto 0);
+ SYN_READ_IN : in std_logic;
+ -- status signals
+ DEBUG_OUT : out std_logic_vector(31 downto 0);
+ STAT_BUFFER : out std_logic
+ );
+end my_sbuf;
+
+architecture my_sbuf_arch of my_sbuf is
+
+-- small DPRAM LUT based
+component dpram_8x19 is
+port( WRADDRESS : in std_logic_vector(3 downto 0);
+ DATA : in std_logic_vector(18 downto 0);
+ WRCLOCK : in std_logic;
+ WE : in std_logic;
+ WRCLOCKEN : in std_logic;
+ RDADDRESS : in std_logic_vector(3 downto 0);
+-- RDCLOCK : in std_logic;
+-- RDCLOCKEN : in std_logic;
+-- RESET : in std_logic;
+ Q : out std_logic_vector(18 downto 0)
+ );
+end component dpram_8x19;
+
+-- signals
+signal fifo_wr_data : std_logic_vector(18 downto 0);
+signal fifo_rd_data : std_logic_vector(18 downto 0);
+signal fifo_we : std_logic;
+signal fifo_rd : std_logic;
+signal wr_pointer : std_logic_vector(3 downto 0);
+signal comb_ce_wr_pointer : std_logic;
+signal rd_pointer : std_logic_vector(3 downto 0);
+signal comb_ce_rd_pointer : std_logic;
+signal lvl_counter : std_logic_vector(4 downto 0);
+signal free_counter : std_logic_vector(4 downto 0);
+signal comb_inc_free_counter : std_logic;
+signal comb_dec_free_counter : std_logic;
+
+signal debug : std_logic_vector(31 downto 0);
+
+begin
+
+-------------------------------------------------------------
+-- debug signals
+-------------------------------------------------------------
+debug(31 downto 24) <= (others => '0');
+
+debug(23 downto 21) <= (others => '0');
+debug(20 downto 16) <= lvl_counter;
+debug(15 downto 13) <= (others => '0');
+debug(12 downto 8) <= free_counter;
+debug(7 downto 4) <= rd_pointer;
+debug(3 downto 0) <= wr_pointer;
+-------------------------------------------------------------
+-- write pointer
+-------------------------------------------------------------
+comb_ce_wr_pointer <= fifo_we; -- BUG
+
+THE_WR_POINTER_PROC: process( clk )
+begin
+ if( rising_edge(clk) ) then
+ if ( reset = '1' ) then
+ wr_pointer <= (others => '0');
+ elsif( comb_ce_wr_pointer = '1' ) then
+ wr_pointer <= wr_pointer + 1;
+ end if;
+ end if;
+end process THE_WR_POINTER_PROC;
+
+
+-------------------------------------------------------------
+-- read pointer
+-------------------------------------------------------------
+comb_ce_rd_pointer <= fifo_rd; -- BUG
+
+THE_RD_POINTER_PROC: process( clk )
+begin
+ if( rising_edge(clk) ) then
+ if ( reset = '1' ) then
+ rd_pointer <= (others => '0');
+ elsif( comb_ce_rd_pointer = '1' ) then
+ rd_pointer <= rd_pointer + 1;
+ end if;
+ end if;
+end process THE_RD_POINTER_PROC;
+
+-------------------------------------------------------------
+-- free counter
+-------------------------------------------------------------
+comb_inc_free_counter <= fifo_rd; -- BUG
+comb_dec_free_counter <= fifo_we; -- BUG
+
+THE_FREE_COUNTER_PROC: process( clk )
+begin
+ if( rising_edge(clk) ) then
+ if ( reset = '1' ) then
+ free_counter <= b"1_0000";
+ elsif( (comb_inc_free_counter = '1') and (comb_dec_free_counter = '0') ) then
+ free_counter <= free_counter + 1;
+ elsif( (comb_inc_free_counter = '0') and (comb_dec_free_counter = '1') ) then
+ free_counter <= free_counter - 1;
+ end if;
+ end if;
+end process THE_FREE_COUNTER_PROC;
+
+THE_LVL_COUNTER_PROC: process( clk )
+begin
+ if( rising_edge(clk) ) then
+ if ( reset = '1' ) then
+ lvl_counter <= (others => '0');
+ elsif( (comb_inc_free_counter = '1') and (comb_dec_free_counter = '0') ) then
+ lvl_counter <= lvl_counter - 1;
+ elsif( (comb_inc_free_counter = '0') and (comb_dec_free_counter = '1') ) then
+ lvl_counter <= lvl_counter + 1;
+ end if;
+ end if;
+end process THE_LVL_COUNTER_PROC;
+
+-------------------------------------------------------------
+-- the buffer memory
+-------------------------------------------------------------
+fifo_we <= comb_dataready_in and comb_read_in; -- BUG
+fifo_rd <= syn_read_in; -- BUG
+fifo_wr_data <= comb_data_in;
+
+THE_BUFFER_DPRAM: dpram_8x19
+port map( WRADDRESS => wr_pointer,
+ DATA => fifo_wr_data,
+ WRCLOCK => clk,
+ WE => fifo_we,
+ WRCLOCKEN => '1',
+ RDADDRESS => rd_pointer,
+-- RDCLOCK => clk,
+-- RDCLOCKEN => '1',
+-- RESET => reset,
+ Q => fifo_rd_data
+ );
+
+-------------------------------------------------------------
+-- output signals
+-------------------------------------------------------------
+debug_out <= debug;
+comb_next_read_out <= '0';
+syn_dataready_out <= '0';
+stat_buffer <= '0';
+syn_data_out <= fifo_rd_data;
+
+end architecture;
\ No newline at end of file
--- /dev/null
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+
+library work;
+use work.trb_net_std.all;
+
+-- stolen from Jan Michel, was trb_net_onewire.vhd
+
+entity onewire_master is
+ generic( CLK_PERIOD : integer := 10 ); -- clock perion in nanoseconds
+ port( CLK : in std_logic;
+ RESET : in std_logic;
+ READOUT_ENABLE_IN : in std_logic;
+ -- connection to 1-wire interface (16 APV FEs)
+ ONEWIRE : inout std_logic_vector(15 downto 0);
+ BP_ONEWIRE : inout std_logic;
+ -- connection to external DPRAM for slow control readout
+ BP_DATA_OUT : out std_logic_vector(15 downto 0);
+ DATA_OUT : out std_logic_vector(15 downto 0);
+ ADDR_OUT : out std_logic_vector(6 downto 0);
+ WRITE_OUT : out std_logic;
+ BUSY_OUT : out std_logic;
+ -- debug
+ BSM_OUT : out std_logic_vector(7 downto 0);
+ STAT : out std_logic_vector(15 downto 0)
+ );
+end entity;
+
+architecture onewire_master_arch of onewire_master is
+
+ constant MAX_COUNTER : integer := 2**28-1;
+ type state_t is (START, IDLE, SEND_RESET, WAIT_AFTER_RESET, SEND_ROM_COMMAND, READ_WAIT,
+ WRITE_START, WRITE_WAIT, READ_BIT, READ_READ_ROM, SEND_CONV_TEMP,
+ READ_CONV_TEMP, SEND_READ_TEMP, READ_READ_TEMP, CHECK_PULSE);
+ signal STATE : state_t;
+ signal NEXT_STATE : state_t;
+ signal bsm : std_logic_vector(7 downto 0);
+ signal timecounter : integer range 0 to MAX_COUNTER;
+ signal bitcounter : integer range 0 to 127;
+ signal bitcounter_vector : std_logic_vector(6 downto 0);
+ signal inc_bitcounter : std_logic;
+ signal reset_bitcounter : std_logic;
+ signal reset_timecounter : std_logic;
+ signal send_bit : std_logic;
+ signal next_send_bit : std_logic;
+ signal recv_bit_ready : std_logic;
+ signal next_recv_bit_ready : std_logic;
+ signal ext_ram_addr : std_logic_vector(3 downto 0);
+ signal ram_addr : std_logic_vector(2 downto 0);
+ signal ram_wr : std_logic;
+
+ -- state machine auxiliary signals
+ signal wait_pulse : std_logic;
+ signal next_wait_pulse : std_logic;
+ signal strong_pullup : std_logic;
+ signal next_strong_pullup : std_logic;
+ signal presence_reset : std_logic;
+ signal next_presence_reset : std_logic;
+ signal send_rom : std_logic; -- read UniqueID
+ signal next_send_rom : std_logic;
+ signal conv_temp : std_logic; -- send CONV_TEMP
+ signal next_conv_temp : std_logic;
+ signal reading_temp : std_logic; -- readback of temperature
+ signal next_reading_temp : std_logic;
+ signal skip_rom : std_logic; -- send SKIP_ROM
+ signal next_skip_rom : std_logic;
+ signal output_tmp : std_logic; -- 1W output signal
+ signal next_output_tmp : std_logic;
+ signal output : std_logic;
+ signal next_output : std_logic;
+
+ -- presence pulse detection
+ signal neg_edge : std_logic_vector(16 downto 0); -- presence pulse edge detection
+ signal presence_found : std_logic_vector(16 downto 0); -- set signal for presence bits
+ signal presence : std_logic_vector(16 downto 0); -- presence bits
+
+ type input_t is array (0 to 16) of std_logic_vector(7 downto 0);
+ signal input : input_t;
+
+ type word_t is array (0 to 16) of std_logic_vector(15 downto 0);
+ signal word : word_t;
+
+ signal recv_bit : std_logic_vector(16 downto 0);
+ signal next_recv_bit : std_logic_vector(16 downto 0);
+
+ signal comb_ext_addr_go : std_logic;
+
+ -- output signals, delayed by one cycle
+ signal mux_data : std_logic_vector(15 downto 0);
+ signal mux_addr : std_logic_vector(6 downto 0);
+ signal mux_wr : std_logic;
+
+ signal onewire_tmp : std_logic_vector(16 downto 0);
+
+ signal comb_busy : std_logic;
+ signal busy : std_logic;
+
+begin
+
+-- bidirectional connection
+IO_GEN: for i in 0 to 15 generate
+ onewire(i) <= '0' when (output = '0') else '1' when (strong_pullup = '1') else 'Z';
+ onewire_tmp(i) <= '0' when onewire(i) = '0' else '1'; -- BUGBUGBUG
+end generate IO_GEN;
+
+-- We have one "special" connection for the backplane 1Wire ID
+bp_onewire <= '0' when (output = '0') else '1' when (strong_pullup = '1') else 'Z';
+onewire_tmp(16) <= '0' when bp_onewire = '0' else '1'; -- BUGBUGBUG
+
+-- shift and sync register
+THE_SHIFT_PROC : process(clk)
+begin
+ if( rising_edge(clk) ) then
+ for i in 0 to 16 loop
+ -- Shift registers
+ input(i)(7 downto 1) <= input(i)(6 downto 0);
+ input(i)(0) <= onewire_tmp(i); -- BUGBUGBUG
+ -- Edge detection
+ neg_edge(i) <= input(i)(7) and not input(i)(6) and not input(i)(5) and not input(i)(4) and not input(i)(3) and not input(i)(2);
+ presence_found(i) <= wait_pulse and neg_edge(i);
+ -- presence registers
+ if ( presence_reset = '1') then
+ presence(i) <= '0';
+ elsif( presence_found(i) = '1' ) then
+ presence(i) <= '1';
+ end if;
+ end loop;
+ -- Synchronize signals
+ end if;
+end process THE_SHIFT_PROC;
+
+bitcounter_vector <= conv_std_logic_vector(bitcounter,7);
+
+--------------------------------------------------------------------------------------
+--------------------------------------------------------------------------------------
+--------------------------------------------------------------------------------------
+-- State machine registers
+THE_STATE_REGS_PROC: process(clk)
+begin
+ if( rising_edge(clk) ) then
+ if( reset = '1' ) then
+ STATE <= START;
+ send_bit <= '0';
+ output_tmp <= '0';
+ recv_bit <= (others => '0');
+ strong_pullup <= '0';
+ wait_pulse <= '0';
+ presence_reset <= '0';
+ send_rom <= '1';
+ conv_temp <= '0';
+ reading_temp <= '0';
+ skip_rom <= '0';
+ busy <= '0';
+ else
+ recv_bit_ready <= next_recv_bit_ready;
+ state <= next_state;
+ send_bit <= next_send_bit;
+ output <= next_output;
+ output_tmp <= next_output_tmp;
+ recv_bit <= next_recv_bit;
+ strong_pullup <= next_strong_pullup;
+ wait_pulse <= next_wait_pulse;
+ presence_reset <= next_presence_reset;
+ send_rom <= next_send_rom;
+ conv_temp <= next_conv_temp;
+ reading_temp <= next_reading_temp;
+ skip_rom <= next_skip_rom;
+ busy <= comb_busy;
+ end if;
+ end if;
+end process THE_STATE_REGS_PROC;
+
+comb_busy <= '0' when (STATE = START) else '1';
+
+-- State machine transitions
+THE_STATE_MACHINE: process( STATE, timecounter, bitcounter_vector, input, send_bit, output_tmp,
+ skip_rom, recv_bit, conv_temp, reading_temp, send_rom, readout_enable_in )
+begin
+ NEXT_STATE <= STATE;
+ next_output <= '1';
+ reset_timecounter <= '0';
+ reset_bitcounter <= '0';
+ next_output_tmp <= output_tmp;
+ inc_bitcounter <= '0';
+ next_send_bit <= send_bit;
+ next_recv_bit <= (others => '0');
+ next_recv_bit_ready <= '0';
+ next_send_rom <= send_rom;
+ next_conv_temp <= conv_temp;
+ next_reading_temp <= reading_temp;
+ next_recv_bit <= recv_bit;
+ next_skip_rom <= skip_rom;
+ next_strong_pullup <= '0';
+ next_wait_pulse <= '0';
+ next_presence_reset <= '0';
+
+ case STATE is
+ --
+ when START =>
+ if( readout_enable_in = '1' ) then
+ NEXT_STATE <= IDLE;
+ reset_timecounter <= '1';
+ end if;
+
+ -- idle state for the DS1822
+ when IDLE =>
+ if( is_time_reached(timecounter,640000,CLK_PERIOD) = '1' ) then
+ NEXT_STATE <= SEND_RESET;
+ reset_timecounter <= '1';
+ end if;
+
+ -- send the reset pulse
+ when SEND_RESET =>
+ next_output <= '0';
+ if( is_time_reached(timecounter,640000,CLK_PERIOD) = '1' ) then
+ reset_timecounter <= '1';
+ next_presence_reset <= '1';
+ NEXT_STATE <= WAIT_AFTER_RESET;
+ end if;
+
+ -- delay after RESET pulse (earliest presence pulse @15us)
+ when WAIT_AFTER_RESET =>
+ if( is_time_reached(timecounter,10000,CLK_PERIOD) = '1' ) then
+ reset_timecounter <= '1';
+ NEXT_STATE <= CHECK_PULSE;
+ end if;
+
+ -- check if the is a pulse
+ when CHECK_PULSE =>
+ next_wait_pulse <= '1';
+ if( is_time_reached(timecounter,320000,CLK_PERIOD) = '1' ) then
+ next_wait_pulse <= '0';
+ reset_timecounter <= '1';
+ NEXT_STATE <= SEND_ROM_COMMAND;
+ end if;
+
+ -- sending rom commands
+ when SEND_ROM_COMMAND =>
+ next_skip_rom <= not send_rom and not bitcounter_vector(3);
+ inc_bitcounter <= '1';
+ NEXT_STATE <= WRITE_START;
+
+ if( send_rom = '1' ) then
+ next_send_bit <= not bitcounter_vector(1); -- this is x33 (READ_ROM_COMMAND), lsb first
+ else
+ next_send_bit <= bitcounter_vector(1); -- this is xCC (SKIP_ROM_COMMAND), lsb first
+ end if;
+
+ if( bitcounter_vector(3) = '1' ) then --send 8 bit
+ if ( send_rom = '1' ) then
+ NEXT_STATE <= READ_READ_ROM;
+ elsif( conv_temp = '1' ) then
+ NEXT_STATE <= SEND_CONV_TEMP;
+ else
+ NEXT_STATE <= SEND_READ_TEMP;
+ end if;
+ reset_bitcounter <= '1';
+ end if;
+
+ --sending sensor commands
+ when SEND_CONV_TEMP =>
+ next_send_bit <= bitcounter_vector(1) and not bitcounter_vector(0);
+ --this is x44, lsb first
+ inc_bitcounter <= '1';
+ if( bitcounter_vector(3) = '1' ) then --send 8 bit
+ NEXT_STATE <= READ_CONV_TEMP;
+ reset_bitcounter <= '1';
+ reset_timecounter <= '1';
+ next_recv_bit <= (others => '0');
+ else
+ NEXT_STATE <= WRITE_START;
+ end if;
+
+ when SEND_READ_TEMP =>
+ if( (bitcounter_vector(2 downto 0) = "000") or (bitcounter_vector(2 downto 0) = "110") ) then
+ next_send_bit <= '0'; --this is xBE, lsb first
+ else
+ next_send_bit <= '1';
+ end if;
+
+ inc_bitcounter <= '1';
+
+ if( bitcounter_vector(3) = '1' ) then --send 8 bit
+ NEXT_STATE <= READ_READ_TEMP;
+ reset_bitcounter <= '1';
+ next_recv_bit <= (others => '0');
+ else
+ NEXT_STATE <= WRITE_START;
+ end if;
+
+ --reading rom answers
+ when READ_READ_ROM =>
+ inc_bitcounter <= '1';
+ if( bitcounter_vector(6) = '1' ) then --read 64 bit
+ NEXT_STATE <= IDLE;
+ next_send_rom <= '0';
+ next_conv_temp <= '1';
+ reset_bitcounter <= '1';
+ else
+ NEXT_STATE <= READ_BIT;
+ end if;
+
+ --reading sensor answers
+ when READ_CONV_TEMP => --waiting for end of conversion
+ next_strong_pullup <= '1';
+ if( is_time_reached(timecounter,1300000000,CLK_PERIOD) = '1' ) then -- reality is 1.3s delay
+-- if( is_time_reached(timecounter,3000000,CLK_PERIOD) = '1' ) then -- simulation is 3ms delay
+ NEXT_STATE <= IDLE;
+ reset_timecounter <= '1';
+ next_conv_temp <= '0';
+ next_reading_temp <= '1';
+ end if;
+
+ when READ_READ_TEMP =>
+ inc_bitcounter <= '1';
+ if( bitcounter_vector(3 downto 2) = "11" ) then --read 12 bit
+ NEXT_STATE <= START;
+ next_send_rom <= '1';
+ next_reading_temp <= '0';
+ reset_bitcounter <= '1';
+ else
+ NEXT_STATE <= READ_BIT;
+ end if;
+
+ --write cycle
+ when WRITE_START =>
+ next_output <= output_tmp;
+ if( is_time_reached(timecounter,1200,CLK_PERIOD) = '1' ) then
+ next_output_tmp <= send_bit;
+ end if;
+ if( is_time_reached(timecounter,80000,CLK_PERIOD) = '1' ) then
+ NEXT_STATE <= WRITE_WAIT;
+ next_output_tmp <= '0';
+ reset_timecounter <= '1';
+ end if;
+
+ when WRITE_WAIT =>
+ if( is_time_reached(timecounter,1200,CLK_PERIOD) = '1' ) then
+ reset_timecounter <= '1';
+ if( (send_rom = '1') or (skip_rom = '1') ) then
+ NEXT_STATE <= SEND_ROM_COMMAND;
+ elsif( conv_temp = '1' ) then
+ NEXT_STATE <= SEND_CONV_TEMP;
+ elsif( reading_temp = '1' ) then
+ NEXT_STATE <= SEND_READ_TEMP;
+ end if;
+ end if;
+
+ --read cycle
+ when READ_BIT =>
+ next_output <= output_tmp;
+ if( is_time_reached(timecounter,1200,CLK_PERIOD) = '1' ) then
+ next_output_tmp <= '1';
+ end if;
+ if( is_time_reached(timecounter,10000,CLK_PERIOD) = '1' ) then
+ for i in 0 to 16 loop
+ next_recv_bit(i) <= input(i)(2);
+ end loop;
+ next_recv_bit_ready <= '1';
+ NEXT_STATE <= READ_WAIT;
+ end if;
+
+ when READ_WAIT =>
+ if( is_time_reached(timecounter,80000,CLK_PERIOD) = '1' ) then
+ reset_timecounter <= '1';
+ next_output_tmp <= '0';
+ if ( send_rom = '1' ) then
+ NEXT_STATE <= READ_READ_ROM;
+ elsif( conv_temp = '1' ) then
+ NEXT_STATE <= READ_CONV_TEMP;
+ else
+ NEXT_STATE <= READ_READ_TEMP;
+ end if;
+ end if;
+
+ when others =>
+ NEXT_STATE <= START;
+ end case;
+end process THE_STATE_MACHINE;
+
+-- State machine decoding
+STATE_DECODE: process( STATE )
+begin
+ case STATE is
+ when START => bsm <= x"00";
+ when IDLE => bsm <= x"01";
+ when SEND_RESET => bsm <= x"02";
+ when WAIT_AFTER_RESET => bsm <= x"03";
+ when CHECK_PULSE => bsm <= x"0e";
+ when SEND_ROM_COMMAND => bsm <= x"04";
+ when READ_WAIT => bsm <= x"05";
+ when WRITE_START => bsm <= x"06";
+ when WRITE_WAIT => bsm <= x"07";
+ when READ_BIT => bsm <= x"08";
+ when READ_READ_ROM => bsm <= x"09";
+ when SEND_CONV_TEMP => bsm <= x"0a";
+ when READ_CONV_TEMP => bsm <= x"0b";
+ when SEND_READ_TEMP => bsm <= x"0c";
+ when READ_READ_TEMP => bsm <= x"0d";
+ when others => bsm <= x"ff";
+ end case;
+end process STATE_DECODE;
+--------------------------------------------------------------------------------------
+--------------------------------------------------------------------------------------
+--------------------------------------------------------------------------------------
+
+-- Time counter for 1Wire bus accesses
+THE_TIME_COUNTER: process(clk)
+begin
+ if( rising_edge(clk) ) then
+ if( reset_timecounter = '1' ) then
+ timecounter <= 0;
+ else
+ timecounter <= timecounter + 1;
+ end if;
+ end if;
+end process THE_TIME_COUNTER;
+
+-- Bit counter
+THE_BIT_COUNTER: process(clk)
+begin
+ if( rising_edge(clk) ) then
+ if ( reset_bitcounter = '1' ) then
+ bitcounter <= 0;
+ elsif( inc_bitcounter = '1' ) then
+ bitcounter <= bitcounter + 1;
+ end if;
+ end if;
+end process THE_BIT_COUNTER;
+
+-- Saving received data
+THE_DATA_SAVE_PROC: process(clk)
+begin
+ if( rising_edge(clk) ) then
+ if( reset = '1' ) then
+ ram_addr(1 downto 0) <= (others => '0');
+ ram_wr <= '0';
+-- word(i) <= (others => '0');
+ else
+ ram_wr <= '0';
+ -- Shift process for serial / parallel data conversion
+ if( (recv_bit_ready = '1') and ((send_rom = '1') or (reading_temp = '1')) ) then
+ ram_addr(1 downto 0) <= (bitcounter_vector(5 downto 4)) - 1;
+ ram_addr(2) <= '0';
+ for i in 0 to 16 loop
+ word(i)(14 downto 0) <= word(i)(15 downto 1);
+ word(i)(15) <= recv_bit(i);
+ end loop;
+ -- UniqueID write process
+ if( (bitcounter_vector(3 downto 0) = "0000") and (send_rom = '1') ) then
+ ram_wr <= '1';
+ end if;
+ -- temperature value copy process
+ if( (bitcounter_vector(3 downto 0) = "1100") and (reading_temp = '1') ) then
+ ram_addr <= "100";
+ ram_wr <= '1';
+ for i in 0 to 16 loop
+ word(i)(11) <= recv_bit(i);
+ word(i)(10 downto 0) <= word(i)(15 downto 5);
+ word(i)(14 downto 12) <= (others => '0');
+ word(i)(15) <= presence(i);
+ end loop;
+
+ end if;
+ end if;
+ end if;
+ end if;
+end process THE_DATA_SAVE_PROC;
+
+-- Data output multiplexer
+THE_EXT_ADDR_PROC: process(clk)
+begin
+ if( rising_edge(clk) ) then
+ if( reset = '1' ) then
+ ext_ram_addr <= (others => '0');
+ elsif( (comb_ext_addr_go = '1') ) then
+ ext_ram_addr <= ext_ram_addr + 1;
+ end if;
+ end if;
+end process THE_EXT_ADDR_PROC;
+
+comb_ext_addr_go <= '1' when ((ext_ram_addr /= "0000") or (ram_wr = '1')) else '0';
+
+-- Data multiplexer
+DATA_MUX_PROC: process(clk)
+begin
+ if( rising_edge(clk) ) then
+ case ext_ram_addr is
+ when x"0" => mux_data <= word(0);
+ when x"1" => mux_data <= word(1);
+ when x"2" => mux_data <= word(2);
+ when x"3" => mux_data <= word(3);
+ when x"4" => mux_data <= word(4);
+ when x"5" => mux_data <= word(5);
+ when x"6" => mux_data <= word(6);
+ when x"7" => mux_data <= word(7);
+ when x"8" => mux_data <= word(8);
+ when x"9" => mux_data <= word(9);
+ when x"a" => mux_data <= word(10);
+ when x"b" => mux_data <= word(11);
+ when x"c" => mux_data <= word(12);
+ when x"d" => mux_data <= word(13);
+ when x"e" => mux_data <= word(14);
+ when x"f" => mux_data <= word(15);
+ when others => mux_data <= x"dead";
+ end case;
+ mux_addr(2 downto 0) <= ram_addr;
+ mux_addr(6 downto 3) <= ext_ram_addr;
+ mux_wr <= comb_ext_addr_go; -- really?
+ end if;
+end process DATA_MUX_PROC;
+
+-- Output signals
+bp_data_out <= word(16);
+addr_out <= mux_addr;
+data_out <= mux_data;
+write_out <= mux_wr;
+busy_out <= busy;
+
+bsm_out <= bsm;
+
+-- Status signals
+stat(0) <= '0' when ( input(0)(7) = '0' ) else '1';
+stat(1) <= ram_wr;
+stat(2) <= send_rom;
+stat(3) <= skip_rom;
+stat(4) <= send_bit;
+stat(5) <= recv_bit(0);
+stat(6) <= recv_bit_ready;
+stat(7) <= conv_temp;
+stat(8) <= reading_temp;
+stat(9) <= strong_pullup;
+stat(10) <= reset_bitcounter;
+stat(11) <= inc_bitcounter;
+stat(15 downto 12) <= bitcounter_vector(3 downto 0);
+
+
+end architecture;
+
+
+
+
+
+
+
+
+
--- /dev/null
+[Device]\r
+Family=latticeecp2m\r
+PartType=LFE2M100E\r
+PartName=LFE2M100E-6F900C\r
+SpeedGrade=-6\r
+Package=FPBGA900\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=Distributed_ROM\r
+CoreRevision=2.4\r
+ModuleName=onewire_spare_one\r
+SourceFormat=VHDL\r
+ParameterFileVersion=1.0\r
+Date=11/05/2009\r
+Time=15:51:35\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+Addresses=8\r
+Data=4\r
+LUT=0\r
+MemFile=\\home\mboehmer\vhdl_pro\adcmv3\src\spare_onewire_mapping.mem\r
+MemFormat=orca\r
--- /dev/null
+SCUBA, Version ispLever_v72_SP2_Build (23)
+Thu Nov 05 15:51:35 2009
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp. All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
+Copyright (c) 2001 Agere Systems All rights reserved.
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
+
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n onewire_spare_one -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 3 -num_words 8 -data_width 4 -outdata UNREGISTERED -memfile \\home\mboehmer\vhdl_pro\adcmv3\src\spare_onewire_mapping.mem -memformat orca -e
+ Circuit name : onewire_spare_one
+ Module type : rom
+ Module Version : 2.4
+ Address width : 3
+ Ports :
+ Inputs : Address[2:0]
+ Outputs : Q[3:0]
+ I/O buffer : not inserted
+ Memory file : \\home\mboehmer\vhdl_pro\adcmv3\src\spare_onewire_mapping.mem
+ EDIF output : suppressed
+ VHDL output : onewire_spare_one.vhd
+ VHDL template : onewire_spare_one_tmpl.vhd
+ VHDL testbench : tb_onewire_spare_one_tmpl.vhd
+ VHDL purpose : for synthesis and simulation
+ Bus notation : big endian
+ Report output : onewire_spare_one.srp
+ Element Usage :
+ ROM16X1 : 4
+ Estimated Resource Usage:
+ LUT : 4
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23)
+-- Module Version: 2.4
+--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type rom -addr_width 3 -num_rows 8 -data_width 4 -outdata UNREGISTERED -memfile \\home\mboehmer\vhdl_pro\adcmv3\src\spare_onewire_mapping.mem -memformat orca -e
+
+-- Thu Nov 05 15:51:35 2009
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity onewire_spare_one is
+ port (
+ Address: in std_logic_vector(2 downto 0);
+ Q: out std_logic_vector(3 downto 0));
+end onewire_spare_one;
+
+architecture Structure of onewire_spare_one is
+
+ -- internal signal declarations
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component ROM16X1
+ -- synopsys translate_off
+ generic (initval : in String);
+ -- synopsys translate_on
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ attribute initval : string;
+ attribute initval of mem_0_3 : label is "0x00EA";
+ attribute initval of mem_0_2 : label is "0x00E7";
+ attribute initval of mem_0_1 : label is "0x00EC";
+ attribute initval of mem_0_0 : label is "0x00E0";
+
+begin
+ -- component instantiation statements
+ mem_0_3: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x00EA")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>Address(2), AD1=>Address(1),
+ AD0=>Address(0), DO0=>Q(3));
+
+ mem_0_2: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x00E7")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>Address(2), AD1=>Address(1),
+ AD0=>Address(0), DO0=>Q(2));
+
+ mem_0_1: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x00EC")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>Address(2), AD1=>Address(1),
+ AD0=>Address(0), DO0=>Q(1));
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ mem_0_0: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x00E0")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>Address(2), AD1=>Address(1),
+ AD0=>Address(0), DO0=>Q(0));
+
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of onewire_spare_one is
+ for Structure
+ for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for;
+ for all:VLO use entity ecp2m.VLO(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+Starting process: \r
+\r
+SCUBA, Version ispLever_v72_SP2_Build (23)\r
+Thu Nov 05 15:51:35 2009\r
+\r
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
+Copyright (c) 1995 AT&T Corp. All rights reserved.\r
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
+Copyright (c) 2001 Agere Systems All rights reserved.\r
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
+\r
+BEGIN SCUBA Module Synthesis\r
+\r
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n onewire_spare_one -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 3 -num_words 8 -data_width 4 -outdata UNREGISTERED -memfile \\home\mboehmer\vhdl_pro\adcmv3\src\spare_onewire_mapping.mem -memformat orca -e \r
+ Circuit name : onewire_spare_one\r
+ Module type : rom\r
+ Module Version : 2.4\r
+ Address width : 3\r
+ Data width : 4\r
+ Ports : \r
+ Inputs : Address[2:0]\r
+ Outputs : Q[3:0]\r
+ I/O buffer : not inserted\r
+ Memory file : \\home\mboehmer\vhdl_pro\adcmv3\src\spare_onewire_mapping.mem\r
+ EDIF output : suppressed\r
+ VHDL output : onewire_spare_one.vhd\r
+ VHDL template : onewire_spare_one_tmpl.vhd\r
+ VHDL testbench : tb_onewire_spare_one_tmpl.vhd\r
+ VHDL purpose : for synthesis and simulation\r
+ Bus notation : big endian\r
+ Report output : onewire_spare_one.srp\r
+ Estimated Resource Usage:\r
+ LUT : 4\r
+\r
+END SCUBA Module Synthesis\r
+\r
+File: onewire_spare_one.lpc created.\r
+\r
+\r
+End process: completed successfully.\r
+\r
+\r
+Total Warnings: 0\r
+\r
+Total Errors: 0\r
+\r
+\r
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23)
+-- Module Version: 2.4
+-- Thu Nov 05 15:51:35 2009
+
+-- parameterized module component declaration
+component onewire_spare_one
+ port (Address: in std_logic_vector(2 downto 0);
+ Q: out std_logic_vector(3 downto 0));
+end component;
+
+-- parameterized module component instance
+__ : onewire_spare_one
+ port map (Address(2 downto 0)=>__, Q(3 downto 0)=>__);
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.std_logic_arith.all;\r
+use ieee.std_logic_unsigned.all;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+-- eds_data_in[35:32] = num_frames must be used for checking free space inside ipu_stage.vhd\r
+-- max_space = (num_frames * 128 + num_frames) = num_frames * 129\r
+\r
+entity ped_corr_ctrl is\r
+ port( CLK_IN : in std_logic; -- 100MHz local clock\r
+ RESET_IN : in std_logic; -- synchronous reset\r
+ -- Slow control registers\r
+ -- EDS buffer -- back to previous source stage\r
+ EDS_DATA_IN : in std_logic_vector(39 downto 0); \r
+ EDS_AVAIL_IN : in std_logic;\r
+ EDS_DONE_OUT : out std_logic;\r
+ EVT_TYPE_IN : in std_logic_vector(2 downto 0);\r
+ -- DHDR information -- to next stage\r
+ DHDR_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ DHDR_LENGTH_OUT : out std_logic_vector(15 downto 0);\r
+ DHDR_STORE_OUT : out std_logic;\r
+ DHDR_BUF_FULL_IN : in std_logic;\r
+ -- data buffers -- from raw_buf_stage\r
+ BUF_ADDR_OUT : out std_logic_vector(6 downto 0);\r
+ BUF_DONE_OUT : out std_logic;\r
+ BUF_TICK_IN : in std_logic_vector(15 downto 0);\r
+ BUF_START_IN : in std_logic_vector(15 downto 0);\r
+ -- raw data\r
+ BUF_0_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_1_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_2_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_3_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_4_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_5_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_6_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_7_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_8_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_9_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_10_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_11_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_12_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_13_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_14_DATA_IN : in std_logic_vector(37 downto 0);\r
+ BUF_15_DATA_IN : in std_logic_vector(37 downto 0);\r
+ -- Pedestal data \r
+ PED_ADDR_OUT : out std_logic_vector(6 downto 0);\r
+ PED_0_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_1_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_2_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_3_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_4_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_5_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_6_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_7_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_8_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_9_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_10_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_11_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_12_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_13_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_14_DATA_IN : in std_logic_vector(17 downto 0);\r
+ PED_15_DATA_IN : in std_logic_vector(17 downto 0);\r
+ -- Threshold data\r
+ THR_ADDR_OUT : out std_logic_vector(6 downto 0);\r
+ THR_0_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_1_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_2_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_3_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_4_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_5_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_6_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_7_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_8_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_9_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_10_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_11_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_12_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_13_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_14_DATA_IN : in std_logic_vector(17 downto 0);\r
+ THR_15_DATA_IN : in std_logic_vector(17 downto 0);\r
+ -- processed data\r
+ FIFO_START_OUT : out std_logic;\r
+ FIFO_0_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_1_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_2_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_3_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_4_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_5_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_6_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_7_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_8_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_9_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_10_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_11_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_12_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_13_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_14_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_15_DATA_OUT : out std_logic_vector(39 downto 0);\r
+ FIFO_WE_OUT : out std_logic_vector(15 downto 0);\r
+ FIFO_DONE_OUT : out std_logic; -- write level information into small FIFOs\r
+ -- Debug signals\r
+ DBG_BSM_OUT : out std_logic_vector(7 downto 0);\r
+ DBG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
+end;\r
+\r
+architecture behavioral of ped_corr_ctrl is\r
+\r
+ -- state machine definitions\r
+ type STATES is (SLEEP,LOADFC,DELFC,CHECK,FULL,DEL0,NBERR,EMPTY,CHKFC,FCERR,CHKRW,RWERR,CHKAE,AEERR,\r
+ FINIT,FLOAD,FZERO,FREAD,FDONE,FDEL,FDEC,WREDS,ACKEDS,WHDR,EHDR,CCNT,CDEL0,CDEL1,DEL1,DEL2); \r
+ signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+ -- signals\r
+ signal debug : std_logic_vector(15 downto 0);\r
+ signal bsm_x : std_logic_vector(7 downto 0);\r
+\r
+ -- status signals from TOCs\r
+ signal buf_gooddata : std_logic_vector(15 downto 0);\r
+ signal buf_baddata : std_logic_vector(15 downto 0);\r
+ signal buf_nodata : std_logic_vector(15 downto 0);\r
+ signal buf_ready : std_logic_vector(15 downto 0);\r
+\r
+ -- local frame counter\r
+ signal to_do_ctr : std_logic_vector(3 downto 0);\r
+ signal done_ctr : std_logic_vector(3 downto 0);\r
+ signal loc_frm_ctr : std_logic_vector(3 downto 0);\r
+ signal next_ld_frm_ctr : std_logic;\r
+ signal ld_frm_ctr : std_logic; -- load frame counter with EDS start value \r
+ signal next_ce_frm_ctr : std_logic;\r
+ signal ce_frm_ctr : std_logic; -- increment frame counter\r
+ signal next_last_frame : std_logic;\r
+ signal last_frame : std_logic; -- all frame buffers have been copied\r
+ signal next_cleaned_up : std_logic;\r
+ signal cleaned_up : std_logic; -- only relevant in case of errors\r
+ signal next_multi_frame : std_logic;\r
+ signal multi_frame : std_logic; -- more than one frame requested\r
+ signal next_do_hdr : std_logic;\r
+ signal do_hdr : std_logic; -- insert debug header (in case of common errors, in case of multiframe)\r
+ signal next_do_error : std_logic;\r
+ signal do_error : std_logic; -- insert debug header (in case of broken buffer only) \r
+ signal next_do_start : std_logic; \r
+ signal do_start : std_logic; -- start signal for one event processing\r
+ \r
+ -- buffer status signals, error signals from checkers\r
+ signal buffers_ready : std_logic; -- all buffers are ready for data transport\r
+ signal buffers_valid : std_logic; -- at least one buffer has valid data\r
+ signal frame_row_error : std_logic; \r
+ signal frame_apv_error : std_logic;\r
+ signal frame_ctr_error : std_logic;\r
+ \r
+ signal frame_busy : std_logic; -- from ALU\r
+ \r
+ -- Buffer read address counter, control signals\r
+ signal buf_addr : std_logic_vector(5 downto 0); -- buffer / pedestal read address\r
+ signal buf_half : std_logic;\r
+ signal next_buf_addr_ce : std_logic;\r
+ signal buf_addr_ce : std_logic;\r
+ signal next_buf_addr_rst : std_logic;\r
+ signal buf_addr_rst : std_logic;\r
+ signal next_buf_addr_init : std_logic; -- needed for THR\r
+ signal buf_addr_init : std_logic;\r
+ signal next_buf_addr_done : std_logic;\r
+ signal buf_addr_done : std_logic;\r
+ signal next_buf_done : std_logic;\r
+ signal buf_done : std_logic;\r
+ signal next_frame_valid : std_logic;\r
+ signal frame_valid : std_logic;\r
+ signal buf_frame_valid : std_logic;\r
+ signal raw_addr : std_logic_vector(6 downto 0);\r
+ signal buf_raw_addr : std_logic_vector(6 downto 0);\r
+\r
+ signal thr_addr : std_logic_vector(6 downto 0); -- threshold read address\r
+ signal thr_addr_ce : std_logic;\r
+ signal thr_addr_rst : std_logic;\r
+ signal dly_thr_addr_ce : std_logic_vector(7 downto 0);\r
+ signal dly_thr_addr_rst : std_logic_vector(7 downto 0);\r
+\r
+-- signal ped_addr : std_logic_vector(6 downto 0); -- pedestal read address\r
+\r
+ -- statemachine signals\r
+ signal next_wait_frames : std_logic;\r
+ signal wait_frames : std_logic; -- we are in the waiting phase for incoming frames\r
+ signal next_eds_wr : std_logic;\r
+ signal eds_wr : std_logic; -- copy current EDS into new buffer\r
+ signal next_eds_done : std_logic;\r
+ signal eds_done : std_logic; -- acknowledge and release old EDS\r
+\r
+ -- generate needs arrays...\r
+ type raw_data_t is array (0 to 15) of std_logic_vector(37 downto 0);\r
+ signal raw_data : raw_data_t;\r
+ type fifo_data_t is array (0 to 15) of std_logic_vector(39 downto 0);\r
+ signal fifo_data : fifo_data_t;\r
+ type sc_data_t is array (0 to 15) of std_logic_vector(17 downto 0);\r
+ signal ped_data : sc_data_t;\r
+ signal thr_data : sc_data_t;\r
+\r
+ signal fifo_we : std_logic_vector(15 downto 0);\r
+\r
+ signal errors : std_logic_vector(3 downto 0);\r
+\r
+ -- for summing up\r
+ signal next_small_0_sum : std_logic_vector(4 downto 0);\r
+ signal small_0_sum : std_logic_vector(4 downto 0);\r
+ signal next_small_1_sum : std_logic_vector(4 downto 0);\r
+ signal small_1_sum : std_logic_vector(4 downto 0);\r
+ signal small_sum : std_logic_vector(15 downto 0);\r
+ signal total_sum : std_logic_vector(15 downto 0);\r
+ signal reset_sum : std_logic;\r
+\r
+\r
+begin\r
+\r
+---------------------------------------------------------------------------\r
+-- Aliasing the data streams\r
+---------------------------------------------------------------------------\r
+raw_data(0) <= buf_0_data_in;\r
+raw_data(1) <= buf_1_data_in;\r
+raw_data(2) <= buf_2_data_in;\r
+raw_data(3) <= buf_3_data_in;\r
+raw_data(4) <= buf_4_data_in;\r
+raw_data(5) <= buf_5_data_in;\r
+raw_data(6) <= buf_6_data_in;\r
+raw_data(7) <= buf_7_data_in;\r
+raw_data(8) <= buf_8_data_in;\r
+raw_data(9) <= buf_9_data_in;\r
+raw_data(10) <= buf_10_data_in;\r
+raw_data(11) <= buf_11_data_in;\r
+raw_data(12) <= buf_12_data_in;\r
+raw_data(13) <= buf_13_data_in;\r
+raw_data(14) <= buf_14_data_in;\r
+raw_data(15) <= buf_15_data_in;\r
+\r
+ped_data(0) <= ped_0_data_in;\r
+ped_data(1) <= ped_1_data_in;\r
+ped_data(2) <= ped_2_data_in;\r
+ped_data(3) <= ped_3_data_in;\r
+ped_data(4) <= ped_4_data_in;\r
+ped_data(5) <= ped_5_data_in;\r
+ped_data(6) <= ped_6_data_in;\r
+ped_data(7) <= ped_7_data_in;\r
+ped_data(8) <= ped_8_data_in;\r
+ped_data(9) <= ped_9_data_in;\r
+ped_data(10) <= ped_10_data_in;\r
+ped_data(11) <= ped_11_data_in;\r
+ped_data(12) <= ped_12_data_in;\r
+ped_data(13) <= ped_13_data_in;\r
+ped_data(14) <= ped_14_data_in;\r
+ped_data(15) <= ped_15_data_in;\r
+\r
+thr_data(0) <= thr_0_data_in;\r
+thr_data(1) <= thr_1_data_in;\r
+thr_data(2) <= thr_2_data_in;\r
+thr_data(3) <= thr_3_data_in;\r
+thr_data(4) <= thr_4_data_in;\r
+thr_data(5) <= thr_5_data_in;\r
+thr_data(6) <= thr_6_data_in;\r
+thr_data(7) <= thr_7_data_in;\r
+thr_data(8) <= thr_8_data_in;\r
+thr_data(9) <= thr_9_data_in;\r
+thr_data(10) <= thr_10_data_in;\r
+thr_data(11) <= thr_11_data_in;\r
+thr_data(12) <= thr_12_data_in;\r
+thr_data(13) <= thr_13_data_in;\r
+thr_data(14) <= thr_14_data_in;\r
+thr_data(15) <= thr_15_data_in;\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- framecounter check, must be done once per frame\r
+---------------------------------------------------------------------------\r
+THE_FRMCTR_CHECK: frmctr_check\r
+port map( CLK_IN => clk_in,\r
+ GOODDATA_IN => buf_gooddata,\r
+ FRAMECOUNTER_IN => loc_frm_ctr,\r
+ FRM_NR_0_IN => raw_data(0)(17 downto 14),\r
+ FRM_NR_1_IN => raw_data(1)(17 downto 14),\r
+ FRM_NR_2_IN => raw_data(2)(17 downto 14),\r
+ FRM_NR_3_IN => raw_data(3)(17 downto 14),\r
+ FRM_NR_4_IN => raw_data(4)(17 downto 14),\r
+ FRM_NR_5_IN => raw_data(5)(17 downto 14),\r
+ FRM_NR_6_IN => raw_data(6)(17 downto 14),\r
+ FRM_NR_7_IN => raw_data(7)(17 downto 14),\r
+ FRM_NR_8_IN => raw_data(8)(17 downto 14),\r
+ FRM_NR_9_IN => raw_data(9)(17 downto 14),\r
+ FRM_NR_10_IN => raw_data(10)(17 downto 14),\r
+ FRM_NR_11_IN => raw_data(11)(17 downto 14),\r
+ FRM_NR_12_IN => raw_data(12)(17 downto 14),\r
+ FRM_NR_13_IN => raw_data(13)(17 downto 14),\r
+ FRM_NR_14_IN => raw_data(14)(17 downto 14),\r
+ FRM_NR_15_IN => raw_data(15)(17 downto 14),\r
+ FRC_ERROR_OUT => frame_ctr_error, -- BUG\r
+ DBG_OUT => open\r
+ );\r
+\r
+---------------------------------------------------------------------------\r
+-- framewise ROW and ERROR checker\r
+---------------------------------------------------------------------------\r
+THE_REF_ROW_SEL: ref_row_sel\r
+port map( CLK_IN => clk_in,\r
+ READY_IN => buf_ready,\r
+ GOODDATA_IN => buf_gooddata,\r
+ FRAME_0_IN => raw_data(0)(29 downto 18),\r
+ FRAME_1_IN => raw_data(1)(29 downto 18),\r
+ FRAME_2_IN => raw_data(2)(29 downto 18),\r
+ FRAME_3_IN => raw_data(3)(29 downto 18),\r
+ FRAME_4_IN => raw_data(4)(29 downto 18),\r
+ FRAME_5_IN => raw_data(5)(29 downto 18),\r
+ FRAME_6_IN => raw_data(6)(29 downto 18),\r
+ FRAME_7_IN => raw_data(7)(29 downto 18),\r
+ FRAME_8_IN => raw_data(8)(29 downto 18),\r
+ FRAME_9_IN => raw_data(9)(29 downto 18),\r
+ FRAME_10_IN => raw_data(10)(29 downto 18),\r
+ FRAME_11_IN => raw_data(11)(29 downto 18),\r
+ FRAME_12_IN => raw_data(12)(29 downto 18),\r
+ FRAME_13_IN => raw_data(13)(29 downto 18),\r
+ FRAME_14_IN => raw_data(14)(29 downto 18),\r
+ FRAME_15_IN => raw_data(15)(29 downto 18),\r
+ VALID_BUFS_OUT => buffers_valid,\r
+ READY_OUT => buffers_ready,\r
+ ROW_ERROR_OUT => frame_row_error,\r
+ APV_ERROR_OUT => frame_apv_error,\r
+ APV_ERROR_BITS_OUT => open, -- BUGBUGBUG\r
+ REF_ROW_OUT => open, -- selected reference row\r
+ DBG_OUT => open\r
+ );\r
+\r
+---------------------------------------------------------------------------\r
+-- Statemachine\r
+---------------------------------------------------------------------------\r
+\r
+-- state registers\r
+STATE_MEM: process( clk_in ) \r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ CURRENT_STATE <= SLEEP;\r
+ wait_frames <= '0';\r
+ ld_frm_ctr <= '0';\r
+ ce_frm_ctr <= '0';\r
+ eds_done <= '0';\r
+ eds_wr <= '0';\r
+ buf_addr_rst <= '0';\r
+ buf_addr_init <= '0';\r
+ buf_addr_ce <= '0';\r
+ frame_valid <= '0';\r
+ do_hdr <= '0';\r
+ do_error <= '0';\r
+ do_start <= '0';\r
+ else\r
+ CURRENT_STATE <= NEXT_STATE;\r
+ wait_frames <= next_wait_frames;\r
+ ld_frm_ctr <= next_ld_frm_ctr;\r
+ ce_frm_ctr <= next_ce_frm_ctr;\r
+ buf_done <= next_buf_done;\r
+ eds_done <= next_eds_done;\r
+ eds_wr <= next_eds_wr;\r
+ buf_addr_rst <= next_buf_addr_rst;\r
+ buf_addr_init <= next_buf_addr_init;\r
+ buf_addr_ce <= next_buf_addr_ce;\r
+ frame_valid <= next_frame_valid;\r
+ do_hdr <= next_do_hdr;\r
+ do_error <= next_do_error;\r
+ do_start <= next_do_start;\r
+ end if;\r
+ end if;\r
+end process STATE_MEM;\r
+\r
+-- Error pattern\r
+errors(3) <= not buffers_valid;\r
+errors(2) <= frame_ctr_error;\r
+errors(1) <= frame_row_error;\r
+errors(0) <= frame_apv_error;\r
+\r
+-- state transitions\r
+STATE_TRANSFORM: process( CURRENT_STATE, eds_avail_in, dhdr_buf_full_in, last_frame, multi_frame, frame_busy, \r
+ buffers_ready, buffers_valid, frame_ctr_error, frame_row_error, frame_apv_error, \r
+ buf_addr_done, buf_half )\r
+begin\r
+ NEXT_STATE <= SLEEP; -- avoid latches\r
+ next_wait_frames <= '0';\r
+ next_ld_frm_ctr <= '0';\r
+ next_ce_frm_ctr <= '0';\r
+ next_buf_done <= '0';\r
+ next_eds_done <= '0';\r
+ next_eds_wr <= '0';\r
+ next_buf_addr_rst <= '0';\r
+ next_buf_addr_init <= '0';\r
+ next_buf_addr_ce <= '0';\r
+ next_frame_valid <= '0';\r
+ next_do_hdr <= '0';\r
+ next_do_error <= '0';\r
+ next_do_start <= '0';\r
+ case CURRENT_STATE is\r
+ when SLEEP => if( (eds_avail_in = '1') and (dhdr_buf_full_in = '0') ) then\r
+ NEXT_STATE <= LOADFC;\r
+ next_ld_frm_ctr <= '1';\r
+ else\r
+ NEXT_STATE <= SLEEP;\r
+ end if;\r
+ when LOADFC => NEXT_STATE <= DELFC;\r
+ next_do_start <= '1';\r
+ when DELFC => NEXT_STATE <= CHECK;\r
+ when CHECK => if( last_frame = '0' ) then\r
+ NEXT_STATE <= FULL;\r
+ next_wait_frames <= '1';\r
+ else\r
+ NEXT_STATE <= EMPTY;\r
+ end if;\r
+ when EMPTY => NEXT_STATE <= WREDS;\r
+ next_eds_wr <= '1';\r
+ when FULL => if( buffers_ready = '1' ) then\r
+ NEXT_STATE <= DEL0;\r
+ next_do_error <= '1'; -- here broken channels deliver a "I DON'T FEEL GOOD" word...\r
+ else\r
+ NEXT_STATE <= FULL;\r
+ next_wait_frames <= '1';\r
+ end if;\r
+ when DEL0 => if ( buffers_valid = '1' ) then\r
+ NEXT_STATE <= CHKFC;\r
+ else\r
+ NEXT_STATE <= NBERR;\r
+ end if;\r
+ when CHKFC => if( frame_ctr_error = '0' ) then\r
+ NEXT_STATE <= CHKRW;\r
+ else\r
+ NEXT_STATE <= FCERR;\r
+ end if;\r
+ when CHKRW => if( frame_row_error = '0' ) then\r
+ NEXT_STATE <= CHKAE;\r
+ else\r
+ NEXT_STATE <= RWERR;\r
+ end if;\r
+ when CHKAE => if ( (frame_apv_error = '0') and (multi_frame = '1') ) then\r
+ NEXT_STATE <= WHDR;\r
+ next_do_hdr <= '1';\r
+ elsif( (frame_apv_error = '0') and (multi_frame = '0') ) then\r
+ NEXT_STATE <= FINIT;\r
+ next_buf_addr_rst <= '1';\r
+ else\r
+ NEXT_STATE <= AEERR;\r
+ end if;\r
+ when WHDR => NEXT_STATE <= FINIT;\r
+ next_buf_addr_rst <= '1';\r
+ when FINIT => NEXT_STATE <= FLOAD; -- load address x"01";\r
+ next_buf_addr_ce <= '1';\r
+ when FLOAD => NEXT_STATE <= FZERO; -- load address x"00";\r
+ next_buf_addr_rst <= '1';\r
+ next_buf_addr_init <= not buf_half;\r
+ when FZERO => NEXT_STATE <= FREAD;\r
+ next_buf_addr_ce <= '1';\r
+ when FREAD => if ( (buf_addr_done = '1') and (buf_half = '1') ) then\r
+ NEXT_STATE <= FDONE;\r
+ next_ce_frm_ctr <= '1';\r
+ next_buf_done <= '1';\r
+ next_frame_valid <= '1';\r
+ elsif( (buf_addr_done = '1') and (buf_half = '0') ) then\r
+ NEXT_STATE <= FINIT;\r
+ next_frame_valid <= '1';\r
+ else\r
+ NEXT_STATE <= FREAD; -- read buffer completely\r
+ next_buf_addr_ce <= '1';\r
+ next_frame_valid <= '1';\r
+ end if;\r
+ when FDONE => if( frame_busy = '1' ) then\r
+ NEXT_STATE <= FDONE;\r
+ else\r
+ NEXT_STATE <= FDEL;\r
+ end if;\r
+ when FDEL => NEXT_STATE <= FDEC;\r
+ when FDEC => if( last_frame = '1' ) then\r
+ NEXT_STATE <= WREDS; -- copy current EDS to new buffer\r
+ next_eds_wr <= '1';\r
+ else\r
+ NEXT_STATE <= DEL0; -- only for multiframe readout, will not work (needs headers!!!)\r
+ end if;\r
+ when WREDS => NEXT_STATE <= ACKEDS; -- release old EDS\r
+ next_eds_done <= '1';\r
+ when ACKEDS => NEXT_STATE <= DEL1;\r
+ when DEL1 => NEXT_STATE <= DEL2;\r
+ when DEL2 => NEXT_STATE <= SLEEP;\r
+ \r
+ when NBERR => NEXT_STATE <= EHDR;\r
+ next_do_hdr <= '1';\r
+ when FCERR => NEXT_STATE <= EHDR;\r
+ next_do_hdr <= '1';\r
+ when RWERR => NEXT_STATE <= EHDR;\r
+ next_do_hdr <= '1';\r
+ when AEERR => NEXT_STATE <= EHDR;\r
+ next_do_hdr <= '1';\r
+ when EHDR => if( last_frame = '1' ) then\r
+ NEXT_STATE <= WREDS;\r
+ next_eds_wr <= '1';\r
+ else\r
+ NEXT_STATE <= CCNT;\r
+ next_ce_frm_ctr <= '1';\r
+ next_buf_done <= '1';\r
+ end if;\r
+ when CCNT => NEXT_STATE <= CDEL0;\r
+ when CDEL0 => NEXT_STATE <= CDEL1;\r
+ when CDEL1 => if( last_frame = '1' ) then\r
+ NEXT_STATE <= WREDS;\r
+ next_eds_wr <= '1';\r
+ else\r
+ NEXT_STATE <= EHDR;\r
+ next_do_hdr <= '1';\r
+ end if;\r
+ when others => NEXT_STATE <= SLEEP;\r
+ end case;\r
+end process STATE_TRANSFORM; \r
+\r
+-- state decoding (ONLY FOR DEBUGGING!)\r
+STATE_DECODE: process( CURRENT_STATE )\r
+begin\r
+ case CURRENT_STATE is\r
+ when SLEEP => bsm_x <= x"00";\r
+ when LOADFC => bsm_x <= x"01";\r
+ when DELFC => bsm_x <= x"02";\r
+ when CHECK => bsm_x <= x"03";\r
+ when FULL => bsm_x <= x"04";\r
+ when EMPTY => bsm_x <= x"05";\r
+ when NBERR => bsm_x <= x"06";\r
+ when CHKFC => bsm_x <= x"07";\r
+ when FCERR => bsm_x <= x"08";\r
+ when CHKRW => bsm_x <= x"09";\r
+ when RWERR => bsm_x <= x"0a";\r
+ when CHKAE => bsm_x <= x"0b";\r
+ when AEERR => bsm_x <= x"0c";\r
+ when FINIT => bsm_x <= x"0d";\r
+ when FLOAD => bsm_x <= x"0e";\r
+ when FZERO => bsm_x <= x"0f";\r
+ when FREAD => bsm_x <= x"10";\r
+ when FDONE => bsm_x <= x"11";\r
+ when FDEL => bsm_x <= x"12";\r
+ when FDEC => bsm_x <= x"13";\r
+ when WREDS => bsm_x <= x"14";\r
+ when ACKEDS => bsm_x <= x"15";\r
+ when EHDR => bsm_x <= x"16";\r
+ when CDEL0 => bsm_x <= x"17";\r
+ when CDEL1 => bsm_x <= x"18";\r
+ when CCNT => bsm_x <= x"19";\r
+ when DEL0 => bsm_x <= x"20";\r
+ when DEL1 => bsm_x <= x"21";\r
+ when DEL2 => bsm_x <= x"22";\r
+ when WHDR => bsm_x <= x"23";\r
+ when others => bsm_x <= x"ff";\r
+ end case;\r
+end process STATE_DECODE;\r
+\r
+---------------------------------------------------------------------------\r
+-- Buffer address counter, fetches raw data and pedestal values from EBRs\r
+---------------------------------------------------------------------------\r
+THE_BUF_ADDR_COUNTER_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( (buf_addr_rst = '1') or (reset_in = '1') ) then\r
+ buf_addr <= (others => '0');\r
+ elsif( buf_addr_ce = '1' ) then\r
+ buf_addr <= buf_addr + 1;\r
+ end if;\r
+ end if;\r
+end process THE_BUF_ADDR_COUNTER_PROC;\r
+\r
+next_buf_addr_done <= '1' when ( buf_addr = "111110" ) else '0';\r
+\r
+THE_HALF_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( (ld_frm_ctr = '1') or (reset_in = '1') ) then\r
+ buf_half <= '0';\r
+ elsif( (buf_addr_done = '1') and (buf_half = '0') ) then\r
+ buf_half <= '1';\r
+ elsif( (buf_addr_done = '1') and (buf_half = '1') ) then\r
+ buf_half <= '0';\r
+ end if;\r
+ end if;\r
+end process THE_HALF_PROC;\r
+\r
+raw_addr <= buf_half & buf_addr;\r
+\r
+---------------------------------------------------------------------------\r
+-- threshold address counter\r
+---------------------------------------------------------------------------\r
+THE_THR_ADDR_COUNTER_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( (thr_addr_rst = '1') or (reset_in = '1') ) then\r
+ thr_addr <= (others => '0');\r
+ elsif( thr_addr_ce = '1' ) then\r
+ thr_addr <= thr_addr + 1;\r
+ end if;\r
+ end if;\r
+end process THE_THR_ADDR_COUNTER_PROC;\r
+\r
+-- was '3'\r
+thr_addr_ce <= dly_thr_addr_ce(2);\r
+thr_addr_rst <= dly_thr_addr_rst(2);\r
+\r
+---------------------------------------------------------------------------\r
+-- local frame counter, loaded / counted by SM for checking\r
+---------------------------------------------------------------------------\r
+THE_LOC_FRAME_COUNTER_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( reset_in = '1' ) then\r
+ loc_frm_ctr <= (others => '0');\r
+ to_do_ctr <= (others => '0');\r
+ done_ctr <= (others => '0');\r
+ elsif( ld_frm_ctr = '1' ) then\r
+ loc_frm_ctr <= eds_data_in(39 downto 36);\r
+ to_do_ctr <= eds_data_in(35 downto 32);\r
+ done_ctr <= (others => '0');\r
+ elsif( ce_frm_ctr = '1' ) then\r
+ loc_frm_ctr <= loc_frm_ctr + 1; -- local frame counter\r
+ to_do_ctr <= to_do_ctr - 1; -- frames still to process\r
+ done_ctr <= done_ctr + 1; -- frames already processed\r
+ end if;\r
+ end if;\r
+end process THE_LOC_FRAME_COUNTER_PROC;\r
+\r
+-- check if we have still buffers to copy\r
+next_last_frame <= '1' when ( to_do_ctr = x"0" ) else '0';\r
+\r
+-- check if we have clean up the mess in case of error\r
+next_cleaned_up <= '1' when ( done_ctr = x"0" ) else '0';\r
+\r
+-- insert administration words if more than one frame is requested (MULTIFRAME)\r
+next_multi_frame <= '1' when ( eds_data_in(35 downto 32) > x"1" ) else '0';\r
+\r
+---------------------------------------------------------------------------\r
+-- synchronizing process\r
+---------------------------------------------------------------------------\r
+THE_SYNC_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ last_frame <= next_last_frame;\r
+ multi_frame <= next_multi_frame;\r
+ cleaned_up <= next_cleaned_up;\r
+ buf_addr_done <= next_buf_addr_done;\r
+ buf_frame_valid <= frame_valid;\r
+ buf_raw_addr <= raw_addr;\r
+ small_0_sum <= next_small_0_sum;\r
+ small_1_sum <= next_small_1_sum;\r
+ dly_thr_addr_ce(7 downto 0) <= dly_thr_addr_ce(6 downto 0) & buf_addr_ce;\r
+ dly_thr_addr_rst(7 downto 0) <= dly_thr_addr_rst(6 downto 0) & buf_addr_init;\r
+ end if;\r
+end process THE_SYNC_PROC;\r
+\r
+---------------------------------------------------------------------------\r
+-- DHDR information assembly\r
+---------------------------------------------------------------------------\r
+dhdr_data_out(31 downto 29) <= "000"; -- reserved bits\r
+dhdr_data_out(28) <= '1'; -- packbit\r
+dhdr_data_out(27 downto 24) <= eds_data_in(7 downto 4);\r
+dhdr_data_out(23 downto 16) <= eds_data_in(15 downto 8);\r
+dhdr_data_out(15 downto 0) <= eds_data_in(31 downto 16);\r
+\r
+dhdr_length_out <= total_sum;\r
+\r
+dhdr_store_out <= eds_wr;\r
+\r
+--##########################################################################\r
+--##########################################################################\r
+\r
+-- generate TimeOutCounters for all 16 APVs\r
+GEN_TOC: for i in 0 to 15 generate\r
+ THE_BUF_TOC: buf_toc\r
+ port map( CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ BUF_TICK_IN => buf_tick_in(i),\r
+ BUF_START_IN => buf_start_in(i),\r
+ WAITFRAME_IN => wait_frames,\r
+ FRAMES_REQD_IN => eds_data_in(35 downto 32), -- always the same\r
+ BUF_LVL_IN => raw_data(i)(37 downto 30),\r
+ GOODDATA_OUT => buf_gooddata(i),\r
+ BADDATA_OUT => buf_baddata(i),\r
+ NODATA_OUT => buf_nodata(i),\r
+ READY_OUT => buf_ready(i),\r
+ BSM_OUT => open,\r
+ DBG_OUT => open\r
+ );\r
+end generate GEN_TOC;\r
+\r
+-- generate ALUs for all 16 APV data streams\r
+GEN_ALU: for i in 0 to 15 generate\r
+ THE_ALU: apv_pc_nc_alu\r
+ port map( CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ START_IN => ld_frm_ctr,\r
+ MAX_FRAMES_IN => eds_data_in(35 downto 32),\r
+ CURR_FRAME_IN => done_ctr,\r
+ LOC_FRM_CTR_IN => loc_frm_ctr, -- DEBUG\r
+ EDS_FRM_CTR_IN => eds_data_in(39 downto 36), -- DEBUG\r
+ BUF_GOOD_IN => buf_gooddata(i),\r
+ BUF_BAD_IN => buf_baddata(i),\r
+ BUF_IGNORE_IN => buf_nodata(i),\r
+ ERROR_IN => errors,\r
+ DO_HEADER_IN => do_hdr,\r
+ DO_ERROR_IN => do_error,\r
+ EVT_TYPE_IN => eds_data_in(6 downto 4), --evt_type_in, -- just a quick fix, does not work lateron!\r
+ RAW_ADDR_IN => buf_raw_addr, -- delayed by one cycle\r
+ RAW_DATA_IN => raw_data(i),\r
+ PED_DATA_IN => ped_data(i),\r
+ THR_DATA_IN => thr_data(i),\r
+ FRAME_IN => buf_frame_valid, -- delayed by one cycle\r
+ FIFO_DATA_OUT => fifo_data(i)(26 downto 0),\r
+ WE_OUT => fifo_we(i),\r
+ COUNT_OUT => fifo_data(i)(36 downto 27),\r
+ ANYDATA_OUT => fifo_data(i)(37),\r
+ DBG_OUT => open\r
+ );\r
+ fifo_data(i)(39) <= '0';\r
+ fifo_data(i)(38) <= '0';\r
+end generate GEN_ALU;\r
+\r
+frame_busy <= fifo_data(0)(26); -- WORKAROUND!\r
+\r
+--##################################################################################\r
+---------------------------------------------------------------------------\r
+-- Sum up all data words of one event\r
+---------------------------------------------------------------------------\r
+THE_DECODER_0: decoder_8bit\r
+port map( ADDRESS => fifo_we(7 downto 0),\r
+ Q => next_small_0_sum(3 downto 0)\r
+ );\r
+next_small_0_sum(4) <= '0';\r
+\r
+THE_DECODER_1: decoder_8bit\r
+port map( ADDRESS => fifo_we(15 downto 8),\r
+ Q => next_small_1_sum(3 downto 0)\r
+ );\r
+next_small_1_sum(4) <= '0';\r
+\r
+reset_sum <= reset_in or ld_frm_ctr;\r
+\r
+THE_FIRST_ADDER: adder_5bit\r
+port map( DATAA => small_0_sum,\r
+ DATAB => small_1_sum,\r
+ CLOCK => clk_in, \r
+ RESET => reset_sum, -- BUG\r
+ CLOCKEN => '1', \r
+ RESULT => small_sum(4 downto 0)\r
+ );\r
+small_sum(15 downto 5) <= (others => '0');\r
+\r
+THE_ACCUMULATOR: adder_16bit\r
+port map( DATAA => small_sum,\r
+ DATAB => total_sum,\r
+ CLOCK => clk_in, \r
+ RESET => reset_sum, -- BUG \r
+ CLOCKEN => '1',\r
+ RESULT => total_sum\r
+ );\r
+\r
+fifo_we_out <= fifo_we;\r
+fifo_start_out <= do_start;\r
+fifo_done_out <= eds_wr;\r
+--##################################################################################\r
+\r
+\r
+-- Aliasing the data output\r
+fifo_0_data_out <= fifo_data(0);\r
+fifo_1_data_out <= fifo_data(1);\r
+fifo_2_data_out <= fifo_data(2);\r
+fifo_3_data_out <= fifo_data(3);\r
+fifo_4_data_out <= fifo_data(4);\r
+fifo_5_data_out <= fifo_data(5);\r
+fifo_6_data_out <= fifo_data(6);\r
+fifo_7_data_out <= fifo_data(7);\r
+fifo_8_data_out <= fifo_data(8);\r
+fifo_9_data_out <= fifo_data(9);\r
+fifo_10_data_out <= fifo_data(10);\r
+fifo_11_data_out <= fifo_data(11);\r
+fifo_12_data_out <= fifo_data(12);\r
+fifo_13_data_out <= fifo_data(13);\r
+fifo_14_data_out <= fifo_data(14);\r
+fifo_15_data_out <= fifo_data(15);\r
+\r
+---------------------------------------------------------------------------\r
+---------------------------------------------------------------------------\r
+debug(15) <= frame_valid;\r
+debug(14) <= buf_frame_valid;\r
+debug(13 downto 0) <= (others => '0');\r
+--debug(15) <= last_frame;\r
+--debug(14) <= cleaned_up;\r
+--debug(13 downto 12) <= (others => '0');\r
+--debug(11 downto 8) <= loc_frm_ctr;\r
+--debug(7 downto 4) <= to_do_ctr;\r
+--debug(3 downto 0) <= done_ctr;\r
+---------------------------------------------------------------------------\r
+---------------------------------------------------------------------------\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- Output signals\r
+---------------------------------------------------------------------------\r
+eds_done_out <= eds_done;\r
+buf_done_out <= buf_done;\r
+buf_addr_out <= raw_addr;\r
+ped_addr_out <= raw_addr;\r
+thr_addr_out <= thr_addr;\r
+\r
+---------------------------------------------------------------------------\r
+-- DEBUG signals\r
+---------------------------------------------------------------------------\r
+dbg_bsm_out <= bsm_x;\r
+dbg_out <= debug;\r
+\r
+end behavioral;\r
+\r
+\r
+ \r
+\r
+\r
--- /dev/null
+#Format=AddrHex
+#Depth=1024
+#Width=18
+#AddrRadix=3
+#DataRadix=3
+#Data
+000: 00000 00000 00000 00000 00000 00000 00000 00000
+008: 00000 00000 00000 00000 00000 00000 00000 00000
+010: 00000 00000 00000 00000 00000 00000 00000 00000
+018: 00000 00000 00000 00000 00000 00000 00000 00000
+020: 00000 00000 00000 00000 00000 00000 00000 00000
+028: 00000 00000 00000 00000 00000 00000 00000 00000
+030: 00000 00000 00000 00000 00000 00000 00000 00000
+038: 00000 00000 00000 00000 00000 00000 00000 00000
+040: 00000 00000 00000 00000 00000 00000 00000 00000
+048: 00000 00000 00000 00000 00000 00000 00000 00000
+050: 00000 00000 00000 00000 00000 00000 00000 00000
+058: 00000 00000 00000 00000 00000 00000 00000 00000
+060: 00000 00000 00000 00000 00000 00000 00000 00000
+068: 00000 00000 00000 00000 00000 00000 00000 00000
+070: 00000 00000 00000 00000 00000 00000 00000 00000
+078: 00000 00000 00000 00000 00000 00000 00000 00000
--- /dev/null
+[Device]\r
+Family=latticeecp2m\r
+PartType=LFE2M100E\r
+PartName=LFE2M100E-6F900C\r
+SpeedGrade=-6\r
+Package=FPBGA900\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=RAM_DP_TRUE\r
+CoreRevision=7.1\r
+ModuleName=ped_thr_true\r
+SourceFormat=VHDL\r
+ParameterFileVersion=1.0\r
+Date=09/14/2009\r
+Time=12:54:09\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+AAddress=128\r
+BAddress=128\r
+AData=18\r
+BData=18\r
+enByte=0\r
+ByteSize=9\r
+AadPipeline=0\r
+BadPipeline=0\r
+AinPipeline=0\r
+BinPipeline=0\r
+AoutPipeline=1\r
+BoutPipeline=1\r
+AMOR=0\r
+BMOR=0\r
+AInData=Registered\r
+BInData=Registered\r
+AAdControl=Registered\r
+BAdControl=Registered\r
+MemFile=\r
+MemFormat=bin\r
+Reset=Sync\r
+GSR=Enabled\r
+WriteA=Normal\r
+WriteB=Normal\r
+Pad=0\r
+EnECC=0\r
+Optimization=Speed\r
+Pipeline=0\r
--- /dev/null
+SCUBA, Version ispLever_v72_SP2_Build (23)
+Mon Sep 14 12:54:09 2009
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp. All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
+Copyright (c) 2001 Agere Systems All rights reserved.
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
+
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n ped_thr_true -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ramdp -device LFE2M100E -aaddr_width 7 -widtha 18 -baddr_width 7 -widthb 18 -anum_words 128 -bnum_words 128 -outdataA REGISTERED -outdataB REGISTERED -writemodeA NORMAL -writemodeB NORMAL -resetmode SYNC -cascade -1 -e
+ Circuit name : ped_thr_true
+ Module type : RAM_DP_TRUE
+ Module Version : 7.1
+ Ports :
+ Inputs : DataInA[17:0], DataInB[17:0], AddressA[6:0], AddressB[6:0], ClockA, ClockB, ClockEnA, ClockEnB, WrA, WrB, ResetA, ResetB
+ Outputs : QA[17:0], QB[17:0]
+ I/O buffer : not inserted
+ EDIF output : suppressed
+ VHDL output : ped_thr_true.vhd
+ VHDL template : ped_thr_true_tmpl.vhd
+ VHDL testbench : tb_ped_thr_true_tmpl.vhd
+ VHDL purpose : for synthesis and simulation
+ Bus notation : big endian
+ Report output : ped_thr_true.srp
+ Element Usage :
+ DP16KB : 1
+ Estimated Resource Usage:
+ EBR : 1
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23)
+-- Module Version: 7.1
+--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type bram -wp 11 -rp 1010 -data_width 18 -rdata_width 18 -num_rows 128 -outdataA REGISTERED -outdataB REGISTERED -writemodeA NORMAL -writemodeB NORMAL -resetmode SYNC -cascade -1 -e
+
+-- Mon Sep 14 12:54:09 2009
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity ped_thr_true is
+ port (
+ DataInA: in std_logic_vector(17 downto 0);
+ DataInB: in std_logic_vector(17 downto 0);
+ AddressA: in std_logic_vector(6 downto 0);
+ AddressB: in std_logic_vector(6 downto 0);
+ ClockA: in std_logic;
+ ClockB: in std_logic;
+ ClockEnA: in std_logic;
+ ClockEnB: in std_logic;
+ WrA: in std_logic;
+ WrB: in std_logic;
+ ResetA: in std_logic;
+ ResetB: in std_logic;
+ QA: out std_logic_vector(17 downto 0);
+ QB: out std_logic_vector(17 downto 0));
+end ped_thr_true;
+
+architecture Structure of ped_thr_true is
+
+ -- internal signal declarations
+ signal scuba_vlo: std_logic;
+ signal scuba_vhi: std_logic;
+
+ -- local component declarations
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component DP16KB
+ -- synopsys translate_off
+ generic (GSR : in String; WRITEMODE_B : in String;
+ CSDECODE_B : in std_logic_vector(2 downto 0);
+ CSDECODE_A : in std_logic_vector(2 downto 0);
+ WRITEMODE_A : in String; RESETMODE : in String;
+ REGMODE_B : in String; REGMODE_A : in String;
+ DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer);
+ -- synopsys translate_on
+ port (DIA0: in std_logic; DIA1: in std_logic;
+ DIA2: in std_logic; DIA3: in std_logic;
+ DIA4: in std_logic; DIA5: in std_logic;
+ DIA6: in std_logic; DIA7: in std_logic;
+ DIA8: in std_logic; DIA9: in std_logic;
+ DIA10: in std_logic; DIA11: in std_logic;
+ DIA12: in std_logic; DIA13: in std_logic;
+ DIA14: in std_logic; DIA15: in std_logic;
+ DIA16: in std_logic; DIA17: in std_logic;
+ ADA0: in std_logic; ADA1: in std_logic;
+ ADA2: in std_logic; ADA3: in std_logic;
+ ADA4: in std_logic; ADA5: in std_logic;
+ ADA6: in std_logic; ADA7: in std_logic;
+ ADA8: in std_logic; ADA9: in std_logic;
+ ADA10: in std_logic; ADA11: in std_logic;
+ ADA12: in std_logic; ADA13: in std_logic;
+ CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic;
+ CSA0: in std_logic; CSA1: in std_logic;
+ CSA2: in std_logic; RSTA: in std_logic;
+ DIB0: in std_logic; DIB1: in std_logic;
+ DIB2: in std_logic; DIB3: in std_logic;
+ DIB4: in std_logic; DIB5: in std_logic;
+ DIB6: in std_logic; DIB7: in std_logic;
+ DIB8: in std_logic; DIB9: in std_logic;
+ DIB10: in std_logic; DIB11: in std_logic;
+ DIB12: in std_logic; DIB13: in std_logic;
+ DIB14: in std_logic; DIB15: in std_logic;
+ DIB16: in std_logic; DIB17: in std_logic;
+ ADB0: in std_logic; ADB1: in std_logic;
+ ADB2: in std_logic; ADB3: in std_logic;
+ ADB4: in std_logic; ADB5: in std_logic;
+ ADB6: in std_logic; ADB7: in std_logic;
+ ADB8: in std_logic; ADB9: in std_logic;
+ ADB10: in std_logic; ADB11: in std_logic;
+ ADB12: in std_logic; ADB13: in std_logic;
+ CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic;
+ CSB0: in std_logic; CSB1: in std_logic;
+ CSB2: in std_logic; RSTB: in std_logic;
+ DOA0: out std_logic; DOA1: out std_logic;
+ DOA2: out std_logic; DOA3: out std_logic;
+ DOA4: out std_logic; DOA5: out std_logic;
+ DOA6: out std_logic; DOA7: out std_logic;
+ DOA8: out std_logic; DOA9: out std_logic;
+ DOA10: out std_logic; DOA11: out std_logic;
+ DOA12: out std_logic; DOA13: out std_logic;
+ DOA14: out std_logic; DOA15: out std_logic;
+ DOA16: out std_logic; DOA17: out std_logic;
+ DOB0: out std_logic; DOB1: out std_logic;
+ DOB2: out std_logic; DOB3: out std_logic;
+ DOB4: out std_logic; DOB5: out std_logic;
+ DOB6: out std_logic; DOB7: out std_logic;
+ DOB8: out std_logic; DOB9: out std_logic;
+ DOB10: out std_logic; DOB11: out std_logic;
+ DOB12: out std_logic; DOB13: out std_logic;
+ DOB14: out std_logic; DOB15: out std_logic;
+ DOB16: out std_logic; DOB17: out std_logic);
+ end component;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute CSDECODE_B : string;
+ attribute CSDECODE_A : string;
+ attribute WRITEMODE_B : string;
+ attribute WRITEMODE_A : string;
+ attribute GSR : string;
+ attribute RESETMODE : string;
+ attribute REGMODE_B : string;
+ attribute REGMODE_A : string;
+ attribute DATA_WIDTH_B : string;
+ attribute DATA_WIDTH_A : string;
+ attribute MEM_LPC_FILE of ped_thr_true_0_0_0 : label is "ped_thr_true.lpc";
+ attribute MEM_INIT_FILE of ped_thr_true_0_0_0 : label is "";
+ attribute CSDECODE_B of ped_thr_true_0_0_0 : label is "0b000";
+ attribute CSDECODE_A of ped_thr_true_0_0_0 : label is "0b000";
+ attribute WRITEMODE_B of ped_thr_true_0_0_0 : label is "NORMAL";
+ attribute WRITEMODE_A of ped_thr_true_0_0_0 : label is "NORMAL";
+ attribute GSR of ped_thr_true_0_0_0 : label is "DISABLED";
+ attribute RESETMODE of ped_thr_true_0_0_0 : label is "SYNC";
+ attribute REGMODE_B of ped_thr_true_0_0_0 : label is "OUTREG";
+ attribute REGMODE_A of ped_thr_true_0_0_0 : label is "OUTREG";
+ attribute DATA_WIDTH_B of ped_thr_true_0_0_0 : label is "18";
+ attribute DATA_WIDTH_A of ped_thr_true_0_0_0 : label is "18";
+
+begin
+ -- component instantiation statements
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ ped_thr_true_0_0_0: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 18,
+ DATA_WIDTH_A=> 18)
+ -- synopsys translate_on
+ port map (DIA0=>DataInA(0), DIA1=>DataInA(1), DIA2=>DataInA(2),
+ DIA3=>DataInA(3), DIA4=>DataInA(4), DIA5=>DataInA(5),
+ DIA6=>DataInA(6), DIA7=>DataInA(7), DIA8=>DataInA(8),
+ DIA9=>DataInA(9), DIA10=>DataInA(10), DIA11=>DataInA(11),
+ DIA12=>DataInA(12), DIA13=>DataInA(13), DIA14=>DataInA(14),
+ DIA15=>DataInA(15), DIA16=>DataInA(16), DIA17=>DataInA(17),
+ ADA0=>scuba_vhi, ADA1=>scuba_vhi, ADA2=>scuba_vlo,
+ ADA3=>scuba_vlo, ADA4=>AddressA(0), ADA5=>AddressA(1),
+ ADA6=>AddressA(2), ADA7=>AddressA(3), ADA8=>AddressA(4),
+ ADA9=>AddressA(5), ADA10=>AddressA(6), ADA11=>scuba_vlo,
+ ADA12=>scuba_vlo, ADA13=>scuba_vlo, CEA=>ClockEnA,
+ CLKA=>ClockA, WEA=>WrA, CSA0=>scuba_vlo, CSA1=>scuba_vlo,
+ CSA2=>scuba_vlo, RSTA=>ResetA, DIB0=>DataInB(0),
+ DIB1=>DataInB(1), DIB2=>DataInB(2), DIB3=>DataInB(3),
+ DIB4=>DataInB(4), DIB5=>DataInB(5), DIB6=>DataInB(6),
+ DIB7=>DataInB(7), DIB8=>DataInB(8), DIB9=>DataInB(9),
+ DIB10=>DataInB(10), DIB11=>DataInB(11), DIB12=>DataInB(12),
+ DIB13=>DataInB(13), DIB14=>DataInB(14), DIB15=>DataInB(15),
+ DIB16=>DataInB(16), DIB17=>DataInB(17), ADB0=>scuba_vhi,
+ ADB1=>scuba_vhi, ADB2=>scuba_vlo, ADB3=>scuba_vlo,
+ ADB4=>AddressB(0), ADB5=>AddressB(1), ADB6=>AddressB(2),
+ ADB7=>AddressB(3), ADB8=>AddressB(4), ADB9=>AddressB(5),
+ ADB10=>AddressB(6), ADB11=>scuba_vlo, ADB12=>scuba_vlo,
+ ADB13=>scuba_vlo, CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB,
+ CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
+ RSTB=>ResetB, DOA0=>QA(0), DOA1=>QA(1), DOA2=>QA(2),
+ DOA3=>QA(3), DOA4=>QA(4), DOA5=>QA(5), DOA6=>QA(6),
+ DOA7=>QA(7), DOA8=>QA(8), DOA9=>QA(9), DOA10=>QA(10),
+ DOA11=>QA(11), DOA12=>QA(12), DOA13=>QA(13), DOA14=>QA(14),
+ DOA15=>QA(15), DOA16=>QA(16), DOA17=>QA(17), DOB0=>QB(0),
+ DOB1=>QB(1), DOB2=>QB(2), DOB3=>QB(3), DOB4=>QB(4),
+ DOB5=>QB(5), DOB6=>QB(6), DOB7=>QB(7), DOB8=>QB(8),
+ DOB9=>QB(9), DOB10=>QB(10), DOB11=>QB(11), DOB12=>QB(12),
+ DOB13=>QB(13), DOB14=>QB(14), DOB15=>QB(15), DOB16=>QB(16),
+ DOB17=>QB(17));
+
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of ped_thr_true is
+ for Structure
+ for all:VHI use entity ecp2m.VHI(V); end for;
+ for all:VLO use entity ecp2m.VLO(V); end for;
+ for all:DP16KB use entity ecp2m.DP16KB(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23)
+-- Module Version: 7.1
+-- Mon Sep 14 12:54:09 2009
+
+-- parameterized module component declaration
+component ped_thr_true
+ port (DataInA: in std_logic_vector(17 downto 0);
+ DataInB: in std_logic_vector(17 downto 0);
+ AddressA: in std_logic_vector(6 downto 0);
+ AddressB: in std_logic_vector(6 downto 0);
+ ClockA: in std_logic; ClockB: in std_logic;
+ ClockEnA: in std_logic; ClockEnB: in std_logic;
+ WrA: in std_logic; WrB: in std_logic; ResetA: in std_logic;
+ ResetB: in std_logic; QA: out std_logic_vector(17 downto 0);
+ QB: out std_logic_vector(17 downto 0));
+end component;
+
+-- parameterized module component instance
+__ : ped_thr_true
+ port map (DataInA(17 downto 0)=>__, DataInB(17 downto 0)=>__,
+ AddressA(6 downto 0)=>__, AddressB(6 downto 0)=>__, ClockA=>__,
+ ClockB=>__, ClockEnA=>__, ClockEnB=>__, WrA=>__, WrB=>__, ResetA=>__,
+ ResetB=>__, QA(17 downto 0)=>__, QB(17 downto 0)=>__);
--- /dev/null
+[Device]\r
+Family=latticeecp2m\r
+PartType=LFE2M100E\r
+PartName=LFE2M100E-6F900C\r
+SpeedGrade=-6\r
+Package=FPBGA900\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=PLL\r
+CoreRevision=4.2\r
+ModuleName=pll_40m\r
+SourceFormat=VHDL\r
+ParameterFileVersion=1.0\r
+Date=01/30/2009\r
+Time=10:01:30\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=None\r
+Order=None\r
+IO=0\r
+Type=ehxpllb\r
+mode=normal\r
+IFrq=100\r
+OFrq=40.000000\r
+KFrq=100.000000\r
+U_OFrq=40\r
+U_KFrq=50\r
+OP_Tol=0.0\r
+OK_Tol=0.0\r
+Div=5\r
+Mult=2\r
+Post=32\r
+SecD=2\r
+fb_mode=CLKOP\r
+PhaseDuty=Dynamic\r
+DelayControl=GPLL_NO_DELAY\r
+External=DISABLED\r
+PCDR=1\r
+ClkOPBp=0\r
+EnCLKOS=1\r
+ClkOSBp=0\r
+Phase=0.0\r
+Duty=8\r
+DPD=50% Duty\r
+EnCLKOK=0\r
+ClkOKBp=0\r
+ClkRst=0\r
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v72_PROD_Build (44)
+-- Module Version: 4.2
+--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n pll_40m -lang vhdl -synth synplify -arch ep5m00 -type pll -fin 100 -phase_cntl DYNAMIC -fclkop 40 -fclkop_tol 0.0 -delay_cntl GPLL_NO_DELAY -fb_mode CLOCKTREE -extcap DISABLED -phaseadj 0.0 -duty 8 -duty50 -noclkok -use_rst -e
+
+-- Fri Jan 30 10:01:31 2009
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity pll_40m is
+ port (
+ CLK: in std_logic;
+ RESET: in std_logic;
+ DPAMODE: in std_logic;
+ DPHASE0: in std_logic;
+ DPHASE1: in std_logic;
+ DPHASE2: in std_logic;
+ DPHASE3: in std_logic;
+ CLKOP: out std_logic;
+ CLKOS: out std_logic;
+ LOCK: out std_logic);
+ attribute dont_touch : string;
+ attribute dont_touch of pll_40m : entity is "true";
+end pll_40m;
+
+architecture Structure of pll_40m is
+
+ -- internal signal declarations
+ signal DPHASE3_inv: std_logic;
+ signal CLKOP_t: std_logic;
+ signal scuba_vlo: std_logic;
+ signal CLK_t: std_logic;
+
+ -- local component declarations
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component EPLLD
+ -- synopsys translate_off
+ generic (PLLCAP : in String; CLKOK_BYPASS : in String;
+ CLKOS_BYPASS : in String; CLKOP_BYPASS : in String;
+ DUTY : in Integer; PHASEADJ : in String;
+ PHASE_CNTL : in String; CLKOK_DIV : in Integer;
+ CLKFB_DIV : in Integer; CLKOP_DIV : in Integer;
+ CLKI_DIV : in Integer);
+ -- synopsys translate_on
+ port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic;
+ RSTK: in std_logic; DPAMODE: in std_logic; DRPAI3: in std_logic;
+ DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic;
+ DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic;
+ DFPAI0: in std_logic; CLKOP: out std_logic; CLKOS: out std_logic;
+ CLKOK: out std_logic; LOCK: out std_logic; CLKINTFB: out std_logic);
+ end component;
+ attribute PLLCAP : string;
+ attribute PLLTYPE : string;
+ attribute CLKOK_BYPASS : string;
+ attribute FREQUENCY_PIN_CLKOK : string;
+ attribute CLKOK_DIV : string;
+ attribute CLKOS_BYPASS : string;
+ attribute FREQUENCY_PIN_CLKOS : string;
+ attribute FREQUENCY_PIN_CLKOP : string;
+ attribute CLKOP_BYPASS : string;
+ attribute PHASE_CNTL : string;
+ attribute FDEL : string;
+ attribute DUTY : string;
+ attribute PHASEADJ : string;
+ attribute FREQUENCY_PIN_CLKI : string;
+ attribute CLKOP_DIV : string;
+ attribute CLKFB_DIV : string;
+ attribute CLKI_DIV : string;
+ attribute FIN : string;
+ attribute PLLCAP of PLLDInst_0 : label is "DISABLED";
+ attribute PLLTYPE of PLLDInst_0 : label is "GPLL";
+ attribute CLKOK_BYPASS of PLLDInst_0 : label is "DISABLED";
+ attribute FREQUENCY_PIN_CLKOK of PLLDInst_0 : label is "50.000000";
+ attribute CLKOK_DIV of PLLDInst_0 : label is "2";
+ attribute CLKOS_BYPASS of PLLDInst_0 : label is "DISABLED";
+ attribute FREQUENCY_PIN_CLKOS of PLLDInst_0 : label is "40.000000";
+ attribute FREQUENCY_PIN_CLKOP of PLLDInst_0 : label is "40.000000";
+ attribute CLKOP_BYPASS of PLLDInst_0 : label is "DISABLED";
+ attribute PHASE_CNTL of PLLDInst_0 : label is "DYNAMIC";
+ attribute FDEL of PLLDInst_0 : label is "0";
+ attribute DUTY of PLLDInst_0 : label is "8";
+ attribute PHASEADJ of PLLDInst_0 : label is "0.0";
+ attribute FREQUENCY_PIN_CLKI of PLLDInst_0 : label is "100.000000";
+ attribute CLKOP_DIV of PLLDInst_0 : label is "32";
+ attribute CLKFB_DIV of PLLDInst_0 : label is "2";
+ attribute CLKI_DIV of PLLDInst_0 : label is "5";
+ attribute FIN of PLLDInst_0 : label is "100.000000";
+ attribute syn_keep : boolean;
+ attribute syn_noprune : boolean;
+ attribute syn_noprune of Structure : architecture is true;
+
+begin
+ -- component instantiation statements
+ INV_0: INV
+ port map (A=>DPHASE3, Z=>DPHASE3_inv);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ PLLDInst_0: EPLLD
+ -- synopsys translate_off
+ generic map (PLLCAP=> "DISABLED", CLKOK_BYPASS=> "DISABLED",
+ CLKOK_DIV=> 2, CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED",
+ PHASE_CNTL=> "DYNAMIC", DUTY=> 8, PHASEADJ=> "0.0", CLKOP_DIV=> 32,
+ CLKFB_DIV=> 2, CLKI_DIV=> 5)
+ -- synopsys translate_on
+ port map (CLKI=>CLK_t, CLKFB=>CLKOP_t, RST=>RESET,
+ RSTK=>scuba_vlo, DPAMODE=>DPAMODE, DRPAI3=>DPHASE3,
+ DRPAI2=>DPHASE2, DRPAI1=>DPHASE1, DRPAI0=>DPHASE0,
+ DFPAI3=>DPHASE3_inv, DFPAI2=>DPHASE2, DFPAI1=>DPHASE1,
+ DFPAI0=>DPHASE0, CLKOP=>CLKOP_t, CLKOS=>CLKOS, CLKOK=>open,
+ LOCK=>LOCK, CLKINTFB=>open);
+
+ CLKOP <= CLKOP_t;
+ CLK_t <= CLK;
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of pll_40m is
+ for Structure
+ for all:INV use entity ecp2m.INV(V); end for;
+ for all:VLO use entity ecp2m.VLO(V); end for;
+ for all:EPLLD use entity ecp2m.EPLLD(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_PROD_Build (44)
+-- Module Version: 4.2
+-- Fri Jan 30 10:01:31 2009
+
+-- parameterized module component declaration
+component pll_40m
+ port (CLK: in std_logic; RESET: in std_logic; DPAMODE: in std_logic;
+ DPHASE0: in std_logic; DPHASE1: in std_logic; DPHASE2: in std_logic;
+ DPHASE3: in std_logic; CLKOP: out std_logic; CLKOS: out std_logic;
+ LOCK: out std_logic);
+end component;
+
+-- parameterized module component instance
+__ : pll_40m
+ port map (CLK=>__, RESET=>__, DPAMODE=>__, DPHASE0=>__, DPHASE1=>__,
+ DPHASE2=>__, DPHASE3=>__, CLKOP=>__, CLKOS=>__, LOCK=>__);
--- /dev/null
+library ieee; \r
+use ieee.std_logic_1164.all; \r
+use ieee.std_logic_arith.all; \r
+use ieee.std_logic_unsigned.all;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+entity pulse_stretch is\r
+ port( CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ START_IN : in std_logic;\r
+ PULSE_OUT : out std_logic;\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
+end;\r
+\r
+architecture behavioral of pulse_stretch is\r
+\r
+ -- normal signals\r
+ signal pulse_cnt : std_logic_vector(3 downto 0);\r
+ signal pulse_cnt_ce : std_logic;\r
+ signal pulse_x : std_logic;\r
+ signal pulse : std_logic;\r
+ \r
+begin \r
+\r
+-- Pulse length counter\r
+THE_PULSE_LENGTH_CTR: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( reset_in = '1' ) then\r
+ pulse_cnt <= (others => '0');\r
+ elsif( pulse_cnt_ce = '1' ) then\r
+ pulse_cnt <= pulse_cnt + 1;\r
+ end if;\r
+ end if;\r
+end process THE_PULSE_LENGTH_CTR;\r
+\r
+pulse_cnt_ce <= '1' when ( (start_in = '1') or (pulse_cnt /= x"0") ) else '0';\r
+\r
+pulse_x <= '1' when ( (pulse_cnt(2) = '1') or (pulse_cnt(3) = '1') ) else '0';\r
+\r
+-- Syanchronize it\r
+THE_SYNC_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ pulse <= '0';\r
+ else\r
+ pulse <= pulse_x;\r
+ end if;\r
+ end if; \r
+end process THE_SYNC_PROC;\r
+\r
+\r
+-- output signals\r
+pulse_out <= pulse;\r
+debug_out(15 downto 4) <= (others => '0'); \r
+debug_out(3 downto 0) <= pulse_cnt;\r
+\r
+end behavioral; \r
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.std_logic_arith.all;\r
+use ieee.std_logic_unsigned.all;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+entity pulse_sync is\r
+ port( CLK_A_IN : in std_logic;\r
+ RESET_A_IN : in std_logic;\r
+ PULSE_A_IN : in std_logic;\r
+ CLK_B_IN : in std_logic;\r
+ RESET_B_IN : in std_logic;\r
+ PULSE_B_OUT : out std_logic\r
+ );\r
+end;\r
+\r
+architecture behavioral of pulse_sync is\r
+\r
+ -- normal signals\r
+ signal toggle_ff : std_logic;\r
+ signal sync_q : std_logic;\r
+ signal sync_qq : std_logic;\r
+ signal sync_qqq : std_logic;\r
+ signal pulse_b : std_logic;\r
+ \r
+begin\r
+\r
+-- toggle flip flop in clock domain A\r
+THE_TOGGLE_FF_PROC: process( clk_a_in )\r
+begin\r
+ if( rising_edge(clk_a_in) ) then\r
+ if ( reset_a_in = '1' ) then\r
+ toggle_ff <= '0';\r
+ elsif( pulse_a_in = '1' ) then\r
+ toggle_ff <= not toggle_ff;\r
+ end if;\r
+ end if;\r
+end process THE_TOGGLE_FF_PROC;\r
+\r
+-- synchronizing stage for clock domain B\r
+THE_SYNC_STAGE_PROC: process( clk_b_in )\r
+begin\r
+ if( rising_edge(clk_b_in) ) then\r
+ if( reset_b_in = '1' ) then\r
+ sync_q <= '0'; sync_qq <= '0'; sync_qqq <= '0';\r
+ else\r
+ sync_qqq <= sync_qq;\r
+ sync_qq <= sync_q;\r
+ sync_q <= toggle_ff;\r
+ end if;\r
+ end if;\r
+end process THE_SYNC_STAGE_PROC;\r
+\r
+-- output pulse registering\r
+THE_OUTPUT_PULSE_PROC: process( clk_b_in )\r
+begin\r
+ if( rising_edge(clk_b_in) ) then\r
+ if( reset_b_in = '1' ) then\r
+ pulse_b <= '0';\r
+ else\r
+ pulse_b <= sync_qqq xor sync_qq;\r
+ end if;\r
+ end if;\r
+end process THE_OUTPUT_PULSE_PROC;\r
+\r
+-- output signals\r
+pulse_b_out <= pulse_b;\r
+\r
+end behavioral;\r
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.std_logic_arith.all;\r
+use ieee.std_logic_unsigned.all;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+entity raw_buf_stage_new is\r
+ port( CLK_IN : in std_logic; -- 100MHz local clock\r
+ CLK_APV_IN : in std_logic; -- 40MHz APV clock\r
+ RESET_IN : in std_logic; -- general reset (100MHz)\r
+ -- trigger related signals\r
+ APV_RESET_IN : in std_logic; -- APV reset signal (100MHz)\r
+ APV_SYNC_IN : in std_logic; -- APV sync trigger has been sent (40MHz)\r
+ APV_FRAME_REQD_IN : in std_logic; -- one APV frame has been requested (100MHz)\r
+ -- ADC0 signals\r
+ ADC0_VALID_IN : in std_logic; -- 40M reconstructed clock is valid\r
+ ADC0_0_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 0\r
+ ADC0_1_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 1\r
+ ADC0_2_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 2\r
+ ADC0_3_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 3\r
+ ADC0_4_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 4\r
+ ADC0_5_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 5\r
+ ADC0_6_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 6\r
+ ADC0_7_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 7\r
+ -- ADC1 signals\r
+ ADC1_VALID_IN : in std_logic; -- 40M reconstructed clock is valid\r
+ ADC1_0_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 0\r
+ ADC1_1_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 1\r
+ ADC1_2_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 2\r
+ ADC1_3_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 3\r
+ ADC1_4_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 4\r
+ ADC1_5_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 5\r
+ ADC1_6_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 6\r
+ ADC1_7_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 7\r
+ -- Slow control registers\r
+ MAX_TRG_NUM_IN : in std_logic_vector(3 downto 0); -- maximum number of triggers / event\r
+ BIT_LOW_IN : in std_logic_vector(11 downto 0); -- "bit low" threshold\r
+ BIT_HIGH_IN : in std_logic_vector(11 downto 0); -- "bit high" threshold\r
+ FL_LOW_IN : in std_logic_vector(11 downto 0); -- "flatline low" threshold\r
+ FL_HIGH_IN : in std_logic_vector(11 downto 0); -- "flatline high" threshold\r
+ APV_ON_IN : in std_logic_vector(15 downto 0); -- APV on/off bits from slow control\r
+ -- 100MHZ synchronous interface\r
+ BUF_FULL_OUT : out std_logic;\r
+ BUF_ADDR_IN : in std_logic_vector(6 downto 0);\r
+ BUF_DONE_IN : in std_logic;\r
+ BUF_TICK_OUT : out std_logic_vector(15 downto 0);\r
+ BUF_START_OUT : out std_logic_vector(15 downto 0);\r
+ BUF_READY_OUT : out std_logic_vector(15 downto 0);\r
+ BUF_0_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_1_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_2_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_3_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_4_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_5_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_6_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_7_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_8_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_9_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_10_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_11_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_12_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_13_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_14_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ BUF_15_DATA_OUT : out std_logic_vector(37 downto 0);\r
+ -- Debug signals\r
+ DEBUG_OUT : out std_logic_vector(63 downto 0)\r
+ );\r
+end;\r
+\r
+architecture behavioral of raw_buf_stage_new is\r
+\r
+ -- Reset signals, combinatorial and registered\r
+ signal next_reset_all : std_logic; \r
+ signal reset_all : std_logic; -- 40MHz clock domain\r
+ signal next_reset : std_logic; \r
+ signal reset : std_logic; -- 100MHz clock domain \r
+\r
+ -- APV locker signals (arrays / vectors)\r
+ type adc_data_t is array (0 to 15) of std_logic_vector(11 downto 0);\r
+ signal adc_data : adc_data_t;\r
+ type apv_status_t is array (0 to 15) of std_logic_vector(7 downto 0);\r
+ signal apv_status : apv_status_t;\r
+ type apv_frame_t is array (0 to 15) of std_logic_vector(11 downto 0);\r
+ signal apv_frame : apv_frame_t;\r
+ type apv_channel_t is array (0 to 15) of std_logic_vector(6 downto 0); \r
+ signal apv_channel : apv_channel_t;\r
+ type apv_data_t is array (0 to 15) of std_logic_vector(17 downto 0);\r
+ signal apv_data : apv_data_t;\r
+\r
+ signal apv_analog : std_logic_vector(15 downto 0);\r
+ signal apv_start : std_logic_vector(15 downto 0);\r
+ signal apv_last : std_logic_vector(15 downto 0);\r
+\r
+ -- Buffer signals (arrays / vectors)\r
+ type buf_data_t is array (0 to 15) of std_logic_vector(17 downto 0);\r
+ signal buf_data : buf_data_t;\r
+ type buf_status_t is array (0 to 15) of std_logic_vector(7 downto 0);\r
+ signal buf_status : buf_status_t;\r
+ type buf_frame_t is array (0 to 15) of std_logic_vector(11 downto 0);\r
+ signal buf_frame : buf_frame_t;\r
+ type buf_level_t is array (0 to 15) of std_logic_vector(7 downto 0);\r
+ signal buf_level : buf_level_t; \r
+\r
+ signal buf_tick : std_logic_vector(15 downto 0);\r
+ signal buf_start : std_logic_vector(15 downto 0);\r
+ signal buf_ready : std_logic_vector(15 downto 0);\r
+ signal buf_full : std_logic_vector(15 downto 0); \r
+\r
+ signal next_raw_buf_full : std_logic;\r
+ signal raw_buf_full : std_logic;\r
+\r
+ -- Debug\r
+ signal debug : std_logic_vector(63 downto 0);\r
+ \r
+begin\r
+\r
+---------------------------------------------------------------------------\r
+-- Debugging signals\r
+---------------------------------------------------------------------------\r
+--debug(31 downto 0) <= (others => '0');\r
+debug(63 downto 60) <= apv_data(15)(17 downto 14);\r
+debug(59 downto 56) <= apv_data(14)(17 downto 14);\r
+debug(55 downto 52) <= apv_data(13)(17 downto 14);\r
+debug(51 downto 48) <= apv_data(12)(17 downto 14);\r
+debug(47 downto 44) <= apv_data(11)(17 downto 14);\r
+debug(43 downto 40) <= apv_data(10)(17 downto 14);\r
+debug(39 downto 36) <= apv_data(9)(17 downto 14);\r
+debug(35 downto 32) <= apv_data(8)(17 downto 14);\r
+debug(31 downto 28) <= apv_data(7)(17 downto 14);\r
+debug(27 downto 24) <= apv_data(6)(17 downto 14);\r
+debug(23 downto 20) <= apv_data(5)(17 downto 14);\r
+debug(19 downto 16) <= apv_data(4)(17 downto 14);\r
+debug(15 downto 12) <= apv_data(3)(17 downto 14);\r
+debug(11 downto 8) <= apv_data(2)(17 downto 14);\r
+debug(7 downto 4) <= apv_data(1)(17 downto 14);\r
+debug(3 downto 0) <= apv_data(0)(17 downto 14);\r
+\r
+---------------------------------------------------------------------------\r
+-- Reset handling\r
+---------------------------------------------------------------------------\r
+next_reset_all <= (reset_in or apv_reset_in); -- 40MHz clock domain \r
+next_reset <= (reset_in or apv_reset_in); -- 100MHz clock domain\r
+\r
+THE_RESET_SYNC: state_sync\r
+port map( STATE_A_IN => next_reset_all,\r
+ CLK_B_IN => clk_apv_in,\r
+ RESET_B_IN => '0',\r
+ STATE_B_OUT => reset_all\r
+ );\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- Busy and reset handling\r
+---------------------------------------------------------------------------\r
+next_raw_buf_full <= '1' when ( buf_full /= x"0000" ) else '0';\r
+\r
+THE_SYNC_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ raw_buf_full <= next_raw_buf_full;\r
+ reset <= next_reset_all;\r
+ end if;\r
+end process THE_SYNC_PROC;\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- ADC0: APV [7:0] lock handler, data separation, raw data buffer\r
+---------------------------------------------------------------------------\r
+\r
+-- Aliasing the inputs for the generator\r
+adc_data(7) <= adc0_7_data_in;\r
+adc_data(6) <= adc0_6_data_in;\r
+adc_data(5) <= adc0_5_data_in;\r
+adc_data(4) <= adc0_4_data_in;\r
+adc_data(3) <= adc0_3_data_in;\r
+adc_data(2) <= adc0_2_data_in;\r
+adc_data(1) <= adc0_1_data_in;\r
+adc_data(0) <= adc0_0_data_in;\r
+\r
+-- generate 8 identical blocks, one per APV connected to ADC0\r
+GEN_ADC0: for i in 0 to 7 generate\r
+\r
+ -- APV locker, handles synchronisation and all the other stuff\r
+ THE_APV_LOCKER: apv_locker\r
+ port map( CLK_APV_IN => clk_apv_in,\r
+ RESET_IN => reset_all,\r
+ SYNC_IN => apv_sync_in,\r
+ ADC_RAW_IN => adc_data(i),\r
+ ADC_VALID_IN => adc0_valid_in,\r
+ APV_ON_IN => apv_on_in(i),\r
+ BIT_LOW_IN => bit_low_in,\r
+ BIT_HIGH_IN => bit_high_in,\r
+ FL_LOW_IN => fl_low_in,\r
+ FL_HIGH_IN => fl_high_in,\r
+ STATUS_IGNORE_OUT => apv_status(i)(1),\r
+ STATUS_UNKNOWN_OUT => apv_status(i)(6),\r
+ STATUS_BADADC_OUT => apv_status(i)(7),\r
+ STATUS_LOCKED_OUT => apv_status(i)(5),\r
+ STATUS_LOST_OUT => apv_status(i)(4),\r
+ STATUS_NOSYNC_OUT => apv_status(i)(3),\r
+ STATUS_MISSING_OUT => apv_status(i)(2),\r
+ STATUS_TICKMARK_OUT => apv_status(i)(0),\r
+ FRAME_ROW_OUT => apv_frame(i)(7 downto 0),\r
+ FRAME_ERROR_OUT => apv_frame(i)(8), \r
+ FRAME_OVF_OUT => apv_frame(i)(9),\r
+ FRAME_UDF_OUT => apv_frame(i)(10),\r
+ FRAME_FLAT_OUT => apv_frame(i)(11),\r
+ FRAME_CTR_OUT => apv_data(i)(17 downto 14),\r
+ APV_CHANNEL_OUT => apv_channel(i),\r
+ APV_OVERFLOW_OUT => apv_data(i)(13),\r
+ APV_UNDERFLOW_OUT => apv_data(i)(12),\r
+ APV_RAW_OUT => apv_data(i)(11 downto 0),\r
+ APV_ANALOG_OUT => apv_analog(i),\r
+ APV_START_OUT => apv_start(i),\r
+ APV_LAST_OUT => apv_last(i),\r
+ DEBUG_OUT => open\r
+ ); \r
+ \r
+ -- raw buffer, stores frame data, all outputs are 100MHz synchronized\r
+ THE_APV_RAW_BUFFER: apv_raw_buffer\r
+ port map( CLK_APV_IN => clk_apv_in,\r
+ RESET_IN => reset_all,\r
+ FRM_REQD_IN => apv_frame_reqd_in,\r
+ MAX_TRG_NUM_IN => max_trg_num_in,\r
+ ADC_ANALOG_IN => apv_analog(i),\r
+ ADC_START_IN => apv_start(i),\r
+ ADC_LAST_IN => apv_last(i),\r
+ ADC_CHANNEL_IN => apv_channel(i),\r
+ ADC_RAW_IN => apv_data(i),\r
+ ADC_STATUS_IN => apv_status(i),\r
+ ADC_FRAME_IN => apv_frame(i),\r
+ BUF_CLK_IN => clk_in,\r
+ BUF_RESET_IN => reset,\r
+ BUF_START_OUT => buf_start(i),\r
+ BUF_READY_OUT => buf_ready(i),\r
+ BUF_ADDR_IN => buf_addr_in,\r
+ BUF_DONE_IN => buf_done_in, \r
+ BUF_DATA_OUT => buf_data(i),\r
+ BUF_STATUS_OUT => buf_status(i),\r
+ BUF_FRAME_OUT => buf_frame(i),\r
+ BUF_GOOD_OUT => buf_level(i)(7),\r
+ BUF_BROKEN_OUT => buf_level(i)(6),\r
+ BUF_IGNORE_OUT => buf_level(i)(5),\r
+ BUF_LEVEL_OUT => buf_level(i)(4 downto 0),\r
+ BUF_TICKMARK_OUT => buf_tick(i),\r
+ BUF_FULL_OUT => buf_full(i),\r
+ DEBUG_OUT => open\r
+ );\r
+\r
+end generate GEN_ADC0;\r
+\r
+---------------------------------------------------------------------------\r
+-- ADC1: APV [15:8] lock handler, data separation, raw data buffer\r
+---------------------------------------------------------------------------\r
+\r
+-- Aliasing the inputs for the generator\r
+adc_data(15) <= adc1_7_data_in;\r
+adc_data(14) <= adc1_6_data_in;\r
+adc_data(13) <= adc1_5_data_in;\r
+adc_data(12) <= adc1_4_data_in;\r
+adc_data(11) <= adc1_3_data_in;\r
+adc_data(10) <= adc1_2_data_in;\r
+adc_data(9) <= adc1_1_data_in;\r
+adc_data(8) <= adc1_0_data_in;\r
+\r
+-- generate 8 identical blocks, one per APV connected to ADC1\r
+GEN_ADC1: for i in 8 to 15 generate\r
+\r
+ -- APV locker, handles synchronisation and all the other stuff\r
+ THE_APV_LOCKER: apv_locker\r
+ port map( CLK_APV_IN => clk_apv_in,\r
+ RESET_IN => reset_all,\r
+ SYNC_IN => apv_sync_in,\r
+ ADC_RAW_IN => adc_data(i),\r
+ ADC_VALID_IN => adc1_valid_in,\r
+ APV_ON_IN => apv_on_in(i),\r
+ BIT_LOW_IN => bit_low_in,\r
+ BIT_HIGH_IN => bit_high_in,\r
+ FL_LOW_IN => fl_low_in,\r
+ FL_HIGH_IN => fl_high_in,\r
+ STATUS_IGNORE_OUT => apv_status(i)(1),\r
+ STATUS_UNKNOWN_OUT => apv_status(i)(6),\r
+ STATUS_BADADC_OUT => apv_status(i)(7),\r
+ STATUS_LOCKED_OUT => apv_status(i)(5),\r
+ STATUS_LOST_OUT => apv_status(i)(4),\r
+ STATUS_NOSYNC_OUT => apv_status(i)(3),\r
+ STATUS_MISSING_OUT => apv_status(i)(2),\r
+ STATUS_TICKMARK_OUT => apv_status(i)(0),\r
+ FRAME_ROW_OUT => apv_frame(i)(7 downto 0),\r
+ FRAME_ERROR_OUT => apv_frame(i)(8), \r
+ FRAME_OVF_OUT => apv_frame(i)(9),\r
+ FRAME_UDF_OUT => apv_frame(i)(10),\r
+ FRAME_FLAT_OUT => apv_frame(i)(11),\r
+ FRAME_CTR_OUT => apv_data(i)(17 downto 14),\r
+ APV_CHANNEL_OUT => apv_channel(i),\r
+ APV_OVERFLOW_OUT => apv_data(i)(13),\r
+ APV_UNDERFLOW_OUT => apv_data(i)(12),\r
+ APV_RAW_OUT => apv_data(i)(11 downto 0),\r
+ APV_ANALOG_OUT => apv_analog(i),\r
+ APV_START_OUT => apv_start(i),\r
+ APV_LAST_OUT => apv_last(i),\r
+ DEBUG_OUT => open\r
+ ); \r
+ \r
+ -- raw buffer, stores frame data, all outputs are 100MHz synchronized\r
+ THE_APV_RAW_BUFFER: apv_raw_buffer\r
+ port map( CLK_APV_IN => clk_apv_in,\r
+ RESET_IN => reset_all,\r
+ FRM_REQD_IN => apv_frame_reqd_in,\r
+ MAX_TRG_NUM_IN => max_trg_num_in,\r
+ ADC_ANALOG_IN => apv_analog(i),\r
+ ADC_START_IN => apv_start(i),\r
+ ADC_LAST_IN => apv_last(i),\r
+ ADC_CHANNEL_IN => apv_channel(i),\r
+ ADC_RAW_IN => apv_data(i),\r
+ ADC_STATUS_IN => apv_status(i),\r
+ ADC_FRAME_IN => apv_frame(i),\r
+ BUF_CLK_IN => clk_in,\r
+ BUF_RESET_IN => reset,\r
+ BUF_START_OUT => buf_start(i),\r
+ BUF_READY_OUT => buf_ready(i),\r
+ BUF_ADDR_IN => buf_addr_in,\r
+ BUF_DONE_IN => buf_done_in, \r
+ BUF_DATA_OUT => buf_data(i),\r
+ BUF_STATUS_OUT => buf_status(i),\r
+ BUF_FRAME_OUT => buf_frame(i),\r
+ BUF_GOOD_OUT => buf_level(i)(7),\r
+ BUF_BROKEN_OUT => buf_level(i)(6),\r
+ BUF_IGNORE_OUT => buf_level(i)(5),\r
+ BUF_LEVEL_OUT => buf_level(i)(4 downto 0),\r
+ BUF_TICKMARK_OUT => buf_tick(i),\r
+ BUF_FULL_OUT => buf_full(i),\r
+ DEBUG_OUT => open\r
+ );\r
+\r
+end generate GEN_ADC1;\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- Output signals\r
+---------------------------------------------------------------------------\r
+\r
+buf_full_out <= raw_buf_full;\r
+buf_tick_out <= buf_tick; -- needed for TOCs\r
+buf_start_out <= buf_start; -- needed for TOCs\r
+buf_ready_out <= buf_ready; -- debug signal\r
+\r
+-- Alias the outputs from generator\r
+buf_0_data_out(17 downto 0) <= buf_data(0);\r
+buf_0_data_out(29 downto 18) <= buf_frame(0);\r
+buf_0_data_out(37 downto 30) <= buf_level(0);\r
+buf_1_data_out(17 downto 0) <= buf_data(1);\r
+buf_1_data_out(29 downto 18) <= buf_frame(1);\r
+buf_1_data_out(37 downto 30) <= buf_level(1);\r
+buf_2_data_out(17 downto 0) <= buf_data(2);\r
+buf_2_data_out(29 downto 18) <= buf_frame(2);\r
+buf_2_data_out(37 downto 30) <= buf_level(2);\r
+buf_3_data_out(17 downto 0) <= buf_data(3);\r
+buf_3_data_out(29 downto 18) <= buf_frame(3);\r
+buf_3_data_out(37 downto 30) <= buf_level(3);\r
+buf_4_data_out(17 downto 0) <= buf_data(4);\r
+buf_4_data_out(29 downto 18) <= buf_frame(4);\r
+buf_4_data_out(37 downto 30) <= buf_level(4);\r
+buf_5_data_out(17 downto 0) <= buf_data(5);\r
+buf_5_data_out(29 downto 18) <= buf_frame(5);\r
+buf_5_data_out(37 downto 30) <= buf_level(5);\r
+buf_6_data_out(17 downto 0) <= buf_data(6);\r
+buf_6_data_out(29 downto 18) <= buf_frame(6);\r
+buf_6_data_out(37 downto 30) <= buf_level(6);\r
+buf_7_data_out(17 downto 0) <= buf_data(7);\r
+buf_7_data_out(29 downto 18) <= buf_frame(7);\r
+buf_7_data_out(37 downto 30) <= buf_level(7);\r
+buf_8_data_out(17 downto 0) <= buf_data(8);\r
+buf_8_data_out(29 downto 18) <= buf_frame(8);\r
+buf_8_data_out(37 downto 30) <= buf_level(8);\r
+buf_9_data_out(17 downto 0) <= buf_data(9);\r
+buf_9_data_out(29 downto 18) <= buf_frame(9);\r
+buf_9_data_out(37 downto 30) <= buf_level(9);\r
+buf_10_data_out(17 downto 0) <= buf_data(10);\r
+buf_10_data_out(29 downto 18) <= buf_frame(10);\r
+buf_10_data_out(37 downto 30) <= buf_level(10);\r
+buf_11_data_out(17 downto 0) <= buf_data(11);\r
+buf_11_data_out(29 downto 18) <= buf_frame(11);\r
+buf_11_data_out(37 downto 30) <= buf_level(11);\r
+buf_12_data_out(17 downto 0) <= buf_data(12);\r
+buf_12_data_out(29 downto 18) <= buf_frame(12);\r
+buf_12_data_out(37 downto 30) <= buf_level(12);\r
+buf_13_data_out(17 downto 0) <= buf_data(13);\r
+buf_13_data_out(29 downto 18) <= buf_frame(13);\r
+buf_13_data_out(37 downto 30) <= buf_level(13);\r
+buf_14_data_out(17 downto 0) <= buf_data(14);\r
+buf_14_data_out(29 downto 18) <= buf_frame(14);\r
+buf_14_data_out(37 downto 30) <= buf_level(14);\r
+buf_15_data_out(17 downto 0) <= buf_data(15);\r
+buf_15_data_out(29 downto 18) <= buf_frame(15);\r
+buf_15_data_out(37 downto 30) <= buf_level(15);\r
+\r
+---------------------------------------------------------------------------\r
+-- DEBUG signals\r
+---------------------------------------------------------------------------\r
+debug_out <= debug;\r
+\r
+end behavioral;\r
+\r
+\r
+ \r
+\r
+\r
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.std_logic_arith.all;\r
+use ieee.std_logic_unsigned.all;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+-- Comment: better than the first version, but still a lot of optimization possible.\r
+\r
+-- (1) no more compare tags here. some steps in the FSM can be taken out.\r
+-- (2) no more rst_lvl1_counter signal anymore in the CCR. to be replaced!\r
+\r
+entity real_trg_handler is\r
+ port( CLK_IN : in std_logic; -- 100MHz master clock\r
+ RESET_IN : in std_logic; \r
+ TIME_TRG_IN : in std_logic_vector(3 downto 0); -- timing trigger inputs\r
+ TRB_TRG_IN : in std_logic_vector(3 downto 0); -- TRB trigger inputs\r
+ APV_TRGDONE_IN : in std_logic; -- APV trigger statemachine finished (one pulse)\r
+ TRG_3_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 3\r
+ TRG_2_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 2\r
+ TRG_1_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 1\r
+ TRG_0_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 0\r
+ TRG_SETUP_IN : in std_logic_vector(7 downto 0); -- setup of external triggers\r
+ TRG_FOUND_OUT : out std_logic; -- single pulse for endpoint\r
+ -- TRB LVL1 channel signals\r
+ TRB_TTAG_IN : in std_logic_vector(15 downto 0); -- LVL1 16bit trigger tag \r
+ TRB_TRND_IN : in std_logic_vector(7 downto 0); -- LVL1 8bit random number \r
+ TRB_TTYPE_IN : in std_logic_vector(3 downto 0); -- LVL1 trigger type\r
+ TRB_TRGRCVD_IN : in std_logic; -- LVL1 trigger has been received on TRB\r
+ TRB_MISSING_OUT : out std_logic; -- LVL1 trigger without timing trigger\r
+ RST_LVL1_COUNTER_IN : in std_logic; -- reset LVL1 counter\r
+ LVL1_COUNTER_OUT : out std_logic_vector(15 downto 0);\r
+ BUSY_RELEASE_IN : in std_logic; -- common signal from busy calculator\r
+ -- \r
+ APV_TRGSEL_OUT : out std_logic_vector(3 downto 0); -- select one APV trigger state machine\r
+ APV_TRGSTART_OUT : out std_logic; -- start an APV trigger state machine\r
+ EDS_DATA_OUT : out std_logic_vector(39 downto 0); -- EDS data\r
+ EDS_WE_OUT : out std_logic; -- EDS write enable (general interface)\r
+ EDS_START_OUT : out std_logic; -- separate increment signal for EDS buffer level\r
+ EDS_READY_OUT : out std_logic; -- APV trigger sequence done\r
+ DBG_FRMCTR_OUT : out std_logic_vector(3 downto 0); -- framecounter itself\r
+ BSM_OUT : out std_logic_vector(7 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(63 downto 0)\r
+ );\r
+end;\r
+\r
+architecture behavioral of real_trg_handler is\r
+\r
+ -- state machine signals\r
+ type STATES is (SLEEP, STORE, START, COUNT, RELAX, CHECK, WAPV, WLVL1, TRBS, COMP, CTAG, STAG,\r
+ DTAG, WEDS, WDEL0, WDEL1, WBUSY, DONE, CNTEVT, BADTRG);\r
+ signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+ -- normal signals\r
+ signal trg_comb : std_logic_vector(3 downto 0); -- TRB or hardware inputs\r
+ signal trg_q : std_logic_vector(3 downto 0);\r
+ signal trg_qq : std_logic_vector(3 downto 0);\r
+ signal trg_qqq : std_logic_vector(3 downto 0);\r
+ signal trg_qqqq : std_logic_vector(3 downto 0);\r
+ signal trg_edge : std_logic_vector(3 downto 0); \r
+ signal decoded_trg : std_logic_vector(3 downto 0);\r
+ signal todo_start : std_logic_vector(3 downto 0);\r
+ signal trg_found : std_logic;\r
+ signal trg_pattern : std_logic_vector(3 downto 0);\r
+\r
+ signal evtctr : std_logic_vector(15 downto 0); -- event counter\r
+ signal ce_evtctr : std_logic;\r
+ signal ce_evtctr_x : std_logic;\r
+ signal frmctr : std_logic_vector(3 downto 0); -- frame counter\r
+ signal ce_frmctr : std_logic;\r
+ signal ce_frmctr_x : std_logic;\r
+ signal todo_ctr : std_logic_vector(3 downto 0);\r
+ signal todo_done_x : std_logic;\r
+ signal todo_done : std_logic;\r
+ signal apv_trgstart_x : std_logic;\r
+ signal apv_trgstart : std_logic;\r
+ signal eds_data : std_logic_vector(39 downto 0);\r
+ signal eds_start : std_logic;\r
+ signal eds_start_x : std_logic;\r
+ signal eds_we : std_logic;\r
+ signal eds_we_x : std_logic;\r
+ signal eds_ready_x : std_logic; \r
+ signal eds_ready : std_logic; -- end signal, release busy by sending TERM and clean up misc stuff\r
+ signal apv_trg_finished : std_logic;\r
+ signal accept_x : std_logic; -- we can accept a trigger\r
+ signal accept : std_logic; \r
+ signal missed_trg_x : std_logic;\r
+ signal missed_trg : std_logic;\r
+ signal missing_trg : std_logic;\r
+ signal rst_status_x : std_logic;\r
+ signal rst_status : std_logic;\r
+\r
+ signal time_trg : std_logic_vector(3 downto 0);\r
+\r
+ -- Information to be collected for the EDS\r
+ signal trb_ttag_reg : std_logic_vector(15 downto 0); -- TRB LVL1 trigger tag (16bit)\r
+ signal trb_trnd_reg : std_logic_vector(7 downto 0); -- TRB LVL1 random byte (8bit)\r
+ signal trb_ttype_reg : std_logic_vector(3 downto 0); -- TRB LVL1 trigger type (4bit) \r
+ signal trg_pattern_reg : std_logic_vector(3 downto 0); -- timing trigger input pattern (4bit)\r
+ signal trg_dectrg_reg : std_logic_vector(3 downto 0); -- priority encoded timing trigger (4bit)\r
+ signal trg_frmctr_reg : std_logic_vector(3 downto 0); -- frame counter start value (4bit)\r
+ signal trg_frmnum_reg : std_logic_vector(3 downto 0); -- number of frames in this event (4bit)\r
+\r
+ signal store_local_x : std_logic;\r
+ signal store_local : std_logic;\r
+ signal store_remote_x : std_logic;\r
+ signal store_remote : std_logic;\r
+\r
+ signal time_trg_on : std_logic_vector(3 downto 0);\r
+ signal time_trg_inv : std_logic_vector(3 downto 0);\r
+ \r
+ signal bsm_x : std_logic_vector(7 downto 0);\r
+\r
+begin\r
+\r
+-- Aliasing the control bits\r
+time_trg_on(3) <= trg_setup_in(7);\r
+time_trg_inv(3) <= trg_setup_in(3);\r
+time_trg_on(2) <= trg_setup_in(6);\r
+time_trg_inv(2) <= trg_setup_in(2);\r
+time_trg_on(1) <= trg_setup_in(5);\r
+time_trg_inv(1) <= trg_setup_in(1);\r
+time_trg_on(0) <= trg_setup_in(4);\r
+time_trg_inv(0) <= trg_setup_in(0);\r
+\r
+------------------------------------------------------------\r
+-- Synchronize the external trigger inputs\r
+THE_TIME_TRG_3_SYNC: state_sync\r
+port map( STATE_A_IN => time_trg_in(3),\r
+ CLK_B_IN => clk_in,\r
+ RESET_B_IN => reset_in,\r
+ STATE_B_OUT => time_trg(3)\r
+ );\r
+THE_TIME_TRG_2_SYNC: state_sync\r
+port map( STATE_A_IN => time_trg_in(2),\r
+ CLK_B_IN => clk_in,\r
+ RESET_B_IN => reset_in,\r
+ STATE_B_OUT => time_trg(2)\r
+ );\r
+THE_TIME_TRG_1_SYNC: state_sync\r
+port map( STATE_A_IN => time_trg_in(1),\r
+ CLK_B_IN => clk_in,\r
+ RESET_B_IN => reset_in,\r
+ STATE_B_OUT => time_trg(1)\r
+ );\r
+THE_TIME_TRG_0_SYNC: state_sync\r
+port map( STATE_A_IN => time_trg_in(0),\r
+ CLK_B_IN => clk_in,\r
+ RESET_B_IN => reset_in,\r
+ STATE_B_OUT => time_trg(0)\r
+ );\r
+------------------------------------------------------------\r
+\r
+-- For all four possible hardware triggers we combine hardware and TRB inputs\r
+-- TRB slow control trigger inputs are already synchronized to SYSCLK.\r
+--trg_comb <= time_trg or trb_trg_in;\r
+\r
+trg_comb(3) <= ((time_trg(3) xor time_trg_inv(3)) and time_trg_on(3)) or trb_trg_in(3);\r
+trg_comb(2) <= ((time_trg(2) xor time_trg_inv(2)) and time_trg_on(2)) or trb_trg_in(2);\r
+trg_comb(1) <= ((time_trg(1) xor time_trg_inv(1)) and time_trg_on(1)) or trb_trg_in(1);\r
+trg_comb(0) <= ((time_trg(0) xor time_trg_inv(0)) and time_trg_on(0)) or trb_trg_in(0);\r
+\r
+-- Now we shift the synced signals into shift registers with four FF in a row.\r
+-- This gives us a 16bit pattern in total to decide which trigger input was active.\r
+THE_TRG_LENGTH_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ trg_qqqq <= (others => '0');\r
+ trg_qqq <= (others => '0');\r
+ trg_qq <= (others => '0');\r
+ trg_q <= (others => '0');\r
+ else\r
+ trg_qqqq <= trg_qqq;\r
+ trg_qqq <= trg_qq;\r
+ trg_qq <= trg_q;\r
+ trg_q <= trg_comb;\r
+ end if;\r
+ end if;\r
+end process THE_TRG_LENGTH_PROC;\r
+\r
+-- Check for rising edges in the signals, with a long steady state signal following.\r
+-- We accept only signals of three clock cycles minimum length (as sent by the TRB_TRG).\r
+THE_RISING_EDGES_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ trg_edge <= (others => '0');\r
+ else\r
+ trg_edge(3) <= not trg_qqqq(3) and trg_qqq(3) and trg_qq(3) and trg_q(3);\r
+ trg_edge(2) <= not trg_qqqq(2) and trg_qqq(2) and trg_qq(2) and trg_q(2);\r
+ trg_edge(1) <= not trg_qqqq(1) and trg_qqq(1) and trg_qq(1) and trg_q(1);\r
+ trg_edge(0) <= not trg_qqqq(0) and trg_qqq(0) and trg_qq(0) and trg_q(0);\r
+ end if;\r
+ end if;\r
+end process THE_RISING_EDGES_PROC;\r
+\r
+-- Now we are almost done. \r
+-- The detected edges are priorized.\r
+THE_TRG_PRIORITY_PROC: process( clk_in ) \r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ decoded_trg <= (others => '0');\r
+ todo_start <= (others => '0');\r
+ trg_found <= '0';\r
+ else\r
+ if( trg_edge(3) = '1' ) then\r
+ decoded_trg <= "1000";\r
+ todo_start <= trg_3_todo_in;\r
+ trg_found <= '1';\r
+ elsif( trg_edge(3 downto 2) = "01" ) then\r
+ decoded_trg <= "0100";\r
+ todo_start <= trg_2_todo_in;\r
+ trg_found <= '1';\r
+ elsif( trg_edge(3 downto 1) = "001" ) then\r
+ decoded_trg <= "0010";\r
+ todo_start <= trg_1_todo_in;\r
+ trg_found <= '1';\r
+ elsif( trg_edge(3 downto 0) = "0001" ) then\r
+ decoded_trg <= "0001";\r
+ todo_start <= trg_0_todo_in;\r
+ trg_found <= '1';\r
+ else\r
+ decoded_trg <= "0000";\r
+ todo_start <= "0000";\r
+ trg_found <= '0';\r
+ end if;\r
+ end if;\r
+ end if;\r
+end process THE_TRG_PRIORITY_PROC;\r
+\r
+-- We need to store some information for the EDS... from local counters\r
+-- NB: after one cycle this information set is reset to zero!\r
+-- needed for missing timing trigger handling.\r
+THE_LOCALSTORE_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( (reset_in = '1') or (eds_we = '1') ) then\r
+ trg_pattern_reg <= (others => '0');\r
+ trg_frmctr_reg <= (others => '0');\r
+ trg_frmnum_reg <= (others => '0');\r
+ trg_dectrg_reg <= (others => '0');\r
+ elsif( (accept = '1') and (trg_found = '1') ) then -- the clock cycle before local_store pulse\r
+ trg_pattern_reg <= trg_pattern; -- BUGBUGBUG\r
+ trg_frmctr_reg <= frmctr;\r
+ trg_frmnum_reg <= todo_start;\r
+ trg_dectrg_reg <= decoded_trg;\r
+ end if;\r
+ end if;\r
+end process THE_LOCALSTORE_PROC;\r
+\r
+-- The ToDo counter: is loaded with the number of APV triggers, and counts down.\r
+THE_TODO_COUNTER_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( reset_in = '1' ) then\r
+ todo_ctr <= (others => '0');\r
+ elsif( store_local = '1' ) then\r
+ todo_ctr <= trg_frmnum_reg; --todo_start;\r
+ elsif( ce_frmctr = '1' ) then\r
+ todo_ctr <= todo_ctr - 1;\r
+ end if;\r
+ end if;\r
+end process THE_TODO_COUNTER_PROC;\r
+todo_done_x <= '1' when (todo_ctr = x"0") else '0';\r
+\r
+-- We need to store some information for the EDS... from TRBnet LVL1 trigger endpoint\r
+THE_REMOTESTORE_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ trb_ttag_reg <= (others => '0');\r
+ trb_trnd_reg <= (others => '0');\r
+ trb_ttype_reg <= (others => '0'); \r
+ elsif( store_remote = '1' ) then\r
+ trb_ttag_reg <= trb_ttag_in;\r
+ trb_trnd_reg <= trb_trnd_in;\r
+ trb_ttype_reg <= trb_ttype_in;\r
+ end if;\r
+ end if;\r
+end process THE_REMOTESTORE_PROC;\r
+\r
+-------------------------------------------------\r
+-------------------------------------------------\r
+-------------------------------------------------\r
+\r
+THE_TRG_SYNC_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ trg_pattern <= (others => '0');\r
+ todo_done <= '0';\r
+ else\r
+ trg_pattern <= trg_edge;\r
+ todo_done <= todo_done_x;\r
+ end if;\r
+ end if;\r
+end process THE_TRG_SYNC_PROC;\r
+\r
+-- We store the end pulse from the APV trigger handler, as we need to wait for\r
+-- LVL1 in any case before we can take care of this signal.\r
+THE_TRGDONE_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ apv_trg_finished <= '0';\r
+ elsif( apv_trgdone_in = '1' ) then\r
+ apv_trg_finished <= '1';\r
+ elsif( eds_ready = '1' ) then\r
+ apv_trg_finished <= '0';\r
+ end if;\r
+ end if;\r
+end process THE_TRGDONE_PROC;\r
+\r
+-- A statemachine handles all actions for filling out the trigger information sheet\r
+-- state registers\r
+STATE_MEM: process( clk_in ) \r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ CURRENT_STATE <= SLEEP;\r
+ ce_evtctr <= '0';\r
+ ce_frmctr <= '0';\r
+ eds_ready <= '0';\r
+ eds_we <= '0';\r
+ eds_start <= '0';\r
+ store_local <= '0';\r
+ store_remote <= '0';\r
+ apv_trgstart <= '0';\r
+ accept <= '1';\r
+ missed_trg <= '0';\r
+ rst_status <= '0';\r
+ else\r
+ CURRENT_STATE <= NEXT_STATE;\r
+ ce_evtctr <= ce_evtctr_x;\r
+ ce_frmctr <= ce_frmctr_x;\r
+ eds_ready <= eds_ready_x;\r
+ eds_we <= eds_we_x;\r
+ eds_start <= eds_start_x;\r
+ store_local <= store_local_x;\r
+ store_remote <= store_remote_x;\r
+ apv_trgstart <= apv_trgstart_x;\r
+ accept <= accept_x;\r
+ missed_trg <= missed_trg_x;\r
+ rst_status <= rst_status_x;\r
+ end if;\r
+ end if;\r
+end process STATE_MEM;\r
+\r
+-- state transitions\r
+STATE_TRANSFORM: process( CURRENT_STATE, trg_found, todo_done, trb_trgrcvd_in, apv_trg_finished, busy_release_in, missing_trg )\r
+begin\r
+ NEXT_STATE <= SLEEP; -- avoid latches\r
+ ce_evtctr_x <= '0'; \r
+ ce_frmctr_x <= '0';\r
+ eds_ready_x <= '0';\r
+ eds_we_x <= '0';\r
+ eds_start_x <= '0';\r
+ store_local_x <= '0';\r
+ store_remote_x <= '0';\r
+ apv_trgstart_x <= '0';\r
+ accept_x <= '0';\r
+ missed_trg_x <= '0';\r
+ rst_status_x <= '0';\r
+ case CURRENT_STATE is\r
+ -- not good. if no timing trigger was received but a trb trigger arrives, we must do something!\r
+ when SLEEP => if ( trg_found = '1' ) then\r
+ -- normal way: timing trigger found\r
+ NEXT_STATE <= STORE;\r
+ store_local_x <= '1';\r
+ eds_start_x <= '1';\r
+ elsif( (trg_found = '0') and (trb_trgrcvd_in = '1') ) then\r
+ -- bad way: missing timing trigger\r
+ NEXT_STATE <= BADTRG;\r
+ missed_trg_x <= '1';\r
+ else\r
+ NEXT_STATE <= SLEEP;\r
+ accept_x <= '1';\r
+ end if;\r
+ when BADTRG => NEXT_STATE <= TRBS;\r
+ store_remote_x <= '1';\r
+ when STORE => NEXT_STATE <= START;\r
+ apv_trgstart_x <= '1';\r
+ when START => NEXT_STATE <= CHECK;\r
+ when CHECK => if( todo_done = '1' ) then\r
+ NEXT_STATE <= WAPV;\r
+ else\r
+ NEXT_STATE <= COUNT;\r
+ ce_frmctr_x <= '1';\r
+ end if;\r
+ when COUNT => NEXT_STATE <= RELAX;\r
+ when RELAX => NEXT_STATE <= CHECK;\r
+ when WAPV => if( apv_trg_finished = '1' ) then\r
+ NEXT_STATE <= WLVL1;\r
+ else\r
+ NEXT_STATE <= WAPV;\r
+ end if;\r
+ when WLVL1 => if( trb_trgrcvd_in = '1' ) then\r
+ NEXT_STATE <= TRBS;\r
+ store_remote_x <= '1';\r
+ else\r
+ NEXT_STATE <= WLVL1;\r
+ end if;\r
+ when TRBS => NEXT_STATE <= CTAG;\r
+ when CTAG => NEXT_STATE <= STAG;\r
+ when STAG => NEXT_STATE <= DTAG;\r
+ when DTAG => if( missing_trg = '0' ) then\r
+ -- everything is fine\r
+ NEXT_STATE <= WEDS;\r
+ eds_we_x <= '1';\r
+ else\r
+ -- we missed a timing trigger, so no EDS was created\r
+ NEXT_STATE <= CNTEVT;\r
+ ce_evtctr_x <= '1';\r
+ end if;\r
+ when WEDS => NEXT_STATE <= CNTEVT;\r
+ ce_evtctr_x <= '1';\r
+ when CNTEVT => NEXT_STATE <= WDEL0;\r
+ when WDEL0 => NEXT_STATE <= WDEL1;\r
+ when WDEL1 => NEXT_STATE <= WBUSY;\r
+ when WBUSY => if( busy_release_in = '1' ) then\r
+ NEXT_STATE <= DONE;\r
+ eds_ready_x <= '1';\r
+ else\r
+ NEXT_STATE <= WBUSY;\r
+ end if;\r
+ when DONE => if( trb_trgrcvd_in = '0' ) then -- mind the state synchronizer delay!!!\r
+ NEXT_STATE <= SLEEP;\r
+ accept_x <= '1';\r
+ rst_status_x <= '1';\r
+ else\r
+ NEXT_STATE <= DONE;\r
+ end if;\r
+ when others => NEXT_STATE <= SLEEP;\r
+ accept_x <= '1';\r
+ end case;\r
+end process STATE_TRANSFORM;\r
+\r
+-- state decoding\r
+STATE_DECODE: process( CURRENT_STATE )\r
+begin\r
+ case CURRENT_STATE is\r
+ when SLEEP => bsm_x <= x"00";\r
+ when STORE => bsm_x <= x"01"; \r
+ when START => bsm_x <= x"02";\r
+ when CHECK => bsm_x <= x"03";\r
+ when COUNT => bsm_x <= x"04";\r
+ when RELAX => bsm_x <= x"14";\r
+ when WAPV => bsm_x <= x"05";\r
+ when WLVL1 => bsm_x <= x"06";\r
+ when TRBS => bsm_x <= x"07";\r
+ when CTAG => bsm_x <= x"08";\r
+ when STAG => bsm_x <= x"09";\r
+ when DTAG => bsm_x <= x"0a";\r
+ when WEDS => bsm_x <= x"0b";\r
+ when WDEL0 => bsm_x <= x"0c";\r
+ when WDEL1 => bsm_x <= x"0d";\r
+ when WBUSY => bsm_x <= x"0e";\r
+ when DONE => bsm_x <= x"0f";\r
+ when CNTEVT => bsm_x <= x"10";\r
+ when BADTRG => bsm_x <= x"11";\r
+ when others => bsm_x <= x"ff";\r
+ end case;\r
+end process STATE_DECODE;\r
+\r
+\r
+-- The event counter: is incremented with each accepted trigger\r
+THE_EVENT_COUNTER_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( (reset_in = '1') or (rst_lvl1_counter_in = '1') ) then\r
+ evtctr <= (others => '0');\r
+ elsif( ce_evtctr = '1' ) then\r
+ evtctr <= evtctr + 1;\r
+ end if;\r
+ end if;\r
+end process THE_EVENT_COUNTER_PROC;\r
+\r
+-- The frame counter: is incremented with each 1-0-0 trigger sent to APV\r
+THE_FRAME_COUNTER_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ frmctr <= (others => '0');\r
+ elsif( ce_frmctr = '1' ) then\r
+ frmctr <= frmctr + 1;\r
+ end if;\r
+ end if;\r
+end process THE_FRAME_COUNTER_PROC;\r
+\r
+-- If a timing trigger was missing, we simply ignore this LVL1 trigger\r
+THE_MISSED_TRG_REG: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( (reset_in = '1') or (rst_status = '1') ) then\r
+ missing_trg <= '0';\r
+ elsif( missed_trg = '1' ) then\r
+ missing_trg <= '1';\r
+ end if;\r
+ end if;\r
+end process THE_MISSED_TRG_REG;\r
+\r
+-- EDS bits:\r
+eds_data(39 downto 36) <= trg_frmctr_reg;\r
+eds_data(35 downto 32) <= trg_frmnum_reg;\r
+eds_data(31 downto 16) <= trb_ttag_reg;\r
+eds_data(15 downto 8) <= trb_trnd_reg;\r
+eds_data(7 downto 4) <= trb_ttype_reg;\r
+eds_data(3 downto 0) <= trg_pattern_reg;\r
+\r
+-- output signals\r
+apv_trgstart_out <= apv_trgstart;\r
+apv_trgsel_out <= trg_dectrg_reg;\r
+\r
+eds_data_out <= eds_data;\r
+eds_start_out <= eds_start;\r
+eds_we_out <= eds_we;\r
+eds_ready_out <= eds_ready;\r
+trb_missing_out <= missing_trg;\r
+lvl1_counter_out <= evtctr;\r
+trg_found_out <= trg_found;\r
+\r
+-- Debug signals\r
+bsm_out <= bsm_x;\r
+\r
+debug_out(63 downto 32) <= (others => '0');\r
+debug_out(31 downto 24) <= evtctr(7 downto 0);\r
+debug_out(23 downto 16) <= trb_ttag_reg(7 downto 0);\r
+debug_out(15) <= ce_evtctr;\r
+debug_out(14) <= '0';\r
+debug_out(13) <= missing_trg;\r
+debug_out(12) <= accept;\r
+debug_out(11) <= '0';\r
+debug_out(10) <= '0';\r
+debug_out(9) <= trb_trgrcvd_in;\r
+debug_out(8) <= trg_found;\r
+debug_out(7 downto 0) <= bsm_x;\r
+\r
+dbg_frmctr_out <= frmctr;\r
+\r
+end behavioral;\r
+\r
--- /dev/null
+library ieee; \r
+use ieee.std_logic_1164.all; \r
+use ieee.std_logic_arith.all; \r
+use ieee.std_logic_unsigned.all;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+entity reboot_handler is\r
+ port( RESET_IN : in std_logic;\r
+ CLK_IN : in std_logic;\r
+ START_IN : in std_logic;\r
+ REBOOT_OUT : out std_logic;\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
+end;\r
+\r
+architecture behavioral of reboot_handler is\r
+\r
+ -- normal signals \r
+ signal reboot_counter : std_logic_vector(15 downto 0);\r
+ signal reboot_ce : std_logic;\r
+ signal reboot_x : std_logic;\r
+ signal reboot : std_logic;\r
+ \r
+begin \r
+\r
+-- Latch the start pulse\r
+THE_START_PULSE: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( reset_in = '1' ) then\r
+ reboot_ce <= '0';\r
+ elsif( start_in = '1' ) then\r
+ reboot_ce <= '1';\r
+ end if;\r
+ end if;\r
+end process THE_START_PULSE;\r
+\r
+-- Reboot counter\r
+THE_REBOOT_COUNTER: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( reset_in = '1' ) then\r
+ reboot_counter <= (others => '0');\r
+ reboot <= '0';\r
+ elsif( reboot_ce = '1' ) then\r
+ reboot_counter <= reboot_counter + 1;\r
+ end if;\r
+ reboot <= reboot_x;\r
+ end if;\r
+end process THE_REBOOT_COUNTER;\r
+\r
+reboot_x <= reboot_counter(15) and reboot_counter(14) and reboot_counter(13);\r
+\r
+-- output signals\r
+reboot_out <= reboot;\r
+\r
+debug_out(15 downto 0) <= reboot_counter; \r
+\r
+end behavioral; \r
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.std_logic_arith.all;\r
+use ieee.std_logic_unsigned.all;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+-- This module takes ROW and ERROR information from all sixteen raw buffers, and \r
+-- checks if the APVs with "good data" buffers are OK.\r
+-- APV frame errors are sensed, as well as APV row errors.\r
+-- The row error recognition is based somehow on the old RICH RC logic, as it takes\r
+-- one APV as reference row by prioritiy encoding, and checks all other APVs against\r
+-- this reference row.\r
+\r
+entity ref_row_sel is\r
+ port( CLK_IN : in std_logic;\r
+ READY_IN : in std_logic_vector(15 downto 0); -- buffer ready signals (data or timeout)\r
+ GOODDATA_IN : in std_logic_vector(15 downto 0); -- buffer data good signals\r
+ FRAME_0_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_1_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_2_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_3_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_4_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_5_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_6_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_7_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_8_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_9_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_10_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_11_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_12_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_13_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_14_IN : in std_logic_vector(11 downto 0);\r
+ FRAME_15_IN : in std_logic_vector(11 downto 0);\r
+ READY_OUT : out std_logic; -- all buffers reported being ready for data transport\r
+ VALID_BUFS_OUT : out std_logic; -- at least one APV raw buffer has data to fetch \r
+ ROW_ERROR_OUT : out std_logic; -- at least one row number is wrong\r
+ APV_ERROR_OUT : out std_logic; -- at least one APV sent ERROR bit\r
+ APV_ERROR_BITS_OUT : out std_logic_vector(15 downto 0);\r
+ REF_ROW_OUT : out std_logic_vector(7 downto 0); -- selected reference row\r
+ DBG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
+end;\r
+\r
+architecture behavioral of ref_row_sel is\r
+\r
+ -- normal signals\r
+ signal debug_x : std_logic_vector(15 downto 0);\r
+ \r
+ signal next_sel_ref_row : std_logic_vector(3 downto 0);\r
+ signal sel_ref_row : std_logic_vector(3 downto 0);\r
+ signal next_valid_bufs : std_logic;\r
+ signal valid_bufs : std_logic;\r
+ signal next_all_ready : std_logic;\r
+ signal all_ready : std_logic;\r
+ \r
+ signal ref_row : std_logic_vector(7 downto 0); -- selected reference row number\r
+ \r
+ signal next_row_match : std_logic_vector(15 downto 0);\r
+ signal row_match : std_logic_vector(15 downto 0); -- APV frame row matches reference number\r
+ \r
+ signal next_apv_error : std_logic_vector(15 downto 0);\r
+ signal apv_error : std_logic_vector(15 downto 0); -- APV frame error is set\r
+ \r
+ signal next_frame_row_err : std_logic;\r
+ signal frame_row_err : std_logic;\r
+ signal next_frame_apv_err : std_logic;\r
+ signal frame_apv_err : std_logic;\r
+\r
+ \r
+begin\r
+\r
+-- Sync process\r
+THE_SYNC_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ sel_ref_row <= next_sel_ref_row;\r
+ valid_bufs <= next_valid_bufs;\r
+ apv_error <= next_apv_error;\r
+ row_match <= next_row_match;\r
+ frame_row_err <= next_frame_row_err;\r
+ frame_apv_err <= next_frame_apv_err;\r
+ all_ready <= next_all_ready;\r
+ end if;\r
+end process THE_SYNC_PROC;\r
+\r
+-- All channels ready?\r
+next_all_ready <= '1' when ( ready_in = x"ffff" ) else '0';\r
+\r
+-- If no gooddata channel is available then we have no reference row\r
+next_valid_bufs <= '1' when ( gooddata_in /= x"0000" ) else '0';\r
+\r
+-- Do a priority encoding to select the reference row\r
+THE_PRI_ENCODER_PROC: process( gooddata_in )\r
+begin\r
+ if ( gooddata_in(15 downto 15) = "1" ) then\r
+ next_sel_ref_row <= "1111";\r
+ elsif( gooddata_in(15 downto 14) = "01" ) then\r
+ next_sel_ref_row <= "1110";\r
+ elsif( gooddata_in(15 downto 13) = "001" ) then\r
+ next_sel_ref_row <= "1101";\r
+ elsif( gooddata_in(15 downto 12) = "0001" ) then\r
+ next_sel_ref_row <= "1100";\r
+ elsif( gooddata_in(15 downto 11) = "00001" ) then\r
+ next_sel_ref_row <= "1011";\r
+ elsif( gooddata_in(15 downto 10) = "000001" ) then\r
+ next_sel_ref_row <= "1010";\r
+ elsif( gooddata_in(15 downto 9) = "0000001" ) then\r
+ next_sel_ref_row <= "1001";\r
+ elsif( gooddata_in(15 downto 8) = "00000001" ) then\r
+ next_sel_ref_row <= "1000";\r
+ elsif( gooddata_in(15 downto 7) = "000000001" ) then\r
+ next_sel_ref_row <= "0111";\r
+ elsif( gooddata_in(15 downto 6) = "0000000001" ) then\r
+ next_sel_ref_row <= "0110";\r
+ elsif( gooddata_in(15 downto 5) = "00000000001" ) then\r
+ next_sel_ref_row <= "0101";\r
+ elsif( gooddata_in(15 downto 4) = "000000000001" ) then\r
+ next_sel_ref_row <= "0100";\r
+ elsif( gooddata_in(15 downto 3) = "0000000000001" ) then\r
+ next_sel_ref_row <= "0011";\r
+ elsif( gooddata_in(15 downto 2) = "00000000000001" ) then\r
+ next_sel_ref_row <= "0010";\r
+ elsif( gooddata_in(15 downto 1) = "000000000000001" ) then\r
+ next_sel_ref_row <= "0001";\r
+ elsif( gooddata_in(15 downto 0) = "0000000000000001" ) then\r
+ next_sel_ref_row <= "0000";\r
+ else\r
+ next_sel_ref_row <= "0000";\r
+ end if;\r
+end process THE_PRI_ENCODER_PROC;\r
+\r
+-- Select one reference row, and store it\r
+THE_REF_ROW_SELECT_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ case sel_ref_row is\r
+ when "0000" => ref_row <= frame_0_in(7 downto 0);\r
+ when "0001" => ref_row <= frame_1_in(7 downto 0);\r
+ when "0010" => ref_row <= frame_2_in(7 downto 0);\r
+ when "0011" => ref_row <= frame_3_in(7 downto 0);\r
+ when "0100" => ref_row <= frame_4_in(7 downto 0);\r
+ when "0101" => ref_row <= frame_5_in(7 downto 0);\r
+ when "0110" => ref_row <= frame_6_in(7 downto 0);\r
+ when "0111" => ref_row <= frame_7_in(7 downto 0);\r
+ when "1000" => ref_row <= frame_8_in(7 downto 0);\r
+ when "1001" => ref_row <= frame_9_in(7 downto 0);\r
+ when "1010" => ref_row <= frame_10_in(7 downto 0);\r
+ when "1011" => ref_row <= frame_11_in(7 downto 0);\r
+ when "1100" => ref_row <= frame_12_in(7 downto 0);\r
+ when "1101" => ref_row <= frame_13_in(7 downto 0);\r
+ when "1110" => ref_row <= frame_14_in(7 downto 0);\r
+ when "1111" => ref_row <= frame_15_in(7 downto 0);\r
+ when others => ref_row <= x"ee"; -- will not be used... all cases are covered.\r
+ end case;\r
+ end if;\r
+end process THE_REF_ROW_SELECT_PROC;\r
+\r
+-- Check all rows against the reference\r
+-- Only channels with GOODDATA are to be taken into account; if the channel is invalid, we ignore it.\r
+\r
+next_row_match(0) <= '1' when ( (gooddata_in(0) = '0') or\r
+ ((gooddata_in(0) = '1') and (frame_0_in(7 downto 0) = ref_row) ) ) \r
+ else '0';\r
+next_row_match(1) <= '1' when ( (gooddata_in(1) = '0') or\r
+ ((gooddata_in(1) = '1') and (frame_1_in(7 downto 0) = ref_row) ) ) \r
+ else '0';\r
+next_row_match(2) <= '1' when ( (gooddata_in(2) = '0') or\r
+ ((gooddata_in(2) = '1') and (frame_2_in(7 downto 0) = ref_row) ) ) \r
+ else '0';\r
+next_row_match(3) <= '1' when ( (gooddata_in(3) = '0') or\r
+ ((gooddata_in(3) = '1') and (frame_3_in(7 downto 0) = ref_row) ) ) \r
+ else '0';\r
+next_row_match(4) <= '1' when ( (gooddata_in(4) = '0') or\r
+ ((gooddata_in(4) = '1') and (frame_4_in(7 downto 0) = ref_row) ) ) \r
+ else '0';\r
+next_row_match(5) <= '1' when ( (gooddata_in(5) = '0') or\r
+ ((gooddata_in(5) = '1') and (frame_5_in(7 downto 0) = ref_row) ) ) \r
+ else '0';\r
+next_row_match(6) <= '1' when ( (gooddata_in(6) = '0') or\r
+ ((gooddata_in(6) = '1') and (frame_6_in(7 downto 0) = ref_row) ) ) \r
+ else '0';\r
+next_row_match(7) <= '1' when ( (gooddata_in(7) = '0') or\r
+ ((gooddata_in(7) = '1') and (frame_7_in(7 downto 0) = ref_row) ) ) \r
+ else '0';\r
+next_row_match(8) <= '1' when ( (gooddata_in(8) = '0') or\r
+ ((gooddata_in(8) = '1') and (frame_8_in(7 downto 0) = ref_row) ) ) \r
+ else '0';\r
+next_row_match(9) <= '1' when ( (gooddata_in(9) = '0') or\r
+ ((gooddata_in(9) = '1') and (frame_9_in(7 downto 0) = ref_row) ) ) \r
+ else '0';\r
+next_row_match(10) <= '1' when ( (gooddata_in(10) = '0') or\r
+ ((gooddata_in(10) = '1') and (frame_10_in(7 downto 0) = ref_row) ) ) \r
+ else '0';\r
+next_row_match(11) <= '1' when ( (gooddata_in(11) = '0') or\r
+ ((gooddata_in(11) = '1') and (frame_11_in(7 downto 0) = ref_row) ) ) \r
+ else '0';\r
+next_row_match(12) <= '1' when ( (gooddata_in(12) = '0') or\r
+ ((gooddata_in(12) = '1') and (frame_12_in(7 downto 0) = ref_row) ) ) \r
+ else '0';\r
+next_row_match(13) <= '1' when ( (gooddata_in(13) = '0') or\r
+ ((gooddata_in(13) = '1') and (frame_13_in(7 downto 0) = ref_row) ) ) \r
+ else '0';\r
+next_row_match(14) <= '1' when ( (gooddata_in(14) = '0') or\r
+ ((gooddata_in(14) = '1') and (frame_14_in(7 downto 0) = ref_row) ) ) \r
+ else '0';\r
+next_row_match(15) <= '1' when ( (gooddata_in(15) = '0') or\r
+ ((gooddata_in(15) = '1') and (frame_15_in(7 downto 0) = ref_row) ) ) \r
+ else '0';\r
+\r
+-- APV error recognition - same issue.\r
+next_apv_error(0) <= '1' when ( (gooddata_in(0) = '1') and (frame_0_in(8) = '1') ) else '0';\r
+next_apv_error(1) <= '1' when ( (gooddata_in(1) = '1') and (frame_1_in(8) = '1') ) else '0';\r
+next_apv_error(2) <= '1' when ( (gooddata_in(2) = '1') and (frame_2_in(8) = '1') ) else '0';\r
+next_apv_error(3) <= '1' when ( (gooddata_in(3) = '1') and (frame_3_in(8) = '1') ) else '0';\r
+next_apv_error(4) <= '1' when ( (gooddata_in(4) = '1') and (frame_4_in(8) = '1') ) else '0';\r
+next_apv_error(5) <= '1' when ( (gooddata_in(5) = '1') and (frame_5_in(8) = '1') ) else '0';\r
+next_apv_error(6) <= '1' when ( (gooddata_in(6) = '1') and (frame_6_in(8) = '1') ) else '0';\r
+next_apv_error(7) <= '1' when ( (gooddata_in(7) = '1') and (frame_7_in(8) = '1') ) else '0';\r
+next_apv_error(8) <= '1' when ( (gooddata_in(8) = '1') and (frame_8_in(8) = '1') ) else '0';\r
+next_apv_error(9) <= '1' when ( (gooddata_in(9) = '1') and (frame_9_in(8) = '1') ) else '0';\r
+next_apv_error(10) <= '1' when ( (gooddata_in(10) = '1') and (frame_10_in(8) = '1') ) else '0';\r
+next_apv_error(11) <= '1' when ( (gooddata_in(11) = '1') and (frame_11_in(8) = '1') ) else '0';\r
+next_apv_error(12) <= '1' when ( (gooddata_in(12) = '1') and (frame_12_in(8) = '1') ) else '0';\r
+next_apv_error(13) <= '1' when ( (gooddata_in(13) = '1') and (frame_13_in(8) = '1') ) else '0';\r
+next_apv_error(14) <= '1' when ( (gooddata_in(14) = '1') and (frame_14_in(8) = '1') ) else '0';\r
+next_apv_error(15) <= '1' when ( (gooddata_in(15) = '1') and (frame_15_in(8) = '1') ) else '0';\r
+\r
+-- Now we must "condense" the information\r
+next_frame_row_err <= '1' when ( row_match /= x"ffff" ) else '0';\r
+next_frame_apv_err <= '1' when ( apv_error /= x"0000" ) else '0';\r
+\r
+-- output signals\r
+valid_bufs_out <= valid_bufs; \r
+ready_out <= all_ready;\r
+row_error_out <= frame_row_err;\r
+apv_error_out <= frame_apv_err;\r
+ref_row_out <= ref_row;\r
+apv_error_bits_out <= apv_error;\r
+\r
+-- debug signals\r
+debug_x(15) <= '0';\r
+debug_x(14) <= frame_apv_err;\r
+debug_x(13) <= frame_row_err;\r
+debug_x(12) <= valid_bufs;\r
+debug_x(11 downto 8) <= sel_ref_row;\r
+debug_x(7 downto 0) <= ref_row;\r
+\r
+dbg_out <= debug_x;\r
+\r
+end behavioral;\r
--- /dev/null
+library IEEE;\r
+use IEEE.STD_LOGIC_1164.ALL;\r
+use IEEE.STD_LOGIC_ARITH.ALL;\r
+use IEEE.STD_LOGIC_UNSIGNED.ALL;\r
+\r
+library work;\r
+\r
+entity replacement is\r
+port( CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_ADDR_IN : in std_logic_vector(9 downto 0);\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- I/O to the backend\r
+ ADC_SEL_OUT : out std_logic_vector(2 downto 0); -- selects the ADC channel to snoop from\r
+ ADC_CLK_IN : in std_logic; -- ADC reconstructed clock\r
+ ADC_DATA_IN : in std_logic_vector(11 downto 0); -- ADC selected channel data\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+ );\r
+end entity;\r
+\r
+architecture Behavioral of replacement is\r
+\r
+-- Signals\r
+\r
+ type STATES is (SLEEP,RD_RDY,RD_DEL0,RD_DEL1,WR_DEL0,WR_DEL1,WR_RDY,RD_ACK,WR_ACK,DONE);\r
+ signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+ -- slave bus signals\r
+ signal slv_ack_x : std_logic;\r
+ signal slv_ack : std_logic;\r
+ signal store_wr_x : std_logic;\r
+ signal store_wr : std_logic;\r
+ signal store_rd_x : std_logic;\r
+ signal store_rd : std_logic;\r
+\r
+ signal arm_x : std_logic;\r
+ signal trg_x : std_logic;\r
+\r
+ signal ctrl_reg : std_logic_vector(15 downto 0);\r
+ signal status_reg : std_logic_vector(31 downto 0);\r
+\r
+ signal rd_data : std_logic_vector(15 downto 0);\r
+\r
+ -- 40MHz clock domain!!!\r
+ signal wr_data : std_logic_vector(15 downto 0);\r
+ signal wr_addr : std_logic_vector(9 downto 0);\r
+ signal wr_we : std_logic;\r
+ signal reset_40mhz : std_logic;\r
+ signal arm_40mhz : std_logic;\r
+ signal trg_40mhz : std_logic;\r
+\r
+ signal sm_clear : std_logic;\r
+ signal sm_run : std_logic;\r
+ signal sm_sample : std_logic;\r
+ signal sm_ready : std_logic;\r
+ signal sm_last : std_logic;\r
+ signal sm_bsm : std_logic_vector(3 downto 0);\r
+ \r
+begin\r
+\r
+-- Fake\r
+stat(31 downto 25) <= (others => '0');\r
+stat(24) <= sm_last;\r
+stat(23) <= sm_ready;\r
+stat(22) <= sm_sample;\r
+stat(21) <= sm_run;\r
+stat(20) <= sm_clear;\r
+stat(19 downto 16) <= sm_bsm;\r
+stat(15 downto 0) <= ctrl_reg;\r
+\r
+---------------------------------------------------------\r
+-- Statemachine --\r
+---------------------------------------------------------\r
+-- State memory process\r
+STATE_MEM: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ CURRENT_STATE <= SLEEP;\r
+ slv_ack <= '0';\r
+ store_wr <= '0';\r
+ store_rd <= '0';\r
+ else\r
+ CURRENT_STATE <= NEXT_STATE;\r
+ slv_ack <= slv_ack_x;\r
+ store_wr <= store_wr_x;\r
+ store_rd <= store_rd_x;\r
+ end if;\r
+ end if;\r
+end process STATE_MEM;\r
+\r
+-- Transition matrix\r
+TRANSFORM: process( CURRENT_STATE, slv_read_in, slv_write_in )\r
+begin\r
+ NEXT_STATE <= SLEEP;\r
+ slv_ack_x <= '0';\r
+ store_wr_x <= '0';\r
+ store_rd_x <= '0';\r
+ case CURRENT_STATE is\r
+ when SLEEP => if ( slv_read_in = '1' ) then\r
+ NEXT_STATE <= RD_DEL0;\r
+ store_rd_x <= '1';\r
+ elsif( slv_write_in = '1' ) then\r
+ NEXT_STATE <= WR_DEL0;\r
+ store_wr_x <= '1';\r
+ else \r
+ NEXT_STATE <= SLEEP;\r
+ end if;\r
+ when RD_DEL0 => NEXT_STATE <= RD_DEL1;\r
+ when RD_DEL1 => NEXT_STATE <= RD_RDY;\r
+ when RD_RDY => NEXT_STATE <= RD_ACK;\r
+ when RD_ACK => if( slv_read_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ slv_ack_x <= '1';\r
+ else\r
+ NEXT_STATE <= RD_ACK;\r
+ slv_ack_x <= '1';\r
+ end if;\r
+ when WR_DEL0 => NEXT_STATE <= WR_DEL1;\r
+ when WR_DEL1 => NEXT_STATE <= WR_RDY;\r
+ when WR_RDY => NEXT_STATE <= WR_ACK;\r
+ when WR_ACK => if( slv_write_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ slv_ack_x <= '1';\r
+ else\r
+ NEXT_STATE <= WR_ACK;\r
+ slv_ack_x <= '1';\r
+ end if;\r
+ when DONE => NEXT_STATE <= SLEEP;\r
+ \r
+ when others => NEXT_STATE <= SLEEP;\r
+ end case;\r
+end process TRANSFORM;\r
+\r
+---------------------------------------------------------\r
+-- data handling --\r
+---------------------------------------------------------\r
+\r
+THE_RST_SYNC: state_sync\r
+port map( STATE_A_IN => reset_in,\r
+ CLK_B_IN => adc_clk_in,\r
+ RESET_B_IN => '0',\r
+ STATE_B_OUT => reset_40mhz\r
+ );\r
+\r
+arm_x <= slv_data_in(30) and store_wr;\r
+\r
+THE_ARM_PULSE_SYNC: pulse_sync\r
+port map( CLK_A_IN => clk_in,\r
+ RESET_A_IN => reset_in,\r
+ PULSE_A_IN => arm_x,\r
+ CLK_B_IN => adc_clk_in,\r
+ RESET_B_IN => reset_40mhz,\r
+ PULSE_B_OUT => arm_40mhz\r
+ );\r
+\r
+trg_x <= slv_data_in(31) and store_wr;\r
+\r
+THE_TRG_PULSE_SYNC: pulse_sync\r
+port map( CLK_A_IN => clk_in,\r
+ RESET_A_IN => reset_in,\r
+ PULSE_A_IN => trg_x,\r
+ CLK_B_IN => adc_clk_in,\r
+ RESET_B_IN => reset_40mhz,\r
+ PULSE_B_OUT => trg_40mhz\r
+ );\r
+\r
+THE_LOGIC_ANALYZER: logic_analyzer\r
+port map( CLK_IN => adc_clk_in,\r
+ RESET_IN => reset_40mhz,\r
+ -- control signals\r
+ ARM_IN => arm_40mhz, -- BUGBUGBUG\r
+ TRG_IN => trg_40mhz, -- BUGBUGBUG\r
+ MAX_SAMPLE_IN => ctrl_reg(9 downto 0),\r
+ -- status signals\r
+ SM_ADDR_OUT => wr_addr,\r
+ SM_CE_OUT => open,\r
+ SM_WE_OUT => wr_we,\r
+ CLEAR_OUT => sm_clear,\r
+ RUN_OUT => sm_run,\r
+ SAMPLE_OUT => sm_sample,\r
+ READY_OUT => sm_ready,\r
+ LAST_OUT => sm_last,\r
+ -- Status lines\r
+ BSM_OUT => sm_bsm,\r
+ STAT => open\r
+ );\r
+\r
+wr_data(15) <= sm_clear;\r
+wr_data(14) <= sm_run;\r
+wr_data(13) <= sm_sample;\r
+wr_data(12) <= sm_last;\r
+wr_data(11 downto 0) <= adc_data_in;\r
+\r
+THE_ADC0_SNOOP_MEM: adc_snoop_mem\r
+port map( WRADDRESS => wr_addr,\r
+ DATA => wr_data,\r
+ WE => wr_we,\r
+ WRCLOCK => adc_clk_in,\r
+ WRCLOCKEN => '1',\r
+ RDADDRESS => slv_addr_in, \r
+ RDCLOCK => clk_in,\r
+ RDCLOCKEN => '1',\r
+ RESET => reset_in,\r
+ Q => rd_data\r
+ );\r
+\r
+-- register write\r
+THE_WRITE_REG_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( reset_in = '1' ) then\r
+ ctrl_reg <= (others => '0');\r
+ elsif( store_wr = '1' ) then\r
+ ctrl_reg <= slv_data_in(15 downto 0);\r
+ end if;\r
+ end if;\r
+end process THE_WRITE_REG_PROC;\r
+\r
+-- register read\r
+THE_READ_REG_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( reset_in = '1' ) then\r
+ status_reg <= (others => '0');\r
+ elsif( store_rd = '1' ) then\r
+ status_reg <= b"0000_00" & wr_addr & rd_data;\r
+ end if;\r
+ end if;\r
+end process THE_READ_REG_PROC;\r
+\r
+-- output signals\r
+slv_ack_out <= slv_ack;\r
+slv_data_out <= status_reg;\r
+\r
+adc_sel_out <= ctrl_reg(14 downto 12);\r
+\r
+end Behavioral;\r
--- /dev/null
+library ieee; \r
+use ieee.std_logic_1164.all; \r
+use ieee.std_logic_arith.all; \r
+use ieee.std_logic_unsigned.all;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+entity reset_handler is\r
+ port( CLEAR_IN : in std_logic; -- async reset from outside, if available (otherwise '0')\r
+ RESET_IN : in std_logic; -- for testing, if not needed, set to '0'\r
+ CLK_IN : in std_logic;\r
+ TRB_RESET_IN : in std_logic;\r
+ RESET_OUT : out std_logic;\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
+end;\r
+\r
+architecture behavioral of reset_handler is\r
+\r
+-- normal signals\r
+ signal async_sampler : std_logic_vector(7 downto 0);\r
+ signal async_pulse_x : std_logic;\r
+ signal async_pulse : std_logic;\r
+ signal reset_cnt : std_logic_vector(15 downto 0);\r
+ signal debug : std_logic_vector(15 downto 0);\r
+ signal reset : std_logic;\r
+\r
+ attribute syn_preserve : boolean;\r
+ attribute syn_preserve of async_sampler : signal is true;\r
+ attribute syn_preserve of async_pulse : signal is true;\r
+ attribute syn_preserve of reset : signal is true;\r
+ attribute syn_preserve of reset_cnt : signal is true;\r
+ \r
+begin \r
+\r
+-- sample the async reset line and react only on a long pulse\r
+THE_ASYNC_SAMPLER_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ async_sampler(7 downto 0) <= async_sampler(6 downto 0) & clear_in;\r
+ async_pulse <= async_pulse_x;\r
+ end if;\r
+end process THE_ASYNC_SAMPLER_PROC;\r
+\r
+async_pulse_x <= '1' when ( async_sampler = x"ff" ) else '0';\r
+\r
+-- one global reset counter\r
+THE_GLOBAL_RESET_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( (async_pulse = '1') or (reset_in = '1') or (trb_reset_in = '1') ) then\r
+ reset_cnt <= (others => '0');\r
+ reset <= '1';\r
+ else\r
+ reset_cnt <= reset_cnt + 1;\r
+ reset <= '1';\r
+ if( reset_cnt = x"001F" ) then\r
+ reset <= '0';\r
+ reset_cnt <= x"001F";\r
+ end if;\r
+ end if;\r
+ end if;\r
+end process THE_GLOBAL_RESET_PROC;\r
+\r
+\r
+-- Debug signals\r
+debug <= reset_cnt;\r
+\r
+-- Output signals\r
+debug_out <= debug;\r
+reset_out <= reset;\r
+ \r
+end behavioral; \r
+
\ No newline at end of file
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.numeric_std.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;
+
+library work;
+use work.version.all;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.adcmv3_components.all;
+
+entity rich_trb is
+port( CLK100M_IN : in std_logic; -- SerDes exclusive clock
+ SYSCLK_IN : in std_logic; -- fabric clock
+ RESET_IN : in std_logic; -- synchronous reset
+ -- SFP connections
+ SD_RXD_P_IN : in std_logic;
+ SD_RXD_N_IN : in std_logic;
+ SD_TXD_P_OUT : out std_logic;
+ SD_TXD_N_OUT : out std_logic;
+ SD_PRESENT_IN : in std_logic;
+ SD_TXDIS_OUT : out std_logic;
+ SD_LOS_IN : in std_logic;
+ ONEWIRE_INOUT : inout std_logic;
+ -- common regIO status / control registers
+ COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REGISTER_WIDTH-1 downto 0); -- common status register, bit definitions like in WIKI
+ COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*c_REGIO_REGISTER_WIDTH-1 downto 0); -- common control register, bit definitions like in WIKI
+ -- status register input to regIO / control register output from regIO
+ CONTROL_OUT : out std_logic_vector(63 downto 0);
+ STATUS_IN : in std_logic_vector(127 downto 0);
+ -- LVL1 signals
+ LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0);
+ LVL1_TRG_RECEIVED_OUT : out std_logic;
+ LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0);
+ LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0);
+ LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0);
+ LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0);
+ LVL1_TRG_RELEASE_IN : in std_logic;
+ TIMING_TRG_FOUND_IN : in std_logic;
+ -- IPU data channel signals (yes, we will use ComputeNodes (tm) (R) (C) one day... :-)
+ IPU_NUMBER_OUT : out std_logic_vector(15 downto 0); -- trigger tag
+ IPU_INFORMATION_OUT : out std_logic_vector(7 downto 0); -- trigger information
+ IPU_START_READOUT_OUT : out std_logic; -- gimme data!
+ IPU_DATA_IN : in std_logic_vector(31 downto 0); -- detector data, equipped with DHDR
+ IPU_DATAREADY_IN : in std_logic; -- data is valid
+ IPU_READOUT_FINISHED_IN : in std_logic; -- no more data, end transfer, send TRM
+ IPU_READ_OUT : out std_logic; -- read strobe, low every second cycle
+ IPU_LENGTH_IN : in std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?)
+ IPU_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); -- error pattern
+ -- regIO bus
+ REGIO_ADDR_OUT : out std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0);
+ REGIO_READ_ENABLE_OUT : out std_logic;
+ REGIO_WRITE_ENABLE_OUT : out std_logic;
+ REGIO_DATA_OUT : out std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0);
+ REGIO_DATA_IN : in std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0);
+ REGIO_DATAREADY_IN : in std_logic;
+ REGIO_NO_MORE_DATA_IN : in std_logic;
+ REGIO_WRITE_ACK_IN : in std_logic;
+ REGIO_UNKNOWN_ADDR_IN : in std_logic;
+ REGIO_TIMEOUT_OUT : out std_logic;
+ -- status LEDs
+ LED_LINK_STAT : out std_logic;
+ LED_LINK_TXD : out std_logic;
+ LED_LINK_RXD : out std_logic;
+ LINK_BSM_OUT : out std_logic_vector(3 downto 0);
+ RESET_OUT : out std_logic;
+ -- Debug
+ DEBUG : out std_logic_vector(63 downto 0)
+ );
+end entity;
+
+architecture rich_arch of rich_trb is
+
+ -- Placer Directives
+ attribute HGROUP : string;
+ -- for whole architecture
+ attribute HGROUP of rich_arch : architecture is "RICH_TRB_group";
+
+ -- Signals
+ signal clk_en : std_logic;
+ signal med_data_in : std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ signal med_packet_num_in : std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ signal med_dataready_in : std_logic;
+ signal med_read_out : std_logic;
+ signal med_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ signal med_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ signal med_dataready_out : std_logic;
+ signal med_read_in : std_logic;
+ signal med_stat_debug : std_logic_vector(63 downto 0);
+ signal med_ctrl_op : std_logic_vector(15 downto 0);
+ signal med_stat_op : std_logic_vector(15 downto 0);
+
+ -- general purpose control and status registers in regIO
+ signal regio_ctrl_regs : std_logic_vector(32*2-1 downto 0);
+ signal regio_stat_regs : std_logic_vector(32*4-1 downto 0);
+
+ signal common_stat_reg : std_logic_vector(std_COMSTATREG*c_REGIO_REGISTER_WIDTH-1 downto 0);
+ signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*c_REGIO_REGISTER_WIDTH-1 downto 0);
+
+ signal debug_x : std_logic_vector(63 downto 0);
+
+ signal stat_debug_1 : std_logic_vector(31 downto 0);
+
+begin
+
+--#######################################################################
+
+--#######################################################################
+
+-- Debug
+debug <= debug_x;
+
+-- Clock assignment. We don't use CLK_EN really in our designs.
+clk_en <= '1';
+
+-------------------------------------------------------------
+-- Serdes
+-------------------------------------------------------------
+THE_MEDIA_INTERFACE : trb_net16_med_ecp_sfp_gbe
+generic map( SERDES_NUM => 2 )
+port map( CLK => clk100m_in,
+ SYSCLK => sysclk_in,
+ RESET => reset_in,
+ CLK_EN => clk_en,
+ --Internal Connection
+ MED_DATA_IN => med_data_out,
+ MED_PACKET_NUM_IN => med_packet_num_out,
+ MED_DATAREADY_IN => med_dataready_out,
+ MED_READ_OUT => med_read_in,
+ MED_DATA_OUT => med_data_in,
+ MED_PACKET_NUM_OUT => med_packet_num_in,
+ MED_DATAREADY_OUT => med_dataready_in,
+ MED_READ_IN => med_read_out,
+ REFCLK2CORE_OUT => open,
+ --SFP Connection
+ SD_RXD_P_IN => sd_rxd_p_in,
+ SD_RXD_N_IN => sd_rxd_n_in,
+ SD_TXD_P_OUT => sd_txd_p_out,
+ SD_TXD_N_OUT => sd_txd_n_out,
+ SD_REFCLK_P_IN => '1',
+ SD_REFCLK_N_IN => '0',
+ SD_PRSNT_N_IN => sd_present_in,
+ SD_LOS_IN => sd_los_in,
+ SD_TXDIS_OUT => sd_txdis_out,
+ -- Status and control port
+ STAT_OP => med_stat_op,
+ CTRL_OP => med_ctrl_op, -- input
+ STAT_DEBUG => med_stat_debug,
+ CTRL_DEBUG => (others => '0')
+ );
+
+--debug_x <= med_stat_debug;
+
+debug_x(63 downto 42) <= (others => '0');
+debug_x(41) <= med_read_out; -- MED_READ_IN
+debug_x(40) <= med_dataready_in; -- MED_DATAREADY_OUT
+debug_x(39 downto 37) <= med_packet_num_in; -- MED_PACKET_NUM_OUT
+debug_x(36 downto 21) <= med_data_in; -- MED_DATA_OUT
+debug_x(20) <= med_read_in; -- MED_READ_OUT
+debug_x(19) <= med_dataready_out; -- MED_DATAREADY_IN
+debug_x(18 downto 16) <= med_packet_num_out; -- MED_PACKET_NUM_IN
+debug_x(15 downto 0) <= med_data_out; -- MED_DATA_IN
+
+-- 16 MED_DATA_IN : in std_logic_vector(15 downto 0);
+-- 3 MED_PACKET_NUM_IN : in std_logic_vector(2 downto 0);
+-- 1 MED_DATAREADY_IN : in std_logic;
+-- 1 MED_READ_OUT : out std_logic;
+-- 16 MED_DATA_OUT : out std_logic_vector(15 downto 0);
+-- 3 MED_PACKET_NUM_OUT : out std_logic_vector(2 downto 0);
+-- 1 MED_DATAREADY_OUT : out std_logic;
+-- 1 MED_READ_IN : in std_logic;
+-- 42
+
+ ------------------------------------------------------------
+-- Full featured HADES endpoint
+-------------------------------------------------------------
+THE_UNIFIED_ENDPOINT: trb_net16_endpoint_hades_full
+generic map( USE_CHANNEL => (c_YES,c_YES,c_NO,c_YES),
+ INIT_CAN_SEND_DATA => (c_NO,c_NO,c_NO,c_NO), -- was c_YES before?
+ REPLY_CAN_SEND_DATA => (c_YES,c_YES,c_YES,c_YES),
+ REPLY_CAN_RECEIVE_DATA => (c_NO,c_NO,c_NO,c_NO),
+ BROADCAST_BITMASK => x"FB", -- RICH uses 0xfffb as subnet mask for broadcasts
+ REGIO_NUM_STAT_REGS => 2, -- minimum number: 32 * 2^0 - 1 = 31 => D[31:0]
+ REGIO_NUM_CTRL_REGS => 1, -- minimum number: 32 * 2^0 - 1 = 31 => D[31:0]
+ --standard values for output registers
+ REGIO_INIT_CTRL_REGS => x"00000000_00000000_00000000_00000000" &
+ x"00000000_00000000_00000000_00000000",
+ --set to 0 for unused ctrl registers to save resources
+ REGIO_USED_CTRL_REGS => "00000001",
+ --set to 0 for each unused bit in a register
+ REGIO_USED_CTRL_BITMASK => x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF" &
+ x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF",
+ REGIO_USE_DAT_PORT => c_YES,
+ REGIO_INIT_ADDRESS => x"fb00",
+ REGIO_INIT_UNIQUE_ID => x"dead_beef_affe_d00f",
+ REGIO_INIT_BOARD_INFO => x"5aa5_3cc3",
+ REGIO_INIT_ENDPOINT_ID => x"0001",
+ REGIO_COMPILE_TIME => VERSION_NUMBER_TIME,
+ REGIO_COMPILE_VERSION => x"0003",
+ REGIO_HARDWARE_VERSION => x"0002_0000",
+ REGIO_USE_1WIRE_INTERFACE => c_YES,
+ CLOCK_FREQUENCY => 100
+ )
+port map( CLK => sysclk_in,
+ RESET => reset_in,
+ CLK_EN => clk_en,
+ -- Media direction port
+ MED_DATAREADY_OUT => med_dataready_out,
+ MED_DATA_OUT => med_data_out,
+ MED_PACKET_NUM_OUT => med_packet_num_out,
+ MED_READ_IN => med_read_in,
+ MED_DATAREADY_IN => med_dataready_in,
+ MED_DATA_IN => med_data_in,
+ MED_PACKET_NUM_IN => med_packet_num_in,
+ MED_READ_OUT => med_read_out,
+ MED_STAT_OP_IN => med_stat_op,
+ MED_CTRL_OP_OUT => med_ctrl_op,
+ -- LVL1 trigger APL
+ LVL1_TRG_TYPE_OUT => lvl1_trg_type_out,
+ LVL1_TRG_RECEIVED_OUT => lvl1_trg_received_out,
+ LVL1_TRG_NUMBER_OUT => lvl1_trg_number_out,
+ LVL1_TRG_CODE_OUT => lvl1_trg_code_out,
+ LVL1_TRG_INFORMATION_OUT => lvl1_trg_information_out,
+ LVL1_ERROR_PATTERN_IN => lvl1_error_pattern_in,
+ LVL1_TRG_RELEASE_IN => lvl1_trg_release_in,
+ LVL1_INT_TRG_NUMBER_OUT => open, -- unknown!!!
+ -- IPU Port
+ IPU_NUMBER_OUT => ipu_number_out,
+ IPU_READOUT_TYPE_OUT => open, -- 4bit readout type
+ IPU_INFORMATION_OUT => ipu_information_out,
+ IPU_START_READOUT_OUT => ipu_start_readout_out,
+ IPU_DATA_IN => ipu_data_in,
+ IPU_DATAREADY_IN => ipu_dataready_in,
+ IPU_READOUT_FINISHED_IN => ipu_readout_finished_in,
+ IPU_READ_OUT => ipu_read_out,
+ IPU_LENGTH_IN => ipu_length_in,
+ IPU_ERROR_PATTERN_IN => ipu_error_pattern_in,
+ -- Slow Control Data Port
+ REGIO_COMMON_STAT_REG_IN => common_stat_reg,
+ REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg,
+ REGIO_REGISTERS_IN => regio_stat_regs,
+ REGIO_REGISTERS_OUT => regio_ctrl_regs,
+ COMMON_STAT_REG_STROBE => open, --: out std_logic_vector(std_COMSTATREG-1 downto 0);
+ COMMON_CTRL_REG_STROBE => open, --: out std_logic_vector(std_COMCTRLREG-1 downto 0);
+ STAT_REG_STROBE => open, --: out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0);
+ CTRL_REG_STROBE => open, --: out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
+ --following ports only used when using internal data port
+ REGIO_ADDR_OUT => regio_addr_out,
+ REGIO_READ_ENABLE_OUT => regio_read_enable_out,
+ REGIO_WRITE_ENABLE_OUT => regio_write_enable_out,
+ REGIO_DATA_OUT => regio_data_out,
+ REGIO_DATA_IN => regio_data_in,
+ REGIO_DATAREADY_IN => regio_dataready_in,
+ REGIO_NO_MORE_DATA_IN => regio_no_more_data_in,
+ REGIO_WRITE_ACK_IN => regio_write_ack_in,
+ REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr_in,
+ REGIO_TIMEOUT_OUT => regio_timeout_out,
+ --IDRAM is used if no 1-wire interface, onewire used otherwise
+ REGIO_IDRAM_DATA_IN => x"0000", -- not used
+ REGIO_IDRAM_DATA_OUT => open, -- not used
+ REGIO_IDRAM_ADDR_IN => "000", -- not used
+ REGIO_IDRAM_WR_IN => '0', -- not used
+ REGIO_ONEWIRE_INOUT => onewire_inout,
+ REGIO_ONEWIRE_MONITOR_IN => '1', -- not used
+ REGIO_ONEWIRE_MONITOR_OUT => open, -- not used
+ -- New stuff?!?
+ TRIGGER_MONITOR_IN => timing_trg_found_in,
+ GLOBAL_TIME_OUT => open,
+ LOCAL_TIME_OUT => open,
+ TIME_SINCE_LAST_TRG_OUT => open,
+ TIMER_US_TICK_OUT => open,
+ -- Status and debug
+ STAT_DEBUG_IPU => open,
+ STAT_DEBUG_1 => stat_debug_1, --open,
+ STAT_DEBUG_2 => open,
+ MED_STAT_OP => open,
+ CTRL_MPLEX => x"00000000",
+ IOBUF_CTRL_GEN => x"00000000_00000000_00000000_00000000",
+ STAT_ONEWIRE => open,
+ STAT_ADDR_DEBUG => open
+ );
+
+-- Control register assignment
+
+-- Common status register
+common_stat_reg(COMMON_STAT_REG'left downto 32) <= common_stat_reg_in(63 downto 32); --(others => '0');
+common_stat_reg(31 downto 20) <= (others => '0'); -- already taken by TEMP of 1WID
+common_stat_reg(19 downto 0) <= common_stat_reg_in(19 downto 0); --(others => '0');
+
+-- Common control register
+common_ctrl_reg_out <= common_ctrl_reg;
+
+-- User status register
+regio_stat_regs <= status_in;
+control_out <= regio_ctrl_regs;
+
+-- FPGA LEDs
+led_link_stat <= not med_stat_op(9); -- link status
+led_link_rxd <= not med_stat_op(10); -- not med_packet_num_in(2); -- data receive
+led_link_txd <= not med_stat_op(11); -- data transmit
+link_bsm_out <= med_stat_op(7 downto 4); -- LSM state bits
+reset_out <= med_stat_op(13); -- TRB generated reset
+
+end architecture;
+
\ No newline at end of file
--- /dev/null
+library IEEE;\r
+use IEEE.STD_LOGIC_1164.ALL;\r
+use IEEE.STD_LOGIC_ARITH.ALL;\r
+use IEEE.STD_LOGIC_UNSIGNED.ALL;\r
+\r
+library work;\r
+use work.trb_net_std.all;\r
+use work.trb_net_components.all;\r
+use work.adcmv3_components.all;\r
+\r
+\r
+entity slave_bus is\r
+port( CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- RegIO signals\r
+ REGIO_ADDR_IN : in std_logic_vector(15 downto 0); -- address bus \r
+ REGIO_DATA_IN : in std_logic_vector(31 downto 0); -- data from TRB endpoint\r
+ REGIO_DATA_OUT : out std_logic_vector(31 downto 0); -- data to TRB endpoint\r
+ REGIO_READ_ENABLE_IN : in std_logic; -- read pulse\r
+ REGIO_WRITE_ENABLE_IN : in std_logic; -- write pulse\r
+ REGIO_TIMEOUT_IN : in std_logic; -- access timed out\r
+ REGIO_DATAREADY_OUT : out std_logic; -- your data, master, as requested\r
+ REGIO_WRITE_ACK_OUT : out std_logic; -- data accepted\r
+ REGIO_NO_MORE_DATA_OUT : out std_logic; -- don't disturb me now\r
+ REGIO_UNKNOWN_ADDR_OUT : out std_logic; -- noone here to answer your request\r
+ -- I2C connections\r
+ SDA_IN : in std_logic;\r
+ SDA_OUT : out std_logic;\r
+ SCL_IN : in std_logic;\r
+ SCL_OUT : out std_logic;\r
+ -- 1Wire connections\r
+ ONEWIRE_START_IN : in std_logic; -- start 1Wire scan (pulse)\r
+ ONEWIRE_INOUT : inout std_logic_vector(15 downto 0);\r
+ BP_ONEWIRE_INOUT : inout std_logic; -- 1Wire ID on backplane\r
+ -- SPI connections\r
+ SPI_CS_OUT : out std_logic;\r
+ SPI_SCK_OUT : out std_logic;\r
+ SPI_SDI_IN : in std_logic;\r
+ SPI_SDO_OUT : out std_logic;\r
+ -- ADC 0 SPI connections\r
+ SPI_ADC0_CS_OUT : out std_logic;\r
+ SPI_ADC0_SCK_OUT : out std_logic;\r
+ SPI_ADC0_SDO_OUT : out std_logic;\r
+ ADC0_PLL_LOCKED_IN : in std_logic;\r
+ ADC0_PD_OUT : out std_logic;\r
+ ADC0_RST_OUT : out std_logic;\r
+ ADC0_DEL_OUT : out std_logic_vector(3 downto 0);\r
+ ADC0_CLK_IN : in std_logic;\r
+ ADC0_DATA_IN : in std_logic_vector(11 downto 0);\r
+ ADC0_SEL_OUT : out std_logic_vector(2 downto 0);\r
+ APV0_RST_OUT : out std_logic;\r
+ -- ADC 1 SPI connections\r
+ SPI_ADC1_CS_OUT : out std_logic;\r
+ SPI_ADC1_SCK_OUT : out std_logic;\r
+ SPI_ADC1_SDO_OUT : out std_logic;\r
+ ADC1_PLL_LOCKED_IN : in std_logic;\r
+ ADC1_PD_OUT : out std_logic;\r
+ ADC1_RST_OUT : out std_logic;\r
+ ADC1_DEL_OUT : out std_logic_vector(3 downto 0);\r
+ ADC1_CLK_IN : in std_logic;\r
+ ADC1_DATA_IN : in std_logic_vector(11 downto 0);\r
+ ADC1_SEL_OUT : out std_logic_vector(2 downto 0);\r
+ APV1_RST_OUT : out std_logic;\r
+ -- User specific inputs / outputs\r
+ BACKPLANE_IN : in std_logic_vector(2 downto 0);\r
+ -- pedestal interface\r
+ PED_ADDR_IN : in std_logic_vector(6 downto 0); -- pedestal addressing from data handlers\r
+ PED_DATA_0_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_1_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_2_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_3_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_4_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_5_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_6_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_7_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_8_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_9_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_10_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_11_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_12_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_13_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_14_OUT : out std_logic_vector(17 downto 0);\r
+ PED_DATA_15_OUT : out std_logic_vector(17 downto 0);\r
+ -- threshold interface\r
+ THR_ADDR_IN : in std_logic_vector(6 downto 0); -- threshold addressing from data handlers\r
+ THR_DATA_0_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_1_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_2_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_3_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_4_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_5_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_6_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_7_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_8_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_9_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_10_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_11_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_12_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_13_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_14_OUT : out std_logic_vector(17 downto 0);\r
+ THR_DATA_15_OUT : out std_logic_vector(17 downto 0);\r
+ -- APV control / status\r
+ CTRL_0_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_1_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_2_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_3_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_4_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_5_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_6_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_7_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_8_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_9_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_10_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_11_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_12_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_13_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_14_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_15_OUT : out std_logic_vector(15 downto 0);\r
+ STAT_0_IN : in std_logic_vector(15 downto 0);\r
+ STAT_1_IN : in std_logic_vector(15 downto 0);\r
+ STAT_2_IN : in std_logic_vector(15 downto 0);\r
+ STAT_3_IN : in std_logic_vector(15 downto 0);\r
+ STAT_4_IN : in std_logic_vector(15 downto 0);\r
+ STAT_5_IN : in std_logic_vector(15 downto 0);\r
+ STAT_6_IN : in std_logic_vector(15 downto 0);\r
+ STAT_7_IN : in std_logic_vector(15 downto 0);\r
+ STAT_8_IN : in std_logic_vector(15 downto 0);\r
+ STAT_9_IN : in std_logic_vector(15 downto 0);\r
+ STAT_10_IN : in std_logic_vector(15 downto 0);\r
+ STAT_11_IN : in std_logic_vector(15 downto 0);\r
+ STAT_12_IN : in std_logic_vector(15 downto 0);\r
+ STAT_13_IN : in std_logic_vector(15 downto 0);\r
+ STAT_14_IN : in std_logic_vector(15 downto 0);\r
+ STAT_15_IN : in std_logic_vector(15 downto 0);\r
+ -- some control signals\r
+ CTRL_LVL_OUT : out std_logic_vector(31 downto 0);\r
+ CTRL_TRG_OUT : out std_logic_vector(31 downto 0);\r
+ CTRL_PLL_OUT : out std_logic_vector(15 downto 0);\r
+ STATUS_PLL_IN : in std_logic_vector(15 downto 0);\r
+ -- temporary stuff\r
+ TEST_REG_IN : in std_logic_vector(31 downto 0); -- just for testing!\r
+ TEST_REG_OUT : out std_logic_vector(31 downto 0); -- just for testing!\r
+ -- Debug\r
+ DEBUG_OUT : out std_logic_vector(63 downto 0);\r
+ STAT : out std_logic_vector(31 downto 0)\r
+ );\r
+end entity;\r
+\r
+architecture Behavioral of slave_bus is\r
+\r
+ -- Signals\r
+ signal slv_read : std_logic_vector(15-1 downto 0);\r
+ signal slv_write : std_logic_vector(15-1 downto 0);\r
+ signal slv_busy : std_logic_vector(15-1 downto 0);\r
+ signal slv_ack : std_logic_vector(15-1 downto 0);\r
+ signal slv_addr : std_logic_vector(15*16-1 downto 0);\r
+ signal slv_data_rd : std_logic_vector(15*32-1 downto 0);\r
+ signal slv_data_wr : std_logic_vector(15*32-1 downto 0);\r
+ \r
+ -- SPI controller BRAM lines\r
+ signal spi_bram_addr : std_logic_vector(7 downto 0);\r
+ signal spi_bram_wr_d : std_logic_vector(7 downto 0);\r
+ signal spi_bram_rd_d : std_logic_vector(7 downto 0);\r
+ signal spi_bram_we : std_logic;\r
+ \r
+ signal spi_cs : std_logic;\r
+ signal spi_sck : std_logic;\r
+ signal spi_sdi : std_logic;\r
+ signal spi_sdo : std_logic;\r
+ signal spi_debug : std_logic_vector(31 downto 0);\r
+ \r
+ signal ctrl_lvl : std_logic_vector(31 downto 0);\r
+ signal ctrl_trg : std_logic_vector(31 downto 0);\r
+ signal ctrl_pll : std_logic_vector(15 downto 0);\r
+ \r
+ signal debug : std_logic_vector(63 downto 0);\r
+ signal onewire_debug : std_logic_vector(63 downto 0);\r
+ \r
+begin\r
+\r
+-- Bus handler: acts as bridge between RegIO and the FPGA internal slave bus\r
+THE_BUS_HANDLER: trb_net16_regio_bus_handler\r
+generic map( PORT_NUMBER => 15,\r
+ PORT_ADDRESSES => ( 0 => x"a000", -- pedestal memories \r
+ 1 => x"a800", -- threshold memories\r
+ 2 => x"8040", -- I2C master\r
+ 3 => x"c000", -- 1Wire master + memory\r
+ 4 => x"d000", -- SPI master\r
+ 5 => x"d100", -- SPI data memory \r
+ 6 => x"d010", -- ADC0 SPI \r
+ 7 => x"d020", -- ADC1 SPI\r
+ 8 => x"b000", -- APV control / status\r
+ 9 => x"b010", -- ADC level settings\r
+ 10 => x"b020", -- trigger settings\r
+ 11 => x"b030", -- PLL settings\r
+ 12 => x"f000", -- ADC 0 snooper\r
+ 13 => x"f800", -- ADC 1 snooper\r
+ 14 => x"8000", -- test register (busy)\r
+ others => x"0000"), \r
+ PORT_ADDR_MASK => ( 0 => 11, -- pedestal memories\r
+ 1 => 11, -- threshold memories\r
+ 2 => 0, -- I2C master\r
+ 3 => 6, -- 1Wire master + memory\r
+ 4 => 1, -- SPI master\r
+ 5 => 6, -- SPI data memory\r
+ 6 => 0, -- ADC0 SPI\r
+ 7 => 0, -- ADC1 SPI\r
+ 8 => 4, -- APV control / status \r
+ 9 => 0, -- ADC level settings\r
+ 10 => 0, -- trigger settings\r
+ 11 => 0, -- PLL settings\r
+ 12 => 10, -- ADC 0 snooper\r
+ 13 => 10, -- ADC 1 snooper\r
+ 14 => 0, -- test register (normal)\r
+ others => 0)\r
+ )\r
+port map( CLK => clk_in,\r
+ RESET => reset_in,\r
+ DAT_ADDR_IN => regio_addr_in,\r
+ DAT_DATA_IN => regio_data_in,\r
+ DAT_DATA_OUT => regio_data_out,\r
+ DAT_READ_ENABLE_IN => regio_read_enable_in,\r
+ DAT_WRITE_ENABLE_IN => regio_write_enable_in,\r
+ DAT_TIMEOUT_IN => regio_timeout_in,\r
+ DAT_DATAREADY_OUT => regio_dataready_out,\r
+ DAT_WRITE_ACK_OUT => regio_write_ack_out,\r
+ DAT_NO_MORE_DATA_OUT => regio_no_more_data_out,\r
+ DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_out,\r
+ -- pedestal memories\r
+ BUS_READ_ENABLE_OUT(0) => slv_read(0),\r
+ BUS_WRITE_ENABLE_OUT(0) => slv_write(0),\r
+ BUS_DATA_OUT(0*32+31 downto 0*32) => slv_data_wr(0*32+31 downto 0*32),\r
+ BUS_DATA_IN(0*32+31 downto 0*32) => slv_data_rd(0*32+31 downto 0*32), \r
+ BUS_ADDR_OUT(0*16+15 downto 0*16) => slv_addr(0*16+15 downto 0*16),\r
+ BUS_TIMEOUT_OUT(0) => open,\r
+ BUS_DATAREADY_IN(0) => slv_ack(0),\r
+ BUS_WRITE_ACK_IN(0) => slv_ack(0),\r
+ BUS_NO_MORE_DATA_IN(0) => slv_busy(0),\r
+ BUS_UNKNOWN_ADDR_IN(0) => '0',\r
+ -- threshold memories\r
+ BUS_READ_ENABLE_OUT(1) => slv_read(1),\r
+ BUS_WRITE_ENABLE_OUT(1) => slv_write(1),\r
+ BUS_DATA_OUT(1*32+31 downto 1*32) => slv_data_wr(1*32+31 downto 1*32),\r
+ BUS_DATA_IN(1*32+31 downto 1*32) => slv_data_rd(1*32+31 downto 1*32), \r
+ BUS_ADDR_OUT(1*16+15 downto 1*16) => slv_addr(1*16+15 downto 1*16),\r
+ BUS_TIMEOUT_OUT(1) => open,\r
+ BUS_DATAREADY_IN(1) => slv_ack(1),\r
+ BUS_WRITE_ACK_IN(1) => slv_ack(1),\r
+ BUS_NO_MORE_DATA_IN(1) => slv_busy(1),\r
+ BUS_UNKNOWN_ADDR_IN(1) => '0',\r
+ -- I2C master\r
+ BUS_READ_ENABLE_OUT(2) => slv_read(2),\r
+ BUS_WRITE_ENABLE_OUT(2) => slv_write(2),\r
+ BUS_DATA_OUT(2*32+31 downto 2*32) => slv_data_wr(2*32+31 downto 2*32),\r
+ BUS_DATA_IN(2*32+31 downto 2*32) => slv_data_rd(2*32+31 downto 2*32), \r
+ BUS_ADDR_OUT(2*16+15 downto 2*16) => open,\r
+ BUS_TIMEOUT_OUT(2) => open,\r
+ BUS_DATAREADY_IN(2) => slv_ack(2),\r
+ BUS_WRITE_ACK_IN(2) => slv_ack(2),\r
+ BUS_NO_MORE_DATA_IN(2) => slv_busy(2),\r
+ BUS_UNKNOWN_ADDR_IN(2) => '0',\r
+ -- OneWire master\r
+ BUS_READ_ENABLE_OUT(3) => slv_read(3),\r
+ BUS_WRITE_ENABLE_OUT(3) => slv_write(3),\r
+ BUS_DATA_OUT(3*32+31 downto 3*32) => slv_data_wr(3*32+31 downto 3*32),\r
+ BUS_DATA_IN(3*32+31 downto 3*32) => slv_data_rd(3*32+31 downto 3*32), \r
+ BUS_ADDR_OUT(3*16+15 downto 3*16) => slv_addr(3*16+15 downto 3*16),\r
+ BUS_TIMEOUT_OUT(3) => open,\r
+ BUS_DATAREADY_IN(3) => slv_ack(3),\r
+ BUS_WRITE_ACK_IN(3) => slv_ack(3),\r
+ BUS_NO_MORE_DATA_IN(3) => slv_busy(3),\r
+ BUS_UNKNOWN_ADDR_IN(3) => '0',\r
+ -- SPI control registers\r
+ BUS_READ_ENABLE_OUT(4) => slv_read(4),\r
+ BUS_WRITE_ENABLE_OUT(4) => slv_write(4),\r
+ BUS_DATA_OUT(4*32+31 downto 4*32) => slv_data_wr(4*32+31 downto 4*32),\r
+ BUS_DATA_IN(4*32+31 downto 4*32) => slv_data_rd(4*32+31 downto 4*32), \r
+ BUS_ADDR_OUT(4*16+15 downto 4*16) => slv_addr(4*16+15 downto 4*16),\r
+ BUS_TIMEOUT_OUT(4) => open,\r
+ BUS_DATAREADY_IN(4) => slv_ack(4),\r
+ BUS_WRITE_ACK_IN(4) => slv_ack(4),\r
+ BUS_NO_MORE_DATA_IN(4) => slv_busy(4),\r
+ BUS_UNKNOWN_ADDR_IN(4) => '0',\r
+ -- SPI data memory\r
+ BUS_READ_ENABLE_OUT(5) => slv_read(5),\r
+ BUS_WRITE_ENABLE_OUT(5) => slv_write(5),\r
+ BUS_DATA_OUT(5*32+31 downto 5*32) => slv_data_wr(5*32+31 downto 5*32),\r
+ BUS_DATA_IN(5*32+31 downto 5*32) => slv_data_rd(5*32+31 downto 5*32), \r
+ BUS_ADDR_OUT(5*16+15 downto 5*16) => slv_addr(5*16+15 downto 5*16),\r
+ BUS_TIMEOUT_OUT(5) => open,\r
+ BUS_DATAREADY_IN(5) => slv_ack(5),\r
+ BUS_WRITE_ACK_IN(5) => slv_ack(5),\r
+ BUS_NO_MORE_DATA_IN(5) => slv_busy(5),\r
+ BUS_UNKNOWN_ADDR_IN(5) => '0',\r
+ -- ADC 0 SPI control registers\r
+ BUS_READ_ENABLE_OUT(6) => slv_read(6),\r
+ BUS_WRITE_ENABLE_OUT(6) => slv_write(6),\r
+ BUS_DATA_OUT(6*32+31 downto 6*32) => slv_data_wr(6*32+31 downto 6*32),\r
+ BUS_DATA_IN(6*32+31 downto 6*32) => slv_data_rd(6*32+31 downto 6*32), \r
+ BUS_ADDR_OUT(6*16+15 downto 6*16) => open,\r
+ BUS_TIMEOUT_OUT(6) => open,\r
+ BUS_DATAREADY_IN(6) => slv_ack(6),\r
+ BUS_WRITE_ACK_IN(6) => slv_ack(6),\r
+ BUS_NO_MORE_DATA_IN(6) => slv_busy(6),\r
+ BUS_UNKNOWN_ADDR_IN(6) => '0',\r
+ -- ADC 1 SPI control registers\r
+ BUS_READ_ENABLE_OUT(7) => slv_read(7),\r
+ BUS_WRITE_ENABLE_OUT(7) => slv_write(7),\r
+ BUS_DATA_OUT(7*32+31 downto 7*32) => slv_data_wr(7*32+31 downto 7*32),\r
+ BUS_DATA_IN(7*32+31 downto 7*32) => slv_data_rd(7*32+31 downto 7*32), \r
+ BUS_ADDR_OUT(7*16+15 downto 7*16) => open,\r
+ BUS_TIMEOUT_OUT(7) => open,\r
+ BUS_DATAREADY_IN(7) => slv_ack(7),\r
+ BUS_WRITE_ACK_IN(7) => slv_ack(7),\r
+ BUS_NO_MORE_DATA_IN(7) => slv_busy(7),\r
+ BUS_UNKNOWN_ADDR_IN(7) => '0',\r
+ -- APV control / status registers\r
+ BUS_READ_ENABLE_OUT(8) => slv_read(8),\r
+ BUS_WRITE_ENABLE_OUT(8) => slv_write(8),\r
+ BUS_DATA_OUT(8*32+31 downto 8*32) => slv_data_wr(8*32+31 downto 8*32),\r
+ BUS_DATA_IN(8*32+31 downto 8*32) => slv_data_rd(8*32+31 downto 8*32), \r
+ BUS_ADDR_OUT(8*16+15 downto 8*16) => slv_addr(8*16+15 downto 8*16),\r
+ BUS_TIMEOUT_OUT(8) => open,\r
+ BUS_DATAREADY_IN(8) => slv_ack(8),\r
+ BUS_WRITE_ACK_IN(8) => slv_ack(8),\r
+ BUS_NO_MORE_DATA_IN(8) => slv_busy(8),\r
+ BUS_UNKNOWN_ADDR_IN(8) => '0',\r
+ -- ADC / PLL / trigger ctrl register\r
+ BUS_READ_ENABLE_OUT(11 downto 9) => slv_read(11 downto 9),\r
+ BUS_WRITE_ENABLE_OUT(11 downto 9) => slv_write(11 downto 9),\r
+ BUS_DATA_OUT(11*32+31 downto 9*32) => slv_data_wr(11*32+31 downto 9*32),\r
+ BUS_DATA_IN(11*32+31 downto 9*32) => slv_data_rd(11*32+31 downto 9*32), \r
+ BUS_ADDR_OUT(11*16+15 downto 9*16) => open,\r
+ BUS_TIMEOUT_OUT(11 downto 9) => open,\r
+ BUS_DATAREADY_IN(11 downto 9) => slv_ack(11 downto 9),\r
+ BUS_WRITE_ACK_IN(11 downto 9) => slv_ack(11 downto 9),\r
+ BUS_NO_MORE_DATA_IN(11 downto 9) => slv_busy(11 downto 9),\r
+ BUS_UNKNOWN_ADDR_IN(11 downto 9) => (others => '0'),\r
+ -- ADC0 snooper\r
+ BUS_READ_ENABLE_OUT(12) => slv_read(12),\r
+ BUS_WRITE_ENABLE_OUT(12) => slv_write(12),\r
+ BUS_DATA_OUT(12*32+31 downto 12*32) => slv_data_wr(12*32+31 downto 12*32),\r
+ BUS_DATA_IN(12*32+31 downto 12*32) => slv_data_rd(12*32+31 downto 12*32), \r
+ BUS_ADDR_OUT(12*16+15 downto 12*16) => slv_addr(12*16+15 downto 12*16),\r
+ BUS_TIMEOUT_OUT(12) => open,\r
+ BUS_DATAREADY_IN(12) => slv_ack(12),\r
+ BUS_WRITE_ACK_IN(12) => slv_ack(12),\r
+ BUS_NO_MORE_DATA_IN(12) => slv_busy(12),\r
+ BUS_UNKNOWN_ADDR_IN(12) => '0',\r
+ -- ADC1 snooper\r
+ BUS_READ_ENABLE_OUT(13) => slv_read(13),\r
+ BUS_WRITE_ENABLE_OUT(13) => slv_write(13),\r
+ BUS_DATA_OUT(13*32+31 downto 13*32) => slv_data_wr(13*32+31 downto 13*32),\r
+ BUS_DATA_IN(13*32+31 downto 13*32) => slv_data_rd(13*32+31 downto 13*32), \r
+ BUS_ADDR_OUT(13*16+15 downto 13*16) => slv_addr(13*16+15 downto 13*16),\r
+ BUS_TIMEOUT_OUT(13) => open,\r
+ BUS_DATAREADY_IN(13) => slv_ack(13),\r
+ BUS_WRITE_ACK_IN(13) => slv_ack(13),\r
+ BUS_NO_MORE_DATA_IN(13) => slv_busy(13),\r
+ BUS_UNKNOWN_ADDR_IN(13) => '0',\r
+ -- Test register\r
+ BUS_READ_ENABLE_OUT(14) => slv_read(14),\r
+ BUS_WRITE_ENABLE_OUT(14) => slv_write(14),\r
+ BUS_DATA_OUT(14*32+31 downto 14*32) => slv_data_wr(14*32+31 downto 14*32),\r
+ BUS_DATA_IN(14*32+31 downto 14*32) => slv_data_rd(14*32+31 downto 14*32), \r
+ BUS_ADDR_OUT(14*16+15 downto 14*16) => open,\r
+ BUS_TIMEOUT_OUT(14) => open,\r
+ BUS_DATAREADY_IN(14) => slv_ack(14),\r
+ BUS_WRITE_ACK_IN(14) => slv_ack(14),\r
+ BUS_NO_MORE_DATA_IN(14) => slv_busy(14),\r
+ BUS_UNKNOWN_ADDR_IN(14) => '0',\r
+ -- debug\r
+ STAT_DEBUG => stat\r
+ );\r
+\r
+\r
+------------------------------------------------------------------------------------\r
+-- pedestal memories (16x128 = 2048, 18bit)\r
+------------------------------------------------------------------------------------\r
+THE_PED_MEM: slv_ped_thr_mem\r
+port map( CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ -- Slave bus\r
+ SLV_ADDR_IN => slv_addr(0*16+10 downto 0*16),\r
+ SLV_READ_IN => slv_read(0),\r
+ SLV_WRITE_IN => slv_write(0),\r
+ SLV_ACK_OUT => slv_ack(0),\r
+ SLV_DATA_IN => slv_data_wr(0*32+31 downto 0*32),\r
+ SLV_DATA_OUT => slv_data_rd(0*32+31 downto 0*32),\r
+ -- backplane identifier\r
+ BACKPLANE_IN => backplane_in,\r
+ -- I/O to the backend\r
+ MEM_CLK_IN => clk_in,\r
+ MEM_ADDR_IN => ped_addr_in,\r
+ MEM_0_D_OUT => ped_data_0_out,\r
+ MEM_1_D_OUT => ped_data_1_out,\r
+ MEM_2_D_OUT => ped_data_2_out,\r
+ MEM_3_D_OUT => ped_data_3_out,\r
+ MEM_4_D_OUT => ped_data_4_out,\r
+ MEM_5_D_OUT => ped_data_5_out,\r
+ MEM_6_D_OUT => ped_data_6_out,\r
+ MEM_7_D_OUT => ped_data_7_out,\r
+ MEM_8_D_OUT => ped_data_8_out,\r
+ MEM_9_D_OUT => ped_data_9_out,\r
+ MEM_10_D_OUT => ped_data_10_out,\r
+ MEM_11_D_OUT => ped_data_11_out,\r
+ MEM_12_D_OUT => ped_data_12_out,\r
+ MEM_13_D_OUT => ped_data_13_out,\r
+ MEM_14_D_OUT => ped_data_14_out,\r
+ MEM_15_D_OUT => ped_data_15_out,\r
+ -- Status lines\r
+ STAT => open\r
+ );\r
+slv_busy(0) <= '0';\r
+\r
+------------------------------------------------------------------------------------\r
+-- threshold memories (16x128 = 2048, 18bit)\r
+------------------------------------------------------------------------------------\r
+THE_THR_MEM: slv_ped_thr_mem\r
+port map( CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ -- Slave bus\r
+ SLV_ADDR_IN => slv_addr(1*16+10 downto 1*16),\r
+ SLV_READ_IN => slv_read(1),\r
+ SLV_WRITE_IN => slv_write(1),\r
+ SLV_ACK_OUT => slv_ack(1),\r
+ SLV_DATA_IN => slv_data_wr(1*32+31 downto 1*32),\r
+ SLV_DATA_OUT => slv_data_rd(1*32+31 downto 1*32),\r
+ -- backplane identifier\r
+ BACKPLANE_IN => backplane_in,\r
+ -- I/O to the backend\r
+ MEM_CLK_IN => clk_in,\r
+ MEM_ADDR_IN => thr_addr_in,\r
+ MEM_0_D_OUT => thr_data_0_out,\r
+ MEM_1_D_OUT => thr_data_1_out,\r
+ MEM_2_D_OUT => thr_data_2_out,\r
+ MEM_3_D_OUT => thr_data_3_out,\r
+ MEM_4_D_OUT => thr_data_4_out,\r
+ MEM_5_D_OUT => thr_data_5_out,\r
+ MEM_6_D_OUT => thr_data_6_out,\r
+ MEM_7_D_OUT => thr_data_7_out,\r
+ MEM_8_D_OUT => thr_data_8_out,\r
+ MEM_9_D_OUT => thr_data_9_out,\r
+ MEM_10_D_OUT => thr_data_10_out,\r
+ MEM_11_D_OUT => thr_data_11_out,\r
+ MEM_12_D_OUT => thr_data_12_out,\r
+ MEM_13_D_OUT => thr_data_13_out,\r
+ MEM_14_D_OUT => thr_data_14_out,\r
+ MEM_15_D_OUT => thr_data_15_out,\r
+ -- Status lines\r
+ STAT => open\r
+ );\r
+slv_busy(1) <= '0';\r
+\r
+------------------------------------------------------------------------------------\r
+-- I2C master block for accessing APVs\r
+------------------------------------------------------------------------------------\r
+THE_I2C_MASTER: i2c_master\r
+port map( CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ -- Slave bus\r
+ SLV_READ_IN => slv_read(2),\r
+ SLV_WRITE_IN => slv_write(2),\r
+ SLV_BUSY_OUT => slv_busy(2),\r
+ SLV_ACK_OUT => slv_ack(2),\r
+ SLV_DATA_IN => slv_data_wr(2*32+31 downto 2*32),\r
+ SLV_DATA_OUT => slv_data_rd(2*32+31 downto 2*32),\r
+ -- I2C connections\r
+ SDA_IN => sda_in,\r
+ SDA_OUT => sda_out,\r
+ SCL_IN => scl_in,\r
+ SCL_OUT => scl_out,\r
+ -- Status lines\r
+ STAT => open\r
+ );\r
+\r
+------------------------------------------------------------------------------------\r
+-- 1Wire master including status memory\r
+------------------------------------------------------------------------------------\r
+THE_ONEWIRE_MEMORY: slv_onewire_memory\r
+port map( CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ -- Slave bus\r
+ SLV_ADDR_IN => slv_addr(3*16+5 downto 3*16),\r
+ SLV_READ_IN => slv_read(3),\r
+ SLV_WRITE_IN => slv_write(3),\r
+ SLV_ACK_OUT => slv_ack(3),\r
+ SLV_BUSY_OUT => open, \r
+ SLV_DATA_OUT => slv_data_rd(3*32+31 downto 3*32),\r
+ -- backplane identifier\r
+ BACKPLANE_IN => backplane_in,\r
+ -- 1Wire lines\r
+ ONEWIRE_START_IN => onewire_start_in, -- not used yet\r
+ ONEWIRE_INOUT => onewire_inout,\r
+ BP_ONEWIRE_INOUT => bp_onewire_inout,\r
+ -- Status lines\r
+ STAT => onewire_debug --open\r
+ );\r
+slv_busy(3) <= '0';\r
+\r
+------------------------------------------------------------------------------------\r
+-- SPI master\r
+------------------------------------------------------------------------------------\r
+THE_SPI_MASTER: spi_master\r
+port map( CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ -- Slave bus\r
+ BUS_READ_IN => slv_read(4),\r
+ BUS_WRITE_IN => slv_write(4),\r
+ BUS_BUSY_OUT => slv_busy(4),\r
+ BUS_ACK_OUT => slv_ack(4),\r
+ BUS_ADDR_IN => slv_addr(4*16+0 downto 4*16),\r
+ BUS_DATA_IN => slv_data_wr(4*32+31 downto 4*32),\r
+ BUS_DATA_OUT => slv_data_rd(4*32+31 downto 4*32),\r
+ -- SPI connections\r
+ SPI_CS_OUT => spi_cs,\r
+ SPI_SDI_IN => spi_sdi,\r
+ SPI_SDO_OUT => spi_sdo,\r
+ SPI_SCK_OUT => spi_sck,\r
+ -- BRAM for read/write data\r
+ BRAM_A_OUT => spi_bram_addr,\r
+ BRAM_WR_D_IN => spi_bram_wr_d,\r
+ BRAM_RD_D_OUT => spi_bram_rd_d,\r
+ BRAM_WE_OUT => spi_bram_we,\r
+ -- Status lines\r
+ STAT => spi_debug --open\r
+ );\r
+\r
+------------------------------------------------------------------------------------\r
+-- data memory for SPI accesses\r
+------------------------------------------------------------------------------------\r
+THE_SPI_MEMORY: spi_databus_memory\r
+port map( CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ -- Slave bus\r
+ BUS_ADDR_IN => slv_addr(5*16+5 downto 5*16),\r
+ BUS_READ_IN => slv_read(5),\r
+ BUS_WRITE_IN => slv_write(5),\r
+ BUS_ACK_OUT => slv_ack(5),\r
+ BUS_DATA_IN => slv_data_wr(5*32+31 downto 5*32),\r
+ BUS_DATA_OUT => slv_data_rd(5*32+31 downto 5*32),\r
+ -- state machine connections\r
+ BRAM_ADDR_IN => spi_bram_addr,\r
+ BRAM_WR_D_OUT => spi_bram_wr_d,\r
+ BRAM_RD_D_IN => spi_bram_rd_d,\r
+ BRAM_WE_IN => spi_bram_we, \r
+ -- Status lines\r
+ STAT => open\r
+ );\r
+slv_busy(5) <= '0';\r
+\r
+------------------------------------------------------------------------------------\r
+-- ADC0 SPI master\r
+------------------------------------------------------------------------------------\r
+THE_SPI_ADC0_MASTER: spi_adc_master\r
+generic map( RESET_VALUE_CTRL => x"60" )\r
+port map( CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ -- Slave bus\r
+ SLV_READ_IN => slv_read(6),\r
+ SLV_WRITE_IN => slv_write(6),\r
+ SLV_BUSY_OUT => slv_busy(6),\r
+ SLV_ACK_OUT => slv_ack(6),\r
+ SLV_DATA_IN => slv_data_wr(6*32+31 downto 6*32),\r
+ SLV_DATA_OUT => slv_data_rd(6*32+31 downto 6*32),\r
+ -- SPI connections\r
+ SPI_CS_OUT => spi_adc0_cs_out,\r
+ SPI_SDO_OUT => spi_adc0_sdo_out,\r
+ SPI_SCK_OUT => spi_adc0_sck_out,\r
+ -- ADC connections\r
+ ADC_LOCKED_IN => adc0_pll_locked_in,\r
+ ADC_PD_OUT => adc0_pd_out,\r
+ ADC_RST_OUT => adc0_rst_out,\r
+ ADC_DEL_OUT => adc0_del_out,\r
+ -- APV connections\r
+ APV_RST_OUT => apv0_rst_out,\r
+ -- Status lines\r
+ STAT => open\r
+ );\r
+\r
+------------------------------------------------------------------------------------\r
+-- ADC1 SPI master\r
+------------------------------------------------------------------------------------\r
+THE_SPI_ADC1_MASTER: spi_adc_master\r
+generic map( RESET_VALUE_CTRL => x"60" )\r
+port map( CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ -- Slave bus\r
+ SLV_READ_IN => slv_read(7),\r
+ SLV_WRITE_IN => slv_write(7),\r
+ SLV_BUSY_OUT => slv_busy(7),\r
+ SLV_ACK_OUT => slv_ack(7),\r
+ SLV_DATA_IN => slv_data_wr(7*32+31 downto 7*32),\r
+ SLV_DATA_OUT => slv_data_rd(7*32+31 downto 7*32),\r
+ -- SPI connections\r
+ SPI_CS_OUT => spi_adc1_cs_out,\r
+ SPI_SDO_OUT => spi_adc1_sdo_out,\r
+ SPI_SCK_OUT => spi_adc1_sck_out,\r
+ -- ADC connections\r
+ ADC_LOCKED_IN => adc1_pll_locked_in,\r
+ ADC_PD_OUT => adc1_pd_out,\r
+ ADC_RST_OUT => adc1_rst_out,\r
+ ADC_DEL_OUT => adc1_del_out,\r
+ -- APV connections\r
+ APV_RST_OUT => apv1_rst_out,\r
+ -- Status lines\r
+ STAT => open\r
+ );\r
+\r
+------------------------------------------------------------------------------------\r
+-- APV control / status registers\r
+------------------------------------------------------------------------------------\r
+THE_SLV_REGISTER_BANK: slv_register_bank\r
+generic map( RESET_VALUE => x"0001" )\r
+port map( CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ -- Slave bus\r
+ SLV_ADDR_IN => slv_addr(8*16+3 downto 8*16),\r
+ SLV_READ_IN => slv_read(8),\r
+ SLV_WRITE_IN => slv_write(8),\r
+ SLV_ACK_OUT => slv_ack(8),\r
+ SLV_DATA_IN => slv_data_wr(8*32+31 downto 8*32),\r
+ SLV_DATA_OUT => slv_data_rd(8*32+31 downto 8*32),\r
+ -- I/O to the backend\r
+ BACKPLANE_IN => backplane_in,\r
+ CTRL_0_OUT => ctrl_0_out,\r
+ CTRL_1_OUT => ctrl_1_out,\r
+ CTRL_2_OUT => ctrl_2_out,\r
+ CTRL_3_OUT => ctrl_3_out,\r
+ CTRL_4_OUT => ctrl_4_out,\r
+ CTRL_5_OUT => ctrl_5_out,\r
+ CTRL_6_OUT => ctrl_6_out,\r
+ CTRL_7_OUT => ctrl_7_out,\r
+ CTRL_8_OUT => ctrl_8_out,\r
+ CTRL_9_OUT => ctrl_9_out,\r
+ CTRL_10_OUT => ctrl_10_out,\r
+ CTRL_11_OUT => ctrl_11_out,\r
+ CTRL_12_OUT => ctrl_12_out,\r
+ CTRL_13_OUT => ctrl_13_out,\r
+ CTRL_14_OUT => ctrl_14_out,\r
+ CTRL_15_OUT => ctrl_15_out,\r
+ STAT_0_IN => stat_0_in,\r
+ STAT_1_IN => stat_1_in,\r
+ STAT_2_IN => stat_2_in,\r
+ STAT_3_IN => stat_3_in,\r
+ STAT_4_IN => stat_4_in,\r
+ STAT_5_IN => stat_5_in,\r
+ STAT_6_IN => stat_6_in,\r
+ STAT_7_IN => stat_7_in,\r
+ STAT_8_IN => stat_8_in,\r
+ STAT_9_IN => stat_9_in,\r
+ STAT_10_IN => stat_10_in,\r
+ STAT_11_IN => stat_11_in,\r
+ STAT_12_IN => stat_12_in,\r
+ STAT_13_IN => stat_13_in,\r
+ STAT_14_IN => stat_14_in,\r
+ STAT_15_IN => stat_15_in,\r
+ -- Status lines\r
+ STAT => open\r
+ );\r
+slv_busy(8) <= '0';\r
+\r
+------------------------------------------------------------------------------------\r
+-- ADC level register\r
+------------------------------------------------------------------------------------\r
+THE_ADC_LVL_REG: slv_register\r
+generic map( RESET_VALUE => x"d0_20_78_88" )\r
+port map( CLK_IN => clk_in,\r
+ RESET_IN => reset_in, -- general reset\r
+ BUSY_IN => '0',\r
+ -- Slave bus\r
+ SLV_READ_IN => slv_read(9),\r
+ SLV_WRITE_IN => slv_write(9),\r
+ SLV_BUSY_OUT => slv_busy(9),\r
+ SLV_ACK_OUT => slv_ack(9),\r
+ SLV_DATA_IN => slv_data_wr(9*32+31 downto 9*32),\r
+ SLV_DATA_OUT => slv_data_rd(9*32+31 downto 9*32),\r
+ -- I/O to the backend\r
+ REG_DATA_IN => ctrl_lvl,\r
+ REG_DATA_OUT => ctrl_lvl,\r
+ -- Status lines\r
+ STAT => open\r
+ );\r
+\r
+------------------------------------------------------------------------------------\r
+-- trigger control register\r
+------------------------------------------------------------------------------------\r
+THE_TRG_CTRL_REG: slv_register\r
+generic map( RESET_VALUE => x"10_10_10_10" )\r
+port map( CLK_IN => clk_in,\r
+ RESET_IN => reset_in, -- general reset\r
+ BUSY_IN => '0',\r
+ -- Slave bus\r
+ SLV_READ_IN => slv_read(10),\r
+ SLV_WRITE_IN => slv_write(10),\r
+ SLV_BUSY_OUT => slv_busy(10),\r
+ SLV_ACK_OUT => slv_ack(10),\r
+ SLV_DATA_IN => slv_data_wr(10*32+31 downto 10*32),\r
+ SLV_DATA_OUT => slv_data_rd(10*32+31 downto 10*32),\r
+ -- I/O to the backend\r
+ REG_DATA_IN => ctrl_trg,\r
+ REG_DATA_OUT => ctrl_trg,\r
+ -- Status lines\r
+ STAT => open\r
+ );\r
+\r
+------------------------------------------------------------------------------------\r
+-- PLL control register\r
+------------------------------------------------------------------------------------\r
+THE_PLL_CTRL_REG: slv_half_register\r
+generic map( RESET_VALUE => x"00_02" )\r
+port map( CLK_IN => clk_in,\r
+ RESET_IN => reset_in, -- general reset\r
+ -- Slave bus\r
+ SLV_READ_IN => slv_read(11),\r
+ SLV_WRITE_IN => slv_write(11),\r
+ SLV_ACK_OUT => slv_ack(11),\r
+ SLV_DATA_IN => slv_data_wr(11*32+31 downto 11*32),\r
+ SLV_DATA_OUT => slv_data_rd(11*32+31 downto 11*32),\r
+ -- I/O to the backend\r
+ STATUS_REG_IN => status_pll_in,\r
+ CTRL_REG_OUT => ctrl_pll,\r
+ -- Status lines\r
+ STAT => open\r
+ );\r
+slv_busy(11) <= '0';\r
+\r
+------------------------------------------------------------------------------------\r
+-- ADC0 snooper\r
+------------------------------------------------------------------------------------\r
+THE_ADC0_SNOOPER: slv_adc_snoop\r
+port map( CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ -- Slave bus\r
+ SLV_ADDR_IN => slv_addr(12*16+9 downto 12*16),\r
+ SLV_READ_IN => slv_read(12),\r
+ SLV_WRITE_IN => slv_write(12),\r
+ SLV_ACK_OUT => slv_ack(12),\r
+ SLV_DATA_IN => slv_data_wr(12*32+31 downto 12*32),\r
+ SLV_DATA_OUT => slv_data_rd(12*32+31 downto 12*32),\r
+ -- I/O to the backend\r
+ ADC_SEL_OUT => adc0_sel_out,\r
+ ADC_CLK_IN => adc0_clk_in,\r
+ ADC_DATA_IN => adc0_data_in,\r
+ -- Status lines\r
+ STAT => open\r
+ );\r
+slv_busy(12) <= '0';\r
+\r
+\r
+------------------------------------------------------------------------------------\r
+-- ADC1 snooper\r
+------------------------------------------------------------------------------------\r
+THE_ADC1_SNOOPER: slv_adc_snoop\r
+port map( CLK_IN => clk_in,\r
+ RESET_IN => reset_in,\r
+ -- Slave bus\r
+ SLV_ADDR_IN => slv_addr(13*16+9 downto 13*16),\r
+ SLV_READ_IN => slv_read(13),\r
+ SLV_WRITE_IN => slv_write(13),\r
+ SLV_ACK_OUT => slv_ack(13),\r
+ SLV_DATA_IN => slv_data_wr(13*32+31 downto 13*32),\r
+ SLV_DATA_OUT => slv_data_rd(13*32+31 downto 13*32),\r
+ -- I/O to the backend\r
+ ADC_SEL_OUT => adc1_sel_out,\r
+ ADC_CLK_IN => adc1_clk_in,\r
+ ADC_DATA_IN => adc1_data_in,\r
+ -- Status lines\r
+ STAT => open\r
+ );\r
+slv_busy(13) <= '0';\r
+\r
+ \r
+------------------------------------------------------------------------------------\r
+-- test register (normal)\r
+------------------------------------------------------------------------------------\r
+THE_GOOD_TEST_REG: slv_register\r
+generic map( RESET_VALUE => x"dead_beef" )\r
+port map( CLK_IN => clk_in,\r
+ RESET_IN => reset_in, -- general reset\r
+ BUSY_IN => '0',\r
+ -- Slave bus\r
+ SLV_READ_IN => slv_read(14),\r
+ SLV_WRITE_IN => slv_write(14),\r
+ SLV_BUSY_OUT => slv_busy(14),\r
+ SLV_ACK_OUT => slv_ack(14),\r
+ SLV_DATA_IN => slv_data_wr(14*32+31 downto 14*32),\r
+ SLV_DATA_OUT => slv_data_rd(14*32+31 downto 14*32),\r
+ -- I/O to the backend\r
+ REG_DATA_IN => test_reg_in, --x"5a3c_87e1",\r
+ REG_DATA_OUT => test_reg_out,\r
+ -- Status lines\r
+ STAT => open\r
+ );\r
+\r
+\r
+\r
+\r
+-- unusable pins\r
+debug(63 downto 43) <= (others => '0');\r
+-- connected pins\r
+debug(42 downto 0) <= (others => '0');\r
+\r
+-- input signals\r
+spi_sdi <= spi_sdi_in;\r
+\r
+-- Output signals\r
+spi_cs_out <= spi_cs;\r
+spi_sck_out <= spi_sck;\r
+spi_sdo_out <= spi_sdo;\r
+\r
+ctrl_lvl_out <= ctrl_lvl;\r
+ctrl_trg_out <= ctrl_trg;\r
+ctrl_pll_out <= ctrl_pll;\r
+\r
+debug_out <= debug;\r
+\r
+end Behavioral;\r
--- /dev/null
+library IEEE;\r
+use IEEE.STD_LOGIC_1164.ALL;\r
+use IEEE.STD_LOGIC_ARITH.ALL;\r
+use IEEE.STD_LOGIC_UNSIGNED.ALL;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+\r
+entity slv_adc_la is\r
+port( CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_ADDR_IN : in std_logic_vector(9 downto 0);\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- I/O to the backend\r
+ ADC_SEL_OUT : out std_logic_vector(2 downto 0); -- selects the ADC channel to snoop from\r
+ ADC_CLK_IN : in std_logic; -- ADC reconstructed clock\r
+ ADC_DATA_IN : in std_logic_vector(11 downto 0); -- ADC selected channel data\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+ );\r
+end entity;\r
+\r
+architecture Behavioral of slv_adc_la is\r
+\r
+-- Signals\r
+\r
+ type STATES is (SLEEP,RD_RDY,RD_DEL0,RD_DEL1,WR_DEL0,WR_DEL1,WR_RDY,RD_ACK,WR_ACK,DONE);\r
+ signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+ -- slave bus signals\r
+ signal slv_ack_x : std_logic;\r
+ signal slv_ack : std_logic;\r
+ signal store_wr_x : std_logic;\r
+ signal store_wr : std_logic;\r
+ signal store_rd_x : std_logic;\r
+ signal store_rd : std_logic;\r
+\r
+ signal arm_x : std_logic;\r
+ signal trg_x : std_logic;\r
+\r
+ signal ctrl_reg : std_logic_vector(15 downto 0);\r
+ signal status_reg : std_logic_vector(31 downto 0);\r
+\r
+ signal rd_data : std_logic_vector(15 downto 0);\r
+\r
+ -- 40MHz clock domain!!!\r
+ signal wr_data : std_logic_vector(15 downto 0);\r
+ signal wr_addr : std_logic_vector(9 downto 0);\r
+ signal wr_we : std_logic;\r
+ signal reset_40mhz : std_logic;\r
+ signal arm_40mhz : std_logic;\r
+ signal trg_40mhz : std_logic;\r
+\r
+ signal sm_clear : std_logic;\r
+ signal sm_run : std_logic;\r
+ signal sm_sample : std_logic;\r
+ signal sm_ready : std_logic;\r
+ signal sm_last : std_logic;\r
+ signal sm_bsm : std_logic_vector(3 downto 0);\r
+ \r
+begin\r
+\r
+-- Fake\r
+stat(31 downto 25) <= (others => '0');\r
+stat(24) <= sm_last;\r
+stat(23) <= sm_ready;\r
+stat(22) <= sm_sample;\r
+stat(21) <= sm_run;\r
+stat(20) <= sm_clear;\r
+stat(19 downto 16) <= sm_bsm;\r
+stat(15 downto 0) <= ctrl_reg;\r
+\r
+---------------------------------------------------------\r
+-- Statemachine --\r
+---------------------------------------------------------\r
+-- State memory process\r
+STATE_MEM: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ CURRENT_STATE <= SLEEP;\r
+ slv_ack <= '0';\r
+ store_wr <= '0';\r
+ store_rd <= '0';\r
+ else\r
+ CURRENT_STATE <= NEXT_STATE;\r
+ slv_ack <= slv_ack_x;\r
+ store_wr <= store_wr_x;\r
+ store_rd <= store_rd_x;\r
+ end if;\r
+ end if;\r
+end process STATE_MEM;\r
+\r
+-- Transition matrix\r
+TRANSFORM: process( CURRENT_STATE, slv_read_in, slv_write_in )\r
+begin\r
+ NEXT_STATE <= SLEEP;\r
+ slv_ack_x <= '0';\r
+ store_wr_x <= '0';\r
+ store_rd_x <= '0';\r
+ case CURRENT_STATE is\r
+ when SLEEP => if ( slv_read_in = '1' ) then\r
+ NEXT_STATE <= RD_DEL0;\r
+ store_rd_x <= '1';\r
+ elsif( slv_write_in = '1' ) then\r
+ NEXT_STATE <= WR_DEL0;\r
+ store_wr_x <= '1';\r
+ else \r
+ NEXT_STATE <= SLEEP;\r
+ end if;\r
+ when RD_DEL0 => NEXT_STATE <= RD_DEL1;\r
+ when RD_DEL1 => NEXT_STATE <= RD_RDY;\r
+ when RD_RDY => NEXT_STATE <= RD_ACK;\r
+ when RD_ACK => if( slv_read_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ slv_ack_x <= '1';\r
+ else\r
+ NEXT_STATE <= RD_ACK;\r
+ slv_ack_x <= '1';\r
+ end if;\r
+ when WR_DEL0 => NEXT_STATE <= WR_DEL1;\r
+ when WR_DEL1 => NEXT_STATE <= WR_RDY;\r
+ when WR_RDY => NEXT_STATE <= WR_ACK;\r
+ when WR_ACK => if( slv_write_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ slv_ack_x <= '1';\r
+ else\r
+ NEXT_STATE <= WR_ACK;\r
+ slv_ack_x <= '1';\r
+ end if;\r
+ when DONE => NEXT_STATE <= SLEEP;\r
+ \r
+ when others => NEXT_STATE <= SLEEP;\r
+ end case;\r
+end process TRANSFORM;\r
+\r
+---------------------------------------------------------\r
+-- data handling --\r
+---------------------------------------------------------\r
+\r
+THE_RST_SYNC: state_sync\r
+port map( STATE_A_IN => reset_in,\r
+ CLK_B_IN => adc_clk_in,\r
+ RESET_B_IN => '0',\r
+ STATE_B_OUT => reset_40mhz\r
+ );\r
+\r
+arm_x <= slv_data_in(30) and store_wr;\r
+\r
+THE_ARM_PULSE_SYNC: pulse_sync\r
+port map( CLK_A_IN => clk_in,\r
+ RESET_A_IN => reset_in,\r
+ PULSE_A_IN => arm_x,\r
+ CLK_B_IN => adc_clk_in,\r
+ RESET_B_IN => reset_40mhz,\r
+ PULSE_B_OUT => arm_40mhz\r
+ );\r
+\r
+trg_x <= slv_data_in(31) and store_wr;\r
+\r
+THE_TRG_PULSE_SYNC: pulse_sync\r
+port map( CLK_A_IN => clk_in,\r
+ RESET_A_IN => reset_in,\r
+ PULSE_A_IN => trg_x,\r
+ CLK_B_IN => adc_clk_in,\r
+ RESET_B_IN => reset_40mhz,\r
+ PULSE_B_OUT => trg_40mhz\r
+ );\r
+\r
+THE_LOGIC_ANALYZER: logic_analyzer\r
+port map( CLK_IN => adc_clk_in,\r
+ RESET_IN => reset_40mhz,\r
+ -- control signals\r
+ ARM_IN => arm_40mhz, -- BUGBUGBUG\r
+ TRG_IN => trg_40mhz, -- BUGBUGBUG\r
+ MAX_SAMPLE_IN => ctrl_reg(9 downto 0),\r
+ -- status signals\r
+ SM_ADDR_OUT => wr_addr,\r
+ SM_CE_OUT => open,\r
+ SM_WE_OUT => wr_we,\r
+ CLEAR_OUT => sm_clear,\r
+ RUN_OUT => sm_run,\r
+ SAMPLE_OUT => sm_sample,\r
+ READY_OUT => sm_ready,\r
+ LAST_OUT => sm_last,\r
+ -- Status lines\r
+ BSM_OUT => sm_bsm,\r
+ STAT => open\r
+ );\r
+\r
+wr_data(15) <= sm_clear;\r
+wr_data(14) <= sm_run;\r
+wr_data(13) <= sm_sample;\r
+wr_data(12) <= sm_last;\r
+wr_data(11 downto 0) <= adc_data_in;\r
+\r
+THE_ADC0_SNOOP_MEM: adc_snoop_mem\r
+port map( WRADDRESS => wr_addr,\r
+ DATA => wr_data,\r
+ WE => wr_we,\r
+ WRCLOCK => adc_clk_in,\r
+ WRCLOCKEN => '1',\r
+ RDADDRESS => slv_addr_in, \r
+ RDCLOCK => clk_in,\r
+ RDCLOCKEN => '1',\r
+ RESET => reset_in,\r
+ Q => rd_data\r
+ );\r
+\r
+-- register write\r
+THE_WRITE_REG_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( reset_in = '1' ) then\r
+ ctrl_reg <= (others => '0');\r
+ elsif( store_wr = '1' ) then\r
+ ctrl_reg <= slv_data_in(15 downto 0);\r
+ end if;\r
+ end if;\r
+end process THE_WRITE_REG_PROC;\r
+\r
+-- register read\r
+THE_READ_REG_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( reset_in = '1' ) then\r
+ status_reg <= (others => '0');\r
+ elsif( store_rd = '1' ) then\r
+ status_reg <= b"0000_00" & wr_addr & rd_data;\r
+ end if;\r
+ end if;\r
+end process THE_READ_REG_PROC;\r
+\r
+-- output signals\r
+slv_ack_out <= slv_ack;\r
+slv_data_out <= status_reg;\r
+\r
+adc_sel_out <= ctrl_reg(14 downto 12);\r
+\r
+end Behavioral;\r
--- /dev/null
+library IEEE;\r
+use IEEE.STD_LOGIC_1164.ALL;\r
+use IEEE.STD_LOGIC_ARITH.ALL;\r
+use IEEE.STD_LOGIC_UNSIGNED.ALL;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+\r
+entity slv_adc_snoop is\r
+port( CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_ADDR_IN : in std_logic_vector(9 downto 0);\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- I/O to the backend\r
+ ADC_SEL_OUT : out std_logic_vector(2 downto 0); -- selects the ADC channel to snoop from\r
+ ADC_CLK_IN : in std_logic; -- ADC reconstructed clock\r
+ ADC_DATA_IN : in std_logic_vector(11 downto 0); -- ADC selected channel data\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+ );\r
+end entity;\r
+\r
+architecture Behavioral of slv_adc_snoop is\r
+\r
+-- Signals\r
+\r
+ type STATES is (SLEEP,RD_RDY,RD_DEL0,RD_DEL1,WR_DEL0,WR_DEL1,WR_RDY,RD_ACK,WR_ACK,DONE);\r
+ signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+ -- slave bus signals\r
+ signal slv_ack_x : std_logic;\r
+ signal slv_ack : std_logic;\r
+ signal store_wr_x : std_logic;\r
+ signal store_wr : std_logic;\r
+ signal store_rd_x : std_logic;\r
+ signal store_rd : std_logic;\r
+\r
+ signal ctrl_reg : std_logic_vector(15 downto 0);\r
+ signal status_reg : std_logic_vector(31 downto 0);\r
+\r
+ signal rd_data : std_logic_vector(15 downto 0);\r
+\r
+ -- 40MHz clock domain!!!\r
+ signal wr_data : std_logic_vector(15 downto 0);\r
+ signal wr_ctr : std_logic_vector(9 downto 0);\r
+ signal rst_wr_ctr : std_logic;\r
+ signal ce_wr_ctr : std_logic;\r
+ signal reset : std_logic;\r
+\r
+begin\r
+\r
+-- Fake\r
+stat(31 downto 18) <= (others => '0');\r
+stat(17) <= rst_wr_ctr;\r
+stat(16) <= ce_wr_ctr;\r
+stat(15 downto 0) <= ctrl_reg;\r
+ \r
+---------------------------------------------------------\r
+-- Statemachine --\r
+---------------------------------------------------------\r
+-- State memory process\r
+STATE_MEM: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ CURRENT_STATE <= SLEEP;\r
+ slv_ack <= '0';\r
+ store_wr <= '0';\r
+ store_rd <= '0';\r
+ else\r
+ CURRENT_STATE <= NEXT_STATE;\r
+ slv_ack <= slv_ack_x;\r
+ store_wr <= store_wr_x;\r
+ store_rd <= store_rd_x;\r
+ end if;\r
+ end if;\r
+end process STATE_MEM;\r
+\r
+-- Transition matrix\r
+TRANSFORM: process( CURRENT_STATE, slv_read_in, slv_write_in )\r
+begin\r
+ NEXT_STATE <= SLEEP;\r
+ slv_ack_x <= '0';\r
+ store_wr_x <= '0';\r
+ store_rd_x <= '0';\r
+ case CURRENT_STATE is\r
+ when SLEEP => if ( slv_read_in = '1' ) then\r
+ NEXT_STATE <= RD_DEL0;\r
+ store_rd_x <= '1';\r
+ elsif( slv_write_in = '1' ) then\r
+ NEXT_STATE <= WR_DEL0;\r
+ store_wr_x <= '1';\r
+ else \r
+ NEXT_STATE <= SLEEP;\r
+ end if;\r
+ when RD_DEL0 => NEXT_STATE <= RD_DEL1;\r
+ when RD_DEL1 => NEXT_STATE <= RD_RDY;\r
+ when RD_RDY => NEXT_STATE <= RD_ACK;\r
+ when RD_ACK => if( slv_read_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ slv_ack_x <= '1';\r
+ else\r
+ NEXT_STATE <= RD_ACK;\r
+ slv_ack_x <= '1';\r
+ end if;\r
+ when WR_DEL0 => NEXT_STATE <= WR_DEL1;\r
+ when WR_DEL1 => NEXT_STATE <= WR_RDY;\r
+ when WR_RDY => NEXT_STATE <= WR_ACK;\r
+ when WR_ACK => if( slv_write_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ slv_ack_x <= '1';\r
+ else\r
+ NEXT_STATE <= WR_ACK;\r
+ slv_ack_x <= '1';\r
+ end if;\r
+ when DONE => NEXT_STATE <= SLEEP;\r
+ \r
+ when others => NEXT_STATE <= SLEEP;\r
+ end case;\r
+end process TRANSFORM;\r
+\r
+---------------------------------------------------------\r
+-- data handling --\r
+---------------------------------------------------------\r
+\r
+THE_RESET_SYNC: state_sync\r
+port map( STATE_A_IN => reset_in,\r
+ CLK_B_IN => adc_clk_in,\r
+ RESET_B_IN => '0',\r
+ STATE_B_OUT => reset\r
+ );\r
+\r
+THE_RST_SYNC: state_sync\r
+port map( STATE_A_IN => ctrl_reg(15),\r
+ CLK_B_IN => adc_clk_in,\r
+ RESET_B_IN => reset,\r
+ STATE_B_OUT => rst_wr_ctr\r
+ );\r
+\r
+THE_CE_SYNC: state_sync\r
+port map( STATE_A_IN => ctrl_reg(14),\r
+ CLK_B_IN => adc_clk_in,\r
+ RESET_B_IN => reset,\r
+ STATE_B_OUT => ce_wr_ctr\r
+ );\r
+\r
+THE_WR_CTR_PROC: process( adc_clk_in )\r
+begin\r
+ if( rising_edge(adc_clk_in) ) then\r
+ if ( (reset = '1') or (rst_wr_ctr = '1') ) then\r
+ wr_ctr <= (others => '0');\r
+ elsif( ce_wr_ctr = '1' ) then\r
+ wr_ctr <= wr_ctr + 1;\r
+ end if;\r
+ end if;\r
+end process THE_WR_CTR_PROC;\r
+\r
+wr_data <= x"0" & adc_data_in;\r
+\r
+THE_ADC0_SNOOP_MEM: adc_snoop_mem\r
+port map( WRADDRESS => wr_ctr,\r
+ DATA => wr_data,\r
+ WE => ce_wr_ctr,\r
+ WRCLOCK => adc_clk_in,\r
+ WRCLOCKEN => '1',\r
+ RDADDRESS => slv_addr_in, \r
+ RDCLOCK => clk_in,\r
+ RDCLOCKEN => '1',\r
+ RESET => reset_in,\r
+ Q => rd_data\r
+ );\r
+\r
+-- register write\r
+THE_WRITE_REG_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( reset_in = '1' ) then\r
+ ctrl_reg <= (others => '0');\r
+ elsif( store_wr = '1' ) then\r
+ ctrl_reg <= slv_data_in(15 downto 0);\r
+ end if;\r
+ end if;\r
+end process THE_WRITE_REG_PROC;\r
+\r
+-- register read\r
+THE_READ_REG_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( reset_in = '1' ) then\r
+ status_reg <= (others => '0');\r
+ elsif( store_rd = '1' ) then\r
+ status_reg <= b"0000_00" & wr_ctr & rd_data;\r
+ end if;\r
+ end if;\r
+end process THE_READ_REG_PROC;\r
+\r
+-- output signals\r
+slv_ack_out <= slv_ack;\r
+slv_data_out <= status_reg;\r
+\r
+adc_sel_out <= ctrl_reg(2 downto 0);\r
+\r
+end Behavioral;\r
--- /dev/null
+library IEEE;\r
+use IEEE.STD_LOGIC_1164.ALL;\r
+use IEEE.STD_LOGIC_ARITH.ALL;\r
+use IEEE.STD_LOGIC_UNSIGNED.ALL;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+\r
+entity slv_half_register is\r
+generic( RESET_VALUE : std_logic_vector(15 downto 0) := x"0000" );\r
+port( CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- I/O to the backend\r
+ STATUS_REG_IN : in std_logic_vector(15 downto 0);\r
+ CTRL_REG_OUT : out std_logic_vector(15 downto 0);\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+ );\r
+end entity;\r
+\r
+architecture Behavioral of slv_half_register is\r
+\r
+-- Signals\r
+\r
+ type STATES is (SLEEP,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE);\r
+ signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+ -- slave bus signals\r
+ signal slv_ack_x : std_logic;\r
+ signal slv_ack : std_logic;\r
+ signal store_wr_x : std_logic;\r
+ signal store_wr : std_logic;\r
+ signal store_rd_x : std_logic;\r
+ signal store_rd : std_logic;\r
+\r
+ signal ctrl_reg : std_logic_vector(15 downto 0);\r
+\r
+ signal reg_slv_data_out : std_logic_vector(31 downto 0); -- read back data\r
+\r
+begin\r
+\r
+-- Fake\r
+stat <= (others => '0');\r
+\r
+---------------------------------------------------------\r
+-- Statemachine --\r
+---------------------------------------------------------\r
+-- State memory process\r
+STATE_MEM: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ CURRENT_STATE <= SLEEP;\r
+ slv_ack <= '0';\r
+ store_wr <= '0';\r
+ store_rd <= '0';\r
+ else\r
+ CURRENT_STATE <= NEXT_STATE;\r
+ slv_ack <= slv_ack_x;\r
+ store_wr <= store_wr_x;\r
+ store_rd <= store_rd_x;\r
+ end if;\r
+ end if;\r
+end process STATE_MEM;\r
+\r
+-- Transition matrix\r
+TRANSFORM: process(CURRENT_STATE, slv_read_in, slv_write_in )\r
+begin\r
+ NEXT_STATE <= SLEEP;\r
+ slv_ack_x <= '0';\r
+ store_wr_x <= '0';\r
+ store_rd_x <= '0';\r
+ case CURRENT_STATE is\r
+ when SLEEP => if ( slv_read_in = '1' ) then\r
+ NEXT_STATE <= RD_RDY;\r
+ store_rd_x <= '1';\r
+ elsif( slv_write_in = '1' ) then\r
+ NEXT_STATE <= WR_RDY;\r
+ store_wr_x <= '1';\r
+ else \r
+ NEXT_STATE <= SLEEP;\r
+ end if;\r
+ when RD_RDY => NEXT_STATE <= RD_ACK;\r
+ slv_ack_x <= '1';\r
+ when WR_RDY => NEXT_STATE <= WR_ACK;\r
+ slv_ack_x <= '1';\r
+ when RD_ACK => if( slv_read_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ else\r
+ NEXT_STATE <= RD_ACK;\r
+ slv_ack_x <= '1';\r
+ end if;\r
+ when WR_ACK => if( slv_write_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ else\r
+ NEXT_STATE <= WR_ACK;\r
+ slv_ack_x <= '1';\r
+ end if;\r
+ when DONE => NEXT_STATE <= SLEEP;\r
+ \r
+ when others => NEXT_STATE <= SLEEP;\r
+ end case;\r
+end process TRANSFORM;\r
+\r
+---------------------------------------------------------\r
+-- data handling --\r
+---------------------------------------------------------\r
+\r
+-- register write\r
+THE_WRITE_REG_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( reset_in = '1' ) then\r
+ ctrl_reg <= (others => '0');\r
+ elsif( store_wr = '1' ) then\r
+ ctrl_reg <= slv_data_in(15 downto 0);\r
+ end if;\r
+ end if;\r
+end process THE_WRITE_REG_PROC;\r
+\r
+-- register read\r
+THE_READ_REG_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( reset_in = '1' ) then\r
+ reg_slv_data_out <= (others => '0');\r
+ elsif( store_rd = '1' ) then\r
+ reg_slv_data_out <= status_reg_in & ctrl_reg;\r
+ end if;\r
+ end if;\r
+end process THE_READ_REG_PROC;\r
+\r
+-- output signals\r
+slv_ack_out <= slv_ack;\r
+slv_data_out <= reg_slv_data_out;\r
+\r
+---------------------------------------------------------\r
+-- signals to backend --\r
+---------------------------------------------------------\r
+\r
+ctrl_reg_out <= ctrl_reg;\r
+\r
+end Behavioral;\r
--- /dev/null
+library IEEE;\r
+use IEEE.STD_LOGIC_1164.ALL;\r
+use IEEE.STD_LOGIC_ARITH.ALL;\r
+use IEEE.STD_LOGIC_UNSIGNED.ALL;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+entity slv_memory_true is\r
+port( CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ BUSY_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_ADDR_IN : in std_logic_vector(8 downto 0);\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_BUSY_OUT : out std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- I/O to the backend\r
+ MEM_CLK_IN : in std_logic;\r
+ MEM_ADDR_IN : in std_logic_vector(7 downto 0);\r
+ MEM_DATA_OUT : out std_logic_vector(17 downto 0);\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+ );\r
+end entity;\r
+\r
+architecture Behavioral of slv_memory_true is\r
+\r
+\r
+-- Signals\r
+ type STATES is (SLEEP,RD_BSY,WR_BSY,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE);\r
+ signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+ -- slave bus signals\r
+ signal slv_busy_x : std_logic;\r
+ signal slv_busy : std_logic;\r
+ signal slv_ack_x : std_logic;\r
+ signal slv_ack : std_logic;\r
+ signal store_wr_x : std_logic;\r
+ signal store_wr : std_logic;\r
+ signal store_rd_x : std_logic;\r
+ signal store_rd : std_logic;\r
+\r
+ signal wr_addr : std_logic_vector(9 downto 0); -- some bits are masked\r
+ signal mem_data : std_logic_vector(17 downto 0);\r
+ signal rd_addr : std_logic_vector(9 downto 0); -- some bits are masked\r
+ signal readback_data : std_logic_vector(17 downto 0);\r
+\r
+ signal reg_busy : std_logic;\r
+\r
+begin\r
+\r
+-- Fake\r
+reg_busy <= busy_in;\r
+stat <= (others => '0');\r
+\r
+---------------------------------------------------------\r
+-- Statemachine --\r
+---------------------------------------------------------\r
+-- State memory process\r
+STATE_MEM: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ CURRENT_STATE <= SLEEP;\r
+ slv_busy <= '0';\r
+ slv_ack <= '0';\r
+ store_wr <= '0';\r
+ store_rd <= '0';\r
+ else\r
+ CURRENT_STATE <= NEXT_STATE;\r
+ slv_busy <= slv_busy_x;\r
+ slv_ack <= slv_ack_x;\r
+ store_wr <= store_wr_x;\r
+ store_rd <= store_rd_x;\r
+ end if;\r
+ end if;\r
+end process STATE_MEM;\r
+\r
+-- Transition matrix\r
+TRANSFORM: process(CURRENT_STATE, slv_read_in, slv_write_in, reg_busy )\r
+begin\r
+ NEXT_STATE <= SLEEP;\r
+ slv_busy_x <= '0';\r
+ slv_ack_x <= '0';\r
+ store_wr_x <= '0';\r
+ store_rd_x <= '0';\r
+ case CURRENT_STATE is\r
+ when SLEEP => if ( (reg_busy = '0') and (slv_read_in = '1') ) then\r
+ NEXT_STATE <= RD_RDY;\r
+ store_rd_x <= '1';\r
+ elsif( (reg_busy = '0') and (slv_write_in = '1') ) then\r
+ NEXT_STATE <= WR_RDY;\r
+ store_wr_x <= '1';\r
+ elsif( (reg_busy = '1') and (slv_read_in = '1') ) then\r
+ NEXT_STATE <= RD_BSY;\r
+ elsif( (reg_busy = '1') and (slv_write_in = '1') ) then\r
+ NEXT_STATE <= WR_BSY;\r
+ else \r
+ NEXT_STATE <= SLEEP;\r
+ end if;\r
+ when RD_RDY => NEXT_STATE <= RD_ACK;\r
+ when WR_RDY => NEXT_STATE <= WR_ACK;\r
+ when RD_ACK => if( slv_read_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ slv_ack_x <= '1';\r
+ else\r
+ NEXT_STATE <= RD_ACK;\r
+ slv_ack_x <= '1';\r
+ end if;\r
+ when WR_ACK => if( slv_write_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ slv_ack_x <= '1';\r
+ else\r
+ NEXT_STATE <= WR_ACK;\r
+ slv_ack_x <= '1';\r
+ end if;\r
+ when RD_BSY => if( slv_read_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ else\r
+ NEXT_STATE <= RD_BSY;\r
+ slv_busy_x <= '1';\r
+ end if;\r
+ when WR_BSY => if( slv_write_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ else\r
+ NEXT_STATE <= WR_BSY;\r
+ slv_busy_x <= '1';\r
+ end if;\r
+ when DONE => NEXT_STATE <= SLEEP;\r
+ \r
+ when others => NEXT_STATE <= SLEEP;\r
+ end case;\r
+end process TRANSFORM;\r
+\r
+---------------------------------------------------------\r
+-- data handling --\r
+---------------------------------------------------------\r
+\r
+wr_addr <= b"00" & slv_addr_in(7 downto 0);\r
+rd_addr <= b"00" & mem_addr_in(7 downto 0);\r
+\r
+-- one EBR used for one APV (A: TRBnet side, B: statemachines)\r
+THE_PED_THR_MEM: ped_thr_mem_true\r
+port map( DATAINA => slv_data_in(17 downto 0),\r
+ ADDRESSA => wr_addr,\r
+ CLOCKA => clk_in,\r
+ CLOCKENA => '1', \r
+ WRA => store_wr, \r
+ RESETA => reset_in,\r
+ QA => readback_data,\r
+ DATAINB => b"00_0000_0000_0000_0000", -- not used!\r
+ ADDRESSB => rd_addr, \r
+ CLOCKB => mem_clk_in, \r
+ CLOCKENB => '1', \r
+ WRB => '0', -- no write by statemachines!\r
+ RESETB => reset_in, \r
+ QB => mem_data\r
+ );\r
+\r
+-- output signals\r
+slv_ack_out <= slv_ack;\r
+slv_busy_out <= slv_busy;\r
+slv_data_out <= b"0000_0000_0000_00" & readback_data;\r
+\r
+---------------------------------------------------------\r
+-- signals to backend --\r
+---------------------------------------------------------\r
+\r
+mem_data_out <= mem_data;\r
+\r
+end Behavioral;\r
--- /dev/null
+[Device]\r
+Family=latticeecp2m\r
+PartType=LFE2M100E\r
+PartName=LFE2M100E-6F900C\r
+SpeedGrade=-6\r
+Package=FPBGA900\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=RAM_DP\r
+CoreRevision=6.1\r
+ModuleName=slv_onewire_dpram\r
+SourceFormat=VHDL\r
+ParameterFileVersion=1.0\r
+Date=08/11/2009\r
+Time=14:48:40\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+RAddress=64\r
+RData=32\r
+WAddress=128\r
+WData=16\r
+enByte=0\r
+ByteSize=9\r
+adPipeline=0\r
+inPipeline=0\r
+outPipeline=0\r
+MOR=0\r
+InData=Registered\r
+AdControl=Registered\r
+MemFile=\r
+MemFormat=bin\r
+Reset=Sync\r
+GSR=Enabled\r
+Pad=0\r
+EnECC=0\r
+Optimization=Speed\r
+EnSleep=ENABLED\r
+Pipeline=0\r
--- /dev/null
+SCUBA, Version ispLever_v72_SP2_Build (23)
+Tue Aug 11 14:48:40 2009
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp. All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
+Copyright (c) 2001 Agere Systems All rights reserved.
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
+
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n slv_onewire_dpram -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -device LFE2M100E -type ramdps -raddr_width 6 -rwidth 32 -waddr_width 7 -wwidth 16 -rnum_words 64 -wnum_words 128 -resetmode SYNC -cascade -1 -e
+ Circuit name : slv_onewire_dpram
+ Module type : RAM_DP
+ Module Version : 6.1
+ Ports :
+ Inputs : WrAddress[6:0], RdAddress[5:0], Data[15:0], WE, RdClock, RdClockEn, Reset, WrClock, WrClockEn
+ Outputs : Q[31:0]
+ I/O buffer : not inserted
+ EDIF output : suppressed
+ VHDL output : slv_onewire_dpram.vhd
+ VHDL template : slv_onewire_dpram_tmpl.vhd
+ VHDL testbench : tb_slv_onewire_dpram_tmpl.vhd
+ VHDL purpose : for synthesis and simulation
+ Bus notation : big endian
+ Report output : slv_onewire_dpram.srp
+ Element Usage :
+ DP16KB : 1
+ Estimated Resource Usage:
+ EBR : 1
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23)
+-- Module Version: 6.1
+--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type bram -wp 10 -rp 0011 -rdata_width 32 -data_width 16 -num_rows 128 -resetmode SYNC -cascade -1 -e
+
+-- Tue Aug 11 14:48:40 2009
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity slv_onewire_dpram is
+ port (
+ WrAddress: in std_logic_vector(6 downto 0);
+ RdAddress: in std_logic_vector(5 downto 0);
+ Data: in std_logic_vector(15 downto 0);
+ WE: in std_logic;
+ RdClock: in std_logic;
+ RdClockEn: in std_logic;
+ Reset: in std_logic;
+ WrClock: in std_logic;
+ WrClockEn: in std_logic;
+ Q: out std_logic_vector(31 downto 0));
+end slv_onewire_dpram;
+
+architecture Structure of slv_onewire_dpram is
+
+ -- internal signal declarations
+ signal scuba_vhi: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component DP16KB
+ -- synopsys translate_off
+ generic (GSR : in String; WRITEMODE_B : in String;
+ CSDECODE_B : in std_logic_vector(2 downto 0);
+ CSDECODE_A : in std_logic_vector(2 downto 0);
+ WRITEMODE_A : in String; RESETMODE : in String;
+ REGMODE_B : in String; REGMODE_A : in String;
+ DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer);
+ -- synopsys translate_on
+ port (DIA0: in std_logic; DIA1: in std_logic;
+ DIA2: in std_logic; DIA3: in std_logic;
+ DIA4: in std_logic; DIA5: in std_logic;
+ DIA6: in std_logic; DIA7: in std_logic;
+ DIA8: in std_logic; DIA9: in std_logic;
+ DIA10: in std_logic; DIA11: in std_logic;
+ DIA12: in std_logic; DIA13: in std_logic;
+ DIA14: in std_logic; DIA15: in std_logic;
+ DIA16: in std_logic; DIA17: in std_logic;
+ ADA0: in std_logic; ADA1: in std_logic;
+ ADA2: in std_logic; ADA3: in std_logic;
+ ADA4: in std_logic; ADA5: in std_logic;
+ ADA6: in std_logic; ADA7: in std_logic;
+ ADA8: in std_logic; ADA9: in std_logic;
+ ADA10: in std_logic; ADA11: in std_logic;
+ ADA12: in std_logic; ADA13: in std_logic;
+ CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic;
+ CSA0: in std_logic; CSA1: in std_logic;
+ CSA2: in std_logic; RSTA: in std_logic;
+ DIB0: in std_logic; DIB1: in std_logic;
+ DIB2: in std_logic; DIB3: in std_logic;
+ DIB4: in std_logic; DIB5: in std_logic;
+ DIB6: in std_logic; DIB7: in std_logic;
+ DIB8: in std_logic; DIB9: in std_logic;
+ DIB10: in std_logic; DIB11: in std_logic;
+ DIB12: in std_logic; DIB13: in std_logic;
+ DIB14: in std_logic; DIB15: in std_logic;
+ DIB16: in std_logic; DIB17: in std_logic;
+ ADB0: in std_logic; ADB1: in std_logic;
+ ADB2: in std_logic; ADB3: in std_logic;
+ ADB4: in std_logic; ADB5: in std_logic;
+ ADB6: in std_logic; ADB7: in std_logic;
+ ADB8: in std_logic; ADB9: in std_logic;
+ ADB10: in std_logic; ADB11: in std_logic;
+ ADB12: in std_logic; ADB13: in std_logic;
+ CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic;
+ CSB0: in std_logic; CSB1: in std_logic;
+ CSB2: in std_logic; RSTB: in std_logic;
+ DOA0: out std_logic; DOA1: out std_logic;
+ DOA2: out std_logic; DOA3: out std_logic;
+ DOA4: out std_logic; DOA5: out std_logic;
+ DOA6: out std_logic; DOA7: out std_logic;
+ DOA8: out std_logic; DOA9: out std_logic;
+ DOA10: out std_logic; DOA11: out std_logic;
+ DOA12: out std_logic; DOA13: out std_logic;
+ DOA14: out std_logic; DOA15: out std_logic;
+ DOA16: out std_logic; DOA17: out std_logic;
+ DOB0: out std_logic; DOB1: out std_logic;
+ DOB2: out std_logic; DOB3: out std_logic;
+ DOB4: out std_logic; DOB5: out std_logic;
+ DOB6: out std_logic; DOB7: out std_logic;
+ DOB8: out std_logic; DOB9: out std_logic;
+ DOB10: out std_logic; DOB11: out std_logic;
+ DOB12: out std_logic; DOB13: out std_logic;
+ DOB14: out std_logic; DOB15: out std_logic;
+ DOB16: out std_logic; DOB17: out std_logic);
+ end component;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute CSDECODE_B : string;
+ attribute CSDECODE_A : string;
+ attribute WRITEMODE_B : string;
+ attribute WRITEMODE_A : string;
+ attribute GSR : string;
+ attribute RESETMODE : string;
+ attribute REGMODE_B : string;
+ attribute REGMODE_A : string;
+ attribute DATA_WIDTH_B : string;
+ attribute DATA_WIDTH_A : string;
+ attribute MEM_LPC_FILE of slv_onewire_dpram_0_0_0 : label is "slv_onewire_dpram.lpc";
+ attribute MEM_INIT_FILE of slv_onewire_dpram_0_0_0 : label is "";
+ attribute CSDECODE_B of slv_onewire_dpram_0_0_0 : label is "0b000";
+ attribute CSDECODE_A of slv_onewire_dpram_0_0_0 : label is "0b000";
+ attribute WRITEMODE_B of slv_onewire_dpram_0_0_0 : label is "NORMAL";
+ attribute WRITEMODE_A of slv_onewire_dpram_0_0_0 : label is "NORMAL";
+ attribute GSR of slv_onewire_dpram_0_0_0 : label is "DISABLED";
+ attribute RESETMODE of slv_onewire_dpram_0_0_0 : label is "SYNC";
+ attribute REGMODE_B of slv_onewire_dpram_0_0_0 : label is "NOREG";
+ attribute REGMODE_A of slv_onewire_dpram_0_0_0 : label is "NOREG";
+ attribute DATA_WIDTH_B of slv_onewire_dpram_0_0_0 : label is "36";
+ attribute DATA_WIDTH_A of slv_onewire_dpram_0_0_0 : label is "18";
+
+begin
+ -- component instantiation statements
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ slv_onewire_dpram_0_0_0: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 36,
+ DATA_WIDTH_A=> 18)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
+ DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
+ DIA14=>Data(14), DIA15=>Data(15), DIA16=>scuba_vlo,
+ DIA17=>scuba_vlo, ADA0=>scuba_vhi, ADA1=>scuba_vhi,
+ ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>WrAddress(0),
+ ADA5=>WrAddress(1), ADA6=>WrAddress(2), ADA7=>WrAddress(3),
+ ADA8=>WrAddress(4), ADA9=>WrAddress(5), ADA10=>WrAddress(6),
+ ADA11=>scuba_vlo, ADA12=>scuba_vlo, ADA13=>scuba_vlo,
+ CEA=>WrClockEn, CLKA=>WrClock, WEA=>WE, CSA0=>scuba_vlo,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>scuba_vlo, ADB4=>scuba_vlo, ADB5=>RdAddress(0),
+ ADB6=>RdAddress(1), ADB7=>RdAddress(2), ADB8=>RdAddress(3),
+ ADB9=>RdAddress(4), ADB10=>RdAddress(5), ADB11=>scuba_vlo,
+ ADB12=>scuba_vlo, ADB13=>scuba_vlo, CEB=>RdClockEn,
+ CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>scuba_vlo,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>Q(0),
+ DOA1=>Q(1), DOA2=>Q(2), DOA3=>Q(3), DOA4=>Q(4), DOA5=>Q(5),
+ DOA6=>Q(6), DOA7=>Q(7), DOA8=>Q(8), DOA9=>Q(9), DOA10=>Q(10),
+ DOA11=>Q(11), DOA12=>Q(12), DOA13=>Q(13), DOA14=>Q(14),
+ DOA15=>Q(15), DOA16=>open, DOA17=>open, DOB0=>Q(16),
+ DOB1=>Q(17), DOB2=>Q(18), DOB3=>Q(19), DOB4=>Q(20),
+ DOB5=>Q(21), DOB6=>Q(22), DOB7=>Q(23), DOB8=>Q(24),
+ DOB9=>Q(25), DOB10=>Q(26), DOB11=>Q(27), DOB12=>Q(28),
+ DOB13=>Q(29), DOB14=>Q(30), DOB15=>Q(31), DOB16=>open,
+ DOB17=>open);
+
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of slv_onewire_dpram is
+ for Structure
+ for all:VHI use entity ecp2m.VHI(V); end for;
+ for all:VLO use entity ecp2m.VLO(V); end for;
+ for all:DP16KB use entity ecp2m.DP16KB(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+Starting process: \r
+\r
+SCUBA, Version ispLever_v72_SP2_Build (23)\r
+Tue Aug 11 14:48:40 2009\r
+\r
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
+Copyright (c) 1995 AT&T Corp. All rights reserved.\r
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
+Copyright (c) 2001 Agere Systems All rights reserved.\r
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
+\r
+BEGIN SCUBA Module Synthesis\r
+\r
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n slv_onewire_dpram -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -device LFE2M100E -type ramdps -raddr_width 6 -rwidth 32 -waddr_width 7 -wwidth 16 -rnum_words 64 -wnum_words 128 -resetmode SYNC -cascade -1 -e \r
+ Circuit name : slv_onewire_dpram\r
+ Module type : RAM_DP\r
+ Module Version : 6.1\r
+ Ports : \r
+ Inputs : WrAddress[6:0], RdAddress[5:0], Data[15:0], WE, RdClock, RdClockEn, Reset, WrClock, WrClockEn\r
+ Outputs : Q[31:0]\r
+ I/O buffer : not inserted\r
+ EDIF output : suppressed\r
+ VHDL output : slv_onewire_dpram.vhd\r
+ VHDL template : slv_onewire_dpram_tmpl.vhd\r
+ VHDL testbench : tb_slv_onewire_dpram_tmpl.vhd\r
+ VHDL purpose : for synthesis and simulation\r
+ Bus notation : big endian\r
+ Report output : slv_onewire_dpram.srp\r
+ Estimated Resource Usage:\r
+ EBR : 1\r
+\r
+END SCUBA Module Synthesis\r
+\r
+File: slv_onewire_dpram.lpc created.\r
+\r
+\r
+End process: completed successfully.\r
+\r
+\r
+Total Warnings: 0\r
+\r
+Total Errors: 0\r
+\r
+\r
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23)
+-- Module Version: 6.1
+-- Tue Aug 11 14:48:40 2009
+
+-- parameterized module component declaration
+component slv_onewire_dpram
+ port (WrAddress: in std_logic_vector(6 downto 0);
+ RdAddress: in std_logic_vector(5 downto 0);
+ Data: in std_logic_vector(15 downto 0); WE: in std_logic;
+ RdClock: in std_logic; RdClockEn: in std_logic;
+ Reset: in std_logic; WrClock: in std_logic;
+ WrClockEn: in std_logic; Q: out std_logic_vector(31 downto 0));
+end component;
+
+-- parameterized module component instance
+__ : slv_onewire_dpram
+ port map (WrAddress(6 downto 0)=>__, RdAddress(5 downto 0)=>__, Data(15 downto 0)=>__,
+ WE=>__, RdClock=>__, RdClockEn=>__, Reset=>__, WrClock=>__,
+ WrClockEn=>__, Q(31 downto 0)=>__);
--- /dev/null
+library IEEE;\r
+use IEEE.STD_LOGIC_1164.ALL;\r
+use IEEE.STD_LOGIC_ARITH.ALL;\r
+use IEEE.STD_LOGIC_UNSIGNED.ALL;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+entity slv_onewire_memory is\r
+port( CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_ADDR_IN : in std_logic_vector(5 downto 0);\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_BUSY_OUT : out std_logic;\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- backplane identifier\r
+ BACKPLANE_IN : in std_logic_vector(2 downto 0);\r
+ -- 1Wire lines\r
+ ONEWIRE_START_IN : in std_logic;\r
+ ONEWIRE_INOUT : inout std_logic_vector(15 downto 0);\r
+ BP_ONEWIRE_INOUT : inout std_logic;\r
+ -- Status lines\r
+ STAT : out std_logic_vector(63 downto 0) -- DEBUG\r
+ );\r
+end entity;\r
+\r
+architecture Behavioral of slv_onewire_memory is\r
+\r
+-- Signals\r
+ type STATES is (SLEEP,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE);\r
+ signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+ -- slave bus signals\r
+ signal slv_ack_x : std_logic;\r
+ signal slv_ack : std_logic;\r
+ signal slv_busy : std_logic;\r
+ signal store_wr_x : std_logic;\r
+ signal store_wr : std_logic;\r
+ signal store_rd_x : std_logic;\r
+ signal store_rd : std_logic;\r
+\r
+ -- for replacing the lost FE with BP data\r
+ signal wr_addr_q : std_logic_vector(6 downto 0); -- some bits are masked\r
+ signal wr_data_q : std_logic_vector(15 downto 0);\r
+ signal wr_we_q : std_logic;\r
+\r
+ signal wr_addr : std_logic_vector(6 downto 0); -- some bits are masked\r
+ signal wr_bp_data : std_logic_vector(15 downto 0);\r
+ signal wr_data : std_logic_vector(15 downto 0);\r
+ signal wr_we : std_logic;\r
+ signal buf_slv_data_out : std_logic_vector(31 downto 0);\r
+\r
+ signal read_address : std_logic_vector(5 downto 0);\r
+ signal missing_one : std_logic_vector(3 downto 0); -- missing APV FE <-> backplane\r
+ signal overlay : std_logic;\r
+\r
+ signal onewire_bsm : std_logic_vector(7 downto 0);\r
+\r
+begin\r
+\r
+-- Fake\r
+stat(63 downto 40) <= (others => '0');\r
+\r
+stat(39 downto 32) <= buf_slv_data_out(7 downto 0);\r
+stat(31 downto 26) <= slv_addr_in;\r
+stat(25) <= slv_write_in;\r
+stat(24) <= slv_read_in;\r
+stat(23) <= store_wr;\r
+stat(22) <= store_rd;\r
+stat(21) <= slv_ack;\r
+stat(20) <= slv_busy;\r
+stat(19) <= wr_we;\r
+stat(18 downto 12) <= wr_addr;\r
+stat(11 downto 4) <= wr_data(7 downto 0);\r
+stat(3 downto 0) <= onewire_bsm(3 downto 0);\r
+\r
+-- Remap the 1Wire chips to Luigi's world\r
+THE_ADC_ONEWIRE_MAP_MEM: adc_onewire_map_mem\r
+port map( ADDRESS(6 downto 4) => backplane_in,\r
+ ADDRESS(3 downto 0) => slv_addr_in(5 downto 2),\r
+ Q => read_address(5 downto 2)\r
+ );\r
+read_address(1 downto 0) <= slv_addr_in(1 downto 0);\r
+\r
+-- One APV FE connector is missing ("Roman's FE"), and replace the \r
+-- 1Wire ID by the backplane\r
+THE_ONEWIRE_SPARE_ONE: onewire_spare_one\r
+port map( ADDRESS => backplane_in,\r
+ Q => missing_one\r
+ );\r
+\r
+-- Check if we need to replace data\r
+overlay <= '1' when (wr_addr(6 downto 3) = missing_one) else '0';\r
+\r
+\r
+---------------------------------------------------------\r
+-- Statemachine --\r
+---------------------------------------------------------\r
+-- State memory process\r
+STATE_MEM: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ CURRENT_STATE <= SLEEP;\r
+ slv_ack <= '0';\r
+ store_wr <= '0';\r
+ store_rd <= '0';\r
+ else\r
+ CURRENT_STATE <= NEXT_STATE;\r
+ slv_ack <= slv_ack_x;\r
+ store_wr <= store_wr_x;\r
+ store_rd <= store_rd_x;\r
+ end if;\r
+ end if;\r
+end process STATE_MEM;\r
+\r
+-- Transition matrix\r
+TRANSFORM: process(CURRENT_STATE, slv_read_in, slv_write_in )\r
+begin\r
+ NEXT_STATE <= SLEEP;\r
+ slv_ack_x <= '0';\r
+ store_wr_x <= '0';\r
+ store_rd_x <= '0';\r
+ case CURRENT_STATE is\r
+ when SLEEP => if ( (slv_read_in = '1') ) then\r
+ NEXT_STATE <= RD_RDY;\r
+ store_rd_x <= '1';\r
+ elsif( (slv_write_in = '1') ) then\r
+ NEXT_STATE <= WR_RDY;\r
+ store_wr_x <= '1';\r
+ else \r
+ NEXT_STATE <= SLEEP;\r
+ end if;\r
+ when RD_RDY => NEXT_STATE <= RD_ACK;\r
+ when WR_RDY => NEXT_STATE <= WR_ACK;\r
+ when RD_ACK => if( slv_read_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ slv_ack_x <= '1';\r
+ else\r
+ NEXT_STATE <= RD_ACK;\r
+ slv_ack_x <= '1';\r
+ end if;\r
+ when WR_ACK => if( slv_write_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ slv_ack_x <= '1';\r
+ else\r
+ NEXT_STATE <= WR_ACK;\r
+ slv_ack_x <= '1';\r
+ end if;\r
+ when DONE => NEXT_STATE <= SLEEP;\r
+ \r
+ when others => NEXT_STATE <= SLEEP;\r
+ end case;\r
+end process TRANSFORM;\r
+\r
+\r
+---------------------------------------------------------\r
+-- 1 Wire master --\r
+---------------------------------------------------------\r
+THE_ONEWIRE_MASTER: onewire_master\r
+generic map( CLK_PERIOD => 10 )\r
+port map( CLK => clk_in,\r
+ RESET => reset_in,\r
+ READOUT_ENABLE_IN => store_wr,\r
+ -- connection to 1-wire interface (16 APV FEs)\r
+ ONEWIRE => onewire_inout,\r
+ BP_ONEWIRE => bp_onewire_inout,\r
+ -- connection to external DPRAM for slow control readout\r
+ BP_DATA_OUT => wr_bp_data, \r
+ DATA_OUT => wr_data,\r
+ ADDR_OUT => wr_addr,\r
+ WRITE_OUT => wr_we,\r
+ BUSY_OUT => slv_busy, -- could be used...\r
+ -- debug\r
+ BSM_OUT => onewire_bsm,\r
+ STAT => open\r
+ );\r
+\r
+---------------------------------------------------------\r
+-- data replacing --\r
+---------------------------------------------------------\r
+THE_DATA_REPLACE_PROC: process(clk_in)\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ wr_addr_q <= wr_addr;\r
+ wr_we_q <= wr_we;\r
+ if( overlay = '1' ) then\r
+ wr_data_q <= wr_bp_data;\r
+ else\r
+ wr_data_q <= wr_data;\r
+ end if;\r
+ end if;\r
+end process THE_DATA_REPLACE_PROC;\r
+\r
+---------------------------------------------------------\r
+-- data handling --\r
+---------------------------------------------------------\r
+THE_SLV_ONEWIRE_DPRAM: slv_onewire_dpram\r
+port map( WRADDRESS => wr_addr_q,\r
+ RDADDRESS => read_address,\r
+ DATA => wr_data_q,\r
+ WE => wr_we_q,\r
+ RDCLOCK => clk_in,\r
+ RDCLOCKEN => '1',\r
+ RESET => reset_in,\r
+ WRCLOCK => clk_in,\r
+ WRCLOCKEN => '1',\r
+ Q => buf_slv_data_out\r
+ );\r
+\r
+\r
+\r
+-- output signals\r
+slv_data_out <= buf_slv_data_out;\r
+slv_ack_out <= slv_ack;\r
+slv_busy_out <= slv_busy;\r
+\r
+end Behavioral;\r
--- /dev/null
+library IEEE;\r
+use IEEE.STD_LOGIC_1164.ALL;\r
+use IEEE.STD_LOGIC_ARITH.ALL;\r
+use IEEE.STD_LOGIC_UNSIGNED.ALL;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+entity slv_ped_thr_mem is\r
+port( CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_ADDR_IN : in std_logic_vector(10 downto 0);\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- backplane identifier\r
+ BACKPLANE_IN : in std_logic_vector(2 downto 0);\r
+ -- I/O to the backend\r
+ MEM_CLK_IN : in std_logic;\r
+ MEM_ADDR_IN : in std_logic_vector(6 downto 0);\r
+ MEM_0_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_1_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_2_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_3_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_4_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_5_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_6_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_7_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_8_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_9_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_10_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_11_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_12_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_13_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_14_D_OUT : out std_logic_vector(17 downto 0);\r
+ MEM_15_D_OUT : out std_logic_vector(17 downto 0);\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+ );\r
+end entity;\r
+\r
+architecture Behavioral of slv_ped_thr_mem is\r
+\r
+-- Signals\r
+ type STATES is (SLEEP,RD_RDY,RD_DEL0,RD_DEL1,WR_DEL0,WR_DEL1,WR_RDY,RD_ACK,WR_ACK,DONE);\r
+ signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+ -- statemachine signals\r
+ signal slv_ack_x : std_logic;\r
+ signal slv_ack : std_logic;\r
+ signal store_wr_x : std_logic;\r
+ signal store_wr : std_logic;\r
+ signal store_rd_x : std_logic;\r
+ signal store_rd : std_logic;\r
+\r
+ signal block_addr : std_logic_vector(3 downto 0);\r
+\r
+ type ped_data_t is array (0 to 15) of std_logic_vector(17 downto 0);\r
+ signal ped_data : ped_data_t;\r
+ signal mem_data : ped_data_t;\r
+\r
+ signal mem_wr_x : std_logic_vector(15 downto 0);\r
+ signal mem_wr : std_logic_vector(15 downto 0);\r
+ signal mem_sel : std_logic_vector(15 downto 0);\r
+\r
+ signal rdback_data : std_logic_vector(17 downto 0);\r
+ \r
+begin\r
+\r
+---------------------------------------------------------\r
+-- Mapping of backplanes --\r
+---------------------------------------------------------\r
+THE_APV_ADC_MAP_MEM: apv_adc_map_mem\r
+port map( ADDRESS(6 downto 4) => backplane_in,\r
+ ADDRESS(3 downto 0) => slv_addr_in(10 downto 7),\r
+ Q => block_addr\r
+ );\r
+\r
+THE_MEM_SEL_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ case block_addr is\r
+ when x"0" => mem_sel <= b"0000_0000_0000_0001";\r
+ rdback_data <= mem_data(0);\r
+ when x"1" => mem_sel <= b"0000_0000_0000_0010";\r
+ rdback_data <= mem_data(1);\r
+ when x"2" => mem_sel <= b"0000_0000_0000_0100";\r
+ rdback_data <= mem_data(2);\r
+ when x"3" => mem_sel <= b"0000_0000_0000_1000";\r
+ rdback_data <= mem_data(3);\r
+ when x"4" => mem_sel <= b"0000_0000_0001_0000";\r
+ rdback_data <= mem_data(4);\r
+ when x"5" => mem_sel <= b"0000_0000_0010_0000";\r
+ rdback_data <= mem_data(5);\r
+ when x"6" => mem_sel <= b"0000_0000_0100_0000";\r
+ rdback_data <= mem_data(6);\r
+ when x"7" => mem_sel <= b"0000_0000_1000_0000";\r
+ rdback_data <= mem_data(7);\r
+ when x"8" => mem_sel <= b"0000_0001_0000_0000";\r
+ rdback_data <= mem_data(8);\r
+ when x"9" => mem_sel <= b"0000_0010_0000_0000";\r
+ rdback_data <= mem_data(9);\r
+ when x"a" => mem_sel <= b"0000_0100_0000_0000";\r
+ rdback_data <= mem_data(10);\r
+ when x"b" => mem_sel <= b"0000_1000_0000_0000";\r
+ rdback_data <= mem_data(11);\r
+ when x"c" => mem_sel <= b"0001_0000_0000_0000";\r
+ rdback_data <= mem_data(12);\r
+ when x"d" => mem_sel <= b"0010_0000_0000_0000";\r
+ rdback_data <= mem_data(13);\r
+ when x"e" => mem_sel <= b"0100_0000_0000_0000";\r
+ rdback_data <= mem_data(14);\r
+ when x"f" => mem_sel <= b"1000_0000_0000_0000";\r
+ rdback_data <= mem_data(15);\r
+ when others => mem_sel <= b"0000_0000_0000_0000"; -- never used\r
+ rdback_data <= (others => '0');\r
+ end case;\r
+ end if;\r
+end process THE_MEM_SEL_PROC;\r
+\r
+---------------------------------------------------------\r
+-- Statemachine --\r
+---------------------------------------------------------\r
+-- State memory process\r
+STATE_MEM: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ CURRENT_STATE <= SLEEP;\r
+ slv_ack <= '0';\r
+ store_wr <= '0';\r
+ store_rd <= '0';\r
+ else\r
+ CURRENT_STATE <= NEXT_STATE;\r
+ slv_ack <= slv_ack_x;\r
+ store_wr <= store_wr_x;\r
+ store_rd <= store_rd_x;\r
+ end if;\r
+ end if;\r
+end process STATE_MEM;\r
+\r
+-- Transition matrix\r
+TRANSFORM: process( CURRENT_STATE, slv_read_in, slv_write_in )\r
+begin\r
+ NEXT_STATE <= SLEEP;\r
+ slv_ack_x <= '0';\r
+ store_wr_x <= '0';\r
+ store_rd_x <= '0';\r
+ case CURRENT_STATE is\r
+ when SLEEP => if ( slv_read_in = '1' ) then\r
+ NEXT_STATE <= RD_DEL0;\r
+ store_rd_x <= '1';\r
+ elsif( slv_write_in = '1' ) then\r
+ NEXT_STATE <= WR_DEL0;\r
+ store_wr_x <= '1';\r
+ else \r
+ NEXT_STATE <= SLEEP;\r
+ end if;\r
+ when RD_DEL0 => NEXT_STATE <= RD_DEL1;\r
+ when RD_DEL1 => NEXT_STATE <= RD_RDY;\r
+ when RD_RDY => NEXT_STATE <= RD_ACK;\r
+ when RD_ACK => if( slv_read_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ slv_ack_x <= '1';\r
+ else\r
+ NEXT_STATE <= RD_ACK;\r
+ slv_ack_x <= '1';\r
+ end if;\r
+ when WR_DEL0 => NEXT_STATE <= WR_DEL1;\r
+ when WR_DEL1 => NEXT_STATE <= WR_RDY;\r
+ when WR_RDY => NEXT_STATE <= WR_ACK;\r
+ when WR_ACK => if( slv_write_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ slv_ack_x <= '1';\r
+ else\r
+ NEXT_STATE <= WR_ACK;\r
+ slv_ack_x <= '1';\r
+ end if;\r
+ when DONE => NEXT_STATE <= SLEEP;\r
+ \r
+ when others => NEXT_STATE <= SLEEP;\r
+ end case;\r
+end process TRANSFORM;\r
+\r
+---------------------------------------------------------\r
+-- block memories --\r
+---------------------------------------------------------\r
+GEN_PED_MEM: for i in 0 to 15 generate \r
+ -- Port A: SLV_BUS\r
+ -- Port B: state machine\r
+ THE_PED_MEM: ped_thr_true \r
+ port map( DATAINA => slv_data_in(17 downto 0), \r
+ DATAINB => b"00_0000_0000_0000_0000",\r
+ ADDRESSA => slv_addr_in(6 downto 0),\r
+ ADDRESSB => mem_addr_in,\r
+ CLOCKA => clk_in,\r
+ CLOCKB => mem_clk_in,\r
+ CLOCKENA => '1',\r
+ CLOCKENB => '1',\r
+ WRA => mem_wr(i), -- BUGBUGBUG\r
+ WRB => '0', -- state machine never writes!\r
+ RESETA => reset_in,\r
+ RESETB => reset_in,\r
+ QA => mem_data(i),\r
+ QB => ped_data(i)\r
+ );\r
+ -- Write signals\r
+ mem_wr_x(i) <= '1' when ( (mem_sel(i) = '1') and (store_wr = '1') ) else '0';\r
+end generate GEN_PED_MEM;\r
+\r
+-- Synchronize\r
+THE_SYNC_PROC: process(clk_in)\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ mem_wr <= mem_wr_x;\r
+ end if;\r
+end process THE_SYNC_PROC;\r
+\r
+---------------------------------------------------------\r
+-- output signals --\r
+---------------------------------------------------------\r
+slv_ack_out <= slv_ack;\r
+slv_data_out <= b"0000_0000_0000_00" & rdback_data;\r
+\r
+mem_0_d_out <= ped_data(0);\r
+mem_1_d_out <= ped_data(1);\r
+mem_2_d_out <= ped_data(2);\r
+mem_3_d_out <= ped_data(3);\r
+mem_4_d_out <= ped_data(4);\r
+mem_5_d_out <= ped_data(5);\r
+mem_6_d_out <= ped_data(6);\r
+mem_7_d_out <= ped_data(7);\r
+mem_8_d_out <= ped_data(8);\r
+mem_9_d_out <= ped_data(9);\r
+mem_10_d_out <= ped_data(10);\r
+mem_11_d_out <= ped_data(11);\r
+mem_12_d_out <= ped_data(12);\r
+mem_13_d_out <= ped_data(13);\r
+mem_14_d_out <= ped_data(14);\r
+mem_15_d_out <= ped_data(15);\r
+\r
+stat(31 downto 20) <= (others => '0');\r
+stat(19 downto 16) <= block_addr;\r
+stat(15 downto 0) <= mem_sel;\r
+\r
+end Behavioral;\r
--- /dev/null
+library IEEE;\r
+use IEEE.STD_LOGIC_1164.ALL;\r
+use IEEE.STD_LOGIC_ARITH.ALL;\r
+use IEEE.STD_LOGIC_UNSIGNED.ALL;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+\r
+entity slv_register is\r
+generic( RESET_VALUE : std_logic_vector(31 downto 0) := x"0000_0000" );\r
+port( CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ BUSY_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_BUSY_OUT : out std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- I/O to the backend\r
+ REG_DATA_IN : in std_logic_vector(31 downto 0);\r
+ REG_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+ );\r
+end entity;\r
+\r
+architecture Behavioral of slv_register is\r
+\r
+-- Signals\r
+\r
+ type STATES is (SLEEP,RD_BSY,WR_BSY,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE);\r
+ signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+ -- slave bus signals\r
+ signal slv_busy_x : std_logic;\r
+ signal slv_busy : std_logic;\r
+ signal slv_ack_x : std_logic;\r
+ signal slv_ack : std_logic;\r
+ signal store_wr_x : std_logic;\r
+ signal store_wr : std_logic;\r
+ signal store_rd_x : std_logic;\r
+ signal store_rd : std_logic;\r
+\r
+ signal reg_slv_data_in : std_logic_vector(31 downto 0); -- registered data input\r
+ signal reg_slv_data_out : std_logic_vector(31 downto 0); -- read back data\r
+ signal reg_busy : std_logic;\r
+\r
+begin\r
+\r
+-- Fake\r
+reg_busy <= busy_in;\r
+stat <= (others => '0');\r
+\r
+---------------------------------------------------------\r
+-- Statemachine --\r
+---------------------------------------------------------\r
+-- State memory process\r
+STATE_MEM: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ CURRENT_STATE <= SLEEP;\r
+ slv_busy <= '0';\r
+ slv_ack <= '0';\r
+ store_wr <= '0';\r
+ store_rd <= '0';\r
+ else\r
+ CURRENT_STATE <= NEXT_STATE;\r
+ slv_busy <= slv_busy_x;\r
+ slv_ack <= slv_ack_x;\r
+ store_wr <= store_wr_x;\r
+ store_rd <= store_rd_x;\r
+ end if;\r
+ end if;\r
+end process STATE_MEM;\r
+\r
+-- Transition matrix\r
+TRANSFORM: process(CURRENT_STATE, slv_read_in, slv_write_in, reg_busy )\r
+begin\r
+ NEXT_STATE <= SLEEP;\r
+ slv_busy_x <= '0';\r
+ slv_ack_x <= '0';\r
+ store_wr_x <= '0';\r
+ store_rd_x <= '0';\r
+ case CURRENT_STATE is\r
+ when SLEEP => if ( (reg_busy = '0') and (slv_read_in = '1') ) then\r
+ NEXT_STATE <= RD_RDY;\r
+ store_rd_x <= '1';\r
+ elsif( (reg_busy = '0') and (slv_write_in = '1') ) then\r
+ NEXT_STATE <= WR_RDY;\r
+ store_wr_x <= '1';\r
+ elsif( (reg_busy = '1') and (slv_read_in = '1') ) then\r
+ NEXT_STATE <= RD_BSY;\r
+ slv_busy_x <= '1'; -- added 23022009\r
+ elsif( (reg_busy = '1') and (slv_write_in = '1') ) then\r
+ NEXT_STATE <= WR_BSY;\r
+ slv_busy_x <= '1'; -- added 23022009\r
+ else \r
+ NEXT_STATE <= SLEEP;\r
+ end if;\r
+ when RD_RDY => NEXT_STATE <= RD_ACK;\r
+ slv_ack_x <= '1';\r
+ when WR_RDY => NEXT_STATE <= WR_ACK;\r
+ slv_ack_x <= '1';\r
+ when RD_ACK => if( slv_read_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ else\r
+ NEXT_STATE <= RD_ACK;\r
+ slv_ack_x <= '1';\r
+ end if;\r
+ when WR_ACK => if( slv_write_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ else\r
+ NEXT_STATE <= WR_ACK;\r
+ slv_ack_x <= '1';\r
+ end if;\r
+ when RD_BSY => if( slv_read_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ else\r
+ NEXT_STATE <= RD_BSY;\r
+ slv_busy_x <= '1';\r
+ end if;\r
+ when WR_BSY => if( slv_write_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ else\r
+ NEXT_STATE <= WR_BSY;\r
+ slv_busy_x <= '1';\r
+ end if;\r
+ when DONE => NEXT_STATE <= SLEEP;\r
+ \r
+ when others => NEXT_STATE <= SLEEP;\r
+ end case;\r
+end process TRANSFORM;\r
+\r
+---------------------------------------------------------\r
+-- data handling --\r
+---------------------------------------------------------\r
+\r
+-- register write\r
+THE_WRITE_REG_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( reset_in = '1' ) then\r
+ reg_slv_data_in <= RESET_VALUE;\r
+ elsif( store_wr = '1' ) then\r
+ reg_slv_data_in <= slv_data_in;\r
+ end if;\r
+ end if;\r
+end process THE_WRITE_REG_PROC;\r
+\r
+-- register read\r
+THE_READ_REG_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( reset_in = '1' ) then\r
+ reg_slv_data_out <= (others => '0');\r
+ elsif( store_rd = '1' ) then\r
+ reg_slv_data_out <= reg_data_in;\r
+ end if;\r
+ end if;\r
+end process THE_READ_REG_PROC;\r
+\r
+-- output signals\r
+slv_ack_out <= slv_ack;\r
+slv_busy_out <= slv_busy;\r
+slv_data_out <= reg_slv_data_out;\r
+\r
+---------------------------------------------------------\r
+-- signals to backend --\r
+---------------------------------------------------------\r
+\r
+reg_data_out <= reg_slv_data_in;\r
+\r
+end Behavioral;\r
--- /dev/null
+library IEEE;\r
+use IEEE.STD_LOGIC_1164.ALL;\r
+use IEEE.STD_LOGIC_ARITH.ALL;\r
+use IEEE.STD_LOGIC_UNSIGNED.ALL;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+entity slv_register_bank is\r
+generic( RESET_VALUE : std_logic_vector(15 downto 0) := x"0001" );\r
+port( CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_ADDR_IN : in std_logic_vector(3 downto 0);\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- I/O to the backend\r
+ BACKPLANE_IN : in std_logic_vector(2 downto 0);\r
+ CTRL_0_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_1_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_2_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_3_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_4_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_5_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_6_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_7_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_8_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_9_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_10_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_11_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_12_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_13_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_14_OUT : out std_logic_vector(15 downto 0);\r
+ CTRL_15_OUT : out std_logic_vector(15 downto 0);\r
+ STAT_0_IN : in std_logic_vector(15 downto 0);\r
+ STAT_1_IN : in std_logic_vector(15 downto 0);\r
+ STAT_2_IN : in std_logic_vector(15 downto 0);\r
+ STAT_3_IN : in std_logic_vector(15 downto 0);\r
+ STAT_4_IN : in std_logic_vector(15 downto 0);\r
+ STAT_5_IN : in std_logic_vector(15 downto 0);\r
+ STAT_6_IN : in std_logic_vector(15 downto 0);\r
+ STAT_7_IN : in std_logic_vector(15 downto 0);\r
+ STAT_8_IN : in std_logic_vector(15 downto 0);\r
+ STAT_9_IN : in std_logic_vector(15 downto 0);\r
+ STAT_10_IN : in std_logic_vector(15 downto 0);\r
+ STAT_11_IN : in std_logic_vector(15 downto 0);\r
+ STAT_12_IN : in std_logic_vector(15 downto 0);\r
+ STAT_13_IN : in std_logic_vector(15 downto 0);\r
+ STAT_14_IN : in std_logic_vector(15 downto 0);\r
+ STAT_15_IN : in std_logic_vector(15 downto 0);\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+ );\r
+end entity;\r
+\r
+architecture Behavioral of slv_register_bank is\r
+\r
+-- Signals\r
+ type STATES is (SLEEP,RD_RDY,RD_DEL0,RD_DEL1,WR_DEL0,WR_DEL1,WR_RDY,RD_ACK,WR_ACK,DONE);\r
+ signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+ signal slv_ack_x : std_logic;\r
+ signal slv_ack : std_logic;\r
+ signal store_wr_x : std_logic;\r
+ signal store_wr : std_logic;\r
+ signal store_rd_x : std_logic;\r
+ signal store_rd : std_logic;\r
+\r
+ signal adc_addr : std_logic_vector(3 downto 0); -- ADC address after mapping\r
+ signal reg_sel : std_logic_vector(15 downto 0);\r
+ signal reg_wr : std_logic_vector(15 downto 0);\r
+ signal reg_wr_x : std_logic_vector(15 downto 0);\r
+\r
+ type ctrl_reg_t is array (0 to 15) of std_logic_vector(15 downto 0);\r
+ signal ctrl_reg : ctrl_reg_t;\r
+\r
+ signal rdback_data : std_logic_vector(31 downto 0);\r
+ \r
+begin\r
+\r
+-- Fake\r
+stat <= (others => '0');\r
+\r
+---------------------------------------------------------\r
+-- Mapping of backplanes --\r
+---------------------------------------------------------\r
+THE_APV_ADC_MAP_MEM: apv_adc_map_mem\r
+port map( ADDRESS(6 downto 4) => backplane_in,\r
+ ADDRESS(3 downto 0) => slv_addr_in,\r
+ Q => adc_addr\r
+ );\r
+\r
+THE_REG_SEL_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ case adc_addr is\r
+ when x"0" => reg_sel <= b"0000_0000_0000_0001";\r
+ rdback_data <= stat_0_in & ctrl_reg(0);\r
+ when x"1" => reg_sel <= b"0000_0000_0000_0010";\r
+ rdback_data <= stat_1_in & ctrl_reg(1);\r
+ when x"2" => reg_sel <= b"0000_0000_0000_0100";\r
+ rdback_data <= stat_2_in & ctrl_reg(2);\r
+ when x"3" => reg_sel <= b"0000_0000_0000_1000";\r
+ rdback_data <= stat_3_in & ctrl_reg(3);\r
+ when x"4" => reg_sel <= b"0000_0000_0001_0000";\r
+ rdback_data <= stat_4_in & ctrl_reg(4);\r
+ when x"5" => reg_sel <= b"0000_0000_0010_0000";\r
+ rdback_data <= stat_5_in & ctrl_reg(5);\r
+ when x"6" => reg_sel <= b"0000_0000_0100_0000";\r
+ rdback_data <= stat_6_in & ctrl_reg(6);\r
+ when x"7" => reg_sel <= b"0000_0000_1000_0000";\r
+ rdback_data <= stat_7_in & ctrl_reg(7);\r
+ when x"8" => reg_sel <= b"0000_0001_0000_0000";\r
+ rdback_data <= stat_8_in & ctrl_reg(8);\r
+ when x"9" => reg_sel <= b"0000_0010_0000_0000";\r
+ rdback_data <= stat_9_in & ctrl_reg(9);\r
+ when x"a" => reg_sel <= b"0000_0100_0000_0000";\r
+ rdback_data <= stat_10_in & ctrl_reg(10);\r
+ when x"b" => reg_sel <= b"0000_1000_0000_0000";\r
+ rdback_data <= stat_11_in & ctrl_reg(11);\r
+ when x"c" => reg_sel <= b"0001_0000_0000_0000";\r
+ rdback_data <= stat_12_in & ctrl_reg(12);\r
+ when x"d" => reg_sel <= b"0010_0000_0000_0000";\r
+ rdback_data <= stat_13_in & ctrl_reg(13);\r
+ when x"e" => reg_sel <= b"0100_0000_0000_0000";\r
+ rdback_data <= stat_14_in & ctrl_reg(14);\r
+ when x"f" => reg_sel <= b"1000_0000_0000_0000";\r
+ rdback_data <= stat_15_in & ctrl_reg(15);\r
+ when others => reg_sel <= b"0000_0000_0000_0000"; -- never used\r
+ rdback_data <= x"0000_0000";\r
+ end case;\r
+ end if;\r
+end process THE_REG_SEL_PROC;\r
+\r
+---------------------------------------------------------\r
+-- Statemachine --\r
+---------------------------------------------------------\r
+-- State memory process\r
+STATE_MEM: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ CURRENT_STATE <= SLEEP;\r
+ slv_ack <= '0';\r
+ store_wr <= '0';\r
+ store_rd <= '0';\r
+ else\r
+ CURRENT_STATE <= NEXT_STATE;\r
+ slv_ack <= slv_ack_x;\r
+ store_wr <= store_wr_x;\r
+ store_rd <= store_rd_x;\r
+ end if;\r
+ end if;\r
+end process STATE_MEM;\r
+\r
+-- Transition matrix\r
+TRANSFORM: process( CURRENT_STATE, slv_read_in, slv_write_in )\r
+begin\r
+ NEXT_STATE <= SLEEP;\r
+ slv_ack_x <= '0';\r
+ store_wr_x <= '0';\r
+ store_rd_x <= '0';\r
+ case CURRENT_STATE is\r
+ when SLEEP => if ( slv_read_in = '1' ) then\r
+ NEXT_STATE <= RD_DEL0;\r
+ store_rd_x <= '1';\r
+ elsif( slv_write_in = '1' ) then\r
+ NEXT_STATE <= WR_DEL0;\r
+ store_wr_x <= '1';\r
+ else \r
+ NEXT_STATE <= SLEEP;\r
+ end if;\r
+ when RD_DEL0 => NEXT_STATE <= RD_DEL1;\r
+ when RD_DEL1 => NEXT_STATE <= RD_RDY;\r
+ when RD_RDY => NEXT_STATE <= RD_ACK;\r
+ when RD_ACK => if( slv_read_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ slv_ack_x <= '1';\r
+ else\r
+ NEXT_STATE <= RD_ACK;\r
+ slv_ack_x <= '1';\r
+ end if;\r
+ when WR_DEL0 => NEXT_STATE <= WR_DEL1;\r
+ when WR_DEL1 => NEXT_STATE <= WR_RDY;\r
+ when WR_RDY => NEXT_STATE <= WR_ACK;\r
+ when WR_ACK => if( slv_write_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ slv_ack_x <= '1';\r
+ else\r
+ NEXT_STATE <= WR_ACK;\r
+ slv_ack_x <= '1';\r
+ end if;\r
+ when DONE => NEXT_STATE <= SLEEP;\r
+ \r
+ when others => NEXT_STATE <= SLEEP;\r
+ end case;\r
+end process TRANSFORM;\r
+\r
+---------------------------------------------------------\r
+-- data handling --\r
+---------------------------------------------------------\r
+\r
+-- register write\r
+GEN_CTRL_REG: for i in 0 to 15 generate \r
+ THE_WR_REG_PROC: process( clk_in )\r
+ begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( reset_in = '1' ) then\r
+ ctrl_reg(i) <= RESET_VALUE;\r
+ elsif( reg_wr(i) = '1' ) then\r
+ ctrl_reg(i) <= slv_data_in(15 downto 0);\r
+ end if;\r
+ end if;\r
+ end process THE_WR_REG_PROC;\r
+ reg_wr_x(i) <= '1' when ( (reg_sel(i) = '1') and (store_wr = '1') ) else '0';\r
+end generate GEN_CTRL_REG;\r
+\r
+THE_SYNC_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ reg_wr <= reg_wr_x;\r
+ end if;\r
+end process THE_SYNC_PROC;\r
+\r
+---------------------------------------------------------\r
+-- output signals --\r
+---------------------------------------------------------\r
+ctrl_0_out <= ctrl_reg(0);\r
+ctrl_1_out <= ctrl_reg(1);\r
+ctrl_2_out <= ctrl_reg(2);\r
+ctrl_3_out <= ctrl_reg(3);\r
+ctrl_4_out <= ctrl_reg(4);\r
+ctrl_5_out <= ctrl_reg(5);\r
+ctrl_6_out <= ctrl_reg(6);\r
+ctrl_7_out <= ctrl_reg(7);\r
+ctrl_8_out <= ctrl_reg(8);\r
+ctrl_9_out <= ctrl_reg(9);\r
+ctrl_10_out <= ctrl_reg(10);\r
+ctrl_11_out <= ctrl_reg(11);\r
+ctrl_12_out <= ctrl_reg(12);\r
+ctrl_13_out <= ctrl_reg(13);\r
+ctrl_14_out <= ctrl_reg(14);\r
+ctrl_15_out <= ctrl_reg(15);\r
+\r
+slv_ack_out <= slv_ack;\r
+slv_data_out <= rdback_data;\r
+\r
+stat <= (others => '0');\r
+\r
+end Behavioral;\r
--- /dev/null
+#Format=Address-Hex\r
+#Depth=8\r
+#DataWidth=4\r
+#AddrRadix=3\r
+#DataRadix=3\r
+\r
+# This mapping memory denotes the "spare" 1Wire port, which is connected to Roman's APV.\r
+# This information can be used to replace the 1Wire ID of the non-existing APV-FE by the \r
+# backplane 1Wire ID.\r
+\r
+# IMPORTANT: KEEP IN SYNC WITH adc_onewire_mapping.mem!!!\r
+\r
+00: 4\r
+01: c\r
+02: 6\r
+03: a\r
+04: 0\r
+05: f\r
+06: f\r
+07: f\r
--- /dev/null
+library IEEE;\r
+use IEEE.STD_LOGIC_1164.ALL;\r
+use IEEE.STD_LOGIC_ARITH.ALL;\r
+use IEEE.STD_LOGIC_UNSIGNED.ALL;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+entity spi_adc_master is\r
+generic( RESET_VALUE_CTRL : std_logic_vector(7 downto 0) := x"60" );\r
+port( CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_BUSY_OUT : out std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- SPI connections\r
+ SPI_CS_OUT : out std_logic;\r
+ SPI_SDO_OUT : out std_logic;\r
+ SPI_SCK_OUT : out std_logic;\r
+ -- ADC connections\r
+ ADC_LOCKED_IN : in std_logic;\r
+ ADC_PD_OUT : out std_logic;\r
+ ADC_RST_OUT : out std_logic;\r
+ ADC_DEL_OUT : out std_logic_vector(3 downto 0);\r
+ -- APV connections\r
+ APV_RST_OUT : out std_logic;\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+ );\r
+end entity;\r
+\r
+architecture Behavioral of spi_adc_master is\r
+\r
+-- Signals\r
+ type STATES is (SLEEP,RD_BSY,WR_BSY,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE);\r
+ signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+ signal status_data : std_logic_vector(31 downto 0);\r
+ signal spi_busy : std_logic;\r
+ \r
+ signal reg_ctrl_data : std_logic_vector(7 downto 0); \r
+ signal adc_ctrl_data : std_logic_vector(7 downto 0); \r
+ \r
+ signal reg_slv_data_out : std_logic_vector(31 downto 0); -- readback\r
+ \r
+ signal spi_start_x : std_logic;\r
+ signal spi_start : std_logic;\r
+ \r
+ -- State machine signals\r
+ signal slv_busy_x : std_logic;\r
+ signal slv_busy : std_logic;\r
+ signal slv_ack_x : std_logic;\r
+ signal slv_ack : std_logic;\r
+ signal store_wr_x : std_logic;\r
+ signal store_wr : std_logic;\r
+ signal store_rd_x : std_logic;\r
+ signal store_rd : std_logic;\r
+\r
+begin\r
+\r
+---------------------------------------------------------\r
+-- SPI master --\r
+---------------------------------------------------------\r
+\r
+THE_SPI_REAL_SLIM: spi_real_slim\r
+port map( SYSCLK => clk_in,\r
+ RESET => reset_in,\r
+ -- Command interface\r
+ START_IN => spi_start,\r
+ BUSY_OUT => spi_busy,\r
+ CMD_IN => reg_ctrl_data,\r
+ -- SPI interface\r
+ SPI_SCK_OUT => spi_sck_out,\r
+ SPI_CS_OUT => spi_cs_out,\r
+ SPI_SDO_OUT => spi_sdo_out,\r
+ -- DEBUG\r
+ CLK_EN_OUT => open,\r
+ BSM_OUT => open,\r
+ DEBUG_OUT => open\r
+ );\r
+\r
+---------------------------------------------------------\r
+-- Statemachine --\r
+---------------------------------------------------------\r
+-- State memory process\r
+STATE_MEM: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ CURRENT_STATE <= SLEEP;\r
+ slv_busy <= '0';\r
+ slv_ack <= '0';\r
+ store_wr <= '0';\r
+ store_rd <= '0';\r
+ else\r
+ CURRENT_STATE <= NEXT_STATE;\r
+ slv_busy <= slv_busy_x;\r
+ slv_ack <= slv_ack_x;\r
+ store_wr <= store_wr_x;\r
+ store_rd <= store_rd_x;\r
+ end if;\r
+ end if;\r
+end process STATE_MEM;\r
+\r
+-- Transition matrix\r
+TRANSFORM: process(CURRENT_STATE, slv_read_in, slv_write_in, spi_busy )\r
+begin\r
+ NEXT_STATE <= SLEEP;\r
+ slv_busy_x <= '0';\r
+ slv_ack_x <= '0';\r
+ store_wr_x <= '0';\r
+ store_rd_x <= '0';\r
+ case CURRENT_STATE is\r
+ when SLEEP => if ( (spi_busy = '0') and (slv_read_in = '1') ) then\r
+ NEXT_STATE <= RD_RDY;\r
+ store_rd_x <= '1';\r
+ elsif( (spi_busy = '0') and (slv_write_in = '1') ) then\r
+ NEXT_STATE <= WR_RDY;\r
+ store_wr_x <= '1';\r
+ elsif( (spi_busy = '1') and (slv_read_in = '1') ) then\r
+ NEXT_STATE <= RD_BSY;\r
+ slv_busy_x <= '1';\r
+ elsif( (spi_busy = '1') and (slv_write_in = '1') ) then\r
+ NEXT_STATE <= WR_BSY;\r
+ slv_busy_x <= '1';\r
+ else \r
+ NEXT_STATE <= SLEEP;\r
+ end if;\r
+ when RD_RDY => NEXT_STATE <= RD_ACK;\r
+ slv_ack_x <= '1';\r
+ when WR_RDY => NEXT_STATE <= WR_ACK;\r
+ slv_ack_x <= '1';\r
+ when RD_ACK => if( slv_read_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ else\r
+ NEXT_STATE <= RD_ACK;\r
+ slv_ack_x <= '1';\r
+ end if;\r
+ when WR_ACK => if( slv_write_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ else\r
+ NEXT_STATE <= WR_ACK;\r
+ slv_ack_x <= '1';\r
+ end if;\r
+ when RD_BSY => if( slv_read_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ else\r
+ NEXT_STATE <= RD_BSY;\r
+ slv_busy_x <= '1';\r
+ end if;\r
+ when WR_BSY => if( slv_write_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ else\r
+ NEXT_STATE <= WR_BSY;\r
+ slv_busy_x <= '1';\r
+ end if;\r
+ when DONE => NEXT_STATE <= SLEEP;\r
+ \r
+ when others => NEXT_STATE <= SLEEP;\r
+ end case;\r
+end process TRANSFORM;\r
+\r
+---------------------------------------------------------\r
+-- data handling --\r
+---------------------------------------------------------\r
+\r
+-- register write\r
+THE_WRITE_REG_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( reset_in = '1' ) then\r
+ reg_ctrl_data <= (others => '0');\r
+ adc_ctrl_data <= RESET_VALUE_CTRL;\r
+ spi_start <= '0';\r
+ elsif( store_wr = '1' ) then\r
+ reg_ctrl_data <= slv_data_in(31 downto 24);\r
+ adc_ctrl_data <= slv_data_in(7 downto 0);\r
+ end if;\r
+ spi_start <= spi_start_x;\r
+ end if;\r
+end process THE_WRITE_REG_PROC;\r
+\r
+spi_start_x <= '1' when ( (store_wr = '1') and (slv_data_in(3) = '1') ) else '0';\r
+\r
+-- register read\r
+THE_READ_REG_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( reset_in = '1' ) then\r
+ reg_slv_data_out <= (others => '0');\r
+ elsif( store_rd = '1' ) then\r
+ reg_slv_data_out <= reg_ctrl_data & x"000" & b"000" & adc_locked_in & adc_ctrl_data;\r
+ end if;\r
+ end if;\r
+end process THE_READ_REG_PROC;\r
+\r
+-- debug signals\r
+status_data(31 downto 0) <= (others => '0');\r
+\r
+-- output signals\r
+adc_del_out <= adc_ctrl_data(7 downto 4);\r
+apv_rst_out <= adc_ctrl_data(2);\r
+adc_pd_out <= adc_ctrl_data(1);\r
+adc_rst_out <= not adc_ctrl_data(0);\r
+\r
+stat <= status_data;\r
+slv_ack_out <= slv_ack;\r
+slv_busy_out <= slv_busy;\r
+slv_data_out <= reg_slv_data_out;\r
+\r
+end Behavioral;\r
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.std_logic_unsigned.all;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+\r
+entity spi_real_slim is\r
+ port( SYSCLK : in std_logic; -- 100MHz sysclock\r
+ RESET : in std_logic; -- synchronous reset\r
+ -- Command interface\r
+ START_IN : in std_logic; -- one start pulse\r
+ BUSY_OUT : out std_logic; -- SPI transactions are ongoing\r
+ CMD_IN : in std_logic_vector(7 downto 0); -- SPI command byte\r
+ -- SPI interface\r
+ SPI_SCK_OUT : out std_logic;\r
+ SPI_CS_OUT : out std_logic;\r
+ SPI_SDO_OUT : out std_logic;\r
+ -- DEBUG\r
+ CLK_EN_OUT : out std_logic;\r
+ BSM_OUT : out std_logic_vector(7 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(31 downto 0)\r
+ );\r
+end spi_real_slim;\r
+\r
+architecture Behavioral of spi_real_slim is\r
+\r
+-- new clock divider\r
+signal div_counter : std_logic_vector(1 downto 0);\r
+signal div_done_x : std_logic;\r
+signal div_done : std_logic; -- same as clk_en\r
+signal clk_en : std_logic; -- same as div_done\r
+\r
+-- Statemachine signals\r
+type state_t is (IDLE,CSL,TXCMD,CSH);\r
+signal STATE, NEXT_STATE : state_t;\r
+\r
+signal tx_ena_x : std_logic;\r
+signal tx_ena : std_logic;\r
+signal busy_x : std_logic;\r
+signal busy : std_logic;\r
+signal spi_cs_x : std_logic; -- SPI chip select (low active)\r
+signal spi_cs : std_logic;\r
+signal spi_sck_x : std_logic; -- SPI clock (rising edge active, from counter)\r
+signal spi_sck : std_logic;\r
+signal tx_load_x : std_logic; -- load TX shift register\r
+signal tx_load : std_logic;\r
+\r
+signal last_tx_bit_x : std_logic;\r
+signal last_tx_bit : std_logic;\r
+\r
+-- debug signals\r
+signal bsm_x : std_logic_vector(7 downto 0);\r
+signal debug_x : std_logic_vector(31 downto 0);\r
+\r
+signal start : std_logic; -- buffered start_in signal, as we have a clocked down state machine\r
+signal cmd_int : std_logic_vector(7 downto 0); -- internal command and address bytes\r
+\r
+-- transmitter\r
+signal tx_sreg : std_logic_vector(7 downto 0);\r
+signal tx_reg_comb : std_logic_vector(7 downto 0); -- multiplexer\r
+signal tx_bit_cnt : std_logic_vector(3 downto 0);\r
+\r
+begin\r
+\r
+-----------------------------------------------------------\r
+-- Debug signals\r
+-----------------------------------------------------------\r
+debug_x(31 downto 24) <= tx_sreg; --(others => '0');\r
+debug_x(23 downto 20) <= tx_bit_cnt; --(others => '0');\r
+debug_x(19 downto 16) <= (others => '0');\r
+debug_x(15) <= '0';\r
+debug_x(14) <= '0';\r
+debug_x(13) <= '0';\r
+debug_x(12) <= '0';\r
+debug_x(11) <= last_tx_bit;\r
+debug_x(10) <= '0';\r
+debug_x(9) <= '0';\r
+debug_x(8) <= '0';\r
+debug_x(7) <= '0';\r
+debug_x(6) <= '0';\r
+debug_x(5) <= tx_load;\r
+debug_x(4) <= tx_ena;\r
+debug_x(3) <= '0'; \r
+debug_x(2 downto 0) <= (others => '0');\r
+\r
+\r
+-----------------------------------------------------------\r
+-- SPI clock generator\r
+-----------------------------------------------------------\r
+THE_CLOCK_DIVIDER: process( sysclk )\r
+begin\r
+ if( rising_edge(sysclk) ) then\r
+ if( reset = '1' ) then\r
+ div_counter <= (others => '0');\r
+ div_done <= '0';\r
+ spi_sck <= '0';\r
+ else\r
+ div_counter <= div_counter + 1;\r
+ div_done <= div_done_x;\r
+ spi_sck <= spi_sck_x;\r
+ end if;\r
+ end if;\r
+end process THE_CLOCK_DIVIDER;\r
+\r
+div_done_x <= '1' when ( div_counter = b"00" ) else '0';\r
+\r
+spi_sck_x <= '1' when ( ((div_counter = b"11") or (div_counter = b"00")) and\r
+ (tx_ena = '1') ) else '0';\r
+\r
+clk_en <= div_done;\r
+\r
+-----------------------------------------------------------\r
+-- start signal and local register sets for CMD and ADR\r
+-----------------------------------------------------------\r
+THE_START_PROC: process( sysclk )\r
+begin\r
+ if( rising_edge(sysclk) ) then\r
+ if ( reset = '1' ) then\r
+ start <= '0';\r
+ cmd_int <= (others => '0');\r
+ elsif( (start_in = '1') and (busy = '0') ) then\r
+ start <= '1';\r
+ cmd_int <= cmd_in;\r
+ elsif( busy = '1' ) then\r
+ start <= '0';\r
+ end if;\r
+ end if;\r
+end process THE_START_PROC;\r
+\r
+-----------------------------------------------------------\r
+-- statemachine: clocked process\r
+-----------------------------------------------------------\r
+THE_STATEMACHINE: process( sysclk )\r
+begin\r
+ if( rising_edge(sysclk) ) then\r
+ if ( reset = '1' ) then\r
+ STATE <= IDLE;\r
+ tx_ena <= '0';\r
+ busy <= '0';\r
+ spi_cs <= '1';\r
+ tx_load <= '0';\r
+ elsif( clk_en = '1' ) then\r
+ STATE <= NEXT_STATE;\r
+ tx_ena <= tx_ena_x;\r
+ busy <= busy_x;\r
+ spi_cs <= spi_cs_x;\r
+ tx_load <= tx_load_x;\r
+ end if;\r
+ end if;\r
+end process THE_STATEMACHINE;\r
+\r
+-----------------------------------------------------------\r
+-- state machine transition table\r
+-----------------------------------------------------------\r
+THE_STATE_TRANSITIONS: process( STATE, start, tx_bit_cnt )\r
+begin\r
+ tx_ena_x <= '0';\r
+ busy_x <= '1';\r
+ spi_cs_x <= '1';\r
+ tx_load_x <= '0';\r
+ case STATE is\r
+ when IDLE =>\r
+ if( start = '1' ) then\r
+ NEXT_STATE <= CSL;\r
+ spi_cs_x <= '0';\r
+ tx_load_x <= '1';\r
+ else\r
+ NEXT_STATE <= IDLE;\r
+ busy_x <= '0';\r
+ end if;\r
+\r
+ when CSL =>\r
+ NEXT_STATE <= TXCMD;\r
+ tx_ena_x <= '1';\r
+ spi_cs_x <= '0';\r
+\r
+ when TXCMD =>\r
+ if( tx_bit_cnt < x"7" ) then\r
+ NEXT_STATE <= TXCMD;\r
+ tx_ena_x <= '1';\r
+ spi_cs_x <= '0';\r
+ else\r
+ NEXT_STATE <= CSH;\r
+ spi_cs_x <= '0';\r
+ end if;\r
+\r
+ when CSH =>\r
+ NEXT_STATE <= IDLE;\r
+ busy_x <= '0';\r
+\r
+ when others =>\r
+ NEXT_STATE <= IDLE;\r
+\r
+ end case;\r
+end process THE_STATE_TRANSITIONS;\r
+\r
+-- state machine output table\r
+THE_STATEMACHINE_OUT: process( STATE )\r
+begin\r
+ case STATE is\r
+ when IDLE => bsm_x <= x"00";\r
+ when CSL => bsm_x <= x"01";\r
+ when TXCMD => bsm_x <= x"02";\r
+ when CSH => bsm_x <= x"03";\r
+ when others => bsm_x <= x"ff";\r
+ end case;\r
+end process THE_STATEMACHINE_OUT;\r
+\r
+-- We only use one CMD byte\r
+tx_reg_comb <= cmd_int;\r
+\r
+-- TXData shift register and bit counter\r
+THE_TX_SHIFT_AND_BITCOUNT: process( sysclk )\r
+begin\r
+ if( rising_edge(sysclk) ) then\r
+ if ( (clk_en = '1' ) and (tx_load = '1') ) then\r
+ tx_bit_cnt <= (others => '0');\r
+ tx_sreg <= tx_reg_comb;\r
+ elsif( (clk_en = '1') and (tx_ena = '1') ) then\r
+ tx_bit_cnt <= tx_bit_cnt + 1;\r
+ tx_sreg <= tx_sreg (6 downto 0) & '0';\r
+ end if;\r
+ last_tx_bit <= last_tx_bit_x;\r
+ end if;\r
+end process THE_TX_SHIFT_AND_BITCOUNT;\r
+\r
+last_tx_bit_x <= '1' when ( tx_bit_cnt = x"7" ) else '0';\r
+\r
+-- output signals\r
+spi_cs_out <= spi_cs;\r
+spi_sck_out <= spi_sck;\r
+spi_sdo_out <= tx_sreg(7);\r
+busy_out <= busy;\r
+\r
+clk_en_out <= clk_en;\r
+bsm_out <= bsm_x;\r
+debug_out <= debug_x;\r
+\r
+\r
+end Behavioral;\r
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.std_logic_arith.all;\r
+use ieee.std_logic_unsigned.all;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+entity state_sync is\r
+ port( STATE_A_IN : in std_logic;\r
+ RESET_B_IN : in std_logic;\r
+ CLK_B_IN : in std_logic;\r
+ STATE_B_OUT : out std_logic\r
+ );\r
+end;\r
+\r
+architecture behavioral of state_sync is\r
+\r
+ -- normal signals\r
+ signal sync_q : std_logic;\r
+ signal sync_qq : std_logic;\r
+ \r
+begin\r
+\r
+-- synchronizing stage for clock domain B\r
+THE_SYNC_STAGE_PROC: process( clk_b_in )\r
+begin\r
+ if( rising_edge(clk_b_in) ) then\r
+ if( reset_b_in = '1' ) then\r
+ sync_q <= '0'; sync_qq <= '0';\r
+ else\r
+ sync_qq <= sync_q;\r
+ sync_q <= state_a_in;\r
+ end if;\r
+ end if;\r
+end process THE_SYNC_STAGE_PROC;\r
+\r
+-- output signals\r
+state_b_out <= sync_qq;\r
+\r
+end behavioral;\r
--- /dev/null
+[Device]\r
+Family=latticeecp2m\r
+PartType=LFE2M100E\r
+PartName=LFE2M100E-6F900C\r
+SpeedGrade=-6\r
+Package=FPBGA900\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=Subtractor\r
+CoreRevision=3.1\r
+ModuleName=suber_12bit\r
+SourceFormat=VHDL\r
+ParameterFileVersion=1.0\r
+Date=10/27/2009\r
+Time=16:54:01\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+InputWidth=12\r
+Representation=Unsigned\r
+UseCIport=0\r
+COport=None\r
+OutReg=1\r
+Complex=0\r
+Stage=0\r
--- /dev/null
+SCUBA, Version ispLever_v72_SP2_Build (23)
+Tue Oct 27 16:54:01 2009
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp. All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
+Copyright (c) 2001 Agere Systems All rights reserved.
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
+
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n suber_12bit -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type mgaddsub -direction sub -width 12 -unsigned -output_reg -enable -pipeline 0 -e
+ Circuit name : suber_12bit
+ Module type : sub
+ Module Version : 3.1
+ Width : 12
+ Ports :
+ Inputs : DataA[11:0], DataB[11:0], Clock, Reset, ClockEn
+ Outputs : Result[11:0]
+ I/O buffer : not inserted
+ Representation : unsigned number
+ EDIF output : suppressed
+ VHDL output : suber_12bit.vhd
+ VHDL template : suber_12bit_tmpl.vhd
+ VHDL testbench : tb_suber_12bit_tmpl.vhd
+ VHDL purpose : for synthesis and simulation
+ Bus notation : big endian
+ Report output : suber_12bit.srp
+ Element Usage :
+ FSUB2B : 7
+ FD1P3DX : 12
+ Estimated Resource Usage:
+ LUT : 14
+ Reg : 12
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23)
+-- Module Version: 3.1
+--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type sub -width 12 -unsigned -output_reg -enable -pipeline 0 -e
+
+-- Tue Oct 27 16:54:01 2009
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity suber_12bit is
+ port (
+ DataA: in std_logic_vector(11 downto 0);
+ DataB: in std_logic_vector(11 downto 0);
+ Clock: in std_logic;
+ Reset: in std_logic;
+ ClockEn: in std_logic;
+ Result: out std_logic_vector(11 downto 0));
+end suber_12bit;
+
+architecture Structure of suber_12bit is
+
+ -- internal signal declarations
+ signal r0_diff11: std_logic;
+ signal r0_diff10: std_logic;
+ signal r0_diff9: std_logic;
+ signal r0_diff8: std_logic;
+ signal r0_diff7: std_logic;
+ signal r0_diff6: std_logic;
+ signal r0_diff5: std_logic;
+ signal r0_diff4: std_logic;
+ signal r0_diff3: std_logic;
+ signal r0_diff2: std_logic;
+ signal r0_diff1: std_logic;
+ signal r0_diff0: std_logic;
+ signal tdiff0: std_logic;
+ signal scuba_vhi: std_logic;
+ signal tdiff1: std_logic;
+ signal tdiff2: std_logic;
+ signal co0: std_logic;
+ signal tdiff3: std_logic;
+ signal tdiff4: std_logic;
+ signal co1: std_logic;
+ signal tdiff5: std_logic;
+ signal tdiff6: std_logic;
+ signal co2: std_logic;
+ signal tdiff7: std_logic;
+ signal tdiff8: std_logic;
+ signal co3: std_logic;
+ signal tdiff9: std_logic;
+ signal tdiff10: std_logic;
+ signal co4: std_logic;
+ signal tdiff11: std_logic;
+ signal co5: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component FSUB2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; BI: in std_logic; BOUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FD1P3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ attribute GSR : string;
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ FF_11: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>tdiff11, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>r0_diff11);
+
+ FF_10: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>tdiff10, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>r0_diff10);
+
+ FF_9: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>tdiff9, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>r0_diff9);
+
+ FF_8: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>tdiff8, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>r0_diff8);
+
+ FF_7: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>tdiff7, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>r0_diff7);
+
+ FF_6: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>tdiff6, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>r0_diff6);
+
+ FF_5: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>tdiff5, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>r0_diff5);
+
+ FF_4: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>tdiff4, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>r0_diff4);
+
+ FF_3: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>tdiff3, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>r0_diff3);
+
+ FF_2: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>tdiff2, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>r0_diff2);
+
+ FF_1: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>tdiff1, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>r0_diff1);
+
+ FF_0: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>tdiff0, SP=>ClockEn, CK=>Clock, CD=>Reset,
+ Q=>r0_diff0);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ addsub_0: FSUB2B
+ port map (A0=>scuba_vhi, A1=>DataA(0), B0=>scuba_vlo,
+ B1=>DataB(0), BI=>scuba_vlo, BOUT=>co0, S0=>open, S1=>tdiff0);
+
+ addsub_1: FSUB2B
+ port map (A0=>DataA(1), A1=>DataA(2), B0=>DataB(1), B1=>DataB(2),
+ BI=>co0, BOUT=>co1, S0=>tdiff1, S1=>tdiff2);
+
+ addsub_2: FSUB2B
+ port map (A0=>DataA(3), A1=>DataA(4), B0=>DataB(3), B1=>DataB(4),
+ BI=>co1, BOUT=>co2, S0=>tdiff3, S1=>tdiff4);
+
+ addsub_3: FSUB2B
+ port map (A0=>DataA(5), A1=>DataA(6), B0=>DataB(5), B1=>DataB(6),
+ BI=>co2, BOUT=>co3, S0=>tdiff5, S1=>tdiff6);
+
+ addsub_4: FSUB2B
+ port map (A0=>DataA(7), A1=>DataA(8), B0=>DataB(7), B1=>DataB(8),
+ BI=>co3, BOUT=>co4, S0=>tdiff7, S1=>tdiff8);
+
+ addsub_5: FSUB2B
+ port map (A0=>DataA(9), A1=>DataA(10), B0=>DataB(9),
+ B1=>DataB(10), BI=>co4, BOUT=>co5, S0=>tdiff9, S1=>tdiff10);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ addsub_6: FSUB2B
+ port map (A0=>DataA(11), A1=>scuba_vlo, B0=>DataB(11),
+ B1=>scuba_vlo, BI=>co5, BOUT=>open, S0=>tdiff11, S1=>open);
+
+ Result(11) <= r0_diff11;
+ Result(10) <= r0_diff10;
+ Result(9) <= r0_diff9;
+ Result(8) <= r0_diff8;
+ Result(7) <= r0_diff7;
+ Result(6) <= r0_diff6;
+ Result(5) <= r0_diff5;
+ Result(4) <= r0_diff4;
+ Result(3) <= r0_diff3;
+ Result(2) <= r0_diff2;
+ Result(1) <= r0_diff1;
+ Result(0) <= r0_diff0;
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of suber_12bit is
+ for Structure
+ for all:FSUB2B use entity ecp2m.FSUB2B(V); end for;
+ for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
+ for all:VHI use entity ecp2m.VHI(V); end for;
+ for all:VLO use entity ecp2m.VLO(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+Starting process: \r
+\r
+SCUBA, Version ispLever_v72_SP2_Build (23)\r
+Tue Oct 27 16:54:01 2009\r
+\r
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.\r
+Copyright (c) 1995 AT&T Corp. All rights reserved.\r
+Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.\r
+Copyright (c) 2001 Agere Systems All rights reserved.\r
+Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.\r
+\r
+BEGIN SCUBA Module Synthesis\r
+\r
+ Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n suber_12bit -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type mgaddsub -direction sub -width 12 -unsigned -output_reg -enable -pipeline 0 -e \r
+ Circuit name : suber_12bit\r
+ Module type : sub\r
+ Module Version : 3.1\r
+ Width : 12\r
+ Ports : \r
+ Inputs : DataA[11:0], DataB[11:0], Clock, Reset, ClockEn\r
+ Outputs : Result[11:0]\r
+ I/O buffer : not inserted\r
+ Representation : unsigned number\r
+ EDIF output : suppressed\r
+ VHDL output : suber_12bit.vhd\r
+ VHDL template : suber_12bit_tmpl.vhd\r
+ VHDL testbench : tb_suber_12bit_tmpl.vhd\r
+ VHDL purpose : for synthesis and simulation\r
+ Bus notation : big endian\r
+ Report output : suber_12bit.srp\r
+ Estimated Resource Usage:\r
+ LUT : 14\r
+ Reg : 12\r
+\r
+END SCUBA Module Synthesis\r
+\r
+File: suber_12bit.lpc created.\r
+\r
+\r
+End process: completed successfully.\r
+\r
+\r
+Total Warnings: 0\r
+\r
+Total Errors: 0\r
+\r
+\r
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23)
+-- Module Version: 3.1
+-- Tue Oct 27 16:54:01 2009
+
+-- parameterized module component declaration
+component suber_12bit
+ port (DataA: in std_logic_vector(11 downto 0);
+ DataB: in std_logic_vector(11 downto 0); Clock: in std_logic;
+ Reset: in std_logic; ClockEn: in std_logic;
+ Result: out std_logic_vector(11 downto 0));
+end component;
+
+-- parameterized module component instance
+__ : suber_12bit
+ port map (DataA(11 downto 0)=>__, DataB(11 downto 0)=>__, Clock=>__,
+ Reset=>__, ClockEn=>__, Result(11 downto 0)=>__);
--- /dev/null
+-- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23)
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity tb is
+end entity tb;
+
+
+architecture test of tb is
+
+ component adc_apv_map_mem
+ port (Address : in std_logic_vector(6 downto 0);
+ Q : out std_logic_vector(3 downto 0)
+ );
+ end component;
+
+ signal Address : std_logic_vector(6 downto 0) := (others => '0');
+ signal Q : std_logic_vector(3 downto 0);
+begin
+ u1 : adc_apv_map_mem
+ port map (Address => Address, Q => Q
+ );
+
+ process
+
+ begin
+ Address <= (others => '0') ;
+ wait for 100 ns;
+ wait for 10 ns;
+ for i in 0 to 131 loop
+ wait for 10 ns;
+ Address <= Address + '1' ;
+ end loop;
+ wait;
+ end process;
+
+end architecture test;
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT adc_data_handler\r
+ PORT(\r
+ RESET_IN : IN std_logic;\r
+ RESET_PLL_IN : IN std_logic;\r
+ ADC_LCLK_IN : IN std_logic;\r
+ ADC_ADCLK_IN : IN std_logic;\r
+ ADC_CHNL_IN : IN std_logic_vector(7 downto 0);\r
+ PLL_CTRL_IN : IN std_logic_vector(3 downto 0); \r
+ PLL_LOCK_OUT : OUT std_logic;\r
+ CLK40M_OUT : OUT std_logic;\r
+ ADC_ADCLK_OUT : OUT std_logic;\r
+ ADC_DATA7_OUT : OUT std_logic_vector(11 downto 0);\r
+ ADC_DATA6_OUT : OUT std_logic_vector(11 downto 0);\r
+ ADC_DATA5_OUT : OUT std_logic_vector(11 downto 0);\r
+ ADC_DATA4_OUT : OUT std_logic_vector(11 downto 0);\r
+ ADC_DATA3_OUT : OUT std_logic_vector(11 downto 0);\r
+ ADC_DATA2_OUT : OUT std_logic_vector(11 downto 0);\r
+ ADC_DATA1_OUT : OUT std_logic_vector(11 downto 0);\r
+ ADC_DATA0_OUT : OUT std_logic_vector(11 downto 0);\r
+ DEBUG_OUT : OUT std_logic_vector(15 downto 0)\r
+ );\r
+ END COMPONENT;\r
+\r
+ COMPONENT adc_crossover\r
+ PORT(\r
+ CLK_APV_IN : IN std_logic;\r
+ RESET_IN : IN std_logic;\r
+ ADC_CLK_IN : IN std_logic;\r
+ ADC_CE_IN : IN std_logic;\r
+ ADC_PLL_LOCKED_IN : IN std_logic;\r
+ ADC_DATA_0_IN : IN std_logic_vector(11 downto 0);\r
+ ADC_DATA_1_IN : IN std_logic_vector(11 downto 0);\r
+ ADC_DATA_2_IN : IN std_logic_vector(11 downto 0);\r
+ ADC_DATA_3_IN : IN std_logic_vector(11 downto 0);\r
+ ADC_DATA_4_IN : IN std_logic_vector(11 downto 0);\r
+ ADC_DATA_5_IN : IN std_logic_vector(11 downto 0);\r
+ ADC_DATA_6_IN : IN std_logic_vector(11 downto 0);\r
+ ADC_DATA_7_IN : IN std_logic_vector(11 downto 0); \r
+ LEVEL_WR_OUT : OUT std_logic_vector(4 downto 0);\r
+ APV_DATA_0_OUT : OUT std_logic_vector(11 downto 0);\r
+ APV_DATA_1_OUT : OUT std_logic_vector(11 downto 0);\r
+ APV_DATA_2_OUT : OUT std_logic_vector(11 downto 0);\r
+ APV_DATA_3_OUT : OUT std_logic_vector(11 downto 0);\r
+ APV_DATA_4_OUT : OUT std_logic_vector(11 downto 0);\r
+ APV_DATA_5_OUT : OUT std_logic_vector(11 downto 0);\r
+ APV_DATA_6_OUT : OUT std_logic_vector(11 downto 0);\r
+ APV_DATA_7_OUT : OUT std_logic_vector(11 downto 0);\r
+ APV_DATA_VALID_OUT : OUT std_logic;\r
+ LEVEL_RD_OUT : OUT std_logic_vector(4 downto 0);\r
+ DEBUG_OUT : OUT std_logic_vector(31 downto 0)\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL CLK_APV_IN : std_logic;\r
+ SIGNAL ADC_CE_IN : std_logic;\r
+ SIGNAL LEVEL_WR_OUT : std_logic_vector(4 downto 0);\r
+ SIGNAL LEVEL_RD_OUT : std_logic_vector(4 downto 0);\r
+ SIGNAL APV_DATA_0_OUT : std_logic_vector(11 downto 0);\r
+ SIGNAL APV_DATA_1_OUT : std_logic_vector(11 downto 0);\r
+ SIGNAL APV_DATA_2_OUT : std_logic_vector(11 downto 0);\r
+ SIGNAL APV_DATA_3_OUT : std_logic_vector(11 downto 0);\r
+ SIGNAL APV_DATA_4_OUT : std_logic_vector(11 downto 0);\r
+ SIGNAL APV_DATA_5_OUT : std_logic_vector(11 downto 0);\r
+ SIGNAL APV_DATA_6_OUT : std_logic_vector(11 downto 0);\r
+ SIGNAL APV_DATA_7_OUT : std_logic_vector(11 downto 0);\r
+ SIGNAL APV_DATA_VALID_OUT : std_logic;\r
+ SIGNAL DEBUG2_OUT : std_logic_vector(31 downto 0);\r
+\r
+ SIGNAL CLK40M_INT : std_logic;\r
+ SIGNAL PLL_LOCK_INT : std_logic;\r
+ SIGNAL ADC_DATA_7_INT : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC_DATA_6_INT : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC_DATA_5_INT : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC_DATA_4_INT : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC_DATA_3_INT : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC_DATA_2_INT : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC_DATA_1_INT : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC_DATA_0_INT : std_logic_vector(11 downto 0);\r
+ \r
+ \r
+ SIGNAL RESET_IN : std_logic;\r
+ SIGNAL RESET_PLL_IN : std_logic;\r
+ SIGNAL ADC_LCLK_IN : std_logic;\r
+ SIGNAL ADC_ADCLK_IN : std_logic;\r
+ SIGNAL ADC_CHNL_IN : std_logic_vector(7 downto 0);\r
+ SIGNAL PLL_CTRL_IN : std_logic_vector(3 downto 0);\r
+-- SIGNAL ADC_ADCLK_OUT : std_logic;\r
+ SIGNAL DEBUG1_OUT : std_logic_vector(15 downto 0);\r
+\r
+ signal adc_0_real : std_logic_vector(11 downto 0);\r
+ signal adc_7_real : std_logic_vector(11 downto 0);\r
+\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut1: adc_data_handler PORT MAP(\r
+ RESET_IN => RESET_IN,\r
+ RESET_PLL_IN => RESET_PLL_IN,\r
+ ADC_LCLK_IN => ADC_LCLK_IN,\r
+ ADC_ADCLK_IN => ADC_ADCLK_IN,\r
+ ADC_CHNL_IN => ADC_CHNL_IN,\r
+ PLL_CTRL_IN => PLL_CTRL_IN,\r
+ PLL_LOCK_OUT => PLL_LOCK_INT,\r
+ CLK40M_OUT => CLK40M_INT,\r
+ ADC_ADCLK_OUT => ADC_CE_IN, --open,\r
+ ADC_DATA7_OUT => ADC_DATA_7_INT,\r
+ ADC_DATA6_OUT => ADC_DATA_6_INT,\r
+ ADC_DATA5_OUT => ADC_DATA_5_INT,\r
+ ADC_DATA4_OUT => ADC_DATA_4_INT,\r
+ ADC_DATA3_OUT => ADC_DATA_3_INT,\r
+ ADC_DATA2_OUT => ADC_DATA_2_INT,\r
+ ADC_DATA1_OUT => ADC_DATA_1_INT,\r
+ ADC_DATA0_OUT => ADC_DATA_0_INT,\r
+ DEBUG_OUT => DEBUG1_OUT\r
+ );\r
+\r
+ uut2: adc_crossover PORT MAP(\r
+ CLK_APV_IN => CLK_APV_IN,\r
+ RESET_IN => RESET_IN,\r
+ ADC_CLK_IN => ADC_LCLK_IN, --CLK40M_INT,\r
+ ADC_CE_IN => ADC_CE_IN,\r
+ ADC_PLL_LOCKED_IN => PLL_LOCK_INT,\r
+ ADC_DATA_0_IN => ADC_DATA_0_INT,\r
+ ADC_DATA_1_IN => ADC_DATA_1_INT,\r
+ ADC_DATA_2_IN => ADC_DATA_2_INT,\r
+ ADC_DATA_3_IN => ADC_DATA_3_INT,\r
+ ADC_DATA_4_IN => ADC_DATA_4_INT,\r
+ ADC_DATA_5_IN => ADC_DATA_5_INT,\r
+ ADC_DATA_6_IN => ADC_DATA_6_INT,\r
+ ADC_DATA_7_IN => ADC_DATA_7_INT,\r
+ LEVEL_WR_OUT => LEVEL_WR_OUT,\r
+ APV_DATA_0_OUT => APV_DATA_0_OUT,\r
+ APV_DATA_1_OUT => APV_DATA_1_OUT,\r
+ APV_DATA_2_OUT => APV_DATA_2_OUT,\r
+ APV_DATA_3_OUT => APV_DATA_3_OUT,\r
+ APV_DATA_4_OUT => APV_DATA_4_OUT,\r
+ APV_DATA_5_OUT => APV_DATA_5_OUT,\r
+ APV_DATA_6_OUT => APV_DATA_6_OUT,\r
+ APV_DATA_7_OUT => APV_DATA_7_OUT,\r
+ APV_DATA_VALID_OUT => APV_DATA_VALID_OUT,\r
+ LEVEL_RD_OUT => LEVEL_RD_OUT,\r
+ DEBUG_OUT => DEBUG2_OUT\r
+ );\r
+\r
+APV_CLK_GEN: process\r
+begin\r
+ clk_apv_in <= '1'; wait for 12.50 ns;\r
+ clk_apv_in <= '0'; wait for 12.50 ns;\r
+end process APV_CLK_GEN;\r
+\r
+-- 240MHz DDR clock from ADC, aka bit clock\r
+THE_CLOCK_GEN: process\r
+begin\r
+ adc_lclk_in <= '1'; wait for 2.08 ns;\r
+ adc_lclk_in <= '0'; wait for 2.08 ns;\r
+end process THE_CLOCK_GEN;\r
+\r
+-- test data generator\r
+BLA: process\r
+variable adc_0_data : unsigned(11 downto 0) := x"000";\r
+variable adc_7_data : unsigned(11 downto 0) := x"fff";\r
+variable my_bit : integer := 0;\r
+begin\r
+ \r
+ my_bit := 0;\r
+ adc_0_real <= std_logic_vector(adc_0_data);\r
+ adc_7_real <= std_logic_vector(adc_7_data);\r
+ \r
+ BIT_LOOP: for I in 0 to 5 loop\r
+\r
+ wait until rising_edge(adc_lclk_in);\r
+ wait for 1.04 ns;\r
+ if( I < 3 ) then\r
+ adc_adclk_in <= '1'; \r
+ else\r
+ adc_adclk_in <= '0'; -- second half\r
+ end if;\r
+ adc_chnl_in(7) <= adc_7_data(my_bit);\r
+ adc_chnl_in(6 downto 1) <= (others => '0');\r
+ adc_chnl_in(0) <= adc_0_data(my_bit);\r
+ my_bit := my_bit + 1;\r
+ wait until falling_edge(adc_lclk_in);\r
+ wait for 1.04 ns;\r
+ adc_chnl_in(7) <= adc_7_data(my_bit);\r
+ adc_chnl_in(6 downto 1) <= (others => '0');\r
+ adc_chnl_in(0) <= adc_0_data(my_bit);\r
+ my_bit := my_bit + 1;\r
+ \r
+ end loop BIT_LOOP;\r
+ \r
+ adc_7_data := adc_7_data - 1;\r
+ adc_0_data := adc_0_data + 1;\r
+\r
+end process BLA;\r
+\r
+\r
+THE_TEST_BENCH: process\r
+begin\r
+ -- Setup signals\r
+ reset_in <= '0';\r
+ reset_pll_in <= '0';\r
+ pll_ctrl_in <= x"6";\r
+-- adc_ce_in <= '1';\r
+ wait for 100 ns;\r
+\r
+ -- Reset all\r
+ reset_in <= '1';\r
+ wait for 100 ns;\r
+ reset_in <= '0';\r
+ wait for 100 ns;\r
+\r
+ -- Tests may start now\r
+\r
+\r
+ -- Stay a while, stay forever!\r
+ wait;\r
+ \r
+end process THE_TEST_BENCH;\r
+\r
+\r
+END;\r
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT adc_crossover\r
+ PORT(\r
+ CLK_APV_IN : IN std_logic;\r
+ RESET_IN : IN std_logic;\r
+ ADC_CLK_IN : IN std_logic;\r
+ ADC_CE_IN : IN std_logic;\r
+ ADC_PLL_LOCKED_IN : IN std_logic;\r
+ ADC_DATA_0_IN : IN std_logic_vector(11 downto 0);\r
+ ADC_DATA_1_IN : IN std_logic_vector(11 downto 0);\r
+ ADC_DATA_2_IN : IN std_logic_vector(11 downto 0);\r
+ ADC_DATA_3_IN : IN std_logic_vector(11 downto 0);\r
+ ADC_DATA_4_IN : IN std_logic_vector(11 downto 0);\r
+ ADC_DATA_5_IN : IN std_logic_vector(11 downto 0);\r
+ ADC_DATA_6_IN : IN std_logic_vector(11 downto 0);\r
+ ADC_DATA_7_IN : IN std_logic_vector(11 downto 0); \r
+ LEVEL_WR_OUT : OUT std_logic_vector(4 downto 0);\r
+ APV_DATA_0_OUT : OUT std_logic_vector(11 downto 0);\r
+ APV_DATA_1_OUT : OUT std_logic_vector(11 downto 0);\r
+ APV_DATA_2_OUT : OUT std_logic_vector(11 downto 0);\r
+ APV_DATA_3_OUT : OUT std_logic_vector(11 downto 0);\r
+ APV_DATA_4_OUT : OUT std_logic_vector(11 downto 0);\r
+ APV_DATA_5_OUT : OUT std_logic_vector(11 downto 0);\r
+ APV_DATA_6_OUT : OUT std_logic_vector(11 downto 0);\r
+ APV_DATA_7_OUT : OUT std_logic_vector(11 downto 0);\r
+ APV_DATA_VALID_OUT : OUT std_logic;\r
+ LEVEL_RD_OUT : OUT std_logic_vector(4 downto 0);\r
+ DEBUG_OUT : OUT std_logic_vector(31 downto 0)\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL CLK_APV_IN : std_logic;\r
+ SIGNAL RESET_IN : std_logic;\r
+ SIGNAL ADC_CLK_IN : std_logic;\r
+ SIGNAL ADC_CE_IN : std_logic;\r
+ SIGNAL ADC_PLL_LOCKED_IN : std_logic;\r
+ SIGNAL ADC_DATA_0_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC_DATA_1_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC_DATA_2_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC_DATA_3_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC_DATA_4_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC_DATA_5_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC_DATA_6_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC_DATA_7_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL LEVEL_WR_OUT : std_logic_vector(4 downto 0);\r
+ SIGNAL APV_DATA_0_OUT : std_logic_vector(11 downto 0);\r
+ SIGNAL APV_DATA_1_OUT : std_logic_vector(11 downto 0);\r
+ SIGNAL APV_DATA_2_OUT : std_logic_vector(11 downto 0);\r
+ SIGNAL APV_DATA_3_OUT : std_logic_vector(11 downto 0);\r
+ SIGNAL APV_DATA_4_OUT : std_logic_vector(11 downto 0);\r
+ SIGNAL APV_DATA_5_OUT : std_logic_vector(11 downto 0);\r
+ SIGNAL APV_DATA_6_OUT : std_logic_vector(11 downto 0);\r
+ SIGNAL APV_DATA_7_OUT : std_logic_vector(11 downto 0);\r
+ SIGNAL APV_DATA_VALID_OUT : std_logic;\r
+ SIGNAL LEVEL_RD_OUT : std_logic_vector(4 downto 0);\r
+ SIGNAL DEBUG_OUT : std_logic_vector(31 downto 0);\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: adc_crossover PORT MAP(\r
+ CLK_APV_IN => CLK_APV_IN,\r
+ RESET_IN => RESET_IN,\r
+ ADC_CLK_IN => ADC_CLK_IN,\r
+ ADC_CE_IN => ADC_CE_IN,\r
+ ADC_PLL_LOCKED_IN => ADC_PLL_LOCKED_IN,\r
+ ADC_DATA_0_IN => ADC_DATA_0_IN,\r
+ ADC_DATA_1_IN => ADC_DATA_1_IN,\r
+ ADC_DATA_2_IN => ADC_DATA_2_IN,\r
+ ADC_DATA_3_IN => ADC_DATA_3_IN,\r
+ ADC_DATA_4_IN => ADC_DATA_4_IN,\r
+ ADC_DATA_5_IN => ADC_DATA_5_IN,\r
+ ADC_DATA_6_IN => ADC_DATA_6_IN,\r
+ ADC_DATA_7_IN => ADC_DATA_7_IN,\r
+ LEVEL_WR_OUT => LEVEL_WR_OUT,\r
+ APV_DATA_0_OUT => APV_DATA_0_OUT,\r
+ APV_DATA_1_OUT => APV_DATA_1_OUT,\r
+ APV_DATA_2_OUT => APV_DATA_2_OUT,\r
+ APV_DATA_3_OUT => APV_DATA_3_OUT,\r
+ APV_DATA_4_OUT => APV_DATA_4_OUT,\r
+ APV_DATA_5_OUT => APV_DATA_5_OUT,\r
+ APV_DATA_6_OUT => APV_DATA_6_OUT,\r
+ APV_DATA_7_OUT => APV_DATA_7_OUT,\r
+ APV_DATA_VALID_OUT => APV_DATA_VALID_OUT,\r
+ LEVEL_RD_OUT => LEVEL_RD_OUT,\r
+ DEBUG_OUT => DEBUG_OUT\r
+ );\r
+\r
+RDCLOCK_GEN: process\r
+begin\r
+ clk_apv_in <= '1'; wait for 12.50 ns;\r
+ clk_apv_in <= '0'; wait for 12.50 ns;\r
+end process RDCLOCK_GEN;\r
+\r
+--WRCLOCK_GEN: process\r
+--begin\r
+-- adc_clk_in <= '1'; wait for 12.45 ns;\r
+-- adc_clk_in <= '0'; wait for 12.45 ns;\r
+--end process WRCLOCK_GEN;\r
+\r
+WRCLOCK_GEN: process\r
+begin\r
+ wait until rising_edge(clk_apv_in); wait for 3.33 ns; adc_clk_in <= '1';\r
+ wait until falling_edge(clk_apv_in); wait for 3.33 ns; adc_clk_in <= '0';\r
+end process WRCLOCK_GEN;\r
+\r
+THE_TEST_BENCH: process\r
+begin\r
+ -- Setup signals\r
+ adc_ce_in <= '1';\r
+ adc_data_0_in <= x"000";\r
+ adc_data_1_in <= x"000";\r
+ adc_data_2_in <= x"000";\r
+ adc_data_3_in <= x"000";\r
+ adc_data_4_in <= x"000";\r
+ adc_data_5_in <= x"000";\r
+ adc_data_6_in <= x"000";\r
+ adc_data_7_in <= x"000";\r
+ adc_pll_locked_in <= '0';\r
+ reset_in <= '0';\r
+\r
+ -- Reset all\r
+ reset_in <= '1'; wait for 50 ns;\r
+ reset_in <= '0'; wait for 50 ns;\r
+\r
+ -- Tests may start here\r
+ wait for 101 ns;\r
+ adc_pll_locked_in <= '1';\r
+ wait for 55 ns;\r
+\r
+ wait until rising_edge(adc_clk_in);\r
+ adc_data_0_in <= x"ffe";\r
+ wait until rising_edge(adc_clk_in);\r
+ adc_data_0_in <= x"001";\r
+ wait until rising_edge(adc_clk_in);\r
+ adc_data_0_in <= x"001";\r
+ wait until rising_edge(adc_clk_in);\r
+ adc_data_0_in <= x"001";\r
+ wait until rising_edge(adc_clk_in);\r
+ adc_data_0_in <= x"001";\r
+ wait until rising_edge(adc_clk_in);\r
+ adc_data_0_in <= x"001";\r
+ wait until rising_edge(adc_clk_in);\r
+ adc_data_0_in <= x"001";\r
+ wait until rising_edge(adc_clk_in);\r
+ adc_data_0_in <= x"001";\r
+ wait until rising_edge(adc_clk_in);\r
+ adc_data_0_in <= x"001";\r
+ wait until rising_edge(adc_clk_in);\r
+ adc_data_0_in <= x"001";\r
+ wait until rising_edge(adc_clk_in);\r
+ adc_data_0_in <= x"001";\r
+\r
+ wait until rising_edge(adc_clk_in);\r
+ adc_data_0_in <= x"ffd";\r
+ wait until rising_edge(adc_clk_in);\r
+ adc_data_0_in <= x"002";\r
+ wait until rising_edge(adc_clk_in);\r
+ adc_data_0_in <= x"002";\r
+ wait until rising_edge(adc_clk_in);\r
+ adc_data_0_in <= x"002";\r
+ wait until rising_edge(adc_clk_in);\r
+ adc_data_0_in <= x"002";\r
+ wait until rising_edge(adc_clk_in);\r
+ adc_data_0_in <= x"002";\r
+ wait until rising_edge(adc_clk_in);\r
+ adc_data_0_in <= x"002";\r
+ wait until rising_edge(adc_clk_in);\r
+ adc_data_0_in <= x"002";\r
+ wait until rising_edge(adc_clk_in);\r
+ adc_data_0_in <= x"002";\r
+ wait until rising_edge(adc_clk_in);\r
+ adc_data_0_in <= x"002";\r
+ wait until rising_edge(adc_clk_in);\r
+ adc_data_0_in <= x"002";\r
+\r
+ wait until rising_edge(adc_clk_in);\r
+ adc_data_0_in <= x"ffc";\r
+ wait until rising_edge(adc_clk_in);\r
+ adc_data_0_in <= x"003";\r
+ wait until rising_edge(adc_clk_in);\r
+ adc_data_0_in <= x"003";\r
+ wait until rising_edge(adc_clk_in);\r
+ adc_data_0_in <= x"003";\r
+ wait until rising_edge(adc_clk_in);\r
+ adc_data_0_in <= x"003";\r
+ wait until rising_edge(adc_clk_in);\r
+ adc_data_0_in <= x"003";\r
+ wait until rising_edge(adc_clk_in);\r
+ adc_data_0_in <= x"003";\r
+ wait until rising_edge(adc_clk_in);\r
+ adc_data_0_in <= x"003";\r
+ wait until rising_edge(adc_clk_in);\r
+ adc_data_0_in <= x"003";\r
+ wait until rising_edge(adc_clk_in);\r
+ adc_data_0_in <= x"003";\r
+ wait until rising_edge(adc_clk_in);\r
+ adc_data_0_in <= x"003";\r
+\r
+ wait until rising_edge(adc_clk_in);\r
+ adc_data_0_in <= x"ffb";\r
+ wait until rising_edge(adc_clk_in);\r
+ adc_data_0_in <= x"004";\r
+ wait until rising_edge(adc_clk_in);\r
+ adc_data_0_in <= x"004";\r
+ wait until rising_edge(adc_clk_in);\r
+ adc_data_0_in <= x"004";\r
+ wait until rising_edge(adc_clk_in);\r
+ adc_data_0_in <= x"004";\r
+ wait until rising_edge(adc_clk_in);\r
+ adc_data_0_in <= x"004";\r
+ wait until rising_edge(adc_clk_in);\r
+ adc_data_0_in <= x"004";\r
+ wait until rising_edge(adc_clk_in);\r
+ adc_data_0_in <= x"004";\r
+ wait until rising_edge(adc_clk_in);\r
+ adc_data_0_in <= x"004";\r
+ wait until rising_edge(adc_clk_in);\r
+ adc_data_0_in <= x"004";\r
+ wait until rising_edge(adc_clk_in);\r
+ adc_data_0_in <= x"004";\r
+\r
+\r
+ -- Stay a while, stay forever.\r
+ wait;\r
+\r
+end process THE_TEST_BENCH;\r
+ \r
+END;\r
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT adc_data_handler\r
+ PORT(\r
+ RESET_IN : IN std_logic;\r
+ RESET_PLL_IN : IN std_logic;\r
+ ADC_LCLK_IN : IN std_logic;\r
+ ADC_ADCLK_IN : IN std_logic;\r
+ ADC_CHNL_IN : IN std_logic_vector(7 downto 0);\r
+ PLL_CTRL_IN : IN std_logic_vector(3 downto 0); \r
+ PLL_LOCK_OUT : OUT std_logic;\r
+ CLK40M_OUT : OUT std_logic;\r
+ ADC_ADCLK_OUT : OUT std_logic;\r
+ ADC_DATA7_OUT : OUT std_logic_vector(11 downto 0);\r
+ ADC_DATA6_OUT : OUT std_logic_vector(11 downto 0);\r
+ ADC_DATA5_OUT : OUT std_logic_vector(11 downto 0);\r
+ ADC_DATA4_OUT : OUT std_logic_vector(11 downto 0);\r
+ ADC_DATA3_OUT : OUT std_logic_vector(11 downto 0);\r
+ ADC_DATA2_OUT : OUT std_logic_vector(11 downto 0);\r
+ ADC_DATA1_OUT : OUT std_logic_vector(11 downto 0);\r
+ ADC_DATA0_OUT : OUT std_logic_vector(11 downto 0);\r
+ DEBUG_OUT : OUT std_logic_vector(15 downto 0)\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL RESET_IN : std_logic;\r
+ SIGNAL RESET_PLL_IN : std_logic;\r
+ SIGNAL ADC_LCLK_IN : std_logic;\r
+ SIGNAL ADC_ADCLK_IN : std_logic;\r
+ SIGNAL ADC_CHNL_IN : std_logic_vector(7 downto 0);\r
+ SIGNAL PLL_CTRL_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL PLL_LOCK_OUT : std_logic;\r
+ SIGNAL CLK40M_OUT : std_logic;\r
+ SIGNAL ADC_ADCLK_OUT : std_logic;\r
+ SIGNAL ADC_DATA7_OUT : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC_DATA6_OUT : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC_DATA5_OUT : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC_DATA4_OUT : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC_DATA3_OUT : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC_DATA2_OUT : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC_DATA1_OUT : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC_DATA0_OUT : std_logic_vector(11 downto 0);\r
+ SIGNAL DEBUG_OUT : std_logic_vector(15 downto 0);\r
+\r
+ signal adc_0_real : std_logic_vector(11 downto 0);\r
+ signal adc_7_real : std_logic_vector(11 downto 0);\r
+\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: adc_data_handler PORT MAP(\r
+ RESET_IN => RESET_IN,\r
+ RESET_PLL_IN => RESET_PLL_IN,\r
+ ADC_LCLK_IN => ADC_LCLK_IN,\r
+ ADC_ADCLK_IN => ADC_ADCLK_IN,\r
+ ADC_CHNL_IN => ADC_CHNL_IN,\r
+ PLL_CTRL_IN => PLL_CTRL_IN,\r
+ PLL_LOCK_OUT => PLL_LOCK_OUT,\r
+ CLK40M_OUT => CLK40M_OUT,\r
+ ADC_ADCLK_OUT => ADC_ADCLK_OUT,\r
+ ADC_DATA7_OUT => ADC_DATA7_OUT,\r
+ ADC_DATA6_OUT => ADC_DATA6_OUT,\r
+ ADC_DATA5_OUT => ADC_DATA5_OUT,\r
+ ADC_DATA4_OUT => ADC_DATA4_OUT,\r
+ ADC_DATA3_OUT => ADC_DATA3_OUT,\r
+ ADC_DATA2_OUT => ADC_DATA2_OUT,\r
+ ADC_DATA1_OUT => ADC_DATA1_OUT,\r
+ ADC_DATA0_OUT => ADC_DATA0_OUT,\r
+ DEBUG_OUT => DEBUG_OUT\r
+ );\r
+\r
+-- 240MHz DDR clock from ADC, aka bit clock\r
+THE_CLOCK_GEN: process\r
+begin\r
+ adc_lclk_in <= '1'; wait for 2.08 ns;\r
+ adc_lclk_in <= '0'; wait for 2.08 ns;\r
+end process THE_CLOCK_GEN;\r
+\r
+-- test data generator\r
+BLA: process\r
+variable adc_0_data : unsigned(11 downto 0) := x"000";\r
+variable adc_7_data : unsigned(11 downto 0) := x"fff";\r
+variable my_bit : integer := 0;\r
+begin\r
+ \r
+ my_bit := 0;\r
+ adc_0_real <= std_logic_vector(adc_0_data);\r
+ adc_7_real <= std_logic_vector(adc_7_data);\r
+ \r
+ BIT_LOOP: for I in 0 to 5 loop\r
+\r
+ wait until rising_edge(adc_lclk_in);\r
+ wait for 1.04 ns;\r
+ if( I < 3 ) then\r
+ adc_adclk_in <= '1'; \r
+ else\r
+ adc_adclk_in <= '0'; -- second half\r
+ end if;\r
+ adc_chnl_in(7) <= adc_7_data(my_bit);\r
+ adc_chnl_in(6 downto 1) <= (others => '0');\r
+ adc_chnl_in(0) <= adc_0_data(my_bit);\r
+ my_bit := my_bit + 1;\r
+ wait until falling_edge(adc_lclk_in);\r
+ wait for 1.04 ns;\r
+ adc_chnl_in(7) <= adc_7_data(my_bit);\r
+ adc_chnl_in(6 downto 1) <= (others => '0');\r
+ adc_chnl_in(0) <= adc_0_data(my_bit);\r
+ my_bit := my_bit + 1;\r
+ \r
+ end loop BIT_LOOP;\r
+ \r
+ adc_7_data := adc_7_data - 1;\r
+ adc_0_data := adc_0_data + 1;\r
+\r
+end process BLA;\r
+\r
+\r
+THE_TEST_BENCH: process\r
+begin\r
+ -- Setup signals\r
+ reset_in <= '0';\r
+ reset_pll_in <= '0';\r
+ pll_ctrl_in <= x"6";\r
+ wait for 100 ns;\r
+\r
+ -- Reset all\r
+ reset_in <= '1';\r
+ wait for 100 ns;\r
+ reset_in <= '0';\r
+ wait for 100 ns;\r
+\r
+ -- Tests may start now\r
+\r
+\r
+ -- Stay a while, stay forever!\r
+ wait;\r
+ \r
+end process THE_TEST_BENCH;\r
+\r
+\r
+END;\r
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT adc_data_handler\r
+ PORT(\r
+ RESET_IN : IN std_logic;\r
+ RESET_PLL_IN : IN std_logic;\r
+ ADC_LCLK_IN : IN std_logic;\r
+ ADC_ADCLK_IN : IN std_logic;\r
+ ADC_CHNL_IN : IN std_logic_vector(7 downto 0);\r
+ PLL_CTRL_IN : IN std_logic_vector(3 downto 0); \r
+ PLL_LOCK_OUT : OUT std_logic;\r
+ CLK40M_OUT : OUT std_logic;\r
+ ADC_ADCLK_OUT : OUT std_logic;\r
+ ADC_DATA7_OUT : OUT std_logic_vector(11 downto 0);\r
+ ADC_DATA6_OUT : OUT std_logic_vector(11 downto 0);\r
+ ADC_DATA5_OUT : OUT std_logic_vector(11 downto 0);\r
+ ADC_DATA4_OUT : OUT std_logic_vector(11 downto 0);\r
+ ADC_DATA3_OUT : OUT std_logic_vector(11 downto 0);\r
+ ADC_DATA2_OUT : OUT std_logic_vector(11 downto 0);\r
+ ADC_DATA1_OUT : OUT std_logic_vector(11 downto 0);\r
+ ADC_DATA0_OUT : OUT std_logic_vector(11 downto 0);\r
+ DEBUG_OUT : OUT std_logic_vector(15 downto 0)\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL RESET_IN : std_logic;\r
+ SIGNAL RESET_PLL_IN : std_logic;\r
+ SIGNAL ADC_LCLK_IN : std_logic;\r
+ SIGNAL ADC_ADCLK_IN : std_logic;\r
+ SIGNAL ADC_CHNL_IN : std_logic_vector(7 downto 0);\r
+ SIGNAL PLL_CTRL_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL PLL_LOCK_OUT : std_logic;\r
+ SIGNAL CLK40M_OUT : std_logic;\r
+ SIGNAL ADC_ADCLK_OUT : std_logic;\r
+ SIGNAL ADC_DATA7_OUT : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC_DATA6_OUT : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC_DATA5_OUT : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC_DATA4_OUT : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC_DATA3_OUT : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC_DATA2_OUT : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC_DATA1_OUT : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC_DATA0_OUT : std_logic_vector(11 downto 0);\r
+ SIGNAL DEBUG_OUT : std_logic_vector(15 downto 0);\r
+\r
+ signal adc_0_real : std_logic_vector(11 downto 0);\r
+ signal adc_7_real : std_logic_vector(11 downto 0);\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: adc_data_handler PORT MAP(\r
+ RESET_IN => RESET_IN,\r
+ RESET_PLL_IN => RESET_PLL_IN,\r
+ ADC_LCLK_IN => ADC_LCLK_IN,\r
+ ADC_ADCLK_IN => ADC_ADCLK_IN,\r
+ ADC_CHNL_IN => ADC_CHNL_IN,\r
+ PLL_CTRL_IN => PLL_CTRL_IN,\r
+ PLL_LOCK_OUT => PLL_LOCK_OUT,\r
+ CLK40M_OUT => CLK40M_OUT,\r
+ ADC_ADCLK_OUT => ADC_ADCLK_OUT,\r
+ ADC_DATA7_OUT => ADC_DATA7_OUT,\r
+ ADC_DATA6_OUT => ADC_DATA6_OUT,\r
+ ADC_DATA5_OUT => ADC_DATA5_OUT,\r
+ ADC_DATA4_OUT => ADC_DATA4_OUT,\r
+ ADC_DATA3_OUT => ADC_DATA3_OUT,\r
+ ADC_DATA2_OUT => ADC_DATA2_OUT,\r
+ ADC_DATA1_OUT => ADC_DATA1_OUT,\r
+ ADC_DATA0_OUT => ADC_DATA0_OUT,\r
+ DEBUG_OUT => DEBUG_OUT\r
+ );\r
+\r
+THE_CLOCK_GEN: process\r
+begin\r
+ adc_lclk_in <= '1'; wait for 4.16 ns;\r
+ adc_lclk_in <= '0'; wait for 4.16 ns;\r
+end process THE_CLOCK_GEN;\r
+\r
+BLA: process\r
+variable adc_0_data : unsigned(11 downto 0) := x"000";\r
+variable adc_7_data : unsigned(11 downto 0) := x"fff";\r
+variable my_bit : integer := 0;\r
+begin\r
+ \r
+ my_bit := 0;\r
+ adc_0_real <= std_logic_vector(adc_0_data);\r
+ adc_7_real <= std_logic_vector(adc_7_data);\r
+ \r
+ BIT_LOOP: for I in 0 to 5 loop\r
+\r
+ wait until rising_edge(adc_lclk_in);\r
+ wait for 2.08 ns;\r
+ if( I < 3 ) then\r
+ adc_adclk_in <= '1'; \r
+ else\r
+ adc_adclk_in <= '0'; -- second half\r
+ end if;\r
+ adc_chnl_in(7) <= adc_7_data(my_bit);\r
+ adc_chnl_in(6 downto 1) <= (others => '0');\r
+ adc_chnl_in(0) <= adc_0_data(my_bit);\r
+ my_bit := my_bit + 1;\r
+ wait until falling_edge(adc_lclk_in);\r
+ wait for 2.08 ns;\r
+ adc_chnl_in(7) <= adc_7_data(my_bit);\r
+ adc_chnl_in(6 downto 1) <= (others => '0');\r
+ adc_chnl_in(0) <= adc_0_data(my_bit);\r
+ my_bit := my_bit + 1;\r
+ \r
+ end loop BIT_LOOP;\r
+ \r
+ adc_7_data := adc_7_data - 1;\r
+ adc_0_data := adc_0_data + 1;\r
+\r
+end process BLA;\r
+\r
+THE_TEST_BENCH: process\r
+begin\r
+ -- Setup signals\r
+ reset_in <= '0';\r
+ reset_pll_in <= '0';\r
+ pll_ctrl_in <= x"6";\r
+ wait for 100 ns;\r
+\r
+ -- Reset all\r
+ reset_in <= '1';\r
+ wait for 100 ns;\r
+ reset_in <= '0';\r
+ wait for 100 ns;\r
+\r
+ -- Tests may start now\r
+\r
+\r
+\r
+\r
+\r
+ -- Stay a while, stay forever!\r
+ wait;\r
+ \r
+end process THE_TEST_BENCH;\r
+\r
+END;\r
+\r
+\r
+-- -- ADCLK = '1' => first half of data word\r
+-- wait until rising_edge(adc_lclk_in);\r
+-- wait for 2.08 ns;\r
+-- adc_adclk_in <= '1'; adc_chnl_in <= b"0000_0000"; -- Bit D0\r
+-- wait until falling_edge(adc_lclk_in);\r
+-- wait for 2.08 ns;\r
+-- adc_adclk_in <= '1'; adc_chnl_in <= b"1111_1111"; -- Bit D1\r
+-- wait until rising_edge(adc_lclk_in);\r
+-- wait for 2.08 ns;\r
+-- adc_adclk_in <= '1'; adc_chnl_in <= b"0000_0000"; -- Bit D2\r
+-- wait until falling_edge(adc_lclk_in);\r
+-- wait for 2.08 ns;\r
+-- adc_adclk_in <= '1'; adc_chnl_in <= b"1111_1111"; -- Bit D3\r
+-- wait until rising_edge(adc_lclk_in);\r
+-- wait for 2.08 ns;\r
+-- adc_adclk_in <= '1'; adc_chnl_in <= b"0000_0000"; -- Bit D4\r
+-- wait until falling_edge(adc_lclk_in);\r
+-- wait for 2.08 ns;\r
+-- adc_adclk_in <= '1'; adc_chnl_in <= b"1111_1111"; -- Bit D5\r
+-- -- ADCLK = '0' => second half of data word\r
+-- wait until rising_edge(adc_lclk_in);\r
+-- wait for 2.08 ns;\r
+-- adc_adclk_in <= '0'; adc_chnl_in <= b"0000_0000"; -- Bit D6\r
+-- wait until falling_edge(adc_lclk_in);\r
+-- wait for 2.08 ns;\r
+-- adc_adclk_in <= '0'; adc_chnl_in <= b"1111_1111"; -- Bit D7\r
+-- wait until rising_edge(adc_lclk_in);\r
+-- wait for 2.08 ns;\r
+-- adc_adclk_in <= '0'; adc_chnl_in <= b"0000_0000"; -- Bit D8\r
+-- wait until falling_edge(adc_lclk_in);\r
+-- wait for 2.08 ns;\r
+-- adc_adclk_in <= '0'; adc_chnl_in <= b"1111_1111"; -- Bit D9\r
+-- wait until rising_edge(adc_lclk_in);\r
+-- wait for 2.08 ns;\r
+-- adc_adclk_in <= '0'; adc_chnl_in <= b"0000_0000"; -- Bit D10\r
+-- wait until falling_edge(adc_lclk_in);\r
+-- wait for 2.08 ns;\r
+-- adc_adclk_in <= '0'; adc_chnl_in <= b"1111_1111"; -- Bit D11\r
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT adc_data_handler_new\r
+ PORT(\r
+ RESET_IN : IN std_logic;\r
+ ADC_LCLK_IN : IN std_logic;\r
+ ADC_ADCLK_IN : IN std_logic;\r
+ ADC_CHNL_IN : IN std_logic_vector(7 downto 0);\r
+ PLL_CTRL_IN : IN std_logic_vector(3 downto 0); \r
+ ADC_DATA7_OUT : OUT std_logic_vector(11 downto 0);\r
+ ADC_DATA6_OUT : OUT std_logic_vector(11 downto 0);\r
+ ADC_DATA5_OUT : OUT std_logic_vector(11 downto 0);\r
+ ADC_DATA4_OUT : OUT std_logic_vector(11 downto 0);\r
+ ADC_DATA3_OUT : OUT std_logic_vector(11 downto 0);\r
+ ADC_DATA2_OUT : OUT std_logic_vector(11 downto 0);\r
+ ADC_DATA1_OUT : OUT std_logic_vector(11 downto 0);\r
+ ADC_DATA0_OUT : OUT std_logic_vector(11 downto 0);\r
+ ADC_CE_OUT : OUT std_logic;\r
+ ADC_VALID_OUT : OUT std_logic;\r
+ DEBUG_OUT : OUT std_logic_vector(15 downto 0)\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL RESET_IN : std_logic;\r
+ SIGNAL ADC_LCLK_IN : std_logic;\r
+ SIGNAL ADC_ADCLK_IN : std_logic;\r
+ SIGNAL ADC_CHNL_IN : std_logic_vector(7 downto 0);\r
+ SIGNAL PLL_CTRL_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL ADC_DATA7_OUT : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC_DATA6_OUT : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC_DATA5_OUT : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC_DATA4_OUT : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC_DATA3_OUT : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC_DATA2_OUT : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC_DATA1_OUT : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC_DATA0_OUT : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC_CE_OUT : std_logic;\r
+ SIGNAL ADC_VALID_OUT : std_logic;\r
+ SIGNAL DEBUG_OUT : std_logic_vector(15 downto 0);\r
+\r
+ signal adc_0_real : std_logic_vector(11 downto 0);\r
+ signal adc_7_real : std_logic_vector(11 downto 0);\r
+\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: adc_data_handler_new PORT MAP(\r
+ RESET_IN => RESET_IN,\r
+ ADC_LCLK_IN => ADC_LCLK_IN,\r
+ ADC_ADCLK_IN => ADC_ADCLK_IN,\r
+ ADC_CHNL_IN => ADC_CHNL_IN,\r
+ PLL_CTRL_IN => PLL_CTRL_IN,\r
+ ADC_DATA7_OUT => ADC_DATA7_OUT,\r
+ ADC_DATA6_OUT => ADC_DATA6_OUT,\r
+ ADC_DATA5_OUT => ADC_DATA5_OUT,\r
+ ADC_DATA4_OUT => ADC_DATA4_OUT,\r
+ ADC_DATA3_OUT => ADC_DATA3_OUT,\r
+ ADC_DATA2_OUT => ADC_DATA2_OUT,\r
+ ADC_DATA1_OUT => ADC_DATA1_OUT,\r
+ ADC_DATA0_OUT => ADC_DATA0_OUT,\r
+ ADC_CE_OUT => ADC_CE_OUT,\r
+ ADC_VALID_OUT => ADC_VALID_OUT,\r
+ DEBUG_OUT => DEBUG_OUT\r
+ );\r
+\r
+-- 240MHz DDR clock from ADC, aka bit clock\r
+THE_CLOCK_GEN: process\r
+begin\r
+ adc_lclk_in <= '1'; wait for 2.08 ns;\r
+ adc_lclk_in <= '0'; wait for 2.08 ns;\r
+end process THE_CLOCK_GEN;\r
+\r
+-- test data generator\r
+BLA: process\r
+variable adc_0_data : unsigned(11 downto 0) := x"000";\r
+variable adc_7_data : unsigned(11 downto 0) := x"fff";\r
+variable my_bit : integer := 0;\r
+begin\r
+ \r
+ my_bit := 0;\r
+ adc_0_real <= std_logic_vector(adc_0_data);\r
+ adc_7_real <= std_logic_vector(adc_7_data);\r
+ \r
+ BIT_LOOP: for I in 0 to 5 loop\r
+\r
+ wait until rising_edge(adc_lclk_in);\r
+ wait for 1.04 ns;\r
+ if( I < 3 ) then\r
+ adc_adclk_in <= '1'; \r
+ else\r
+ adc_adclk_in <= '0'; -- second half\r
+ end if;\r
+ adc_chnl_in(7) <= adc_7_data(my_bit);\r
+ adc_chnl_in(6 downto 1) <= (others => '0');\r
+ adc_chnl_in(0) <= adc_0_data(my_bit);\r
+ my_bit := my_bit + 1;\r
+ wait until falling_edge(adc_lclk_in);\r
+ wait for 1.04 ns;\r
+ adc_chnl_in(7) <= adc_7_data(my_bit);\r
+ adc_chnl_in(6 downto 1) <= (others => '0');\r
+ adc_chnl_in(0) <= adc_0_data(my_bit);\r
+ my_bit := my_bit + 1;\r
+ \r
+ end loop BIT_LOOP;\r
+ \r
+ adc_7_data := adc_7_data - 1;\r
+ adc_0_data := adc_0_data + 1;\r
+\r
+end process BLA;\r
+\r
+\r
+THE_TEST_BENCH: process\r
+begin\r
+ -- Setup signals\r
+ reset_in <= '0';\r
+ pll_ctrl_in <= x"6";\r
+ wait for 100 ns;\r
+\r
+ -- Reset all\r
+ reset_in <= '1';\r
+ wait for 100 ns;\r
+ reset_in <= '0';\r
+ wait for 100 ns;\r
+\r
+ -- Tests may start now\r
+\r
+\r
+ -- Stay a while, stay forever!\r
+ wait;\r
+ \r
+end process THE_TEST_BENCH;\r
+\r
+\r
+END;\r
--- /dev/null
+-- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23)
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity tb is
+end entity tb;
+
+
+architecture test of tb is
+
+ component adc_onewire_map_mem
+ port (Address : in std_logic_vector(6 downto 0);
+ Q : out std_logic_vector(3 downto 0)
+ );
+ end component;
+
+ signal Address : std_logic_vector(6 downto 0) := (others => '0');
+ signal Q : std_logic_vector(3 downto 0);
+begin
+ u1 : adc_onewire_map_mem
+ port map (Address => Address, Q => Q
+ );
+
+ process
+
+ begin
+ Address <= (others => '0') ;
+ wait for 100 ns;
+ wait for 10 ns;
+ for i in 0 to 131 loop
+ wait for 10 ns;
+ Address <= Address + '1' ;
+ end loop;
+ wait;
+ end process;
+
+end architecture test;
--- /dev/null
+-- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23)
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity tb is
+end entity tb;
+
+
+architecture test of tb is
+
+ component apv_adc_map_mem
+ port (Address : in std_logic_vector(6 downto 0);
+ Q : out std_logic_vector(3 downto 0)
+ );
+ end component;
+
+ signal Address : std_logic_vector(6 downto 0) := (others => '0');
+ signal Q : std_logic_vector(3 downto 0);
+begin
+ u1 : apv_adc_map_mem
+ port map (Address => Address, Q => Q
+ );
+
+ process
+
+ begin
+ Address <= (others => '0') ;
+ wait for 100 ns;
+ wait for 10 ns;
+ for i in 0 to 131 loop
+ wait for 10 ns;
+ Address <= Address + '1' ;
+ end loop;
+ wait;
+ end process;
+
+end architecture test;
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT apv_locker\r
+ PORT(\r
+ CLK_APV_IN : IN std_logic;\r
+ RESET_IN : IN std_logic;\r
+ SYNC_IN : IN std_logic;\r
+ ADC_RAW_IN : IN std_logic_vector(11 downto 0);\r
+ ADC_VALID_IN : IN std_logic;\r
+ APV_ON_IN : IN std_logic;\r
+ BIT_LOW_IN : IN std_logic_vector(11 downto 0);\r
+ BIT_HIGH_IN : IN std_logic_vector(11 downto 0);\r
+ FL_LOW_IN : IN std_logic_vector(11 downto 0);\r
+ FL_HIGH_IN : IN std_logic_vector(11 downto 0); \r
+ STATUS_IGNORE_OUT : OUT std_logic;\r
+ STATUS_UNKNOWN_OUT : OUT std_logic;\r
+ STATUS_BADADC_OUT : OUT std_logic;\r
+ STATUS_LOCKED_OUT : OUT std_logic;\r
+ STATUS_LOST_OUT : OUT std_logic;\r
+ STATUS_NOSYNC_OUT : OUT std_logic;\r
+ STATUS_MISSING_OUT : OUT std_logic;\r
+ STATUS_TICKMARK_OUT : OUT std_logic;\r
+ FRAME_ROW_OUT : OUT std_logic_vector(7 downto 0);\r
+ FRAME_ERROR_OUT : OUT std_logic;\r
+ FRAME_FLAT_OUT : OUT std_logic;\r
+ FRAME_OVF_OUT : OUT std_logic;\r
+ FRAME_UDF_OUT : OUT std_logic;\r
+ FRAME_CTR_OUT : OUT std_logic_vector(3 downto 0);\r
+ APV_CHANNEL_OUT : OUT std_logic_vector(6 downto 0);\r
+ APV_OVERFLOW_OUT : OUT std_logic;\r
+ APV_UNDERFLOW_OUT : OUT std_logic;\r
+ APV_RAW_OUT : OUT std_logic_vector(11 downto 0);\r
+ APV_ANALOG_OUT : OUT std_logic;\r
+ APV_START_OUT : OUT std_logic;\r
+ APV_LAST_OUT : OUT std_logic;\r
+ DEBUG_OUT : OUT std_logic_vector(15 downto 0)\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL CLK_APV_IN : std_logic;\r
+ SIGNAL RESET_IN : std_logic;\r
+ SIGNAL SYNC_IN : std_logic;\r
+ SIGNAL ADC_RAW_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC_VALID_IN : std_logic;\r
+ SIGNAL APV_ON_IN : std_logic;\r
+ SIGNAL BIT_LOW_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL BIT_HIGH_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL FL_LOW_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL FL_HIGH_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL STATUS_IGNORE_OUT : std_logic;\r
+ SIGNAL STATUS_UNKNOWN_OUT : std_logic;\r
+ SIGNAL STATUS_BADADC_OUT : std_logic;\r
+ SIGNAL STATUS_LOCKED_OUT : std_logic;\r
+ SIGNAL STATUS_LOST_OUT : std_logic;\r
+ SIGNAL STATUS_NOSYNC_OUT : std_logic;\r
+ SIGNAL STATUS_MISSING_OUT : std_logic;\r
+ SIGNAL STATUS_TICKMARK_OUT : std_logic;\r
+ SIGNAL FRAME_ROW_OUT : std_logic_vector(7 downto 0);\r
+ SIGNAL FRAME_ERROR_OUT : std_logic;\r
+ SIGNAL FRAME_FLAT_OUT : std_logic;\r
+ SIGNAL FRAME_OVF_OUT : std_logic;\r
+ SIGNAL FRAME_UDF_OUT : std_logic;\r
+ SIGNAL FRAME_CTR_OUT : std_logic_vector(3 downto 0);\r
+ SIGNAL APV_CHANNEL_OUT : std_logic_vector(6 downto 0);\r
+ SIGNAL APV_OVERFLOW_OUT : std_logic;\r
+ SIGNAL APV_UNDERFLOW_OUT : std_logic;\r
+ SIGNAL APV_RAW_OUT : std_logic_vector(11 downto 0);\r
+ SIGNAL APV_ANALOG_OUT : std_logic;\r
+ SIGNAL APV_START_OUT : std_logic;\r
+ SIGNAL APV_LAST_OUT : std_logic;\r
+ SIGNAL DEBUG_OUT : std_logic_vector(15 downto 0);\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: apv_locker PORT MAP(\r
+ CLK_APV_IN => CLK_APV_IN,\r
+ RESET_IN => RESET_IN,\r
+ SYNC_IN => SYNC_IN,\r
+ ADC_RAW_IN => ADC_RAW_IN,\r
+ ADC_VALID_IN => ADC_VALID_IN,\r
+ APV_ON_IN => APV_ON_IN,\r
+ BIT_LOW_IN => BIT_LOW_IN,\r
+ BIT_HIGH_IN => BIT_HIGH_IN,\r
+ FL_LOW_IN => FL_LOW_IN,\r
+ FL_HIGH_IN => FL_HIGH_IN,\r
+ STATUS_IGNORE_OUT => STATUS_IGNORE_OUT,\r
+ STATUS_UNKNOWN_OUT => STATUS_UNKNOWN_OUT,\r
+ STATUS_BADADC_OUT => STATUS_BADADC_OUT,\r
+ STATUS_LOCKED_OUT => STATUS_LOCKED_OUT,\r
+ STATUS_LOST_OUT => STATUS_LOST_OUT,\r
+ STATUS_NOSYNC_OUT => STATUS_NOSYNC_OUT,\r
+ STATUS_MISSING_OUT => STATUS_MISSING_OUT,\r
+ STATUS_TICKMARK_OUT => STATUS_TICKMARK_OUT,\r
+ FRAME_ROW_OUT => FRAME_ROW_OUT,\r
+ FRAME_ERROR_OUT => FRAME_ERROR_OUT,\r
+ FRAME_FLAT_OUT => FRAME_FLAT_OUT,\r
+ FRAME_OVF_OUT => FRAME_OVF_OUT,\r
+ FRAME_UDF_OUT => FRAME_UDF_OUT,\r
+ FRAME_CTR_OUT => FRAME_CTR_OUT,\r
+ APV_CHANNEL_OUT => APV_CHANNEL_OUT,\r
+ APV_OVERFLOW_OUT => APV_OVERFLOW_OUT,\r
+ APV_UNDERFLOW_OUT => APV_UNDERFLOW_OUT,\r
+ APV_RAW_OUT => APV_RAW_OUT,\r
+ APV_ANALOG_OUT => APV_ANALOG_OUT,\r
+ APV_START_OUT => APV_START_OUT,\r
+ APV_LAST_OUT => APV_LAST_OUT,\r
+ DEBUG_OUT => DEBUG_OUT\r
+ );\r
+\r
+THE_ADC_CLOCK_GEN: process\r
+begin\r
+ clk_apv_in <= '1'; wait for 12.5 ns;\r
+ clk_apv_in <= '0'; wait for 12.5 ns;\r
+end process THE_ADC_CLOCK_GEN;\r
+\r
+THE_APV_SIM_PROC: process\r
+begin\r
+ LOOP_IT: for J in 0 to 32 loop\r
+ wait until rising_edge(clk_apv_in);\r
+ adc_raw_in <= x"e00";\r
+ wait until rising_edge(clk_apv_in);\r
+ adc_raw_in <= x"100";\r
+ ONE_LOOP: for I in 0 to 32 loop\r
+ wait until rising_edge(clk_apv_in);\r
+ end loop ONE_LOOP;\r
+ end loop LOOP_IT;\r
+\r
+ wait until rising_edge(clk_apv_in);\r
+ adc_raw_in <= x"fff";\r
+ wait until rising_edge(clk_apv_in);\r
+ adc_raw_in <= x"fff";\r
+ wait until rising_edge(clk_apv_in);\r
+ adc_raw_in <= x"fff";\r
+ HEADER_LOOP: for L in 0 to 8 loop\r
+ wait until rising_edge(clk_apv_in);\r
+ adc_raw_in <= x"eee";\r
+ end loop HEADER_LOOP;\r
+ DATA_LOOP: for L in 0 to 127 loop\r
+ wait until rising_edge(clk_apv_in);\r
+ adc_raw_in <= x"222";\r
+ end loop DATA_LOOP;\r
+ \r
+end process THE_APV_SIM_PROC;\r
+\r
+THE_TEST_BENCH: process\r
+begin\r
+ -- Setup signals\r
+ reset_in <= '0';\r
+ sync_in <= '0';\r
+ adc_valid_in <= '0';\r
+ apv_on_in <= '1';\r
+ bit_low_in <= x"200";\r
+ bit_high_in <= x"d00";\r
+ fl_low_in <= x"780";\r
+ fl_high_in <= x"880";\r
+ wait for 100 ns;\r
+\r
+ -- Reset all\r
+ reset_in <= '1';\r
+ wait for 100 ns;\r
+ reset_in <= '0';\r
+ wait for 100 ns;\r
+ adc_valid_in <= '1';\r
+ wait for 100 ns;\r
+\r
+ -- Tests may start now\r
+ -- send a SYNC sequence b"101"\r
+ wait until rising_edge(clk_apv_in);\r
+ sync_in <= '1';\r
+ wait until rising_edge(clk_apv_in);\r
+ sync_in <= '0';\r
+\r
+ -- wait until sync'ed\r
+-- wait until rising_edge(status_locked_out);\r
+-- wait for 300 ns;\r
+ \r
+ \r
+\r
+\r
+ -- Stay a while, stay forever!\r
+ wait;\r
+ \r
+end process THE_TEST_BENCH;\r
+\r
+END;\r
--- /dev/null
+-- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23)
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity tb is
+end entity tb;
+
+
+architecture test of tb is
+
+ component apv_map_mem
+ port (Address : in std_logic_vector(6 downto 0);
+ Q : out std_logic_vector(3 downto 0)
+ );
+ end component;
+
+ signal Address : std_logic_vector(6 downto 0) := (others => '0');
+ signal Q : std_logic_vector(3 downto 0);
+begin
+ u1 : apv_map_mem
+ port map (Address => Address, Q => Q
+ );
+
+ process
+
+ begin
+ Address <= (others => '0') ;
+ wait for 100 ns;
+ wait for 10 ns;
+ for i in 0 to 131 loop
+ wait for 10 ns;
+ Address <= Address + '1' ;
+ end loop;
+ wait;
+ end process;
+
+end architecture test;
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT apv_trgctrl\r
+ PORT(\r
+ CLK_APV_IN : IN std_logic;\r
+ CLK_IN : IN std_logic;\r
+ RESET_IN : IN std_logic;\r
+ SYNC_TRG_IN : IN std_logic;\r
+ TIME_TRG_IN : IN std_logic_vector(3 downto 0);\r
+ TRB_TRG_IN : IN std_logic_vector(3 downto 0);\r
+ STILL_BUSY_IN : IN std_logic;\r
+ TRG_3_TODO_IN : IN std_logic_vector(3 downto 0);\r
+ TRG_3_DELAY_IN : IN std_logic_vector(3 downto 0);\r
+ TRG_2_TODO_IN : IN std_logic_vector(3 downto 0);\r
+ TRG_2_DELAY_IN : IN std_logic_vector(3 downto 0);\r
+ TRG_1_TODO_IN : IN std_logic_vector(3 downto 0);\r
+ TRG_1_DELAY_IN : IN std_logic_vector(3 downto 0);\r
+ TRG_0_TODO_IN : IN std_logic_vector(3 downto 0);\r
+ TRG_0_DELAY_IN : IN std_logic_vector(3 downto 0);\r
+ TRG_SETUP_IN : IN std_logic_vector(7 downto 0);\r
+ TRB_TTAG_IN : IN std_logic_vector(15 downto 0);\r
+ TRB_TRND_IN : IN std_logic_vector(7 downto 0);\r
+ TRB_TTYPE_IN : IN std_logic_vector(3 downto 0);\r
+ TRB_TRGRCVD_IN : IN std_logic;\r
+ TRB_RST_COUNTER_IN : IN std_logic;\r
+ EDS_DONE_IN : IN std_logic; \r
+ TRG_FOUND_OUT : OUT std_logic;\r
+ TRB_MISSING_OUT : OUT std_logic;\r
+ TRB_RELEASE_OUT : OUT std_logic;\r
+ TRB_COUNTER_OUT : OUT std_logic_vector(15 downto 0);\r
+ EDS_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ EDS_AVAIL_OUT : OUT std_logic;\r
+ EDS_FULL_OUT : OUT std_logic;\r
+ EDS_LEVEL_OUT : OUT std_logic_vector(4 downto 0);\r
+ FRM_REQD_OUT : OUT std_logic;\r
+ APV_TRG_OUT : OUT std_logic;\r
+ APV_SYNC_OUT : OUT std_logic;\r
+ DEBUG_OUT : OUT std_logic_vector(63 downto 0)\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL CLK_APV_IN : std_logic;\r
+ SIGNAL CLK_IN : std_logic;\r
+ SIGNAL RESET_IN : std_logic;\r
+ SIGNAL SYNC_TRG_IN : std_logic;\r
+ SIGNAL TIME_TRG_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL TRB_TRG_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL STILL_BUSY_IN : std_logic;\r
+ SIGNAL TRG_FOUND_OUT : std_logic;\r
+ SIGNAL TRG_3_TODO_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL TRG_3_DELAY_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL TRG_2_TODO_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL TRG_2_DELAY_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL TRG_1_TODO_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL TRG_1_DELAY_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL TRG_0_TODO_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL TRG_0_DELAY_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL TRG_SETUP_IN : std_logic_vector(7 downto 0);\r
+ SIGNAL TRB_TTAG_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL TRB_TRND_IN : std_logic_vector(7 downto 0);\r
+ SIGNAL TRB_TTYPE_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL TRB_TRGRCVD_IN : std_logic;\r
+ SIGNAL TRB_MISSING_OUT : std_logic;\r
+ SIGNAL TRB_RELEASE_OUT : std_logic;\r
+ SIGNAL TRB_RST_COUNTER_IN : std_logic;\r
+ SIGNAL TRB_COUNTER_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL EDS_DATA_OUT : std_logic_vector(39 downto 0);\r
+ SIGNAL EDS_AVAIL_OUT : std_logic;\r
+ SIGNAL EDS_DONE_IN : std_logic;\r
+ SIGNAL EDS_FULL_OUT : std_logic;\r
+ SIGNAL EDS_LEVEL_OUT : std_logic_vector(4 downto 0);\r
+ SIGNAL FRM_REQD_OUT : std_logic;\r
+ SIGNAL APV_TRG_OUT : std_logic;\r
+ SIGNAL APV_SYNC_OUT : std_logic;\r
+ SIGNAL DEBUG_OUT : std_logic_vector(63 downto 0);\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: apv_trgctrl PORT MAP(\r
+ CLK_APV_IN => CLK_APV_IN,\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ SYNC_TRG_IN => SYNC_TRG_IN,\r
+ TIME_TRG_IN => TIME_TRG_IN,\r
+ TRB_TRG_IN => TRB_TRG_IN,\r
+ STILL_BUSY_IN => STILL_BUSY_IN,\r
+ TRG_FOUND_OUT => TRG_FOUND_OUT,\r
+ TRG_3_TODO_IN => TRG_3_TODO_IN,\r
+ TRG_3_DELAY_IN => TRG_3_DELAY_IN,\r
+ TRG_2_TODO_IN => TRG_2_TODO_IN,\r
+ TRG_2_DELAY_IN => TRG_2_DELAY_IN,\r
+ TRG_1_TODO_IN => TRG_1_TODO_IN,\r
+ TRG_1_DELAY_IN => TRG_1_DELAY_IN,\r
+ TRG_0_TODO_IN => TRG_0_TODO_IN,\r
+ TRG_0_DELAY_IN => TRG_0_DELAY_IN,\r
+ TRG_SETUP_IN => TRG_SETUP_IN,\r
+ TRB_TTAG_IN => TRB_TTAG_IN,\r
+ TRB_TRND_IN => TRB_TRND_IN,\r
+ TRB_TTYPE_IN => TRB_TTYPE_IN,\r
+ TRB_TRGRCVD_IN => TRB_TRGRCVD_IN,\r
+ TRB_MISSING_OUT => TRB_MISSING_OUT,\r
+ TRB_RELEASE_OUT => TRB_RELEASE_OUT,\r
+ TRB_RST_COUNTER_IN => TRB_RST_COUNTER_IN,\r
+ TRB_COUNTER_OUT => TRB_COUNTER_OUT,\r
+ EDS_DATA_OUT => EDS_DATA_OUT,\r
+ EDS_AVAIL_OUT => EDS_AVAIL_OUT,\r
+ EDS_DONE_IN => EDS_DONE_IN,\r
+ EDS_FULL_OUT => EDS_FULL_OUT,\r
+ EDS_LEVEL_OUT => EDS_LEVEL_OUT,\r
+ FRM_REQD_OUT => FRM_REQD_OUT,\r
+ APV_TRG_OUT => APV_TRG_OUT,\r
+ APV_SYNC_OUT => APV_SYNC_OUT,\r
+ DEBUG_OUT => DEBUG_OUT\r
+ );\r
+\r
+-- Generate the clock\r
+THE_CLOCK_GEN: process\r
+begin\r
+ clk_in <= '0'; wait for 5 ns;\r
+ clk_in <= '1'; wait for 5 ns;\r
+end process THE_CLOCK_GEN;\r
+\r
+THE_APV_CLOCK_GEN: process\r
+begin\r
+ clk_apv_in <= '0'; wait for 12.5 ns;\r
+ clk_apv_in <= '1'; wait for 12.5 ns;\r
+end process THE_APV_CLOCK_GEN;\r
+\r
+-- The real testbench\r
+THE_TESTBENCH_PROC: process\r
+begin\r
+ -- Setup signals\r
+ reset_in <= '0';\r
+ sync_trg_in <= '0';\r
+ time_trg_in <= x"0";\r
+ trb_trg_in <= x"0";\r
+ still_busy_in <= '0';\r
+ trg_3_todo_in <= x"1";\r
+ trg_3_delay_in <= x"0";\r
+ trg_2_todo_in <= x"1";\r
+ trg_2_delay_in <= x"0";\r
+ trg_1_todo_in <= x"1";\r
+ trg_1_delay_in <= x"0";\r
+ trg_0_todo_in <= x"1";\r
+ trg_0_delay_in <= x"0";\r
+ trg_setup_in <= x"10"; -- TRG0 is active, non-inverted\r
+ trb_ttag_in <= x"0000";\r
+ trb_trnd_in <= x"00";\r
+ trb_ttype_in <= x"0";\r
+ trb_trgrcvd_in <= '0';\r
+ trb_rst_counter_in <= '0';\r
+ eds_done_in <= '0';\r
+ \r
+ wait for 20 ns;\r
+ \r
+ -- Do a reset\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ \r
+ wait for 100 ns;\r
+ \r
+ -- test may start here\r
+ \r
+ wait until rising_edge(clk_in);\r
+ sync_trg_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ sync_trg_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+\r
+ wait for 1 us;\r
+ \r
+ -- first trigger\r
+ -- send in one timing trigger\r
+ wait for 77.7 ns;\r
+ time_trg_in <= x"1"; \r
+ wait for 222.2 ns;\r
+ time_trg_in <= x"0";\r
+ \r
+ -- send TRB trigger infos\r
+ wait for 2.3 us;\r
+ wait until rising_edge(clk_in);\r
+ trb_ttype_in <= x"1";\r
+ trb_ttag_in <= x"abcd";\r
+ trb_trnd_in <= x"ef";\r
+ wait until rising_edge(clk_in);\r
+ trb_trgrcvd_in <= '1';\r
+\r
+ -- release trigger\r
+ wait until rising_edge(trb_release_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ trb_trgrcvd_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+\r
+ wait for 1.22 us;\r
+\r
+ -- next trigger\r
+ -- send in one timing trigger\r
+ wait for 77.7 ns;\r
+ time_trg_in <= x"1"; \r
+ wait for 222.2 ns;\r
+ time_trg_in <= x"0";\r
+ \r
+ -- send TRB trigger infos\r
+ wait for 2.3 us;\r
+ wait until rising_edge(clk_in);\r
+ trb_ttype_in <= x"2";\r
+ trb_ttag_in <= x"dead";\r
+ trb_trnd_in <= x"42";\r
+ wait until rising_edge(clk_in);\r
+ trb_trgrcvd_in <= '1';\r
+\r
+ -- release trigger\r
+ wait until rising_edge(trb_release_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ trb_trgrcvd_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+\r
+ wait for 1.11 us;\r
+ \r
+ -- release one EDS\r
+ wait until rising_edge(clk_in);\r
+ eds_done_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ eds_done_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+\r
+ wait for 200 ns;\r
+\r
+ -- release one EDS\r
+ wait until rising_edge(clk_in);\r
+ eds_done_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ eds_done_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+\r
+ \r
+ -- Stay a while, stay forever.... wuhahahahaha\r
+ wait;\r
+end process THE_TESTBENCH_PROC;\r
+\r
+\r
+END;\r
--- /dev/null
+-- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23)
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity tb is
+end entity tb;
+
+
+architecture test of tb is
+
+ component comp4bit
+ port (DataA : in std_logic_vector(3 downto 0);
+ DataB : in std_logic_vector(3 downto 0); AGTB: out std_logic
+ );
+ end component;
+
+ signal DataA : std_logic_vector(3 downto 0) := (others => '0');
+ signal DataB : std_logic_vector(3 downto 0) := (others => '0');
+ signal AGTB: std_logic;
+begin
+ u1 : comp4bit
+ port map (DataA => DataA, DataB => DataB, AGTB => AGTB
+ );
+
+ process
+
+ begin
+ DataA <= (others => '0') ;
+ for i in 0 to 200 loop
+ wait for 10 ns;
+ DataA <= DataA + '1' ;
+ end loop;
+ wait;
+ end process;
+
+ process
+
+ begin
+ DataB <= (others => '0') ;
+ for i in 0 to 100 loop
+ wait for 10 ns;
+ DataB <= DataB + '1' ;
+ end loop;
+ wait;
+ end process;
+
+end architecture test;
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ component crossfifo is\r
+ port( DATA : in std_logic_vector(95 downto 0); \r
+ WRCLOCK : in std_logic; \r
+ RDCLOCK : in std_logic; \r
+ WREN : in std_logic; \r
+ RDEN : in std_logic; \r
+ RESET : in std_logic; \r
+ RPRESET : in std_logic; \r
+ Q : out std_logic_vector(95 downto 0); \r
+ EMPTY : out std_logic; \r
+ FULL : out std_logic; \r
+ ALMOSTEMPTY : out std_logic\r
+ );\r
+ end component;\r
+\r
+ signal DATA : std_logic_vector(95 downto 0); \r
+ signal WRCLOCK : std_logic; \r
+ signal RDCLOCK : std_logic; \r
+ signal WREN : std_logic; \r
+ signal RDEN : std_logic; \r
+ signal RESET : std_logic; \r
+ signal RPRESET : std_logic; \r
+ signal Q : std_logic_vector(95 downto 0); \r
+ signal EMPTY : std_logic; \r
+ signal FULL : std_logic; \r
+ signal ALMOSTEMPTY : std_logic;\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: crossfifo PORT MAP(\r
+ DATA => DATA,\r
+ WRCLOCK => WRCLOCK,\r
+ RDCLOCK => RDCLOCK,\r
+ WREN => WREN,\r
+ RDEN => RDEN,\r
+ RESET => RESET,\r
+ RPRESET => RPRESET,\r
+ Q => Q,\r
+ EMPTY => EMPTY,\r
+ FULL => FULL,\r
+ ALMOSTEMPTY => ALMOSTEMPTY\r
+ );\r
+ \r
+RDCLOCK_GEN: process\r
+begin\r
+ rdclock <= '1'; wait for 12.5 ns;\r
+ rdclock <= '0'; wait for 12.5 ns;\r
+end process RDCLOCK_GEN;\r
+\r
+WRCLOCK_GEN: process\r
+begin\r
+ wait until rising_edge(rdclock); wait for 3.33 ns; wrclock <= '1';\r
+ wait until falling_edge(rdclock); wait for 3.33 ns; wrclock <= '0';\r
+end process WRCLOCK_GEN;\r
+\r
+RDEN_GEN: process\r
+begin\r
+ rden <= '0';\r
+ wait until falling_edge(reset);\r
+ wait until falling_edge(almostempty); \r
+ rden <= '1';\r
+end process RDEN_GEN;\r
+\r
+THE_TEST_BENCH: process\r
+begin\r
+ -- Setup signals\r
+ data <= x"000_000_000_000_000_000_000_000";\r
+ wren <= '0';\r
+ --rden <= '0';\r
+ reset <= '0';\r
+ rpreset <= '0';\r
+\r
+ -- Reset all\r
+ reset <= '1'; wait for 50 ns;\r
+ reset <= '0'; wait for 50 ns;\r
+\r
+ -- Tests may start here\r
+\r
+ wait until rising_edge(wrclock);\r
+ wren <= '1';\r
+ data(95 downto 84) <= x"001";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"002";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"003";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"004";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"005";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"006";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"007";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"008";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"009";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"00a";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"00b";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"00c";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"00d";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"00e";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"00e";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"00f";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"010";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"011";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"012";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"013";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"014";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"015";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"016";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"017";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"018";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"019";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"01a";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"01b";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"01c";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"01d";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"01e";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"01f";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"020";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"021";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"022";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"023";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"024";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"025";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"026";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"027";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"028";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"029";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"02a";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"02b";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"02c";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"02d";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"02e";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"02f";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"030";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"031";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"032";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"033";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"034";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"035";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"036";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"037";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"038";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"039";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"03a";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"03b";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"03c";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"03d";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"03e";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"03f";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"040";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"041";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"042";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"043";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"044";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"045";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"046";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"047";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"048";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"049";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"04a";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"04b";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"04c";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"04d";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"04e";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"04f";\r
+ wait until rising_edge(wrclock);\r
+\r
+\r
+ -- Stay a while, stay forever.\r
+ wait;\r
+\r
+end process THE_TEST_BENCH;\r
+\r
+\r
+END;\r
+\r
--- /dev/null
+-- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23)
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity tb is
+end entity tb;
+
+
+architecture test of tb is
+
+ component crossfifo
+ port (Data : in std_logic_vector(95 downto 0);
+ WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic;
+ RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic;
+ Q : out std_logic_vector(95 downto 0); Empty: out std_logic;
+ Full: out std_logic; AlmostEmpty: out std_logic
+ );
+ end component;
+
+ signal Data : std_logic_vector(95 downto 0) := (others => '0');
+ signal WrClock: std_logic := '0';
+ signal RdClock: std_logic := '0';
+ signal WrEn: std_logic := '0';
+ signal RdEn: std_logic := '0';
+ signal Reset: std_logic := '0';
+ signal RPReset: std_logic := '0';
+ signal Q : std_logic_vector(95 downto 0);
+ signal Empty: std_logic;
+ signal Full: std_logic;
+ signal AlmostEmpty: std_logic;
+begin
+ u1 : crossfifo
+ port map (Data => Data, WrClock => WrClock, RdClock => RdClock,
+ WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset,
+ Q => Q, Empty => Empty, Full => Full, AlmostEmpty => AlmostEmpty
+ );
+
+ process
+
+ begin
+ Data <= (others => '0') ;
+ wait for 100 ns;
+ wait until Reset = '0';
+ for i in 0 to 259 loop
+ wait until WrClock'event and WrClock = '1';
+ Data <= Data + '1' after 1 ns;
+ end loop;
+ wait;
+ end process;
+
+ WrClock <= not WrClock after 5.00 ns;
+
+ RdClock <= not RdClock after 5.00 ns;
+
+ process
+
+ begin
+ WrEn <= '0' ;
+ wait for 100 ns;
+ wait until Reset = '0';
+ for i in 0 to 259 loop
+ wait until WrClock'event and WrClock = '1';
+ WrEn <= '1' after 1 ns;
+ end loop;
+ WrEn <= '0' ;
+ wait;
+ end process;
+
+ process
+
+ begin
+ RdEn <= '0' ;
+ wait until Reset = '0';
+ wait until WrEn = '1';
+ wait until WrEn = '0';
+ for i in 0 to 259 loop
+ wait until RdClock'event and RdClock = '1';
+ RdEn <= '1' after 1 ns;
+ end loop;
+ RdEn <= '0' ;
+ wait;
+ end process;
+
+ process
+
+ begin
+ Reset <= '1' ;
+ wait for 100 ns;
+ Reset <= '0' ;
+ wait;
+ end process;
+
+ process
+
+ begin
+ RPReset <= '1' ;
+ wait for 100 ns;
+ RPReset <= '0' ;
+ wait;
+ end process;
+
+end architecture test;
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ component crossover is\r
+ port( DATA : in std_logic_vector(95 downto 0); \r
+ WRCLOCK : in std_logic; \r
+ RDCLOCK : in std_logic; \r
+ WREN : in std_logic; \r
+ RDEN : in std_logic; \r
+ RESET : in std_logic; \r
+ RPRESET : in std_logic; \r
+ Q : out std_logic_vector(95 downto 0); \r
+ WCNT : out std_logic_vector(4 downto 0); \r
+ RCNT : out std_logic_vector(4 downto 0); \r
+ EMPTY : out std_logic; \r
+ FULL : out std_logic\r
+ );\r
+ end component;\r
+ \r
+ signal DATA : std_logic_vector(95 downto 0); \r
+ signal WRCLOCK : std_logic; \r
+ signal RDCLOCK : std_logic; \r
+ signal WREN : std_logic; \r
+ signal RDEN : std_logic; \r
+ signal RESET : std_logic; \r
+ signal RPRESET : std_logic; \r
+ signal Q : std_logic_vector(95 downto 0); \r
+ signal WCNT : std_logic_vector(4 downto 0); \r
+ signal RCNT : std_logic_vector(4 downto 0); \r
+ signal EMPTY : std_logic; \r
+ signal FULL : std_logic; \r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: crossover PORT MAP(\r
+ DATA => DATA,\r
+ WRCLOCK => WRCLOCK,\r
+ RDCLOCK => RDCLOCK,\r
+ WREN => WREN,\r
+ RDEN => RDEN,\r
+ RESET => RESET,\r
+ RPRESET => RPRESET,\r
+ Q => Q,\r
+ RCNT => RCNT,\r
+ WCNT => WCNT,\r
+ EMPTY => EMPTY,\r
+ FULL => FULL\r
+ );\r
+ \r
+RDCLOCK_GEN: process\r
+begin\r
+ rdclock <= '1'; wait for 12.5 ns;\r
+ rdclock <= '0'; wait for 12.5 ns;\r
+end process RDCLOCK_GEN;\r
+\r
+WRCLOCK_GEN: process\r
+begin\r
+ wait until rising_edge(rdclock); wait for 3.33 ns; wrclock <= '1';\r
+ wait until falling_edge(rdclock); wait for 3.33 ns; wrclock <= '0';\r
+end process WRCLOCK_GEN;\r
+\r
+THE_TEST_BENCH: process\r
+begin\r
+ -- Setup signals\r
+ data <= x"000_000_000_000_000_000_000_000";\r
+ wren <= '0';\r
+ rden <= '0';\r
+ reset <= '0';\r
+ rpreset <= '0';\r
+\r
+ -- Reset all\r
+ reset <= '1'; wait for 50 ns;\r
+ reset <= '0'; wait for 50 ns;\r
+\r
+ -- Tests may start here\r
+\r
+ wait until rising_edge(wrclock);\r
+ wren <= '1';\r
+ data(95 downto 84) <= x"100";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"101";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"102";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"103";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"104";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"105";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"106";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"107";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"108";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"109";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"10a";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"10b";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"10c";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"10d";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"10e";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"10f";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"110";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"111";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"112";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"113";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"114";\r
+ wait until rising_edge(wrclock);\r
+ data(95 downto 84) <= x"115";\r
+ wait until rising_edge(wrclock);\r
+ wren <= '0';\r
+\r
+ wait until rising_edge(rdclock);\r
+ rden <= '1';\r
+ wait until rising_edge(rdclock);\r
+ wait until rising_edge(rdclock);\r
+ wait until rising_edge(rdclock);\r
+ wait until rising_edge(rdclock);\r
+ wait until rising_edge(rdclock);\r
+ wait until rising_edge(rdclock);\r
+ wait until rising_edge(rdclock);\r
+ wait until rising_edge(rdclock);\r
+ wait until rising_edge(rdclock);\r
+ wait until rising_edge(rdclock);\r
+ wait until rising_edge(rdclock);\r
+ wait until rising_edge(rdclock);\r
+ wait until rising_edge(rdclock);\r
+ wait until rising_edge(rdclock);\r
+ wait until rising_edge(rdclock);\r
+ wait until rising_edge(rdclock);\r
+ \r
+ wait until rising_edge(rdclock);\r
+ wait until rising_edge(rdclock);\r
+\r
+ -- Stay a while, stay forever.\r
+ wait;\r
+\r
+end process THE_TEST_BENCH;\r
+\r
+\r
+END;\r
+\r
--- /dev/null
+-- VHDL testbench template generated by SCUBA ispLever_v72_PROD_Build (44)
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity tb is
+end entity tb;
+
+
+architecture test of tb is
+
+ component crossover
+ port (Data : in std_logic_vector(95 downto 0);
+ WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic;
+ RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic;
+ Q : out std_logic_vector(95 downto 0);
+ WCNT : out std_logic_vector(4 downto 0);
+ RCNT : out std_logic_vector(4 downto 0); Empty: out std_logic;
+ Full: out std_logic
+ );
+ end component;
+
+ signal Data : std_logic_vector(95 downto 0) := (others => '0');
+ signal WrClock: std_logic := '0';
+ signal RdClock: std_logic := '0';
+ signal WrEn: std_logic := '0';
+ signal RdEn: std_logic := '0';
+ signal Reset: std_logic := '0';
+ signal RPReset: std_logic := '0';
+ signal Q : std_logic_vector(95 downto 0);
+ signal WCNT : std_logic_vector(4 downto 0);
+ signal RCNT : std_logic_vector(4 downto 0);
+ signal Empty: std_logic;
+ signal Full: std_logic;
+begin
+ u1 : crossover
+ port map (Data => Data, WrClock => WrClock, RdClock => RdClock,
+ WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset,
+ Q => Q, WCNT => WCNT, RCNT => RCNT, Empty => Empty, Full => Full
+ );
+
+ process
+
+ begin
+ Data <= (others => '0') ;
+ wait for 100 ns;
+ wait until Reset = '0';
+ for i in 0 to 19 loop
+ wait until WrClock'event and WrClock = '1';
+ Data <= Data + '1' after 1 ns;
+ end loop;
+ wait;
+ end process;
+
+ WrClock <= not WrClock after 5.00 ns;
+
+ RdClock <= not RdClock after 5.00 ns;
+
+ process
+
+ begin
+ WrEn <= '0' ;
+ wait for 100 ns;
+ wait until Reset = '0';
+ for i in 0 to 19 loop
+ wait until WrClock'event and WrClock = '1';
+ WrEn <= '1' after 1 ns;
+ end loop;
+ WrEn <= '0' ;
+ wait;
+ end process;
+
+ process
+
+ begin
+ RdEn <= '0' ;
+ wait until Reset = '0';
+ wait until WrEn = '1';
+ wait until WrEn = '0';
+ for i in 0 to 19 loop
+ wait until RdClock'event and RdClock = '1';
+ RdEn <= '1' after 1 ns;
+ end loop;
+ RdEn <= '0' ;
+ wait;
+ end process;
+
+ process
+
+ begin
+ Reset <= '1' ;
+ wait for 100 ns;
+ Reset <= '0' ;
+ wait;
+ end process;
+
+ process
+
+ begin
+ RPReset <= '1' ;
+ wait for 100 ns;
+ RPReset <= '0' ;
+ wait;
+ end process;
+
+end architecture test;
--- /dev/null
+-- VHDL testbench template generated by SCUBA ispLever_v72_PROD_Build (44)
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity tb is
+end entity tb;
+
+
+architecture test of tb is
+
+ component dpram_8x19
+ port (WrAddress : in std_logic_vector(3 downto 0);
+ Data : in std_logic_vector(18 downto 0); WrClock: in std_logic;
+ WE: in std_logic; WrClockEn: in std_logic;
+ RdAddress : in std_logic_vector(3 downto 0);
+ Q : out std_logic_vector(18 downto 0)
+ );
+ end component;
+
+ signal WrAddress : std_logic_vector(3 downto 0) := (others => '0');
+ signal Data : std_logic_vector(18 downto 0) := (others => '0');
+ signal WrClock: std_logic := '0';
+ signal WE: std_logic := '0';
+ signal WrClockEn: std_logic := '0';
+ signal RdAddress : std_logic_vector(3 downto 0) := (others => '0');
+ signal Q : std_logic_vector(18 downto 0);
+begin
+ u1 : dpram_8x19
+ port map (WrAddress => WrAddress, Data => Data, WrClock => WrClock,
+ WE => WE, WrClockEn => WrClockEn, RdAddress => RdAddress, Q => Q
+ );
+
+ process
+
+ begin
+ WrAddress <= (others => '0') ;
+ wait for 100 ns;
+ wait for 10 ns;
+ for i in 0 to 38 loop
+ wait until WrClock'event and WrClock = '1';
+ WrAddress <= WrAddress + '1' after 1 ns;
+ end loop;
+ wait;
+ end process;
+
+ process
+
+ begin
+ Data <= (others => '0') ;
+ wait for 100 ns;
+ wait for 10 ns;
+ for i in 0 to 19 loop
+ wait until WrClock'event and WrClock = '1';
+ Data <= Data + '1' after 1 ns;
+ end loop;
+ wait;
+ end process;
+
+ WrClock <= not WrClock after 5.00 ns;
+
+ process
+
+ begin
+ WE <= '0' ;
+ wait for 10 ns;
+ for i in 0 to 19 loop
+ wait until WrClock'event and WrClock = '1';
+ WE <= '1' after 1 ns;
+ end loop;
+ WE <= '0' ;
+ wait;
+ end process;
+
+ process
+
+ begin
+ WrClockEn <= '0' ;
+ wait for 100 ns;
+ wait for 10 ns;
+ WrClockEn <= '1' ;
+ wait;
+ end process;
+
+ process
+
+ begin
+ RdAddress <= (others => '0') ;
+ wait for 100 ns;
+ wait for 10 ns;
+ for i in 0 to 38 loop
+ wait for 10 ns;
+ RdAddress <= RdAddress + '1' ;
+ end loop;
+ wait;
+ end process;
+
+end architecture test;
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT ipu_fifo_stage\r
+ PORT(\r
+ CLK_IN : IN std_logic;\r
+ RESET_IN : IN std_logic;\r
+ SECTOR_IN : IN std_logic_vector(2 downto 0);\r
+ MODULE_IN : IN std_logic_vector(2 downto 0);\r
+ IPU_NUMBER_IN : IN std_logic_vector(15 downto 0);\r
+ IPU_INFORMATION_IN : IN std_logic_vector(7 downto 0);\r
+ IPU_START_READOUT_IN : IN std_logic;\r
+ IPU_READ_IN : IN std_logic;\r
+ DHDR_DATA_IN : IN std_logic_vector(31 downto 0);\r
+ DHDR_LENGTH_IN : IN std_logic_vector(15 downto 0);\r
+ DHDR_STORE_IN : IN std_logic;\r
+ FIFO_START_IN : IN std_logic;\r
+ FIFO_0_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_1_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_2_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_3_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_4_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_5_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_6_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_7_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_8_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_9_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_10_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_11_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_12_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_13_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_14_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_15_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_WE_IN : IN std_logic_vector(15 downto 0);\r
+ FIFO_DONE_IN : IN std_logic; \r
+ IPU_DATA_OUT : OUT std_logic_vector(31 downto 0);\r
+ IPU_DATAREADY_OUT : OUT std_logic;\r
+ IPU_READOUT_FINISHED_OUT : OUT std_logic;\r
+ IPU_LENGTH_OUT : OUT std_logic_vector(15 downto 0);\r
+ IPU_ERROR_PATTERN_OUT : OUT std_logic_vector(31 downto 0);\r
+ DBG_BSM_OUT : OUT std_logic_vector(7 downto 0);\r
+ DBG_OUT : OUT std_logic_vector(63 downto 0)\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL CLK_IN : std_logic;\r
+ SIGNAL RESET_IN : std_logic;\r
+ SIGNAL SECTOR_IN : std_logic_vector(2 downto 0);\r
+ SIGNAL MODULE_IN : std_logic_vector(2 downto 0);\r
+ SIGNAL IPU_NUMBER_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL IPU_INFORMATION_IN : std_logic_vector(7 downto 0);\r
+ SIGNAL IPU_START_READOUT_IN : std_logic;\r
+ SIGNAL IPU_DATA_OUT : std_logic_vector(31 downto 0);\r
+ SIGNAL IPU_DATAREADY_OUT : std_logic;\r
+ SIGNAL IPU_READOUT_FINISHED_OUT : std_logic;\r
+ SIGNAL IPU_READ_IN : std_logic;\r
+ SIGNAL IPU_LENGTH_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL IPU_ERROR_PATTERN_OUT : std_logic_vector(31 downto 0);\r
+ SIGNAL DHDR_DATA_IN : std_logic_vector(31 downto 0);\r
+ SIGNAL DHDR_LENGTH_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL DHDR_STORE_IN : std_logic;\r
+ SIGNAL FIFO_START_IN : std_logic;\r
+ SIGNAL FIFO_0_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_1_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_2_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_3_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_4_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_5_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_6_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_7_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_8_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_9_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_10_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_11_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_12_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_13_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_14_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_15_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_WE_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL FIFO_DONE_IN : std_logic;\r
+ SIGNAL DBG_BSM_OUT : std_logic_vector(7 downto 0);\r
+ SIGNAL DBG_OUT : std_logic_vector(63 downto 0);\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: ipu_fifo_stage PORT MAP(\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ SECTOR_IN => SECTOR_IN,\r
+ MODULE_IN => MODULE_IN,\r
+ IPU_NUMBER_IN => IPU_NUMBER_IN,\r
+ IPU_INFORMATION_IN => IPU_INFORMATION_IN,\r
+ IPU_START_READOUT_IN => IPU_START_READOUT_IN,\r
+ IPU_DATA_OUT => IPU_DATA_OUT,\r
+ IPU_DATAREADY_OUT => IPU_DATAREADY_OUT,\r
+ IPU_READOUT_FINISHED_OUT => IPU_READOUT_FINISHED_OUT,\r
+ IPU_READ_IN => IPU_READ_IN,\r
+ IPU_LENGTH_OUT => IPU_LENGTH_OUT,\r
+ IPU_ERROR_PATTERN_OUT => IPU_ERROR_PATTERN_OUT,\r
+ DHDR_DATA_IN => DHDR_DATA_IN,\r
+ DHDR_LENGTH_IN => DHDR_LENGTH_IN,\r
+ DHDR_STORE_IN => DHDR_STORE_IN,\r
+ FIFO_START_IN => FIFO_START_IN,\r
+ FIFO_0_DATA_IN => FIFO_0_DATA_IN,\r
+ FIFO_1_DATA_IN => FIFO_1_DATA_IN,\r
+ FIFO_2_DATA_IN => FIFO_2_DATA_IN,\r
+ FIFO_3_DATA_IN => FIFO_3_DATA_IN,\r
+ FIFO_4_DATA_IN => FIFO_4_DATA_IN,\r
+ FIFO_5_DATA_IN => FIFO_5_DATA_IN,\r
+ FIFO_6_DATA_IN => FIFO_6_DATA_IN,\r
+ FIFO_7_DATA_IN => FIFO_7_DATA_IN,\r
+ FIFO_8_DATA_IN => FIFO_8_DATA_IN,\r
+ FIFO_9_DATA_IN => FIFO_9_DATA_IN,\r
+ FIFO_10_DATA_IN => FIFO_10_DATA_IN,\r
+ FIFO_11_DATA_IN => FIFO_11_DATA_IN,\r
+ FIFO_12_DATA_IN => FIFO_12_DATA_IN,\r
+ FIFO_13_DATA_IN => FIFO_13_DATA_IN,\r
+ FIFO_14_DATA_IN => FIFO_14_DATA_IN,\r
+ FIFO_15_DATA_IN => FIFO_15_DATA_IN,\r
+ FIFO_WE_IN => FIFO_WE_IN,\r
+ FIFO_DONE_IN => FIFO_DONE_IN,\r
+ DBG_BSM_OUT => DBG_BSM_OUT,\r
+ DBG_OUT => DBG_OUT\r
+ );\r
+\r
+-- Generate the clock\r
+THE_CLOCK_GEN: process\r
+begin\r
+ clk_in <= '0'; wait for 5 ns;\r
+ clk_in <= '1'; wait for 5 ns;\r
+end process THE_CLOCK_GEN;\r
+\r
+-- The real testbench\r
+THE_TESTBENCH_PROC: process\r
+variable LOOP_I: integer;\r
+begin\r
+ -- Setup signals\r
+ reset_in <= '0';\r
+ module_in <= "000";\r
+ sector_in <= "111";\r
+ ipu_number_in <= x"0000";\r
+ ipu_information_in <= x"00";\r
+ ipu_start_readout_in <= '0';\r
+ ipu_read_in <= '0';\r
+ dhdr_data_in <= x"01234567";\r
+ dhdr_length_in <= x"0000";\r
+ dhdr_store_in <= '0';\r
+ fifo_start_in <= '0';\r
+ fifo_we_in <= x"0000";\r
+ fifo_done_in <= '0';\r
+ fifo_0_data_in <= (others => '0');\r
+ fifo_1_data_in <= (others => '0');\r
+ fifo_2_data_in <= (others => '0');\r
+ fifo_3_data_in <= (others => '0');\r
+ fifo_4_data_in <= (others => '0');\r
+ fifo_5_data_in <= (others => '0');\r
+ fifo_6_data_in <= (others => '0');\r
+ fifo_7_data_in <= (others => '0');\r
+ fifo_8_data_in <= (others => '0');\r
+ fifo_9_data_in <= (others => '0');\r
+ fifo_10_data_in <= (others => '0');\r
+ fifo_11_data_in <= (others => '0');\r
+ fifo_12_data_in <= (others => '0');\r
+ fifo_13_data_in <= (others => '0');\r
+ fifo_14_data_in <= (others => '0');\r
+ fifo_15_data_in <= (others => '0');\r
+ \r
+ wait for 20 ns;\r
+ \r
+ -- Do a reset\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- test may start here\r
+\r
+ -- Data is coming from processing stage\r
+ -- Start of event\r
+ wait until rising_edge(clk_in);\r
+ fifo_start_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ fifo_start_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- Fill data buffers\r
+ wait until rising_edge(clk_in);\r
+ fifo_we_in <= b"1111_1111_1111_1111";\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_1111";\r
+ fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0001_1110";\r
+ fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0010_1101";\r
+ fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0011_1100";\r
+ fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0100_1011";\r
+ fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0101_1010";\r
+ fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0110_1001";\r
+ fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0111_1000";\r
+ fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_1000_0111";\r
+ fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_1001_0110";\r
+ fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_1010_0101";\r
+ fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_1011_0100";\r
+ fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_1100_0011";\r
+ fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_1101_0010";\r
+ fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_1110_0001";\r
+ fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_1111_0000";\r
+ wait until rising_edge(clk_in);\r
+ fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000";\r
+ fifo_we_in(0) <= '0';\r
+ wait until rising_edge(clk_in);\r
+\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- Final stage, counter values setting\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ fifo_0_data_in(37 downto 27) <= "10000000001"; -- "10000000011"; -- 3\r
+ fifo_1_data_in(37 downto 27) <= "10000000001"; -- "00000000000"; -- invalid\r
+ fifo_2_data_in(37 downto 27) <= "10000000001"; -- "00000000000"; -- invalid\r
+ fifo_3_data_in(37 downto 27) <= "10000000001"; -- "00000000000"; -- invalid\r
+ fifo_4_data_in(37 downto 27) <= "10000000001"; -- "10000000101"; -- 5\r
+ fifo_5_data_in(37 downto 27) <= "10000000001"; -- "00000000000"; -- invalid\r
+ fifo_6_data_in(37 downto 27) <= "10000000001"; -- "00000000000"; -- invalid\r
+ fifo_7_data_in(37 downto 27) <= "10000000001"; -- "10000000111"; -- 7\r
+ fifo_8_data_in(37 downto 27) <= "10000000001"; -- "10000000001"; -- 1\r
+ fifo_9_data_in(37 downto 27) <= "10000000001"; -- "10000000010"; -- 2\r
+ fifo_10_data_in(37 downto 27) <= "10000000001"; -- "00000000000"; -- invalid\r
+ fifo_11_data_in(37 downto 27) <= "10000000001"; -- "00000000000"; -- invalid\r
+ fifo_12_data_in(37 downto 27) <= "10000000001"; -- "00000000000"; -- invalid\r
+ fifo_13_data_in(37 downto 27) <= "10000000001"; -- "10000001000"; -- 8\r
+ fifo_14_data_in(37 downto 27) <= "10000000001"; -- "10000000111"; -- 7\r
+ fifo_15_data_in(37 downto 27) <= "10000000001"; -- "00000000000"; -- invalid\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- Event (0) DHDR\r
+ wait until rising_edge(clk_in);\r
+ dhdr_data_in <= x"1abbcccc";\r
+ dhdr_length_in <= x"0010";\r
+ dhdr_store_in <= '1';\r
+ fifo_done_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ dhdr_store_in <= '0';\r
+ fifo_done_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ \r
+ -- IPU request\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ ipu_number_in <= x"cccc";\r
+ ipu_information_in <= x"ff";\r
+ ipu_start_readout_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+\r
+\r
+ -- wait for statemachine to react \r
+ -- transfer DHDR\r
+ wait until rising_edge(ipu_dataready_out);\r
+ wait until rising_edge(clk_in);\r
+ ipu_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ ipu_read_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ ipu_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ ipu_read_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ ipu_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ ipu_read_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ ipu_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ ipu_read_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ ipu_read_in <= '1';\r
+ wait until rising_edge(ipu_readout_finished_out);\r
+ wait until rising_edge(clk_in);\r
+ ipu_read_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ ipu_start_readout_in <= '0';\r
+ \r
+ wait;\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+ ------------------------------------------------------------------------\r
+ ------------------------------------------------------------------------\r
+\r
+ -- wait for statemachine to react \r
+ -- DHDR\r
+ wait until rising_edge(ipu_dataready_out);\r
+-- wait until rising_edge(clk_in);\r
+-- wait until rising_edge(clk_in);\r
+-- wait until rising_edge(clk_in);\r
+ ipu_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ ipu_read_in <= '0';\r
+\r
+ DATA_LOOP: for LOOP_I in 34 downto 0 loop\r
+ -- one data word\r
+ wait until rising_edge(ipu_dataready_out);\r
+-- wait until rising_edge(clk_in);\r
+-- wait until rising_edge(clk_in);\r
+-- wait until rising_edge(clk_in);\r
+ ipu_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ ipu_read_in <= '0';\r
+ end loop DATA_LOOP;\r
+\r
+\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- Stay a while, stay forever.... wuhahahahaha\r
+ wait;\r
+end process THE_TESTBENCH_PROC;\r
+\r
+\r
+END;\r
+\r
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT ipu_fifo_stage\r
+ PORT(\r
+ CLK_IN : IN std_logic;\r
+ RESET_IN : IN std_logic;\r
+ SECTOR_IN : IN std_logic_vector(2 downto 0);\r
+ MODULE_IN : IN std_logic_vector(2 downto 0);\r
+ IPU_NUMBER_IN : IN std_logic_vector(15 downto 0);\r
+ IPU_INFORMATION_IN : IN std_logic_vector(7 downto 0);\r
+ IPU_START_READOUT_IN : IN std_logic;\r
+ IPU_READ_IN : IN std_logic;\r
+ DHDR_DATA_IN : IN std_logic_vector(31 downto 0);\r
+ DHDR_LENGTH_IN : IN std_logic_vector(15 downto 0);\r
+ DHDR_STORE_IN : IN std_logic;\r
+ FIFO_START_IN : IN std_logic;\r
+ FIFO_0_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_1_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_2_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_3_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_4_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_5_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_6_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_7_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_8_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_9_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_10_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_11_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_12_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_13_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_14_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_15_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ FIFO_WE_IN : IN std_logic_vector(15 downto 0);\r
+ FIFO_DONE_IN : IN std_logic; \r
+ IPU_DATA_OUT : OUT std_logic_vector(31 downto 0);\r
+ IPU_DATAREADY_OUT : OUT std_logic;\r
+ IPU_READOUT_FINISHED_OUT : OUT std_logic;\r
+ IPU_LENGTH_OUT : OUT std_logic_vector(15 downto 0);\r
+ IPU_ERROR_PATTERN_OUT : OUT std_logic_vector(31 downto 0);\r
+ DBG_BSM_OUT : OUT std_logic_vector(7 downto 0);\r
+ DBG_OUT : OUT std_logic_vector(63 downto 0)\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL CLK_IN : std_logic;\r
+ SIGNAL RESET_IN : std_logic;\r
+ SIGNAL SECTOR_IN : std_logic_vector(2 downto 0);\r
+ SIGNAL MODULE_IN : std_logic_vector(2 downto 0);\r
+ SIGNAL IPU_NUMBER_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL IPU_INFORMATION_IN : std_logic_vector(7 downto 0);\r
+ SIGNAL IPU_START_READOUT_IN : std_logic;\r
+ SIGNAL IPU_DATA_OUT : std_logic_vector(31 downto 0);\r
+ SIGNAL IPU_DATAREADY_OUT : std_logic;\r
+ SIGNAL IPU_READOUT_FINISHED_OUT : std_logic;\r
+ SIGNAL IPU_READ_IN : std_logic;\r
+ SIGNAL IPU_LENGTH_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL IPU_ERROR_PATTERN_OUT : std_logic_vector(31 downto 0);\r
+ SIGNAL DHDR_DATA_IN : std_logic_vector(31 downto 0);\r
+ SIGNAL DHDR_LENGTH_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL DHDR_STORE_IN : std_logic;\r
+ SIGNAL FIFO_START_IN : std_logic;\r
+ SIGNAL FIFO_0_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_1_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_2_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_3_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_4_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_5_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_6_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_7_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_8_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_9_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_10_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_11_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_12_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_13_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_14_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_15_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_WE_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL FIFO_DONE_IN : std_logic;\r
+ SIGNAL DBG_BSM_OUT : std_logic_vector(7 downto 0);\r
+ SIGNAL DBG_OUT : std_logic_vector(63 downto 0);\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: ipu_fifo_stage PORT MAP(\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ SECTOR_IN => SECTOR_IN,\r
+ MODULE_IN => MODULE_IN,\r
+ IPU_NUMBER_IN => IPU_NUMBER_IN,\r
+ IPU_INFORMATION_IN => IPU_INFORMATION_IN,\r
+ IPU_START_READOUT_IN => IPU_START_READOUT_IN,\r
+ IPU_DATA_OUT => IPU_DATA_OUT,\r
+ IPU_DATAREADY_OUT => IPU_DATAREADY_OUT,\r
+ IPU_READOUT_FINISHED_OUT => IPU_READOUT_FINISHED_OUT,\r
+ IPU_READ_IN => IPU_READ_IN,\r
+ IPU_LENGTH_OUT => IPU_LENGTH_OUT,\r
+ IPU_ERROR_PATTERN_OUT => IPU_ERROR_PATTERN_OUT,\r
+ DHDR_DATA_IN => DHDR_DATA_IN,\r
+ DHDR_LENGTH_IN => DHDR_LENGTH_IN,\r
+ DHDR_STORE_IN => DHDR_STORE_IN,\r
+ FIFO_START_IN => FIFO_START_IN,\r
+ FIFO_0_DATA_IN => FIFO_0_DATA_IN,\r
+ FIFO_1_DATA_IN => FIFO_1_DATA_IN,\r
+ FIFO_2_DATA_IN => FIFO_2_DATA_IN,\r
+ FIFO_3_DATA_IN => FIFO_3_DATA_IN,\r
+ FIFO_4_DATA_IN => FIFO_4_DATA_IN,\r
+ FIFO_5_DATA_IN => FIFO_5_DATA_IN,\r
+ FIFO_6_DATA_IN => FIFO_6_DATA_IN,\r
+ FIFO_7_DATA_IN => FIFO_7_DATA_IN,\r
+ FIFO_8_DATA_IN => FIFO_8_DATA_IN,\r
+ FIFO_9_DATA_IN => FIFO_9_DATA_IN,\r
+ FIFO_10_DATA_IN => FIFO_10_DATA_IN,\r
+ FIFO_11_DATA_IN => FIFO_11_DATA_IN,\r
+ FIFO_12_DATA_IN => FIFO_12_DATA_IN,\r
+ FIFO_13_DATA_IN => FIFO_13_DATA_IN,\r
+ FIFO_14_DATA_IN => FIFO_14_DATA_IN,\r
+ FIFO_15_DATA_IN => FIFO_15_DATA_IN,\r
+ FIFO_WE_IN => FIFO_WE_IN,\r
+ FIFO_DONE_IN => FIFO_DONE_IN,\r
+ DBG_BSM_OUT => DBG_BSM_OUT,\r
+ DBG_OUT => DBG_OUT\r
+ );\r
+\r
+-- Generate the clock\r
+THE_CLOCK_GEN: process\r
+begin\r
+ clk_in <= '0'; wait for 5 ns;\r
+ clk_in <= '1'; wait for 5 ns;\r
+end process THE_CLOCK_GEN;\r
+\r
+-- The real testbench\r
+THE_TESTBENCH_PROC: process\r
+variable LOOP_I: integer;\r
+begin\r
+ -- Setup signals\r
+ reset_in <= '0';\r
+ module_in <= "000";\r
+ sector_in <= "111";\r
+ ipu_number_in <= x"0000";\r
+ ipu_information_in <= x"00";\r
+ ipu_start_readout_in <= '0';\r
+ ipu_read_in <= '0';\r
+ dhdr_data_in <= x"01234567";\r
+ dhdr_length_in <= x"0000";\r
+ dhdr_store_in <= '0';\r
+ fifo_start_in <= '0';\r
+ fifo_we_in <= x"0000";\r
+ fifo_done_in <= '0';\r
+ fifo_0_data_in <= (others => '0');\r
+ fifo_1_data_in <= (others => '0');\r
+ fifo_2_data_in <= (others => '0');\r
+ fifo_3_data_in <= (others => '0');\r
+ fifo_4_data_in <= (others => '0');\r
+ fifo_5_data_in <= (others => '0');\r
+ fifo_6_data_in <= (others => '0');\r
+ fifo_7_data_in <= (others => '0');\r
+ fifo_8_data_in <= (others => '0');\r
+ fifo_9_data_in <= (others => '0');\r
+ fifo_10_data_in <= (others => '0');\r
+ fifo_11_data_in <= (others => '0');\r
+ fifo_12_data_in <= (others => '0');\r
+ fifo_13_data_in <= (others => '0');\r
+ fifo_14_data_in <= (others => '0');\r
+ fifo_15_data_in <= (others => '0');\r
+ \r
+ wait for 20 ns;\r
+ \r
+ -- Do a reset\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- test may start here\r
+\r
+ -- Data is coming from processing stage\r
+ -- Start of event\r
+ wait until rising_edge(clk_in);\r
+ fifo_start_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ fifo_start_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- Fill data buffers\r
+ -- FIFO 0 - 3 data words\r
+ wait until rising_edge(clk_in);\r
+ fifo_we_in(0) <= '1';\r
+ fifo_0_data_in(26 downto 0) <= b"111_111_0000000_00_0000_0001_0001";\r
+ wait until rising_edge(clk_in);\r
+ fifo_0_data_in(26 downto 0) <= b"111_111_0000001_00_0000_0010_0010";\r
+ wait until rising_edge(clk_in);\r
+ fifo_0_data_in(26 downto 0) <= b"111_111_0000010_00_0000_0011_0011";\r
+ wait until rising_edge(clk_in);\r
+ fifo_0_data_in(26 downto 0) <= b"000_000_0000000_00_0000_0000_0000";\r
+ fifo_we_in(0) <= '0';\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- FIFO 4 - 5 data words\r
+ wait until rising_edge(clk_in);\r
+ fifo_we_in(4) <= '1';\r
+ fifo_4_data_in(26 downto 0) <= b"111_111_0000000_00_0100_0001_0001";\r
+ wait until rising_edge(clk_in);\r
+ fifo_4_data_in(26 downto 0) <= b"111_111_0000001_00_0100_0010_0010";\r
+ wait until rising_edge(clk_in);\r
+ fifo_4_data_in(26 downto 0) <= b"111_111_0000010_00_0100_0011_0011";\r
+ wait until rising_edge(clk_in);\r
+ fifo_4_data_in(26 downto 0) <= b"111_111_0000011_00_0100_0100_0100";\r
+ wait until rising_edge(clk_in);\r
+ fifo_4_data_in(26 downto 0) <= b"111_111_0000100_00_0100_0101_0101";\r
+ wait until rising_edge(clk_in);\r
+ fifo_4_data_in(26 downto 0) <= b"000_000_0000000_00_0000_0000_0000";\r
+ fifo_we_in(4) <= '0';\r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- FIFO 7 - 7 data words\r
+ wait until rising_edge(clk_in);\r
+ fifo_we_in(7) <= '1';\r
+ fifo_7_data_in(26 downto 0) <= b"111_111_0000000_00_0111_0001_0001";\r
+ wait until rising_edge(clk_in);\r
+ fifo_7_data_in(26 downto 0) <= b"111_111_0000001_00_0111_0010_0010";\r
+ wait until rising_edge(clk_in);\r
+ fifo_7_data_in(26 downto 0) <= b"111_111_0000010_00_0111_0011_0011";\r
+ wait until rising_edge(clk_in);\r
+ fifo_7_data_in(26 downto 0) <= b"111_111_0000011_00_0111_0100_0100";\r
+ wait until rising_edge(clk_in);\r
+ fifo_7_data_in(26 downto 0) <= b"111_111_0000100_00_0111_0101_0101";\r
+ wait until rising_edge(clk_in);\r
+ fifo_7_data_in(26 downto 0) <= b"111_111_0000101_00_0111_0110_0110";\r
+ wait until rising_edge(clk_in);\r
+ fifo_7_data_in(26 downto 0) <= b"111_111_0000110_00_0111_0111_0111";\r
+ wait until rising_edge(clk_in);\r
+ fifo_7_data_in(26 downto 0) <= b"000_000_0000000_00_0000_0000_0000";\r
+ fifo_we_in(7) <= '0';\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- FIFO 8 - 1 data words\r
+ wait until rising_edge(clk_in);\r
+ fifo_we_in(8) <= '1';\r
+ fifo_8_data_in(26 downto 0) <= b"111_111_0000000_00_1000_0001_0001";\r
+ wait until rising_edge(clk_in);\r
+ fifo_8_data_in(26 downto 0) <= b"000_000_0000000_00_0000_0000_0000";\r
+ fifo_we_in(8) <= '0';\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- FIFO 9 - 2 data words\r
+ wait until rising_edge(clk_in);\r
+ fifo_we_in(9) <= '1';\r
+ fifo_9_data_in(26 downto 0) <= b"111_111_0000000_00_1001_0001_0001";\r
+ wait until rising_edge(clk_in);\r
+ fifo_9_data_in(26 downto 0) <= b"111_111_0000001_00_1001_0010_0010";\r
+ wait until rising_edge(clk_in);\r
+ fifo_9_data_in(26 downto 0) <= b"000_000_0000000_00_0000_0000_0000";\r
+ fifo_we_in(9) <= '0';\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- FIFO 13 - 8 data words\r
+ wait until rising_edge(clk_in);\r
+ fifo_we_in(13) <= '1';\r
+ fifo_13_data_in(26 downto 0) <= b"111_111_0000000_00_1101_0001_0001";\r
+ wait until rising_edge(clk_in);\r
+ fifo_13_data_in(26 downto 0) <= b"111_111_0000001_00_1101_0010_0010";\r
+ wait until rising_edge(clk_in);\r
+ fifo_13_data_in(26 downto 0) <= b"111_111_0000010_00_1101_0011_0011";\r
+ wait until rising_edge(clk_in);\r
+ fifo_13_data_in(26 downto 0) <= b"111_111_0000011_00_1101_0100_0100";\r
+ wait until rising_edge(clk_in);\r
+ fifo_13_data_in(26 downto 0) <= b"111_111_0000100_00_1101_0101_0101";\r
+ wait until rising_edge(clk_in);\r
+ fifo_13_data_in(26 downto 0) <= b"111_111_0000101_00_1101_0110_0110";\r
+ wait until rising_edge(clk_in);\r
+ fifo_13_data_in(26 downto 0) <= b"111_111_0000110_00_1101_0111_0111";\r
+ wait until rising_edge(clk_in);\r
+ fifo_13_data_in(26 downto 0) <= b"111_111_0000111_00_1101_1000_1000";\r
+ wait until rising_edge(clk_in);\r
+ fifo_13_data_in(26 downto 0) <= b"000_000_0000000_00_0000_0000_0000";\r
+ fifo_we_in(13) <= '0';\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- FIFO 14 - 7 data words\r
+ wait until rising_edge(clk_in);\r
+ fifo_we_in(14) <= '1';\r
+ fifo_14_data_in(26 downto 0) <= b"111_111_0000000_00_1110_0001_0001";\r
+ wait until rising_edge(clk_in);\r
+ fifo_14_data_in(26 downto 0) <= b"111_111_0000001_00_1110_0010_0010";\r
+ wait until rising_edge(clk_in);\r
+ fifo_14_data_in(26 downto 0) <= b"111_111_0000010_00_1110_0011_0011";\r
+ wait until rising_edge(clk_in);\r
+ fifo_14_data_in(26 downto 0) <= b"111_111_0000011_00_1110_0100_0100";\r
+ wait until rising_edge(clk_in);\r
+ fifo_14_data_in(26 downto 0) <= b"111_111_0000100_00_1110_0101_0101";\r
+ wait until rising_edge(clk_in);\r
+ fifo_14_data_in(26 downto 0) <= b"111_111_0000101_00_1110_0110_0110";\r
+ wait until rising_edge(clk_in);\r
+ fifo_14_data_in(26 downto 0) <= b"111_111_0000110_00_1110_0111_0111";\r
+ wait until rising_edge(clk_in);\r
+ fifo_14_data_in(26 downto 0) <= b"000_000_0000000_00_0000_0000_0000";\r
+ fifo_we_in(14) <= '0';\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- Final stage, counter values setting\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ fifo_0_data_in(37 downto 27) <= "10000000010"; -- "10000000011"; -- 3\r
+ fifo_1_data_in(37 downto 27) <= "00000000000"; -- "00000000000"; -- invalid\r
+ fifo_2_data_in(37 downto 27) <= "00000000000"; -- "00000000000"; -- invalid\r
+ fifo_3_data_in(37 downto 27) <= "00000000000"; -- "00000000000"; -- invalid\r
+ fifo_4_data_in(37 downto 27) <= "10000000100"; -- "10000000101"; -- 5\r
+ fifo_5_data_in(37 downto 27) <= "00000000000"; -- "00000000000"; -- invalid\r
+ fifo_6_data_in(37 downto 27) <= "00000000000"; -- "00000000000"; -- invalid\r
+ fifo_7_data_in(37 downto 27) <= "10000000110"; -- "10000000111"; -- 7\r
+ fifo_8_data_in(37 downto 27) <= "10000000000"; -- "10000000001"; -- 1\r
+ fifo_9_data_in(37 downto 27) <= "10000000001"; -- "10000000010"; -- 2\r
+ fifo_10_data_in(37 downto 27) <= "00000000000"; -- "00000000000"; -- invalid\r
+ fifo_11_data_in(37 downto 27) <= "00000000000"; -- "00000000000"; -- invalid\r
+ fifo_12_data_in(37 downto 27) <= "00000000000"; -- "00000000000"; -- invalid\r
+ fifo_13_data_in(37 downto 27) <= "10000000111"; -- "10000001000"; -- 8\r
+ fifo_14_data_in(37 downto 27) <= "10000000110"; -- "10000000111"; -- 7\r
+ fifo_15_data_in(37 downto 27) <= "00000000000"; -- "00000000000"; -- invalid\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- Event (0) DHDR\r
+ wait until rising_edge(clk_in);\r
+ dhdr_data_in <= x"1abbcccc";\r
+ dhdr_length_in <= x"0021";\r
+ dhdr_store_in <= '1';\r
+ fifo_done_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ dhdr_store_in <= '0';\r
+ fifo_done_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ \r
+ -- IPU request\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ ipu_number_in <= x"cccc";\r
+ ipu_information_in <= x"ff";\r
+ ipu_start_readout_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+\r
+\r
+ -- wait for statemachine to react \r
+ -- transfer DHDR\r
+ wait until rising_edge(ipu_dataready_out);\r
+ wait until rising_edge(clk_in);\r
+ ipu_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ ipu_read_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ ipu_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ ipu_read_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ ipu_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ ipu_read_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ ipu_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ ipu_read_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ ipu_read_in <= '1';\r
+ wait until rising_edge(ipu_readout_finished_out);\r
+ wait until rising_edge(clk_in);\r
+ ipu_read_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ ipu_start_readout_in <= '0';\r
+ \r
+ wait;\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+ ------------------------------------------------------------------------\r
+ ------------------------------------------------------------------------\r
+\r
+ -- wait for statemachine to react \r
+ -- DHDR\r
+ wait until rising_edge(ipu_dataready_out);\r
+-- wait until rising_edge(clk_in);\r
+-- wait until rising_edge(clk_in);\r
+-- wait until rising_edge(clk_in);\r
+ ipu_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ ipu_read_in <= '0';\r
+\r
+ DATA_LOOP: for LOOP_I in 34 downto 0 loop\r
+ -- one data word\r
+ wait until rising_edge(ipu_dataready_out);\r
+-- wait until rising_edge(clk_in);\r
+-- wait until rising_edge(clk_in);\r
+-- wait until rising_edge(clk_in);\r
+ ipu_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ ipu_read_in <= '0';\r
+ end loop DATA_LOOP;\r
+\r
+\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- Stay a while, stay forever.... wuhahahahaha\r
+ wait;\r
+end process THE_TESTBENCH_PROC;\r
+\r
+\r
+END;\r
+\r
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT logic_analyzer\r
+ PORT(\r
+ CLK_IN : IN std_logic;\r
+ RESET_IN : IN std_logic;\r
+ ARM_IN : IN std_logic;\r
+ TRG_IN : IN std_logic;\r
+ MAX_SAMPLE_IN : IN std_logic_vector(9 downto 0); \r
+ SM_ADDR_OUT : OUT std_logic_vector(9 downto 0);\r
+ SM_CE_OUT : OUT std_logic;\r
+ SM_WE_OUT : OUT std_logic;\r
+ CLEAR_OUT : OUT std_logic;\r
+ RUN_OUT : OUT std_logic;\r
+ SAMPLE_OUT : OUT std_logic;\r
+ READY_OUT : OUT std_logic;\r
+ LAST_OUT : OUT std_logic;\r
+ BSM_OUT : OUT std_logic_vector(3 downto 0);\r
+ STAT : OUT std_logic_vector(31 downto 0)\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL CLK_IN : std_logic;\r
+ SIGNAL RESET_IN : std_logic;\r
+ SIGNAL ARM_IN : std_logic;\r
+ SIGNAL TRG_IN : std_logic;\r
+ SIGNAL MAX_SAMPLE_IN : std_logic_vector(9 downto 0);\r
+ SIGNAL SM_ADDR_OUT : std_logic_vector(9 downto 0);\r
+ SIGNAL SM_CE_OUT : std_logic;\r
+ SIGNAL SM_WE_OUT : std_logic;\r
+ SIGNAL CLEAR_OUT : std_logic;\r
+ SIGNAL RUN_OUT : std_logic;\r
+ SIGNAL SAMPLE_OUT : std_logic;\r
+ SIGNAL READY_OUT : std_logic;\r
+ SIGNAL LAST_OUT : std_logic;\r
+ SIGNAL BSM_OUT : std_logic_vector(3 downto 0);\r
+ SIGNAL STAT : std_logic_vector(31 downto 0);\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: logic_analyzer PORT MAP(\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ ARM_IN => ARM_IN,\r
+ TRG_IN => TRG_IN,\r
+ MAX_SAMPLE_IN => MAX_SAMPLE_IN,\r
+ SM_ADDR_OUT => SM_ADDR_OUT,\r
+ SM_CE_OUT => SM_CE_OUT,\r
+ SM_WE_OUT => SM_WE_OUT,\r
+ CLEAR_OUT => CLEAR_OUT,\r
+ RUN_OUT => RUN_OUT,\r
+ SAMPLE_OUT => SAMPLE_OUT,\r
+ READY_OUT => READY_OUT,\r
+ LAST_OUT => LAST_OUT,\r
+ BSM_OUT => BSM_OUT,\r
+ STAT => STAT\r
+ );\r
+\r
+\r
+THE_CLOCK_GEN: process\r
+begin\r
+ clk_in <= '1'; wait for 5 ns;\r
+ clk_in <= '0'; wait for 5 ns;\r
+end process THE_CLOCK_GEN;\r
+\r
+\r
+THE_TEST_BENCH: process\r
+begin\r
+ -- Setup signals\r
+ reset_in <= '0';\r
+ trg_in <= '0';\r
+ arm_in <= '0';\r
+ max_sample_in <= b"00_0000_1000";\r
+ wait for 100 ns;\r
+\r
+ -- Reset all\r
+ reset_in <= '1';\r
+ wait for 100 ns;\r
+ reset_in <= '0';\r
+ wait for 400 ns;\r
+\r
+ -- Tests may start now\r
+ -- arm the machine\r
+ wait until rising_edge(clk_in);\r
+ arm_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ arm_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- wait for memory clear\r
+ wait until rising_edge(run_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- trigger it\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ trg_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ trg_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- wait for end of cycle\r
+ wait until rising_edge(last_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ wait for 200 ns;\r
+\r
+ -- retrigger\r
+ max_sample_in <= b"00_0000_1111";\r
+ wait until rising_edge(clk_in);\r
+ arm_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ arm_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- wait for memory clear\r
+ wait until rising_edge(run_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- trigger it\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ trg_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ trg_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+\r
+ \r
+ -- Stay a while, stay forever!\r
+ wait;\r
+end process THE_TEST_BENCH;\r
+\r
+END;\r
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT max_data\r
+ PORT(\r
+ CLK_IN : IN std_logic;\r
+ RESET_IN : IN std_logic;\r
+ TODO_3_IN : IN std_logic_vector(3 downto 0);\r
+ TODO_2_IN : IN std_logic_vector(3 downto 0);\r
+ TODO_1_IN : IN std_logic_vector(3 downto 0);\r
+ TODO_0_IN : IN std_logic_vector(3 downto 0); \r
+ TODO_MAX_OUT : OUT std_logic_vector(3 downto 0);\r
+ DEBUG_OUT : OUT std_logic_vector(15 downto 0)\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL CLK_IN : std_logic;\r
+ SIGNAL RESET_IN : std_logic;\r
+ SIGNAL TODO_3_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL TODO_2_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL TODO_1_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL TODO_0_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL TODO_MAX_OUT : std_logic_vector(3 downto 0);\r
+ SIGNAL DEBUG_OUT : std_logic_vector(15 downto 0);\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: max_data PORT MAP(\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ TODO_3_IN => TODO_3_IN,\r
+ TODO_2_IN => TODO_2_IN,\r
+ TODO_1_IN => TODO_1_IN,\r
+ TODO_0_IN => TODO_0_IN,\r
+ TODO_MAX_OUT => TODO_MAX_OUT,\r
+ DEBUG_OUT => DEBUG_OUT\r
+ );\r
+\r
+THE_CLOCK_GEN: process\r
+begin\r
+ clk_in <= '1'; wait for 5 ns;\r
+ clk_in <= '0'; wait for 5 ns;\r
+end process THE_CLOCK_GEN;\r
+\r
+THE_TEST_BENCH: process\r
+begin\r
+ -- Setup signals\r
+ reset_in <= '0';\r
+ todo_3_in <= x"0";\r
+ todo_2_in <= x"5";\r
+ todo_1_in <= x"0";\r
+ todo_0_in <= x"7";\r
+ \r
+ -- Sync reset\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait for 140 ns;\r
+ \r
+ -- Tests may start now\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ todo_3_in <= x"0";\r
+ todo_2_in <= x"1";\r
+ todo_1_in <= x"f";\r
+ todo_0_in <= x"c";\r
+\r
+\r
+ -- Stay a while, stay forever....\r
+ wait;\r
+end process THE_TEST_BENCH; \r
+\r
+\r
+END;\r
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT mult_3x8 is\r
+ PORT( CLOCK : in std_logic; \r
+ CLKEN : in std_logic; \r
+ ACLR : in std_logic; \r
+ DATAA : in std_logic_vector(2 downto 0); \r
+ DATAB : in std_logic_vector(7 downto 0); \r
+ RESULT : out std_logic_vector(10 downto 0)\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL CLOCK : std_logic;\r
+ SIGNAL CLKEN : std_logic;\r
+ SIGNAL ACLR : std_logic;\r
+ SIGNAL DATAA : std_logic_vector(2 downto 0);\r
+ SIGNAL DATAB : std_logic_vector(7 downto 0);\r
+ SIGNAL RESULT : std_logic_vector(10 downto 0);\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: mult_3x8 PORT MAP(\r
+ CLOCK => CLOCK,\r
+ CLKEN => CLKEN,\r
+ ACLR => ACLR,\r
+ DATAA => DATAA,\r
+ DATAB => DATAB,\r
+ RESULT => RESULT\r
+ );\r
+\r
+-- Generate the clock\r
+THE_CLOCK_GEN: process\r
+begin\r
+ clock <= '0'; wait for 5 ns;\r
+ clock <= '1'; wait for 5 ns;\r
+end process THE_CLOCK_GEN;\r
+\r
+-- The real testbench\r
+THE_TESTBENCH_PROC: process\r
+begin\r
+ -- Setup signals\r
+ aclr <= '0';\r
+ clken <= '1';\r
+ dataa <= b"000";\r
+ datab <= b"0000_0000";\r
+ \r
+ wait for 20 ns;\r
+ \r
+ -- Do a reset\r
+ wait until rising_edge(clock);\r
+ aclr <= '1';\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+ aclr <= '0';\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+ \r
+ -- test may start here\r
+ wait until rising_edge(clock);\r
+ dataa <= b"000";\r
+ datab <= x"81";\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+\r
+ wait until rising_edge(clock);\r
+ dataa <= b"001";\r
+ datab <= x"81";\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+\r
+ wait until rising_edge(clock);\r
+ dataa <= b"010";\r
+ datab <= x"81";\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+ \r
+ wait until rising_edge(clock);\r
+ dataa <= b"011";\r
+ datab <= x"81";\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+\r
+ wait until rising_edge(clock);\r
+ dataa <= b"100";\r
+ datab <= x"81";\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+\r
+ wait until rising_edge(clock);\r
+ dataa <= b"101";\r
+ datab <= x"81";\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+\r
+ wait until rising_edge(clock);\r
+ dataa <= b"110";\r
+ datab <= x"81";\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+\r
+ wait until rising_edge(clock);\r
+ dataa <= b"111";\r
+ datab <= x"81";\r
+ wait until rising_edge(clock);\r
+ wait until rising_edge(clock);\r
+\r
+ -- Stay a while, stay forever.... wuhahahahaha\r
+ wait;\r
+end process THE_TESTBENCH_PROC;\r
+\r
+\r
+END;\r
+\r
+\r
--- /dev/null
+-- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23)
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity tb is
+end entity tb;
+
+
+architecture test of tb is
+
+ component mult_3x8
+ port (Clock: in std_logic; ClkEn: in std_logic;
+ Aclr: in std_logic; DataA : in std_logic_vector(2 downto 0);
+ DataB : in std_logic_vector(7 downto 0);
+ Result : out std_logic_vector(10 downto 0)
+ );
+ end component;
+
+ signal Clock: std_logic := '0';
+ signal ClkEn: std_logic := '0';
+ signal Aclr: std_logic := '0';
+ signal DataA : std_logic_vector(2 downto 0) := (others => '0');
+ signal DataB : std_logic_vector(7 downto 0) := (others => '0');
+ signal Result : std_logic_vector(10 downto 0);
+begin
+ u1 : mult_3x8
+ port map (Clock => Clock, ClkEn => ClkEn, Aclr => Aclr, DataA => DataA,
+ DataB => DataB, Result => Result
+ );
+
+ Clock <= not Clock after 5.00 ns;
+
+ process
+
+ begin
+ ClkEn <= '1' ;
+ wait;
+ end process;
+
+ process
+
+ begin
+ Aclr <= '1' ;
+ wait for 100 ns;
+ Aclr <= '0' ;
+ wait;
+ end process;
+
+ process
+
+ begin
+ DataA <= (others => '0') ;
+ for i in 0 to 200 loop
+ wait until Clock'event and Clock = '1';
+ DataA <= DataA + '1' after 1 ns;
+ end loop;
+ wait;
+ end process;
+
+ process
+
+ begin
+ DataB <= (others => '0') ;
+ for i in 0 to 200 loop
+ wait until Clock'event and Clock = '1';
+ DataB <= DataB + '1' after 1 ns;
+ end loop;
+ wait;
+ end process;
+
+end architecture test;
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT my_sbuf\r
+ PORT(\r
+ CLK : IN std_logic;\r
+ RESET : IN std_logic;\r
+ CLK_EN : IN std_logic;\r
+ COMB_DATAREADY_IN : IN std_logic;\r
+ COMB_READ_IN : IN std_logic;\r
+ COMB_DATA_IN : IN std_logic_vector(18 downto 0);\r
+ SYN_READ_IN : IN std_logic; \r
+ COMB_NEXT_READ_OUT : OUT std_logic;\r
+ SYN_DATAREADY_OUT : OUT std_logic;\r
+ SYN_DATA_OUT : OUT std_logic_vector(18 downto 0);\r
+ DEBUG_OUT : OUT std_logic_vector(31 downto 0);\r
+ STAT_BUFFER : OUT std_logic\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL CLK : std_logic;\r
+ SIGNAL RESET : std_logic;\r
+ SIGNAL CLK_EN : std_logic;\r
+ SIGNAL COMB_DATAREADY_IN : std_logic;\r
+ SIGNAL COMB_NEXT_READ_OUT : std_logic;\r
+ SIGNAL COMB_READ_IN : std_logic;\r
+ SIGNAL COMB_DATA_IN : std_logic_vector(18 downto 0);\r
+ SIGNAL SYN_DATAREADY_OUT : std_logic;\r
+ SIGNAL SYN_DATA_OUT : std_logic_vector(18 downto 0);\r
+ SIGNAL SYN_READ_IN : std_logic;\r
+ SIGNAL DEBUG_OUT : std_logic_vector(31 downto 0);\r
+ SIGNAL STAT_BUFFER : std_logic;\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: my_sbuf PORT MAP(\r
+ CLK => CLK,\r
+ RESET => RESET,\r
+ CLK_EN => CLK_EN,\r
+ COMB_DATAREADY_IN => COMB_DATAREADY_IN,\r
+ COMB_NEXT_READ_OUT => COMB_NEXT_READ_OUT,\r
+ COMB_READ_IN => COMB_READ_IN,\r
+ COMB_DATA_IN => COMB_DATA_IN,\r
+ SYN_DATAREADY_OUT => SYN_DATAREADY_OUT,\r
+ SYN_DATA_OUT => SYN_DATA_OUT,\r
+ SYN_READ_IN => SYN_READ_IN,\r
+ DEBUG_OUT => DEBUG_OUT,\r
+ STAT_BUFFER => STAT_BUFFER\r
+ );\r
+\r
+THE_CLOCK_GEN: process\r
+begin\r
+ clk <= '1'; wait for 5.0 ns;\r
+ clk <= '0'; wait for 5.0 ns;\r
+end process THE_CLOCK_GEN;\r
+\r
+THE_TESTBENCH_PROC: process\r
+begin\r
+ -- Setup signals\r
+ reset <= '0';\r
+ clk_en <= '1';\r
+ comb_dataready_in <= '0';\r
+ comb_read_in <= '0';\r
+ comb_data_in <= b"000_0000_0000_0000_0000";\r
+ syn_read_in <= '0';\r
+ \r
+ -- Reset the whole stuff\r
+ wait until rising_edge(clk);\r
+ reset <= '1';\r
+ wait until rising_edge(clk);\r
+ wait until rising_edge(clk);\r
+ reset <= '0';\r
+ wait until rising_edge(clk);\r
+ \r
+ -- Tests may begin now\r
+ wait until rising_edge(clk);\r
+ comb_dataready_in <= '1';\r
+ comb_read_in <= '1';\r
+ comb_data_in <= b"100_0000_0000_0000_0000";\r
+ wait until rising_edge(clk);\r
+ comb_data_in <= b"100_0000_0000_0000_0001";\r
+ wait until rising_edge(clk);\r
+ comb_data_in <= b"100_0000_0000_0000_0010";\r
+ wait until rising_edge(clk);\r
+ comb_data_in <= b"100_0000_0000_0000_0011";\r
+ wait until rising_edge(clk);\r
+ comb_data_in <= b"100_0000_0000_0000_0100";\r
+ wait until rising_edge(clk);\r
+ comb_data_in <= b"100_0000_0000_0000_0101";\r
+ wait until rising_edge(clk);\r
+ comb_dataready_in <= '0';\r
+ comb_read_in <= '0';\r
+\r
+ wait until rising_edge(clk);\r
+ syn_read_in <= '1'; \r
+ wait until rising_edge(clk);\r
+ wait until rising_edge(clk);\r
+ syn_read_in <= '0';\r
+\r
+ -- Stay a while... stay FOREVER!!! MUHAHAHAHA!\r
+ wait;\r
+\r
+end process THE_TESTBENCH_PROC;\r
+\r
+END;\r
--- /dev/null
+LIBRARY ieee; \r
+USE ieee.std_logic_1164.ALL; \r
+USE ieee.numeric_std.ALL; \r
+\r
+library work;\r
+use work.trb_net_std.all;\r
+ \r
+ENTITY testbench IS \r
+END testbench; \r
+ \r
+ARCHITECTURE behavior OF testbench IS \r
+ \r
+ COMPONENT onewire_master \r
+ GENERIC(\r
+ CLK_PERIOD : integer := 10 --clk period in ns\r
+ );\r
+ PORT( \r
+ CLK : IN std_logic; \r
+ RESET : IN std_logic; \r
+ READOUT_ENABLE_IN : IN std_logic; \r
+ ONEWIRE : INOUT std_logic_vector(15 downto 0); \r
+ BP_ONEWIRE : INOUT std_logic; \r
+ BP_DATA_OUT : OUT std_logic_vector(15 downto 0); \r
+ DATA_OUT : OUT std_logic_vector(15 downto 0); \r
+ ADDR_OUT : OUT std_logic_vector(6 downto 0); \r
+ WRITE_OUT : OUT std_logic;\r
+ BUSY_OUT : OUT std_logic;\r
+ BSM_OUT : OUT std_logic_vector(7 downto 0); \r
+ STAT : OUT std_logic_vector(15 downto 0) \r
+ ); \r
+ END COMPONENT; \r
+ \r
+ SIGNAL CLK : std_logic;\r
+ SIGNAL RESET : std_logic;\r
+ SIGNAL READOUT_ENABLE_IN : std_logic;\r
+ SIGNAL ONEWIRE : std_logic_vector(15 downto 0);\r
+ SIGNAL BP_ONEWIRE : std_logic;\r
+ SIGNAL BP_DATA_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL DATA_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL ADDR_OUT : std_logic_vector(6 downto 0);\r
+ SIGNAL WRITE_OUT : std_logic;\r
+ SIGNAL BUSY_OUT : std_logic;\r
+ SIGNAL BSM_OUT : std_logic_vector(7 downto 0);\r
+ SIGNAL STAT : std_logic_vector(15 downto 0);\r
+ \r
+BEGIN \r
+ \r
+-- Please check and add your generic clause manually \r
+ uut: onewire_master \r
+ GENERIC MAP(\r
+ CLK_PERIOD => 10\r
+ )\r
+ PORT MAP( \r
+ CLK => CLK,\r
+ RESET => RESET,\r
+ READOUT_ENABLE_IN => READOUT_ENABLE_IN,\r
+ ONEWIRE => ONEWIRE,\r
+ BP_ONEWIRE => BP_ONEWIRE,\r
+ BP_DATA_OUT => BP_DATA_OUT,\r
+ DATA_OUT => DATA_OUT,\r
+ ADDR_OUT => ADDR_OUT,\r
+ WRITE_OUT => WRITE_OUT,\r
+ BUSY_OUT => BUSY_OUT,\r
+ BSM_OUT => BSM_OUT, \r
+ STAT => STAT \r
+ ); \r
+ \r
+THE_CLOCK_GEN: process\r
+begin\r
+ clk <= '1'; wait for 5 ns;\r
+ clk <= '0'; wait for 5 ns;\r
+end process THE_CLOCK_GEN;\r
+\r
+THE_TEST_BENCH: process\r
+begin\r
+ -- Setup signals\r
+ readout_enable_in <= '0';\r
+ reset <= '0';\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- Reset all\r
+ wait for 10 ns;\r
+ reset <= '1';\r
+ wait for 200 ns;\r
+ reset <= '0';\r
+ \r
+ -- Tests may start now\r
+ wait for 1 us;\r
+ wait until rising_edge(clk);\r
+ readout_enable_in <= '1';\r
+ wait until rising_edge(clk);\r
+ readout_enable_in <= '0';\r
+ wait until rising_edge(clk);\r
+\r
+ -- wait for reset pulse (READ_ID)\r
+ wait until falling_edge(onewire(0));\r
+ wait until rising_edge(onewire(0));\r
+ wait for 30 us;\r
+ onewire <= b"0000_0000_0000_0000";\r
+ bp_onewire <= '0';\r
+ wait for 120 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+\r
+ -- skip the command sequence\r
+ wait until falling_edge(onewire(0));\r
+ wait until falling_edge(onewire(0));\r
+ wait until falling_edge(onewire(0));\r
+ wait until falling_edge(onewire(0));\r
+ wait until falling_edge(onewire(0));\r
+ wait until falling_edge(onewire(0));\r
+ wait until falling_edge(onewire(0));\r
+ wait until falling_edge(onewire(0));\r
+\r
+ -- serial number\r
+ -- bit 0\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"fe80";\r
+ bp_onewire <= '0';\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 1\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"ef71";\r
+ bp_onewire <= '0';\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 2\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"d062";\r
+ bp_onewire <= '0';\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 3\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"c153";\r
+ bp_onewire <= '0';\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 4\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"b244";\r
+ bp_onewire <= '0';\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 5\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"a335";\r
+ bp_onewire <= '0';\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 6\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"9426";\r
+ bp_onewire <= '0';\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 7\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"8517";\r
+ bp_onewire <= '0';\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 8\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"7608";\r
+ bp_onewire <= '1';\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 9\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"67f9";\r
+ bp_onewire <= '1';\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 10\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"58ea";\r
+ bp_onewire <= '1';\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 11\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"49db";\r
+ bp_onewire <= '1';\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 12\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"3acc";\r
+ bp_onewire <= '0';\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 13\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"2bbd";\r
+ bp_onewire <= '0';\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 14\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"1cae";\r
+ bp_onewire <= '1';\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 15\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"0d9f";\r
+ bp_onewire <= '1';\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+\r
+ -- bit 16\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"dead";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 17\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"beef";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 18\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"affe";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 19\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"d00f";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 20\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"facc";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 21\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"0123";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 22\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"4567";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 23\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"89ab";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 24\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"cdef";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 25\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"aaaa";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 26\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"5555";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 27\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"6271";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 28\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"4711";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 29\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"0666";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 30\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"7550";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 31\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"bacc";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+\r
+ -- bit 32\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"0123";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 33\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"4567";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 34\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"89ab";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 35\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"cdef";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 36\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"0f1e";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 37\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"2d3c";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 38\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"4b5a";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 39\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"6978";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 40\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"8796";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 41\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"a5b4";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 42\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"c3d2";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 43\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"e1f0";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 44\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"fedc";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 45\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"ba98";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 46\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"7654";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 47\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"3210";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+\r
+ -- bit 48\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"fffe";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 49\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"fffd";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 50\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"fffb";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 51\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"fff7";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 52\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"ffef";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 53\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"ffdf";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 54\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"ffbf";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 55\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"ff7f";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 56\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"feff";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 57\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"fdff";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 58\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"fbff";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 59\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"f7ff";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 60\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"efff";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 61\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"dfff";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 62\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"bfff";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 63\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"7fff";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+\r
+ -- wait for reset pulse (CONV_TEMP)\r
+ wait until falling_edge(onewire(0));\r
+ wait until rising_edge(onewire(0));\r
+ wait for 30 us;\r
+ onewire <= b"0000_0000_0000_0000";\r
+ bp_onewire <= '0';\r
+ wait for 120 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+\r
+ -- skip the command sequence\r
+ wait until falling_edge(onewire(0));\r
+ wait until falling_edge(onewire(0));\r
+ wait until falling_edge(onewire(0));\r
+ wait until falling_edge(onewire(0));\r
+ wait until falling_edge(onewire(0));\r
+ wait until falling_edge(onewire(0));\r
+ wait until falling_edge(onewire(0));\r
+ wait until falling_edge(onewire(0));\r
+\r
+ wait until falling_edge(onewire(0));\r
+ wait until falling_edge(onewire(0));\r
+ wait until falling_edge(onewire(0));\r
+ wait until falling_edge(onewire(0));\r
+ wait until falling_edge(onewire(0));\r
+ wait until falling_edge(onewire(0));\r
+ wait until falling_edge(onewire(0));\r
+ wait until falling_edge(onewire(0));\r
+\r
+ -- wait for reset pulse (READ_TEMP)\r
+ wait until falling_edge(onewire(0));\r
+ wait until rising_edge(onewire(0));\r
+ wait for 30 us;\r
+ onewire <= b"0000_0000_0000_0000";\r
+ bp_onewire <= '0';\r
+ wait for 120 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+\r
+ -- skip the command sequence\r
+ wait until falling_edge(onewire(0));\r
+ wait until falling_edge(onewire(0));\r
+ wait until falling_edge(onewire(0));\r
+ wait until falling_edge(onewire(0));\r
+ wait until falling_edge(onewire(0));\r
+ wait until falling_edge(onewire(0));\r
+ wait until falling_edge(onewire(0));\r
+ wait until falling_edge(onewire(0));\r
+\r
+ wait until falling_edge(onewire(0));\r
+ wait until falling_edge(onewire(0));\r
+ wait until falling_edge(onewire(0));\r
+ wait until falling_edge(onewire(0));\r
+ wait until falling_edge(onewire(0));\r
+ wait until falling_edge(onewire(0));\r
+ wait until falling_edge(onewire(0));\r
+ wait until falling_edge(onewire(0));\r
+\r
+ -- temparature\r
+ -- bit 0\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"4001";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 1\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"5002";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 2\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"6004";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 3\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"7008";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 4\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"8010";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 5\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"9020";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 6\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"a040";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 7\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"b080";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 8\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"c100";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 9\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"d200";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 10\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"e400";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+ -- bit 11\r
+ wait until falling_edge(onewire(0));\r
+ onewire <= x"f800";\r
+ wait for 30 us;\r
+ onewire <= (others => 'H');\r
+ bp_onewire <= 'H';\r
+\r
+ -- Stay a while, stay forever.\r
+ wait;\r
+\r
+end process THE_TEST_BENCH; \r
+ \r
+ \r
+END;
\ No newline at end of file
--- /dev/null
+-- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23)
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity tb is
+end entity tb;
+
+
+architecture test of tb is
+
+ component onewire_spare_one
+ port (Address : in std_logic_vector(2 downto 0);
+ Q : out std_logic_vector(3 downto 0)
+ );
+ end component;
+
+ signal Address : std_logic_vector(2 downto 0) := (others => '0');
+ signal Q : std_logic_vector(3 downto 0);
+begin
+ u1 : onewire_spare_one
+ port map (Address => Address, Q => Q
+ );
+
+ process
+
+ begin
+ Address <= (others => '0') ;
+ wait for 100 ns;
+ wait for 10 ns;
+ for i in 0 to 11 loop
+ wait for 10 ns;
+ Address <= Address + '1' ;
+ end loop;
+ wait;
+ end process;
+
+end architecture test;
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT ped_corr_ctrl\r
+ PORT(\r
+ CLK_IN : IN std_logic;\r
+ RESET_IN : IN std_logic;\r
+ EDS_DATA_IN : IN std_logic_vector(39 downto 0);\r
+ EDS_AVAIL_IN : IN std_logic;\r
+ EVT_TYPE_IN : IN std_logic_vector(2 downto 0);\r
+ BUF_TICK_IN : IN std_logic_vector(15 downto 0);\r
+ BUF_START_IN : IN std_logic_vector(15 downto 0);\r
+ BUF_0_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ BUF_1_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ BUF_2_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ BUF_3_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ BUF_4_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ BUF_5_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ BUF_6_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ BUF_7_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ BUF_8_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ BUF_9_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ BUF_10_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ BUF_11_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ BUF_12_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ BUF_13_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ BUF_14_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ BUF_15_DATA_IN : IN std_logic_vector(37 downto 0);\r
+ PED_0_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ PED_1_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ PED_2_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ PED_3_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ PED_4_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ PED_5_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ PED_6_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ PED_7_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ PED_8_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ PED_9_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ PED_10_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ PED_11_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ PED_12_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ PED_13_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ PED_14_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ PED_15_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_0_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_1_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_2_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_3_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_4_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_5_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_6_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_7_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_8_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_9_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_10_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_11_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_12_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_13_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_14_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ THR_15_DATA_IN : IN std_logic_vector(17 downto 0);\r
+ EDS_DONE_OUT : OUT std_logic;\r
+ DHDR_DATA_OUT : OUT std_logic_vector(31 downto 0);\r
+ DHDR_LENGTH_OUT : OUT std_logic_vector(15 downto 0);\r
+ DHDR_STORE_OUT : OUT std_logic;\r
+ PED_ADDR_OUT : OUT std_logic_vector(6 downto 0);\r
+ THR_ADDR_OUT : OUT std_logic_vector(6 downto 0);\r
+ BUF_ADDR_OUT : OUT std_logic_vector(6 downto 0);\r
+ BUF_DONE_OUT : OUT std_logic;\r
+ FIFO_START_OUT : OUT std_logic;\r
+ FIFO_0_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_1_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_2_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_3_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_4_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_5_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_6_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_7_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_8_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_9_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_10_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_11_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_12_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_13_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_14_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_15_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ FIFO_WE_OUT : OUT std_logic_vector(15 downto 0);\r
+ FIFO_DONE_OUT : OUT std_logic;\r
+ DBG_BSM_OUT : OUT std_logic_vector(7 downto 0);\r
+ DBG_OUT : OUT std_logic_vector(15 downto 0)\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL CLK_IN : std_logic;\r
+ SIGNAL RESET_IN : std_logic;\r
+ SIGNAL EDS_DATA_IN : std_logic_vector(39 downto 0);\r
+ SIGNAL EDS_AVAIL_IN : std_logic;\r
+ SIGNAL EDS_DONE_OUT : std_logic;\r
+ SIGNAL DHDR_DATA_OUT : std_logic_vector(31 downto 0);\r
+ SIGNAL DHDR_LENGTH_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL DHDR_STORE_OUT : std_logic;\r
+ SIGNAL EVT_TYPE_IN : std_logic_vector(2 downto 0);\r
+ SIGNAL BUF_ADDR_OUT : std_logic_vector(6 downto 0);\r
+ SIGNAL BUF_DONE_OUT : std_logic;\r
+ SIGNAL BUF_TICK_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL BUF_START_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL BUF_0_DATA_IN : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_1_DATA_IN : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_2_DATA_IN : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_3_DATA_IN : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_4_DATA_IN : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_5_DATA_IN : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_6_DATA_IN : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_7_DATA_IN : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_8_DATA_IN : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_9_DATA_IN : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_10_DATA_IN : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_11_DATA_IN : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_12_DATA_IN : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_13_DATA_IN : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_14_DATA_IN : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_15_DATA_IN : std_logic_vector(37 downto 0);\r
+ SIGNAL THR_ADDR_OUT : std_logic_vector(6 downto 0);\r
+ SIGNAL THR_0_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL THR_1_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL THR_2_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL THR_3_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL THR_4_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL THR_5_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL THR_6_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL THR_7_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL THR_8_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL THR_9_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL THR_10_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL THR_11_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL THR_12_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL THR_13_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL THR_14_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL THR_15_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL PED_ADDR_OUT : std_logic_vector(6 downto 0);\r
+ SIGNAL PED_0_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL PED_1_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL PED_2_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL PED_3_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL PED_4_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL PED_5_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL PED_6_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL PED_7_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL PED_8_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL PED_9_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL PED_10_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL PED_11_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL PED_12_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL PED_13_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL PED_14_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL PED_15_DATA_IN : std_logic_vector(17 downto 0);\r
+ SIGNAL FIFO_START_OUT : std_logic;\r
+ SIGNAL FIFO_0_DATA_OUT : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_1_DATA_OUT : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_2_DATA_OUT : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_3_DATA_OUT : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_4_DATA_OUT : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_5_DATA_OUT : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_6_DATA_OUT : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_7_DATA_OUT : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_8_DATA_OUT : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_9_DATA_OUT : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_10_DATA_OUT : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_11_DATA_OUT : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_12_DATA_OUT : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_13_DATA_OUT : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_14_DATA_OUT : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_15_DATA_OUT : std_logic_vector(39 downto 0);\r
+ SIGNAL FIFO_WE_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL FIFO_DONE_OUT : std_logic;\r
+ SIGNAL DBG_BSM_OUT : std_logic_vector(7 downto 0);\r
+ SIGNAL DBG_OUT : std_logic_vector(15 downto 0);\r
+\r
+\r
+ SIGNAL BUF_ADDR : std_logic_vector(6 downto 0);\r
+ SIGNAL PED_ADDR : std_logic_vector(6 downto 0);\r
+ SIGNAL THR_ADDR : std_logic_vector(6 downto 0);\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: ped_corr_ctrl PORT MAP(\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ EDS_DATA_IN => EDS_DATA_IN,\r
+ EDS_AVAIL_IN => EDS_AVAIL_IN,\r
+ EDS_DONE_OUT => EDS_DONE_OUT,\r
+ DHDR_DATA_OUT => DHDR_DATA_OUT,\r
+ DHDR_LENGTH_OUT => DHDR_LENGTH_OUT,\r
+ DHDR_STORE_OUT => DHDR_STORE_OUT,\r
+ EVT_TYPE_IN => EVT_TYPE_IN,\r
+ BUF_ADDR_OUT => BUF_ADDR_OUT,\r
+ BUF_DONE_OUT => BUF_DONE_OUT,\r
+ BUF_TICK_IN => BUF_TICK_IN,\r
+ BUF_START_IN => BUF_START_IN,\r
+ BUF_0_DATA_IN => BUF_0_DATA_IN,\r
+ BUF_1_DATA_IN => BUF_1_DATA_IN,\r
+ BUF_2_DATA_IN => BUF_2_DATA_IN,\r
+ BUF_3_DATA_IN => BUF_3_DATA_IN,\r
+ BUF_4_DATA_IN => BUF_4_DATA_IN,\r
+ BUF_5_DATA_IN => BUF_5_DATA_IN,\r
+ BUF_6_DATA_IN => BUF_6_DATA_IN,\r
+ BUF_7_DATA_IN => BUF_7_DATA_IN,\r
+ BUF_8_DATA_IN => BUF_8_DATA_IN,\r
+ BUF_9_DATA_IN => BUF_9_DATA_IN,\r
+ BUF_10_DATA_IN => BUF_10_DATA_IN,\r
+ BUF_11_DATA_IN => BUF_11_DATA_IN,\r
+ BUF_12_DATA_IN => BUF_12_DATA_IN,\r
+ BUF_13_DATA_IN => BUF_13_DATA_IN,\r
+ BUF_14_DATA_IN => BUF_14_DATA_IN,\r
+ BUF_15_DATA_IN => BUF_15_DATA_IN,\r
+ PED_ADDR_OUT => PED_ADDR_OUT,\r
+ PED_0_DATA_IN => PED_0_DATA_IN,\r
+ PED_1_DATA_IN => PED_1_DATA_IN,\r
+ PED_2_DATA_IN => PED_2_DATA_IN,\r
+ PED_3_DATA_IN => PED_3_DATA_IN,\r
+ PED_4_DATA_IN => PED_4_DATA_IN,\r
+ PED_5_DATA_IN => PED_5_DATA_IN,\r
+ PED_6_DATA_IN => PED_6_DATA_IN,\r
+ PED_7_DATA_IN => PED_7_DATA_IN,\r
+ PED_8_DATA_IN => PED_8_DATA_IN,\r
+ PED_9_DATA_IN => PED_9_DATA_IN,\r
+ PED_10_DATA_IN => PED_10_DATA_IN,\r
+ PED_11_DATA_IN => PED_11_DATA_IN,\r
+ PED_12_DATA_IN => PED_12_DATA_IN,\r
+ PED_13_DATA_IN => PED_13_DATA_IN,\r
+ PED_14_DATA_IN => PED_14_DATA_IN,\r
+ PED_15_DATA_IN => PED_15_DATA_IN,\r
+ THR_ADDR_OUT => THR_ADDR_OUT,\r
+ THR_0_DATA_IN => THR_0_DATA_IN,\r
+ THR_1_DATA_IN => THR_1_DATA_IN,\r
+ THR_2_DATA_IN => THR_2_DATA_IN,\r
+ THR_3_DATA_IN => THR_3_DATA_IN,\r
+ THR_4_DATA_IN => THR_4_DATA_IN,\r
+ THR_5_DATA_IN => THR_5_DATA_IN,\r
+ THR_6_DATA_IN => THR_6_DATA_IN,\r
+ THR_7_DATA_IN => THR_7_DATA_IN,\r
+ THR_8_DATA_IN => THR_8_DATA_IN,\r
+ THR_9_DATA_IN => THR_9_DATA_IN,\r
+ THR_10_DATA_IN => THR_10_DATA_IN,\r
+ THR_11_DATA_IN => THR_11_DATA_IN,\r
+ THR_12_DATA_IN => THR_12_DATA_IN,\r
+ THR_13_DATA_IN => THR_13_DATA_IN,\r
+ THR_14_DATA_IN => THR_14_DATA_IN,\r
+ THR_15_DATA_IN => THR_15_DATA_IN,\r
+ FIFO_START_OUT => FIFO_START_OUT,\r
+ FIFO_0_DATA_OUT => FIFO_0_DATA_OUT,\r
+ FIFO_1_DATA_OUT => FIFO_1_DATA_OUT,\r
+ FIFO_2_DATA_OUT => FIFO_2_DATA_OUT,\r
+ FIFO_3_DATA_OUT => FIFO_3_DATA_OUT,\r
+ FIFO_4_DATA_OUT => FIFO_4_DATA_OUT,\r
+ FIFO_5_DATA_OUT => FIFO_5_DATA_OUT,\r
+ FIFO_6_DATA_OUT => FIFO_6_DATA_OUT,\r
+ FIFO_7_DATA_OUT => FIFO_7_DATA_OUT,\r
+ FIFO_8_DATA_OUT => FIFO_8_DATA_OUT,\r
+ FIFO_9_DATA_OUT => FIFO_9_DATA_OUT,\r
+ FIFO_10_DATA_OUT => FIFO_10_DATA_OUT,\r
+ FIFO_11_DATA_OUT => FIFO_11_DATA_OUT,\r
+ FIFO_12_DATA_OUT => FIFO_12_DATA_OUT,\r
+ FIFO_13_DATA_OUT => FIFO_13_DATA_OUT,\r
+ FIFO_14_DATA_OUT => FIFO_14_DATA_OUT,\r
+ FIFO_15_DATA_OUT => FIFO_15_DATA_OUT,\r
+ FIFO_WE_OUT => FIFO_WE_OUT,\r
+ FIFO_DONE_OUT => FIFO_DONE_OUT,\r
+ DBG_BSM_OUT => DBG_BSM_OUT,\r
+ DBG_OUT => DBG_OUT\r
+ );\r
+\r
+THE_CLOCK_GEN: process\r
+begin\r
+ clk_in <= '1'; wait for 5 ns;\r
+ clk_in <= '0'; wait for 5 ns;\r
+end process THE_CLOCK_GEN;\r
+\r
+-- Delay the BUF and PED address reaction\r
+THE_ADDR_DELAY: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ buf_addr <= buf_addr_out;\r
+ thr_addr <= thr_addr_out;\r
+ ped_addr <= ped_addr_out;\r
+ end if;\r
+end process THE_ADDR_DELAY;\r
+\r
+\r
+-- The real testbench\r
+TESTBENCH: process\r
+begin\r
+ -- Setup signal\r
+ reset_in <= '0';\r
+ eds_data_in <= (others => '0'); \r
+ eds_avail_in <= '0';\r
+ evt_type_in <= "000";\r
+ buf_start_in <= (others => '0'); \r
+ buf_tick_in <= (others => '0');\r
+ -- Buffer level information: 7 -> good, 6 -> broken, 5 -> ignore, rest LEVEL\r
+ buf_0_data_in(37 downto 30) <= x"80"; -- good\r
+ buf_1_data_in(37 downto 30) <= x"20"; -- ignore\r
+ buf_2_data_in(37 downto 30) <= x"20"; -- ignore\r
+ buf_3_data_in(37 downto 30) <= x"20"; -- ignore\r
+ buf_4_data_in(37 downto 30) <= x"40"; -- broken!!!\r
+ buf_5_data_in(37 downto 30) <= x"20"; -- ignore\r
+ buf_6_data_in(37 downto 30) <= x"20"; -- ignore\r
+ buf_7_data_in(37 downto 30) <= x"20"; -- ignore\r
+ buf_8_data_in(37 downto 30) <= x"20"; -- ignore\r
+ buf_9_data_in(37 downto 30) <= x"20"; -- ignore\r
+ buf_10_data_in(37 downto 30) <= x"20"; -- ignore\r
+ buf_11_data_in(37 downto 30) <= x"20"; -- ignore\r
+ buf_12_data_in(37 downto 30) <= x"20"; -- ignore\r
+ buf_13_data_in(37 downto 30) <= x"20"; -- ignore\r
+ buf_14_data_in(37 downto 30) <= x"20"; -- ignore\r
+ buf_15_data_in(37 downto 30) <= x"20"; -- ignore\r
+ -- Buffer frame information: 8 -> APV error, [7:0] row\r
+ buf_0_data_in(29 downto 18) <= x"011"; -- row 0x11, no error\r
+ buf_1_data_in(29 downto 18) <= x"0ee"; --\r
+ buf_2_data_in(29 downto 18) <= x"0ee"; --\r
+ buf_3_data_in(29 downto 18) <= x"0ee"; --\r
+ buf_4_data_in(29 downto 18) <= x"0aa"; --\r
+ buf_5_data_in(29 downto 18) <= x"0ee"; --\r
+ buf_6_data_in(29 downto 18) <= x"0ee"; --\r
+ buf_7_data_in(29 downto 18) <= x"0ee"; --\r
+ buf_8_data_in(29 downto 18) <= x"0ee"; --\r
+ buf_9_data_in(29 downto 18) <= x"0ee"; --\r
+ buf_10_data_in(29 downto 18) <= x"0ee"; --\r
+ buf_11_data_in(29 downto 18) <= x"0ee"; --\r
+ buf_12_data_in(29 downto 18) <= x"0ee"; --\r
+ buf_13_data_in(29 downto 18) <= x"0ee"; --\r
+ buf_14_data_in(29 downto 18) <= x"0ee"; --\r
+ buf_15_data_in(29 downto 18) <= x"0ee"; --\r
+ -- Buffer data\r
+ buf_0_data_in(17 downto 14) <= x"0";\r
+ buf_1_data_in(17 downto 14) <= x"0"; buf_1_data_in(13 downto 0) <= "00000000000000";\r
+ buf_2_data_in(17 downto 14) <= x"0"; buf_2_data_in(13 downto 0) <= "00000000000000";\r
+ buf_3_data_in(17 downto 14) <= x"0"; buf_3_data_in(13 downto 0) <= "00000000000000";\r
+ buf_4_data_in(17 downto 14) <= x"0"; buf_4_data_in(13 downto 0) <= "00000000000000";\r
+ buf_5_data_in(17 downto 14) <= x"0"; buf_5_data_in(13 downto 0) <= "00000000000000";\r
+ buf_6_data_in(17 downto 14) <= x"0"; buf_6_data_in(13 downto 0) <= "00000000000000";\r
+ buf_7_data_in(17 downto 14) <= x"0"; buf_7_data_in(13 downto 0) <= "00000000000000";\r
+ buf_8_data_in(17 downto 14) <= x"0"; buf_8_data_in(13 downto 0) <= "00000000000000";\r
+ buf_9_data_in(17 downto 14) <= x"0"; buf_9_data_in(13 downto 0) <= "00000000000000";\r
+ buf_10_data_in(17 downto 14) <= x"0"; buf_10_data_in(13 downto 0) <= "00000000000000";\r
+ buf_11_data_in(17 downto 14) <= x"0"; buf_11_data_in(13 downto 0) <= "00000000000000";\r
+ buf_12_data_in(17 downto 14) <= x"0"; buf_12_data_in(13 downto 0) <= "00000000000000";\r
+ buf_13_data_in(17 downto 14) <= x"0"; buf_13_data_in(13 downto 0) <= "00000000000000";\r
+ buf_14_data_in(17 downto 14) <= x"0"; buf_14_data_in(13 downto 0) <= "00000000000000";\r
+ buf_15_data_in(17 downto 14) <= x"0"; buf_15_data_in(13 downto 0) <= "00000000000000";\r
+ -- Pedestal data\r
+-- ped_0_data_in <= "00" & x"0000";\r
+ ped_1_data_in <= "00" & x"0000";\r
+ ped_2_data_in <= "00" & x"0000";\r
+ ped_3_data_in <= "00" & x"0000";\r
+ ped_4_data_in <= "00" & x"0000";\r
+ ped_5_data_in <= "00" & x"0000";\r
+ ped_6_data_in <= "00" & x"0000";\r
+ ped_7_data_in <= "00" & x"0000";\r
+ ped_8_data_in <= "00" & x"0000";\r
+ ped_9_data_in <= "00" & x"0000";\r
+ ped_10_data_in <= "00" & x"0000";\r
+ ped_11_data_in <= "00" & x"0000";\r
+ ped_12_data_in <= "00" & x"0000";\r
+ ped_13_data_in <= "00" & x"0000";\r
+ ped_14_data_in <= "00" & x"0000";\r
+ ped_15_data_in <= "00" & x"0000";\r
+ -- Threshold data\r
+-- thr_0_data_in <= "00" & x"0000";\r
+ thr_1_data_in <= "00" & x"0000";\r
+ thr_2_data_in <= "00" & x"0000";\r
+ thr_3_data_in <= "00" & x"0000";\r
+ thr_4_data_in <= "00" & x"0000";\r
+ thr_5_data_in <= "00" & x"0000";\r
+ thr_6_data_in <= "00" & x"0000";\r
+ thr_7_data_in <= "00" & x"0000";\r
+ thr_8_data_in <= "00" & x"0000";\r
+ thr_9_data_in <= "00" & x"0000";\r
+ thr_10_data_in <= "00" & x"0000";\r
+ thr_11_data_in <= "00" & x"0000";\r
+ thr_12_data_in <= "00" & x"0000";\r
+ thr_13_data_in <= "00" & x"0000";\r
+ thr_14_data_in <= "00" & x"0000";\r
+ thr_15_data_in <= "00" & x"0000";\r
+\r
+ -- Reset\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+\r
+ ----------------------------------------------------------------------------------------\r
+ ----------------------------------------------------------------------------------------\r
+ ----------------------------------------------------------------------------------------\r
+ ----------------------------------------------------------------------------------------\r
+\r
+ ----------------------------------------------------------------\r
+ -- "000" -> RAW128\r
+ ----------------------------------------------------------------\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ evt_type_in <= "000";\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait for 55 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- EDS comes in\r
+ eds_data_in <= x"01abcdee01";\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '0'; \r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- Buffer 0 becomes ready\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ buf_0_data_in(37 downto 30) <= x"81"; \r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ buf_0_data_in(37 downto 30) <= x"82"; \r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ buf_0_data_in(37 downto 30) <= x"83"; \r
+ \r
+ -- wait for first buffer \r
+ wait until rising_edge(buf_done_out);\r
+ wait for 300 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+\r
+ ----------------------------------------------------------------\r
+ -- "001" -> PED128\r
+ ----------------------------------------------------------------\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ evt_type_in <= "001";\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait for 55 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- EDS comes in\r
+ eds_data_in <= x"01abcdee11";\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '0'; \r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- Buffer 0 becomes ready\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ buf_0_data_in(37 downto 30) <= x"81"; \r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ buf_0_data_in(37 downto 30) <= x"82"; \r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ buf_0_data_in(37 downto 30) <= x"83"; \r
+ \r
+ -- wait for first buffer \r
+ wait until rising_edge(buf_done_out);\r
+ wait for 300 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ ----------------------------------------------------------------\r
+ -- "010" -> PED128THR\r
+ ----------------------------------------------------------------\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ evt_type_in <= "010";\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait for 55 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- EDS comes in\r
+ eds_data_in <= x"01abcdee21";\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '0'; \r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- Buffer 0 becomes ready\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ buf_0_data_in(37 downto 30) <= x"81"; \r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ buf_0_data_in(37 downto 30) <= x"82"; \r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ buf_0_data_in(37 downto 30) <= x"83"; \r
+ \r
+ -- wait for first buffer \r
+ wait until rising_edge(buf_done_out);\r
+ wait for 300 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ ----------------------------------------------------------------------------------------\r
+ ----------------------------------------------------------------------------------------\r
+ ----------------------------------------------------------------------------------------\r
+ ----------------------------------------------------------------------------------------\r
+ wait; \r
+\r
+ -- Tests may start now\r
+ ----------------------------------------------------------------\r
+ -- "000" -> RAW128\r
+ ----------------------------------------------------------------\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ evt_type_in <= "000";\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait for 55 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- EDS comes in\r
+ eds_data_in <= x"01abcdee01";\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '0'; \r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- Buffer 0 becomes ready\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ buf_0_data_in(37 downto 30) <= x"81"; \r
+ \r
+ -- wait for first buffer \r
+ wait until rising_edge(buf_done_out);\r
+ wait for 300 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ ----------------------------------------------------------------\r
+ -- "001" -> PED128\r
+ ----------------------------------------------------------------\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ evt_type_in <= "001";\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait for 55 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- EDS comes in\r
+ eds_data_in <= x"01abcdee01";\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '0'; \r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- Buffer 0 becomes ready\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ buf_0_data_in(37 downto 30) <= x"81"; \r
+ \r
+ -- wait for first buffer \r
+ wait until rising_edge(buf_done_out);\r
+ wait for 300 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ ----------------------------------------------------------------\r
+ -- "010" -> PED128THR\r
+ ----------------------------------------------------------------\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ evt_type_in <= "010";\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait for 55 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- EDS comes in\r
+ eds_data_in <= x"01abcdee01";\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '0'; \r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- Buffer 0 becomes ready\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ buf_0_data_in(37 downto 30) <= x"81"; \r
+ \r
+ -- wait for first buffer \r
+ wait until rising_edge(buf_done_out);\r
+ wait for 300 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ ----------------------------------------------------------------\r
+ -- "100" -> NC64PED64\r
+ ----------------------------------------------------------------\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ evt_type_in <= "100";\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait for 55 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- EDS comes in\r
+ eds_data_in <= x"01abcdee01";\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '0'; \r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- Buffer 0 becomes ready\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ buf_0_data_in(37 downto 30) <= x"81"; \r
+ \r
+ -- wait for first buffer \r
+ wait until rising_edge(buf_done_out);\r
+ wait for 300 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ ----------------------------------------------------------------\r
+ -- "101" -> NC64\r
+ ----------------------------------------------------------------\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ evt_type_in <= "101";\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait for 55 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- EDS comes in\r
+ eds_data_in <= x"01abcdee01";\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '0'; \r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- Buffer 0 becomes ready\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ buf_0_data_in(37 downto 30) <= x"81"; \r
+ \r
+ -- wait for first buffer \r
+ wait until rising_edge(buf_done_out);\r
+ wait for 300 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ ----------------------------------------------------------------\r
+ -- "110" -> NC64GOOD\r
+ ----------------------------------------------------------------\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ evt_type_in <= "110";\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait for 55 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- EDS comes in\r
+ eds_data_in <= x"01abcdee01";\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '0'; \r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- Buffer 0 becomes ready\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ buf_0_data_in(37 downto 30) <= x"81"; \r
+ \r
+ -- wait for first buffer \r
+ wait until rising_edge(buf_done_out);\r
+ wait for 300 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ ----------------------------------------------------------------\r
+ -- "111" -> NC64THR\r
+ ----------------------------------------------------------------\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ evt_type_in <= "111";\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait for 55 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- EDS comes in\r
+ eds_data_in <= x"01abcdee01";\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ eds_avail_in <= '0'; \r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- Buffer 0 becomes ready\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ buf_0_data_in(37 downto 30) <= x"81"; \r
+ \r
+ -- wait for first buffer \r
+ wait until rising_edge(buf_done_out);\r
+ wait for 300 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+\r
+\r
+\r
+\r
+ \r
+ -- stay a while, stay forever!\r
+ wait; \r
+end process TESTBENCH; \r
+\r
+-- Data faker for "APV 0"...\r
+BUF_0_DATA_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ case buf_addr is\r
+ when "0000000" => buf_0_data_in(13 downto 0) <= "00" & x"44b";\r
+ when "0000001" => buf_0_data_in(13 downto 0) <= "00" & x"474"; \r
+ when "0000010" => buf_0_data_in(13 downto 0) <= "00" & x"462"; \r
+ when "0000011" => buf_0_data_in(13 downto 0) <= "00" & x"45f"; \r
+-- when "0000100" => buf_0_data_in(13 downto 0) <= "00" & x"44c";\r
+ when "0000100" => buf_0_data_in(13 downto 0) <= "01" & x"111"; -- physical UNDERFLOW\r
+ when "0000101" => buf_0_data_in(13 downto 0) <= "00" & x"457"; \r
+ when "0000110" => buf_0_data_in(13 downto 0) <= "00" & x"476"; \r
+ when "0000111" => buf_0_data_in(13 downto 0) <= "00" & x"456"; \r
+ when "0001000" => buf_0_data_in(13 downto 0) <= "00" & x"450"; \r
+ when "0001001" => buf_0_data_in(13 downto 0) <= "00" & x"45c"; \r
+-- when "0001010" => buf_0_data_in(13 downto 0) <= "00" & x"46b"; \r
+ when "0001010" => buf_0_data_in(13 downto 0) <= "10" & x"eee"; -- physical OVERFLOW\r
+ when "0001011" => buf_0_data_in(13 downto 0) <= "00" & x"461"; \r
+ when "0001100" => buf_0_data_in(13 downto 0) <= "00" & x"466"; \r
+ when "0001101" => buf_0_data_in(13 downto 0) <= "00" & x"449"; \r
+ when "0001110" => buf_0_data_in(13 downto 0) <= "00" & x"450"; \r
+ when "0001111" => buf_0_data_in(13 downto 0) <= "00" & x"451"; \r
+ when "0010000" => buf_0_data_in(13 downto 0) <= "00" & x"432"; \r
+-- when "0010001" => buf_0_data_in(13 downto 0) <= "00" & x"459"; \r
+ when "0010001" => buf_0_data_in(13 downto 0) <= "01" & x"111"; -- correction UNDERFLOW \r
+ when "0010010" => buf_0_data_in(13 downto 0) <= "00" & x"45c"; \r
+ when "0010011" => buf_0_data_in(13 downto 0) <= "00" & x"430"; \r
+ when "0010100" => buf_0_data_in(13 downto 0) <= "00" & x"42f"; \r
+ when "0010101" => buf_0_data_in(13 downto 0) <= "00" & x"452"; \r
+ when "0010110" => buf_0_data_in(13 downto 0) <= "00" & x"43a"; \r
+-- when "0010111" => buf_0_data_in(13 downto 0) <= "00" & x"431"; \r
+ when "0010111" => buf_0_data_in(13 downto 0) <= "10" & x"eee"; -- correction OVERFLOW\r
+ when "0011000" => buf_0_data_in(13 downto 0) <= "00" & x"42b"; \r
+ when "0011001" => buf_0_data_in(13 downto 0) <= "00" & x"443"; \r
+ when "0011010" => buf_0_data_in(13 downto 0) <= "00" & x"424"; \r
+ when "0011011" => buf_0_data_in(13 downto 0) <= "00" & x"436"; \r
+ when "0011100" => buf_0_data_in(13 downto 0) <= "00" & x"45e"; \r
+ when "0011101" => buf_0_data_in(13 downto 0) <= "00" & x"453"; \r
+ when "0011110" => buf_0_data_in(13 downto 0) <= "00" & x"44c"; \r
+ when "0011111" => buf_0_data_in(13 downto 0) <= "00" & x"449"; \r
+ when "0100000" => buf_0_data_in(13 downto 0) <= "00" & x"40a"; \r
+ when "0100001" => buf_0_data_in(13 downto 0) <= "00" & x"43f"; \r
+-- when "0100010" => buf_0_data_in(13 downto 0) <= "00" & x"411"; \r
+ when "0100010" => buf_0_data_in(13 downto 0) <= "00" & x"411"; -- physical OFF \r
+ when "0100011" => buf_0_data_in(13 downto 0) <= "00" & x"455"; \r
+ when "0100100" => buf_0_data_in(13 downto 0) <= "00" & x"44b"; \r
+ when "0100101" => buf_0_data_in(13 downto 0) <= "00" & x"431"; \r
+ when "0100110" => buf_0_data_in(13 downto 0) <= "00" & x"425"; \r
+ when "0100111" => buf_0_data_in(13 downto 0) <= "00" & x"44a"; \r
+ when "0101000" => buf_0_data_in(13 downto 0) <= "00" & x"442"; \r
+ when "0101001" => buf_0_data_in(13 downto 0) <= "00" & x"446"; \r
+ when "0101010" => buf_0_data_in(13 downto 0) <= "00" & x"43e"; \r
+ when "0101011" => buf_0_data_in(13 downto 0) <= "00" & x"441"; \r
+ when "0101100" => buf_0_data_in(13 downto 0) <= "00" & x"45b"; \r
+ when "0101101" => buf_0_data_in(13 downto 0) <= "00" & x"44e"; \r
+ when "0101110" => buf_0_data_in(13 downto 0) <= "00" & x"452"; \r
+-- when "0101111" => buf_0_data_in(13 downto 0) <= "00" & x"469"; \r
+ when "0101111" => buf_0_data_in(13 downto 0) <= "00" & x"469"; -- correction OFF\r
+ when "0110000" => buf_0_data_in(13 downto 0) <= "00" & x"456"; \r
+ when "0110001" => buf_0_data_in(13 downto 0) <= "00" & x"45b"; \r
+ when "0110010" => buf_0_data_in(13 downto 0) <= "00" & x"482"; \r
+ when "0110011" => buf_0_data_in(13 downto 0) <= "00" & x"461"; \r
+ when "0110100" => buf_0_data_in(13 downto 0) <= "00" & x"444"; \r
+ when "0110101" => buf_0_data_in(13 downto 0) <= "00" & x"458"; \r
+ when "0110110" => buf_0_data_in(13 downto 0) <= "00" & x"446"; \r
+ when "0110111" => buf_0_data_in(13 downto 0) <= "00" & x"475"; \r
+ when "0111000" => buf_0_data_in(13 downto 0) <= "00" & x"447"; \r
+ when "0111001" => buf_0_data_in(13 downto 0) <= "00" & x"44f"; \r
+ when "0111010" => buf_0_data_in(13 downto 0) <= "00" & x"433"; \r
+ when "0111011" => buf_0_data_in(13 downto 0) <= "00" & x"470"; \r
+ when "0111100" => buf_0_data_in(13 downto 0) <= "00" & x"46d"; \r
+ when "0111101" => buf_0_data_in(13 downto 0) <= "00" & x"45e"; \r
+ when "0111110" => buf_0_data_in(13 downto 0) <= "00" & x"439"; \r
+ when "0111111" => buf_0_data_in(13 downto 0) <= "00" & x"45a"; \r
+ when "1000000" => buf_0_data_in(13 downto 0) <= "00" & x"43b"; \r
+ when "1000001" => buf_0_data_in(13 downto 0) <= "00" & x"42a"; \r
+ when "1000010" => buf_0_data_in(13 downto 0) <= "00" & x"430"; \r
+ when "1000011" => buf_0_data_in(13 downto 0) <= "00" & x"444"; \r
+ when "1000100" => buf_0_data_in(13 downto 0) <= "00" & x"42b"; \r
+ when "1000101" => buf_0_data_in(13 downto 0) <= "00" & x"42b"; \r
+ when "1000110" => buf_0_data_in(13 downto 0) <= "00" & x"403"; \r
+ when "1000111" => buf_0_data_in(13 downto 0) <= "00" & x"429"; \r
+ when "1001000" => buf_0_data_in(13 downto 0) <= "00" & x"3f4"; \r
+ when "1001001" => buf_0_data_in(13 downto 0) <= "00" & x"41b"; \r
+ when "1001010" => buf_0_data_in(13 downto 0) <= "00" & x"42f"; \r
+ when "1001011" => buf_0_data_in(13 downto 0) <= "00" & x"434"; \r
+ when "1001100" => buf_0_data_in(13 downto 0) <= "00" & x"40a"; \r
+ when "1001101" => buf_0_data_in(13 downto 0) <= "00" & x"416"; \r
+ when "1001110" => buf_0_data_in(13 downto 0) <= "00" & x"412"; \r
+ when "1001111" => buf_0_data_in(13 downto 0) <= "00" & x"418"; \r
+ when "1010000" => buf_0_data_in(13 downto 0) <= "00" & x"411"; \r
+ when "1010001" => buf_0_data_in(13 downto 0) <= "00" & x"40e"; \r
+ when "1010010" => buf_0_data_in(13 downto 0) <= "00" & x"4d6"; \r
+ when "1010011" => buf_0_data_in(13 downto 0) <= "00" & x"40d"; \r
+ when "1010100" => buf_0_data_in(13 downto 0) <= "00" & x"3ec"; \r
+ when "1010101" => buf_0_data_in(13 downto 0) <= "00" & x"40e"; \r
+ when "1010110" => buf_0_data_in(13 downto 0) <= "00" & x"419"; \r
+ when "1010111" => buf_0_data_in(13 downto 0) <= "00" & x"40d"; \r
+ when "1011000" => buf_0_data_in(13 downto 0) <= "00" & x"3f1"; \r
+ when "1011001" => buf_0_data_in(13 downto 0) <= "00" & x"3fa"; \r
+ when "1011010" => buf_0_data_in(13 downto 0) <= "00" & x"40e"; \r
+ when "1011011" => buf_0_data_in(13 downto 0) <= "00" & x"408"; \r
+ when "1011100" => buf_0_data_in(13 downto 0) <= "00" & x"3ee"; \r
+ when "1011101" => buf_0_data_in(13 downto 0) <= "00" & x"3fd"; \r
+ when "1011110" => buf_0_data_in(13 downto 0) <= "00" & x"41b"; \r
+ when "1011111" => buf_0_data_in(13 downto 0) <= "00" & x"3f3"; \r
+ when "1100000" => buf_0_data_in(13 downto 0) <= "00" & x"3b2"; \r
+ when "1100001" => buf_0_data_in(13 downto 0) <= "00" & x"3d6"; \r
+ when "1100010" => buf_0_data_in(13 downto 0) <= "00" & x"3f2"; \r
+ when "1100011" => buf_0_data_in(13 downto 0) <= "00" & x"3f2"; \r
+ when "1100100" => buf_0_data_in(13 downto 0) <= "00" & x"40d"; \r
+ when "1100101" => buf_0_data_in(13 downto 0) <= "00" & x"3e4"; \r
+ when "1100110" => buf_0_data_in(13 downto 0) <= "00" & x"902"; \r
+ when "1100111" => buf_0_data_in(13 downto 0) <= "00" & x"40e"; \r
+ when "1101000" => buf_0_data_in(13 downto 0) <= "00" & x"3d2"; \r
+ when "1101001" => buf_0_data_in(13 downto 0) <= "00" & x"3ef"; \r
+ when "1101010" => buf_0_data_in(13 downto 0) <= "00" & x"490"; \r
+ when "1101011" => buf_0_data_in(13 downto 0) <= "00" & x"402"; \r
+ when "1101100" => buf_0_data_in(13 downto 0) <= "00" & x"3bd"; \r
+ when "1101101" => buf_0_data_in(13 downto 0) <= "00" & x"3d1"; \r
+ when "1101110" => buf_0_data_in(13 downto 0) <= "00" & x"497"; \r
+ when "1101111" => buf_0_data_in(13 downto 0) <= "00" & x"3d2"; \r
+ when "1110000" => buf_0_data_in(13 downto 0) <= "00" & x"3b7"; \r
+ when "1110001" => buf_0_data_in(13 downto 0) <= "00" & x"3da"; \r
+ when "1110010" => buf_0_data_in(13 downto 0) <= "00" & x"4bd"; \r
+ when "1110011" => buf_0_data_in(13 downto 0) <= "00" & x"3c9"; \r
+ when "1110100" => buf_0_data_in(13 downto 0) <= "00" & x"3ba"; \r
+ when "1110101" => buf_0_data_in(13 downto 0) <= "00" & x"3c9"; \r
+ when "1110110" => buf_0_data_in(13 downto 0) <= "00" & x"4e9"; \r
+ when "1110111" => buf_0_data_in(13 downto 0) <= "00" & x"3cc"; \r
+ when "1111000" => buf_0_data_in(13 downto 0) <= "00" & x"3e4"; \r
+ when "1111001" => buf_0_data_in(13 downto 0) <= "00" & x"3b2"; \r
+ when "1111010" => buf_0_data_in(13 downto 0) <= "10" & x"edc"; -- real physical OVERFLOW\r
+ when "1111011" => buf_0_data_in(13 downto 0) <= "00" & x"3c4"; \r
+ when "1111100" => buf_0_data_in(13 downto 0) <= "00" & x"3e6"; \r
+ when "1111101" => buf_0_data_in(13 downto 0) <= "00" & x"3f0"; \r
+ when "1111110" => buf_0_data_in(13 downto 0) <= "00" & x"896"; \r
+ when "1111111" => buf_0_data_in(13 downto 0) <= "00" & x"402"; \r
+ when others => buf_0_data_in(13 downto 0) <= "00" & x"fff"; \r
+ end case;\r
+ end if;\r
+end process BUF_0_DATA_PROC;\r
+\r
+\r
+BUF_0_PED_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ case ped_addr is\r
+ when "0000000" => ped_0_data_in <= "00" & x"0485";\r
+ when "0000001" => ped_0_data_in <= "00" & x"148b"; \r
+ when "0000010" => ped_0_data_in <= "00" & x"2466"; \r
+ when "0000011" => ped_0_data_in <= "00" & x"3479"; \r
+-- when "0000100" => ped_0_data_in <= "00" & x"446e";\r
+ when "0000100" => ped_0_data_in <= "00" & x"446e"; -- physical UNDERFLOW\r
+ when "0000101" => ped_0_data_in <= "00" & x"5470"; \r
+ when "0000110" => ped_0_data_in <= "00" & x"647c"; \r
+ when "0000111" => ped_0_data_in <= "00" & x"7472"; \r
+ when "0001000" => ped_0_data_in <= "00" & x"0472"; \r
+ when "0001001" => ped_0_data_in <= "00" & x"1478"; \r
+-- when "0001010" => ped_0_data_in <= "00" & x"247f"; \r
+ when "0001010" => ped_0_data_in <= "00" & x"247f"; -- physical OVERFLOW\r
+ when "0001011" => ped_0_data_in <= "00" & x"3480"; \r
+ when "0001100" => ped_0_data_in <= "00" & x"4479"; \r
+ when "0001101" => ped_0_data_in <= "00" & x"5464"; \r
+ when "0001110" => ped_0_data_in <= "00" & x"645c"; \r
+ when "0001111" => ped_0_data_in <= "00" & x"7464"; \r
+ when "0010000" => ped_0_data_in <= "00" & x"045a"; \r
+-- when "0010001" => ped_0_data_in <= "00" & x"146f"; \r
+ when "0010001" => ped_0_data_in <= "00" & x"146f"; -- correction UNDERFLOW \r
+ when "0010010" => ped_0_data_in <= "00" & x"245c"; \r
+ when "0010011" => ped_0_data_in <= "00" & x"3445"; \r
+ when "0010100" => ped_0_data_in <= "00" & x"4448"; \r
+ when "0010101" => ped_0_data_in <= "00" & x"546e"; \r
+ when "0010110" => ped_0_data_in <= "00" & x"6450"; \r
+-- when "0010111" => ped_0_data_in <= "00" & x"7448"; \r
+ when "0010111" => ped_0_data_in <= "00" & x"7448"; -- correction OVERFLOW\r
+ when "0011000" => ped_0_data_in <= "00" & x"044d"; \r
+ when "0011001" => ped_0_data_in <= "00" & x"145c"; \r
+ when "0011010" => ped_0_data_in <= "00" & x"243b"; \r
+ when "0011011" => ped_0_data_in <= "00" & x"345a"; \r
+ when "0011100" => ped_0_data_in <= "00" & x"4469"; \r
+ when "0011101" => ped_0_data_in <= "00" & x"546f"; \r
+ when "0011110" => ped_0_data_in <= "00" & x"6455"; \r
+ when "0011111" => ped_0_data_in <= "00" & x"7463"; \r
+ when "0100000" => ped_0_data_in <= "00" & x"0429"; \r
+ when "0100001" => ped_0_data_in <= "00" & x"145b"; \r
+-- when "0100010" => ped_0_data_in <= "00" & x"2435"; \r
+ when "0100010" => ped_0_data_in <= "01" & x"2435"; -- physical OFF \r
+ when "0100011" => ped_0_data_in <= "00" & x"346f"; \r
+ when "0100100" => ped_0_data_in <= "00" & x"4463"; \r
+ when "0100101" => ped_0_data_in <= "00" & x"5454"; \r
+ when "0100110" => ped_0_data_in <= "00" & x"6452"; \r
+ when "0100111" => ped_0_data_in <= "00" & x"746e"; \r
+ when "0101000" => ped_0_data_in <= "00" & x"0469"; \r
+ when "0101001" => ped_0_data_in <= "00" & x"1462"; \r
+ when "0101010" => ped_0_data_in <= "00" & x"2464"; \r
+ when "0101011" => ped_0_data_in <= "00" & x"345e"; \r
+ when "0101100" => ped_0_data_in <= "00" & x"4469"; \r
+ when "0101101" => ped_0_data_in <= "00" & x"5469"; \r
+ when "0101110" => ped_0_data_in <= "00" & x"646d"; \r
+-- when "0101111" => ped_0_data_in <= "00" & x"7485"; \r
+ when "0101111" => ped_0_data_in <= "01" & x"7485"; -- correction OFF\r
+ when "0110000" => ped_0_data_in <= "00" & x"0478"; \r
+ when "0110001" => ped_0_data_in <= "00" & x"147d"; \r
+ when "0110010" => ped_0_data_in <= "00" & x"2468"; \r
+ when "0110011" => ped_0_data_in <= "00" & x"3480"; \r
+ when "0110100" => ped_0_data_in <= "00" & x"447d"; \r
+ when "0110101" => ped_0_data_in <= "00" & x"5480"; \r
+ when "0110110" => ped_0_data_in <= "00" & x"6468"; \r
+ when "0110111" => ped_0_data_in <= "00" & x"7496"; \r
+ when "0111000" => ped_0_data_in <= "00" & x"0471"; \r
+ when "0111001" => ped_0_data_in <= "00" & x"1474"; \r
+ when "0111010" => ped_0_data_in <= "00" & x"246b"; \r
+ when "0111011" => ped_0_data_in <= "00" & x"349b"; \r
+ when "0111100" => ped_0_data_in <= "00" & x"4499"; \r
+ when "0111101" => ped_0_data_in <= "00" & x"5484"; \r
+ when "0111110" => ped_0_data_in <= "00" & x"646d"; \r
+ when "0111111" => ped_0_data_in <= "00" & x"7486"; \r
+ when "1000000" => ped_0_data_in <= "00" & x"048e"; \r
+ when "1000001" => ped_0_data_in <= "00" & x"146e"; \r
+ when "1000010" => ped_0_data_in <= "00" & x"2488"; \r
+ when "1000011" => ped_0_data_in <= "00" & x"3491"; \r
+ when "1000100" => ped_0_data_in <= "00" & x"4487"; \r
+ when "1000101" => ped_0_data_in <= "00" & x"5476"; \r
+ when "1000110" => ped_0_data_in <= "00" & x"6453"; \r
+ when "1000111" => ped_0_data_in <= "00" & x"7484"; \r
+ when "1001000" => ped_0_data_in <= "00" & x"0452"; \r
+ when "1001001" => ped_0_data_in <= "00" & x"146f"; \r
+ when "1001010" => ped_0_data_in <= "00" & x"248d"; \r
+ when "1001011" => ped_0_data_in <= "00" & x"3486"; \r
+ when "1001100" => ped_0_data_in <= "00" & x"445c"; \r
+ when "1001101" => ped_0_data_in <= "00" & x"5475"; \r
+ when "1001110" => ped_0_data_in <= "00" & x"6476"; \r
+ when "1001111" => ped_0_data_in <= "00" & x"7475"; \r
+ when "1010000" => ped_0_data_in <= "00" & x"0472"; \r
+ when "1010001" => ped_0_data_in <= "00" & x"146f"; \r
+ when "1010010" => ped_0_data_in <= "00" & x"244c"; \r
+ when "1010011" => ped_0_data_in <= "00" & x"3479"; \r
+ when "1010100" => ped_0_data_in <= "00" & x"4469"; \r
+ when "1010101" => ped_0_data_in <= "00" & x"547f"; \r
+ when "1010110" => ped_0_data_in <= "00" & x"6478"; \r
+ when "1010111" => ped_0_data_in <= "00" & x"7478"; \r
+ when "1011000" => ped_0_data_in <= "00" & x"0472"; \r
+ when "1011001" => ped_0_data_in <= "00" & x"146c"; \r
+ when "1011010" => ped_0_data_in <= "00" & x"2478"; \r
+ when "1011011" => ped_0_data_in <= "00" & x"3481"; \r
+ when "1011100" => ped_0_data_in <= "00" & x"447a"; \r
+ when "1011101" => ped_0_data_in <= "00" & x"547f"; \r
+ when "1011110" => ped_0_data_in <= "00" & x"649f"; \r
+ when "1011111" => ped_0_data_in <= "00" & x"746f"; \r
+ when "1100000" => ped_0_data_in <= "00" & x"0443"; \r
+ when "1100001" => ped_0_data_in <= "00" & x"145d"; \r
+ when "1100010" => ped_0_data_in <= "00" & x"246f"; \r
+ when "1100011" => ped_0_data_in <= "00" & x"3482"; \r
+ when "1100100" => ped_0_data_in <= "00" & x"4498"; \r
+ when "1100101" => ped_0_data_in <= "00" & x"5483"; \r
+ when "1100110" => ped_0_data_in <= "00" & x"649b"; \r
+ when "1100111" => ped_0_data_in <= "00" & x"74a9"; \r
+ when "1101000" => ped_0_data_in <= "00" & x"0471"; \r
+ when "1101001" => ped_0_data_in <= "00" & x"1488"; \r
+ when "1101010" => ped_0_data_in <= "00" & x"249a"; \r
+ when "1101011" => ped_0_data_in <= "00" & x"349f"; \r
+ when "1101100" => ped_0_data_in <= "00" & x"4473"; \r
+ when "1101101" => ped_0_data_in <= "00" & x"5479"; \r
+ when "1101110" => ped_0_data_in <= "00" & x"648b"; \r
+ when "1101111" => ped_0_data_in <= "00" & x"747e"; \r
+ when "1110000" => ped_0_data_in <= "00" & x"0480"; \r
+ when "1110001" => ped_0_data_in <= "00" & x"1492"; \r
+ when "1110010" => ped_0_data_in <= "00" & x"2482"; \r
+ when "1110011" => ped_0_data_in <= "00" & x"3483"; \r
+ when "1110100" => ped_0_data_in <= "00" & x"447a"; \r
+ when "1110101" => ped_0_data_in <= "00" & x"548a"; \r
+ when "1110110" => ped_0_data_in <= "00" & x"6493"; \r
+ when "1110111" => ped_0_data_in <= "00" & x"7496"; \r
+ when "1111000" => ped_0_data_in <= "00" & x"0495"; \r
+ when "1111001" => ped_0_data_in <= "00" & x"1493"; \r
+ when "1111010" => ped_0_data_in <= "00" & x"2487"; -- real physical OVERFLOW\r
+ when "1111011" => ped_0_data_in <= "00" & x"3496"; \r
+ when "1111100" => ped_0_data_in <= "00" & x"449d"; \r
+ when "1111101" => ped_0_data_in <= "00" & x"54cb"; \r
+ when "1111110" => ped_0_data_in <= "00" & x"64b9"; \r
+ when "1111111" => ped_0_data_in <= "00" & x"74df"; \r
+ when others => ped_0_data_in <= "00" & x"ffff"; \r
+ end case;\r
+ end if;\r
+end process BUF_0_PED_PROC;\r
+\r
+\r
+-- Data faker for "APV 0"...\r
+BUF_0_THR_PROC: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ case thr_addr is\r
+ when "0000000" => thr_0_data_in <= "00" & x"001e";\r
+ when "0000001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "0000010" => thr_0_data_in <= "00" & x"201e"; \r
+ when "0000011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "0000100" => thr_0_data_in <= "00" & x"401e"; \r
+ when "0000101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "0000110" => thr_0_data_in <= "00" & x"601b"; \r
+ when "0000111" => thr_0_data_in <= "00" & x"700f"; \r
+ when "0001000" => thr_0_data_in <= "00" & x"001e"; \r
+ when "0001001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "0001010" => thr_0_data_in <= "00" & x"201e"; \r
+ when "0001011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "0001100" => thr_0_data_in <= "00" & x"4021"; \r
+ when "0001101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "0001110" => thr_0_data_in <= "00" & x"601e"; \r
+ when "0001111" => thr_0_data_in <= "00" & x"700f"; \r
+ when "0010000" => thr_0_data_in <= "00" & x"001e"; \r
+ when "0010001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "0010010" => thr_0_data_in <= "00" & x"2021"; \r
+ when "0010011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "0010100" => thr_0_data_in <= "00" & x"402d"; \r
+ when "0010101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "0010110" => thr_0_data_in <= "00" & x"602a"; \r
+ when "0010111" => thr_0_data_in <= "00" & x"700f"; \r
+ when "0011000" => thr_0_data_in <= "00" & x"001e"; \r
+ when "0011001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "0011010" => thr_0_data_in <= "00" & x"2021"; \r
+ when "0011011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "0011100" => thr_0_data_in <= "00" & x"401e"; \r
+ when "0011101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "0011110" => thr_0_data_in <= "00" & x"601b"; \r
+ when "0011111" => thr_0_data_in <= "00" & x"700f"; \r
+ when "0100000" => thr_0_data_in <= "00" & x"001e"; \r
+ when "0100001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "0100010" => thr_0_data_in <= "00" & x"201e"; \r
+ when "0100011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "0100100" => thr_0_data_in <= "00" & x"4021"; \r
+ when "0100101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "0100110" => thr_0_data_in <= "00" & x"601b"; \r
+ when "0100111" => thr_0_data_in <= "00" & x"700f"; \r
+ when "0101000" => thr_0_data_in <= "00" & x"001b"; \r
+ when "0101001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "0101010" => thr_0_data_in <= "00" & x"201e"; \r
+ when "0101011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "0101100" => thr_0_data_in <= "00" & x"401e"; \r
+ when "0101101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "0101110" => thr_0_data_in <= "00" & x"601b"; \r
+ when "0101111" => thr_0_data_in <= "00" & x"700f"; \r
+ when "0110000" => thr_0_data_in <= "00" & x"000f"; \r
+ when "0110001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "0110010" => thr_0_data_in <= "00" & x"201e"; \r
+ when "0110011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "0110100" => thr_0_data_in <= "00" & x"4021"; \r
+ when "0110101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "0110110" => thr_0_data_in <= "00" & x"601e"; \r
+ when "0110111" => thr_0_data_in <= "00" & x"700f"; \r
+ when "0111000" => thr_0_data_in <= "00" & x"0021"; \r
+ when "0111001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "0111010" => thr_0_data_in <= "00" & x"2027"; \r
+ when "0111011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "0111100" => thr_0_data_in <= "00" & x"400f"; \r
+ when "0111101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "0111110" => thr_0_data_in <= "00" & x"6048"; \r
+ when "0111111" => thr_0_data_in <= "00" & x"700f"; \r
+ when "1000000" => thr_0_data_in <= "00" & x"0024"; \r
+ when "1000001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "1000010" => thr_0_data_in <= "00" & x"2024"; \r
+ when "1000011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "1000100" => thr_0_data_in <= "00" & x"4021"; \r
+ when "1000101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "1000110" => thr_0_data_in <= "00" & x"6021"; \r
+ when "1000111" => thr_0_data_in <= "00" & x"700f"; \r
+ when "1001000" => thr_0_data_in <= "00" & x"001e"; \r
+ when "1001001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "1001010" => thr_0_data_in <= "00" & x"2021"; \r
+ when "1001011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "1001100" => thr_0_data_in <= "00" & x"4021"; \r
+ when "1001101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "1001110" => thr_0_data_in <= "00" & x"601b"; \r
+ when "1001111" => thr_0_data_in <= "00" & x"700f"; \r
+ when "1010000" => thr_0_data_in <= "00" & x"001b"; \r
+ when "1010001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "1010010" => thr_0_data_in <= "00" & x"201e"; \r
+ when "1010011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "1010100" => thr_0_data_in <= "00" & x"4021"; \r
+ when "1010101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "1010110" => thr_0_data_in <= "00" & x"601e"; \r
+ when "1010111" => thr_0_data_in <= "00" & x"700f"; \r
+ when "1011000" => thr_0_data_in <= "00" & x"001e"; \r
+ when "1011001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "1011010" => thr_0_data_in <= "00" & x"2021"; \r
+ when "1011011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "1011100" => thr_0_data_in <= "00" & x"4021"; \r
+ when "1011101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "1011110" => thr_0_data_in <= "00" & x"601e"; \r
+ when "1011111" => thr_0_data_in <= "00" & x"700f"; \r
+ when "1100000" => thr_0_data_in <= "00" & x"001e"; \r
+ when "1100001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "1100010" => thr_0_data_in <= "00" & x"2021"; \r
+ when "1100011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "1100100" => thr_0_data_in <= "00" & x"4021"; \r
+ when "1100101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "1100110" => thr_0_data_in <= "00" & x"601e"; \r
+ when "1100111" => thr_0_data_in <= "00" & x"700f"; \r
+ when "1101000" => thr_0_data_in <= "00" & x"0021"; \r
+ when "1101001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "1101010" => thr_0_data_in <= "00" & x"2027"; \r
+ when "1101011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "1101100" => thr_0_data_in <= "00" & x"4024"; \r
+ when "1101101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "1101110" => thr_0_data_in <= "00" & x"6021"; \r
+ when "1101111" => thr_0_data_in <= "00" & x"700f"; \r
+ when "1110000" => thr_0_data_in <= "00" & x"001e"; \r
+ when "1110001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "1110010" => thr_0_data_in <= "00" & x"2024"; \r
+ when "1110011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "1110100" => thr_0_data_in <= "00" & x"400f"; \r
+ when "1110101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "1110110" => thr_0_data_in <= "00" & x"601e"; \r
+ when "1110111" => thr_0_data_in <= "00" & x"700f"; \r
+ when "1111000" => thr_0_data_in <= "00" & x"001e"; \r
+ when "1111001" => thr_0_data_in <= "00" & x"100f"; \r
+ when "1111010" => thr_0_data_in <= "00" & x"2024"; \r
+ when "1111011" => thr_0_data_in <= "00" & x"300f"; \r
+ when "1111100" => thr_0_data_in <= "00" & x"4021"; \r
+ when "1111101" => thr_0_data_in <= "00" & x"500f"; \r
+ when "1111110" => thr_0_data_in <= "00" & x"6021"; \r
+ when "1111111" => thr_0_data_in <= "00" & x"700f"; \r
+ when others => thr_0_data_in <= "00" & x"ffff"; \r
+ end case;\r
+ end if;\r
+end process BUF_0_THR_PROC;\r
+\r
+END;\r
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT pulse_stretch\r
+ PORT(\r
+ RESET_IN : IN std_logic;\r
+ CLK_IN : IN std_logic;\r
+ START_IN : IN std_logic; \r
+ PULSE_OUT : OUT std_logic;\r
+ DEBUG_OUT : OUT std_logic_vector(15 downto 0)\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL RESET_IN : std_logic;\r
+ SIGNAL CLK_IN : std_logic;\r
+ SIGNAL START_IN : std_logic;\r
+ SIGNAL PULSE_OUT : std_logic;\r
+ SIGNAL DEBUG_OUT : std_logic_vector(15 downto 0);\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: pulse_stretch PORT MAP(\r
+ RESET_IN => RESET_IN,\r
+ CLK_IN => CLK_IN,\r
+ START_IN => START_IN,\r
+ PULSE_OUT => PULSE_OUT,\r
+ DEBUG_OUT => DEBUG_OUT\r
+ );\r
+\r
+THE_CLOCK_GEN: process\r
+begin\r
+ clk_in <= '1'; wait for 5 ns;\r
+ clk_in <= '0'; wait for 5 ns;\r
+end process THE_CLOCK_GEN;\r
+\r
+THE_TEST_BENCH: process\r
+begin\r
+ -- Setup signals\r
+ reset_in <= '0';\r
+ start_in <= '0';\r
+ \r
+ -- Sync reset\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait for 140 ns;\r
+ \r
+ -- Tests may start now\r
+ wait until rising_edge(clk_in);\r
+ start_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ start_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ \r
+\r
+\r
+ -- Stay a while, stay forever....\r
+ wait;\r
+end process THE_TEST_BENCH; \r
+\r
+END;\r
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT raw_buf_stage\r
+ PORT(\r
+ CLK_IN : IN std_logic;\r
+ RESET_APV_IN : IN std_logic;\r
+ RESET_IN : IN std_logic;\r
+ APV_SYNC_IN : IN std_logic;\r
+ APV_FRAME_REQD_IN : IN std_logic;\r
+ ADC0_PLL_LOCK_IN : IN std_logic;\r
+ ADC0_CLK40M_IN : IN std_logic;\r
+ ADC0_0_DATA_IN : IN std_logic_vector(11 downto 0);\r
+ ADC0_1_DATA_IN : IN std_logic_vector(11 downto 0);\r
+ ADC0_2_DATA_IN : IN std_logic_vector(11 downto 0);\r
+ ADC0_3_DATA_IN : IN std_logic_vector(11 downto 0);\r
+ ADC0_4_DATA_IN : IN std_logic_vector(11 downto 0);\r
+ ADC0_5_DATA_IN : IN std_logic_vector(11 downto 0);\r
+ ADC0_6_DATA_IN : IN std_logic_vector(11 downto 0);\r
+ ADC0_7_DATA_IN : IN std_logic_vector(11 downto 0);\r
+ ADC1_PLL_LOCK_IN : IN std_logic;\r
+ ADC1_CLK40M_IN : IN std_logic;\r
+ ADC1_0_DATA_IN : IN std_logic_vector(11 downto 0);\r
+ ADC1_1_DATA_IN : IN std_logic_vector(11 downto 0);\r
+ ADC1_2_DATA_IN : IN std_logic_vector(11 downto 0);\r
+ ADC1_3_DATA_IN : IN std_logic_vector(11 downto 0);\r
+ ADC1_4_DATA_IN : IN std_logic_vector(11 downto 0);\r
+ ADC1_5_DATA_IN : IN std_logic_vector(11 downto 0);\r
+ ADC1_6_DATA_IN : IN std_logic_vector(11 downto 0);\r
+ ADC1_7_DATA_IN : IN std_logic_vector(11 downto 0);\r
+ MAX_TRG_NUM_IN : IN std_logic_vector(3 downto 0);\r
+ BIT_LOW_IN : IN std_logic_vector(11 downto 0);\r
+ BIT_HIGH_IN : IN std_logic_vector(11 downto 0);\r
+ FL_LOW_IN : IN std_logic_vector(11 downto 0);\r
+ FL_HIGH_IN : IN std_logic_vector(11 downto 0);\r
+ APV_ON_IN : IN std_logic_vector(15 downto 0);\r
+ BUF_ADDR_IN : IN std_logic_vector(6 downto 0);\r
+ BUF_DONE_IN : IN std_logic; \r
+ BUF_FULL_OUT : OUT std_logic;\r
+ BUF_TICK_OUT : OUT std_logic_vector(15 downto 0);\r
+ BUF_START_OUT : OUT std_logic_vector(15 downto 0);\r
+ BUF_READY_OUT : OUT std_logic_vector(15 downto 0);\r
+ BUF_0_DATA_OUT : OUT std_logic_vector(37 downto 0);\r
+ BUF_1_DATA_OUT : OUT std_logic_vector(37 downto 0);\r
+ BUF_2_DATA_OUT : OUT std_logic_vector(37 downto 0);\r
+ BUF_3_DATA_OUT : OUT std_logic_vector(37 downto 0);\r
+ BUF_4_DATA_OUT : OUT std_logic_vector(37 downto 0);\r
+ BUF_5_DATA_OUT : OUT std_logic_vector(37 downto 0);\r
+ BUF_6_DATA_OUT : OUT std_logic_vector(37 downto 0);\r
+ BUF_7_DATA_OUT : OUT std_logic_vector(37 downto 0);\r
+ BUF_8_DATA_OUT : OUT std_logic_vector(37 downto 0);\r
+ BUF_9_DATA_OUT : OUT std_logic_vector(37 downto 0);\r
+ BUF_10_DATA_OUT : OUT std_logic_vector(37 downto 0);\r
+ BUF_11_DATA_OUT : OUT std_logic_vector(37 downto 0);\r
+ BUF_12_DATA_OUT : OUT std_logic_vector(37 downto 0);\r
+ BUF_13_DATA_OUT : OUT std_logic_vector(37 downto 0);\r
+ BUF_14_DATA_OUT : OUT std_logic_vector(37 downto 0);\r
+ BUF_15_DATA_OUT : OUT std_logic_vector(37 downto 0);\r
+ DEBUG_OUT : OUT std_logic_vector(31 downto 0)\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL CLK_IN : std_logic;\r
+ SIGNAL RESET_APV_IN : std_logic;\r
+ SIGNAL RESET_IN : std_logic;\r
+ SIGNAL APV_SYNC_IN : std_logic;\r
+ SIGNAL APV_FRAME_REQD_IN : std_logic;\r
+ SIGNAL ADC0_PLL_LOCK_IN : std_logic;\r
+ SIGNAL ADC0_CLK40M_IN : std_logic;\r
+ SIGNAL ADC0_0_DATA_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC0_1_DATA_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC0_2_DATA_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC0_3_DATA_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC0_4_DATA_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC0_5_DATA_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC0_6_DATA_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC0_7_DATA_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC1_PLL_LOCK_IN : std_logic;\r
+ SIGNAL ADC1_CLK40M_IN : std_logic;\r
+ SIGNAL ADC1_0_DATA_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC1_1_DATA_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC1_2_DATA_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC1_3_DATA_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC1_4_DATA_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC1_5_DATA_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC1_6_DATA_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC1_7_DATA_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL MAX_TRG_NUM_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL BIT_LOW_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL BIT_HIGH_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL FL_LOW_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL FL_HIGH_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL APV_ON_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL BUF_FULL_OUT : std_logic;\r
+ SIGNAL BUF_ADDR_IN : std_logic_vector(6 downto 0);\r
+ SIGNAL BUF_DONE_IN : std_logic;\r
+ SIGNAL BUF_TICK_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL BUF_START_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL BUF_READY_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL BUF_0_DATA_OUT : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_1_DATA_OUT : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_2_DATA_OUT : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_3_DATA_OUT : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_4_DATA_OUT : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_5_DATA_OUT : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_6_DATA_OUT : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_7_DATA_OUT : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_8_DATA_OUT : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_9_DATA_OUT : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_10_DATA_OUT : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_11_DATA_OUT : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_12_DATA_OUT : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_13_DATA_OUT : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_14_DATA_OUT : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_15_DATA_OUT : std_logic_vector(37 downto 0);\r
+ SIGNAL DEBUG_OUT : std_logic_vector(31 downto 0);\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: raw_buf_stage PORT MAP(\r
+ CLK_IN => CLK_IN,\r
+ RESET_APV_IN => RESET_APV_IN,\r
+ RESET_IN => RESET_IN,\r
+ APV_SYNC_IN => APV_SYNC_IN,\r
+ APV_FRAME_REQD_IN => APV_FRAME_REQD_IN,\r
+ ADC0_PLL_LOCK_IN => ADC0_PLL_LOCK_IN,\r
+ ADC0_CLK40M_IN => ADC0_CLK40M_IN,\r
+ ADC0_0_DATA_IN => ADC0_0_DATA_IN,\r
+ ADC0_1_DATA_IN => ADC0_1_DATA_IN,\r
+ ADC0_2_DATA_IN => ADC0_2_DATA_IN,\r
+ ADC0_3_DATA_IN => ADC0_3_DATA_IN,\r
+ ADC0_4_DATA_IN => ADC0_4_DATA_IN,\r
+ ADC0_5_DATA_IN => ADC0_5_DATA_IN,\r
+ ADC0_6_DATA_IN => ADC0_6_DATA_IN,\r
+ ADC0_7_DATA_IN => ADC0_7_DATA_IN,\r
+ ADC1_PLL_LOCK_IN => ADC1_PLL_LOCK_IN,\r
+ ADC1_CLK40M_IN => ADC1_CLK40M_IN,\r
+ ADC1_0_DATA_IN => ADC1_0_DATA_IN,\r
+ ADC1_1_DATA_IN => ADC1_1_DATA_IN,\r
+ ADC1_2_DATA_IN => ADC1_2_DATA_IN,\r
+ ADC1_3_DATA_IN => ADC1_3_DATA_IN,\r
+ ADC1_4_DATA_IN => ADC1_4_DATA_IN,\r
+ ADC1_5_DATA_IN => ADC1_5_DATA_IN,\r
+ ADC1_6_DATA_IN => ADC1_6_DATA_IN,\r
+ ADC1_7_DATA_IN => ADC1_7_DATA_IN,\r
+ MAX_TRG_NUM_IN => MAX_TRG_NUM_IN,\r
+ BIT_LOW_IN => BIT_LOW_IN,\r
+ BIT_HIGH_IN => BIT_HIGH_IN,\r
+ FL_LOW_IN => FL_LOW_IN,\r
+ FL_HIGH_IN => FL_HIGH_IN,\r
+ APV_ON_IN => APV_ON_IN,\r
+ BUF_FULL_OUT => BUF_FULL_OUT,\r
+ BUF_ADDR_IN => BUF_ADDR_IN,\r
+ BUF_DONE_IN => BUF_DONE_IN,\r
+ BUF_TICK_OUT => BUF_TICK_OUT,\r
+ BUF_START_OUT => BUF_START_OUT,\r
+ BUF_READY_OUT => BUF_READY_OUT,\r
+ BUF_0_DATA_OUT => BUF_0_DATA_OUT,\r
+ BUF_1_DATA_OUT => BUF_1_DATA_OUT,\r
+ BUF_2_DATA_OUT => BUF_2_DATA_OUT,\r
+ BUF_3_DATA_OUT => BUF_3_DATA_OUT,\r
+ BUF_4_DATA_OUT => BUF_4_DATA_OUT,\r
+ BUF_5_DATA_OUT => BUF_5_DATA_OUT,\r
+ BUF_6_DATA_OUT => BUF_6_DATA_OUT,\r
+ BUF_7_DATA_OUT => BUF_7_DATA_OUT,\r
+ BUF_8_DATA_OUT => BUF_8_DATA_OUT,\r
+ BUF_9_DATA_OUT => BUF_9_DATA_OUT,\r
+ BUF_10_DATA_OUT => BUF_10_DATA_OUT,\r
+ BUF_11_DATA_OUT => BUF_11_DATA_OUT,\r
+ BUF_12_DATA_OUT => BUF_12_DATA_OUT,\r
+ BUF_13_DATA_OUT => BUF_13_DATA_OUT,\r
+ BUF_14_DATA_OUT => BUF_14_DATA_OUT,\r
+ BUF_15_DATA_OUT => BUF_15_DATA_OUT,\r
+ DEBUG_OUT => DEBUG_OUT\r
+ );\r
+\r
+-- ADC0 and ADC1 40MHz clock\r
+THE_ADC_CLOCK_GEN: process\r
+begin\r
+ adc0_clk40m_in <= '1'; adc1_clk40m_in <= '1'; wait for 12.5 ns;\r
+ adc0_clk40m_in <= '0'; adc1_clk40m_in <= '0'; wait for 12.5 ns;\r
+end process THE_ADC_CLOCK_GEN;\r
+\r
+-- 100MHz system clock\r
+THE_CLOCK_GEN: process\r
+begin\r
+ clk_in <= '1'; wait for 5 ns;\r
+ clk_in <= '0'; wait for 5 ns;\r
+end process THE_CLOCK_GEN;\r
+\r
+THE_TEST_BENCH: process\r
+begin\r
+ -- Setup signals\r
+ reset_in <= '0'; \r
+ reset_apv_in <= '0';\r
+ apv_sync_in <= '0';\r
+ apv_frame_reqd_in <= '0';\r
+ adc0_pll_lock_in <= '0';\r
+ adc0_0_data_in <= x"000";\r
+ adc0_1_data_in <= x"800";\r
+ adc0_2_data_in <= x"800";\r
+ adc0_3_data_in <= x"800";\r
+ adc0_4_data_in <= x"800";\r
+ adc0_5_data_in <= x"800";\r
+ adc0_6_data_in <= x"800";\r
+ adc0_7_data_in <= x"800";\r
+ adc1_pll_lock_in <= '0';\r
+ adc1_0_data_in <= x"800";\r
+ adc1_1_data_in <= x"800";\r
+ adc1_2_data_in <= x"800";\r
+ adc1_3_data_in <= x"800";\r
+ adc1_4_data_in <= x"800";\r
+ adc1_5_data_in <= x"800";\r
+ adc1_6_data_in <= x"800";\r
+ adc1_7_data_in <= x"800";\r
+ max_trg_num_in <= x"1";\r
+ bit_low_in <= x"200"; \r
+ bit_high_in <= x"e00"; \r
+ fl_low_in <= x"780"; \r
+ fl_high_in <= x"880"; \r
+ apv_on_in <= x"0001";\r
+ buf_addr_in <= (others => '0');\r
+ buf_done_in <= '0';\r
+ wait for 100 ns;\r
+\r
+ -- Reset all\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ reset_apv_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ reset_apv_in <= '0';\r
+ wait for 100 ns;\r
+\r
+ wait until rising_edge(clk_in);\r
+ adc0_pll_lock_in <= '1';\r
+ adc1_pll_lock_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- Tests may start now\r
+ wait until rising_edge(clk_in);\r
+\r
+ \r
+ \r
+\r
+\r
+ -- Stay a while, stay forever!\r
+ wait;\r
+ \r
+end process THE_TEST_BENCH;\r
+\r
+END;\r
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT raw_buf_stage_new\r
+ PORT(\r
+ CLK_IN : IN std_logic;\r
+ RESET_APV_IN : IN std_logic;\r
+ RESET_IN : IN std_logic;\r
+ APV_SYNC_IN : IN std_logic;\r
+ APV_FRAME_REQD_IN : IN std_logic;\r
+ ADC0_PLL_LOCK_IN : IN std_logic;\r
+ ADC0_CLK40M_IN : IN std_logic;\r
+ ADC0_0_DATA_IN : IN std_logic_vector(11 downto 0);\r
+ ADC0_1_DATA_IN : IN std_logic_vector(11 downto 0);\r
+ ADC0_2_DATA_IN : IN std_logic_vector(11 downto 0);\r
+ ADC0_3_DATA_IN : IN std_logic_vector(11 downto 0);\r
+ ADC0_4_DATA_IN : IN std_logic_vector(11 downto 0);\r
+ ADC0_5_DATA_IN : IN std_logic_vector(11 downto 0);\r
+ ADC0_6_DATA_IN : IN std_logic_vector(11 downto 0);\r
+ ADC0_7_DATA_IN : IN std_logic_vector(11 downto 0);\r
+ ADC1_PLL_LOCK_IN : IN std_logic;\r
+ ADC1_CLK40M_IN : IN std_logic;\r
+ ADC1_0_DATA_IN : IN std_logic_vector(11 downto 0);\r
+ ADC1_1_DATA_IN : IN std_logic_vector(11 downto 0);\r
+ ADC1_2_DATA_IN : IN std_logic_vector(11 downto 0);\r
+ ADC1_3_DATA_IN : IN std_logic_vector(11 downto 0);\r
+ ADC1_4_DATA_IN : IN std_logic_vector(11 downto 0);\r
+ ADC1_5_DATA_IN : IN std_logic_vector(11 downto 0);\r
+ ADC1_6_DATA_IN : IN std_logic_vector(11 downto 0);\r
+ ADC1_7_DATA_IN : IN std_logic_vector(11 downto 0);\r
+ MAX_TRG_NUM_IN : IN std_logic_vector(3 downto 0);\r
+ BIT_LOW_IN : IN std_logic_vector(11 downto 0);\r
+ BIT_HIGH_IN : IN std_logic_vector(11 downto 0);\r
+ FL_LOW_IN : IN std_logic_vector(11 downto 0);\r
+ FL_HIGH_IN : IN std_logic_vector(11 downto 0);\r
+ APV_ON_IN : IN std_logic_vector(15 downto 0);\r
+ BUF_ADDR_IN : IN std_logic_vector(6 downto 0);\r
+ BUF_DONE_IN : IN std_logic; \r
+ BUF_FULL_OUT : OUT std_logic;\r
+ BUF_TICK_OUT : OUT std_logic_vector(15 downto 0);\r
+ BUF_START_OUT : OUT std_logic_vector(15 downto 0);\r
+ BUF_READY_OUT : OUT std_logic_vector(15 downto 0);\r
+ BUF_0_DATA_OUT : OUT std_logic_vector(37 downto 0);\r
+ BUF_1_DATA_OUT : OUT std_logic_vector(37 downto 0);\r
+ BUF_2_DATA_OUT : OUT std_logic_vector(37 downto 0);\r
+ BUF_3_DATA_OUT : OUT std_logic_vector(37 downto 0);\r
+ BUF_4_DATA_OUT : OUT std_logic_vector(37 downto 0);\r
+ BUF_5_DATA_OUT : OUT std_logic_vector(37 downto 0);\r
+ BUF_6_DATA_OUT : OUT std_logic_vector(37 downto 0);\r
+ BUF_7_DATA_OUT : OUT std_logic_vector(37 downto 0);\r
+ BUF_8_DATA_OUT : OUT std_logic_vector(37 downto 0);\r
+ BUF_9_DATA_OUT : OUT std_logic_vector(37 downto 0);\r
+ BUF_10_DATA_OUT : OUT std_logic_vector(37 downto 0);\r
+ BUF_11_DATA_OUT : OUT std_logic_vector(37 downto 0);\r
+ BUF_12_DATA_OUT : OUT std_logic_vector(37 downto 0);\r
+ BUF_13_DATA_OUT : OUT std_logic_vector(37 downto 0);\r
+ BUF_14_DATA_OUT : OUT std_logic_vector(37 downto 0);\r
+ BUF_15_DATA_OUT : OUT std_logic_vector(37 downto 0);\r
+ DEBUG_OUT : OUT std_logic_vector(31 downto 0)\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL CLK_IN : std_logic;\r
+ SIGNAL RESET_APV_IN : std_logic;\r
+ SIGNAL RESET_IN : std_logic;\r
+ SIGNAL APV_SYNC_IN : std_logic;\r
+ SIGNAL APV_FRAME_REQD_IN : std_logic;\r
+ SIGNAL ADC0_PLL_LOCK_IN : std_logic;\r
+ SIGNAL ADC0_CLK40M_IN : std_logic;\r
+ SIGNAL ADC0_0_DATA_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC0_1_DATA_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC0_2_DATA_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC0_3_DATA_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC0_4_DATA_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC0_5_DATA_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC0_6_DATA_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC0_7_DATA_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC1_PLL_LOCK_IN : std_logic;\r
+ SIGNAL ADC1_CLK40M_IN : std_logic;\r
+ SIGNAL ADC1_0_DATA_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC1_1_DATA_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC1_2_DATA_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC1_3_DATA_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC1_4_DATA_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC1_5_DATA_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC1_6_DATA_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL ADC1_7_DATA_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL MAX_TRG_NUM_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL BIT_LOW_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL BIT_HIGH_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL FL_LOW_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL FL_HIGH_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL APV_ON_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL BUF_FULL_OUT : std_logic;\r
+ SIGNAL BUF_ADDR_IN : std_logic_vector(6 downto 0);\r
+ SIGNAL BUF_DONE_IN : std_logic;\r
+ SIGNAL BUF_TICK_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL BUF_START_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL BUF_READY_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL BUF_0_DATA_OUT : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_1_DATA_OUT : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_2_DATA_OUT : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_3_DATA_OUT : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_4_DATA_OUT : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_5_DATA_OUT : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_6_DATA_OUT : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_7_DATA_OUT : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_8_DATA_OUT : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_9_DATA_OUT : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_10_DATA_OUT : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_11_DATA_OUT : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_12_DATA_OUT : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_13_DATA_OUT : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_14_DATA_OUT : std_logic_vector(37 downto 0);\r
+ SIGNAL BUF_15_DATA_OUT : std_logic_vector(37 downto 0);\r
+ SIGNAL DEBUG_OUT : std_logic_vector(31 downto 0);\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: raw_buf_stage_new PORT MAP(\r
+ CLK_IN => CLK_IN,\r
+ RESET_APV_IN => RESET_APV_IN,\r
+ RESET_IN => RESET_IN,\r
+ APV_SYNC_IN => APV_SYNC_IN,\r
+ APV_FRAME_REQD_IN => APV_FRAME_REQD_IN,\r
+ ADC0_PLL_LOCK_IN => ADC0_PLL_LOCK_IN,\r
+ ADC0_CLK40M_IN => ADC0_CLK40M_IN,\r
+ ADC0_0_DATA_IN => ADC0_0_DATA_IN,\r
+ ADC0_1_DATA_IN => ADC0_1_DATA_IN,\r
+ ADC0_2_DATA_IN => ADC0_2_DATA_IN,\r
+ ADC0_3_DATA_IN => ADC0_3_DATA_IN,\r
+ ADC0_4_DATA_IN => ADC0_4_DATA_IN,\r
+ ADC0_5_DATA_IN => ADC0_5_DATA_IN,\r
+ ADC0_6_DATA_IN => ADC0_6_DATA_IN,\r
+ ADC0_7_DATA_IN => ADC0_7_DATA_IN,\r
+ ADC1_PLL_LOCK_IN => ADC1_PLL_LOCK_IN,\r
+ ADC1_CLK40M_IN => ADC1_CLK40M_IN,\r
+ ADC1_0_DATA_IN => ADC1_0_DATA_IN,\r
+ ADC1_1_DATA_IN => ADC1_1_DATA_IN,\r
+ ADC1_2_DATA_IN => ADC1_2_DATA_IN,\r
+ ADC1_3_DATA_IN => ADC1_3_DATA_IN,\r
+ ADC1_4_DATA_IN => ADC1_4_DATA_IN,\r
+ ADC1_5_DATA_IN => ADC1_5_DATA_IN,\r
+ ADC1_6_DATA_IN => ADC1_6_DATA_IN,\r
+ ADC1_7_DATA_IN => ADC1_7_DATA_IN,\r
+ MAX_TRG_NUM_IN => MAX_TRG_NUM_IN,\r
+ BIT_LOW_IN => BIT_LOW_IN,\r
+ BIT_HIGH_IN => BIT_HIGH_IN,\r
+ FL_LOW_IN => FL_LOW_IN,\r
+ FL_HIGH_IN => FL_HIGH_IN,\r
+ APV_ON_IN => APV_ON_IN,\r
+ BUF_FULL_OUT => BUF_FULL_OUT,\r
+ BUF_ADDR_IN => BUF_ADDR_IN,\r
+ BUF_DONE_IN => BUF_DONE_IN,\r
+ BUF_TICK_OUT => BUF_TICK_OUT,\r
+ BUF_START_OUT => BUF_START_OUT,\r
+ BUF_READY_OUT => BUF_READY_OUT,\r
+ BUF_0_DATA_OUT => BUF_0_DATA_OUT,\r
+ BUF_1_DATA_OUT => BUF_1_DATA_OUT,\r
+ BUF_2_DATA_OUT => BUF_2_DATA_OUT,\r
+ BUF_3_DATA_OUT => BUF_3_DATA_OUT,\r
+ BUF_4_DATA_OUT => BUF_4_DATA_OUT,\r
+ BUF_5_DATA_OUT => BUF_5_DATA_OUT,\r
+ BUF_6_DATA_OUT => BUF_6_DATA_OUT,\r
+ BUF_7_DATA_OUT => BUF_7_DATA_OUT,\r
+ BUF_8_DATA_OUT => BUF_8_DATA_OUT,\r
+ BUF_9_DATA_OUT => BUF_9_DATA_OUT,\r
+ BUF_10_DATA_OUT => BUF_10_DATA_OUT,\r
+ BUF_11_DATA_OUT => BUF_11_DATA_OUT,\r
+ BUF_12_DATA_OUT => BUF_12_DATA_OUT,\r
+ BUF_13_DATA_OUT => BUF_13_DATA_OUT,\r
+ BUF_14_DATA_OUT => BUF_14_DATA_OUT,\r
+ BUF_15_DATA_OUT => BUF_15_DATA_OUT,\r
+ DEBUG_OUT => DEBUG_OUT\r
+ );\r
+\r
+-- ADC0 and ADC1 40MHz clock\r
+THE_ADC_CLOCK_GEN: process\r
+begin\r
+ adc0_clk40m_in <= '1'; adc1_clk40m_in <= '1'; wait for 12.5 ns;\r
+ adc0_clk40m_in <= '0'; adc1_clk40m_in <= '0'; wait for 12.5 ns;\r
+end process THE_ADC_CLOCK_GEN;\r
+\r
+-- 100MHz system clock\r
+THE_CLOCK_GEN: process\r
+begin\r
+ clk_in <= '1'; wait for 5 ns;\r
+ clk_in <= '0'; wait for 5 ns;\r
+end process THE_CLOCK_GEN;\r
+\r
+THE_TEST_BENCH: process\r
+begin\r
+ -- Setup signals\r
+ reset_in <= '0'; \r
+ reset_apv_in <= '0';\r
+ apv_sync_in <= '0';\r
+ apv_frame_reqd_in <= '0';\r
+ adc0_pll_lock_in <= '0';\r
+ adc0_0_data_in <= x"000";\r
+ adc0_1_data_in <= x"800";\r
+ adc0_2_data_in <= x"800";\r
+ adc0_3_data_in <= x"800";\r
+ adc0_4_data_in <= x"800";\r
+ adc0_5_data_in <= x"800";\r
+ adc0_6_data_in <= x"800";\r
+ adc0_7_data_in <= x"800";\r
+ adc1_pll_lock_in <= '0';\r
+ adc1_0_data_in <= x"800";\r
+ adc1_1_data_in <= x"800";\r
+ adc1_2_data_in <= x"800";\r
+ adc1_3_data_in <= x"800";\r
+ adc1_4_data_in <= x"800";\r
+ adc1_5_data_in <= x"800";\r
+ adc1_6_data_in <= x"800";\r
+ adc1_7_data_in <= x"800";\r
+ max_trg_num_in <= x"1";\r
+ bit_low_in <= x"200"; \r
+ bit_high_in <= x"e00"; \r
+ fl_low_in <= x"780"; \r
+ fl_high_in <= x"880"; \r
+ apv_on_in <= x"0001";\r
+ buf_addr_in <= (others => '0');\r
+ buf_done_in <= '0';\r
+ wait for 100 ns;\r
+\r
+ -- Reset all\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ reset_apv_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ reset_apv_in <= '0';\r
+ wait for 100 ns;\r
+\r
+ wait until rising_edge(clk_in);\r
+ adc0_pll_lock_in <= '1';\r
+ adc1_pll_lock_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- Tests may start now\r
+ wait until rising_edge(clk_in);\r
+\r
+ \r
+ \r
+\r
+\r
+ -- Stay a while, stay forever!\r
+ wait;\r
+ \r
+end process THE_TEST_BENCH;\r
+\r
+END;\r
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT real_trg_handler\r
+ PORT(\r
+ CLK_IN : IN std_logic;\r
+ CLEAR_IN : IN std_logic;\r
+ RESET_IN : IN std_logic;\r
+ TIME_TRG_IN : IN std_logic_vector(3 downto 0);\r
+ TRB_TRG_IN : IN std_logic_vector(3 downto 0);\r
+ APV_TRGDONE_IN : IN std_logic;\r
+ TRG_3_TODO_IN : IN std_logic_vector(3 downto 0);\r
+ TRG_2_TODO_IN : IN std_logic_vector(3 downto 0);\r
+ TRG_1_TODO_IN : IN std_logic_vector(3 downto 0);\r
+ TRG_0_TODO_IN : IN std_logic_vector(3 downto 0);\r
+ TRB_TTAG_IN : IN std_logic_vector(15 downto 0);\r
+ TRB_TRND_IN : IN std_logic_vector(7 downto 0);\r
+ TRB_TTYPE_IN : IN std_logic_vector(3 downto 0);\r
+ TRB_TRGRCVD_IN : IN std_logic;\r
+ BUSY_RELEASE_IN : IN std_logic; \r
+ TRB_MISMATCH_OUT : OUT std_logic;\r
+ LVL1_COUNTER_OUT : OUT std_logic_vector(15 downto 0);\r
+ APV_TRGSEL_OUT : OUT std_logic_vector(3 downto 0);\r
+ APV_TRGSTART_OUT : OUT std_logic;\r
+ EDS_DATA_OUT : OUT std_logic_vector(39 downto 0);\r
+ EDS_WE_OUT : OUT std_logic;\r
+ EDS_START_OUT : OUT std_logic;\r
+ EDS_READY_OUT : OUT std_logic;\r
+ DBG_FRMCTR_OUT : OUT std_logic_vector(3 downto 0);\r
+ BSM_OUT : OUT std_logic_vector(7 downto 0);\r
+ DEBUG_OUT : OUT std_logic_vector(15 downto 0)\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL CLK_IN : std_logic;\r
+ SIGNAL CLEAR_IN : std_logic;\r
+ SIGNAL RESET_IN : std_logic;\r
+ SIGNAL TIME_TRG_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL TRB_TRG_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL APV_TRGDONE_IN : std_logic;\r
+ SIGNAL TRG_3_TODO_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL TRG_2_TODO_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL TRG_1_TODO_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL TRG_0_TODO_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL TRB_TTAG_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL TRB_TRND_IN : std_logic_vector(7 downto 0);\r
+ SIGNAL TRB_TTYPE_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL TRB_TRGRCVD_IN : std_logic;\r
+ SIGNAL TRB_MISMATCH_OUT : std_logic;\r
+ SIGNAL LVL1_COUNTER_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL BUSY_RELEASE_IN : std_logic;\r
+ SIGNAL APV_TRGSEL_OUT : std_logic_vector(3 downto 0);\r
+ SIGNAL APV_TRGSTART_OUT : std_logic;\r
+ SIGNAL EDS_DATA_OUT : std_logic_vector(39 downto 0);\r
+ SIGNAL EDS_WE_OUT : std_logic;\r
+ SIGNAL EDS_START_OUT : std_logic;\r
+ SIGNAL EDS_READY_OUT : std_logic;\r
+ SIGNAL DBG_FRMCTR_OUT : std_logic_vector(3 downto 0);\r
+ SIGNAL BSM_OUT : std_logic_vector(7 downto 0);\r
+ SIGNAL DEBUG_OUT : std_logic_vector(15 downto 0);\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: real_trg_handler PORT MAP(\r
+ CLK_IN => CLK_IN,\r
+ CLEAR_IN => CLEAR_IN,\r
+ RESET_IN => RESET_IN,\r
+ TIME_TRG_IN => TIME_TRG_IN,\r
+ TRB_TRG_IN => TRB_TRG_IN,\r
+ APV_TRGDONE_IN => APV_TRGDONE_IN,\r
+ TRG_3_TODO_IN => TRG_3_TODO_IN,\r
+ TRG_2_TODO_IN => TRG_2_TODO_IN,\r
+ TRG_1_TODO_IN => TRG_1_TODO_IN,\r
+ TRG_0_TODO_IN => TRG_0_TODO_IN,\r
+ TRB_TTAG_IN => TRB_TTAG_IN,\r
+ TRB_TRND_IN => TRB_TRND_IN,\r
+ TRB_TTYPE_IN => TRB_TTYPE_IN,\r
+ TRB_TRGRCVD_IN => TRB_TRGRCVD_IN,\r
+ TRB_MISMATCH_OUT => TRB_MISMATCH_OUT,\r
+ LVL1_COUNTER_OUT => LVL1_COUNTER_OUT,\r
+ BUSY_RELEASE_IN => BUSY_RELEASE_IN,\r
+ APV_TRGSEL_OUT => APV_TRGSEL_OUT,\r
+ APV_TRGSTART_OUT => APV_TRGSTART_OUT,\r
+ EDS_DATA_OUT => EDS_DATA_OUT,\r
+ EDS_WE_OUT => EDS_WE_OUT,\r
+ EDS_START_OUT => EDS_START_OUT,\r
+ EDS_READY_OUT => EDS_READY_OUT,\r
+ DBG_FRMCTR_OUT => DBG_FRMCTR_OUT,\r
+ BSM_OUT => BSM_OUT,\r
+ DEBUG_OUT => DEBUG_OUT\r
+ );\r
+\r
+THE_CLOCK_GEN: process\r
+begin\r
+ clk_in <= '1'; wait for 5 ns;\r
+ clk_in <= '0'; wait for 5 ns;\r
+end process THE_CLOCK_GEN;\r
+\r
+THE_TEST_BENCH: process\r
+begin\r
+ -- Setup signals\r
+ clear_in <= '0'; \r
+ reset_in <= '0';\r
+ time_trg_in <= x"0"; \r
+ trb_trg_in <= x"0";\r
+ apv_trgdone_in <= '0';\r
+ trg_3_todo_in <= x"0";\r
+ trg_2_todo_in <= x"3";\r
+ trg_1_todo_in <= x"2";\r
+ trg_0_todo_in <= x"1";\r
+ trb_ttag_in <= x"dead";\r
+ trb_trnd_in <= x"fc";\r
+ trb_ttype_in <= x"1";\r
+ trb_trgrcvd_in <= '0';\r
+ busy_release_in <= '0';\r
+ -- Reset all\r
+ clear_in <= '1'; wait for 50 ns;\r
+ clear_in <= '0'; wait for 50 ns;\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ -- Tests may start here\r
+\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+\r
+ -- First sync trigger\r
+ wait until rising_edge(clk_in);\r
+ trb_trg_in <= x"8";\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ trb_trg_in <= x"0";\r
+ wait until rising_edge(clk_in);\r
+\r
+ wait for 155 ns;\r
+ wait until rising_edge(clk_in);\r
+ apv_trgdone_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ apv_trgdone_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ wait for 200 ns;\r
+ wait until rising_edge(clk_in);\r
+ trb_trgrcvd_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ wait for 300 ns;\r
+ wait until rising_edge(clk_in);\r
+ busy_release_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ busy_release_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+\r
+ wait for 100 ns;\r
+\r
+ -- Second trigger\r
+ wait until rising_edge(clk_in);\r
+ trb_trg_in <= x"1";\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ trb_trg_in <= x"0";\r
+ wait until rising_edge(clk_in);\r
+\r
+ wait for 155 ns;\r
+ wait until rising_edge(clk_in);\r
+ apv_trgdone_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ apv_trgdone_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ wait for 200 ns;\r
+ wait until rising_edge(clk_in);\r
+ trb_trgrcvd_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ wait for 300 ns;\r
+ wait until rising_edge(clk_in);\r
+ busy_release_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ busy_release_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+\r
+ wait for 100 ns;\r
+\r
+ -- Check it\r
+ wait until rising_edge(clk_in);\r
+ trb_trg_in <= x"c";\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ trb_trg_in <= x"0";\r
+ wait until rising_edge(clk_in);\r
+\r
+ wait for 155 ns;\r
+ wait until rising_edge(clk_in);\r
+ apv_trgdone_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ apv_trgdone_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ wait for 200 ns;\r
+ wait until rising_edge(clk_in);\r
+ trb_trgrcvd_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ wait for 300 ns;\r
+ wait until rising_edge(clk_in);\r
+ busy_release_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ busy_release_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+\r
+\r
+ -- Stay a while, stay forever.\r
+ wait;\r
+\r
+end process THE_TEST_BENCH;\r
+\r
+\r
+END;\r
+\r
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT reboot_handler\r
+ PORT(\r
+ RESET_IN : IN std_logic;\r
+ CLK_IN : IN std_logic;\r
+ START_IN : IN std_logic; \r
+ REBOOT_OUT : OUT std_logic;\r
+ DEBUG_OUT : OUT std_logic_vector(15 downto 0)\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL RESET_IN : std_logic;\r
+ SIGNAL CLK_IN : std_logic;\r
+ SIGNAL START_IN : std_logic;\r
+ SIGNAL REBOOT_OUT : std_logic;\r
+ SIGNAL DEBUG_OUT : std_logic_vector(15 downto 0);\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: reboot_handler PORT MAP(\r
+ RESET_IN => RESET_IN,\r
+ CLK_IN => CLK_IN,\r
+ START_IN => START_IN,\r
+ REBOOT_OUT => REBOOT_OUT,\r
+ DEBUG_OUT => DEBUG_OUT\r
+ );\r
+\r
+THE_CLOCK_GEN: process\r
+begin\r
+ clk_in <= '1'; wait for 5 ns;\r
+ clk_in <= '0'; wait for 5 ns;\r
+end process THE_CLOCK_GEN;\r
+\r
+THE_TEST_BENCH: process\r
+begin\r
+ -- Setup signals\r
+ reset_in <= '0';\r
+ start_in <= '0';\r
+ \r
+ -- Sync reset\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait for 140 ns;\r
+ \r
+ -- Tests may start now\r
+ wait until rising_edge(clk_in);\r
+ start_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ start_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ \r
+\r
+\r
+ -- Stay a while, stay forever....\r
+ wait;\r
+end process THE_TEST_BENCH; \r
+\r
+END;\r
+\r
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT reset_handler\r
+ PORT(\r
+ CLEAR_IN : IN std_logic;\r
+ RESET_IN : IN std_logic;\r
+ CLK_IN : IN std_logic;\r
+ TRB_RESET_IN : IN std_logic; \r
+ RESET_OUT : OUT std_logic;\r
+ DEBUG_OUT : OUT std_logic_vector(15 downto 0)\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL CLEAR_IN : std_logic;\r
+ SIGNAL RESET_IN : std_logic;\r
+ SIGNAL CLK_IN : std_logic;\r
+ SIGNAL TRB_RESET_IN : std_logic;\r
+ SIGNAL RESET_OUT : std_logic;\r
+ SIGNAL DEBUG_OUT : std_logic_vector(15 downto 0);\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: reset_handler PORT MAP(\r
+ CLEAR_IN => CLEAR_IN,\r
+ RESET_IN => RESET_IN,\r
+ CLK_IN => CLK_IN,\r
+ TRB_RESET_IN => TRB_RESET_IN,\r
+ RESET_OUT => RESET_OUT,\r
+ DEBUG_OUT => DEBUG_OUT\r
+ );\r
+\r
+\r
+THE_CLOCK_GEN: process\r
+begin\r
+ clk_in <= '1'; wait for 5 ns;\r
+ clk_in <= '0'; wait for 5 ns;\r
+end process THE_CLOCK_GEN;\r
+\r
+THE_TEST_BENCH: process\r
+begin\r
+ -- Setup signals\r
+ clear_in <= '1';\r
+ reset_in <= '0';\r
+ trb_reset_in <= '0';\r
+ \r
+ \r
+ -- Tests may start now\r
+ wait for 300 ns;\r
+ wait until rising_edge(clk_in);\r
+\r
+ wait for 3.33 ns;\r
+ clear_in <= '0'; \r
+\r
+ wait for 2 us;\r
+\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+\r
+ wait for 2 us;\r
+\r
+ -- Stay a while, stay forever....\r
+ wait;\r
+end process THE_TEST_BENCH; \r
+\r
+END;\r
+\r
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT slv_adc_la\r
+ PORT(\r
+ CLK_IN : IN std_logic;\r
+ RESET_IN : IN std_logic;\r
+ SLV_ADDR_IN : IN std_logic_vector(9 downto 0);\r
+ SLV_READ_IN : IN std_logic;\r
+ SLV_WRITE_IN : IN std_logic;\r
+ SLV_DATA_IN : IN std_logic_vector(31 downto 0);\r
+ ADC_CLK_IN : IN std_logic;\r
+ ADC_DATA_IN : IN std_logic_vector(11 downto 0); \r
+ SLV_ACK_OUT : OUT std_logic;\r
+ SLV_DATA_OUT : OUT std_logic_vector(31 downto 0);\r
+ ADC_SEL_OUT : OUT std_logic_vector(2 downto 0);\r
+ STAT : OUT std_logic_vector(31 downto 0)\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL CLK_IN : std_logic;\r
+ SIGNAL RESET_IN : std_logic;\r
+ SIGNAL SLV_ADDR_IN : std_logic_vector(9 downto 0);\r
+ SIGNAL SLV_READ_IN : std_logic;\r
+ SIGNAL SLV_WRITE_IN : std_logic;\r
+ SIGNAL SLV_ACK_OUT : std_logic;\r
+ SIGNAL SLV_DATA_IN : std_logic_vector(31 downto 0);\r
+ SIGNAL SLV_DATA_OUT : std_logic_vector(31 downto 0);\r
+ SIGNAL ADC_SEL_OUT : std_logic_vector(2 downto 0);\r
+ SIGNAL ADC_CLK_IN : std_logic;\r
+ SIGNAL ADC_DATA_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL STAT : std_logic_vector(31 downto 0);\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: slv_adc_la PORT MAP(\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ SLV_ADDR_IN => SLV_ADDR_IN,\r
+ SLV_READ_IN => SLV_READ_IN,\r
+ SLV_WRITE_IN => SLV_WRITE_IN,\r
+ SLV_ACK_OUT => SLV_ACK_OUT,\r
+ SLV_DATA_IN => SLV_DATA_IN,\r
+ SLV_DATA_OUT => SLV_DATA_OUT,\r
+ ADC_SEL_OUT => ADC_SEL_OUT,\r
+ ADC_CLK_IN => ADC_CLK_IN,\r
+ ADC_DATA_IN => ADC_DATA_IN,\r
+ STAT => STAT\r
+ );\r
+\r
+\r
+THE_CLOCK_GEN: process\r
+begin\r
+ clk_in <= '1'; wait for 5 ns;\r
+ clk_in <= '0'; wait for 5 ns;\r
+end process THE_CLOCK_GEN;\r
+\r
+THE_ADC_CLOCK_GEN: process\r
+begin\r
+ adc_clk_in <= '1'; wait for 12.5 ns;\r
+ adc_clk_in <= '0'; wait for 12.5 ns;\r
+end process THE_ADC_CLOCK_GEN;\r
+\r
+\r
+THE_TEST_BENCH: process\r
+begin\r
+ -- Setup signals\r
+ reset_in <= '0';\r
+ slv_addr_in <= b"00_0000_0000";\r
+ slv_read_in <= '0';\r
+ slv_write_in <= '0';\r
+ slv_data_in <= x"0000_0000";\r
+ wait for 100 ns;\r
+\r
+ -- Reset all\r
+ reset_in <= '1';\r
+ wait for 100 ns;\r
+ reset_in <= '0';\r
+ wait for 400 ns;\r
+\r
+ -- Tests may start now\r
+ \r
+ -- stay a while.... stay forever!!!\r
+ wait;\r
+end process THE_TEST_BENCH;\r
+\r
+END;\r
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT slv_adc_snoop\r
+ PORT(\r
+ CLK_IN : IN std_logic;\r
+ RESET_IN : IN std_logic;\r
+ SLV_ADDR_IN : IN std_logic_vector(9 downto 0);\r
+ SLV_READ_IN : IN std_logic;\r
+ SLV_WRITE_IN : IN std_logic;\r
+ SLV_DATA_IN : IN std_logic_vector(31 downto 0);\r
+ ADC_CLK_IN : IN std_logic;\r
+ ADC_DATA_IN : IN std_logic_vector(11 downto 0); \r
+ SLV_ACK_OUT : OUT std_logic;\r
+ SLV_DATA_OUT : OUT std_logic_vector(31 downto 0);\r
+ ADC_SEL_OUT : OUT std_logic_vector(2 downto 0);\r
+ STAT : OUT std_logic_vector(31 downto 0)\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL CLK_IN : std_logic;\r
+ SIGNAL RESET_IN : std_logic;\r
+ SIGNAL SLV_ADDR_IN : std_logic_vector(9 downto 0);\r
+ SIGNAL SLV_READ_IN : std_logic;\r
+ SIGNAL SLV_WRITE_IN : std_logic;\r
+ SIGNAL SLV_ACK_OUT : std_logic;\r
+ SIGNAL SLV_DATA_IN : std_logic_vector(31 downto 0);\r
+ SIGNAL SLV_DATA_OUT : std_logic_vector(31 downto 0);\r
+ SIGNAL ADC_SEL_OUT : std_logic_vector(2 downto 0);\r
+ SIGNAL ADC_CLK_IN : std_logic;\r
+ SIGNAL ADC_DATA_IN : std_logic_vector(11 downto 0);\r
+ SIGNAL STAT : std_logic_vector(31 downto 0);\r
+\r
+ signal adc_real : std_logic_vector(11 downto 0);\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: slv_adc_snoop PORT MAP(\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ SLV_ADDR_IN => SLV_ADDR_IN,\r
+ SLV_READ_IN => SLV_READ_IN,\r
+ SLV_WRITE_IN => SLV_WRITE_IN,\r
+ SLV_ACK_OUT => SLV_ACK_OUT,\r
+ SLV_DATA_IN => SLV_DATA_IN,\r
+ SLV_DATA_OUT => SLV_DATA_OUT,\r
+ ADC_SEL_OUT => ADC_SEL_OUT,\r
+ ADC_CLK_IN => ADC_CLK_IN,\r
+ ADC_DATA_IN => ADC_DATA_IN,\r
+ STAT => STAT\r
+ );\r
+\r
+THE_CLOCK_GEN: process\r
+begin\r
+ clk_in <= '1'; wait for 5 ns;\r
+ clk_in <= '0'; wait for 5 ns;\r
+end process THE_CLOCK_GEN;\r
+\r
+THE_ADC_CLK_GEN: process\r
+begin\r
+ adc_clk_in <= '1'; wait for 12 ns;\r
+ adc_clk_in <= '0'; wait for 12 ns;\r
+end process THE_ADC_CLK_GEN;\r
+\r
+BLA: process\r
+variable adc_data : unsigned(11 downto 0) := x"000";\r
+begin\r
+ adc_real <= std_logic_vector(adc_data);\r
+ wait until rising_edge(adc_clk_in);\r
+ adc_data_in <= adc_real;\r
+ adc_data := adc_data + 1;\r
+end process BLA;\r
+\r
+THE_TEST_BENCH: process\r
+variable addr : unsigned(9 downto 0) := b"00_0000_0000";\r
+begin\r
+ -- Setup signals\r
+ reset_in <= '0';\r
+ slv_read_in <= '0';\r
+ slv_write_in <= '0';\r
+ slv_data_in <= x"0000_0000";\r
+ slv_addr_in <= b"00_0000_0000";\r
+\r
+ -- Reset the whole bunch\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- Tests may start now\r
+\r
+ -- One write access\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= b"00_0000_0000";\r
+ slv_data_in <= x"0000_4000";\r
+ slv_write_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_write_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ wait for 500 ns;\r
+\r
+ -- One read access\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= b"00_0000_0000";\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ wait for 500 ns;\r
+\r
+ -- One read access\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= b"00_0000_0000";\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ wait for 500 ns;\r
+\r
+ -- One read access\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= b"00_0000_0000";\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ wait for 500 ns;\r
+\r
+ -- One read access\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= b"00_0000_0000";\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ wait for 500 ns;\r
+\r
+ -- One read access\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= b"00_0000_0000";\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ wait for 500 ns;\r
+\r
+ -- One read access\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= b"00_0000_0000";\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ wait for 500 ns;\r
+\r
+ -- Stop the sampling\r
+ -- One write access\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= b"00_0000_0000";\r
+ slv_data_in <= x"0000_0000";\r
+ slv_write_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_write_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- One read access\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= b"00_0000_0000";\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- get last written address\r
+ -- One read access\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= b"00_0000_0000";\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+\r
+ addr := unsigned(slv_data_out(25 downto 16));\r
+ addr := addr + 1;\r
+ \r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- read back the whole stuff\r
+ READ_LOOP: for I in 0 to 1023 loop\r
+ -- One read access\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= std_logic_vector(addr); --b"00_0000_0000";\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ addr := addr + 1;\r
+ end loop READ_LOOP;\r
+\r
+\r
+ -- Stay a while, stay forever!\r
+ wait;\r
+end process THE_TEST_BENCH;\r
+\r
+\r
+END;\r
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT slv_onewire_memory\r
+ PORT(\r
+ CLK_IN : IN std_logic;\r
+ RESET_IN : IN std_logic;\r
+ SLV_ADDR_IN : IN std_logic_vector(5 downto 0);\r
+ SLV_READ_IN : IN std_logic;\r
+ SLV_WRITE_IN : IN std_logic;\r
+ BACKPLANE_IN : IN std_logic_vector(2 downto 0);\r
+ ONEWIRE_START_IN : IN std_logic; \r
+ ONEWIRE_INOUT : INOUT std_logic_vector(15 downto 0); \r
+ BP_ONEWIRE_INOUT : INOUT std_logic; \r
+ SLV_ACK_OUT : OUT std_logic;\r
+ SLV_BUSY_OUT : OUT std_logic;\r
+ SLV_DATA_OUT : OUT std_logic_vector(31 downto 0);\r
+ STAT : OUT std_logic_vector(63 downto 0)\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL CLK_IN : std_logic;\r
+ SIGNAL RESET_IN : std_logic;\r
+ SIGNAL SLV_ADDR_IN : std_logic_vector(5 downto 0);\r
+ SIGNAL SLV_READ_IN : std_logic;\r
+ SIGNAL SLV_WRITE_IN : std_logic;\r
+ SIGNAL BACKPLANE_IN : std_logic_vector(2 downto 0);\r
+ SIGNAL SLV_ACK_OUT : std_logic;\r
+ SIGNAL SLV_BUSY_OUT : std_logic;\r
+ SIGNAL SLV_DATA_OUT : std_logic_vector(31 downto 0);\r
+ SIGNAL ONEWIRE_START_IN : std_logic;\r
+ SIGNAL ONEWIRE_INOUT : std_logic_vector(15 downto 0);\r
+ SIGNAL BP_ONEWIRE_INOUT : std_logic; \r
+ SIGNAL STAT : std_logic_vector(63 downto 0);\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: slv_onewire_memory PORT MAP(\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ SLV_ADDR_IN => SLV_ADDR_IN,\r
+ SLV_READ_IN => SLV_READ_IN,\r
+ SLV_WRITE_IN => SLV_WRITE_IN,\r
+ BACKPLANE_IN => BACKPLANE_IN,\r
+ SLV_ACK_OUT => SLV_ACK_OUT,\r
+ SLV_DATA_OUT => SLV_DATA_OUT,\r
+ SLV_BUSY_OUT => SLV_BUSY_OUT,\r
+ ONEWIRE_START_IN => ONEWIRE_START_IN,\r
+ ONEWIRE_INOUT => ONEWIRE_INOUT,\r
+ BP_ONEWIRE_INOUT => BP_ONEWIRE_INOUT,\r
+ STAT => STAT\r
+ );\r
+\r
+CLK_GEN_PROC: process\r
+begin\r
+ clk_in <= '1'; wait for 5 ns;\r
+ clk_in <= '0'; wait for 5 ns;\r
+end process CLK_GEN_PROC;\r
+\r
+THE_TESTBENCH: process\r
+begin\r
+ -- Setup signals\r
+ reset_in <= '0';\r
+ slv_addr_in <= (others => '0');\r
+ backplane_in <= b"000";\r
+ slv_read_in <= '0';\r
+ slv_write_in <= '0';\r
+ onewire_start_in <= '0';\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ \r
+ -- Do a reset\r
+ wait for 50 ns;\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- Tests may start here\r
+\r
+ -- Start one cycle\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ slv_write_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_write_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- 1Wire access\r
+ -- wait for reset pulse (READ_ID)\r
+ wait until falling_edge(onewire_inout(0));\r
+ wait until rising_edge(onewire_inout(0));\r
+ wait for 30 us;\r
+ onewire_inout <= b"0000_0000_0000_0000";\r
+ bp_onewire_inout <= '0';\r
+ wait for 120 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+\r
+ -- skip the command sequence\r
+ wait until falling_edge(onewire_inout(0));\r
+ wait until falling_edge(onewire_inout(0));\r
+ wait until falling_edge(onewire_inout(0));\r
+ wait until falling_edge(onewire_inout(0));\r
+ wait until falling_edge(onewire_inout(0));\r
+ wait until falling_edge(onewire_inout(0));\r
+ wait until falling_edge(onewire_inout(0));\r
+ wait until falling_edge(onewire_inout(0));\r
+\r
+ -- serial number\r
+ -- bit 0\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"fe80";\r
+ bp_onewire_inout <= '1';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 1\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"ef71";\r
+ bp_onewire_inout <= '0';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 2\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"d062";\r
+ bp_onewire_inout <= '0';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 3\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"c153";\r
+ bp_onewire_inout <= '0';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 4\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"b244";\r
+ bp_onewire_inout <= '0';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 5\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"a335";\r
+ bp_onewire_inout <= '1';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 6\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"9426";\r
+ bp_onewire_inout <= '0';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 7\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"8517";\r
+ bp_onewire_inout <= '0';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 8\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"7608";\r
+ bp_onewire_inout <= '1';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 9\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"67f9";\r
+ bp_onewire_inout <= '1';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 10\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"58ea";\r
+ bp_onewire_inout <= '0';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 11\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"49db";\r
+ bp_onewire_inout <= '0';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 12\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"3acc";\r
+ bp_onewire_inout <= '0';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 13\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"2bbd";\r
+ bp_onewire_inout <= '0';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 14\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"1cae";\r
+ bp_onewire_inout <= '1';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 15\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"0d9f";\r
+ bp_onewire_inout <= '0';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+\r
+ -- bit 16\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"dead";\r
+ bp_onewire_inout <= '1';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 17\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"beef";\r
+ bp_onewire_inout <= '0';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 18\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"affe";\r
+ bp_onewire_inout <= '1';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 19\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"d00f";\r
+ bp_onewire_inout <= '0';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 20\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"facc";\r
+ bp_onewire_inout <= '0';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 21\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"0123";\r
+ bp_onewire_inout <= '1';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 22\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"4567";\r
+ bp_onewire_inout <= '1';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 23\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"89ab";\r
+ bp_onewire_inout <= '0';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 24\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"cdef";\r
+ bp_onewire_inout <= '1';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 25\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"aaaa";\r
+ bp_onewire_inout <= '1';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 26\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"5555";\r
+ bp_onewire_inout <= '1';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 27\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"6271";\r
+ bp_onewire_inout <= '0';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 28\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"4711";\r
+ bp_onewire_inout <= '0';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 29\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"0666";\r
+ bp_onewire_inout <= '0';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 30\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"7550";\r
+ bp_onewire_inout <= '0';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 31\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"bacc";\r
+ bp_onewire_inout <= '1';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+\r
+ -- bit 32\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"0123";\r
+ bp_onewire_inout <= 'H';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 33\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"4567";\r
+ bp_onewire_inout <= 'H';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 34\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"89ab";\r
+ bp_onewire_inout <= 'H';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 35\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"cdef";\r
+ bp_onewire_inout <= 'H';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 36\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"0f1e";\r
+ bp_onewire_inout <= 'H';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 37\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"2d3c";\r
+ bp_onewire_inout <= 'H';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 38\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"4b5a";\r
+ bp_onewire_inout <= 'H';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 39\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"6978";\r
+ bp_onewire_inout <= 'H';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 40\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"8796";\r
+ bp_onewire_inout <= 'H';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 41\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"a5b4";\r
+ bp_onewire_inout <= 'H';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 42\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"c3d2";\r
+ bp_onewire_inout <= 'H';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 43\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"e1f0";\r
+ bp_onewire_inout <= 'H';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 44\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"fedc";\r
+ bp_onewire_inout <= 'H';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 45\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"ba98";\r
+ bp_onewire_inout <= 'H';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 46\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"7654";\r
+ bp_onewire_inout <= 'H';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 47\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"3210";\r
+ bp_onewire_inout <= 'H';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+\r
+ -- bit 48\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"fffe";\r
+ bp_onewire_inout <= 'H';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 49\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"fffd";\r
+ bp_onewire_inout <= 'H';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 50\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"fffb";\r
+ bp_onewire_inout <= 'H';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 51\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"fff7";\r
+ bp_onewire_inout <= 'H';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 52\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"ffef";\r
+ bp_onewire_inout <= 'H';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 53\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"ffdf";\r
+ bp_onewire_inout <= 'H';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 54\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"ffbf";\r
+ bp_onewire_inout <= 'H';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 55\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"ff7f";\r
+ bp_onewire_inout <= 'H';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 56\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"feff";\r
+ bp_onewire_inout <= 'H';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 57\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"fdff";\r
+ bp_onewire_inout <= 'H';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 58\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"fbff";\r
+ bp_onewire_inout <= 'H';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 59\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"f7ff";\r
+ bp_onewire_inout <= 'H';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 60\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"efff";\r
+ bp_onewire_inout <= 'H';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 61\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"dfff";\r
+ bp_onewire_inout <= 'H';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 62\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"bfff";\r
+ bp_onewire_inout <= 'H';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 63\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"7fff";\r
+ bp_onewire_inout <= 'H';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+\r
+ -- wait for reset pulse (CONV_TEMP)\r
+ wait until falling_edge(onewire_inout(0));\r
+ wait until rising_edge(onewire_inout(0));\r
+ wait for 30 us;\r
+ onewire_inout <= b"0000_0000_0000_0000";\r
+ bp_onewire_inout <= '0';\r
+ wait for 120 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+\r
+ -- skip the command sequence\r
+ wait until falling_edge(onewire_inout(0));\r
+ wait until falling_edge(onewire_inout(0));\r
+ wait until falling_edge(onewire_inout(0));\r
+ wait until falling_edge(onewire_inout(0));\r
+ wait until falling_edge(onewire_inout(0));\r
+ wait until falling_edge(onewire_inout(0));\r
+ wait until falling_edge(onewire_inout(0));\r
+ wait until falling_edge(onewire_inout(0));\r
+\r
+ wait until falling_edge(onewire_inout(0));\r
+ wait until falling_edge(onewire_inout(0));\r
+ wait until falling_edge(onewire_inout(0));\r
+ wait until falling_edge(onewire_inout(0));\r
+ wait until falling_edge(onewire_inout(0));\r
+ wait until falling_edge(onewire_inout(0));\r
+ wait until falling_edge(onewire_inout(0));\r
+ wait until falling_edge(onewire_inout(0));\r
+\r
+ -- wait for reset pulse (READ_TEMP)\r
+ wait until falling_edge(onewire_inout(0));\r
+ wait until rising_edge(onewire_inout(0));\r
+ wait for 30 us;\r
+ onewire_inout <= b"0000_0000_0000_0000";\r
+ bp_onewire_inout <= '0';\r
+ wait for 120 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+\r
+ -- skip the command sequence\r
+ wait until falling_edge(onewire_inout(0));\r
+ wait until falling_edge(onewire_inout(0));\r
+ wait until falling_edge(onewire_inout(0));\r
+ wait until falling_edge(onewire_inout(0));\r
+ wait until falling_edge(onewire_inout(0));\r
+ wait until falling_edge(onewire_inout(0));\r
+ wait until falling_edge(onewire_inout(0));\r
+ wait until falling_edge(onewire_inout(0));\r
+\r
+ wait until falling_edge(onewire_inout(0));\r
+ wait until falling_edge(onewire_inout(0));\r
+ wait until falling_edge(onewire_inout(0));\r
+ wait until falling_edge(onewire_inout(0));\r
+ wait until falling_edge(onewire_inout(0));\r
+ wait until falling_edge(onewire_inout(0));\r
+ wait until falling_edge(onewire_inout(0));\r
+ wait until falling_edge(onewire_inout(0));\r
+\r
+ -- temparature\r
+ -- bit 0\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"4001";\r
+ bp_onewire_inout <= 'H';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 1\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"5002";\r
+ bp_onewire_inout <= 'H';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 2\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"6004";\r
+ bp_onewire_inout <= 'H';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 3\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"7008";\r
+ bp_onewire_inout <= 'H';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 4\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"8010";\r
+ bp_onewire_inout <= 'H';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 5\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"9020";\r
+ bp_onewire_inout <= 'H';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 6\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"a040";\r
+ bp_onewire_inout <= 'H';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 7\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"b080";\r
+ bp_onewire_inout <= 'H';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 8\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"c100";\r
+ bp_onewire_inout <= 'H';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 9\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"d200";\r
+ bp_onewire_inout <= 'H';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 10\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"e400";\r
+ bp_onewire_inout <= 'H';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+ -- bit 11\r
+ wait until falling_edge(onewire_inout(0));\r
+ onewire_inout <= x"f800";\r
+ bp_onewire_inout <= 'H';\r
+ wait for 30 us;\r
+ onewire_inout <= (others => 'H');\r
+ bp_onewire_inout <= 'H';\r
+\r
+\r
+ -- wait for end of 1Wire access\r
+ wait until falling_edge(slv_busy_out);\r
+ wait for 100 ns;\r
+\r
+ -- 1Wire 0\r
+ -- read one address\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= b"00_0000";\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- read one address\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= b"00_0001";\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- read one address\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= b"00_0010";\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- read one address\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= b"00_0011";\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- 1Wire 1\r
+ -- read one address\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= b"00_0100";\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- read one address\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= b"00_0101";\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- read one address\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= b"00_0110";\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- read one address\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= b"00_0111";\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- 1Wire 1\r
+ -- read one address\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= b"00_1000";\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- read one address\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= b"00_1001";\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- read one address\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= b"00_1010";\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- read one address\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= b"00_1011";\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- 1Wire 3\r
+ -- read one address\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= b"00_1100";\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- read one address\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= b"00_1101";\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- read one address\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= b"00_1110";\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- read one address\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= b"00_1111";\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+\r
+\r
+\r
+ -- 1Wire 15\r
+ -- read one address\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= b"11_1100";\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- read one address\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= b"11_1101";\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- read one address\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= b"11_1110";\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- read one address\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= b"11_1111";\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- Do a write\r
+ \r
+ -- Stay a while, stay forever!\r
+ wait;\r
+end process THE_TESTBENCH;\r
+\r
+\r
+\r
+END;\r
+\r
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT slv_ped_thr_mem\r
+ PORT(\r
+ CLK_IN : IN std_logic;\r
+ RESET_IN : IN std_logic;\r
+ SLV_ADDR_IN : IN std_logic_vector(10 downto 0);\r
+ SLV_READ_IN : IN std_logic;\r
+ SLV_WRITE_IN : IN std_logic;\r
+ SLV_DATA_IN : IN std_logic_vector(31 downto 0);\r
+ BACKPLANE_IN : IN std_logic_vector(2 downto 0);\r
+ MEM_CLK_IN : IN std_logic;\r
+ MEM_ADDR_IN : IN std_logic_vector(6 downto 0); \r
+ SLV_ACK_OUT : OUT std_logic;\r
+ SLV_DATA_OUT : OUT std_logic_vector(31 downto 0);\r
+ MEM_0_D_OUT : OUT std_logic_vector(17 downto 0);\r
+ MEM_1_D_OUT : OUT std_logic_vector(17 downto 0);\r
+ MEM_2_D_OUT : OUT std_logic_vector(17 downto 0);\r
+ MEM_3_D_OUT : OUT std_logic_vector(17 downto 0);\r
+ MEM_4_D_OUT : OUT std_logic_vector(17 downto 0);\r
+ MEM_5_D_OUT : OUT std_logic_vector(17 downto 0);\r
+ MEM_6_D_OUT : OUT std_logic_vector(17 downto 0);\r
+ MEM_7_D_OUT : OUT std_logic_vector(17 downto 0);\r
+ MEM_8_D_OUT : OUT std_logic_vector(17 downto 0);\r
+ MEM_9_D_OUT : OUT std_logic_vector(17 downto 0);\r
+ MEM_10_D_OUT : OUT std_logic_vector(17 downto 0);\r
+ MEM_11_D_OUT : OUT std_logic_vector(17 downto 0);\r
+ MEM_12_D_OUT : OUT std_logic_vector(17 downto 0);\r
+ MEM_13_D_OUT : OUT std_logic_vector(17 downto 0);\r
+ MEM_14_D_OUT : OUT std_logic_vector(17 downto 0);\r
+ MEM_15_D_OUT : OUT std_logic_vector(17 downto 0);\r
+ STAT : OUT std_logic_vector(31 downto 0)\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL CLK_IN : std_logic;\r
+ SIGNAL RESET_IN : std_logic;\r
+ SIGNAL SLV_ADDR_IN : std_logic_vector(10 downto 0);\r
+ SIGNAL SLV_READ_IN : std_logic;\r
+ SIGNAL SLV_WRITE_IN : std_logic;\r
+ SIGNAL SLV_ACK_OUT : std_logic;\r
+ SIGNAL SLV_DATA_IN : std_logic_vector(31 downto 0);\r
+ SIGNAL SLV_DATA_OUT : std_logic_vector(31 downto 0);\r
+ SIGNAL BACKPLANE_IN : std_logic_vector(2 downto 0);\r
+ SIGNAL MEM_CLK_IN : std_logic;\r
+ SIGNAL MEM_ADDR_IN : std_logic_vector(6 downto 0);\r
+ SIGNAL MEM_0_D_OUT : std_logic_vector(17 downto 0);\r
+ SIGNAL MEM_1_D_OUT : std_logic_vector(17 downto 0);\r
+ SIGNAL MEM_2_D_OUT : std_logic_vector(17 downto 0);\r
+ SIGNAL MEM_3_D_OUT : std_logic_vector(17 downto 0);\r
+ SIGNAL MEM_4_D_OUT : std_logic_vector(17 downto 0);\r
+ SIGNAL MEM_5_D_OUT : std_logic_vector(17 downto 0);\r
+ SIGNAL MEM_6_D_OUT : std_logic_vector(17 downto 0);\r
+ SIGNAL MEM_7_D_OUT : std_logic_vector(17 downto 0);\r
+ SIGNAL MEM_8_D_OUT : std_logic_vector(17 downto 0);\r
+ SIGNAL MEM_9_D_OUT : std_logic_vector(17 downto 0);\r
+ SIGNAL MEM_10_D_OUT : std_logic_vector(17 downto 0);\r
+ SIGNAL MEM_11_D_OUT : std_logic_vector(17 downto 0);\r
+ SIGNAL MEM_12_D_OUT : std_logic_vector(17 downto 0);\r
+ SIGNAL MEM_13_D_OUT : std_logic_vector(17 downto 0);\r
+ SIGNAL MEM_14_D_OUT : std_logic_vector(17 downto 0);\r
+ SIGNAL MEM_15_D_OUT : std_logic_vector(17 downto 0);\r
+ SIGNAL STAT : std_logic_vector(31 downto 0);\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: slv_ped_thr_mem PORT MAP(\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ SLV_ADDR_IN => SLV_ADDR_IN,\r
+ SLV_READ_IN => SLV_READ_IN,\r
+ SLV_WRITE_IN => SLV_WRITE_IN,\r
+ SLV_ACK_OUT => SLV_ACK_OUT,\r
+ SLV_DATA_IN => SLV_DATA_IN,\r
+ SLV_DATA_OUT => SLV_DATA_OUT,\r
+ BACKPLANE_IN => BACKPLANE_IN,\r
+ MEM_CLK_IN => MEM_CLK_IN,\r
+ MEM_ADDR_IN => MEM_ADDR_IN,\r
+ MEM_0_D_OUT => MEM_0_D_OUT,\r
+ MEM_1_D_OUT => MEM_1_D_OUT,\r
+ MEM_2_D_OUT => MEM_2_D_OUT,\r
+ MEM_3_D_OUT => MEM_3_D_OUT,\r
+ MEM_4_D_OUT => MEM_4_D_OUT,\r
+ MEM_5_D_OUT => MEM_5_D_OUT,\r
+ MEM_6_D_OUT => MEM_6_D_OUT,\r
+ MEM_7_D_OUT => MEM_7_D_OUT,\r
+ MEM_8_D_OUT => MEM_8_D_OUT,\r
+ MEM_9_D_OUT => MEM_9_D_OUT,\r
+ MEM_10_D_OUT => MEM_10_D_OUT,\r
+ MEM_11_D_OUT => MEM_11_D_OUT,\r
+ MEM_12_D_OUT => MEM_12_D_OUT,\r
+ MEM_13_D_OUT => MEM_13_D_OUT,\r
+ MEM_14_D_OUT => MEM_14_D_OUT,\r
+ MEM_15_D_OUT => MEM_15_D_OUT,\r
+ STAT => STAT\r
+ );\r
+\r
+THE_CLOCK_GEN: process\r
+begin\r
+ clk_in <= '1'; mem_clk_in <= '1'; wait for 5 ns;\r
+ clk_in <= '0'; mem_clk_in <= '0'; wait for 5 ns;\r
+end process THE_CLOCK_GEN;\r
+\r
+THE_TEST_BENCH: process\r
+begin\r
+ -- Setup signals\r
+ reset_in <= '0';\r
+ slv_read_in <= '0';\r
+ slv_write_in <= '0';\r
+ slv_data_in <= x"0000_0000";\r
+ slv_addr_in <= b"111_1111_1111";\r
+ backplane_in <= b"001";\r
+ mem_addr_in <= b"000_0000";\r
+\r
+ -- Reset the whole bunch\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ \r
+ \r
+ -- Tests may start now\r
+\r
+ -- One write access\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= b"000_0000_0000";\r
+ slv_data_in <= x"0000_dead";\r
+ slv_write_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_write_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- One write access\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= b"000_0000_0001";\r
+ slv_data_in <= x"0000_beef";\r
+ slv_write_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_write_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- One write access\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= b"000_0000_0010";\r
+ slv_data_in <= x"0000_affe";\r
+ slv_write_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_write_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- One write access\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= b"000_0000_0011";\r
+ slv_data_in <= x"0000_d00f";\r
+ slv_write_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_write_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- One read access\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= b"000_0000_0000";\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- One read access\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= b"000_0000_0001";\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- One read access\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= b"000_0000_0010";\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- One read access\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= b"000_0000_0011";\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+\r
+\r
+ -- Stay a while, stay forever....\r
+ wait;\r
+end process THE_TEST_BENCH; \r
+\r
+END;\r
+\r
--- /dev/null
+\r
+-- VHDL Test Bench Created from source file slv_register_bank.vhd -- 07-MAY-2008 01:09:40\r
+--\r
+-- Notes: \r
+-- 1) This testbench template has been automatically generated using types\r
+-- std_logic and std_logic_vector for the ports of the unit under test.\r
+-- Lattice recommends that these types always be used for the top-level\r
+-- I/O of a design in order to guarantee that the testbench will bind\r
+-- correctly to the timing (post-route) simulation model.\r
+-- 2) To use this template as your testbench, change the filename to any\r
+-- name of your choice with the extension .vhd, and use the "source->import"\r
+-- menu in the ispLEVER Project Navigator to import the testbench.\r
+-- Then edit the user defined section below, adding code to generate the \r
+-- stimulus for your design.\r
+-- 3) VHDL simulations will produce errors if there are Lattice FPGA library \r
+-- elements in your design that require the instantiation of GSR, PUR, and\r
+-- TSALL and they are not present in the testbench. For more information see\r
+-- the How To section of online help. \r
+--\r
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT slv_register_bank\r
+ PORT(\r
+ CLK_IN : IN std_logic;\r
+ RESET_IN : IN std_logic;\r
+ SLV_ADDR_IN : IN std_logic_vector(3 downto 0);\r
+ SLV_READ_IN : IN std_logic;\r
+ SLV_WRITE_IN : IN std_logic;\r
+ SLV_DATA_IN : IN std_logic_vector(31 downto 0);\r
+ BACKPLANE_IN : IN std_logic_vector(2 downto 0);\r
+ STAT_0_IN : IN std_logic_vector(15 downto 0);\r
+ STAT_1_IN : IN std_logic_vector(15 downto 0);\r
+ STAT_2_IN : IN std_logic_vector(15 downto 0);\r
+ STAT_3_IN : IN std_logic_vector(15 downto 0);\r
+ STAT_4_IN : IN std_logic_vector(15 downto 0);\r
+ STAT_5_IN : IN std_logic_vector(15 downto 0);\r
+ STAT_6_IN : IN std_logic_vector(15 downto 0);\r
+ STAT_7_IN : IN std_logic_vector(15 downto 0);\r
+ STAT_8_IN : IN std_logic_vector(15 downto 0);\r
+ STAT_9_IN : IN std_logic_vector(15 downto 0);\r
+ STAT_10_IN : IN std_logic_vector(15 downto 0);\r
+ STAT_11_IN : IN std_logic_vector(15 downto 0);\r
+ STAT_12_IN : IN std_logic_vector(15 downto 0);\r
+ STAT_13_IN : IN std_logic_vector(15 downto 0);\r
+ STAT_14_IN : IN std_logic_vector(15 downto 0);\r
+ STAT_15_IN : IN std_logic_vector(15 downto 0); \r
+ SLV_ACK_OUT : OUT std_logic;\r
+ SLV_DATA_OUT : OUT std_logic_vector(31 downto 0);\r
+ CTRL_0_OUT : OUT std_logic_vector(15 downto 0);\r
+ CTRL_1_OUT : OUT std_logic_vector(15 downto 0);\r
+ CTRL_2_OUT : OUT std_logic_vector(15 downto 0);\r
+ CTRL_3_OUT : OUT std_logic_vector(15 downto 0);\r
+ CTRL_4_OUT : OUT std_logic_vector(15 downto 0);\r
+ CTRL_5_OUT : OUT std_logic_vector(15 downto 0);\r
+ CTRL_6_OUT : OUT std_logic_vector(15 downto 0);\r
+ CTRL_7_OUT : OUT std_logic_vector(15 downto 0);\r
+ CTRL_8_OUT : OUT std_logic_vector(15 downto 0);\r
+ CTRL_9_OUT : OUT std_logic_vector(15 downto 0);\r
+ CTRL_10_OUT : OUT std_logic_vector(15 downto 0);\r
+ CTRL_11_OUT : OUT std_logic_vector(15 downto 0);\r
+ CTRL_12_OUT : OUT std_logic_vector(15 downto 0);\r
+ CTRL_13_OUT : OUT std_logic_vector(15 downto 0);\r
+ CTRL_14_OUT : OUT std_logic_vector(15 downto 0);\r
+ CTRL_15_OUT : OUT std_logic_vector(15 downto 0);\r
+ STAT : OUT std_logic_vector(31 downto 0)\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL CLK_IN : std_logic;\r
+ SIGNAL RESET_IN : std_logic;\r
+ SIGNAL SLV_ADDR_IN : std_logic_vector(3 downto 0);\r
+ SIGNAL SLV_READ_IN : std_logic;\r
+ SIGNAL SLV_WRITE_IN : std_logic;\r
+ SIGNAL SLV_ACK_OUT : std_logic;\r
+ SIGNAL SLV_DATA_IN : std_logic_vector(31 downto 0);\r
+ SIGNAL SLV_DATA_OUT : std_logic_vector(31 downto 0);\r
+ SIGNAL BACKPLANE_IN : std_logic_vector(2 downto 0);\r
+ SIGNAL CTRL_0_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL CTRL_1_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL CTRL_2_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL CTRL_3_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL CTRL_4_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL CTRL_5_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL CTRL_6_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL CTRL_7_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL CTRL_8_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL CTRL_9_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL CTRL_10_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL CTRL_11_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL CTRL_12_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL CTRL_13_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL CTRL_14_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL CTRL_15_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL STAT_0_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL STAT_1_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL STAT_2_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL STAT_3_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL STAT_4_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL STAT_5_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL STAT_6_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL STAT_7_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL STAT_8_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL STAT_9_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL STAT_10_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL STAT_11_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL STAT_12_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL STAT_13_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL STAT_14_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL STAT_15_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL STAT : std_logic_vector(31 downto 0);\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: slv_register_bank PORT MAP(\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ SLV_ADDR_IN => SLV_ADDR_IN,\r
+ SLV_READ_IN => SLV_READ_IN,\r
+ SLV_WRITE_IN => SLV_WRITE_IN,\r
+ SLV_ACK_OUT => SLV_ACK_OUT,\r
+ SLV_DATA_IN => SLV_DATA_IN,\r
+ SLV_DATA_OUT => SLV_DATA_OUT,\r
+ BACKPLANE_IN => BACKPLANE_IN,\r
+ CTRL_0_OUT => CTRL_0_OUT,\r
+ CTRL_1_OUT => CTRL_1_OUT,\r
+ CTRL_2_OUT => CTRL_2_OUT,\r
+ CTRL_3_OUT => CTRL_3_OUT,\r
+ CTRL_4_OUT => CTRL_4_OUT,\r
+ CTRL_5_OUT => CTRL_5_OUT,\r
+ CTRL_6_OUT => CTRL_6_OUT,\r
+ CTRL_7_OUT => CTRL_7_OUT,\r
+ CTRL_8_OUT => CTRL_8_OUT,\r
+ CTRL_9_OUT => CTRL_9_OUT,\r
+ CTRL_10_OUT => CTRL_10_OUT,\r
+ CTRL_11_OUT => CTRL_11_OUT,\r
+ CTRL_12_OUT => CTRL_12_OUT,\r
+ CTRL_13_OUT => CTRL_13_OUT,\r
+ CTRL_14_OUT => CTRL_14_OUT,\r
+ CTRL_15_OUT => CTRL_15_OUT,\r
+ STAT_0_IN => STAT_0_IN,\r
+ STAT_1_IN => STAT_1_IN,\r
+ STAT_2_IN => STAT_2_IN,\r
+ STAT_3_IN => STAT_3_IN,\r
+ STAT_4_IN => STAT_4_IN,\r
+ STAT_5_IN => STAT_5_IN,\r
+ STAT_6_IN => STAT_6_IN,\r
+ STAT_7_IN => STAT_7_IN,\r
+ STAT_8_IN => STAT_8_IN,\r
+ STAT_9_IN => STAT_9_IN,\r
+ STAT_10_IN => STAT_10_IN,\r
+ STAT_11_IN => STAT_11_IN,\r
+ STAT_12_IN => STAT_12_IN,\r
+ STAT_13_IN => STAT_13_IN,\r
+ STAT_14_IN => STAT_14_IN,\r
+ STAT_15_IN => STAT_15_IN,\r
+ STAT => STAT\r
+ );\r
+\r
+THE_CLOCK_GEN: process\r
+begin\r
+ clk_in <= '1'; wait for 5 ns;\r
+ clk_in <= '0'; wait for 5 ns;\r
+end process THE_CLOCK_GEN;\r
+\r
+THE_TEST_BENCH: process\r
+begin\r
+ -- Setup signals\r
+ reset_in <= '0';\r
+ slv_read_in <= '0';\r
+ slv_write_in <= '0';\r
+ slv_data_in <= x"0000_0000";\r
+ slv_addr_in <= b"0000";\r
+ backplane_in <= b"000";\r
+ stat_0_in <= x"aa00";\r
+ stat_1_in <= x"aa01";\r
+ stat_2_in <= x"aa02";\r
+ stat_3_in <= x"aa03";\r
+ stat_4_in <= x"aa04";\r
+ stat_5_in <= x"aa05";\r
+ stat_6_in <= x"aa06";\r
+ stat_7_in <= x"aa07";\r
+ stat_8_in <= x"aa08";\r
+ stat_9_in <= x"aa09";\r
+ stat_10_in <= x"aa0a";\r
+ stat_11_in <= x"aa0b";\r
+ stat_12_in <= x"aa0c";\r
+ stat_13_in <= x"aa0d";\r
+ stat_14_in <= x"aa0e";\r
+ stat_15_in <= x"aa0f";\r
+\r
+ -- Reset the whole bunch\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ \r
+ \r
+ -- Tests may start now\r
+ \r
+ -- One write access (APV0)\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= x"0";\r
+ slv_data_in <= x"0000_ff00";\r
+ slv_write_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_write_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- One write access (APV1)\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= x"1";\r
+ slv_data_in <= x"0000_ff01";\r
+ slv_write_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_write_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- One write access (APV2)\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= x"2";\r
+ slv_data_in <= x"0000_ff02";\r
+ slv_write_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_write_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- One write access (APV3)\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= x"3";\r
+ slv_data_in <= x"0000_ff03";\r
+ slv_write_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_write_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- One write access (APV4)\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= x"4";\r
+ slv_data_in <= x"0000_ff04";\r
+ slv_write_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_write_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- One write access (APV5)\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= x"5";\r
+ slv_data_in <= x"0000_ff05";\r
+ slv_write_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_write_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- One write access (APV6)\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= x"6";\r
+ slv_data_in <= x"0000_ff06";\r
+ slv_write_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_write_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- One write access (APV7)\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= x"7";\r
+ slv_data_in <= x"0000_ff07";\r
+ slv_write_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_write_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- One write access (APV8)\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= x"8";\r
+ slv_data_in <= x"0000_ff08";\r
+ slv_write_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_write_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- One write access (APV9)\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= x"9";\r
+ slv_data_in <= x"0000_ff09";\r
+ slv_write_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_write_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- One write access (APV10)\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= x"a";\r
+ slv_data_in <= x"0000_ff0a";\r
+ slv_write_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_write_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- One write access (APV11)\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= x"b";\r
+ slv_data_in <= x"0000_ff0b";\r
+ slv_write_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_write_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- One write access (APV12)\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= x"c";\r
+ slv_data_in <= x"0000_ff0c";\r
+ slv_write_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_write_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- One write access (APV13)\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= x"d";\r
+ slv_data_in <= x"0000_ff0d";\r
+ slv_write_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_write_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- One write access (APV14)\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= x"e";\r
+ slv_data_in <= x"0000_ff0e";\r
+ slv_write_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_write_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- One write access (APV15)\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= x"f";\r
+ slv_data_in <= x"0000_ff0f";\r
+ slv_write_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_write_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+\r
+\r
+\r
+ -- One read access (APV0)\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= x"0";\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- One read access (APV1)\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= x"1";\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- One read access (APV2)\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= x"2";\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- One read access (APV3)\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= x"3";\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- One read access (APV4)\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= x"4";\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- One read access (APV5)\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= x"5";\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- One read access (APV6)\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= x"6";\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- One read access (APV7)\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= x"7";\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- One read access (APV8)\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= x"8";\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- One read access (APV9)\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= x"9";\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- One read access (APV10)\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= x"a";\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- One read access (APV11)\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= x"b";\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- One read access (APV12)\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= x"c";\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- One read access (APV13)\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= x"d";\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- One read access (APV14)\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= x"e";\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- One read access (APV15)\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= x"f";\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ stat_7_in <= x"dead";\r
+ -- One read access (APV15)\r
+ wait until rising_edge(clk_in);\r
+ slv_addr_in <= x"f";\r
+ slv_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ slv_read_in <= '0';\r
+ wait until rising_edge(slv_ack_out);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- Stay a while, stay forever....\r
+ wait;\r
+end process THE_TEST_BENCH; \r
+\r
+END;\r
+\r
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT spi_master\r
+ PORT(\r
+ CLK_IN : IN std_logic;\r
+ RESET_IN : IN std_logic;\r
+ BUS_READ_IN : IN std_logic;\r
+ BUS_WRITE_IN : IN std_logic;\r
+ BUS_ADDR_IN : IN std_logic_vector(0 to 0);\r
+ BUS_DATA_IN : IN std_logic_vector(31 downto 0);\r
+ SPI_SDI_IN : IN std_logic;\r
+ BRAM_WR_D_IN : IN std_logic_vector(7 downto 0); \r
+ BUS_BUSY_OUT : OUT std_logic;\r
+ BUS_ACK_OUT : OUT std_logic;\r
+ BUS_DATA_OUT : OUT std_logic_vector(31 downto 0);\r
+ SPI_CS_OUT : OUT std_logic;\r
+ SPI_SDO_OUT : OUT std_logic;\r
+ SPI_SCK_OUT : OUT std_logic;\r
+ BRAM_A_OUT : OUT std_logic_vector(7 downto 0);\r
+ BRAM_RD_D_OUT : OUT std_logic_vector(7 downto 0);\r
+ BRAM_WE_OUT : OUT std_logic;\r
+ STAT : OUT std_logic_vector(31 downto 0)\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL CLK_IN : std_logic;\r
+ SIGNAL RESET_IN : std_logic;\r
+ SIGNAL BUS_READ_IN : std_logic;\r
+ SIGNAL BUS_WRITE_IN : std_logic;\r
+ SIGNAL BUS_BUSY_OUT : std_logic;\r
+ SIGNAL BUS_ACK_OUT : std_logic;\r
+ SIGNAL BUS_ADDR_IN : std_logic_vector(0 to 0);\r
+ SIGNAL BUS_DATA_IN : std_logic_vector(31 downto 0);\r
+ SIGNAL BUS_DATA_OUT : std_logic_vector(31 downto 0);\r
+ SIGNAL SPI_CS_OUT : std_logic;\r
+ SIGNAL SPI_SDI_IN : std_logic;\r
+ SIGNAL SPI_SDO_OUT : std_logic;\r
+ SIGNAL SPI_SCK_OUT : std_logic;\r
+ SIGNAL BRAM_A_OUT : std_logic_vector(7 downto 0);\r
+ SIGNAL BRAM_WR_D_IN : std_logic_vector(7 downto 0);\r
+ SIGNAL BRAM_RD_D_OUT : std_logic_vector(7 downto 0);\r
+ SIGNAL BRAM_WE_OUT : std_logic;\r
+ SIGNAL STAT : std_logic_vector(31 downto 0);\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: spi_master PORT MAP(\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ BUS_READ_IN => BUS_READ_IN,\r
+ BUS_WRITE_IN => BUS_WRITE_IN,\r
+ BUS_BUSY_OUT => BUS_BUSY_OUT,\r
+ BUS_ACK_OUT => BUS_ACK_OUT,\r
+ BUS_ADDR_IN => BUS_ADDR_IN,\r
+ BUS_DATA_IN => BUS_DATA_IN,\r
+ BUS_DATA_OUT => BUS_DATA_OUT,\r
+ SPI_CS_OUT => SPI_CS_OUT,\r
+ SPI_SDI_IN => SPI_SDI_IN,\r
+ SPI_SDO_OUT => SPI_SDO_OUT,\r
+ SPI_SCK_OUT => SPI_SCK_OUT,\r
+ BRAM_A_OUT => BRAM_A_OUT,\r
+ BRAM_WR_D_IN => BRAM_WR_D_IN,\r
+ BRAM_RD_D_OUT => BRAM_RD_D_OUT,\r
+ BRAM_WE_OUT => BRAM_WE_OUT,\r
+ STAT => STAT\r
+ );\r
+\r
+THE_CLOCK_GEN: process\r
+begin\r
+ clk_in <= '1'; wait for 5 ns;\r
+ clk_in <= '0'; wait for 5 ns;\r
+end process THE_CLOCK_GEN;\r
+\r
+THE_TEST_BENCH: process\r
+begin\r
+ -- Setup signals\r
+ reset_in <= '0';\r
+ spi_sdi_in <= '0';\r
+ bus_read_in <= '0';\r
+ bus_write_in <= '0';\r
+ bus_addr_in <= b"0";\r
+ bus_data_in <= x"0000_0000";\r
+ bram_wr_d_in <= x"00";\r
+ \r
+ -- Sync reset\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ reset_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ wait for 140 ns;\r
+ \r
+ -- Tests may start now\r
+ \r
+ -- Set MAX to 0x03 = 4 bytes\r
+ wait until rising_edge(clk_in);\r
+ bus_addr_in <= b"1";\r
+ bus_data_in <= x"03_00_00_00";\r
+ wait until rising_edge(clk_in);\r
+ bus_write_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ bus_write_in <= '0';\r
+ wait until falling_edge(bus_ack_out);\r
+ bus_data_in <= x"0000_0000";\r
+ bus_addr_in <= b"0";\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- Start SPI access (ReadManId)\r
+ wait until rising_edge(clk_in);\r
+ bus_addr_in <= b"0";\r
+ bus_data_in <= x"9f_aa_bb_cc";\r
+ wait until rising_edge(clk_in);\r
+ bus_write_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ bus_write_in <= '0';\r
+ wait until falling_edge(bus_ack_out);\r
+ bus_data_in <= x"0000_0000";\r
+ bus_addr_in <= b"0";\r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- SPI is busy now...\r
+ wait until rising_edge(clk_in);\r
+ bus_addr_in <= b"0";\r
+ wait until rising_edge(clk_in);\r
+ bus_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ bus_read_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ bus_addr_in <= b"0";\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+\r
+ -- SPI is busy now...\r
+ wait until rising_edge(clk_in);\r
+ bus_addr_in <= b"1";\r
+ wait until rising_edge(clk_in);\r
+ bus_read_in <= '1';\r
+ wait until rising_edge(clk_in);\r
+ bus_read_in <= '0';\r
+ wait until rising_edge(clk_in);\r
+ bus_addr_in <= b"0";\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ wait until rising_edge(clk_in);\r
+ \r
+ -- Stay a while... stay forever!!!\r
+ wait;\r
+ \r
+end process THE_TEST_BENCH;\r
+END;\r
+\r
--- /dev/null
+\r
+-- VHDL Test Bench Created from source file spi_real_slim.vhd -- 07-MAY-2008 01:09:40\r
+--\r
+-- Notes: \r
+-- 1) This testbench template has been automatically generated using types\r
+-- std_logic and std_logic_vector for the ports of the unit under test.\r
+-- Lattice recommends that these types always be used for the top-level\r
+-- I/O of a design in order to guarantee that the testbench will bind\r
+-- correctly to the timing (post-route) simulation model.\r
+-- 2) To use this template as your testbench, change the filename to any\r
+-- name of your choice with the extension .vhd, and use the "source->import"\r
+-- menu in the ispLEVER Project Navigator to import the testbench.\r
+-- Then edit the user defined section below, adding code to generate the \r
+-- stimulus for your design.\r
+-- 3) VHDL simulations will produce errors if there are Lattice FPGA library \r
+-- elements in your design that require the instantiation of GSR, PUR, and\r
+-- TSALL and they are not present in the testbench. For more information see\r
+-- the How To section of online help. \r
+--\r
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT spi_real_slim\r
+ PORT(\r
+ SYSCLK : IN std_logic;\r
+ CLEAR : IN std_logic;\r
+ RESET : IN std_logic;\r
+ START_IN : IN std_logic;\r
+ CMD_IN : IN std_logic_vector(7 downto 0);\r
+ BUSY_OUT : OUT std_logic;\r
+ SPI_SCK_OUT : OUT std_logic;\r
+ SPI_CS_OUT : OUT std_logic;\r
+ SPI_SDO_OUT : OUT std_logic;\r
+ CLK_EN_OUT : OUT std_logic;\r
+ BSM_OUT : OUT std_logic_vector(7 downto 0);\r
+ DEBUG_OUT : OUT std_logic_vector(31 downto 0)\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL SYSCLK : std_logic;\r
+ SIGNAL CLEAR : std_logic;\r
+ SIGNAL RESET : std_logic;\r
+ SIGNAL START_IN : std_logic;\r
+ SIGNAL BUSY_OUT : std_logic;\r
+ SIGNAL CMD_IN : std_logic_vector(7 downto 0);\r
+ SIGNAL SPI_SCK_OUT : std_logic;\r
+ SIGNAL SPI_CS_OUT : std_logic;\r
+ SIGNAL SPI_SDO_OUT : std_logic;\r
+ SIGNAL CLK_EN_OUT : std_logic;\r
+ SIGNAL BSM_OUT : std_logic_vector(7 downto 0);\r
+ SIGNAL DEBUG_OUT : std_logic_vector(31 downto 0);\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: spi_real_slim PORT MAP(\r
+ SYSCLK => SYSCLK,\r
+ CLEAR => CLEAR,\r
+ RESET => RESET,\r
+ START_IN => START_IN,\r
+ BUSY_OUT => BUSY_OUT,\r
+ CMD_IN => CMD_IN,\r
+ SPI_SCK_OUT => SPI_SCK_OUT,\r
+ SPI_CS_OUT => SPI_CS_OUT,\r
+ SPI_SDO_OUT => SPI_SDO_OUT,\r
+ CLK_EN_OUT => CLK_EN_OUT,\r
+ BSM_OUT => BSM_OUT,\r
+ DEBUG_OUT => DEBUG_OUT\r
+ );\r
+\r
+THE_CLOCK_GEN: process\r
+begin\r
+ sysclk <= '1'; wait for 5 ns;\r
+ sysclk <= '0'; wait for 5 ns;\r
+end process THE_CLOCK_GEN;\r
+\r
+THE_TEST_BENCH: process\r
+begin\r
+ -- Setup signals\r
+ clear <= '0';\r
+ reset <= '0';\r
+ start_in <= '0';\r
+ cmd_in <= x"00";\r
+ \r
+ -- Reset all\r
+ wait for 10 ns;\r
+ clear <= '1';\r
+ wait for 10 ns;\r
+ clear <= '0';\r
+ wait for 150 ns;\r
+ \r
+ -- Sync reset\r
+ wait until rising_edge(sysclk);\r
+ reset <= '1';\r
+ wait until rising_edge(sysclk);\r
+ reset <= '0';\r
+ wait until rising_edge(sysclk);\r
+ wait for 140 ns;\r
+ \r
+ \r
+ -- Tests may start now\r
+\r
+ -- check any command\r
+ wait until rising_edge(sysclk);\r
+ cmd_in <= x"a1";\r
+ start_in <= '1';\r
+ wait until rising_edge(sysclk);\r
+ start_in <= '0';\r
+ cmd_in <= x"00";\r
+ wait until rising_edge(busy_out);\r
+ -- Mission accomplished\r
+ wait until falling_edge(busy_out);\r
+ wait for 500 ns;\r
+\r
+ -- check any command\r
+ wait until rising_edge(sysclk);\r
+ cmd_in <= x"c2";\r
+ start_in <= '1';\r
+ wait until rising_edge(sysclk);\r
+ start_in <= '0';\r
+ cmd_in <= x"00";\r
+ wait until rising_edge(busy_out);\r
+ -- Mission accomplished\r
+ wait until falling_edge(busy_out);\r
+ wait for 500 ns;\r
+\r
+ -----------------------------------------------\r
+ -- Stay a while, stay forever... muahahahaha!\r
+ -----------------------------------------------\r
+ wait;\r
+\r
+end process THE_TEST_BENCH;\r
+\r
+END;\r
--- /dev/null
+-- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23)
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity tb is
+end entity tb;
+
+
+architecture test of tb is
+
+ component suber_12bit
+ port (DataA : in std_logic_vector(11 downto 0);
+ DataB : in std_logic_vector(11 downto 0); Clock: in std_logic;
+ Reset: in std_logic; ClockEn: in std_logic;
+ Result : out std_logic_vector(11 downto 0)
+ );
+ end component;
+
+ signal DataA : std_logic_vector(11 downto 0) := (others => '0');
+ signal DataB : std_logic_vector(11 downto 0) := (others => '0');
+ signal Clock: std_logic := '0';
+ signal Reset: std_logic := '0';
+ signal ClockEn: std_logic := '0';
+ signal Result : std_logic_vector(11 downto 0);
+begin
+ u1 : suber_12bit
+ port map (DataA => DataA, DataB => DataB, Clock => Clock, Reset => Reset,
+ ClockEn => ClockEn, Result => Result
+ );
+
+ process
+
+ begin
+ DataA <= (others => '0') ;
+ for i in 0 to 200 loop
+ wait until Clock'event and Clock = '1';
+ DataA <= DataA + '1' after 1 ns;
+ end loop;
+ wait;
+ end process;
+
+ process
+
+ begin
+ DataB <= (others => '0') ;
+ for i in 0 to 200 loop
+ wait until Clock'event and Clock = '1';
+ DataB <= DataB + '1' after 1 ns;
+ end loop;
+ wait;
+ end process;
+
+ Clock <= not Clock after 5.00 ns;
+
+ process
+
+ begin
+ Reset <= '1' ;
+ wait for 100 ns;
+ Reset <= '0' ;
+ wait;
+ end process;
+
+ process
+
+ begin
+ ClockEn <= '1' ;
+ wait;
+ end process;
+
+end architecture test;
--- /dev/null
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+ COMPONENT trb_net16_ibuf2\r
+ PORT(\r
+ CLK : IN std_logic;\r
+ RESET : IN std_logic;\r
+ CLK_EN : IN std_logic;\r
+ MED_DATAREADY_IN : IN std_logic;\r
+ MED_DATA_IN : IN std_logic_vector(15 downto 0);\r
+ MED_PACKET_NUM_IN : IN std_logic_vector(2 downto 0);\r
+ MED_ERROR_IN : IN std_logic_vector(2 downto 0);\r
+ INT_INIT_READ_IN : IN std_logic;\r
+ INT_REPLY_READ_IN : IN std_logic; \r
+ MED_READ_OUT : OUT std_logic;\r
+ INT_INIT_DATA_OUT : OUT std_logic_vector(15 downto 0);\r
+ INT_INIT_PACKET_NUM_OUT : OUT std_logic_vector(2 downto 0);\r
+ INT_INIT_DATAREADY_OUT : OUT std_logic;\r
+ INT_REPLY_DATA_OUT : OUT std_logic_vector(15 downto 0);\r
+ INT_REPLY_PACKET_NUM_OUT : OUT std_logic_vector(2 downto 0);\r
+ INT_REPLY_DATAREADY_OUT : OUT std_logic;\r
+ INT_ERROR_OUT : OUT std_logic_vector(2 downto 0);\r
+ STAT_BUFFER_COUNTER : OUT std_logic_vector(31 downto 0);\r
+ STAT_BUFFER : OUT std_logic_vector(31 downto 0)\r
+ );\r
+ END COMPONENT;\r
+\r
+ SIGNAL CLK : std_logic;\r
+ SIGNAL RESET : std_logic;\r
+ SIGNAL CLK_EN : std_logic;\r
+ SIGNAL MED_DATAREADY_IN : std_logic;\r
+ SIGNAL MED_DATA_IN : std_logic_vector(15 downto 0);\r
+ SIGNAL MED_PACKET_NUM_IN : std_logic_vector(2 downto 0);\r
+ SIGNAL MED_READ_OUT : std_logic;\r
+ SIGNAL MED_ERROR_IN : std_logic_vector(2 downto 0);\r
+ SIGNAL INT_INIT_DATA_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL INT_INIT_PACKET_NUM_OUT : std_logic_vector(2 downto 0);\r
+ SIGNAL INT_INIT_DATAREADY_OUT : std_logic;\r
+ SIGNAL INT_INIT_READ_IN : std_logic;\r
+ SIGNAL INT_REPLY_DATA_OUT : std_logic_vector(15 downto 0);\r
+ SIGNAL INT_REPLY_PACKET_NUM_OUT : std_logic_vector(2 downto 0);\r
+ SIGNAL INT_REPLY_DATAREADY_OUT : std_logic;\r
+ SIGNAL INT_REPLY_READ_IN : std_logic;\r
+ SIGNAL INT_ERROR_OUT : std_logic_vector(2 downto 0);\r
+ SIGNAL STAT_BUFFER_COUNTER : std_logic_vector(31 downto 0);\r
+ SIGNAL STAT_BUFFER : std_logic_vector(31 downto 0);\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+ uut: trb_net16_ibuf2 \r
+ PORT MAP(\r
+ CLK => CLK,\r
+ RESET => RESET,\r
+ CLK_EN => CLK_EN,\r
+ MED_DATAREADY_IN => MED_DATAREADY_IN,\r
+ MED_DATA_IN => MED_DATA_IN,\r
+ MED_PACKET_NUM_IN => MED_PACKET_NUM_IN,\r
+ MED_READ_OUT => MED_READ_OUT,\r
+ MED_ERROR_IN => MED_ERROR_IN,\r
+ INT_INIT_DATA_OUT => INT_INIT_DATA_OUT,\r
+ INT_INIT_PACKET_NUM_OUT => INT_INIT_PACKET_NUM_OUT,\r
+ INT_INIT_DATAREADY_OUT => INT_INIT_DATAREADY_OUT,\r
+ INT_INIT_READ_IN => INT_INIT_READ_IN,\r
+ INT_REPLY_DATA_OUT => INT_REPLY_DATA_OUT,\r
+ INT_REPLY_PACKET_NUM_OUT => INT_REPLY_PACKET_NUM_OUT,\r
+ INT_REPLY_DATAREADY_OUT => INT_REPLY_DATAREADY_OUT,\r
+ INT_REPLY_READ_IN => INT_REPLY_READ_IN,\r
+ INT_ERROR_OUT => INT_ERROR_OUT,\r
+ STAT_BUFFER_COUNTER => STAT_BUFFER_COUNTER,\r
+ STAT_BUFFER => STAT_BUFFER\r
+ );\r
+\r
+CLOCK_GEN_PROC: process\r
+begin\r
+ clk <= '1'; wait for 5.0 ns;\r
+ clk <= '0'; wait for 5.0 ns; \r
+end process CLOCK_GEN_PROC;\r
+\r
+THE_TESTBENCH_PROC: process\r
+begin\r
+ -- Setup signals\r
+ reset <= '0';\r
+ clk_en <= '1';\r
+ med_dataready_in <= '0';\r
+ med_data_in <= x"0000";\r
+ med_packet_num_in <= b"000"; \r
+ med_error_in <= b"000";\r
+ int_init_read_in <= '0';\r
+ int_reply_read_in <= '0';\r
+ wait for 33 ns;\r
+ \r
+ -- Reset the whole stuff\r
+ wait until rising_edge(clk);\r
+ reset <= '1';\r
+ wait until rising_edge(clk);\r
+ wait until rising_edge(clk);\r
+ reset <= '0';\r
+ wait until rising_edge(clk);\r
+ wait until rising_edge(clk);\r
+ wait until rising_edge(clk);\r
+ wait until rising_edge(clk);\r
+ \r
+ -- Tests may start here\r
+\r
+ -- First packet\r
+ wait until rising_edge(clk);\r
+ med_data_in <= x"0001";\r
+ med_packet_num_in <= b"100";\r
+ med_dataready_in <= '1';\r
+ wait until rising_edge(clk);\r
+ med_data_in <= x"dead";\r
+ med_packet_num_in <= b"000";\r
+ wait until rising_edge(clk);\r
+ med_data_in <= x"beef";\r
+ med_packet_num_in <= b"001";\r
+ wait until rising_edge(clk);\r
+ med_data_in <= x"affe";\r
+ med_packet_num_in <= b"010";\r
+ wait until rising_edge(clk);\r
+ med_data_in <= x"d00f";\r
+ med_packet_num_in <= b"011";\r
+ wait until rising_edge(clk);\r
+ med_dataready_in <= '0'; \r
+\r
+ wait until rising_edge(clk);\r
+ wait until rising_edge(clk);\r
+ int_init_read_in <= '1';\r
+ wait until rising_edge(clk);\r
+ wait until rising_edge(clk);\r
+ wait until rising_edge(clk);\r
+ wait until rising_edge(clk);\r
+ wait until rising_edge(clk);\r
+ wait until rising_edge(clk);\r
+\r
+\r
+ -- Second packet\r
+ wait until rising_edge(clk);\r
+ med_data_in <= x"0001";\r
+ med_packet_num_in <= b"100";\r
+ med_dataready_in <= '1';\r
+ wait until rising_edge(clk);\r
+ med_data_in <= x"dead";\r
+ med_packet_num_in <= b"000";\r
+ wait until rising_edge(clk);\r
+ med_data_in <= x"beef";\r
+ med_packet_num_in <= b"001";\r
+ wait until rising_edge(clk);\r
+ med_data_in <= x"affe";\r
+ med_packet_num_in <= b"010";\r
+ wait until rising_edge(clk);\r
+ med_data_in <= x"d00f";\r
+ med_packet_num_in <= b"011";\r
+ wait until rising_edge(clk);\r
+ med_dataready_in <= '0';\r
+ wait until rising_edge(clk);\r
+ wait until rising_edge(clk);\r
+ wait until rising_edge(clk);\r
+ wait until rising_edge(clk);\r
+\r
+\r
+\r
+\r
+ -- Third packet\r
+ wait until rising_edge(clk);\r
+ med_data_in <= x"0001";\r
+ med_packet_num_in <= b"100";\r
+ med_dataready_in <= '1';\r
+ wait until rising_edge(clk);\r
+ med_data_in <= x"dead";\r
+ med_packet_num_in <= b"000";\r
+ wait until rising_edge(clk);\r
+ med_data_in <= x"beef";\r
+ med_packet_num_in <= b"001";\r
+ wait until rising_edge(clk);\r
+ med_data_in <= x"affe";\r
+ med_packet_num_in <= b"010";\r
+ wait until rising_edge(clk);\r
+ med_data_in <= x"d00f";\r
+ med_packet_num_in <= b"011";\r
+ wait until rising_edge(clk);\r
+ med_dataready_in <= '0';\r
+ wait until rising_edge(clk);\r
+ wait until rising_edge(clk);\r
+ wait until rising_edge(clk);\r
+ wait until rising_edge(clk);\r
+ wait until rising_edge(clk);\r
+\r
+\r
+ -- Fourth packet\r
+ wait until rising_edge(clk);\r
+ med_data_in <= x"0009";\r
+ med_packet_num_in <= b"100";\r
+ med_dataready_in <= '1';\r
+ wait until rising_edge(clk);\r
+ med_data_in <= x"dead";\r
+ med_packet_num_in <= b"000";\r
+ wait until rising_edge(clk);\r
+ med_data_in <= x"beef";\r
+ med_packet_num_in <= b"001";\r
+ wait until rising_edge(clk);\r
+ med_data_in <= x"affe";\r
+ med_packet_num_in <= b"010";\r
+ wait until rising_edge(clk);\r
+ med_data_in <= x"d00f";\r
+ med_packet_num_in <= b"011";\r
+ wait until rising_edge(clk);\r
+ med_dataready_in <= '0';\r
+ wait until rising_edge(clk);\r
+ wait until rising_edge(clk);\r
+ int_reply_read_in <= '1';\r
+ wait until rising_edge(clk);\r
+ wait until rising_edge(clk);\r
+ wait until rising_edge(clk);\r
+\r
+\r
+ -- Fifth packet\r
+ wait until rising_edge(clk);\r
+ med_data_in <= x"0009";\r
+ med_packet_num_in <= b"100";\r
+ med_dataready_in <= '1';\r
+ wait until rising_edge(clk);\r
+ med_data_in <= x"dead";\r
+ med_packet_num_in <= b"000";\r
+ wait until rising_edge(clk);\r
+ med_data_in <= x"beef";\r
+ med_packet_num_in <= b"001";\r
+ wait until rising_edge(clk);\r
+ med_data_in <= x"affe";\r
+ med_packet_num_in <= b"010";\r
+ wait until rising_edge(clk);\r
+ med_data_in <= x"d00f";\r
+ med_packet_num_in <= b"011";\r
+ wait until rising_edge(clk);\r
+ med_dataready_in <= '0';\r
+ wait until rising_edge(clk);\r
+ wait until rising_edge(clk);\r
+ wait until rising_edge(clk);\r
+ wait until rising_edge(clk);\r
+ wait until rising_edge(clk);\r
+\r
+ -- Stay a while... stay forever!!! Muhahaha!!!!\r
+ wait;\r
+ \r
+end process THE_TESTBENCH_PROC;\r
+\r
+\r
+END;\r
--- /dev/null
+LIBRARY ieee; \r
+USE ieee.std_logic_1164.ALL; \r
+USE ieee.numeric_std.ALL; \r
+ \r
+ENTITY testbench IS \r
+END testbench; \r
+ \r
+ARCHITECTURE behavior OF testbench IS \r
+ \r
+ COMPONENT trb_net_sbuf2 \r
+ PORT( \r
+ CLK : IN std_logic; \r
+ RESET : IN std_logic; \r
+ CLK_EN : IN std_logic; \r
+ COMB_DATAREADY_IN : IN std_logic; \r
+ COMB_READ_IN : IN std_logic; \r
+ COMB_DATA_IN : IN std_logic_vector(18 downto 0); \r
+ SYN_READ_IN : IN std_logic; \r
+ COMB_NEXT_READ_OUT : OUT std_logic; \r
+ SYN_DATAREADY_OUT : OUT std_logic; \r
+ SYN_DATA_OUT : OUT std_logic_vector(18 downto 0); \r
+ FIFO_WR_OUT : OUT std_logic;\r
+ FIFO_RD_OUT : OUT std_logic; \r
+ STAT_BUFFER : OUT std_logic \r
+ ); \r
+ END COMPONENT; \r
+ \r
+ SIGNAL CLK : std_logic; \r
+ SIGNAL RESET : std_logic; \r
+ SIGNAL CLK_EN : std_logic; \r
+ SIGNAL COMB_DATAREADY_IN : std_logic; \r
+ SIGNAL COMB_NEXT_READ_OUT : std_logic; \r
+ SIGNAL COMB_READ_IN : std_logic; \r
+ SIGNAL COMB_DATA_IN : std_logic_vector(18 downto 0); \r
+ SIGNAL SYN_DATAREADY_OUT : std_logic; \r
+ SIGNAL SYN_DATA_OUT : std_logic_vector(18 downto 0); \r
+ SIGNAL SYN_READ_IN : std_logic; \r
+ signal FIFO_WR_OUT : std_logic;\r
+ signal FIFO_RD_OUT : std_logic; \r
+ SIGNAL STAT_BUFFER : std_logic; \r
+ \r
+BEGIN \r
+ \r
+-- Please check and add your generic clause manually \r
+ uut: trb_net_sbuf2 PORT MAP( \r
+ CLK => CLK, \r
+ RESET => RESET, \r
+ CLK_EN => CLK_EN, \r
+ COMB_DATAREADY_IN => COMB_DATAREADY_IN, \r
+ COMB_NEXT_READ_OUT => COMB_NEXT_READ_OUT, \r
+ COMB_READ_IN => COMB_READ_IN, \r
+ COMB_DATA_IN => COMB_DATA_IN, \r
+ SYN_DATAREADY_OUT => SYN_DATAREADY_OUT, \r
+ SYN_DATA_OUT => SYN_DATA_OUT, \r
+ SYN_READ_IN => SYN_READ_IN,\r
+ FIFO_WR_OUT => FIFO_WR_OUT,\r
+ FIFO_RD_OUT => FIFO_RD_OUT,\r
+ STAT_BUFFER => STAT_BUFFER \r
+ ); \r
+ \r
+CLOCK_GEN_PROC: process\r
+begin\r
+ clk <= '1'; wait for 5.0 ns;\r
+ clk <= '0'; wait for 5.0 ns;\r
+end process CLOCK_GEN_PROC; \r
+ \r
+THE_TEST_BENCH_PROC: process\r
+begin\r
+ -- Setup signals\r
+ reset <= '0';\r
+ clk_en <= '1';\r
+ comb_dataready_in <= '0';\r
+ comb_read_in <= '0';\r
+ comb_data_in <= (others => '0');\r
+ syn_read_in <= '0';\r
+\r
+ -- Reset the whole stuff\r
+ wait until rising_edge(clk);\r
+ reset <= '1';\r
+ wait until rising_edge(clk);\r
+ wait until rising_edge(clk);\r
+ reset <= '0';\r
+ wait until rising_edge(clk);\r
+ \r
+ -- Tests may start now...\r
+ -- see what happens if nothing is in the SBUF\r
+ wait until rising_edge(clk);\r
+ wait until rising_edge(clk);\r
+ wait until rising_edge(clk);\r
+ wait until rising_edge(clk);\r
+\r
+ -- now write some data in\r
+ wait until rising_edge(clk);\r
+ comb_dataready_in <= '1'; \r
+ comb_read_in <= '1';\r
+ comb_data_in <= b"100_0000_0000_0000_0000";\r
+ wait until rising_edge(clk);\r
+ comb_data_in <= b"100_0000_0000_0000_0001";\r
+ wait until rising_edge(clk);\r
+ comb_data_in <= b"100_0000_0000_0000_0010";\r
+ wait until rising_edge(clk);\r
+ comb_data_in <= b"100_0000_0000_0000_0011";\r
+ wait until rising_edge(clk);\r
+ comb_data_in <= b"100_0000_0000_0000_0100";\r
+ wait until rising_edge(clk);\r
+ comb_data_in <= b"100_0000_0000_0000_0101";\r
+ wait until rising_edge(clk);\r
+ comb_data_in <= b"100_0000_0000_0000_0110";\r
+ wait until rising_edge(clk);\r
+ comb_data_in <= b"100_0000_0000_0000_0111";\r
+ wait until rising_edge(clk);\r
+ comb_dataready_in <= '0';\r
+ \r
+ -- Stay a while... stay forever! Muhahaha!!!\r
+ wait;\r
+\r
+end process THE_TEST_BENCH_PROC;\r
+ \r
+END;
\ No newline at end of file
--- /dev/null
+LIBRARY ieee; \r
+USE ieee.std_logic_1164.ALL; \r
+USE ieee.numeric_std.ALL; \r
+ \r
+ENTITY testbench IS \r
+END testbench; \r
+ \r
+ARCHITECTURE behavior OF testbench IS \r
+ \r
+ COMPONENT trb_net_sbuf3 \r
+ GENERIC(\r
+ DATA_WIDTH : integer := 18\r
+ );\r
+ PORT( \r
+ CLK : IN std_logic; \r
+ RESET : IN std_logic; \r
+ CLK_EN : IN std_logic; \r
+ COMB_DATAREADY_IN : IN std_logic; \r
+ COMB_READ_IN : IN std_logic; \r
+ COMB_DATA_IN : IN std_logic_vector(17 downto 0); \r
+ SYN_READ_IN : IN std_logic; \r
+ COMB_NEXT_READ_OUT : OUT std_logic; \r
+ SYN_DATAREADY_OUT : OUT std_logic;\r
+ SYN_DATA_OUT : OUT std_logic_vector(17 downto 0); \r
+ DEBUG_OUT : OUT std_logic_vector(15 downto 0); \r
+ STAT_BUFFER : OUT std_logic \r
+ ); \r
+ END COMPONENT; \r
+\r
+ SIGNAL CLK : std_logic; \r
+ SIGNAL RESET : std_logic; \r
+ SIGNAL CLK_EN : std_logic; \r
+ SIGNAL COMB_DATAREADY_IN : std_logic; \r
+ SIGNAL COMB_NEXT_READ_OUT : std_logic; \r
+ SIGNAL COMB_READ_IN : std_logic; \r
+ SIGNAL COMB_DATA_IN : std_logic_vector(17 downto 0); \r
+ SIGNAL SYN_DATAREADY_OUT : std_logic; \r
+ SIGNAL SYN_DATA_OUT : std_logic_vector(17 downto 0); \r
+ SIGNAL SYN_READ_IN : std_logic; \r
+ SIGNAL STAT_BUFFER : std_logic; \r
+ SIGNAL DEBUG_OUT : std_logic_vector(15 downto 0); \r
+ \r
+BEGIN \r
+ \r
+-- Please check and add your generic clause manually \r
+ uut: trb_net_sbuf3 PORT MAP( \r
+ CLK => CLK, \r
+ RESET => RESET, \r
+ CLK_EN => CLK_EN, \r
+ COMB_DATAREADY_IN => COMB_DATAREADY_IN, \r
+ COMB_NEXT_READ_OUT => COMB_NEXT_READ_OUT, \r
+ COMB_READ_IN => COMB_READ_IN, \r
+ COMB_DATA_IN => COMB_DATA_IN, \r
+ SYN_DATAREADY_OUT => SYN_DATAREADY_OUT, \r
+ SYN_DATA_OUT => SYN_DATA_OUT, \r
+ SYN_READ_IN => SYN_READ_IN,\r
+ DEBUG_OUT => DEBUG_OUT,\r
+ STAT_BUFFER => STAT_BUFFER \r
+ ); \r
+ \r
+CLOCK_GEN_PROC: process\r
+begin\r
+ clk <= '1'; wait for 5.0 ns;\r
+ clk <= '0'; wait for 5.0 ns;\r
+end process CLOCK_GEN_PROC; \r
+ \r
+THE_TEST_BENCH_PROC: process\r
+begin\r
+ -- Setup signals\r
+ reset <= '0';\r
+ clk_en <= '1';\r
+ comb_dataready_in <= '0';\r
+ comb_read_in <= '0';\r
+ comb_data_in <= (others => '0');\r
+ syn_read_in <= '0';\r
+\r
+ -- Reset the whole stuff\r
+ wait until rising_edge(clk);\r
+ reset <= '1';\r
+ wait until rising_edge(clk);\r
+ wait until rising_edge(clk);\r
+ reset <= '0';\r
+ wait until rising_edge(clk);\r
+ \r
+ -- Tests may start now...\r
+ -- see what happens if nothing is in the SBUF\r
+ wait until rising_edge(clk);\r
+ wait until rising_edge(clk);\r
+ wait until rising_edge(clk);\r
+ wait until rising_edge(clk);\r
+\r
+ -- now write some data in\r
+ wait until rising_edge(clk);\r
+ comb_dataready_in <= '1'; \r
+ comb_read_in <= '1';\r
+ comb_data_in <= b"10_0000_0000_0000_0000";\r
+ wait until rising_edge(clk);\r
+ comb_data_in <= b"10_0000_0000_0000_0001";\r
+ wait until rising_edge(clk);\r
+ comb_data_in <= b"10_0000_0000_0000_0010";\r
+ wait until rising_edge(clk);\r
+ comb_data_in <= b"10_0000_0000_0000_0011";\r
+ wait until rising_edge(clk);\r
+ comb_data_in <= b"10_0000_0000_0000_0100";\r
+ wait until rising_edge(clk);\r
+ comb_data_in <= b"10_0000_0000_0000_0101";\r
+ wait until rising_edge(clk);\r
+ comb_data_in <= b"10_0000_0000_0000_0110";\r
+ wait until rising_edge(clk);\r
+ comb_data_in <= b"10_0000_0000_0000_0111";\r
+ wait until rising_edge(clk);\r
+ comb_dataready_in <= '0';\r
+ \r
+ -- Stay a while... stay forever! Muhahaha!!!\r
+ wait;\r
+\r
+end process THE_TEST_BENCH_PROC;\r
+ \r
+END;
\ No newline at end of file
--- /dev/null
+[Device]\r
+Family=latticeecp2m\r
+PartType=LFE2M100E\r
+PartName=LFE2M100E-6F900C\r
+SpeedGrade=-6\r
+Package=FPBGA900\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=FIFO\r
+CoreRevision=4.7\r
+ModuleName=test_fifo\r
+SourceFormat=VHDL\r
+ParameterFileVersion=1.0\r
+Date=12/14/2009\r
+Time=14:54:15\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+FIFOImp=EBR Based\r
+Depth=1024\r
+Width=18\r
+regout=0\r
+CtrlByRdEn=0\r
+EmpFlg=0\r
+PeMode=Static - Dual Threshold\r
+PeAssert=10\r
+PeDeassert=12\r
+FullFlg=0\r
+PfMode=Static - Dual Threshold\r
+PfAssert=508\r
+PfDeassert=506\r
+RDataCount=0\r
+EnECC=0\r
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41)
+-- Module Version: 4.7
+--X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 1024 -width 18 -depth 1024 -no_enable -pe -1 -pf -1 -e
+
+-- Mon Dec 14 14:54:16 2009
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity test_fifo is
+ port (
+ Data: in std_logic_vector(17 downto 0);
+ Clock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ Q: out std_logic_vector(17 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic);
+end test_fifo;
+
+architecture Structure of test_fifo is
+
+ -- internal signal declarations
+ signal invout_1: std_logic;
+ signal invout_0: std_logic;
+ signal rden_i_inv: std_logic;
+ signal fcnt_en: std_logic;
+ signal empty_i: std_logic;
+ signal empty_d: std_logic;
+ signal full_i: std_logic;
+ signal full_d: std_logic;
+ signal ifcount_0: std_logic;
+ signal ifcount_1: std_logic;
+ signal bdcnt_bctr_ci: std_logic;
+ signal ifcount_2: std_logic;
+ signal ifcount_3: std_logic;
+ signal co0: std_logic;
+ signal ifcount_4: std_logic;
+ signal ifcount_5: std_logic;
+ signal co1: std_logic;
+ signal ifcount_6: std_logic;
+ signal ifcount_7: std_logic;
+ signal co2: std_logic;
+ signal ifcount_8: std_logic;
+ signal ifcount_9: std_logic;
+ signal co3: std_logic;
+ signal ifcount_10: std_logic;
+ signal co5: std_logic;
+ signal cnt_con: std_logic;
+ signal co4: std_logic;
+ signal cmp_ci: std_logic;
+ signal rden_i: std_logic;
+ signal co0_1: std_logic;
+ signal co1_1: std_logic;
+ signal co2_1: std_logic;
+ signal co3_1: std_logic;
+ signal co4_1: std_logic;
+ signal cmp_le_1: std_logic;
+ signal cmp_le_1_c: std_logic;
+ signal cmp_ci_1: std_logic;
+ signal fcount_0: std_logic;
+ signal fcount_1: std_logic;
+ signal co0_2: std_logic;
+ signal fcount_2: std_logic;
+ signal fcount_3: std_logic;
+ signal co1_2: std_logic;
+ signal fcount_4: std_logic;
+ signal fcount_5: std_logic;
+ signal co2_2: std_logic;
+ signal fcount_6: std_logic;
+ signal fcount_7: std_logic;
+ signal co3_2: std_logic;
+ signal wren_i: std_logic;
+ signal fcount_8: std_logic;
+ signal fcount_9: std_logic;
+ signal co4_2: std_logic;
+ signal wren_i_inv: std_logic;
+ signal fcount_10: std_logic;
+ signal cmp_ge_d1: std_logic;
+ signal cmp_ge_d1_c: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal w_ctr_ci: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_3: std_logic;
+ signal co0_3: std_logic;
+ signal iwcount_4: std_logic;
+ signal iwcount_5: std_logic;
+ signal wcount_4: std_logic;
+ signal wcount_5: std_logic;
+ signal co1_3: std_logic;
+ signal iwcount_6: std_logic;
+ signal iwcount_7: std_logic;
+ signal wcount_6: std_logic;
+ signal wcount_7: std_logic;
+ signal co2_3: std_logic;
+ signal iwcount_8: std_logic;
+ signal iwcount_9: std_logic;
+ signal wcount_8: std_logic;
+ signal wcount_9: std_logic;
+ signal co3_3: std_logic;
+ signal iwcount_10: std_logic;
+ signal co5_1: std_logic;
+ signal wcount_10: std_logic;
+ signal co4_3: std_logic;
+ signal scuba_vhi: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal r_ctr_ci: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal co0_4: std_logic;
+ signal ircount_4: std_logic;
+ signal ircount_5: std_logic;
+ signal rcount_4: std_logic;
+ signal rcount_5: std_logic;
+ signal co1_4: std_logic;
+ signal ircount_6: std_logic;
+ signal ircount_7: std_logic;
+ signal rcount_6: std_logic;
+ signal rcount_7: std_logic;
+ signal co2_4: std_logic;
+ signal ircount_8: std_logic;
+ signal ircount_9: std_logic;
+ signal rcount_8: std_logic;
+ signal rcount_9: std_logic;
+ signal co3_4: std_logic;
+ signal ircount_10: std_logic;
+ signal co5_2: std_logic;
+ signal rcount_10: std_logic;
+ signal scuba_vlo: std_logic;
+ signal co4_4: std_logic;
+
+ -- local component declarations
+ component AGEB2
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; GE: out std_logic);
+ end component;
+ component ALEB2
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; LE: out std_logic);
+ end component;
+ component AND2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component CU2
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
+ end component;
+ component CB2
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ CON: in std_logic; CO: out std_logic; NC0: out std_logic;
+ NC1: out std_logic);
+ end component;
+ component FADD2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; COUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FD1P3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1S3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component FD1S3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component ROM16X1
+ -- synopsys translate_off
+ generic (initval : in String);
+ -- synopsys translate_on
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component XOR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component DP16KB
+ -- synopsys translate_off
+ generic (GSR : in String; WRITEMODE_B : in String;
+ CSDECODE_B : in std_logic_vector(2 downto 0);
+ CSDECODE_A : in std_logic_vector(2 downto 0);
+ WRITEMODE_A : in String; RESETMODE : in String;
+ REGMODE_B : in String; REGMODE_A : in String;
+ DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer);
+ -- synopsys translate_on
+ port (DIA0: in std_logic; DIA1: in std_logic;
+ DIA2: in std_logic; DIA3: in std_logic;
+ DIA4: in std_logic; DIA5: in std_logic;
+ DIA6: in std_logic; DIA7: in std_logic;
+ DIA8: in std_logic; DIA9: in std_logic;
+ DIA10: in std_logic; DIA11: in std_logic;
+ DIA12: in std_logic; DIA13: in std_logic;
+ DIA14: in std_logic; DIA15: in std_logic;
+ DIA16: in std_logic; DIA17: in std_logic;
+ ADA0: in std_logic; ADA1: in std_logic;
+ ADA2: in std_logic; ADA3: in std_logic;
+ ADA4: in std_logic; ADA5: in std_logic;
+ ADA6: in std_logic; ADA7: in std_logic;
+ ADA8: in std_logic; ADA9: in std_logic;
+ ADA10: in std_logic; ADA11: in std_logic;
+ ADA12: in std_logic; ADA13: in std_logic;
+ CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic;
+ CSA0: in std_logic; CSA1: in std_logic;
+ CSA2: in std_logic; RSTA: in std_logic;
+ DIB0: in std_logic; DIB1: in std_logic;
+ DIB2: in std_logic; DIB3: in std_logic;
+ DIB4: in std_logic; DIB5: in std_logic;
+ DIB6: in std_logic; DIB7: in std_logic;
+ DIB8: in std_logic; DIB9: in std_logic;
+ DIB10: in std_logic; DIB11: in std_logic;
+ DIB12: in std_logic; DIB13: in std_logic;
+ DIB14: in std_logic; DIB15: in std_logic;
+ DIB16: in std_logic; DIB17: in std_logic;
+ ADB0: in std_logic; ADB1: in std_logic;
+ ADB2: in std_logic; ADB3: in std_logic;
+ ADB4: in std_logic; ADB5: in std_logic;
+ ADB6: in std_logic; ADB7: in std_logic;
+ ADB8: in std_logic; ADB9: in std_logic;
+ ADB10: in std_logic; ADB11: in std_logic;
+ ADB12: in std_logic; ADB13: in std_logic;
+ CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic;
+ CSB0: in std_logic; CSB1: in std_logic;
+ CSB2: in std_logic; RSTB: in std_logic;
+ DOA0: out std_logic; DOA1: out std_logic;
+ DOA2: out std_logic; DOA3: out std_logic;
+ DOA4: out std_logic; DOA5: out std_logic;
+ DOA6: out std_logic; DOA7: out std_logic;
+ DOA8: out std_logic; DOA9: out std_logic;
+ DOA10: out std_logic; DOA11: out std_logic;
+ DOA12: out std_logic; DOA13: out std_logic;
+ DOA14: out std_logic; DOA15: out std_logic;
+ DOA16: out std_logic; DOA17: out std_logic;
+ DOB0: out std_logic; DOB1: out std_logic;
+ DOB2: out std_logic; DOB3: out std_logic;
+ DOB4: out std_logic; DOB5: out std_logic;
+ DOB6: out std_logic; DOB7: out std_logic;
+ DOB8: out std_logic; DOB9: out std_logic;
+ DOB10: out std_logic; DOB11: out std_logic;
+ DOB12: out std_logic; DOB13: out std_logic;
+ DOB14: out std_logic; DOB15: out std_logic;
+ DOB16: out std_logic; DOB17: out std_logic);
+ end component;
+ attribute initval : string;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute CSDECODE_B : string;
+ attribute CSDECODE_A : string;
+ attribute WRITEMODE_B : string;
+ attribute WRITEMODE_A : string;
+ attribute RESETMODE : string;
+ attribute REGMODE_B : string;
+ attribute REGMODE_A : string;
+ attribute DATA_WIDTH_B : string;
+ attribute DATA_WIDTH_A : string;
+ attribute GSR : string;
+ attribute initval of LUT4_1 : label is "0x3232";
+ attribute initval of LUT4_0 : label is "0x3232";
+ attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "test_fifo.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
+ attribute CSDECODE_B of pdp_ram_0_0_0 : label is "0b000";
+ attribute CSDECODE_A of pdp_ram_0_0_0 : label is "0b000";
+ attribute WRITEMODE_B of pdp_ram_0_0_0 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_0_0_0 : label is "NORMAL";
+ attribute GSR of pdp_ram_0_0_0 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_0_0 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_0_0_0 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_0_0_0 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_0_0_0 : label is "18";
+ attribute DATA_WIDTH_A of pdp_ram_0_0_0 : label is "18";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ AND2_t3: AND2
+ port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+ INV_3: INV
+ port map (A=>full_i, Z=>invout_1);
+
+ AND2_t2: AND2
+ port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+ INV_2: INV
+ port map (A=>empty_i, Z=>invout_0);
+
+ AND2_t1: AND2
+ port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
+
+ XOR2_t0: XOR2
+ port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
+
+ INV_1: INV
+ port map (A=>rden_i, Z=>rden_i_inv);
+
+ INV_0: INV
+ port map (A=>wren_i, Z=>wren_i_inv);
+
+ LUT4_1: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x3232")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i,
+ AD0=>empty_i, DO0=>empty_d);
+
+ LUT4_0: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x3232")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
+ AD0=>full_i, DO0=>full_d);
+
+ pdp_ram_0_0_0: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18,
+ DATA_WIDTH_A=> 18)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
+ DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
+ DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
+ DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
+ ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wcount_0,
+ ADA5=>wcount_1, ADA6=>wcount_2, ADA7=>wcount_3,
+ ADA8=>wcount_4, ADA9=>wcount_5, ADA10=>wcount_6,
+ ADA11=>wcount_7, ADA12=>wcount_8, ADA13=>wcount_9,
+ CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, CSA0=>scuba_vlo,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>scuba_vlo, ADB4=>rcount_0, ADB5=>rcount_1,
+ ADB6=>rcount_2, ADB7=>rcount_3, ADB8=>rcount_4,
+ ADB9=>rcount_5, ADB10=>rcount_6, ADB11=>rcount_7,
+ ADB12=>rcount_8, ADB13=>rcount_9, CEB=>rden_i, CLKB=>Clock,
+ WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>Q(0), DOB1=>Q(1), DOB2=>Q(2),
+ DOB3=>Q(3), DOB4=>Q(4), DOB5=>Q(5), DOB6=>Q(6), DOB7=>Q(7),
+ DOB8=>Q(8), DOB9=>Q(9), DOB10=>Q(10), DOB11=>Q(11),
+ DOB12=>Q(12), DOB13=>Q(13), DOB14=>Q(14), DOB15=>Q(15),
+ DOB16=>Q(16), DOB17=>Q(17));
+
+ FF_34: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_0);
+
+ FF_33: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_1);
+
+ FF_32: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_2);
+
+ FF_31: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_3);
+
+ FF_30: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_4);
+
+ FF_29: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_5);
+
+ FF_28: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_6);
+
+ FF_27: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_7);
+
+ FF_26: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_8);
+
+ FF_25: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_9);
+
+ FF_24: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_10);
+
+ FF_23: FD1S3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
+
+ FF_22: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
+
+ FF_21: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_0);
+
+ FF_20: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_19: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_18: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_17: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_16: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_5);
+
+ FF_15: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_6);
+
+ FF_14: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_7);
+
+ FF_13: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_8);
+
+ FF_12: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_9);
+
+ FF_11: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_10);
+
+ FF_10: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_0);
+
+ FF_9: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_1);
+
+ FF_8: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_2);
+
+ FF_7: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_3);
+
+ FF_6: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_4);
+
+ FF_5: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_5);
+
+ FF_4: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_6);
+
+ FF_3: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_7);
+
+ FF_2: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_8);
+
+ FF_1: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_9);
+
+ FF_0: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_10);
+
+ bdcnt_bctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con,
+ CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open);
+
+ bdcnt_bctr_0: CB2
+ port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1,
+ CON=>cnt_con, CO=>co0, NC0=>ifcount_0, NC1=>ifcount_1);
+
+ bdcnt_bctr_1: CB2
+ port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con,
+ CO=>co1, NC0=>ifcount_2, NC1=>ifcount_3);
+
+ bdcnt_bctr_2: CB2
+ port map (CI=>co1, PC0=>fcount_4, PC1=>fcount_5, CON=>cnt_con,
+ CO=>co2, NC0=>ifcount_4, NC1=>ifcount_5);
+
+ bdcnt_bctr_3: CB2
+ port map (CI=>co2, PC0=>fcount_6, PC1=>fcount_7, CON=>cnt_con,
+ CO=>co3, NC0=>ifcount_6, NC1=>ifcount_7);
+
+ bdcnt_bctr_4: CB2
+ port map (CI=>co3, PC0=>fcount_8, PC1=>fcount_9, CON=>cnt_con,
+ CO=>co4, NC0=>ifcount_8, NC1=>ifcount_9);
+
+ bdcnt_bctr_5: CB2
+ port map (CI=>co4, PC0=>fcount_10, PC1=>scuba_vlo, CON=>cnt_con,
+ CO=>co5, NC0=>ifcount_10, NC1=>open);
+
+ e_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open,
+ S1=>open);
+
+ e_cmp_0: ALEB2
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo,
+ CI=>cmp_ci, LE=>co0_1);
+
+ e_cmp_1: ALEB2
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co0_1, LE=>co1_1);
+
+ e_cmp_2: ALEB2
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co1_1, LE=>co2_1);
+
+ e_cmp_3: ALEB2
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co2_1, LE=>co3_1);
+
+ e_cmp_4: ALEB2
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co3_1, LE=>co4_1);
+
+ e_cmp_5: ALEB2
+ port map (A0=>fcount_10, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co4_1, LE=>cmp_le_1_c);
+
+ a0: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1,
+ S1=>open);
+
+ g_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open,
+ S1=>open);
+
+ g_cmp_0: AGEB2
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i,
+ CI=>cmp_ci_1, GE=>co0_2);
+
+ g_cmp_1: AGEB2
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i,
+ CI=>co0_2, GE=>co1_2);
+
+ g_cmp_2: AGEB2
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i,
+ CI=>co1_2, GE=>co2_2);
+
+ g_cmp_3: AGEB2
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i,
+ CI=>co2_2, GE=>co3_2);
+
+ g_cmp_4: AGEB2
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i,
+ CI=>co3_2, GE=>co4_2);
+
+ g_cmp_5: AGEB2
+ port map (A0=>fcount_10, A1=>scuba_vlo, B0=>wren_i_inv,
+ B1=>scuba_vlo, CI=>co4_2, GE=>cmp_ge_d1_c);
+
+ a1: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1,
+ S1=>open);
+
+ w_ctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open,
+ S1=>open);
+
+ w_ctr_0: CU2
+ port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3,
+ NC0=>iwcount_0, NC1=>iwcount_1);
+
+ w_ctr_1: CU2
+ port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_3,
+ NC0=>iwcount_2, NC1=>iwcount_3);
+
+ w_ctr_2: CU2
+ port map (CI=>co1_3, PC0=>wcount_4, PC1=>wcount_5, CO=>co2_3,
+ NC0=>iwcount_4, NC1=>iwcount_5);
+
+ w_ctr_3: CU2
+ port map (CI=>co2_3, PC0=>wcount_6, PC1=>wcount_7, CO=>co3_3,
+ NC0=>iwcount_6, NC1=>iwcount_7);
+
+ w_ctr_4: CU2
+ port map (CI=>co3_3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4_3,
+ NC0=>iwcount_8, NC1=>iwcount_9);
+
+ w_ctr_5: CU2
+ port map (CI=>co4_3, PC0=>wcount_10, PC1=>scuba_vlo, CO=>co5_1,
+ NC0=>iwcount_10, NC1=>open);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ r_ctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open,
+ S1=>open);
+
+ r_ctr_0: CU2
+ port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4,
+ NC0=>ircount_0, NC1=>ircount_1);
+
+ r_ctr_1: CU2
+ port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_4,
+ NC0=>ircount_2, NC1=>ircount_3);
+
+ r_ctr_2: CU2
+ port map (CI=>co1_4, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_4,
+ NC0=>ircount_4, NC1=>ircount_5);
+
+ r_ctr_3: CU2
+ port map (CI=>co2_4, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_4,
+ NC0=>ircount_6, NC1=>ircount_7);
+
+ r_ctr_4: CU2
+ port map (CI=>co3_4, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_4,
+ NC0=>ircount_8, NC1=>ircount_9);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ r_ctr_5: CU2
+ port map (CI=>co4_4, PC0=>rcount_10, PC1=>scuba_vlo, CO=>co5_2,
+ NC0=>ircount_10, NC1=>open);
+
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of test_fifo is
+ for Structure
+ for all:AGEB2 use entity ecp2m.AGEB2(V); end for;
+ for all:ALEB2 use entity ecp2m.ALEB2(V); end for;
+ for all:AND2 use entity ecp2m.AND2(V); end for;
+ for all:CU2 use entity ecp2m.CU2(V); end for;
+ for all:CB2 use entity ecp2m.CB2(V); end for;
+ for all:FADD2B use entity ecp2m.FADD2B(V); end for;
+ for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
+ for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for;
+ for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for;
+ for all:INV use entity ecp2m.INV(V); end for;
+ for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for;
+ for all:VHI use entity ecp2m.VHI(V); end for;
+ for all:VLO use entity ecp2m.VLO(V); end for;
+ for all:XOR2 use entity ecp2m.XOR2(V); end for;
+ for all:DP16KB use entity ecp2m.DP16KB(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v8.0_PROD_Build (41)
+-- Module Version: 4.7
+-- Mon Dec 14 14:54:16 2009
+
+-- parameterized module component declaration
+component test_fifo
+ port (Data: in std_logic_vector(17 downto 0); Clock: in std_logic;
+ WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic;
+ Q: out std_logic_vector(17 downto 0); Empty: out std_logic;
+ Full: out std_logic);
+end component;
+
+-- parameterized module component instance
+__ : test_fifo
+ port map (Data(17 downto 0)=>__, Clock=>__, WrEn=>__, RdEn=>__,
+ Reset=>__, Q(17 downto 0)=>__, Empty=>__, Full=>__);
--- /dev/null
+[Device]\r
+Family=latticeecp2m\r
+PartType=LFE2M100E\r
+PartName=LFE2M100E-6F900C\r
+SpeedGrade=-6\r
+Package=FPBGA900\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=FIFO_DC\r
+CoreRevision=5.2\r
+ModuleName=testfifo\r
+SourceFormat=VHDL\r
+ParameterFileVersion=1.0\r
+Date=11/18/2009\r
+Time=17:17:38\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+FIFOImp=EBR Based\r
+Depth=256\r
+Width=96\r
+RDepth=256\r
+RWidth=96\r
+regout=0\r
+CtrlByRdEn=0\r
+EmpFlg=0\r
+PeMode=Static - Dual Threshold\r
+PeAssert=10\r
+PeDeassert=12\r
+FullFlg=0\r
+PfMode=Static - Dual Threshold\r
+PfAssert=508\r
+PfDeassert=506\r
+RDataCount=0\r
+WDataCount=0\r
+EnECC=0\r
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23)
+-- Module Version: 5.2
+--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 256 -width 96 -depth 256 -rdata_width 96 -no_enable -pe -1 -pf -1 -e
+
+-- Wed Nov 18 17:17:38 2009
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity testfifo is
+ port (
+ Data: in std_logic_vector(95 downto 0);
+ WrClock: in std_logic;
+ RdClock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ RPReset: in std_logic;
+ Q: out std_logic_vector(95 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic);
+end testfifo;
+
+architecture Structure of testfifo is
+
+ -- internal signal declarations
+ signal invout_1: std_logic;
+ signal invout_0: std_logic;
+ signal w_g2b_xor_cluster_1: std_logic;
+ signal r_g2b_xor_cluster_1: std_logic;
+ signal w_gdata_0: std_logic;
+ signal w_gdata_1: std_logic;
+ signal w_gdata_2: std_logic;
+ signal w_gdata_3: std_logic;
+ signal w_gdata_4: std_logic;
+ signal w_gdata_5: std_logic;
+ signal w_gdata_6: std_logic;
+ signal w_gdata_7: std_logic;
+ signal wptr_0: std_logic;
+ signal wptr_1: std_logic;
+ signal wptr_2: std_logic;
+ signal wptr_3: std_logic;
+ signal wptr_4: std_logic;
+ signal wptr_5: std_logic;
+ signal wptr_6: std_logic;
+ signal wptr_7: std_logic;
+ signal wptr_8: std_logic;
+ signal r_gdata_0: std_logic;
+ signal r_gdata_1: std_logic;
+ signal r_gdata_2: std_logic;
+ signal r_gdata_3: std_logic;
+ signal r_gdata_4: std_logic;
+ signal r_gdata_5: std_logic;
+ signal r_gdata_6: std_logic;
+ signal r_gdata_7: std_logic;
+ signal rptr_0: std_logic;
+ signal rptr_1: std_logic;
+ signal rptr_2: std_logic;
+ signal rptr_3: std_logic;
+ signal rptr_4: std_logic;
+ signal rptr_5: std_logic;
+ signal rptr_6: std_logic;
+ signal rptr_7: std_logic;
+ signal rptr_8: std_logic;
+ signal w_gcount_0: std_logic;
+ signal w_gcount_1: std_logic;
+ signal w_gcount_2: std_logic;
+ signal w_gcount_3: std_logic;
+ signal w_gcount_4: std_logic;
+ signal w_gcount_5: std_logic;
+ signal w_gcount_6: std_logic;
+ signal w_gcount_7: std_logic;
+ signal w_gcount_8: std_logic;
+ signal r_gcount_0: std_logic;
+ signal r_gcount_1: std_logic;
+ signal r_gcount_2: std_logic;
+ signal r_gcount_3: std_logic;
+ signal r_gcount_4: std_logic;
+ signal r_gcount_5: std_logic;
+ signal r_gcount_6: std_logic;
+ signal r_gcount_7: std_logic;
+ signal r_gcount_8: std_logic;
+ signal w_gcount_r20: std_logic;
+ signal w_gcount_r0: std_logic;
+ signal w_gcount_r21: std_logic;
+ signal w_gcount_r1: std_logic;
+ signal w_gcount_r22: std_logic;
+ signal w_gcount_r2: std_logic;
+ signal w_gcount_r23: std_logic;
+ signal w_gcount_r3: std_logic;
+ signal w_gcount_r24: std_logic;
+ signal w_gcount_r4: std_logic;
+ signal w_gcount_r25: std_logic;
+ signal w_gcount_r5: std_logic;
+ signal w_gcount_r26: std_logic;
+ signal w_gcount_r6: std_logic;
+ signal w_gcount_r27: std_logic;
+ signal w_gcount_r7: std_logic;
+ signal w_gcount_r28: std_logic;
+ signal w_gcount_r8: std_logic;
+ signal r_gcount_w20: std_logic;
+ signal r_gcount_w0: std_logic;
+ signal r_gcount_w21: std_logic;
+ signal r_gcount_w1: std_logic;
+ signal r_gcount_w22: std_logic;
+ signal r_gcount_w2: std_logic;
+ signal r_gcount_w23: std_logic;
+ signal r_gcount_w3: std_logic;
+ signal r_gcount_w24: std_logic;
+ signal r_gcount_w4: std_logic;
+ signal r_gcount_w25: std_logic;
+ signal r_gcount_w5: std_logic;
+ signal r_gcount_w26: std_logic;
+ signal r_gcount_w6: std_logic;
+ signal r_gcount_w27: std_logic;
+ signal r_gcount_w7: std_logic;
+ signal r_gcount_w28: std_logic;
+ signal r_gcount_w8: std_logic;
+ signal empty_i: std_logic;
+ signal rRst: std_logic;
+ signal full_i: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal w_gctr_ci: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal co0: std_logic;
+ signal iwcount_4: std_logic;
+ signal iwcount_5: std_logic;
+ signal co1: std_logic;
+ signal iwcount_6: std_logic;
+ signal iwcount_7: std_logic;
+ signal co2: std_logic;
+ signal iwcount_8: std_logic;
+ signal co4: std_logic;
+ signal wcount_8: std_logic;
+ signal co3: std_logic;
+ signal scuba_vhi: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal r_gctr_ci: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal co0_1: std_logic;
+ signal ircount_4: std_logic;
+ signal ircount_5: std_logic;
+ signal co1_1: std_logic;
+ signal ircount_6: std_logic;
+ signal ircount_7: std_logic;
+ signal co2_1: std_logic;
+ signal ircount_8: std_logic;
+ signal co4_1: std_logic;
+ signal rcount_8: std_logic;
+ signal co3_1: std_logic;
+ signal rden_i: std_logic;
+ signal cmp_ci: std_logic;
+ signal wcount_r0: std_logic;
+ signal wcount_r1: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal co0_2: std_logic;
+ signal wcount_r2: std_logic;
+ signal wcount_r3: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal co1_2: std_logic;
+ signal wcount_r4: std_logic;
+ signal w_g2b_xor_cluster_0: std_logic;
+ signal rcount_4: std_logic;
+ signal rcount_5: std_logic;
+ signal co2_2: std_logic;
+ signal wcount_r6: std_logic;
+ signal wcount_r7: std_logic;
+ signal rcount_6: std_logic;
+ signal rcount_7: std_logic;
+ signal co3_2: std_logic;
+ signal empty_cmp_clr: std_logic;
+ signal empty_cmp_set: std_logic;
+ signal empty_d: std_logic;
+ signal empty_d_c: std_logic;
+ signal wren_i: std_logic;
+ signal cmp_ci_1: std_logic;
+ signal rcount_w0: std_logic;
+ signal rcount_w1: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal co0_3: std_logic;
+ signal rcount_w2: std_logic;
+ signal rcount_w3: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_3: std_logic;
+ signal co1_3: std_logic;
+ signal rcount_w4: std_logic;
+ signal r_g2b_xor_cluster_0: std_logic;
+ signal wcount_4: std_logic;
+ signal wcount_5: std_logic;
+ signal co2_3: std_logic;
+ signal rcount_w6: std_logic;
+ signal rcount_w7: std_logic;
+ signal wcount_6: std_logic;
+ signal wcount_7: std_logic;
+ signal co3_3: std_logic;
+ signal full_cmp_clr: std_logic;
+ signal full_cmp_set: std_logic;
+ signal full_d: std_logic;
+ signal full_d_c: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component AGEB2
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; GE: out std_logic);
+ end component;
+ component AND2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component CU2
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
+ end component;
+ component FADD2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; COUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FD1P3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ PD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1P3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1S3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component FD1S3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component OR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component ROM16X1
+ -- synopsys translate_off
+ generic (initval : in String);
+ -- synopsys translate_on
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component XOR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component PDPW16KB
+ -- synopsys translate_off
+ generic (CSDECODE_R : in std_logic_vector(2 downto 0);
+ CSDECODE_W : in std_logic_vector(2 downto 0);
+ GSR : in String; RESETMODE : in String;
+ REGMODE : in String; DATA_WIDTH_R : in Integer;
+ DATA_WIDTH_W : in Integer);
+ -- synopsys translate_on
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
+ DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
+ DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
+ DI12: in std_logic; DI13: in std_logic;
+ DI14: in std_logic; DI15: in std_logic;
+ DI16: in std_logic; DI17: in std_logic;
+ DI18: in std_logic; DI19: in std_logic;
+ DI20: in std_logic; DI21: in std_logic;
+ DI22: in std_logic; DI23: in std_logic;
+ DI24: in std_logic; DI25: in std_logic;
+ DI26: in std_logic; DI27: in std_logic;
+ DI28: in std_logic; DI29: in std_logic;
+ DI30: in std_logic; DI31: in std_logic;
+ DI32: in std_logic; DI33: in std_logic;
+ DI34: in std_logic; DI35: in std_logic;
+ ADW0: in std_logic; ADW1: in std_logic;
+ ADW2: in std_logic; ADW3: in std_logic;
+ ADW4: in std_logic; ADW5: in std_logic;
+ ADW6: in std_logic; ADW7: in std_logic;
+ ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic;
+ BE2: in std_logic; BE3: in std_logic; CEW: in std_logic;
+ CLKW: in std_logic; CSW0: in std_logic;
+ CSW1: in std_logic; CSW2: in std_logic;
+ ADR0: in std_logic; ADR1: in std_logic;
+ ADR2: in std_logic; ADR3: in std_logic;
+ ADR4: in std_logic; ADR5: in std_logic;
+ ADR6: in std_logic; ADR7: in std_logic;
+ ADR8: in std_logic; ADR9: in std_logic;
+ ADR10: in std_logic; ADR11: in std_logic;
+ ADR12: in std_logic; ADR13: in std_logic;
+ CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic;
+ CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic;
+ DO4: out std_logic; DO5: out std_logic;
+ DO6: out std_logic; DO7: out std_logic;
+ DO8: out std_logic; DO9: out std_logic;
+ DO10: out std_logic; DO11: out std_logic;
+ DO12: out std_logic; DO13: out std_logic;
+ DO14: out std_logic; DO15: out std_logic;
+ DO16: out std_logic; DO17: out std_logic;
+ DO18: out std_logic; DO19: out std_logic;
+ DO20: out std_logic; DO21: out std_logic;
+ DO22: out std_logic; DO23: out std_logic;
+ DO24: out std_logic; DO25: out std_logic;
+ DO26: out std_logic; DO27: out std_logic;
+ DO28: out std_logic; DO29: out std_logic;
+ DO30: out std_logic; DO31: out std_logic;
+ DO32: out std_logic; DO33: out std_logic;
+ DO34: out std_logic; DO35: out std_logic);
+ end component;
+ attribute initval : string;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute CSDECODE_R : string;
+ attribute CSDECODE_W : string;
+ attribute RESETMODE : string;
+ attribute REGMODE : string;
+ attribute DATA_WIDTH_R : string;
+ attribute DATA_WIDTH_W : string;
+ attribute GSR : string;
+ attribute initval of LUT4_21 : label is "0x6996";
+ attribute initval of LUT4_20 : label is "0x6996";
+ attribute initval of LUT4_19 : label is "0x6996";
+ attribute initval of LUT4_18 : label is "0x6996";
+ attribute initval of LUT4_17 : label is "0x6996";
+ attribute initval of LUT4_16 : label is "0x6996";
+ attribute initval of LUT4_15 : label is "0x6996";
+ attribute initval of LUT4_14 : label is "0x6996";
+ attribute initval of LUT4_13 : label is "0x6996";
+ attribute initval of LUT4_12 : label is "0x6996";
+ attribute initval of LUT4_11 : label is "0x6996";
+ attribute initval of LUT4_10 : label is "0x6996";
+ attribute initval of LUT4_9 : label is "0x6996";
+ attribute initval of LUT4_8 : label is "0x6996";
+ attribute initval of LUT4_7 : label is "0x6996";
+ attribute initval of LUT4_6 : label is "0x6996";
+ attribute initval of LUT4_5 : label is "0x6996";
+ attribute initval of LUT4_4 : label is "0x6996";
+ attribute initval of LUT4_3 : label is "0x0410";
+ attribute initval of LUT4_2 : label is "0x1004";
+ attribute initval of LUT4_1 : label is "0x0140";
+ attribute initval of LUT4_0 : label is "0x4001";
+ attribute MEM_LPC_FILE of pdp_ram_0_0_2 : label is "testfifo.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_2 : label is "";
+ attribute CSDECODE_R of pdp_ram_0_0_2 : label is "0b000";
+ attribute CSDECODE_W of pdp_ram_0_0_2 : label is "0b001";
+ attribute GSR of pdp_ram_0_0_2 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_0_2 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_0_0_2 : label is "NOREG";
+ attribute DATA_WIDTH_R of pdp_ram_0_0_2 : label is "36";
+ attribute DATA_WIDTH_W of pdp_ram_0_0_2 : label is "36";
+ attribute MEM_LPC_FILE of pdp_ram_0_1_1 : label is "testfifo.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_1_1 : label is "";
+ attribute CSDECODE_R of pdp_ram_0_1_1 : label is "0b000";
+ attribute CSDECODE_W of pdp_ram_0_1_1 : label is "0b001";
+ attribute GSR of pdp_ram_0_1_1 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_1_1 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_0_1_1 : label is "NOREG";
+ attribute DATA_WIDTH_R of pdp_ram_0_1_1 : label is "36";
+ attribute DATA_WIDTH_W of pdp_ram_0_1_1 : label is "36";
+ attribute MEM_LPC_FILE of pdp_ram_0_2_0 : label is "testfifo.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_2_0 : label is "";
+ attribute CSDECODE_R of pdp_ram_0_2_0 : label is "0b000";
+ attribute CSDECODE_W of pdp_ram_0_2_0 : label is "0b001";
+ attribute GSR of pdp_ram_0_2_0 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_2_0 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_0_2_0 : label is "NOREG";
+ attribute DATA_WIDTH_R of pdp_ram_0_2_0 : label is "36";
+ attribute DATA_WIDTH_W of pdp_ram_0_2_0 : label is "36";
+ attribute GSR of FF_91 : label is "ENABLED";
+ attribute GSR of FF_90 : label is "ENABLED";
+ attribute GSR of FF_89 : label is "ENABLED";
+ attribute GSR of FF_88 : label is "ENABLED";
+ attribute GSR of FF_87 : label is "ENABLED";
+ attribute GSR of FF_86 : label is "ENABLED";
+ attribute GSR of FF_85 : label is "ENABLED";
+ attribute GSR of FF_84 : label is "ENABLED";
+ attribute GSR of FF_83 : label is "ENABLED";
+ attribute GSR of FF_82 : label is "ENABLED";
+ attribute GSR of FF_81 : label is "ENABLED";
+ attribute GSR of FF_80 : label is "ENABLED";
+ attribute GSR of FF_79 : label is "ENABLED";
+ attribute GSR of FF_78 : label is "ENABLED";
+ attribute GSR of FF_77 : label is "ENABLED";
+ attribute GSR of FF_76 : label is "ENABLED";
+ attribute GSR of FF_75 : label is "ENABLED";
+ attribute GSR of FF_74 : label is "ENABLED";
+ attribute GSR of FF_73 : label is "ENABLED";
+ attribute GSR of FF_72 : label is "ENABLED";
+ attribute GSR of FF_71 : label is "ENABLED";
+ attribute GSR of FF_70 : label is "ENABLED";
+ attribute GSR of FF_69 : label is "ENABLED";
+ attribute GSR of FF_68 : label is "ENABLED";
+ attribute GSR of FF_67 : label is "ENABLED";
+ attribute GSR of FF_66 : label is "ENABLED";
+ attribute GSR of FF_65 : label is "ENABLED";
+ attribute GSR of FF_64 : label is "ENABLED";
+ attribute GSR of FF_63 : label is "ENABLED";
+ attribute GSR of FF_62 : label is "ENABLED";
+ attribute GSR of FF_61 : label is "ENABLED";
+ attribute GSR of FF_60 : label is "ENABLED";
+ attribute GSR of FF_59 : label is "ENABLED";
+ attribute GSR of FF_58 : label is "ENABLED";
+ attribute GSR of FF_57 : label is "ENABLED";
+ attribute GSR of FF_56 : label is "ENABLED";
+ attribute GSR of FF_55 : label is "ENABLED";
+ attribute GSR of FF_54 : label is "ENABLED";
+ attribute GSR of FF_53 : label is "ENABLED";
+ attribute GSR of FF_52 : label is "ENABLED";
+ attribute GSR of FF_51 : label is "ENABLED";
+ attribute GSR of FF_50 : label is "ENABLED";
+ attribute GSR of FF_49 : label is "ENABLED";
+ attribute GSR of FF_48 : label is "ENABLED";
+ attribute GSR of FF_47 : label is "ENABLED";
+ attribute GSR of FF_46 : label is "ENABLED";
+ attribute GSR of FF_45 : label is "ENABLED";
+ attribute GSR of FF_44 : label is "ENABLED";
+ attribute GSR of FF_43 : label is "ENABLED";
+ attribute GSR of FF_42 : label is "ENABLED";
+ attribute GSR of FF_41 : label is "ENABLED";
+ attribute GSR of FF_40 : label is "ENABLED";
+ attribute GSR of FF_39 : label is "ENABLED";
+ attribute GSR of FF_38 : label is "ENABLED";
+ attribute GSR of FF_37 : label is "ENABLED";
+ attribute GSR of FF_36 : label is "ENABLED";
+ attribute GSR of FF_35 : label is "ENABLED";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ AND2_t18: AND2
+ port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+ INV_1: INV
+ port map (A=>full_i, Z=>invout_1);
+
+ AND2_t17: AND2
+ port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+ INV_0: INV
+ port map (A=>empty_i, Z=>invout_0);
+
+ OR2_t16: OR2
+ port map (A=>Reset, B=>RPReset, Z=>rRst);
+
+ XOR2_t15: XOR2
+ port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
+
+ XOR2_t14: XOR2
+ port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
+
+ XOR2_t13: XOR2
+ port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
+
+ XOR2_t12: XOR2
+ port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
+
+ XOR2_t11: XOR2
+ port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
+
+ XOR2_t10: XOR2
+ port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
+
+ XOR2_t9: XOR2
+ port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
+
+ XOR2_t8: XOR2
+ port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
+
+ XOR2_t7: XOR2
+ port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
+
+ XOR2_t6: XOR2
+ port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
+
+ XOR2_t5: XOR2
+ port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
+
+ XOR2_t4: XOR2
+ port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
+
+ XOR2_t3: XOR2
+ port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
+
+ XOR2_t2: XOR2
+ port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
+
+ XOR2_t1: XOR2
+ port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
+
+ XOR2_t0: XOR2
+ port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
+
+ LUT4_21: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
+ AD1=>w_gcount_r27, AD0=>w_gcount_r28,
+ DO0=>w_g2b_xor_cluster_0);
+
+ LUT4_20: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
+ AD1=>w_gcount_r23, AD0=>w_gcount_r24,
+ DO0=>w_g2b_xor_cluster_1);
+
+ LUT4_19: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>wcount_r7);
+
+ LUT4_18: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
+ AD1=>w_gcount_r28, AD0=>scuba_vlo, DO0=>wcount_r6);
+
+ LUT4_17: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
+ AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4);
+
+ LUT4_16: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24,
+ AD1=>w_gcount_r25, AD0=>wcount_r6, DO0=>wcount_r3);
+
+ LUT4_15: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23,
+ AD1=>w_gcount_r24, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r2);
+
+ LUT4_14: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r1);
+
+ LUT4_13: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_gcount_r20, AD0=>scuba_vlo, DO0=>wcount_r0);
+
+ LUT4_12: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
+ AD1=>r_gcount_w27, AD0=>r_gcount_w28,
+ DO0=>r_g2b_xor_cluster_0);
+
+ LUT4_11: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
+ AD1=>r_gcount_w23, AD0=>r_gcount_w24,
+ DO0=>r_g2b_xor_cluster_1);
+
+ LUT4_10: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>rcount_w7);
+
+ LUT4_9: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
+ AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w6);
+
+ LUT4_8: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
+ AD1=>r_gcount_w26, AD0=>rcount_w7, DO0=>rcount_w4);
+
+ LUT4_7: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24,
+ AD1=>r_gcount_w25, AD0=>rcount_w6, DO0=>rcount_w3);
+
+ LUT4_6: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
+ AD1=>r_gcount_w24, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w2);
+
+ LUT4_5: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
+ AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w1);
+
+ LUT4_4: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
+ AD1=>r_gcount_w20, AD0=>scuba_vlo, DO0=>rcount_w0);
+
+ LUT4_3: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x0410")
+ -- synopsys translate_on
+ port map (AD3=>rptr_8, AD2=>rcount_8, AD1=>w_gcount_r28,
+ AD0=>scuba_vlo, DO0=>empty_cmp_set);
+
+ LUT4_2: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x1004")
+ -- synopsys translate_on
+ port map (AD3=>rptr_8, AD2=>rcount_8, AD1=>w_gcount_r28,
+ AD0=>scuba_vlo, DO0=>empty_cmp_clr);
+
+ LUT4_1: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x0140")
+ -- synopsys translate_on
+ port map (AD3=>wptr_8, AD2=>wcount_8, AD1=>r_gcount_w28,
+ AD0=>scuba_vlo, DO0=>full_cmp_set);
+
+ LUT4_0: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x4001")
+ -- synopsys translate_on
+ port map (AD3=>wptr_8, AD2=>wcount_8, AD1=>r_gcount_w28,
+ AD0=>scuba_vlo, DO0=>full_cmp_clr);
+
+ pdp_ram_0_0_2: PDPW16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "000", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "NOREG", DATA_WIDTH_R=> 36,
+ DATA_WIDTH_W=> 36)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
+ DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
+ DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
+ DI18=>Data(18), DI19=>Data(19), DI20=>Data(20),
+ DI21=>Data(21), DI22=>Data(22), DI23=>Data(23),
+ DI24=>Data(24), DI25=>Data(25), DI26=>Data(26),
+ DI27=>Data(27), DI28=>Data(28), DI29=>Data(29),
+ DI30=>Data(30), DI31=>Data(31), DI32=>Data(32),
+ DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), ADW0=>wptr_0,
+ ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, ADW4=>wptr_4,
+ ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>wptr_7, ADW8=>scuba_vlo,
+ BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi,
+ BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi,
+ CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo,
+ ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2,
+ ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6,
+ ADR12=>rptr_7, ADR13=>scuba_vlo, CER=>rden_i, CLKR=>RdClock,
+ CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), DO3=>Q(21),
+ DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), DO8=>Q(26),
+ DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), DO12=>Q(30),
+ DO13=>Q(31), DO14=>Q(32), DO15=>Q(33), DO16=>Q(34),
+ DO17=>Q(35), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3),
+ DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8),
+ DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), DO30=>Q(12),
+ DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), DO34=>Q(16),
+ DO35=>Q(17));
+
+ pdp_ram_0_1_1: PDPW16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "000", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "NOREG", DATA_WIDTH_R=> 36,
+ DATA_WIDTH_W=> 36)
+ -- synopsys translate_on
+ port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38),
+ DI3=>Data(39), DI4=>Data(40), DI5=>Data(41), DI6=>Data(42),
+ DI7=>Data(43), DI8=>Data(44), DI9=>Data(45), DI10=>Data(46),
+ DI11=>Data(47), DI12=>Data(48), DI13=>Data(49),
+ DI14=>Data(50), DI15=>Data(51), DI16=>Data(52),
+ DI17=>Data(53), DI18=>Data(54), DI19=>Data(55),
+ DI20=>Data(56), DI21=>Data(57), DI22=>Data(58),
+ DI23=>Data(59), DI24=>Data(60), DI25=>Data(61),
+ DI26=>Data(62), DI27=>Data(63), DI28=>Data(64),
+ DI29=>Data(65), DI30=>Data(66), DI31=>Data(67),
+ DI32=>Data(68), DI33=>Data(69), DI34=>Data(70),
+ DI35=>Data(71), ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2,
+ ADW3=>wptr_3, ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>wptr_6,
+ ADW7=>wptr_7, ADW8=>scuba_vlo, BE0=>scuba_vhi,
+ BE1=>scuba_vhi, BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i,
+ CLKW=>WrClock, CSW0=>scuba_vhi, CSW1=>scuba_vlo,
+ CSW2=>scuba_vlo, ADR0=>scuba_vlo, ADR1=>scuba_vlo,
+ ADR2=>scuba_vlo, ADR3=>scuba_vlo, ADR4=>scuba_vlo,
+ ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, ADR8=>rptr_3,
+ ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6, ADR12=>rptr_7,
+ ADR13=>scuba_vlo, CER=>rden_i, CLKR=>RdClock,
+ CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>Q(54), DO1=>Q(55), DO2=>Q(56), DO3=>Q(57),
+ DO4=>Q(58), DO5=>Q(59), DO6=>Q(60), DO7=>Q(61), DO8=>Q(62),
+ DO9=>Q(63), DO10=>Q(64), DO11=>Q(65), DO12=>Q(66),
+ DO13=>Q(67), DO14=>Q(68), DO15=>Q(69), DO16=>Q(70),
+ DO17=>Q(71), DO18=>Q(36), DO19=>Q(37), DO20=>Q(38),
+ DO21=>Q(39), DO22=>Q(40), DO23=>Q(41), DO24=>Q(42),
+ DO25=>Q(43), DO26=>Q(44), DO27=>Q(45), DO28=>Q(46),
+ DO29=>Q(47), DO30=>Q(48), DO31=>Q(49), DO32=>Q(50),
+ DO33=>Q(51), DO34=>Q(52), DO35=>Q(53));
+
+ pdp_ram_0_2_0: PDPW16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "000", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "NOREG", DATA_WIDTH_R=> 36,
+ DATA_WIDTH_W=> 36)
+ -- synopsys translate_on
+ port map (DI0=>Data(72), DI1=>Data(73), DI2=>Data(74),
+ DI3=>Data(75), DI4=>Data(76), DI5=>Data(77), DI6=>Data(78),
+ DI7=>Data(79), DI8=>Data(80), DI9=>Data(81), DI10=>Data(82),
+ DI11=>Data(83), DI12=>Data(84), DI13=>Data(85),
+ DI14=>Data(86), DI15=>Data(87), DI16=>Data(88),
+ DI17=>Data(89), DI18=>Data(90), DI19=>Data(91),
+ DI20=>Data(92), DI21=>Data(93), DI22=>Data(94),
+ DI23=>Data(95), DI24=>scuba_vlo, DI25=>scuba_vlo,
+ DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo,
+ DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo,
+ DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo,
+ DI35=>scuba_vlo, ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2,
+ ADW3=>wptr_3, ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>wptr_6,
+ ADW7=>wptr_7, ADW8=>scuba_vlo, BE0=>scuba_vhi,
+ BE1=>scuba_vhi, BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i,
+ CLKW=>WrClock, CSW0=>scuba_vhi, CSW1=>scuba_vlo,
+ CSW2=>scuba_vlo, ADR0=>scuba_vlo, ADR1=>scuba_vlo,
+ ADR2=>scuba_vlo, ADR3=>scuba_vlo, ADR4=>scuba_vlo,
+ ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, ADR8=>rptr_3,
+ ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6, ADR12=>rptr_7,
+ ADR13=>scuba_vlo, CER=>rden_i, CLKR=>RdClock,
+ CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>Q(90), DO1=>Q(91), DO2=>Q(92), DO3=>Q(93),
+ DO4=>Q(94), DO5=>Q(95), DO6=>open, DO7=>open, DO8=>open,
+ DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
+ DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>Q(72),
+ DO19=>Q(73), DO20=>Q(74), DO21=>Q(75), DO22=>Q(76),
+ DO23=>Q(77), DO24=>Q(78), DO25=>Q(79), DO26=>Q(80),
+ DO27=>Q(81), DO28=>Q(82), DO29=>Q(83), DO30=>Q(84),
+ DO31=>Q(85), DO32=>Q(86), DO33=>Q(87), DO34=>Q(88),
+ DO35=>Q(89));
+
+ FF_91: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
+ Q=>wcount_0);
+
+ FF_90: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_89: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_88: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_87: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_86: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_5);
+
+ FF_85: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_6);
+
+ FF_84: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_7);
+
+ FF_83: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_8);
+
+ FF_82: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_0);
+
+ FF_81: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_1);
+
+ FF_80: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_2);
+
+ FF_79: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_3);
+
+ FF_78: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_4);
+
+ FF_77: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_5);
+
+ FF_76: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_6);
+
+ FF_75: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_7);
+
+ FF_74: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_8);
+
+ FF_73: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_0);
+
+ FF_72: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_1);
+
+ FF_71: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_2);
+
+ FF_70: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_3);
+
+ FF_69: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_4);
+
+ FF_68: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_5);
+
+ FF_67: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_6);
+
+ FF_66: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_7);
+
+ FF_65: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_8);
+
+ FF_64: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
+ Q=>rcount_0);
+
+ FF_63: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_1);
+
+ FF_62: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_2);
+
+ FF_61: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_3);
+
+ FF_60: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_4);
+
+ FF_59: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_5);
+
+ FF_58: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_6);
+
+ FF_57: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_7);
+
+ FF_56: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_8);
+
+ FF_55: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_0);
+
+ FF_54: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_1);
+
+ FF_53: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_2);
+
+ FF_52: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_3);
+
+ FF_51: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_4);
+
+ FF_50: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_5);
+
+ FF_49: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_6);
+
+ FF_48: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_7);
+
+ FF_47: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_8);
+
+ FF_46: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_0);
+
+ FF_45: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_1);
+
+ FF_44: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_2);
+
+ FF_43: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_3);
+
+ FF_42: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_4);
+
+ FF_41: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_5);
+
+ FF_40: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_6);
+
+ FF_39: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_7);
+
+ FF_38: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_8);
+
+ FF_37: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
+
+ FF_36: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
+
+ FF_35: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
+
+ FF_34: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
+
+ FF_33: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
+
+ FF_32: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
+
+ FF_31: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
+
+ FF_30: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
+
+ FF_29: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
+
+ FF_28: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
+
+ FF_27: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
+
+ FF_26: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
+
+ FF_25: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
+
+ FF_24: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
+
+ FF_23: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
+
+ FF_22: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
+
+ FF_21: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
+
+ FF_20: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
+
+ FF_19: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r20);
+
+ FF_18: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r21);
+
+ FF_17: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r22);
+
+ FF_16: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r23);
+
+ FF_15: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r24);
+
+ FF_14: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r25);
+
+ FF_13: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r26);
+
+ FF_12: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r27);
+
+ FF_11: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r28);
+
+ FF_10: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
+
+ FF_9: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
+
+ FF_8: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
+
+ FF_7: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
+
+ FF_6: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
+
+ FF_5: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
+
+ FF_4: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
+
+ FF_3: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
+
+ FF_2: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
+
+ FF_1: FD1S3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
+
+ FF_0: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
+
+ w_gctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
+ S1=>open);
+
+ w_gctr_0: CU2
+ port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
+ NC0=>iwcount_0, NC1=>iwcount_1);
+
+ w_gctr_1: CU2
+ port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
+ NC0=>iwcount_2, NC1=>iwcount_3);
+
+ w_gctr_2: CU2
+ port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
+ NC0=>iwcount_4, NC1=>iwcount_5);
+
+ w_gctr_3: CU2
+ port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
+ NC0=>iwcount_6, NC1=>iwcount_7);
+
+ w_gctr_4: CU2
+ port map (CI=>co3, PC0=>wcount_8, PC1=>scuba_vlo, CO=>co4,
+ NC0=>iwcount_8, NC1=>open);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ r_gctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
+ S1=>open);
+
+ r_gctr_0: CU2
+ port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
+ NC0=>ircount_0, NC1=>ircount_1);
+
+ r_gctr_1: CU2
+ port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
+ NC0=>ircount_2, NC1=>ircount_3);
+
+ r_gctr_2: CU2
+ port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
+ NC0=>ircount_4, NC1=>ircount_5);
+
+ r_gctr_3: CU2
+ port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
+ NC0=>ircount_6, NC1=>ircount_7);
+
+ r_gctr_4: CU2
+ port map (CI=>co3_1, PC0=>rcount_8, PC1=>scuba_vlo, CO=>co4_1,
+ NC0=>ircount_8, NC1=>open);
+
+ empty_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
+ CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
+
+ empty_cmp_0: AGEB2
+ port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0,
+ B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
+
+ empty_cmp_1: AGEB2
+ port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2,
+ B1=>wcount_r3, CI=>co0_2, GE=>co1_2);
+
+ empty_cmp_2: AGEB2
+ port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4,
+ B1=>w_g2b_xor_cluster_0, CI=>co1_2, GE=>co2_2);
+
+ empty_cmp_3: AGEB2
+ port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6,
+ B1=>wcount_r7, CI=>co2_2, GE=>co3_2);
+
+ empty_cmp_4: AGEB2
+ port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr,
+ B1=>scuba_vlo, CI=>co3_2, GE=>empty_d_c);
+
+ a0: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
+ S1=>open);
+
+ full_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
+ CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
+
+ full_cmp_0: AGEB2
+ port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0,
+ B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
+
+ full_cmp_1: AGEB2
+ port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2,
+ B1=>rcount_w3, CI=>co0_3, GE=>co1_3);
+
+ full_cmp_2: AGEB2
+ port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4,
+ B1=>r_g2b_xor_cluster_0, CI=>co1_3, GE=>co2_3);
+
+ full_cmp_3: AGEB2
+ port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6,
+ B1=>rcount_w7, CI=>co2_3, GE=>co3_3);
+
+ full_cmp_4: AGEB2
+ port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr,
+ B1=>scuba_vlo, CI=>co3_3, GE=>full_d_c);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a1: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
+ S1=>open);
+
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of testfifo is
+ for Structure
+ for all:AGEB2 use entity ecp2m.AGEB2(V); end for;
+ for all:AND2 use entity ecp2m.AND2(V); end for;
+ for all:CU2 use entity ecp2m.CU2(V); end for;
+ for all:FADD2B use entity ecp2m.FADD2B(V); end for;
+ for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for;
+ for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
+ for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for;
+ for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for;
+ for all:INV use entity ecp2m.INV(V); end for;
+ for all:OR2 use entity ecp2m.OR2(V); end for;
+ for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for;
+ for all:VHI use entity ecp2m.VHI(V); end for;
+ for all:VLO use entity ecp2m.VLO(V); end for;
+ for all:XOR2 use entity ecp2m.XOR2(V); end for;
+ for all:PDPW16KB use entity ecp2m.PDPW16KB(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23)
+-- Module Version: 5.2
+-- Wed Nov 18 17:17:38 2009
+
+-- parameterized module component declaration
+component testfifo
+ port (Data: in std_logic_vector(95 downto 0);
+ WrClock: in std_logic; RdClock: in std_logic;
+ WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic;
+ RPReset: in std_logic; Q: out std_logic_vector(95 downto 0);
+ Empty: out std_logic; Full: out std_logic);
+end component;
+
+-- parameterized module component instance
+__ : testfifo
+ port map (Data(95 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__,
+ RdEn=>__, Reset=>__, RPReset=>__, Q(95 downto 0)=>__, Empty=>__,
+ Full=>__);
--- /dev/null
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+--library work;
+--use work.trb_net_std.all;
+
+entity trb_net_sbuf2 is
+ generic( DATA_WIDTH : integer := 19;
+ VERSION : integer := 0
+ );
+ port( CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- connections to data source A
+ COMB_DATAREADY_IN : in std_logic;
+ COMB_NEXT_READ_OUT : out std_logic;
+ COMB_READ_IN : in std_logic;
+ COMB_DATA_IN : in std_logic_vector (DATA_WIDTH-1 downto 0);
+ -- connections to data sink B
+ SYN_DATAREADY_OUT : out std_logic;
+ SYN_DATA_OUT : out std_logic_vector (DATA_WIDTH-1 downto 0);
+ SYN_READ_IN : in std_logic;
+ -- status signals
+ FIFO_WR_OUT : out std_logic;
+ FIFO_RD_OUT : out std_logic;
+ STAT_BUFFER : out std_logic
+ );
+end trb_net_sbuf2;
+
+architecture trb_net_sbuf_arch of trb_net_sbuf2 is
+
+ component fifo_sbuf is
+ port( Data : in std_logic_vector(18 downto 0);
+ Clock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ Q : out std_logic_vector(18 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic;
+ AlmostFull : out std_logic
+ );
+ end component;
+
+ signal fifo_data_in : std_logic_vector(18 downto 0);
+ signal fifo_data_out : std_logic_vector(18 downto 0);
+ signal reg_fifo_data_out : std_logic_vector(18 downto 0);
+ signal fifo_wr_en : std_logic;
+ signal fifo_rd_en : std_logic;
+ signal fifo_empty : std_logic;
+ signal fifo_full : std_logic;
+ signal fifo_almost_full : std_logic;
+ signal fifo_read_before : std_logic;
+ signal next_last_fifo_read : std_logic;
+ signal last_fifo_read : std_logic;
+ signal comb_next_read : std_logic;
+
+begin
+
+-- write to fifo if fifo is not full and data is available
+fifo_data_in <= comb_data_in;
+fifo_wr_en <= comb_dataready_in and comb_read_in and not fifo_full;
+comb_next_read <= not fifo_almost_full;
+
+-- fifo read signal
+--fifo_rd_en <= syn_read_in or not fifo_read_before;
+fifo_rd_en <= syn_read_in or (not next_last_fifo_read and not fifo_read_before);
+
+-- the fifo
+THE_BUFFER : fifo_sbuf
+port map( Data => fifo_data_in,
+ Clock => clk,
+ WrEn => fifo_wr_en,
+ RdEn => fifo_rd_en,
+ Reset => reset,
+ Q => fifo_data_out,
+ Empty => fifo_empty,
+ Full => fifo_full,
+ AlmostFull => fifo_almost_full
+ );
+
+-- is data on output valid?
+PROC_DETECT_VALID_READS : process( clk )
+begin
+ if( rising_edge(CLK) ) then
+ if ( reset = '1' ) then
+ fifo_read_before <= '0';
+ elsif( clk_en = '1' ) then
+ if ( next_last_fifo_read = '1' ) then
+ fifo_read_before <= '1';
+ elsif( syn_read_in = '1' ) then
+ fifo_read_before <= '0';
+ end if;
+ end if;
+ end if;
+end process PROC_DETECT_VALID_READS;
+
+-- keep track of fifo read operations
+PROC_LAST_FIFO_READ : process( clk )
+begin
+ if( rising_edge(clk) ) then
+ next_last_fifo_read <= fifo_rd_en and not fifo_empty;
+ last_fifo_read <= next_last_fifo_read and not RESET;
+ end if;
+end process PROC_LAST_FIFO_READ;
+
+-- register on fifo outputs
+PROC_SYNC_FIFO_OUTPUTS: process( clk )
+begin
+ if( rising_edge(clk) )then
+ if( next_last_fifo_read = '1' ) then
+ reg_fifo_data_out <= fifo_data_out;
+ end if;
+ end if;
+end process PROC_SYNC_FIFO_OUTPUTS;
+
+-- connect to outputs
+syn_dataready_out <= fifo_read_before;
+syn_data_out <= reg_fifo_data_out;
+comb_next_read_out <= comb_next_read;
+
+fifo_wr_out <= fifo_wr_en;
+fifo_rd_out <= fifo_rd_en;
+
+stat_buffer <= fifo_full;
+
+end architecture;
\ No newline at end of file
--- /dev/null
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library work;
+use work.trb_net_std.all;
+
+entity trb_net_sbuf3 is
+ generic( DATA_WIDTH : integer := 18 );
+ port( -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- port to combinatorial logic
+ COMB_DATAREADY_IN : in std_logic; --comb logic provides data word
+ COMB_next_READ_OUT : out std_logic; --sbuf can read in NEXT cycle
+ COMB_READ_IN : in std_logic; --comb logic IS reading
+ -- the COMB_next_READ_OUT should be connected via comb. logic to a register
+ -- to provide COMB_READ_IN (feedback path with 1 cycle delay)
+ COMB_DATA_IN : in std_logic_vector(DATA_WIDTH-1 downto 0); -- Data word
+ -- Port to synchronous output.
+ SYN_DATAREADY_OUT : out std_logic;
+ SYN_DATA_OUT : out std_logic_vector(DATA_WIDTH-1 downto 0); -- Data word
+ SYN_READ_IN : in std_logic;
+ -- Status and control port
+ DEBUG_OUT : out std_logic_vector(15 downto 0);
+ STAT_BUFFER : out std_logic
+ );
+end entity;
+
+architecture trb_net_sbuf3_arch of trb_net_sbuf3 is
+
+signal current_b0_buffer : std_logic_vector (DATA_WIDTH-1 downto 0);
+signal current_b1_buffer : std_logic_vector (DATA_WIDTH-1 downto 0);
+signal current_b2_buffer : std_logic_vector (DATA_WIDTH-1 downto 0);
+
+signal next_next_READ_OUT : std_logic;
+signal current_next_READ_OUT : std_logic;
+signal next_SYN_DATAREADY_OUT : std_logic;
+signal current_SYN_DATAREADY_OUT : std_logic;
+
+type BUFFER_STATE is (BUFFER_EMPTY, BUFFER_B2_FULL, BUFFER_B1_FULL,BUFFER_B0_FULL);
+signal current_buffer_state : BUFFER_STATE;
+signal next_buffer_state : BUFFER_STATE;
+signal current_buffer_state_int : std_logic_vector(1 downto 0);
+
+signal current_got_overflow : std_logic;
+signal next_got_overflow : std_logic;
+signal combined_COMB_DATAREADY_IN : std_logic;
+
+signal move_b1_b2 : std_logic;
+signal move_b0_b1 : std_logic;
+
+signal load_b2 : std_logic;
+signal load_b1 : std_logic;
+signal load_b0 : std_logic;
+
+signal debug : std_logic_vector(15 downto 0);
+
+attribute syn_preserve : boolean;
+attribute syn_keep : boolean;
+attribute syn_preserve of current_SYN_DATAREADY_OUT : signal is true;
+attribute syn_keep of current_SYN_DATAREADY_OUT : signal is true;
+attribute syn_preserve of current_next_READ_OUT : signal is true;
+attribute syn_keep of current_next_READ_OUT : signal is true;
+attribute syn_hier : string;
+attribute syn_hier of trb_net_sbuf3_arch : architecture is "flatten, firm";
+
+
+begin
+
+SYN_DATA_OUT <= current_b2_buffer;
+SYN_DATAREADY_OUT <= current_SYN_DATAREADY_OUT;
+COMB_next_READ_OUT <= current_next_READ_OUT;
+
+STAT_BUFFER <= current_got_overflow;
+
+combined_COMB_DATAREADY_IN <= (COMB_DATAREADY_IN and COMB_READ_IN);
+
+THE_FSM: process(current_buffer_state, SYN_READ_IN,
+ current_SYN_DATAREADY_OUT, current_got_overflow,
+ combined_COMB_DATAREADY_IN)
+begin -- process COMB
+ next_buffer_state <= current_buffer_state;
+ next_next_READ_OUT <= '1';
+ load_b0 <= '0';
+ load_b1 <= '0';
+ load_b2 <= '0';
+ move_b1_b2 <= '0';
+ move_b0_b1 <= '0';
+ next_SYN_DATAREADY_OUT <= current_SYN_DATAREADY_OUT;
+ next_got_overflow <= current_got_overflow;
+
+ case current_buffer_state is
+
+ when BUFFER_EMPTY =>
+ current_buffer_state_int <= "00";
+ if( combined_COMB_DATAREADY_IN = '1' ) then
+ next_buffer_state <= BUFFER_B2_FULL;
+ load_b2 <= '1';
+ next_SYN_DATAREADY_OUT <= '1';
+ end if;
+
+ when BUFFER_B2_FULL =>
+ current_buffer_state_int <= "01";
+ next_SYN_DATAREADY_OUT <= '1';
+ if ( (combined_COMB_DATAREADY_IN = '1') and (SYN_READ_IN = '1') ) then
+ load_b2 <= '1';
+ elsif( (combined_COMB_DATAREADY_IN = '1') and (SYN_READ_IN = '0') ) then
+ next_buffer_state <= BUFFER_B1_FULL;
+ next_next_READ_OUT <= '0';
+ load_b1 <= '1';
+ elsif( (combined_COMB_DATAREADY_IN = '0') and (SYN_READ_IN = '1') ) then
+ next_buffer_state <= BUFFER_EMPTY;
+ next_SYN_DATAREADY_OUT <= '0';
+ end if;
+
+ when BUFFER_B1_FULL =>
+ current_buffer_state_int <= "10";
+ next_SYN_DATAREADY_OUT <= '1';
+ next_next_READ_OUT <= '0';
+ if ( (combined_COMB_DATAREADY_IN = '1') and (SYN_READ_IN = '1') ) then
+ load_b1 <= '1';
+ move_b1_b2 <= '1';
+ elsif( (combined_COMB_DATAREADY_IN = '1') and (SYN_READ_IN = '0') ) then
+ next_buffer_state <= BUFFER_B0_FULL;
+ load_b0 <= '1';
+ elsif( (combined_COMB_DATAREADY_IN = '0') and (SYN_READ_IN = '1') ) then
+ next_buffer_state <= BUFFER_B2_FULL;
+ next_next_READ_OUT <= '1';
+ move_b1_b2 <= '1';
+ end if;
+
+ when BUFFER_B0_FULL =>
+ current_buffer_state_int <= "11";
+ next_SYN_DATAREADY_OUT <= '1';
+ next_next_READ_OUT <= '0';
+ if ( (combined_COMB_DATAREADY_IN = '1') and (SYN_READ_IN = '0') ) then
+ next_got_overflow <= '1';
+ elsif( (combined_COMB_DATAREADY_IN = '0') and (SYN_READ_IN = '1') ) then
+ move_b1_b2 <= '1';
+ move_b0_b1 <= '1';
+ next_buffer_state <= BUFFER_B1_FULL;
+ elsif( (combined_COMB_DATAREADY_IN = '1') and (SYN_READ_IN = '1') ) then
+ move_b1_b2 <= '1';
+ move_b0_b1 <= '1';
+ load_b0 <= '1';
+ end if;
+
+ end case;
+end process;
+
+PROC_FSM_REG : process(CLK)
+begin
+ if( rising_edge(CLK) ) then
+ if ( RESET = '1' ) then
+ current_buffer_state <= BUFFER_EMPTY;
+ current_got_overflow <= '0';
+ current_SYN_DATAREADY_OUT <= '0';
+ current_next_READ_OUT <= '0';
+ elsif( CLK_EN = '1' ) then
+ current_buffer_state <= next_buffer_state;
+ current_got_overflow <= next_got_overflow;
+ current_SYN_DATAREADY_OUT <= next_SYN_DATAREADY_OUT;
+ current_next_READ_OUT <= next_next_READ_OUT;
+ end if;
+ end if;
+end process;
+
+
+PROC_REG_BUFFERS : process(CLK)
+begin
+ if( rising_edge(CLK) ) then
+ if move_b1_b2 = '1' then
+ current_b2_buffer <= current_b1_buffer;
+ end if;
+
+ if move_b0_b1 = '1' then
+ current_b1_buffer <= current_b0_buffer;
+ end if;
+
+ if load_b2 = '1' then
+ current_b2_buffer <= COMB_DATA_IN;
+ end if;
+
+ if load_b1 = '1' then
+ current_b1_buffer <= COMB_DATA_IN;
+ end if;
+
+ if load_b0 = '1' then
+ current_b0_buffer <= COMB_DATA_IN;
+ end if;
+ end if;
+end process;
+
+-- Debug signals
+debug(15 downto 14) <= current_buffer_state_int;
+
+debug(13 downto 6) <= (others => '0');
+
+debug(5) <= move_b1_b2;
+debug(4) <= move_b0_b1;
+debug(3) <= '0';
+debug(2) <= load_b2;
+debug(1) <= load_b1;
+debug(0) <= load_b0;
+
+debug_out <= debug;
+
+end architecture;
+
--- /dev/null
+
+--## attention, automatically generated. Don't change by hand.
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+use ieee.numeric_std.all;
+
+package version is
+
+ constant VERSION_NUMBER_TIME : std_logic_vector(31 downto 0) := CONV_STD_LOGIC_VECTOR(1264600226,32);
+
+end package version;
+
jspc29 / adcm.git / commitdiff