signal cal_phase_q : std_logic;
+ signal rj_io_q : std_logic_vector(1 downto 0);
+
begin
THE_TIME_COUNTER_PROC: process( clk_full_osc )
HDR_IO(6) <= start_ping_q;
HDR_IO(8) <= start_pong_q;
HDR_IO(10) <= '0';
+
+ THE_PING_OR_LVDS: OFS1P3DX
+ port map(
+ SP => '1',
+ CD => '0',
+ SCLK => master_clk_i,
+ D => ping_i,
+ Q => rj_io_q(0)
+ );
+
+ THE_PONG_OR_LVDS: OFS1P3DX
+ port map(
+ SP => '1',
+ CD => '0',
+ SCLK => pong_clk_i,
+ D => pong_i,
+ Q => rj_io_q(1)
+ );
+
--------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------
REFOUT <= (others => cts_trigger_out);
end generate;
- RJ_IO(0) <= '0'; --tx_dlm_i; --cts_trigger_out;
- RJ_IO(1) <= '0'; --rx_dlm_i;
+ RJ_IO(0) <= rj_io_q(0); --tx_dlm_i; --cts_trigger_out;
+ RJ_IO(1) <= rj_io_q(1); --rx_dlm_i;
---------------------------------------------------------------------------
-- LED
---------------------------------------------------------------------------