LOCATE UGROUP "gen_PCSB.THE_MEDIA_PCSB/media_interface_group" REGION "MEDIA_LEFT";
# read from SCI can be delayed due to long read strobe
-MULTICYCLE FROM ASIC gen_PCSB.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns;
# write strobe can be delayed due to A/D being stable after access
+MULTICYCLE FROM ASIC gen_PCSB.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns;
MULTICYCLE TO ASIC gen_PCSB.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns;
# SCI write signal problem...
USE SECONDARY NET "gen_PCSD.THE_MEDIA_4_PCSD/clk_rx_full[1]";
# read from SCI can be delayed due to long read strobe
-MULTICYCLE FROM ASIC gen_PCSB.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns;
# write strobe can be delayed due to A/D being stable after access
-MULTICYCLE TO ASIC gen_PCSB.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns;
+MULTICYCLE FROM ASIC gen_PCSA.THE_MEDIA_PCSA/THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns;
+MULTICYCLE TO ASIC gen_PCSA.THE_MEDIA_PCSA/THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns;
+MULTICYCLE FROM ASIC gen_PCSB_BKPL.THE_MEDIA_4_PCSB/THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns;
+MULTICYCLE TO ASIC gen_PCSB_BKPL.THE_MEDIA_4_PCSB/THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns;
+MULTICYCLE FROM ASIC gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns;
+MULTICYCLE TO ASIC gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns;
+MULTICYCLE FROM ASIC THE_MEDIA_4_PCSC/THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns;
+MULTICYCLE TO ASIC THE_MEDIA_4_PCSC/THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns;
+MULTICYCLE FROM ASIC THE_MEDIA_4_PCSD/THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns;
+MULTICYCLE TO ASIC THE_MEDIA_4_PCSD/THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns;
+
# SCI write signal problem...
#BLOCK NET gen_PCSB.THE_MEDIA_PCSB/sci_write_i;
LOCATE COMP "THE_ENDPOINT/THE_ENDPOINT/genbuffers.1.geniobuf.gen_ipu_apl.gen_gbe.THE_GBE/physical_impl_gen.physical/impl_gen.gbe_serdes/PCSD_INST" SITE "PCSD";
# read from SCI can be delayed due to long read strobe
-MULTICYCLE FROM ASIC gen_PCSB.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns;
# write strobe can be delayed due to A/D being stable after access
-MULTICYCLE TO ASIC gen_PCSB.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns;
+MULTICYCLE FROM ASIC THE_MEDIA_INTERFACE/THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns;
+MULTICYCLE TO ASIC THE_MEDIA_INTERFACE/THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns;
# SCI write signal problem...
-#BLOCK NET gen_PCSB.THE_MEDIA_PCSB/sci_write_i;
+#BLOCK NET THE_MEDIA_INTERFACE/sci_write_i;
#BLOCK INTERCLOCKDOMAIN PATHS;