fix of output port usage in hub_logic_2 for vivado

diff --git a/trb_net16_hub_logic_2.vhd b/trb_net16_hub_logic_2.vhd
index be0631b62bcfd8f19209ab5462d3bc7c31fe9148..f35a0cdb19b194dc41961637031bcc4324a942f3 100644 (file)
--- a/trb_net16_hub_logic_2.vhd
+++ b/trb_net16_hub_logic_2.vhd
@@ -149,6 +149,7 @@ architecture trb_net16_hub_logic_arch of trb_net16_hub_logic is
   attribute syn_keep of reset_i : signal is true;  
   
   signal buf_STAT                        : std_logic_vector(15 downto 0);
+  signal STAT_POINTS_locked_i            : std_logic_vector(31 downto 0);
   
 begin
 
@@ -549,20 +550,20 @@ process(reply_pool_free, reply_open,act_reply_port)
     wait until rising_edge(CLK);
     last_reset_i <= reset_i;
     if reset_i = '1' and last_reset_i = '0' then
-      STAT_after_reset(15 downto  0) <= STAT_POINTS_locked(15 downto 0);
+      STAT_after_reset(15 downto  0) <= STAT_POINTS_locked_i(15 downto 0);
       STAT_after_reset(19 downto 16) <= buf_STAT(3 downto 0);
       STAT_after_reset(23 downto 20) <= std_logic_vector(to_unsigned(act_reply_port,4));
     end if;
   end process;
   
-  STAT_POINTS_locked(31 downto POINT_NUMBER)  <= (others => '0');
+  STAT_POINTS_locked_i(31 downto POINT_NUMBER)  <= (others => '0');
 
   proc_stat_errorbits : process begin
       wait until rising_edge(CLK);
       if currentstate /= IDLE then
-        STAT_POINTS_locked(POINT_NUMBER-1 downto 0) <= not reply_got_trm and real_active_points and not act_init_mask;
+        STAT_POINTS_locked_i(POINT_NUMBER-1 downto 0) <= not reply_got_trm and real_active_points and not act_init_mask;
       else
-        STAT_POINTS_locked(POINT_NUMBER-1 downto 0) <= (others => '0');
+        STAT_POINTS_locked_i(POINT_NUMBER-1 downto 0) <= (others => '0');
       end if;
       
       if currentstate = IDLE  then
@@ -570,6 +571,8 @@ process(reply_pool_free, reply_open,act_reply_port)
       end if;
     end process;
 
+  STAT_POINTS_locked <= STAT_POINTS_locked_i;
+
   gen_monitoring_errorbits : process(CLK)
     begin
       if rising_edge(CLK) then