add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net16_hub_func.vhd"
add_file -vhdl -lib work "../base/code/clock_switch.vhd"
-#add_file -vhdl -lib work "../base/code/SFP_DDM.vhd"
add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd"
add_file -vhdl -lib work "../base/trb3_components.vhd"
add_file -vhdl -lib work "../base/code/mbs_vulom_recv.vhd"
add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd"
add_file -vhdl -lib work "source/cts_pkg.vhd"
-add_file -vhdl -lib work "source/cbmnet_dlm_etm.vhd"
add_file -vhdl -lib work "source/m26_sensor_etm.vhd"
add_file -vhdl -lib work "source/mbs_master.vhd"
add_file -vhdl -lib work "source/timestamp_generator.vhd"
add_file -vhdl -lib "work" "../../tdc/base/cores/ecp3/FIFO/FIFO_36x32_OutReg.vhd"
}
-add_file -vhdl -lib work "./cbmnet_bridge/cbmnet_interface_pkg.vhd"
-add_file -vhdl -lib work "./cbmnet_bridge/cbmnet_phy_pkg.vhd"
-if {$INCLUDE_CBMNET == 1} {
- set_option -include_path {../cbmnet/cbmnet/cores/CBMnet/includes/}
-
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/rams/ram_1w1r_1c.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/rams/ram_1w1r_2c.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/rams/ram_1w2r_1c.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/rams/ram_2rw_1c.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/rams/ram_2rw_2c.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/rams/ram_1w1r_1c_enable.v"
-
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/fast_fifo/fast_fifo.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/fast_fifo/fifo_ram.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/fast_fifo/fifo_reg.v"
-
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/fwft_fifo_spec/spec_fwft_fifo.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/fwft_fifo_spec/spec_standard_fifo.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/fwft_fifo_spec/empty_logic_spec_so.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/fwft_fifo_spec/empty_logic_wo_spec.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/fwft_fifo_spec/full_logic_spec_si.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/fwft_fifo_spec/full_logic_wo_spec.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/fwft_fifo_spec/full_logic_spec_si_all.v"
-
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/async_fifo/async_fifo.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/async_fifo/async_standard_fifo.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/async_fifo/sync_r2w.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/async_fifo/sync_w2r.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/async_fifo/sync_w2r_hs.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/async_fifo/empty_logic.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/async_fifo/full_logic.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/async_fifo/empty_logic_spec_shift_out.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/async_fifo/empty_logic_spec_shift_out_1_inc.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/async_fifo/full_logic_spec_shift_in.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/async_fifo/full_logic_spec_shift_in_1_inc.v"
-
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/pcs_init/cn_barrel_shifter.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/pcs_init/cn_rx_pcs_init_fsm.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/pcs_init/cn_rx_pcs_wrapper.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/pcs_init/cn_tx_pcs_init_fsm.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/pcs_init/cn_tx_pcs_wrapper.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/pcs_init/cn_async_input_sync.v"
-
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/dlm_mixed/dlm_reflect.v"
-
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/link_port_v3/cn_lp_crc_gen.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/link_port_v3/cn_lp_init_fsm.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/link_port_v3/cn_lp_init.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/link_port_v3/cn_lp_rx_buffer_read_fsm.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/link_port_v3/cn_lp_rx_buffer_read.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/link_port_v3/cn_lp_rx_buffer.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/link_port_v3/cn_lp_rx_buffer_write_fsm.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/link_port_v3/cn_lp_rx_dlm.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/link_port_v3/cn_lp_rx_service.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/link_port_v3/cn_lp_rx.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/link_port_v3/cn_lp_top.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/link_port_v3/cn_lp_tx_buffer_read_fsm.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/link_port_v3/cn_lp_tx_buffer.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/link_port_v3/cn_lp_tx_buffer_write_fsm.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/link_port_v3/cn_lp_tx_dlm.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/link_port_v3/cn_lp_tx_out_arbiter_fsm.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/link_port_v3/cn_lp_tx_out.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/link_port_v3/cn_lp_tx_service.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/link_port_v3/cn_lp_tx.v"
-
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/link_tester/lt_random_stopper.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/link_tester/lt_send_fsm.v"
- add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/link_tester/link_tester_fe.v"
-
- add_file -vhdl -lib work "../base/cores/cbmnet_sfp1.vhd"
- add_file -vhdl -lib work "../cbmnet/cores/lattice_ecp3_fifo_16x16_dualport.vhd"
- add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd"
-
- add_file -vhdl -lib work "./cbmnet_bridge/cbmnet_phy_ecp3_rx_reset_fsm.vhd"
- add_file -vhdl -lib work "./cbmnet_bridge/cbmnet_phy_ecp3_tx_reset_fsm.vhd"
- add_file -vhdl -lib work "./cbmnet_bridge/cbmnet_phy_rx_gear.vhd"
- add_file -vhdl -lib work "./cbmnet_bridge/cbmnet_phy_tx_gear.vhd"
- add_file -vhdl -lib work "./cbmnet_bridge/cbmnet_phy_ecp3.vhd"
-
- add_file -vhdl -lib work "../cbmnet/cores/cbmnet_fifo_18x32k_dp.vhd"
- add_file -vhdl -lib work "./cbmnet_bridge/cbmnet_readout_trbnet_decoder.vhd"
- add_file -vhdl -lib work "./cbmnet_bridge/cbmnet_readout_event_packer.vhd"
- add_file -vhdl -lib work "./cbmnet_bridge/cbmnet_readout_fifo_ecp3.vhd"
- add_file -vhdl -lib work "./cbmnet_bridge/cbmnet_readout_frame_packer.vhd"
- add_file -vhdl -lib work "./cbmnet_bridge/cbmnet_readout_tx_fifo.vhd"
- add_file -vhdl -lib work "./cbmnet_bridge/cbmnet_readout_obuf.vhd"
- add_file -vhdl -lib work "./cbmnet_bridge/cbmnet_readout.vhd"
-
- add_file -vhdl -lib work "./cbmnet_bridge/pos_edge_strech_sync.vhd"
- add_file -vhdl -lib work "./cbmnet_bridge/cbmnet_sync_module.vhd"
-
- add_file -vhdl -lib work "./cbmnet_bridge/cbmnet_bridge.vhd"
-}
add_file -vhdl -lib work "./trb3_central.vhd"
#add_file -fpga_constraint "./cts.fdc"
use work.tdc_version.all;
use work.trb_net_gbe_components.all;
-use work.cbmnet_interface_pkg.all;
use work.cts_pkg.all;
-- 7000 - 72FF Readout endpoint registers
-- 8100 - 83FF GbE configuration & status
-- A000 - A7FF CTS configuration & status
--- A800 - A9ff CBMNet
-- C000 - CFFF TDC configuration & status
-- D000 - D13F Flash Programming
signal mbs_clock_i, mbs_data_i : std_logic;
- -- cbmnet
- signal cbm_clk_i : std_logic;
- signal cbm_reset_i : std_logic;
- signal cbm_etm_trigger_i : std_logic;
-
- signal cbm_phy_led_rx_i : std_logic;
- signal cbm_phy_led_tx_i : std_logic;
- signal cbm_phy_led_ok_i : std_logic;
-
- signal cbm_link_active_i : std_logic;
- signal cbm_sync_dlm_sensed_i : std_logic;
- signal cbm_sync_pulser_i : std_logic;
- signal cbm_sync_timing_trigger_i : std_logic;
-
- signal cbm_regio_rx, bustc_rx, busgbeip_rx, busgbereg_rx : CTRLBUS_RX;
- signal cbm_regio_tx, bustc_tx, busgbeip_tx, busgbereg_tx : CTRLBUS_TX;
+ signal bustc_rx, busgbeip_rx, busgbereg_rx : CTRLBUS_RX;
+ signal bustc_tx, busgbeip_tx, busgbereg_tx : CTRLBUS_TX;
signal reboot_from_gbe : std_logic;
end component;
begin
- assert not(USE_4_SFP = c_YES and INCLUDE_CBMNET = c_YES) report "CBMNET uses SFPs 1-4 and hence does not support USE_4_SFP" severity failure;
- assert not(INCLUDE_CBMNET = c_YES and INCLUDE_CTS = c_NO) report "CBMNET is supported only with CTS included" severity failure;
+
assert not(INCLUDE_TDC = c_YES and INCLUDE_MBS_MASTER = c_YES) report "TDC and MBS Master can not be implemented" severity failure;
assert not(INCLUDE_ETM = c_YES and ETM_CHOICE = ETM_CHOICE_MBS_VULOM and INCLUDE_MBS_MASTER = c_YES) report "This ETM and MBS Master can not be implemented" severity failure;
assert not(INCLUDE_ETM = c_YES and ETM_CHOICE = ETM_CHOICE_MAINZ_A2 and INCLUDE_MBS_MASTER = c_YES) report "This ETM and MBS Master can not be implemented" severity failure;
end generate;
--- CBMNet ETM
- gen_cbmnet_etm : if (ETM_CHOICE = ETM_CHOICE_CBMNET and INCLUDE_CTS = c_YES) or (INCLUDE_ETM = c_NO and INCLUDE_MBS_MASTER = c_NO and INCLUDE_TIMESTAMP_GENERATOR = c_NO) generate
- cts_ext_trigger <= cbm_etm_trigger_i;
+-- MBS Master ETM
+ gen_cbmnet_etm : if (INCLUDE_ETM = c_NO and INCLUDE_MBS_MASTER = c_NO and INCLUDE_TIMESTAMP_GENERATOR = c_NO) generate
+ cts_ext_trigger <= '0';
cts_rdo_additional(0).data_finished <= '1';
cts_ext_header <= "00";
cts_ext_status <= x"deadc0de";
cts_trigger_out <= '0';
end generate;
--- ---------------------------------------------------------------------------
--- -- CBMNET stack
--- ---------------------------------------------------------------------------
--- GEN_CBMNET : if INCLUDE_CBMNET = c_YES generate
--- THE_CBM_BRIDGE : cbmnet_bridge
--- port map (
--- -- clock and reset
--- CLK125_IN => clk_125_i, -- in std_logic;
--- ASYNC_RESET_IN => clear_i,
--- TRB_CLK_IN => clk_100_i, -- in std_logic;
--- TRB_RESET_IN => reset_i, -- in std_logic;
---
--- CBM_CLK_OUT => cbm_clk_i, -- out std_logic;
--- CBM_RESET_OUT => cbm_reset_i, -- out std_logic;
---
--- -- Media Interface
--- SD_RXD_P_IN => SFP_RX_P(5),
--- SD_RXD_N_IN => SFP_RX_N(5),
--- SD_TXD_P_OUT => SFP_TX_P(5),
--- SD_TXD_N_OUT => SFP_TX_N(5),
---
--- SD_PRSNT_N_IN => SFP_MOD0(1),
--- SD_LOS_IN => SFP_LOS(1),
--- SD_TXDIS_OUT => SFP_TXDIS(1),
---
--- LED_RX_OUT => cbm_phy_led_rx_i,
--- LED_TX_OUT => cbm_phy_led_tx_i,
--- LED_OK_OUT => cbm_phy_led_ok_i,
---
--- -- Status and strobes
--- CBM_LINK_ACTIVE_OUT => cbm_link_active_i,
--- CBM_DLM_OUT => cbm_sync_dlm_sensed_i, -- out std_logic;
--- CBM_TIMING_TRIGGER_OUT => cbm_sync_timing_trigger_i, -- out std_logic;
--- CBM_SYNC_PULSER_OUT => cbm_sync_pulser_i, -- out std_logic;
---
--- -- TRBNet Terminal
--- TRB_TRIGGER_IN => cts_trigger_out,
--- TRB_RDO_VALID_DATA_TRG_IN => cts_rdo_trg_data_valid, -- in std_logic;
--- TRB_RDO_VALID_NO_TIMING_IN => cts_rdo_valid_notiming_trg, -- in std_logic;
--- TRB_RDO_DATA_OUT => cts_rdo_additional(1).data, -- out std_logic_vector(31 downto 0);
--- TRB_RDO_WRITE_OUT => cts_rdo_additional(1).data_write, -- out std_logic;
--- TRB_RDO_FINISHED_OUT => cts_rdo_additional(1).data_finished, -- out std_logic;
---
--- TRB_TRIGGER_OUT => cbm_etm_trigger_i,
---
--- -- connect to hub
--- HUB_CTS_NUMBER_IN => hub_cts_number, -- in std_logic_vector (15 downto 0);
--- HUB_CTS_CODE_IN => hub_cts_code, -- in std_logic_vector (7 downto 0);
--- HUB_CTS_INFORMATION_IN => hub_cts_information, -- in std_logic_vector (7 downto 0);
--- HUB_CTS_READOUT_TYPE_IN => hub_cts_readout_type, -- in std_logic_vector (3 downto 0);
--- HUB_CTS_START_READOUT_IN => hub_cts_start_readout, -- in std_logic;
--- HUB_CTS_READOUT_FINISHED_OUT => hub_cts_readout_finished, -- out std_logic; --no more data, end transfer, send TRM
--- HUB_CTS_STATUS_BITS_OUT => hub_cts_status_bits, -- out std_logic_vector (31 downto 0);
--- HUB_FEE_DATA_IN => hub_fee_data, -- in std_logic_vector (15 downto 0);
--- HUB_FEE_DATAREADY_IN => hub_fee_dataready, -- in std_logic;
--- HUB_FEE_READ_OUT => hub_fee_read, -- out std_logic; --must be high when idle, otherwise you will never get a dataready
--- HUB_FEE_STATUS_BITS_IN => hub_fee_status_bits, -- in std_logic_vector (31 downto 0);
--- HUB_FEE_BUSY_IN => hub_fee_busy, -- in std_logic;
---
--- -- connect to GbE
--- GBE_CTS_NUMBER_OUT => gbe_cts_number, -- out std_logic_vector (15 downto 0);
--- GBE_CTS_CODE_OUT => gbe_cts_code, -- out std_logic_vector (7 downto 0);
--- GBE_CTS_INFORMATION_OUT => gbe_cts_information, -- out std_logic_vector (7 downto 0);
--- GBE_CTS_READOUT_TYPE_OUT => gbe_cts_readout_type, -- out std_logic_vector (3 downto 0);
--- GBE_CTS_START_READOUT_OUT => gbe_cts_start_readout, -- out std_logic;
--- GBE_CTS_READOUT_FINISHED_IN => gbe_cts_readout_finished, -- in std_logic; --no more data, end transfer, send TRM
--- GBE_CTS_STATUS_BITS_IN => gbe_cts_status_bits, -- in std_logic_vector (31 downto 0);
--- GBE_FEE_DATA_OUT => gbe_fee_data, -- out std_logic_vector (15 downto 0);
--- GBE_FEE_DATAREADY_OUT => gbe_fee_dataready, -- out std_logic;
--- GBE_FEE_READ_IN => gbe_fee_read, -- in std_logic; --must be high when idle, otherwise you will never get a dataready
--- GBE_FEE_STATUS_BITS_OUT => gbe_fee_status_bits, -- out std_logic_vector (31 downto 0);
--- GBE_FEE_BUSY_OUT => gbe_fee_busy, -- out std_logic;
---
--- -- reg io
--- --REGIO_IN => cbm_regio_rx,
--- --REGIO_OUT => cbm_regio_tx
--- REGIO_ADDR_IN => cbm_regio_rx.addr,
--- REGIO_DATA_IN => cbm_regio_rx.data,
--- REGIO_TIMEOUT_IN => cbm_regio_rx.timeout,
--- REGIO_READ_ENABLE_IN => cbm_regio_rx.read,
--- REGIO_WRITE_ENABLE_IN => cbm_regio_rx.write,
---
--- REGIO_DATA_OUT => cbm_regio_tx.data,
--- REGIO_DATAREADY_OUT => cbm_regio_tx.rack,
--- REGIO_WRITE_ACK_OUT => cbm_regio_tx.wack,
--- REGIO_NO_MORE_DATA_OUT => cbm_regio_tx.nack,
--- REGIO_UNKNOWN_ADDR_OUT => cbm_regio_tx.unknown
--- );
---
--- cbm_regio_tx.ack <= cbm_regio_tx.rack or cbm_regio_tx.wack;
---
--- SFP_RATE_SEL(1) <= '1'; -- not supported by SFP, but in general, this should be the correct setting
--- LED_TRIGGER_GREEN <= not cbm_link_active_i;
--- LED_TRIGGER_RED <= '0';
---
--- --Internal Connection
--- med_read_in(4) <= '0';
--- med_data_in(79 downto 64) <= (others => '0');
--- med_packet_num_in(14 downto 12) <= (others => '0');
--- med_dataready_in(4) <= '0';
--- med_stat_op(79 downto 64) <= (
--- 64+2 downto 64 => '1', -- ERROR_NC
--- 64 + 14 => '1', -- indicate "no signal"
--- others => '0');
--- med_stat_debug(4*64+63 downto 4*64) <= (others => '0');
---
--- SFP_TXDIS(4 downto 2) <= (others => '1');
---
--- end generate;
- GEN_NO_CBMNET : if INCLUDE_CBMNET = c_NO generate
gbe_cts_number <= hub_cts_number;
gbe_cts_code <= hub_cts_code;
gbe_cts_information <= hub_cts_information;
LED_TRIGGER_GREEN <= not med_stat_op(4*16+9);
LED_TRIGGER_RED <= not (med_stat_op(4*16+11) or med_stat_op(4*16+10));
- cbm_etm_trigger_i <= '0';
-
- cbm_regio_tx.nack <= cbm_regio_rx.read or cbm_regio_rx.write when rising_edge(clk_100_i);
- cbm_regio_tx.unknown <= cbm_regio_rx.read or cbm_regio_rx.write when rising_edge(clk_100_i);
- end generate;
-
---------------------------------------------------------------------------
-- Reset Generation
---------------------------------------------------------------------------
-- The TrbNet media interface (SFP)
---------------------------------------------------------------------------
- gen_single_sfp : if USE_4_SFP = c_NO and INCLUDE_CBMNET = c_NO generate
+ gen_single_sfp : if USE_4_SFP = c_NO generate
THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp
generic map(
SERDES_NUM => 0, --number of serdes in quad
MED_READ_IN => med_read_out(4),
REFCLK2CORE_OUT => open,
--SFP Connection
- SD_RXD_P_IN => SFP_RX_P(5),
- SD_RXD_N_IN => SFP_RX_N(5),
- SD_TXD_P_OUT => SFP_TX_P(5),
- SD_TXD_N_OUT => SFP_TX_N(5),
- SD_REFCLK_P_IN => open,
- SD_REFCLK_N_IN => open,
SD_PRSNT_N_IN => SFP_MOD0(1),
SD_LOS_IN => SFP_LOS(1),
SD_TXDIS_OUT => SFP_TXDIS(1),
SFP_TXDIS(4 downto 2) <= (others => '1');
end generate;
- gen_four_sfp : if USE_4_SFP = c_YES and INCLUDE_CBMNET = c_NO generate
+ gen_four_sfp : if USE_4_SFP = c_YES generate
THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp_4
generic map(
REVERSE_ORDER => c_NO, --order of ports
);
-
--- process(clk_100_i)
--- begin
--- if rising_edge(clk_100_i) then
--- if (reset_i = '1') then
--- fwd_data <= (others => '0');
--- else
--- fwd_data <= fwd_data + x"1";
--- end if;
--- end if;
--- end process;
---
--- process(clk_100_i)
--- begin
--- if rising_edge(clk_100_i) then
--- if (fwd_data(23 downto 0) = x"100000") then
--- fwd_sop <= x"f";
--- fwd_eop <= x"0";
--- fwd_dv <= x"f";
--- elsif (fwd_data(23 downto 0) > x"100000" and fwd_data(23 downto 0) < x"100064") then
--- fwd_sop <= x"0";
--- fwd_eop <= x"0";
--- fwd_dv <= x"f";
--- elsif (fwd_data(23 downto 0) = x"100064") then
--- fwd_sop <= x"0";
--- fwd_eop <= x"f";
--- fwd_dv <= x"f";
--- else
--- fwd_sop <= x"0";
--- fwd_eop <= x"0";
--- fwd_dv <= x"0";
--- end if;
--- end if;
--- end process;
-
-
---
--- GBE : trb_net16_gbe_buf
--- generic map (
--- DO_SIMULATION => c_NO,
--- USE_125MHZ_EXTCLK => c_NO
--- )
--- port map (
--- CLK => clk_100_i,
--- TEST_CLK => '0',
--- CLK_125_IN => clk_125_i,
--- RESET => reset_i,
--- GSR_N => gsr_n,
--- --Debug
--- STAGE_STAT_REGS_OUT => open, --stage_stat_regs, -- should be come STATUS or similar
--- STAGE_CTRL_REGS_IN => stage_ctrl_regs, -- OBSELETE!
--- ----gk 22.04.10 not used any more, ip_configurator moved inside
--- ---configuration interface
--- IP_CFG_START_IN => stage_ctrl_regs(15),
--- IP_CFG_BANK_SEL_IN => stage_ctrl_regs(11 downto 8),
--- IP_CFG_DONE_OUT => open,
--- IP_CFG_MEM_ADDR_OUT => ip_cfg_mem_addr,
--- IP_CFG_MEM_DATA_IN => ip_cfg_mem_data,
--- IP_CFG_MEM_CLK_OUT => ip_cfg_mem_clk,
--- MR_RESET_IN => stage_ctrl_regs(3),
--- MR_MODE_IN => stage_ctrl_regs(1),
--- MR_RESTART_IN => stage_ctrl_regs(0),
--- ---gk 29.03.10
--- --interface to ip_configurator memory
--- SLV_ADDR_IN => mb_ip_mem_addr(7 downto 0),
--- SLV_READ_IN => mb_ip_mem_read,
--- SLV_WRITE_IN => mb_ip_mem_write,
--- SLV_BUSY_OUT => open,
--- SLV_ACK_OUT => mb_ip_mem_ack,
--- SLV_DATA_IN => mb_ip_mem_data_wr,
--- SLV_DATA_OUT => mb_ip_mem_data_rd,
--- --gk 26.04.10
--- ---gk 22.04.10
--- ---registers setup interface
--- BUS_ADDR_IN => gbe_stp_reg_addr(7 downto 0), --ctrl_reg_addr(7 downto 0),
--- BUS_DATA_IN => gbe_stp_reg_data_wr, --stage_ctrl_regs,
--- BUS_DATA_OUT => gbe_stp_reg_data_rd,
--- BUS_WRITE_EN_IN => gbe_stp_reg_write,
--- BUS_READ_EN_IN => gbe_stp_reg_read,
--- BUS_ACK_OUT => gbe_stp_reg_ack,
--- --gk 23.04.10
--- LED_PACKET_SENT_OUT => open, --buf_SFP_LED_ORANGE(17),
--- LED_AN_DONE_N_OUT => link_ok, --buf_SFP_LED_GREEN(17),
--- --CTS interface
--- CTS_NUMBER_IN => gbe_cts_number,
--- CTS_CODE_IN => gbe_cts_code,
--- CTS_INFORMATION_IN => gbe_cts_information,
--- CTS_READOUT_TYPE_IN => gbe_cts_readout_type,
--- CTS_START_READOUT_IN => gbe_cts_start_readout,
--- CTS_DATA_OUT => open,
--- CTS_DATAREADY_OUT => open,
--- CTS_READOUT_FINISHED_OUT => gbe_cts_readout_finished,
--- CTS_READ_IN => '1',
--- CTS_LENGTH_OUT => open,
--- CTS_ERROR_PATTERN_OUT => gbe_cts_status_bits,
--- --Data payload interface
--- FEE_DATA_IN => gbe_fee_data,
--- FEE_DATAREADY_IN => gbe_fee_dataready,
--- FEE_READ_OUT => gbe_fee_read,
--- FEE_STATUS_BITS_IN => gbe_fee_status_bits,
--- FEE_BUSY_IN => gbe_fee_busy,
--- --SFP Connection
--- SFP_RXD_P_IN => SFP_RX_P(9), --these ports are don't care
--- SFP_RXD_N_IN => SFP_RX_N(9),
--- SFP_TXD_P_OUT => SFP_TX_P(9),
--- SFP_TXD_N_OUT => SFP_TX_N(9),
--- SFP_REFCLK_P_IN => open, --SFP_REFCLKP(2),
--- SFP_REFCLK_N_IN => open, --SFP_REFCLKN(2),
--- SFP_PRSNT_N_IN => SFP_MOD0(8), -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
--- SFP_LOS_IN => SFP_LOS(8), -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
--- SFP_TXDIS_OUT => SFP_TXDIS(8), -- SFP disable
---
--- -- interface between main_controller and hub logic
--- MC_UNIQUE_ID_IN => mc_unique_id,
--- GSC_CLK_IN => clk_100_i,
--- GSC_INIT_DATAREADY_OUT => gsc_init_dataready,
--- GSC_INIT_DATA_OUT => gsc_init_data,
--- GSC_INIT_PACKET_NUM_OUT => gsc_init_packet_num,
--- GSC_INIT_READ_IN => gsc_init_read,
--- GSC_REPLY_DATAREADY_IN => gsc_reply_dataready,
--- GSC_REPLY_DATA_IN => gsc_reply_data,
--- GSC_REPLY_PACKET_NUM_IN => gsc_reply_packet_num,
--- GSC_REPLY_READ_OUT => gsc_reply_read,
--- GSC_BUSY_IN => gsc_busy,
---
--- MAKE_RESET_OUT => reset_via_gbe,
---
--- --for simulation of receiving part only
--- MAC_RX_EOF_IN => '0',
--- MAC_RXD_IN => "00000000",
--- MAC_RX_EN_IN => '0',
---
--- ANALYZER_DEBUG_OUT => debug
--- );
-
-
---------------------------------------------------------------------------
-- Bus Handler
---------------------------------------------------------------------------
THE_BUS_HANDLER : trb_net16_regio_bus_handler
generic map(
- PORT_NUMBER => 14,
+ PORT_NUMBER => 12,
PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"8100", 3 => x"8300", 4 => x"a000",
5 => x"d300", 6 => x"c000", 7 => x"c100", 8 => x"c200", 9 => x"c300",
- 10 => x"c800", 11 => x"a800", 12 => x"d200", others => x"0000"),
+ 10 => x"c800", others => x"0000"),
PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 8, 3 => 8, 4 => 11,
5 => 2, 6 => 7, 7 => 5, 8 => 7, 9 => 7,
- 10 => 3, 11 => 9, 12 => 2, others => 0)
+ 10 => 3, others => 0)
)
port map(
CLK => clk_100_i,
BUS_NO_MORE_DATA_IN(10) => '0',
BUS_UNKNOWN_ADDR_IN(10) => '0',
- BUS_READ_ENABLE_OUT(11) => cbm_regio_rx.read,
- BUS_WRITE_ENABLE_OUT(11) => cbm_regio_rx.write,
- BUS_DATA_OUT(11*32+31 downto 11*32) => cbm_regio_rx.data,
- BUS_ADDR_OUT(11*16+15 downto 11*16) => cbm_regio_rx.addr,
- BUS_TIMEOUT_OUT(11) => cbm_regio_rx.timeout,
- BUS_DATA_IN(11*32+31 downto 11*32) => cbm_regio_tx.data,
- BUS_DATAREADY_IN(11) => cbm_regio_tx.ack,
- BUS_WRITE_ACK_IN(11) => cbm_regio_tx.ack,
- BUS_NO_MORE_DATA_IN(11) => cbm_regio_tx.nack,
- BUS_UNKNOWN_ADDR_IN(11) => cbm_regio_tx.unknown,
-
- --SFP DDM config registers
- BUS_READ_ENABLE_OUT(12) => sfp_ddm_ctrl_read,
- BUS_WRITE_ENABLE_OUT(12) => sfp_ddm_ctrl_write,
- BUS_DATA_OUT(12*32+31 downto 12*32) => sfp_ddm_ctrl_data_in,
- BUS_ADDR_OUT(12*16+1 downto 12*16) => sfp_ddm_ctrl_addr,
- BUS_ADDR_OUT(12*16+15 downto 12*16+3) => open,
- BUS_TIMEOUT_OUT(12) => open,
- BUS_DATA_IN(12*32+31 downto 12*32) => sfp_ddm_ctrl_data_out,
- BUS_DATAREADY_IN(12) => last_sfp_ddm_ctrl_read,
- BUS_WRITE_ACK_IN(12) => sfp_ddm_ctrl_write,
- BUS_NO_MORE_DATA_IN(12) => '0',
- BUS_UNKNOWN_ADDR_IN(12) => '0',
-
STAT_DEBUG => open
);
cts_regio_addr(15 downto 11) <= (others => '0');
--Response to handler
-- TRG_RELEASE_OUT => fee_trg_release_i, -- trigger release signal
TRG_RELEASE_OUT => open,
- TRG_STATUSBIT_OUT => cts_rdo_additional(1+INCLUDE_CBMNET).statusbits,
- DATA_OUT => cts_rdo_additional(1+INCLUDE_CBMNET).data,
- DATA_WRITE_OUT => cts_rdo_additional(1+INCLUDE_CBMNET).data_write,
- DATA_FINISHED_OUT => cts_rdo_additional(1+INCLUDE_CBMNET).data_finished,
+ TRG_STATUSBIT_OUT => cts_rdo_additional(1).statusbits,
+ DATA_OUT => cts_rdo_additional(1).data,
+ DATA_WRITE_OUT => cts_rdo_additional(1).data_write,
+ DATA_FINISHED_OUT => cts_rdo_additional(1).data_finished,
--Hit Counter Bus
HCB_READ_EN_IN => hitreg_read_en, -- bus read en strobe
HCB_WRITE_EN_IN => hitreg_write_en, -- bus write en strobe
);
--tdc_inputs(1) used by CBM-MBS ETM
- tdc_inputs(2) <= cbm_sync_pulser_i;
- tdc_inputs(3) <= cbm_sync_timing_trigger_i;
+-- tdc_inputs(2) <= cbm_sync_pulser_i;
+-- tdc_inputs(3) <= cbm_sync_timing_trigger_i;
tdc_inputs(4) <= JINLVDS(0); --NIM_IN(0);
--JTTL(0 downto 15) <= (others => '0');
-- end generate;
assert (INCLUDE_TIMESTAMP_GENERATOR = c_NO) report "timestamp generator currently not available." severity error;
--------------------------------------------------------------------------------
--- SFP POWER Entity
--------------------------------------------------------------------------------
--- Generate_Sfp_DDM : if INCLUDE_SFP_DDM = c_YES generate
--- SFP_DDM_1 : entity work.SFP_DDM
--- port map (
--- CLK100 => clk_100_i,
--- SLOW_CTRL_IN => sfp_ddm_ctrl_reg(31 downto 0),
--- DATA_OUT => sfp_ddm_ctrl_reg(32*4-1 downto 32),
--- SCL_EXT => SFP_MOD1,
--- SDA_EXT => SFP_MOD2
--- );
---
--- PROC_SFP_DDM_CTRL_REG : process
--- variable pos : integer;
--- begin
--- wait until rising_edge(clk_100_i);
--- pos := to_integer(unsigned(sfp_ddm_ctrl_addr))*32;
--- sfp_ddm_ctrl_data_out <= sfp_ddm_ctrl_reg(pos+31 downto pos);
--- last_sfp_ddm_ctrl_read <= sfp_ddm_ctrl_read;
--- if sfp_ddm_ctrl_write = '1' and to_integer(unsigned(sfp_ddm_ctrl_addr)) = 0 then
--- --sfp_ddm_ctrl_reg(pos+31 downto pos) <= sfp_ddm_ctrl_data_in;
--- sfp_ddm_ctrl_reg(31 downto 0) <= sfp_ddm_ctrl_data_in;
--- end if;
--- end process;
---
---
---
--- end generate Generate_Sfp_DDM;
-
-
---------------------------------------------------------------------------
-- Clock and Trigger Configuration
LED_GREEN <= debug(0);
LED_ORANGE <= debug(1);
- LED_RED <= debug(2) when INCLUDE_CBMNET = c_NO else cbm_link_active_i;
+ LED_RED <= debug(2);
LED_YELLOW <= link_ok;
jspc29 / trb3.git / commitdiff