minor changes to media interface files, Jan

diff --git a/trb_net_18_to_16_converter.vhd b/trb_net_18_to_16_converter.vhd
index a062c28b982b9c81e7af880fc9d7e5f0e1716e78..b43f6a21cf557a59132865560c671068e787c44f 100644 (file)
--- a/trb_net_18_to_16_converter.vhd
+++ b/trb_net_18_to_16_converter.vhd
@@ -210,7 +210,7 @@ D16_PACKET_NUM_OUT <= buf_D16_DATA_OUT(17 downto 16);
 
 next_buf_D16_READ_OUT <= dbuf16_next_read_out;
 D16_READ_OUT <= buf_D16_READ_OUT;
-  
+dbuf16_comb_data_in(15 downto 8) <= (others => '0');
   D16to18 : process(buffer_dbuf16_comb_data_in, dbuf16_comb_data_in,
                    buf_D16_READ_OUT, D16_DATAREADY_IN, D16_DATA_IN, D16_PACKET_NUM_IN)
     variable newdata : std_logic;

diff --git a/trb_net_55_to_18_converter.vhd b/trb_net_55_to_18_converter.vhd
index 305eb9b3f85b80cd4e6c66220a9d1e7b46f41901..4a745c6eccecf0f0ecb5579a3c46063f57d5f735 100644 (file)
--- a/trb_net_55_to_18_converter.vhd
+++ b/trb_net_55_to_18_converter.vhd
@@ -54,11 +54,12 @@ signal next_D18_DATA_OUT, buf_D18_DATA_OUT : std_logic_vector(15 downto 0);
 
 signal next_D18_READ_OUT, buf_D18_READ_OUT : std_logic;
 signal next_D55_DATAREADY_OUT, buf_D55_DATAREADY_OUT : std_logic;
+signal next_dataread55, dataread55 : std_logic;
+                                                  --data from 55 read and waiting to be written
 
-
-signal next_buf_D55_DATA_IN, buf_D55_DATA_IN : std_logic_vector(47 downto 0);
+signal next_buf_D55_DATA_IN, buf_D55_DATA_IN : std_logic_vector(55 downto 0);
 signal next_D55_DATA_OUT, buf_D55_DATA_OUT : std_logic_vector(55 downto 0);
-
+                                                  --databuffer for both directions
 begin
 -----------------------------------------------------------
 --Direction 18 to 55
@@ -157,7 +158,7 @@ D18_READ_OUT <= buf_D18_READ_OUT;
 -----------------------------------------------------------
   D55to18_fsm : process(buf_D18_DATA_OUT, buf_D18_PACKET_NUM_OUT, buf_D18_DATAREADY_OUT,
                         D18_READ_IN, D55_DATA_IN, D55_DATAREADY_IN, D55to18_state, 
-                        buf_D55_READ_OUT, buf_D55_DATA_IN)
+                        buf_D55_READ_OUT, buf_D55_DATA_IN, dataread55)
     variable dataisread : std_logic;
     begin
       next_D18_DATA_OUT <= buf_D18_DATA_OUT;
@@ -165,7 +166,7 @@ D18_READ_OUT <= buf_D18_READ_OUT;
       next_D55to18_state <= D55to18_state;
       next_D55_READ_OUT <= '0';
       next_buf_D55_DATA_IN <= buf_D55_DATA_IN;
-
+      next_dataread55 <= dataread55;
       if(D18_READ_IN = '1' AND buf_D18_DATAREADY_OUT = '1') then
         dataisread := '1';
       else
@@ -182,15 +183,35 @@ D18_READ_OUT <= buf_D18_READ_OUT;
 
       case D55to18_state is
         when IDLE =>
-          next_D55_READ_OUT <= '1';
-          if(D55_DATAREADY_IN = '1' AND buf_D55_READ_OUT = '1') then
-            next_buf_D55_DATA_IN(47 downto 0) <= D55_DATA_IN(47 downto 0);
+                                  --data available?
+          if (D55_DATAREADY_IN = '1' AND buf_D55_READ_OUT = '1') then
+            next_buf_D55_DATA_IN(55 downto 0) <= D55_DATA_IN(55 downto 0);
+            next_D55_READ_OUT <= '0';
+                                  --data available and ready to write
+            if (dataisread = '1' OR buf_D18_DATAREADY_OUT = '0') then
+              next_D18_DATA_OUT(7 downto 0) <= D55_DATA_IN(55 downto 48);
+              next_D18_DATA_OUT(15 downto 8) <= (others => '0');
+              next_D18_PACKET_NUM_OUT <= "00";
+              next_D18_DATAREADY_OUT <= '1';
+              next_D55to18_state <= FIRST;
+                                  --data available but not ready to write
+            else
+              next_dataread55 <= '1';
+            end if;
+                                  --data available before, now ready to write
+          elsif dataisread = '1' and dataread55 = '1' then
+            next_dataread55 <= '0';
             next_D18_DATA_OUT(7 downto 0) <= D55_DATA_IN(55 downto 48);
             next_D18_DATA_OUT(15 downto 8) <= (others => '0');
             next_D18_PACKET_NUM_OUT <= "00";
             next_D18_DATAREADY_OUT <= '1';
             next_D55to18_state <= FIRST;
+                                  --no data available
+          else
+            next_buf_D55_DATA_IN(55 downto 0) <= (others => '0');
+            next_D55_READ_OUT <= '1';
           end if;
+
         when FIRST =>
           if(dataisread = '1') then
             next_D18_DATA_OUT(15 downto 0) <= buf_D55_DATA_IN(47 downto 32);
@@ -210,18 +231,18 @@ D18_READ_OUT <= buf_D18_READ_OUT;
             next_D18_DATA_OUT(15 downto 0) <= buf_D55_DATA_IN(15 downto 0);
             next_D18_DATAREADY_OUT <= '1';
             next_D18_PACKET_NUM_OUT <= "11";
-            next_D55to18_state <= LAST;
-          end if;
-        when LAST =>
-          if(dataisread = '1') then
-            next_D18_DATA_OUT(15 downto 0) <= (others => '0');
-            next_D18_DATAREADY_OUT <= '0';
             next_D55to18_state <= IDLE;
-            next_D18_PACKET_NUM_OUT <= "00";
             next_D55_READ_OUT <= '1';
           end if;
+        when LAST =>
+--           if(dataisread = '1') then
+--             next_D18_DATA_OUT(15 downto 0) <= (others => '0');
+--             next_D18_DATAREADY_OUT <= '0';
+            next_D55to18_state <= IDLE;
+--             next_D18_PACKET_NUM_OUT <= "00";
+--             next_D55_READ_OUT <= '1';
+--           end if;
       end case;
-      
     end process;
 
   D55to18_fsm_reg : process(CLK)
@@ -234,6 +255,7 @@ D18_READ_OUT <= buf_D18_READ_OUT;
           buf_D18_DATAREADY_OUT <= '0';
           buf_D18_PACKET_NUM_OUT <= "00";
           D55to18_state <= IDLE;
+          dataread55 <= '0';
         else
           buf_D18_DATA_OUT <= next_D18_DATA_OUT;
           buf_D18_DATAREADY_OUT <= next_D18_DATAREADY_OUT;
@@ -241,6 +263,7 @@ D18_READ_OUT <= buf_D18_READ_OUT;
           buf_D55_DATA_IN <= next_buf_D55_DATA_IN;
           buf_D18_PACKET_NUM_OUT <= next_D18_PACKET_NUM_OUT;
           D55to18_state <= next_D55to18_state;
+          dataread55 <= next_dataread55;
         end if;
       else
         buf_D18_DATA_OUT <= buf_D18_DATA_OUT;
@@ -249,6 +272,7 @@ D18_READ_OUT <= buf_D18_READ_OUT;
         buf_D55_DATA_IN <= buf_D55_DATA_IN;
         buf_D18_PACKET_NUM_OUT <= buf_D18_PACKET_NUM_OUT;
         D55to18_state <= D55to18_state;
+        dataread55 <= dataread55;
       end if;
     end process;
 

diff --git a/trb_net_med_13bit_slow.vhd b/trb_net_med_13bit_slow.vhd
index 2763616b13d6e4db78aba563af2065f6a93413bb..94d93357dea0507602be8ab78ee2a0a719aa4602 100755 (executable)
--- a/trb_net_med_13bit_slow.vhd
+++ b/trb_net_med_13bit_slow.vhd
@@ -104,7 +104,7 @@ architecture trb_net_med_13bit_slow_arch of trb_net_med_13bit_slow is
   signal reg_MED_DATA_IN : std_logic_vector(12 downto 0);
   signal reg_MED_TRANSMISSION_CLK_IN, reg_MED_CARRIER_IN : std_logic;
   signal reg_MED_PARITY_IN : std_logic;
-
+  signal med2int_state_sig :std_logic_vector(2 downto 0);
 
 begin
 INT_DATAREADY_OUT <= buf_INT_DATAREADY_OUT;
@@ -494,6 +494,18 @@ MED2INT_fsm: process(reg_MED_PARITY_IN,MED2INT_state,CLK,reg_MED_DATA_IN,DAT_MED
   end process;
 
 
+process(MED2INT_state)
+begin
+  case MED2INT_state is
+  when IDLE  => med2int_state_sig <= "000";
+  when RECV2 => med2int_state_sig <= "001";
+  when RECV3 => med2int_state_sig <= "002";
+  when RECV4 => med2int_state_sig <= "003";
+  when RECV5 => med2int_state_sig <= "004";
+  end case;
+end process;
+
+
 MED2INT_fsm_reg: process(CLK,RESET)
   begin
     if RESET='1' then

diff --git a/trb_net_med_8bit_fast.vhd b/trb_net_med_8bit_fast.vhd
index e3d61532e71c8d757ad9f1ecab00a57ca0b16669..d618acccbe4e4a13f57f7f11f3642de678351ce8 100644 (file)
--- a/trb_net_med_8bit_fast.vhd
+++ b/trb_net_med_8bit_fast.vhd
@@ -230,15 +230,11 @@ end component;
 
 signal CLK_TRANS : std_logic;
 signal fifo_data_in, next_fifo_data_in : std_logic_vector(17 downto 0);
---signal next_next_fifo_data_in : std_logic_vector(7 downto 0);
 signal fifo_data_out : std_logic_vector(17 downto 0);
 signal fifo_full_out, fifo_empty_out : std_logic;
 signal fifo_status_out : std_logic_vector(3 downto 0);
 signal fifo_write_enable, next_fifo_write_enable : std_logic;
 signal fifo_read_enable, last_fifo_read_enable : std_logic;
---signal fifo_data_buffer : std_logic_vector(15 downto 0);
-signal packet_in_state : std_logic;
-
 
 signal buf_MED_PARITY_OUT : std_logic;
 signal buf_MED_CARRIER_OUT : std_logic;
@@ -626,7 +622,8 @@ ddr_ff_clk : dualdatarate_flipflop
         buf_MED_CARRIER_OUT <= buf_MED_CARRIER_OUT;
       end if;
     end process;
-
+    
+buf_MED_DATA_OUT(11 downto 8) <= "0000";
 
 -----------------------------------------------------------------------
 -- Output generation