signal powerup_ch : std_logic_vector(3 downto 0);
signal tx_ref_clk_i : std_logic;
- signal tx_rst_word_i : std_logic_vector(4*8-1 downto 0);
signal tx_rst_i : std_logic_vector(3 downto 0);
signal rx_rst_word_i : std_logic_vector(4*8-1 downto 0);
TX_DLM_IN => TX_DLM_IN,
TX_DLM_WORD_IN => TX_DLM_WORD_IN,
TX_RST_IN => tx_rst_i(i),
- TX_RST_WORD_IN => tx_rst_word_i(i*8+7 downto i*8),
+ TX_RST_WORD_IN => TX_RST_WORD_IN,
RX_DLM_OUT => RX_DLM_OUT(i),
RX_DLM_WORD_OUT => RX_DLM_WORD_OUT(i*8+7 downto i*8),
RX_RST_OUT => rx_rst_i(i),