IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;
--media interfaces
MII_NUMBER : integer range 2 to c_MAX_MII_PER_HUB := 12;
- --each row is one media interface and each column is one channel. starting with 0,0, ending with 15,15
MII_INIT_DEPTH : hub_iobuf_config_t := std_HUB_INIT_DEPTH;
MII_REPLY_DEPTH : hub_iobuf_config_t := std_HUB_REPLY_DEPTH;
-- settings for apis
API_NUMBER : integer range 0 to c_MAX_API_PER_HUB := 0;
API_CHANNELS : hub_api_config_t := (3,3,3,3,3,3,3,3);
- --channel, each api is connected to
API_TYPE : hub_api_config_t := (0,0,0,0,0,0,0,0);
API_FIFO_TO_INT_DEPTH : hub_api_config_t := (1,1,1,1,1,1,1,1);
API_FIFO_TO_APL_DEPTH : hub_api_config_t := (1,1,1,1,1,1,1,1);
MED_DATA_OUT : out std_logic_vector (15 downto 0);
MED_PACKET_NUM_OUT : out std_logic_vector (1 downto 0);
MED_ERROR_OUT : out std_logic_vector (2 downto 0);
- STAT : out std_logic_vector (31 downto 0)
+ STAT : out std_logic_vector (63 downto 0)
);
end trb_net16_med_tlk;
signal TLK_CLK_neg : std_logic;
signal CLK_Out, CLK_FB_Out, FB_CLK : std_logic;
+
+ signal buf_STAT : std_logic_vector(33 downto 32);
+
begin
-- STAT(3 downto 0) <= fifo_status_a;
STAT(6) <= fifo_rd_en_m;
STAT(7) <= fifo_empty_m;
STAT(8) <= fifo_full_a;
+ STAT(9) <= fifo_full_m;
STAT(14) <= reg_RX_DV;
STAT(15) <= reg_RX_ER;
STAT(31 downto 16) <= reg_RXD;
+
+ STAT(32) <= buf_STAT(32);
+ STAT(33) <= buf_STAT(33);
+ STAT(39 downto 36) <= fifo_status_a;
+ STAT(43 downto 40) <= fifo_status_m;
+
+
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if internal_reset = '1' then
+ buf_STAT(32) <= '0';
+ buf_STAT(33) <= '0';
+ else
+ buf_STAT(32) <= fifo_full_a or buf_STAT(32);
+ buf_STAT(33) <= fifo_full_m or buf_STAT(33);
+ end if;
+ end if;
+ end process;
process(TLK_RX_CLK)
begin
-- --
----------------------------------------------------------------
--- proc10: PROCESS (read_clock, fifo_gsr)
--- BEGIN
--- IF (fifo_gsr = '1') THEN
--- read_truegray <= "000000000";
--- ELSIF (read_clock'EVENT AND read_clock = '1') THEN
--- read_truegray(8) <= read_addr(8);
--- read_truegray(7) <= read_addr(8) XOR read_addr(7);
--- read_truegray(6) <= read_addr(7) XOR read_addr(6);
--- read_truegray(5) <= read_addr(6) XOR read_addr(5);
--- read_truegray(4) <= read_addr(5) XOR read_addr(4);
--- read_truegray(3) <= read_addr(4) XOR read_addr(3);
--- read_truegray(2) <= read_addr(3) XOR read_addr(2);
--- read_truegray(1) <= read_addr(2) XOR read_addr(1);
--- read_truegray(0) <= read_addr(1) XOR read_addr(0);
--- end IF;
--- end PROCESS proc10;
---
--- proc11: PROCESS (write_clock, fifo_gsr)
--- BEGIN
--- IF (fifo_gsr = '1') THEN
--- rag_writesync <= "000000000";
--- ELSIF (write_clock'EVENT AND write_clock = '1') THEN
--- rag_writesync <= read_truegray;
--- end IF;
--- end PROCESS proc11;
---
--- xorout(0) <= (rag_writesync(8) XOR rag_writesync(7) XOR rag_writesync(6) XOR
--- rag_writesync(5));
--- xorout(1) <= (rag_writesync(4) XOR rag_writesync(3) XOR rag_writesync(2) XOR
--- rag_writesync(1));
---
--- ra_writesync(8) <= rag_writesync(8);
--- ra_writesync(7) <= (rag_writesync(8) XOR rag_writesync(7));
--- ra_writesync(6) <= (rag_writesync(8) XOR rag_writesync(7) XOR rag_writesync(6));
--- ra_writesync(5) <= xorout(0);
--- ra_writesync(4) <= (xorout(0) XOR rag_writesync(4));
--- ra_writesync(3) <= (xorout(0) XOR rag_writesync(4) XOR rag_writesync(3));
--- ra_writesync(2) <= (xorout(0) XOR rag_writesync(4) XOR rag_writesync(3)
--- XOR rag_writesync(2));
--- ra_writesync(1) <= (xorout(0) XOR xorout(1));
--- ra_writesync(0) <= (xorout(0) XOR xorout(1) XOR rag_writesync(0));
---
--- proc12: PROCESS (write_clock, fifo_gsr)
--- BEGIN
--- IF (fifo_gsr = '1') THEN
--- write_addrr <= "000000000";
--- ELSIF (write_clock'EVENT AND write_clock = '1') THEN
--- write_addrr <= write_addr(8 downto 0);
--- end IF;
--- end PROCESS proc12;
---
--- proc13: PROCESS (write_clock, fifo_gsr)
--- BEGIN
--- IF (fifo_gsr = '1') THEN
--- fifostatus <= "000000000";
--- ELSIF (write_clock'EVENT AND write_clock = '1') THEN
--- IF (full = '0') THEN
--- fifostatus <= (write_addrr - ra_writesync);
--- end IF;
--- end IF;
--- end PROCESS proc13;
+proc10: PROCESS (read_clock, fifo_gsr)
+BEGIN
+ IF (fifo_gsr = '1') THEN
+ read_truegray <= "000000000";
+ ELSIF (read_clock'EVENT AND read_clock = '1') THEN
+ read_truegray(8) <= read_addr(8);
+ read_truegray(7) <= read_addr(8) XOR read_addr(7);
+ read_truegray(6) <= read_addr(7) XOR read_addr(6);
+ read_truegray(5) <= read_addr(6) XOR read_addr(5);
+ read_truegray(4) <= read_addr(5) XOR read_addr(4);
+ read_truegray(3) <= read_addr(4) XOR read_addr(3);
+ read_truegray(2) <= read_addr(3) XOR read_addr(2);
+ read_truegray(1) <= read_addr(2) XOR read_addr(1);
+ read_truegray(0) <= read_addr(1) XOR read_addr(0);
+ end IF;
+end PROCESS proc10;
+
+proc11: PROCESS (write_clock, fifo_gsr)
+BEGIN
+ IF (fifo_gsr = '1') THEN
+ rag_writesync <= "000000000";
+ ELSIF (write_clock'EVENT AND write_clock = '1') THEN
+ rag_writesync <= read_truegray;
+ end IF;
+end PROCESS proc11;
+
+xorout(0) <= (rag_writesync(8) XOR rag_writesync(7) XOR rag_writesync(6) XOR
+ rag_writesync(5));
+xorout(1) <= (rag_writesync(4) XOR rag_writesync(3) XOR rag_writesync(2) XOR
+ rag_writesync(1));
+
+ra_writesync(8) <= rag_writesync(8);
+ra_writesync(7) <= (rag_writesync(8) XOR rag_writesync(7));
+ra_writesync(6) <= (rag_writesync(8) XOR rag_writesync(7) XOR rag_writesync(6));
+ra_writesync(5) <= xorout(0);
+ra_writesync(4) <= (xorout(0) XOR rag_writesync(4));
+ra_writesync(3) <= (xorout(0) XOR rag_writesync(4) XOR rag_writesync(3));
+ra_writesync(2) <= (xorout(0) XOR rag_writesync(4) XOR rag_writesync(3)
+ XOR rag_writesync(2));
+ra_writesync(1) <= (xorout(0) XOR xorout(1));
+ra_writesync(0) <= (xorout(0) XOR xorout(1) XOR rag_writesync(0));
+
+proc12: PROCESS (write_clock, fifo_gsr)
+BEGIN
+ IF (fifo_gsr = '1') THEN
+ write_addrr <= "000000000";
+ ELSIF (write_clock'EVENT AND write_clock = '1') THEN
+ write_addrr <= write_addr(8 downto 0);
+ end IF;
+end PROCESS proc12;
+
+proc13: PROCESS (write_clock, fifo_gsr)
+BEGIN
+ IF (fifo_gsr = '1') THEN
+ fifostatus <= "000000000";
+ ELSIF (write_clock'EVENT AND write_clock = '1') THEN
+ IF (full = '0') THEN
+ fifostatus <= (write_addrr - ra_writesync);
+ end IF;
+ end IF;
+end PROCESS proc13;
----------------------------------------------------------------
-- --