small fixes

diff --git a/media_interfaces/sync/tx_control_RS.vhd b/media_interfaces/sync/tx_control_RS.vhd
index ef561ceb480bde776c3fd8d1a70ae677b71c142c..0aac1395139b10fe8d4018409cf93769f2b5a583 100644 (file)
--- a/media_interfaces/sync/tx_control_RS.vhd
+++ b/media_interfaces/sync/tx_control_RS.vhd
@@ -225,7 +225,7 @@ begin
 \r
 --RAM empty\r
   ram_empty <= '1' when ((last_ram_write_addr = ram_read_addr) or (CLEAR = '1')) else '0';\r
-  ram_afull <= '1' when (ram_fill_level >= 4) else '0';\r
+  ram_afull <= '1' when (ram_fill_level >= 4) else '0'; -- INCREASE TO CHECK FOR trbflash BUG\r
 \r
   last_ram_write_addr <= ram_write_addr when rising_edge(CLK_TXI);\r
 \r

diff --git a/special/clockbox.vhd b/special/clockbox.vhd
index 326c6302aa4e490afc7352cdba1f6c2f10e9af2c..155a3364a32f475fde6386b33b7a149ea4a79eeb 100644 (file)
--- a/special/clockbox.vhd
+++ b/special/clockbox.vhd
@@ -19,25 +19,26 @@ end entity clockbox;
 architecture clockbox_arch of clockbox is\r
 \r
 -- Components\r
-  component clockpoint is
-  port(
-    SAMPLE_CLK    : in  std_logic;
-    DATA_IN       : in  std_logic;
-    CLK_DATA      : in  std_logic;
-    DATA_OUT      : out std_logic
-  );
+  component clockpoint is\r
+  port(\r
+    SAMPLE_CLK    : in  std_logic;\r
+    DATA_IN       : in  std_logic;\r
+    CLK_DATA      : in  std_logic;\r
+    DATA_OUT      : out std_logic\r
+  );\r
   end component clockpoint;\r
 \r
 -- state machine signals\r
 \r
 -- Signals\r
 \r
-  attribute HGROUP : string;\r
-  attribute BBOX   : string;\r
-  attribute HGROUP of clockbox_arch : architecture is "clockbox_group";\r
-  attribute BBOX   of clockbox_arch : architecture is "1,2";\r
-  attribute syn_sharing : string;\r
-  attribute syn_sharing of clockbox_arch : architecture is "off";\r
+--  attribute HGROUP : string;\r
+--  attribute BBOX   : string;\r
+--  attribute HGROUP of clockbox_arch : architecture is "clockbox_group";\r
+--  attribute BBOX   of clockbox_arch : architecture is "1,2";\r
+--  attribute BBOX   of clockbox_arch : architecture is "2,1";\r
+--  attribute syn_sharing : string;\r
+--  attribute syn_sharing of clockbox_arch : architecture is "off";\r
   attribute syn_hier : string;\r
   attribute syn_hier of clockbox_arch : architecture is "hard";\r
   \r

diff --git a/special/phaserbox.vhd b/special/phaserbox.vhd
index 80a4a7650894bfcb1e0d63b4881cc7fff33a43c6..f2afec139575f8f94422ee4d72153da921fd5900 100644 (file)
--- a/special/phaserbox.vhd
+++ b/special/phaserbox.vhd
@@ -6,25 +6,30 @@ library work;
 \r
 entity phaserbox is\r
 port(\r
-  SAMPLE_CLK       : in  std_logic; -- auxiliary clock for sampling\r
-  RESET            : in  std_logic;\r
+  SAMPLE_CLK        : in  std_logic; -- auxiliary clock for sampling\r
+  RESET             : in  std_logic;\r
   -- input signals\r
-  TX_SYNC_IN       : in  std_logic; -- outgoing sync signal\r
-  TX_CLK_IN        : in  std_logic; -- TX clock \r
-  RX_SYNC_IN       : in  std_logic; -- incoming sync signal\r
-  RX_CLK_IN        : in  std_logic; -- RX clock\r
-  START_DELAY_IN   : in  std_logic; -- outgoing DLM komma\r
-  STOP_DELAY_IN    : in  std_logic; -- incoming DLM komma\r
+  TX_SYNC_IN        : in  std_logic; -- outgoing sync signal\r
+  TX_CLK_IN         : in  std_logic; -- TX clock \r
+  RX_SYNC_IN        : in  std_logic; -- incoming sync signal\r
+  RX_CLK_IN         : in  std_logic; -- RX clock\r
+  START_DELAY_IN    : in  std_logic; -- outgoing DLM komma\r
+  STOP_DELAY_IN     : in  std_logic; -- incoming DLM komma\r
   -- histogram\r
-  HISTO_CLK        : in  std_logic;\r
-  HISTO_START_IN   : in  std_logic;\r
-  HISTO_DONE_OUT   : out std_logic;\r
-  HISTO_ADDR_IN    : in  std_logic_vector(9 downto 0);\r
-  HISTO_DATA_OUT   : out std_logic_vector(17 downto 0);\r
+  HISTO_CLK         : in  std_logic;\r
+  HISTO_START_IN    : in  std_logic;\r
+  HISTO_DONE_OUT    : out std_logic;\r
+  HISTO_ADDR_IN     : in  std_logic_vector(9 downto 0);\r
+  HISTO_DATA_OUT    : out std_logic_vector(31 downto 0);\r
+  HISTO_READ_IN     : in  std_logic;\r
+  HISTO_WRITE_IN    : in  std_logic;\r
+  HISTO_ACK_OUT     : out std_logic;\r
+  HISTO_NACK_OUT    : out std_logic;\r
+  HISTO_UNKNOWN_OUT : out std_logic;\r
   -- \r
-  COARSE_DELAY_OUT : out std_logic_vector(31 downto 0);\r
+  COARSE_DELAY_OUT  : out std_logic_vector(31 downto 0);\r
   --\r
-  DEBUG_OUT        : out std_logic_vector(15 downto 0)\r
+  DEBUG_OUT         : out std_logic_vector(15 downto 0)\r
 );\r
 end entity phaserbox;\r
 \r
@@ -105,8 +110,13 @@ architecture phaserbox_arch of phaserbox is
   signal cal_phase_q          : std_logic; -- OBSELETE\r
   signal toggle_q             : std_logic; -- OBSELETE\r
   signal coarse_delay_i       : std_logic_vector(31 downto 0);\r
+  signal ack_delay            : std_logic_vector(2 downto 0);\r
+  signal ack_delay_x          : std_logic;\r
   signal debug                : std_logic_vector(15 downto 0);\r
 \r
+  signal histo_data_i         : std_logic_vector(31 downto 0);\r
+  signal histo_done_i         : std_logic;\r
+  \r
   attribute HGROUP : string;\r
 --  attribute BBOX   : string;\r
   attribute HGROUP of phaserbox_arch : architecture is "phaserbox_group";\r
@@ -173,12 +183,25 @@ begin
     FSM_ACTIVE_OUT   => fsm_active_i,\r
     FSM_CE_OUT       => fsm_ce_i,\r
     FSM_RST_OUT      => fsm_rst_i,\r
-    FSM_DONE_OUT     => HISTO_DONE_OUT,\r
+    FSM_DONE_OUT     => histo_done_i,\r
     RD_CLK           => HISTO_CLK,\r
     RD_ADDRESS_IN    => HISTO_ADDR_IN,\r
-    RD_DATA_OUT      => HISTO_DATA_OUT\r
+    RD_DATA_OUT      => histo_data_i(17 downto 0)\r
   );\r
 \r
+  histo_data_i(31)           <= histo_done_i;\r
+  histo_data_i(30 downto 18) <= (others => '0');\r
+  \r
+  -- simple readout\r
+  ack_delay_x <= HISTO_READ_IN or HISTO_WRITE_IN;\r
+\r
+  THE_ACK_DELAY_PROC: process( HISTO_CLK ) \r
+  begin\r
+    if( rising_edge(HISTO_CLK) ) then\r
+      ack_delay <= ack_delay(1 downto 0) & ack_delay_x;\r
+    end if;\r
+  end process THE_ACK_DELAY_PROC;\r
+    \r
   -- DEBUG\r
   debug(15 downto 6) <= (others => '0');\r
   debug(5)  <= start_rx_sync_i;\r
@@ -189,7 +212,12 @@ begin
   debug(0)  <= stretched_tx_sync_i;\r
 \r
   -- Outputs\r
-  COARSE_DELAY_OUT <= cal_phase_q & coarse_delay_i(30 downto 0);\r
-  DEBUG_OUT        <= debug;\r
+  COARSE_DELAY_OUT   <= cal_phase_q & coarse_delay_i(30 downto 0); -- workaround\r
+  HISTO_DONE_OUT     <= histo_done_i;\r
+  HISTO_DATA_OUT     <= histo_data_i;\r
+  HISTO_ACK_OUT      <= ack_delay(2);\r
+  HISTO_NACK_OUT     <= '0';\r
+  HISTO_UNKNOWN_OUT  <= '0';\r
+  DEBUG_OUT          <= debug;\r
 \r
 end architecture;\r

diff --git a/special/trb_net_i2cwire.vhd b/special/trb_net_i2cwire.vhd
index 7bf8da6016d8916eed410119f35ce964091656be..264de3fec683632b003b024813cbf84dc7a17ebb 100644 (file)
--- a/special/trb_net_i2cwire.vhd
+++ b/special/trb_net_i2cwire.vhd
@@ -16,15 +16,15 @@ entity trb_net_i2cwire is
     RESET             : in    std_logic;\r
     READOUT_ENABLE_IN : in    std_logic := '1';\r
     --connection to I2C interface\r
-    SCL_INOUT         :  inout  std_logic;\r
-    SDA_INOUT         :  inout  std_logic;\r
+    SCL_INOUT         : inout std_logic;\r
+    SDA_INOUT         : inout std_logic;\r
     --connection to id ram, according to memory map in TrbNetRegIO\r
-    DATA_OUT          : out    std_logic_vector(15 downto 0);\r
-    ADDR_OUT          : out    std_logic_vector(2 downto 0);\r
-    WRITE_OUT         : out    std_logic;\r
-    TEMP_OUT          : out    std_logic_vector(11 downto 0);\r
-    ID_OUT            : out    std_logic_vector(63 downto 0);\r
-    STAT              : out    std_logic_vector(31 downto 0)\r
+    DATA_OUT          : out   std_logic_vector(15 downto 0);\r
+    ADDR_OUT          : out   std_logic_vector(2 downto 0);\r
+    WRITE_OUT         : out   std_logic;\r
+    TEMP_OUT          : out   std_logic_vector(11 downto 0);\r
+    ID_OUT            : out   std_logic_vector(63 downto 0);\r
+    STAT              : out   std_logic_vector(31 downto 0)\r
   );\r
 end trb_net_i2cwire;\r
 \r
@@ -36,18 +36,18 @@ architecture trb_net_i2cwire_arch of trb_net_i2cwire is
   signal CURRENT_STATE, NEXT_STATE: FSM_STATES;\r
 \r
   -- Signals\r
-  constant MAX_COUNTER      : integer := 2**28-1;  \r
-  signal timecounter        : integer range 0 to MAX_COUNTER;\r
+  constant MAX_COUNTER       : integer := 2**28-1;  \r
+  signal timecounter         : integer range 0 to MAX_COUNTER;\r
   signal rst_tc_x            : std_logic;\r
-  constant IDLE_PERIOD      : integer := 1000; -- unit [ns]\r
+  constant IDLE_PERIOD       : integer := 1000; -- unit [ns]\r
   constant READOUT_PERIOD    : integer := 1000000000; -- unit [ns]\r
-  constant I2C_CYCLE        : integer := 5000; -- unit [ns]\r
+  constant I2C_CYCLE         : integer := 5000; -- unit [ns]\r
   constant I2C_PERIOD        : integer := (((I2C_CYCLE / CLK_PERIOD) - 2)/8);\r
 \r
   signal ram_we_x            : std_logic;\r
   signal ram_we              : std_logic;\r
-  signal temp_we_x          : std_logic;\r
-  signal temp_we            : std_logic;\r
+  signal temp_we_x           : std_logic;\r
+  signal temp_we             : std_logic;\r
   \r
   signal i2c_go_x            : std_logic;\r
   signal i2c_go              : std_logic;\r
@@ -55,48 +55,48 @@ architecture trb_net_i2cwire_arch of trb_net_i2cwire is
   signal i2c_action_int      : std_logic;\r
   signal i2c_word_int        : std_logic;\r
   signal i2c_addr_int        : std_logic_vector(7 downto 0);\r
-  signal i2c_cmd_int        : std_logic_vector(7 downto 0);\r
+  signal i2c_cmd_int         : std_logic_vector(7 downto 0);\r
   signal i2c_dw_int          : std_logic_vector(15 downto 0);\r
   signal i2c_dr_int          : std_logic_vector(15 downto 0);\r
   signal i2c_status_int      : std_logic_vector(7 downto 0);\r
   signal i2c_busy_int        : std_logic;\r
   signal i2c_done_int        : std_logic;\r
-  signal i2c_bsm_int        : std_logic_vector(4 downto 0);\r
-  signal valid_int          : std_logic;\r
+  signal i2c_bsm_int         : std_logic_vector(4 downto 0);\r
+  signal valid_int           : std_logic;\r
 \r
   signal addr_int            : std_logic_vector(2 downto 0);\r
 \r
   signal id_int              : std_logic_vector(63 downto 0);\r
   signal temp_int            : std_logic_vector(11 downto 0);\r
 \r
-  signal sda_drv            : std_logic;\r
-  signal scl_drv            : std_logic;\r
+  signal sda_drv             : std_logic;\r
+  signal scl_drv             : std_logic;\r
   \r
   -- Components\r
   component i2c_slim is\r
     port(\r
-      CLOCK            : in    std_logic;\r
-      RESET            : in    std_logic;\r
+      CLOCK          : in  std_logic;\r
+      RESET          : in  std_logic;\r
       -- I2C command / setup\r
-      I2C_GO_IN        : in    std_logic; -- startbit to trigger I2C actions\r
-      ACTION_IN        : in    std_logic; -- '0' -> write, '1' -> read\r
-      WORD_IN          : in    std_logic; -- '0' -> byte, '1' -> word\r
-      I2C_SPEED_IN    : in    std_logic_vector(5 downto 0); -- speed adjustment (to be defined)\r
-      I2C_ADDR_IN      : in    std_logic_vector(7 downto 0); -- I2C address byte (R/W bit is ignored)\r
-      I2C_CMD_IN      : in    std_logic_vector(7 downto 0); -- I2C command byte (sent after address byte)\r
-      I2C_DW_IN        : in    std_logic_vector(15 downto 0); -- data word for write command\r
-      I2C_DR_OUT      : out    std_logic_vector(15 downto 0); -- data word from read command\r
-      STATUS_OUT      : out    std_logic_vector(7 downto 0); -- status and error bits\r
-      VALID_OUT        : out    std_logic;\r
-      I2C_BUSY_OUT    : out    std_logic;\r
-      I2C_DONE_OUT    : out    std_logic;\r
+      I2C_GO_IN      : in  std_logic; -- startbit to trigger I2C actions\r
+      ACTION_IN      : in  std_logic; -- '0' -> write, '1' -> read\r
+      WORD_IN        : in  std_logic; -- '0' -> byte, '1' -> word\r
+      I2C_SPEED_IN   : in  std_logic_vector(5 downto 0); -- speed adjustment (to be defined)\r
+      I2C_ADDR_IN    : in  std_logic_vector(7 downto 0); -- I2C address byte (R/W bit is ignored)\r
+      I2C_CMD_IN     : in  std_logic_vector(7 downto 0); -- I2C command byte (sent after address byte)\r
+      I2C_DW_IN      : in  std_logic_vector(15 downto 0); -- data word for write command\r
+      I2C_DR_OUT     : out std_logic_vector(15 downto 0); -- data word from read command\r
+      STATUS_OUT     : out std_logic_vector(7 downto 0); -- status and error bits\r
+      VALID_OUT      : out std_logic;\r
+      I2C_BUSY_OUT   : out std_logic;\r
+      I2C_DONE_OUT   : out std_logic;\r
       -- I2C connections\r
-      SDA_IN          : in    std_logic;\r
-      SDA_OUT          : out    std_logic;\r
-      SCL_IN          : in    std_logic;\r
-      SCL_OUT          : out    std_logic;\r
+      SDA_IN         : in  std_logic;\r
+      SDA_OUT        : out std_logic;\r
+      SCL_IN         : in  std_logic;\r
+      SCL_OUT        : out std_logic;\r
       -- Debug\r
-      BSM_OUT          : out    std_logic_vector(4 downto 0)\r
+      BSM_OUT        : out std_logic_vector(4 downto 0)\r
     );\r
   end component i2c_slim;\r
 \r
@@ -117,7 +117,7 @@ begin
     else\r
       CURRENT_STATE <= NEXT_STATE;\r
       ram_we        <= ram_we_x;\r
-      temp_we        <= temp_we_x;\r
+      temp_we       <= temp_we_x;\r
       i2c_go        <= i2c_go_x;\r
     end if;\r
   end if;\r