# alternative, if needed\r
# LOCATE COMP "EXT_IN_0" SITE "P28" ;\r
IOBUF PORT "EXT_IN_0" IO_TYPE=LVTTL33 ;\r
-# LOCATE COMP "DBG_EXP_41" SITE "T27" ;\r
-# LOCATE COMP "DBG_EXP_39" SITE "T26" ;\r
-# LOCATE COMP "DBG_EXP_37" SITE "U26" ;\r
-# LOCATE COMP "DBG_EXP_35" SITE "V25" ;\r
-# LOCATE COMP "DBG_EXP_33" SITE "W25" ;\r
-# LOCATE COMP "DBG_EXP_31" SITE "W26" ;\r
-# LOCATE COMP "DBG_EXP_29" SITE "Y26" ;\r
-# LOCATE COMP "DBG_EXP_27" SITE "Y27" ;\r
-# LOCATE COMP "DBG_EXP_25" SITE "AB26" ;\r
-# LOCATE COMP "DBG_EXP_23" SITE "AC27" ;\r
-# LOCATE COMP "DBG_EXP_21" SITE "U25" ;\r
-# LOCATE COMP "DBG_EXP_19" SITE "U28" ;\r
-# LOCATE COMP "DBG_EXP_17" SITE "U27" ;\r
-# LOCATE COMP "DBG_EXP_5" SITE "R28" ;\r
-# LOCATE COMP "DBG_EXP_3" SITE "R27" ;\r
-# LOCATE COMP "DBG_EXP_1" SITE "T28" ;\r
+LOCATE COMP "DBG_EXP_41" SITE "T27" ;\r
+LOCATE COMP "DBG_EXP_39" SITE "T26" ;\r
+LOCATE COMP "DBG_EXP_37" SITE "U26" ;\r
+LOCATE COMP "DBG_EXP_35" SITE "V25" ;\r
+LOCATE COMP "DBG_EXP_33" SITE "W25" ;\r
+LOCATE COMP "DBG_EXP_31" SITE "W26" ;\r
+LOCATE COMP "DBG_EXP_29" SITE "Y26" ;\r
+LOCATE COMP "DBG_EXP_27" SITE "Y27" ;\r
+LOCATE COMP "DBG_EXP_25" SITE "AB26" ;\r
+LOCATE COMP "DBG_EXP_23" SITE "AC27" ;\r
+LOCATE COMP "DBG_EXP_21" SITE "U25" ;\r
+LOCATE COMP "DBG_EXP_19" SITE "U28" ;\r
+LOCATE COMP "DBG_EXP_17" SITE "U27" ;\r
+LOCATE COMP "DBG_EXP_5" SITE "R28" ;\r
+LOCATE COMP "DBG_EXP_3" SITE "R27" ;\r
+LOCATE COMP "DBG_EXP_1" SITE "T28" ;\r
LOCATE COMP "UC_REBOOT" SITE "Y28" ; # was UC_FPGA3\r
IOBUF PORT "UC_REBOOT" IO_TYPE=LVTTL33 ;\r
# LOCATE COMP "UC_FPGA_2" SITE "W27" ;\r
# I/O bank 2 - 3.30V\r
# SFP control, LEDs, 1Wire ID, debug pins (SMC50)\r
######################################################################\r
-# LOCATE COMP "DBG_EXP_43" SITE "R26" ;\r
-# LOCATE COMP "DBG_EXP_42" SITE "P25" ;\r
-# LOCATE COMP "DBG_EXP_40" SITE "P26" ;\r
-# LOCATE COMP "DBG_EXP_38" SITE "N25" ;\r
-# LOCATE COMP "DBG_EXP_36" SITE "M25" ;\r
-# LOCATE COMP "DBG_EXP_34" SITE "M26" ;\r
-# LOCATE COMP "DBG_EXP_32" SITE "L25" ;\r
-# LOCATE COMP "DBG_EXP_30" SITE "L26" ;\r
-# LOCATE COMP "DBG_EXP_28" SITE "K25" ;\r
-# LOCATE COMP "DBG_EXP_26" SITE "J26" ;\r
-# LOCATE COMP "DBG_EXP_24" SITE "H25" ;\r
-# LOCATE COMP "DBG_EXP_22" SITE "H26" ;\r
-# LOCATE COMP "DBG_EXP_20" SITE "H24" ;\r
-# LOCATE COMP "DBG_EXP_18" SITE "G26" ;\r
-# LOCATE COMP "DBG_EXP_16" SITE "G25" ;\r
-# LOCATE COMP "DBG_EXP_15" SITE "L27" ;\r
-# LOCATE COMP "DBG_EXP_14" SITE "L28" ;\r
-# LOCATE COMP "DBG_EXP_13" SITE "M28" ;\r
-# LOCATE COMP "DBG_EXP_12" SITE "K24" ;\r
-# LOCATE COMP "DBG_EXP_11" SITE "M27" ;\r
-# LOCATE COMP "DBG_EXP_10" SITE "M30" ;\r
-# LOCATE COMP "DBG_EXP_9" SITE "N26" ;\r
-# LOCATE COMP "DBG_EXP_8" SITE "M29" ;\r
-# LOCATE COMP "DBG_EXP_7" SITE "P27" ;\r
-# LOCATE COMP "DBG_EXP_6" SITE "L30" ;\r
-# LOCATE COMP "DBG_EXP_4" SITE "L29" ;\r
-# LOCATE COMP "DBG_EXP_2" SITE "K30" ;\r
-# LOCATE COMP "DBG_EXP_0" SITE "K29" ;\r
+LOCATE COMP "DBG_EXP_43" SITE "R26" ;\r
+LOCATE COMP "DBG_EXP_42" SITE "P25" ;\r
+LOCATE COMP "DBG_EXP_40" SITE "P26" ;\r
+LOCATE COMP "DBG_EXP_38" SITE "N25" ;\r
+LOCATE COMP "DBG_EXP_36" SITE "M25" ;\r
+LOCATE COMP "DBG_EXP_34" SITE "M26" ;\r
+LOCATE COMP "DBG_EXP_32" SITE "L25" ;\r
+LOCATE COMP "DBG_EXP_30" SITE "L26" ;\r
+LOCATE COMP "DBG_EXP_28" SITE "K25" ;\r
+LOCATE COMP "DBG_EXP_26" SITE "J26" ;\r
+LOCATE COMP "DBG_EXP_24" SITE "H25" ;\r
+LOCATE COMP "DBG_EXP_22" SITE "H26" ;\r
+LOCATE COMP "DBG_EXP_20" SITE "H24" ;\r
+LOCATE COMP "DBG_EXP_18" SITE "G26" ;\r
+LOCATE COMP "DBG_EXP_16" SITE "G25" ;\r
+LOCATE COMP "DBG_EXP_15" SITE "L27" ;\r
+LOCATE COMP "DBG_EXP_14" SITE "L28" ;\r
+LOCATE COMP "DBG_EXP_13" SITE "M28" ;\r
+LOCATE COMP "DBG_EXP_12" SITE "K24" ;\r
+LOCATE COMP "DBG_EXP_11" SITE "M27" ;\r
+LOCATE COMP "DBG_EXP_10" SITE "M30" ;\r
+LOCATE COMP "DBG_EXP_9" SITE "N26" ;\r
+LOCATE COMP "DBG_EXP_8" SITE "M29" ;\r
+LOCATE COMP "DBG_EXP_7" SITE "P27" ;\r
+LOCATE COMP "DBG_EXP_6" SITE "L30" ;\r
+LOCATE COMP "DBG_EXP_4" SITE "L29" ;\r
+LOCATE COMP "DBG_EXP_2" SITE "K30" ;\r
+LOCATE COMP "DBG_EXP_0" SITE "K29" ;\r
LOCATE COMP "FPGA_LED_6" SITE "G28" ;\r
IOBUF PORT "FPGA_LED_6" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ;\r
LOCATE COMP "FPGA_LED_5" SITE "G27" ;\r
# simplify IO definitions\r
######################################################################\r
# Debug header (50pin SMC connector)\r
-# DEFINE PORT GROUP "debug_header_group" "DBG_EXP_{0:43}" ;\r
-# IOBUF GROUP "debug_header_group" IO_TYPE=LVCMOS33 PULLMODE=DOWN DRIVE=4 SLEWRATE=FAST ;\r
+DEFINE PORT GROUP "debug_header_group" "DBG_EXP_{0:43}" ;\r
+IOBUF GROUP "debug_header_group" IO_TYPE=LVCMOS33 PULLMODE=DOWN SLEWRATE=FAST ;\r
\r
# LED drivers\r
# DEFINE PORT GROUP "led_output_group" "FPGA_LED*" ;\r
add_file -vhdl -lib work "../trbnet/trb_net_std.vhd"
add_file -vhdl -lib work "../trbnet/trb_net_components.vhd"
add_file -vhdl -lib work "source/adcmv3_components.vhd"
+add_file -vhdl -lib work "source/adcmv3_components2.vhd"
# ADCMv3 design files
# Top level entity
add_file -vhdl -lib work "source/slave_bus.vhd"
add_file -vhdl -lib work "source/rich_trb.vhd"
+# Addons
+add_file -vhdl -lib work "source/debug_multiplexer.vhd"
+
# Core files
add_file -vhdl -lib work "cores/adc_ch_in.vhd"
add_file -vhdl -lib work "cores/eds_buffer_dpram.vhd"
U_SPI_CS : out std_logic; -- OK -- chip select for SPI boot FlashROM\r
U_SPI_SCK : out std_logic; -- OK -- clock\r
U_SPI_SDI : out std_logic; -- OK -- connects to SI on the FlashROM\r
- U_SPI_SDO : in std_logic -- OK -- connects to SO on the FlashROM\r
+ U_SPI_SDO : in std_logic; -- OK -- connects to SO on the FlashROM\r
-- Debug connections\r
--- DBG_EXP : out std_logic_vector(43 downto 0) -- OK -- SMC50 debug header\r
+ DBG_EXP : out std_logic_vector(43 downto 0) -- OK -- SMC50 debug header\r
);\r
end;\r
\r
signal adc_ctrl_reg : reg_16bit_t;\r
signal adc_stat_reg : reg_16bit_t;\r
signal raw_buf_dbg : reg_16bit_t;\r
-\r
---signal debug : std_logic_vector(42 downto 0);\r
---signal debug_q : std_logic_vector(42 downto 0);\r
---signal debug_qq : std_logic_vector(42 downto 0);\r
---signal debug_clk : std_logic;\r
\r
-- LVL1 application interface\r
signal lvl1_trg_type : std_logic_vector(3 downto 0);\r
\r
signal tick_10s : std_logic;\r
\r
+-- Debug Multiplexer\r
+signal debug_o : std_logic_vector(33 downto 0);\r
+\r
begin\r
\r
\r
+-------------------------------------------------------------------------------\r
+-- Debug Out \r
+-------------------------------------------------------------------------------\r
+ \r
+ DEBUG: for I in 0 to 15 generate\r
+ debug_o(2 * I) <= sysclk;\r
+ debug_o(2 * I + 1) <= not sysclk;\r
+ end generate DEBUG;\r
+ debug_o(32) <= sysclk;\r
+ debug_o(33) <= not sysclk;\r
+ \r
+ DBG_EXP(31 downto 0) <= debug_o(31 downto 0);\r
+ DBG_EXP(37 downto 32) <= (others => '0');\r
+ DBG_EXP(38) <= debug_o(32);\r
+ DBG_EXP(41 downto 49) <= (others => '0');\r
+ DBG_EXP(42) <= debug_o(33);\r
+ DBG_EXP(43) <= '0';\r
+ \r
----------------------------------------\r
-- Async reset assignment --\r
----------------------------------------\r
GEN_ADC_LVDS_ON: for i in 0 to 15 generate\r
adc_on(i) <= adc_ctrl_reg(i)(0);\r
lvds_on(i) <= adc_ctrl_reg(i)(1);\r
--- adc_stat_reg(i) <= raw_buf_dbg(i);\r
adc_stat_reg(i) <= buf_data(i)(37 downto 30) & raw_buf_debug(i*4+3 downto i*4+0) & std_logic_vector(to_unsigned(i,4));\r
broken_buf(i) <= buf_data(i)(36); -- BUF_BROKEN bit\r
apv_error(i) <= buf_data(i)(26); -- APV error frame bit\r
+++ /dev/null
-#!/usr/bin/perl
-###########################################
-# Script file to run the flow
-###########################################
-
-# You need the tunnels before!
-
-use Data::Dumper;
-use warnings;
-use strict;
-
-# Path settings for ispLEVER tools
-my $lattice_path = '/usr/local/opt/synplify/8/isptools';
-
-# Path settings for SynplifyPRO
-my $synplify_path = '/usr/local/opt/synplify/premier';
-# my $synplify_path = '/scratch/rich/synplify/D-2009.12';
-
-use FileHandle;
-
-$ENV{'SYNPLIFY'}=$synplify_path;
-$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1;
-$ENV{'LM_LICENSE_FILE'}="27000\@localhost";
-
-# Design top level entity
-my $TOPNAME="adcmv3";
-
-# FPGA chip description
-my $FAMILYNAME="LATTICEECP2M";
-my $DEVICENAME="LFE2M100E";
-my $PACKAGE="FPBGA900";
-my $SPEEDGRADE="6";
-
-# benchmarking
-my $CTIME_String = localtime(time);
-print "Script started: $CTIME_String\n";
-system("echo $CTIME_String > workdir/benchmark.txt");
-
-# cleanup in workdir
-system("rm workdir/$TOPNAME.alt");
-system("rm workdir/$TOPNAME.bgn");
-system("rm workdir/$TOPNAME.bit");
-system("rm workdir/$TOPNAME.edf");
-system("rm workdir/$TOPNAME.fse");
-system("rm workdir/$TOPNAME.mrp");
-system("rm workdir/$TOPNAME.ncd");
-system("rm workdir/$TOPNAME.ngd");
-system("rm workdir/$TOPNAME.ngo");
-system("rm workdir/$TOPNAME.ngy");
-system("rm workdir/$TOPNAME.pad");
-system("rm workdir/$TOPNAME.par");
-system("rm workdir/$TOPNAME.sr?");
-system("rm workdir/$TOPNAME.tlg");
-system("rm workdir/$TOPNAME.twr*");
-
-# Create full lpf file
-#system("cp ../trbnet/pinout/$TOPNAME.lpf workdir/$TOPNAME.lpf");
-#system("cat constraints_$TOPNAME.lpf >> workdir/$TOPNAME.lpf");
-system("cp ./$TOPNAME.lpf workdir/$TOPNAME.lpf");
-system("cat constraints_$TOPNAME.lpf >> workdir/$TOPNAME.lpf");
-
-# Generate timestamp for slowcontrol readback
-my $t=time;
-my $fh = new FileHandle(">version.vhd");
-die "could not open file" if (! defined $fh);
-print $fh <<EOF;
-
---## attention, automatically generated. Don't change by hand.
-library ieee;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.std_logic_ARITH.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-use ieee.numeric_std.all;
-
-package version is
-
- constant VERSION_NUMBER_TIME : integer := $t;
-
-end package version;
-EOF
-$fh->close;
-
-# Run Synplify on the design
-system("env| grep LM_");
-my $r = "";
-my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME".".prj";
-$r=execute($c, "do_not_exit" );
-
-# Check for errors
-chdir "workdir";
-$fh = new FileHandle("<$TOPNAME".".srr");
-my @a = <$fh>;
-$fh -> close;
-
-foreach (@a)
-{
- if(/\@E:/)
- {
- $c="cat $TOPNAME.srr";
- system($c);
- print "ERROR_ERROR_ERROR_ERROR_ERROR\n";
- exit 129;
- }
-}
-
-# ispLEVER design flow starts here
-# new license file must be given
-$ENV{'LM_LICENSE_FILE'}="1710\@cronos.e12.physik.tu-muenchen.de";
-
-# EDIF2NGD
-$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |;
-execute($c);
-
-$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|;
-execute($c);
-
-# NGDBUILD
-$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/or5s00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|;
-execute($c);
-
-# MAP
-my $tpmap = $TOPNAME . "_map" ;
-$c=qq|$lattice_path/ispfpga/bin/lin/map -noinferGSR -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf" -tdm -td_pack|;
-execute($c);
-
-system("rm $TOPNAME.ncd");
-
-# MULTIPAR
-
-my $fh2 = new FileHandle(">$TOPNAME.p2t");
-die "could not open file" if (! defined $fh2);
-print $fh2 <<EOF;
-
--w
--i 5
--l 5
--n 8
--t 1
--s 1
--c 1
--e 2
--m nodelist.txt
--exp parCDP=1
--exp parCDR=1
--exp parPlcInLimit=0
--exp parPlcInNeighborSize=1
--exp parPathBased=ON
--exp parHold=ON
-
-EOF
-$fh2->close;
-
-######################################################################
-# -w # overwrite files
-# -i 15 # maximum number of routing attempts
-# -l 5 # effort level (1-5)
-# -n 1 # starting cost table (n=0 loop)
-# -y # delay summary report
-# -s 12 # number of best results to save
-# -t 1 # start placement with cost table X
-# -c 1 # number of cost-based cleanup passes of the router
-# -e 2 # number of delay-based cleanup passes of the router
-# -m nodelist.txt #
-# -exp parCDP=1 #
-# -exp parCDR=1 #
-# -exp parPlcInLimit=0 #
-# -exp parPlcInNeighborSize=1 #
-# -exp parPathBased=ON #
-# -exp parHold=ON #
-# -exp parHoldLimit=10000 #
-# -exp paruseNBR=1 #
-######################################################################
-
-# real multipar
-$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|;
-execute($c);
-
-# IOR IO Timing Report
-#$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|;
-#execute($c);
-
-# TWR Timing Report (setup)
-$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|;
-execute($c);
-
-# TWR Timing Report (hold)
-$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|;
-execute($c);
-
-# BitGen
-#$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" -f "$TOPNAME.t2b" "$TOPNAME.prf"|;
-$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|;
-execute($c);
-
-chdir "..";
-
-$CTIME_String = localtime(time);
-print "Script ended: $CTIME_String\n";
-system("echo $CTIME_String >> workdir/benchmark.txt");
-
-exit;
-
-sub execute {
- my ($c, $op) = @_;
- #print "option: $op \n";
- $op = "" if(!$op);
- print "\n\ncommand to execute: $c \n";
- $r=system($c);
- if($r) {
- print "$!";
- if($op ne "do_not_exit") {
- exit;
- }
- }
-
- return $r;
-
-}
+++ /dev/null
-#!/usr/bin/perl
-use Data::Dumper;
-use warnings;
-use strict;
-
-
-
-
-###################################################################################
-#Settings for this project
-my $TOPNAME = "adcmv3"; #Name of top-level entity
-my $lattice_path = '/usr/local/opt/lattice_diamond/diamond/2.1';
-my $synplify_path = '/usr/local/opt/synplify/F-2012.03-SP1/';
-my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de";
-my $lm_license_file_for_par = "1702\@hadeb05.gsi.de";
-###################################################################################
-
-
-
-use FileHandle;
-
-$ENV{'SYNPLIFY'}=$synplify_path;
-$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1;
-$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify;
-
-
-# FPGA chip description
-my $FAMILYNAME="LATTICEECP2M";
-my $DEVICENAME="LFE2M100E";
-my $PACKAGE="FPBGA900";
-my $SPEEDGRADE="6";
-
-#create full lpf file
-system("cp ./$TOPNAME.lpf workdir/$TOPNAME.lpf");
-system("cat constraints_$TOPNAME.lpf >> workdir/$TOPNAME.lpf");
-#system("cp ../base/$TOPNAME"."_nxyter.lpf workdir/$TOPNAME.lpf");
-#system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf");
-
-#set -e
-#set -o errexit
-
-#generate timestamp
-my $t=time;
-my $fh = new FileHandle(">version.vhd");
-die "could not open file" if (! defined $fh);
-print $fh <<EOF;
-
---## attention, automatically generated. Don't change by hand.
-library ieee;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.std_logic_ARITH.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-use ieee.numeric_std.all;
-
-package version is
-
- constant VERSION_NUMBER_TIME : integer := $t;
-
-end package version;
-EOF
-$fh->close;
-
-system("env| grep LM_");
-my $r = "";
-
-my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj";
-$r=execute($c, "do_not_exit" );
-
-
-chdir "workdir";
-$fh = new FileHandle("<$TOPNAME".".srr");
-my @a = <$fh>;
-$fh -> close;
-
-
-
-foreach (@a)
-{
- if(/\@E:/)
- {
- print "\n";
- $c="cat $TOPNAME.srr | grep \"\@E\"";
- system($c);
- print "\n\n";
- exit 129;
- }
-}
-
-
-$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par;
-
-$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |;
-execute($c);
-
-$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|;
-execute($c);
-
-$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|;
-execute($c);
-
-my $tpmap = $TOPNAME . "_map" ;
-
-$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|;
-execute($c);
-
-system("rm $TOPNAME.ncd");
-
-
-$c=qq|$lattice_path/ispfpga/bin/lin/par -f "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd" "$TOPNAME.prf"|;
-execute($c);
-
-# IOR IO Timing Report
-$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|;
-execute($c);
-
-# TWR Timing Report
-$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|;
-execute($c);
-
-$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|;
-execute($c);
-
-#$c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|;
-#execute($c);
-
-$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No $TOPNAME.ncd $TOPNAME.bit $TOPNAME.prf|;
-# $c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|;
-execute($c);
-
-chdir "..";
-
-exit;
-
-sub execute {
- my ($c, $op) = @_;
- #print "option: $op \n";
- $op = "" if(!$op);
- print "\n\ncommand to execute: $c \n";
- $r=system($c);
- if($r) {
- print "$!";
- if($op ne "do_not_exit") {
- exit;
- }
- }
-
- return $r;
-
-}
+++ /dev/null
-#!/bin/sh
-
-. /usr/local/opt/lattice_diamond/diamond/2.1/bin/lin64/diamond_env
-
-exec ./compile_munich21.pl
-#exec ./compile.pl
MED_READ_OUT => med_read_out_int,
MED_STAT_OP_IN => med_stat_op,
MED_CTRL_OP_OUT => med_ctrl_op,
- -- LVL1 trigger APL
+
+ -- LVL1 trigger APL
LVL1_TRG_VALID_TIMING_OUT => open, --valid timing trigger has been received
LVL1_TRG_VALID_NOTIMING_OUT => open, --valid trigger without timing trigger has been received
LVL1_TRG_INVALID_OUT => open, --the current trigger is invalid (e.g. no timing trigger, no LVL1...)
LVL1_ERROR_PATTERN_IN => LVL1_ERROR_PATTERN_IN,
LVL1_TRG_RELEASE_IN => LVL1_TRG_RELEASE_IN,
LVL1_INT_TRG_NUMBER_OUT => open, -- internal trigger number from LVL1 endpoint
- -- IPU Port
+
+ -- IPU Port
IPU_NUMBER_OUT => IPU_NUMBER_OUT,
IPU_READOUT_TYPE_OUT => open, -- 4bit readout type
IPU_INFORMATION_OUT => IPU_INFORMATION_OUT,
IPU_READ_OUT => IPU_READ_OUT,
IPU_LENGTH_IN => IPU_LENGTH_IN,
IPU_ERROR_PATTERN_IN => IPU_ERROR_PATTERN_IN,
- -- Slow Control Data Port
+
+ -- Slow Control Data Port
REGIO_COMMON_STAT_REG_IN => common_stat_reg,
REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg,
REGIO_REGISTERS_IN => regio_stat_regs,
COMMON_CTRL_REG_STROBE => common_ctrl_reg_strobe, -- [1] means update on internal trigger number
STAT_REG_STROBE => open,
CTRL_REG_STROBE => open,
- --following ports only used when using internal data port
+
+ --following ports only used when using internal data port
REGIO_ADDR_OUT => REGIO_ADDR_OUT,
REGIO_READ_ENABLE_OUT => REGIO_READ_ENABLE_OUT,
REGIO_WRITE_ENABLE_OUT => REGIO_WRITE_ENABLE_OUT,
REGIO_WRITE_ACK_IN => REGIO_WRITE_ACK_IN,
REGIO_UNKNOWN_ADDR_IN => REGIO_UNKNOWN_ADDR_IN,
REGIO_TIMEOUT_OUT => REGIO_TIMEOUT_OUT,
- --IDRAM is used if no 1-wire interface, onewire used otherwise
+
+ --IDRAM is used if no 1-wire interface, onewire used otherwise
REGIO_IDRAM_DATA_IN => x"0000", -- not used
REGIO_IDRAM_DATA_OUT => open, -- not used
REGIO_IDRAM_ADDR_IN => "000", -- not used
REGIO_ONEWIRE_INOUT => ONEWIRE_INOUT,
REGIO_ONEWIRE_MONITOR_IN => '1', -- not used
REGIO_ONEWIRE_MONITOR_OUT => open, -- not used
- -- New stuff
+
+ -- New stuff
GLOBAL_TIME_OUT => open,
LOCAL_TIME_OUT => open,
TIME_SINCE_LAST_TRG_OUT => open,
TIMER_TICKS_OUT(1) => tick_1ms, -- ms ticks
TIMER_TICKS_OUT(0) => open, -- us ticks
- -- Status and debug
+
+ -- Status and debug
STAT_DEBUG_IPU => open,
STAT_DEBUG_1 => stat_debug_1, --open,
STAT_DEBUG_2 => open,
architecture Behavioral of slave_bus is\r
\r
-- Signals\r
-signal slv_read : std_logic_vector(18-1 downto 0);\r
-signal slv_write : std_logic_vector(18-1 downto 0);\r
+constant NUM_PORTS : integer := 18;\r
+signal slv_read : std_logic_vector(NUM_PORTS-1 downto 0);\r
+signal slv_write : std_logic_vector(NUM_PORTS-1 downto 0);\r
signal slv_busy : std_logic_vector(18-1 downto 0);\r
-signal slv_ack : std_logic_vector(18-1 downto 0);\r
-signal slv_addr : std_logic_vector(18*16-1 downto 0);\r
-signal slv_data_rd : std_logic_vector(18*32-1 downto 0);\r
-signal slv_data_wr : std_logic_vector(18*32-1 downto 0);\r
+signal slv_no_more_data : std_logic_vector(NUM_PORTS-1 downto 0);\r
+signal slv_ack : std_logic_vector(NUM_PORTS-1 downto 0);\r
+signal slv_addr : std_logic_vector(NUM_PORTS*16-1 downto 0);\r
+signal slv_data_rd : std_logic_vector(NUM_PORTS*32-1 downto 0);\r
+signal slv_data_wr : std_logic_vector(NUM_PORTS*32-1 downto 0);\r
+signal slv_unknown_addr : std_logic_vector(NUM_PORTS-1 downto 0);\r
\r
-- SPI controller BRAM lines\r
signal spi_bram_addr : std_logic_vector(7 downto 0);\r
-- Bus handler: acts as bridge between RegIO and the FPGA internal slave bus\r
THE_BUS_HANDLER: trb_net16_regio_bus_handler\r
generic map(\r
- PORT_NUMBER => 18,\r
+ PORT_NUMBER => NUM_PORTS,\r
PORT_ADDRESSES => ( 0 => x"a000", -- pedestal memories\r
1 => x"a800", -- threshold memories\r
2 => x"8040", -- I2C master\r
15 => 4, -- FIFO status registers\r
16 => 0, -- LVL1 release status register\r
17 => 0, -- IPU handler status register\r
- others => 0)\r
-)\r
+ others => 0),\r
+ PORT_MASK_ENABLE => 1\r
+ )\r
port map(\r
CLK => CLK_IN,\r
RESET => RESET_IN,\r
DAT_WRITE_ACK_OUT => REGIO_WRITE_ACK_OUT,\r
DAT_NO_MORE_DATA_OUT => REGIO_NO_MORE_DATA_OUT,\r
DAT_UNKNOWN_ADDR_OUT => REGIO_UNKNOWN_ADDR_OUT,\r
- -- pedestal memories\r
- BUS_READ_ENABLE_OUT(0) => slv_read(0),\r
- BUS_WRITE_ENABLE_OUT(0) => slv_write(0),\r
- BUS_DATA_OUT(0*32+31 downto 0*32) => slv_data_wr(0*32+31 downto 0*32),\r
- BUS_DATA_IN(0*32+31 downto 0*32) => slv_data_rd(0*32+31 downto 0*32),\r
- BUS_ADDR_OUT(0*16+15 downto 0*16) => slv_addr(0*16+15 downto 0*16),\r
- BUS_TIMEOUT_OUT(0) => open,\r
- BUS_DATAREADY_IN(0) => slv_ack(0),\r
- BUS_WRITE_ACK_IN(0) => slv_ack(0),\r
- BUS_NO_MORE_DATA_IN(0) => slv_busy(0),\r
- BUS_UNKNOWN_ADDR_IN(0) => '0',\r
- -- threshold memories\r
- BUS_READ_ENABLE_OUT(1) => slv_read(1),\r
- BUS_WRITE_ENABLE_OUT(1) => slv_write(1),\r
- BUS_DATA_OUT(1*32+31 downto 1*32) => slv_data_wr(1*32+31 downto 1*32),\r
- BUS_DATA_IN(1*32+31 downto 1*32) => slv_data_rd(1*32+31 downto 1*32),\r
- BUS_ADDR_OUT(1*16+15 downto 1*16) => slv_addr(1*16+15 downto 1*16),\r
- BUS_TIMEOUT_OUT(1) => open,\r
- BUS_DATAREADY_IN(1) => slv_ack(1),\r
- BUS_WRITE_ACK_IN(1) => slv_ack(1),\r
- BUS_NO_MORE_DATA_IN(1) => slv_busy(1),\r
- BUS_UNKNOWN_ADDR_IN(1) => '0',\r
- -- I2C master\r
- BUS_READ_ENABLE_OUT(2) => slv_read(2),\r
- BUS_WRITE_ENABLE_OUT(2) => slv_write(2),\r
- BUS_DATA_OUT(2*32+31 downto 2*32) => slv_data_wr(2*32+31 downto 2*32),\r
- BUS_DATA_IN(2*32+31 downto 2*32) => slv_data_rd(2*32+31 downto 2*32),\r
- BUS_ADDR_OUT(2*16+15 downto 2*16) => open,\r
- BUS_TIMEOUT_OUT(2) => open,\r
- BUS_DATAREADY_IN(2) => slv_ack(2),\r
- BUS_WRITE_ACK_IN(2) => slv_ack(2),\r
- BUS_NO_MORE_DATA_IN(2) => slv_busy(2),\r
- BUS_UNKNOWN_ADDR_IN(2) => '0',\r
- -- OneWire master\r
- BUS_READ_ENABLE_OUT(3) => slv_read(3),\r
- BUS_WRITE_ENABLE_OUT(3) => slv_write(3),\r
- BUS_DATA_OUT(3*32+31 downto 3*32) => slv_data_wr(3*32+31 downto 3*32),\r
- BUS_DATA_IN(3*32+31 downto 3*32) => slv_data_rd(3*32+31 downto 3*32),\r
- BUS_ADDR_OUT(3*16+15 downto 3*16) => slv_addr(3*16+15 downto 3*16),\r
- BUS_TIMEOUT_OUT(3) => open,\r
- BUS_DATAREADY_IN(3) => slv_ack(3),\r
- BUS_WRITE_ACK_IN(3) => slv_ack(3),\r
- BUS_NO_MORE_DATA_IN(3) => slv_busy(3),\r
- BUS_UNKNOWN_ADDR_IN(3) => '0',\r
- -- SPI control registers\r
- BUS_READ_ENABLE_OUT(4) => slv_read(4),\r
- BUS_WRITE_ENABLE_OUT(4) => slv_write(4),\r
- BUS_DATA_OUT(4*32+31 downto 4*32) => slv_data_wr(4*32+31 downto 4*32),\r
- BUS_DATA_IN(4*32+31 downto 4*32) => slv_data_rd(4*32+31 downto 4*32),\r
- BUS_ADDR_OUT(4*16+15 downto 4*16) => slv_addr(4*16+15 downto 4*16),\r
- BUS_TIMEOUT_OUT(4) => open,\r
- BUS_DATAREADY_IN(4) => slv_ack(4),\r
- BUS_WRITE_ACK_IN(4) => slv_ack(4),\r
- BUS_NO_MORE_DATA_IN(4) => slv_busy(4),\r
- BUS_UNKNOWN_ADDR_IN(4) => '0',\r
- -- SPI data memory\r
- BUS_READ_ENABLE_OUT(5) => slv_read(5),\r
- BUS_WRITE_ENABLE_OUT(5) => slv_write(5),\r
- BUS_DATA_OUT(5*32+31 downto 5*32) => slv_data_wr(5*32+31 downto 5*32),\r
- BUS_DATA_IN(5*32+31 downto 5*32) => slv_data_rd(5*32+31 downto 5*32),\r
- BUS_ADDR_OUT(5*16+15 downto 5*16) => slv_addr(5*16+15 downto 5*16),\r
- BUS_TIMEOUT_OUT(5) => open,\r
- BUS_DATAREADY_IN(5) => slv_ack(5),\r
- BUS_WRITE_ACK_IN(5) => slv_ack(5),\r
- BUS_NO_MORE_DATA_IN(5) => slv_busy(5),\r
- BUS_UNKNOWN_ADDR_IN(5) => '0',\r
- -- ADC 0 SPI control registers\r
- BUS_READ_ENABLE_OUT(6) => slv_read(6),\r
- BUS_WRITE_ENABLE_OUT(6) => slv_write(6),\r
- BUS_DATA_OUT(6*32+31 downto 6*32) => slv_data_wr(6*32+31 downto 6*32),\r
- BUS_DATA_IN(6*32+31 downto 6*32) => slv_data_rd(6*32+31 downto 6*32),\r
- BUS_ADDR_OUT(6*16+15 downto 6*16) => open,\r
- BUS_TIMEOUT_OUT(6) => open,\r
- BUS_DATAREADY_IN(6) => slv_ack(6),\r
- BUS_WRITE_ACK_IN(6) => slv_ack(6),\r
- BUS_NO_MORE_DATA_IN(6) => slv_busy(6),\r
- BUS_UNKNOWN_ADDR_IN(6) => '0',\r
- -- ADC 1 SPI control registers\r
- BUS_READ_ENABLE_OUT(7) => slv_read(7),\r
- BUS_WRITE_ENABLE_OUT(7) => slv_write(7),\r
- BUS_DATA_OUT(7*32+31 downto 7*32) => slv_data_wr(7*32+31 downto 7*32),\r
- BUS_DATA_IN(7*32+31 downto 7*32) => slv_data_rd(7*32+31 downto 7*32),\r
- BUS_ADDR_OUT(7*16+15 downto 7*16) => open,\r
- BUS_TIMEOUT_OUT(7) => open,\r
- BUS_DATAREADY_IN(7) => slv_ack(7),\r
- BUS_WRITE_ACK_IN(7) => slv_ack(7),\r
- BUS_NO_MORE_DATA_IN(7) => slv_busy(7),\r
- BUS_UNKNOWN_ADDR_IN(7) => '0',\r
- -- APV control / status registers\r
- BUS_READ_ENABLE_OUT(8) => slv_read(8),\r
- BUS_WRITE_ENABLE_OUT(8) => slv_write(8),\r
- BUS_DATA_OUT(8*32+31 downto 8*32) => slv_data_wr(8*32+31 downto 8*32),\r
- BUS_DATA_IN(8*32+31 downto 8*32) => slv_data_rd(8*32+31 downto 8*32),\r
- BUS_ADDR_OUT(8*16+15 downto 8*16) => slv_addr(8*16+15 downto 8*16),\r
- BUS_TIMEOUT_OUT(8) => open,\r
- BUS_DATAREADY_IN(8) => slv_ack(8),\r
- BUS_WRITE_ACK_IN(8) => slv_ack(8),\r
- BUS_NO_MORE_DATA_IN(8) => slv_busy(8),\r
- BUS_UNKNOWN_ADDR_IN(8) => '0',\r
- -- ADC / PLL / trigger ctrl register\r
- BUS_READ_ENABLE_OUT(11 downto 9) => slv_read(11 downto 9),\r
- BUS_WRITE_ENABLE_OUT(11 downto 9) => slv_write(11 downto 9),\r
- BUS_DATA_OUT(11*32+31 downto 9*32) => slv_data_wr(11*32+31 downto 9*32),\r
- BUS_DATA_IN(11*32+31 downto 9*32) => slv_data_rd(11*32+31 downto 9*32),\r
- BUS_ADDR_OUT(11*16+15 downto 9*16) => open,\r
- BUS_TIMEOUT_OUT(11 downto 9) => open,\r
- BUS_DATAREADY_IN(11 downto 9) => slv_ack(11 downto 9),\r
- BUS_WRITE_ACK_IN(11 downto 9) => slv_ack(11 downto 9),\r
- BUS_NO_MORE_DATA_IN(11 downto 9) => slv_busy(11 downto 9),\r
- BUS_UNKNOWN_ADDR_IN(11 downto 9) => (others => '0'),\r
- -- ADC0 snooper\r
- BUS_READ_ENABLE_OUT(12) => slv_read(12),\r
- BUS_WRITE_ENABLE_OUT(12) => slv_write(12),\r
- BUS_DATA_OUT(12*32+31 downto 12*32) => slv_data_wr(12*32+31 downto 12*32),\r
- BUS_DATA_IN(12*32+31 downto 12*32) => slv_data_rd(12*32+31 downto 12*32),\r
- BUS_ADDR_OUT(12*16+15 downto 12*16) => slv_addr(12*16+15 downto 12*16),\r
- BUS_TIMEOUT_OUT(12) => open,\r
- BUS_DATAREADY_IN(12) => slv_ack(12),\r
- BUS_WRITE_ACK_IN(12) => slv_ack(12),\r
- BUS_NO_MORE_DATA_IN(12) => slv_busy(12),\r
- BUS_UNKNOWN_ADDR_IN(12) => '0',\r
- -- ADC1 snooper\r
- BUS_READ_ENABLE_OUT(13) => slv_read(13),\r
- BUS_WRITE_ENABLE_OUT(13) => slv_write(13),\r
- BUS_DATA_OUT(13*32+31 downto 13*32) => slv_data_wr(13*32+31 downto 13*32),\r
- BUS_DATA_IN(13*32+31 downto 13*32) => slv_data_rd(13*32+31 downto 13*32),\r
- BUS_ADDR_OUT(13*16+15 downto 13*16) => slv_addr(13*16+15 downto 13*16),\r
- BUS_TIMEOUT_OUT(13) => open,\r
- BUS_DATAREADY_IN(13) => slv_ack(13),\r
- BUS_WRITE_ACK_IN(13) => slv_ack(13),\r
- BUS_NO_MORE_DATA_IN(13) => slv_busy(13),\r
- BUS_UNKNOWN_ADDR_IN(13) => '0',\r
- -- Test register\r
- BUS_READ_ENABLE_OUT(14) => slv_read(14),\r
- BUS_WRITE_ENABLE_OUT(14) => slv_write(14),\r
- BUS_DATA_OUT(14*32+31 downto 14*32) => slv_data_wr(14*32+31 downto 14*32),\r
- BUS_DATA_IN(14*32+31 downto 14*32) => slv_data_rd(14*32+31 downto 14*32),\r
- BUS_ADDR_OUT(14*16+15 downto 14*16) => open,\r
- BUS_TIMEOUT_OUT(14) => open,\r
- BUS_DATAREADY_IN(14) => slv_ack(14),\r
- BUS_WRITE_ACK_IN(14) => slv_ack(14),\r
- BUS_NO_MORE_DATA_IN(14) => slv_busy(14),\r
- BUS_UNKNOWN_ADDR_IN(14) => '0',\r
- -- data buffer status registers\r
- BUS_READ_ENABLE_OUT(15) => slv_read(15),\r
- BUS_WRITE_ENABLE_OUT(15) => slv_write(15),\r
- BUS_DATA_OUT(15*32+31 downto 15*32) => slv_data_wr(15*32+31 downto 15*32),\r
- BUS_DATA_IN(15*32+31 downto 15*32) => slv_data_rd(15*32+31 downto 15*32),\r
- BUS_ADDR_OUT(15*16+15 downto 15*16) => slv_addr(15*16+15 downto 15*16),\r
- BUS_TIMEOUT_OUT(15) => open,\r
- BUS_DATAREADY_IN(15) => slv_ack(15),\r
- BUS_WRITE_ACK_IN(15) => slv_ack(15),\r
- BUS_NO_MORE_DATA_IN(15) => slv_busy(15),\r
- BUS_UNKNOWN_ADDR_IN(15) => '0',\r
- -- LVL1 release status register\r
- BUS_READ_ENABLE_OUT(16) => slv_read(16),\r
- BUS_WRITE_ENABLE_OUT(16) => slv_write(16),\r
- BUS_DATA_OUT(16*32+31 downto 16*32) => slv_data_wr(16*32+31 downto 16*32),\r
- BUS_DATA_IN(16*32+31 downto 16*32) => slv_data_rd(16*32+31 downto 16*32),\r
- BUS_ADDR_OUT(16*16+15 downto 16*16) => slv_addr(16*16+15 downto 16*16),\r
- BUS_TIMEOUT_OUT(16) => open,\r
- BUS_DATAREADY_IN(16) => slv_ack(16),\r
- BUS_WRITE_ACK_IN(16) => slv_ack(16),\r
- BUS_NO_MORE_DATA_IN(16) => slv_busy(16),\r
- BUS_UNKNOWN_ADDR_IN(16) => '0',\r
- -- IPU handler status register\r
- BUS_READ_ENABLE_OUT(17) => slv_read(17),\r
- BUS_WRITE_ENABLE_OUT(17) => slv_write(17),\r
- BUS_DATA_OUT(17*32+31 downto 17*32) => slv_data_wr(17*32+31 downto 17*32),\r
- BUS_DATA_IN(17*32+31 downto 17*32) => slv_data_rd(17*32+31 downto 17*32),\r
- BUS_ADDR_OUT(17*16+15 downto 17*16) => slv_addr(17*16+15 downto 17*16),\r
- BUS_TIMEOUT_OUT(17) => open,\r
- BUS_DATAREADY_IN(17) => slv_ack(17),\r
- BUS_WRITE_ACK_IN(17) => slv_ack(17),\r
- BUS_NO_MORE_DATA_IN(17) => slv_busy(17),\r
- BUS_UNKNOWN_ADDR_IN(17) => '0',\r
+\r
+ -- All Slow Control Ports\r
+ BUS_READ_ENABLE_OUT => slv_read,\r
+ BUS_WRITE_ENABLE_OUT => slv_write,\r
+ BUS_DATA_OUT => slv_data_wr,\r
+ BUS_DATA_IN => slv_data_rd,\r
+ BUS_ADDR_OUT => slv_addr,\r
+ BUS_TIMEOUT_OUT => open,\r
+ BUS_DATAREADY_IN => slv_ack,\r
+ BUS_WRITE_ACK_IN => slv_ack,\r
+ BUS_NO_MORE_DATA_IN => slv_no_more_data,\r
+ BUS_UNKNOWN_ADDR_IN => slv_unknown_addr,\r
+\r
-- debug\r
- STAT_DEBUG => stat\r
-);\r
+ STAT_DEBUG => stat\r
+ );\r
\r
\r
------------------------------------------------------------------------------------\r
MEM_15_D_OUT => PED_DATA_15_OUT,\r
-- Status lines\r
STAT => open\r
-);\r
+ );\r
slv_busy(0) <= '0';\r
\r
------------------------------------------------------------------------------------\r
);\r
\r
\r
-\r
-\r
-- unusable pins\r
debug(63 downto 43) <= (others => '0');\r
-- connected pins\r
jspc29 / adcm.git / commitdiff