File update, compiling, but media interface missing

diff --git a/code/sedcheck.vhd b/code/sedcheck.vhd
new file mode 100644 (file)
index 0000000..02087fe
--- /dev/null
+++ b/code/sedcheck.vhd
@@ -0,0 +1,224 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+
+library ecp5um;
+use ecp5um.components.all;
+
+entity sedcheck is
+  port(
+    CLK        : in std_logic;
+    ERROR_OUT  : out std_logic;
+    
+    BUS_RX     : in  CTRLBUS_RX;
+    BUS_TX     : out CTRLBUS_TX;
+    DEBUG      : out std_logic_vector(31 downto 0)
+    );
+end entity;
+
+
+architecture sed_arch of sedcheck is
+ 
+  component SEDCA
+    generic (
+      OSC_DIV : integer :=4 ;
+      CHECKALWAYS : string :="DISABLED";
+      AUTORECONFIG: string :="OFF" ;
+      MCCLK_FREQ : string :="20" ;
+      DEV_DENSITY : string :="150K" 
+      );
+    port (
+      SEDENABLE : in std_logic;
+      SEDSTART : in std_logic;
+      SEDFRCERR : in std_logic;
+      SEDERR : out std_logic;
+      SEDDONE : out std_logic;
+      SEDINPROG : out std_logic;
+      SEDCLKOUT : out std_logic
+      );
+  end component;  
+ 
+  type state_t is (IDLE, INIT_1, INIT_2, INIT_3, START_1, START_2, WAITACTIVE, WAITDONE);
+  signal state          : state_t;
+  signal state_bits     : std_logic_vector(3 downto 0);
+
+  signal sed_edge       : std_logic;
+  signal sed_clock_last : std_logic;
+
+  signal sed_clock      : std_logic;
+  signal sed_done       : std_logic;
+  signal sed_enable     : std_logic;
+  signal sed_error      : std_logic;
+  signal sed_inprogress : std_logic;
+  signal sed_start      : std_logic;
+
+  signal sed_clock_q      : std_logic;
+  signal sed_done_q       : std_logic;
+  signal sed_error_q      : std_logic;
+  signal sed_inprogress_q : std_logic;
+
+  signal control_i      : std_logic_vector(31 downto 0) := (others => '0');
+  signal status_i       : std_logic_vector(31 downto 0);
+  
+  signal run_counter    : unsigned(7 downto 0) := (others => '0');
+  signal error_counter  : unsigned(7 downto 0) := (others => '0');
+  signal timer          : unsigned(5 downto 0);
+  
+begin
+
+sed_clock_last <= sed_clock_q when rising_edge(CLK);
+sed_edge       <= sed_clock_q and not sed_clock_last when rising_edge(CLK);
+
+sed_clock_q      <= sed_clock when rising_edge(CLK);
+sed_done_q       <= sed_done when rising_edge(CLK);
+sed_inprogress_q <= sed_inprogress when rising_edge(CLK);
+sed_error_q      <= sed_error when rising_edge(CLK);
+
+
+---------------------------------------------------------------------------
+-- Status / Control Register for internal data bus
+---------------------------------------------------------------------------
+proc_reg : process begin
+  wait until rising_edge(CLK);
+  BUS_TX.ack     <= '0';
+  BUS_TX.nack    <= '0';
+  BUS_TX.unknown <= '0';
+  
+  if BUS_RX.write = '1' then
+    BUS_TX.ack <= '1';
+    case BUS_RX.addr(1 downto 0) is
+      when "00"   => control_i <= BUS_RX.data;
+      when others => BUS_TX.ack <= '0'; BUS_TX.unknown <= '1';
+    end case;
+  elsif BUS_RX.read = '1' then
+    BUS_TX.ack <= '1';
+    case BUS_RX.addr(1 downto 0) is
+      when "00"   => BUS_TX.data <= control_i;
+      when "01"   => BUS_TX.data <= status_i;
+      when others => BUS_TX.ack <= '0'; BUS_TX.unknown <= '1';
+    end case;
+  end if;
+end process;
+
+---------------------------------------------------------------------------
+-- SED control state machine
+---------------------------------------------------------------------------
+proc_ctrl : process begin
+  wait until rising_edge(CLK);
+  timer <= timer + 1;
+  case state is
+    when IDLE =>
+      sed_enable   <= '0';
+      sed_start    <= '0';
+      if control_i(0) = '1' then
+        state      <= INIT_1;
+        timer      <= "000001";
+      end if;
+    when INIT_1 =>
+      sed_enable   <= '1';
+      sed_start    <= '0';
+      if timer = 0 then
+        state      <= INIT_2;
+      end if;
+    when INIT_2 =>
+      sed_enable   <= '1';
+      sed_start    <= '0';
+      if timer = 0 then
+        state      <= INIT_3;
+      end if;
+    when INIT_3 =>
+      sed_enable   <= '0';
+      sed_start    <= '0';
+      if timer = 0 then
+        state      <= START_1;
+      end if;
+    when START_1 =>
+      sed_enable   <= '1';
+      sed_start    <= '0';
+      if sed_edge = '1' then
+        state      <= START_2;
+      end if;
+    when START_2 =>      
+      sed_enable   <= '1';
+      sed_start    <= '1';
+      if sed_edge = '1' and sed_inprogress_q = '1' then
+        state      <= WAITACTIVE;
+      end if;
+    when WAITACTIVE =>
+      sed_enable   <= '1';
+      sed_start    <= '0';
+      if sed_edge = '1' and sed_done_q = '0' then
+        state      <= WAITDONE;
+      end if;
+    when WAITDONE =>
+      sed_enable   <= '1';
+      sed_start    <= '0';
+      if sed_edge = '1' and sed_inprogress_q = '0' and sed_done_q = '1' then
+        state       <= INIT_1;
+        run_counter <= run_counter + 1;
+        if sed_error_q = '1' then
+          error_counter <= error_counter + 1;
+        end if;
+      end if;
+  end case;
+  
+  if control_i(0) = '0' then
+    sed_enable <= '0';
+    state      <= IDLE;
+  end if;
+  
+end process;
+
+---------------------------------------------------------------------------
+-- Status Information
+---------------------------------------------------------------------------
+state_bits <= x"8" when state = IDLE else
+              x"1" when state = INIT_1 else
+              x"2" when state = INIT_2 else
+              x"3" when state = INIT_3 else
+              x"4" when state = START_1 else
+              x"5" when state = START_2 else
+              x"6" when state = WAITACTIVE else
+              x"7" when state = WAITDONE else
+--               x"9" when state = RESULT else
+              x"F";
+
+status_i(3 downto 0) <= state_bits;
+status_i(4)          <= sed_clock_q;
+status_i(5)          <= sed_enable;
+status_i(6)          <= sed_start;
+status_i(7)          <= sed_done_q;
+status_i(8)          <= sed_inprogress_q;
+status_i(9)          <= sed_error_q;
+status_i(10)         <= sed_edge;
+status_i(15 downto 11) <= (others => '0');
+status_i(23 downto 16) <= std_logic_vector(run_counter)(7 downto 0);
+status_i(31 downto 24) <= std_logic_vector(error_counter)(7 downto 0);
+              
+ERROR_OUT <= sed_error;              
+DEBUG     <= status_i when rising_edge(CLK);
+
+---------------------------------------------------------------------------
+-- SED
+---------------------------------------------------------------------------
+THE_SED : SEDGA
+  generic map(
+      CHECKALWAYS  => "DISABLED",
+      SED_CLK_FREQ   => "38.8",
+      DEV_DENSITY  => "85KUM" 
+      )
+  port map(
+    SEDENABLE => sed_enable,
+    SEDSTART  => sed_start,
+    SEDFRCERR => '0',
+    SEDERR    => sed_error,
+    SEDDONE   => sed_done,
+    SEDINPROG => sed_inprogress,
+    SEDCLKOUT => sed_clock
+    );
+    
+    
+end architecture; 

diff --git a/dirich/config_compile_frankfurt.pl b/dirich/config_compile_frankfurt.pl
index 2cf6c3aaab37bf5da43d329cbb14c046d14ba4f8..c76472990765449a0113ff3f257219799014d9d4 100644 (file)
--- a/dirich/config_compile_frankfurt.pl
+++ b/dirich/config_compile_frankfurt.pl
@@ -1,3 +1,9 @@
+Familyname  => 'ECP5UM',
+Devicename  => 'LFE5UM-85F',
+Package     => 'CABGA381',
+Speedgrade  => '8',
+
+
 TOPNAME                      => "dirich",
 lm_license_file_for_synplify => "1702\@hadeb05.gsi.de", #"27000\@lxcad01.gsi.de";
 lm_license_file_for_par      => "1702\@hadeb05.gsi.de",

diff --git a/dirich/dirich.ldf b/dirich/dirich.ldf
index b78c54537324a91a5118ea88cada331a0f2e71ad..347867909c0af20264ef64be7eacaac7057f2e9a 100644 (file)
--- a/dirich/dirich.ldf
+++ b/dirich/dirich.ldf
@@ -2,105 +2,298 @@
 <BaliProject version="3.2" title="dirich" device="LFE5UM-85F-8BG381C" default_implementation="project">
     <Options/>
     <Implementation title="project" dir="project" description="project" synthesis="synplify" default_strategy="Strategy1">
-        <Options def_top="dirich"/>
-        <Source name="workdir/version.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="config.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trb3/base/trb3_components.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/trb_net_std.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../cores/pll_240_100/pll_240_100.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../code/clock_reset_handler.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/special/trb_net_reset_handler.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trb3/base/code/sedcheck.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/lattice/ecp5/trb_net16_fifo_arch.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16bit_dualport/lattice_ecp5_fifo_16bit_dualport.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/lattice/ecp5/trb_net_fifo_16bit_bram_dualport.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/lattice/ecp5/FIFO/fifo_36x256_oreg/fifo_36x256_oreg.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/lattice/ecp5/FIFO/fifo_18x2k_oreg/fifo_18x2k_oreg.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/lattice/ecp5/FIFO/fifo_9x2k_oreg/fifo_9x2k_oreg.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16x16_dualport/lattice_ecp5_fifo_16x16_dualport.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport/lattice_ecp5_fifo_18x16_dualport.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport_oreg/lattice_ecp5_fifo_18x16_dualport_oreg.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/special/slv_register.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/special/spi_master.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/special/spi_slim.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/special/spi_databus_memory.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/special/fpga_reboot.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trb3sc/code/trb3sc_tools.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trb3sc/code/lcd.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trb3sc/code/debuguart.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/special/uart.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/special/uart_rec.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/special/uart_trans.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/special/spi_ltc2600.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trb3sc/code/load_settings.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trb3sc/code/spi_master_generic.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trb3/base/code/input_to_trigger_logic_record.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trb3/base/code/input_statistics.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/trb_net16_regio_bus_handler.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/trb_net16_regio_bus_handler_record.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/trb_net16_regIO.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/trb_net_onewire.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/trb_net16_addresses.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/media_interfaces/sync/med_sync_define.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/trb_net16_term_buf.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/trb_net_CRC.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/trb_net_CRC8.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/basics/rom_16x8.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/basics/ram.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/basics/pulse_sync.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/basics/state_sync.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/basics/ram_16x8_dp.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/basics/ram_16x16_dp.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/basics/ram_dp.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/trb_net16_term.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/trb_net_sbuf.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/trb_net_sbuf5.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/trb_net_sbuf6.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/trb_net16_sbuf.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/trb_net_priority_encoder.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/trb_net_dummy_fifo.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/trb_net16_dummy_fifo.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/trb_net16_term_ibuf.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/trb_net_priority_arbiter.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/trb_net_pattern_gen.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/trb_net16_obuf_nodata.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/trb_net16_obuf.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/trb_net16_ibuf.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/trb_net16_api_base.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/trb_net16_iobuf.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/trb_net16_io_multiplexer.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/trb_net16_trigger.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/trb_net16_ipudata.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/trb_net16_endpoint_hades_full.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/basics/signal_sync.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/basics/ram_dp_rw.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/basics/pulse_stretch.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/special/handler_lvl1.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/special/handler_data.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/special/handler_ipu.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/special/handler_trigger_and_data.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="../../trbnet/special/bus_register_handler.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
-        <Source name="./dirich.vhd" type="VHDL" type_short="VHDL"><Options  lib="work" /></Source>
+        <Options def_top="dirich" top="dirich"/>
+        <Source name="workdir/version.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="config.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trb3/base/trb3_components.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/trb_net_std.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../cores/pll_240_100/pll_240_100.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../code/clock_reset_handler.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/special/trb_net_reset_handler.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/lattice/ecp5/trb_net16_fifo_arch.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16bit_dualport/lattice_ecp5_fifo_16bit_dualport.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/lattice/ecp5/trb_net_fifo_16bit_bram_dualport.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/lattice/ecp5/FIFO/fifo_36x256_oreg/fifo_36x256_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/lattice/ecp5/FIFO/fifo_18x2k_oreg/fifo_18x2k_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/lattice/ecp5/FIFO/fifo_9x2k_oreg/fifo_9x2k_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16x16_dualport/lattice_ecp5_fifo_16x16_dualport.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport/lattice_ecp5_fifo_18x16_dualport.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport_oreg/lattice_ecp5_fifo_18x16_dualport_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/special/slv_register.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/special/spi_master.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/special/spi_slim.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/special/spi_databus_memory.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/special/fpga_reboot.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trb3sc/code/trb3sc_tools.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trb3sc/code/lcd.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trb3sc/code/debuguart.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/special/uart.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/special/uart_rec.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/special/uart_trans.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/special/spi_ltc2600.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trb3sc/code/load_settings.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trb3sc/code/spi_master_generic.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trb3/base/code/input_to_trigger_logic_record.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trb3/base/code/input_statistics.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/trb_net16_regio_bus_handler.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/trb_net16_regio_bus_handler_record.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/trb_net16_regIO.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/trb_net_onewire.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/trb_net16_addresses.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/media_interfaces/sync/med_sync_define.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/trb_net16_term_buf.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/trb_net_CRC.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/trb_net_CRC8.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/basics/rom_16x8.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/basics/ram.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/basics/pulse_sync.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/basics/state_sync.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/basics/ram_16x8_dp.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/basics/ram_16x16_dp.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/basics/ram_dp.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/trb_net16_term.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/trb_net_sbuf.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/trb_net_sbuf5.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/trb_net_sbuf6.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/trb_net16_sbuf.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/trb_net_priority_encoder.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/trb_net_dummy_fifo.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/trb_net16_dummy_fifo.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/trb_net16_term_ibuf.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/trb_net_priority_arbiter.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/trb_net_pattern_gen.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/trb_net16_obuf_nodata.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/trb_net16_obuf.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/trb_net16_ibuf.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/trb_net16_api_base.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/trb_net16_iobuf.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/trb_net16_io_multiplexer.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/trb_net16_trigger.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/trb_net16_ipudata.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/trb_net16_endpoint_hades_full.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/basics/signal_sync.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/basics/ram_dp_rw.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/basics/pulse_stretch.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/special/handler_lvl1.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/special/handler_data.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/special/handler_ipu.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/special/handler_trigger_and_data.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="../../trbnet/special/bus_register_handler.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work"/>
+        </Source>
+        <Source name="dirich.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="work" top_module="dirich"/>
+        </Source>
+        <Source name="../code/sedcheck.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
         <Source name="workdir/dirich.lpf" type="Logic Preference" type_short="LPF">
-            <Options/>           </Source>  
-            </Implementation>
-   <Strategy name="Strategy1" file="dirich1.sty"/>
+            <Options/>
+        </Source>
+    </Implementation>
+    <Strategy name="Strategy1" file="dirich1.sty"/>
 </BaliProject>

diff --git a/dirich/dirich.lpf b/dirich/dirich.lpf
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..90bb1609e308fa8c52d31961734ec99560cc677e 100644 (file)
--- a/dirich/dirich.lpf
+++ b/dirich/dirich.lpf
@@ -0,0 +1,21 @@
+COMMERCIAL ;
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+BLOCK RD_DURING_WR_PATHS ;
+
+BLOCK PATH TO   PORT "LED*";
+BLOCK PATH TO   PORT "PROGRAMN";
+BLOCK PATH TO   PORT "TEMPSENS";
+BLOCK PATH FROM PORT "TEMPSENS";
+BLOCK PATH TO   PORT "TEST_LINE";
+
+MULTICYCLE TO CELL   "THE_CLOCK_RESET/THE_RESET_HANDLER/trb_reset_pulse*" 20 ns;
+MULTICYCLE FROM CELL "THE_CLOCK_RESET/clear_n_i" 20 ns;
+MULTICYCLE TO CELL   "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns;
+MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns;
+
+
+FREQUENCY PORT CLOCK_IN        240 MHz;
+
+SYSCONFIG MCCLK_FREQ = 38.8;
+GSR_NET NET "GSR_N"; 

diff --git a/dirich/dirich.prj b/dirich/dirich.prj
index b212e00f3a8c1a340116a5ca3fbc25e94d316ae2..64f68838c4b99cd55d4a019b6362e549dc7a8ad4 100644 (file)
--- a/dirich/dirich.prj
+++ b/dirich/dirich.prj
@@ -51,7 +51,7 @@ impl -active "workdir"
 
 ####################
 
-add_file -vhdl -lib work "../diamond/cae_library/synthesis/vhdl/ecp5um.vhd"
+add_file -vhdl -lib work "workdir/lattice-diamond/cae_library/synthesis/vhdl/ecp5um.vhd"
 
 #Packages
 add_file -vhdl -lib work "workdir/version.vhd"
@@ -65,7 +65,7 @@ add_file -vhdl -lib work "../cores/pll_240_100/pll_240_100.vhd"
 add_file -vhdl -lib work "../code/clock_reset_handler.vhd"
 add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
 add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd"
-add_file -vhdl -lib work "../../trb3/base/code/sedcheck.vhd"
+add_file -vhdl -lib work "..//code/sedcheck.vhd"
 
 
 #Fifos