add accelerated readout to hub

diff --git a/hub/config.vhd b/hub/config.vhd
index 57578ccd6f46e624637ae64ec948d4952d793646..2208b3d4fcb738f22446455d921abb7d09815fd0 100644 (file)
--- a/hub/config.vhd
+++ b/hub/config.vhd
@@ -13,7 +13,7 @@ package config is
 
 --design options: backplane or front SFP, with or without GBE
     constant USE_BACKPLANE : integer := c_NO;
-    constant INCLUDE_GBE   : integer := c_NO;
+    constant INCLUDE_GBE   : integer := c_YES;
 
     constant FPGA_TYPE               : integer  := 5;  --3: ECP3, 5: ECP5
 
@@ -34,7 +34,7 @@ package config is
     constant INCLUDE_UART           : integer  := c_YES;
     constant INCLUDE_SPI            : integer  := c_YES;
     constant INCLUDE_LCD            : integer  := c_NO;
-    constant INCLUDE_DEBUG_INTERFACE: integer  := c_YES;
+    constant INCLUDE_DEBUG_INTERFACE: integer  := c_NO;
 
     --input monitor and trigger generation logic
     constant INCLUDE_TRIGGER_LOGIC  : integer  := c_NO;

diff --git a/hub/trb3sc_hub.prj b/hub/trb3sc_hub.prj
index a0edfd3c3edca58d970da71608df71fafb766326..9aa1b1338652f2122c87b15d86e6c708ab2b779d 100644 (file)
--- a/hub/trb3sc_hub.prj
+++ b/hub/trb3sc_hub.prj
@@ -69,10 +69,6 @@ add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out200.vhd"
 add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out240.vhd"
 add_file -vhdl -lib work "../../trb3/base/cores/pll_200_4.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/clock_reset_handler.vhd"
-add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd"
-add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd"
-add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd"
-add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd"
 add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
 add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd"
 add_file -vhdl -lib work "../../trb3/base/code/sedcheck.vhd"
@@ -120,6 +116,10 @@ add_file -vhdl -lib work "../../trbnet/special/uart.vhd"
 add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd"
 add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd"
 add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd"
+add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd"
+add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd"
 
 #SlowControl files
 add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"
@@ -180,9 +180,8 @@ add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd"
 add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd"
 
 #Hub
-add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming.vhd"
-#add_file -vhdl -lib work "../../trbnet/trb_net16_hub_streaming_port.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_hub_streaming_port_sctrl_record.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming_accel.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_hub_streaming_port_sctrl_accel.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_hub_base.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_hub_logic_2.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_hub_ipu_logic.vhd"