CLK : in std_logic;
RESET : in std_logic;
DO_REBOOT : in std_logic;
+ REBOOT_ON_RESET : in std_logic := '0';
PROGRAMN : out std_logic := '1'
);
end entity;
begin
wait until rising_edge(CLK);
if RESET = '1' then
- delayed_restart_fpga <= '0';
+ delayed_restart_fpga <= REBOOT_ON_RESET;
restart_fpga_counter <= x"000";
else
delayed_restart_fpga <= '0';
PROGRAMN <= not delayed_restart_fpga;
-end architecture;
\ No newline at end of file
+end architecture;
BUS_TX : out CTRLBUS_TX;
BUS_RX : in CTRLBUS_RX;
- DO_REBOOT_IN : in std_logic;
- PROGRAMN : out std_logic;
+ DO_REBOOT_IN : in std_logic;
+ REBOOT_ON_RESET : in std_logic := '0';
+ PROGRAMN : out std_logic;
SPI_CS_OUT : out std_logic;
SPI_SCK_OUT : out std_logic;
---------------------------------------------------------------------------
-- Reboot FPGA
---------------------------------------------------------------------------
-THE_FPGA_REBOOT : fpga_reboot
+THE_FPGA_REBOOT : entity work.fpga_reboot
port map(
CLK => CLK_IN,
RESET => RESET_IN,
DO_REBOOT => DO_REBOOT_IN,
+ REBOOT_ON_RESET => REBOOT_ON_RESET,
PROGRAMN => PROGRAMN
);