Add missing file to repo

diff --git a/.gitignore b/.gitignore
new file mode 100644 (file)
index 0000000..60dab8f
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,5 @@
+workdir
+version.vhd
+*.tcl
+*.log
+*.bak

diff --git a/cts_fpga1.p2t b/cts_fpga1.p2t
index 9ce01fc1f2e54ff9014886d6d402022ace6a61a8..762eeb07b99dce2b2066aff9060fb19bf5770a73 100644 (file)
--- a/cts_fpga1.p2t
+++ b/cts_fpga1.p2t
@@ -7,7 +7,7 @@
 -t 1
 -c 1
 -e 2
--m nodelist.txt
+#-m nodelist.txt
 # -w
 # -i 6
 # -l 5

diff --git a/cts_fpga1.vhd b/cts_fpga1.vhd
index 464f16a4883f651a3892811c9902b4b2bb194b07..660db34bbbafb3a3de35e2aef3d3ae1cb9819e9a 100644 (file)
--- a/cts_fpga1.vhd
+++ b/cts_fpga1.vhd
@@ -48,7 +48,7 @@ entity cts_fpga1 is
   port(
     --Clocks
     CLK_200_IN          : in  std_logic;
-    ADO_CLKOUT          : out std_logic;
+--     ADO_CLKOUT          : out std_logic;
     --Resets
     RESET_FPGA_1        : in  std_logic;
     ADDON_RESET         : in  std_logic;

diff --git a/ddr2_13out_clkdiv.vhd b/ddr2_13out_clkdiv.vhd
new file mode 100644 (file)
index 0000000..6a1a28c
--- /dev/null
+++ b/ddr2_13out_clkdiv.vhd
@@ -0,0 +1,249 @@
+-- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
+-- Module  Version: 5.2
+--/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n ddr2_13out_clkdiv -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type iol -mode out -width 13 -reg ddr -gear 2 -cdiv -cmode 0 -e 
+
+-- Fri Feb 17 19:38:39 2012
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity ddr2_13out_clkdiv is
+    port (
+        Data: in  std_logic_vector(51 downto 0); 
+        EClk: in  std_logic; 
+        Rst: in  std_logic; 
+        SClk: out  std_logic; 
+        Q: out  std_logic_vector(12 downto 0); 
+        Update: out  std_logic_vector(12 downto 0));
+ attribute dont_touch : boolean;
+ attribute dont_touch of ddr2_13out_clkdiv : entity is true;
+end ddr2_13out_clkdiv;
+
+architecture Structure of ddr2_13out_clkdiv is
+
+    -- internal signal declarations
+    signal ERst: std_logic;
+    signal SClk_t: std_logic;
+    signal buf_Q12: std_logic;
+    signal buf_Q11: std_logic;
+    signal buf_Q10: std_logic;
+    signal buf_Q9: std_logic;
+    signal buf_Q8: std_logic;
+    signal buf_Q7: std_logic;
+    signal buf_Q6: std_logic;
+    signal buf_Q5: std_logic;
+    signal buf_Q4: std_logic;
+    signal buf_Q3: std_logic;
+    signal buf_Q2: std_logic;
+    signal buf_Q1: std_logic;
+    signal buf_Q0: std_logic;
+
+    -- local component declarations
+    component OB
+        port (I: in  std_logic; O: out  std_logic);
+    end component;
+    component ODDRX2A
+    -- synopsys translate_off
+        generic (LSRMODE : in String);
+    -- synopsys translate_on
+        port (DA0: in  std_logic; DB0: in  std_logic; DA1: in  std_logic; 
+            DB1: in  std_logic; ECLK: in  std_logic; SCLK: in  std_logic; 
+            RST: in  std_logic; Q: out  std_logic; 
+            UPDATE: out  std_logic);
+    end component;
+    component CLKDIV
+    -- synopsys translate_off
+        generic (DIV : in Integer);
+    -- synopsys translate_on
+        port (CLKI: in  std_logic; LSR: in  std_logic; 
+            CLKO: out  std_logic; ELSR: out  std_logic);
+    end component;
+    attribute LSRMODE : string; 
+    attribute DIV : string; 
+    attribute LSRMODE of ud_12 : label is "EDGE";
+    attribute LSRMODE of ud_11 : label is "EDGE";
+    attribute LSRMODE of ud_10 : label is "EDGE";
+    attribute LSRMODE of ud_9 : label is "EDGE";
+    attribute LSRMODE of ud_8 : label is "EDGE";
+    attribute LSRMODE of ud_7 : label is "EDGE";
+    attribute LSRMODE of ud_6 : label is "EDGE";
+    attribute LSRMODE of ud_5 : label is "EDGE";
+    attribute LSRMODE of ud_4 : label is "EDGE";
+    attribute LSRMODE of ud_3 : label is "EDGE";
+    attribute LSRMODE of ud_2 : label is "EDGE";
+    attribute LSRMODE of ud_1 : label is "EDGE";
+    attribute LSRMODE of ud_0 : label is "EDGE";
+    attribute DIV of ucdiv : label is "2";
+    attribute syn_keep : boolean;
+    attribute syn_noprune : boolean;
+    attribute syn_noprune of Structure : architecture is true;
+
+begin
+    -- component instantiation statements
+    ud_12: ODDRX2A
+        -- synopsys translate_off
+        generic map (LSRMODE=> "EDGE")
+        -- synopsys translate_on
+        port map (DA0=>Data(12), DB0=>Data(25), DA1=>Data(38), 
+            DB1=>Data(51), ECLK=>EClk, SCLK=>SClk_t, RST=>ERst, 
+            Q=>buf_Q12, UPDATE=>Update(12));
+
+    ud_11: ODDRX2A
+        -- synopsys translate_off
+        generic map (LSRMODE=> "EDGE")
+        -- synopsys translate_on
+        port map (DA0=>Data(11), DB0=>Data(24), DA1=>Data(37), 
+            DB1=>Data(50), ECLK=>EClk, SCLK=>SClk_t, RST=>ERst, 
+            Q=>buf_Q11, UPDATE=>Update(11));
+
+    ud_10: ODDRX2A
+        -- synopsys translate_off
+        generic map (LSRMODE=> "EDGE")
+        -- synopsys translate_on
+        port map (DA0=>Data(10), DB0=>Data(23), DA1=>Data(36), 
+            DB1=>Data(49), ECLK=>EClk, SCLK=>SClk_t, RST=>ERst, 
+            Q=>buf_Q10, UPDATE=>Update(10));
+
+    ud_9: ODDRX2A
+        -- synopsys translate_off
+        generic map (LSRMODE=> "EDGE")
+        -- synopsys translate_on
+        port map (DA0=>Data(9), DB0=>Data(22), DA1=>Data(35), 
+            DB1=>Data(48), ECLK=>EClk, SCLK=>SClk_t, RST=>ERst, 
+            Q=>buf_Q9, UPDATE=>Update(9));
+
+    ud_8: ODDRX2A
+        -- synopsys translate_off
+        generic map (LSRMODE=> "EDGE")
+        -- synopsys translate_on
+        port map (DA0=>Data(8), DB0=>Data(21), DA1=>Data(34), 
+            DB1=>Data(47), ECLK=>EClk, SCLK=>SClk_t, RST=>ERst, 
+            Q=>buf_Q8, UPDATE=>Update(8));
+
+    ud_7: ODDRX2A
+        -- synopsys translate_off
+        generic map (LSRMODE=> "EDGE")
+        -- synopsys translate_on
+        port map (DA0=>Data(7), DB0=>Data(20), DA1=>Data(33), 
+            DB1=>Data(46), ECLK=>EClk, SCLK=>SClk_t, RST=>ERst, 
+            Q=>buf_Q7, UPDATE=>Update(7));
+
+    ud_6: ODDRX2A
+        -- synopsys translate_off
+        generic map (LSRMODE=> "EDGE")
+        -- synopsys translate_on
+        port map (DA0=>Data(6), DB0=>Data(19), DA1=>Data(32), 
+            DB1=>Data(45), ECLK=>EClk, SCLK=>SClk_t, RST=>ERst, 
+            Q=>buf_Q6, UPDATE=>Update(6));
+
+    ud_5: ODDRX2A
+        -- synopsys translate_off
+        generic map (LSRMODE=> "EDGE")
+        -- synopsys translate_on
+        port map (DA0=>Data(5), DB0=>Data(18), DA1=>Data(31), 
+            DB1=>Data(44), ECLK=>EClk, SCLK=>SClk_t, RST=>ERst, 
+            Q=>buf_Q5, UPDATE=>Update(5));
+
+    ud_4: ODDRX2A
+        -- synopsys translate_off
+        generic map (LSRMODE=> "EDGE")
+        -- synopsys translate_on
+        port map (DA0=>Data(4), DB0=>Data(17), DA1=>Data(30), 
+            DB1=>Data(43), ECLK=>EClk, SCLK=>SClk_t, RST=>ERst, 
+            Q=>buf_Q4, UPDATE=>Update(4));
+
+    ud_3: ODDRX2A
+        -- synopsys translate_off
+        generic map (LSRMODE=> "EDGE")
+        -- synopsys translate_on
+        port map (DA0=>Data(3), DB0=>Data(16), DA1=>Data(29), 
+            DB1=>Data(42), ECLK=>EClk, SCLK=>SClk_t, RST=>ERst, 
+            Q=>buf_Q3, UPDATE=>Update(3));
+
+    ud_2: ODDRX2A
+        -- synopsys translate_off
+        generic map (LSRMODE=> "EDGE")
+        -- synopsys translate_on
+        port map (DA0=>Data(2), DB0=>Data(15), DA1=>Data(28), 
+            DB1=>Data(41), ECLK=>EClk, SCLK=>SClk_t, RST=>ERst, 
+            Q=>buf_Q2, UPDATE=>Update(2));
+
+    ud_1: ODDRX2A
+        -- synopsys translate_off
+        generic map (LSRMODE=> "EDGE")
+        -- synopsys translate_on
+        port map (DA0=>Data(1), DB0=>Data(14), DA1=>Data(27), 
+            DB1=>Data(40), ECLK=>EClk, SCLK=>SClk_t, RST=>ERst, 
+            Q=>buf_Q1, UPDATE=>Update(1));
+
+    ud_0: ODDRX2A
+        -- synopsys translate_off
+        generic map (LSRMODE=> "EDGE")
+        -- synopsys translate_on
+        port map (DA0=>Data(0), DB0=>Data(13), DA1=>Data(26), 
+            DB1=>Data(39), ECLK=>EClk, SCLK=>SClk_t, RST=>ERst, 
+            Q=>buf_Q0, UPDATE=>Update(0));
+
+    ucdiv: CLKDIV
+        -- synopsys translate_off
+        generic map (DIV=>  2)
+        -- synopsys translate_on
+        port map (CLKI=>EClk, LSR=>Rst, CLKO=>SClk_t, ELSR=>ERst);
+
+    buf_Q12_out_inst: OB
+        port map (I=>buf_Q12, O=>Q(12));
+
+    buf_Q11_out_inst: OB
+        port map (I=>buf_Q11, O=>Q(11));
+
+    buf_Q10_out_inst: OB
+        port map (I=>buf_Q10, O=>Q(10));
+
+    buf_Q9_out_inst: OB
+        port map (I=>buf_Q9, O=>Q(9));
+
+    buf_Q8_out_inst: OB
+        port map (I=>buf_Q8, O=>Q(8));
+
+    buf_Q7_out_inst: OB
+        port map (I=>buf_Q7, O=>Q(7));
+
+    buf_Q6_out_inst: OB
+        port map (I=>buf_Q6, O=>Q(6));
+
+    buf_Q5_out_inst: OB
+        port map (I=>buf_Q5, O=>Q(5));
+
+    buf_Q4_out_inst: OB
+        port map (I=>buf_Q4, O=>Q(4));
+
+    buf_Q3_out_inst: OB
+        port map (I=>buf_Q3, O=>Q(3));
+
+    buf_Q2_out_inst: OB
+        port map (I=>buf_Q2, O=>Q(2));
+
+    buf_Q1_out_inst: OB
+        port map (I=>buf_Q1, O=>Q(1));
+
+    buf_Q0_out_inst: OB
+        port map (I=>buf_Q0, O=>Q(0));
+
+    SClk <= SClk_t;
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of ddr2_13out_clkdiv is
+    for Structure
+        for all:OB use entity SCM.OB(V); end for;
+        for all:ODDRX2A use entity SCM.ODDRX2A(V); end for;
+        for all:CLKDIV use entity SCM.CLKDIV(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on

diff --git a/version.vhd b/version.vhd
deleted file mode 100644 (file)
index f9e4388..0000000
--- a/version.vhd
+++ /dev/null
@@ -1,13 +0,0 @@
-
---## attention, automatically generated. Don't change by hand.
-library ieee;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.std_logic_ARITH.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-use ieee.numeric_std.all;
-
-package version is
-
-    constant VERSION_NUMBER_TIME  : integer   := 1403204414;
-
-end package version;