IPU_NUMBER_IN : in std_logic_vector (15 downto 0);
IPU_INFORMATION_IN : in std_logic_vector (7 downto 0);
--start strobe
- IPU_START_READOUT_IN: in std_logic;
+ IPU_START_READOUT_IN : in std_logic;
--detector data, equipped with DHDR
IPU_DATA_OUT : out std_logic_vector (31 downto 0);
IPU_DATAREADY_OUT : out std_logic;
end_of_event_transfer_fsm_multiplexer,
dummy_wait_1_fsm_multiplexer,
dummy_wait_2_fsm_multiplexer,
- dummy_wait_3_fsm_multiplexer);
+ dummy_wait_3_fsm_multiplexer,
+ dummy_wait_4_fsm_multiplexer );
signal current_state_fsm_multiplexer, next_state_fsm_multiplexer : state_type_fsm_multiplexer;
signal debug_register_tdc_readout_i : std_logic_vector(3 downto 0);
signal reg_trigger_type : std_logic_vector(3 downto 0);
signal token_tdc_readout_i : std_logic_vector(3 downto 0);
- signal first_header : std_logic_vector(51 downto 0):=(others => '0');
+ signal first_header : std_logic_vector(51 downto 0);
+ signal reg_first_header : std_logic_vector(51 downto 0);
--signal second_header : std_logic_vector(35 downto 0):=(others => '0');
signal reg_token_in : std_logic_vector(3 downto 0);
signal data_tdc_readout_i : std_logic_vector(35 downto 0);
signal reg_debug_register_fsm_multiplexer : std_logic_vector(7 downto 0);
signal fee_data_fifo_out_i : std_logic_vector(35 downto 0);
signal header_data_fifo_out_i : std_logic_vector(51 downto 0);
- signal next_data_to_trb_net : std_logic_vector(35 downto 0);
+ signal next_data_to_trb_net : std_logic_vector(31 downto 0);
signal data_header_fifo_in_i : std_logic_vector(51 downto 0);
signal reg_debug_register_fsm_header, next_debug_register_fsm_header : std_logic_vector(7 downto 0);
signal write_header_fifo_i, next_write_header_fifo_i : std_logic;
signal reg_flag_in_header : std_logic_vector(3 downto 0);
signal push_read_fee_data_i,push_read_header_data_i : std_logic;
signal empty_flag_fee_data_fifo_i, empty_flag_header_data_fifo_i : std_logic;
+ signal reg_empty_flag_fee_data_fifo_i : std_logic;
+ signal last_empty_flag_fee_data_fifo_i : std_logic;
signal pulse_write_header_fifo_i, pulse_write_fee_data_fifo_i : std_logic;
signal counter_pulse_write_header_fifo_i, counter_pulse_write_fee_data_fifo_i : std_logic_vector(15 downto 0);
signal counter_token_back : std_logic_vector(31 downto 0);
-- signal reg_lvl1_trg_code,reg_lvl1_trg_information : std_logic_vector(7 downto 0);
-- signal reg_ipu_number : std_logic_vector (15 downto 0);
-- signal reg_ipu_information : std_logic_vector (7 downto 0);
--- signal reg_ipu_start_readout : std_logic;
- ------------------------------------------------------------------------------
+ signal reg_ipu_start_readout_in : std_logic;
+ signal push_read_fee_data_1_i : std_logic;
+------------------------------------------------------------------------------
-- COUNTERs
-------------------------------------------------------------------------------
component counter_4bit
---------------------------------------------------------------------------
component tdc_readout
port (
- CLK : in std_logic;
- RESET : in std_logic;
-
- A_ADD_IN : in std_logic_vector(8 downto 0);
- A_RESERV_IN : in std_logic; --this is 11 bit of dataword
- A_AOD_IN : in std_logic; --address or data
- -- A_ACK_IN : in std_logic; --acknowledgment
- A_DST_IN : in std_logic;
-
- TOKEN_IN : in std_logic_vector(3 downto 0);
- TOKEN_TDC_READOUT_OUT : out std_logic_vector(3 downto 0);
- FLAG_EVENT_COUNTER_IN : in std_logic_vector(3 downto 0);
- DATA_BUS_OUT : out std_logic_vector(35 downto 0);--(25 downto 0);--(23 downto 0);
- DATA_VALID_OUT : out std_logic;
- FULL_FIFO_IN : in std_logic;
- INIT_TDC_READOUT_IN : in std_logic;
- DEBUG_REGISTER_OUT : out std_logic_vector(3 downto 0));
+ CLK : in std_logic;
+ RESET : in std_logic;
+
+ A_ADD_IN : in std_logic_vector(8 downto 0);
+ A_RESERV_IN : in std_logic; --this is 11 bit of dataword
+ A_AOD_IN : in std_logic; --address or data
+ -- A_ACK_IN : in std_logic; --acknowledgment
+ A_DST_IN : in std_logic;
+
+ TOKEN_IN : in std_logic_vector(3 downto 0);
+ TOKEN_TDC_READOUT_OUT : out std_logic_vector(3 downto 0);
+ FLAG_EVENT_COUNTER_IN : in std_logic_vector(3 downto 0);
+ DATA_BUS_OUT : out std_logic_vector(35 downto 0); --(25 downto 0); --(23 downto 0);
+ DATA_VALID_OUT : out std_logic;
+ FULL_FIFO_IN : in std_logic;
+ INIT_TDC_READOUT_IN : in std_logic;
+ DEBUG_REGISTER_OUT : out std_logic_vector(3 downto 0));
end component;
--- component fifo_fall_through_2048depth_36width
--- port (
--- Data : in std_logic_vector(35 downto 0);
--- Clock : in std_logic;
--- WrEn : in std_logic;
--- RdEn : in std_logic;
--- Reset : in std_logic;
--- Q : out std_logic_vector(35 downto 0);
--- WCNT : out std_logic_vector(11 downto 0);
--- Empty : out std_logic;
--- Full : out std_logic;
--- AlmostEmpty : out std_logic;
--- AlmostFull : out std_logic);
--- end component;
-
component fifo_8192depth_36width_dual_thresh
port (
Data : in std_logic_vector(35 downto 0);
DATA_VALID_OUT => write_fee_data_fifo_i,
DATA_BUS_OUT => data_tdc_readout_i,
- INIT_TDC_READOUT_IN => INIT_TDC_READOUT_IN(0),
+ INIT_TDC_READOUT_IN => INIT_TDC_READOUT_IN(0), --init from common_stop_
+ --generator after send
+ --token
FULL_FIFO_IN => '0',
DEBUG_REGISTER_OUT => debug_register_tdc_readout_i);
-------------------------------------------------------------------------------
-- token_tdc_readout_i = x"4" or
-- token_tdc_readout_i = x"5") else '0';
---extimated 20 normal evt and 1 cal
-
--- FEE_DATA_FIFO : fifo_fall_through_2048depth_36width
--- port map (
--- Data => data_tdc_readout_i,
--- Clock => CLK,
--- WrEn => write_fee_data_fifo_i,
--- RdEn => read_fee_data_fifo,--reg_read_fee_data_fifo_i,
--- Reset => RESET,
--- Q => fee_data_fifo_out_i,
--- WCNT => word_count_fee_data_fifo,
--- Empty => empty_flag_fee_data_fifo_i,
--- Full => full_flag_fee_data_fifo_i,
--- AlmostEmpty => almost_empty_flag_fee_data_fifo_i,
--- AlmostFull => almost_full_flag_fee_data_fifo_i);
FEE_DATA_FIFO: fifo_8192depth_36width_dual_thresh
port map (
AlmostEmpty => almost_empty_flag_fee_data_fifo_i,
AlmostFull => almost_full_flag_fee_data_fifo_i);
- read_fee_data_fifo <= (reg_ipu_read and reg_read_fee_data_fifo_i) or push_read_fee_data_i;
+ read_fee_data_fifo <= (reg_ipu_read and reg_read_fee_data_fifo_i) or push_read_fee_data_i or push_read_fee_data_1_i;
HEADER_FIFO: fifo_fall_through_512depth_52width
port map (
- Data => data_header_fifo_in_i,
+ Data => reg_first_header,--data_header_fifo_in_i,
Clock => CLK,
WrEn => write_header_fifo_i,
RdEn => read_header_fifo, --reg_read_header_fifo_i,
-- I WANT THE FIRST DATAWORD TO APPEAR AT FIFO HEADER
-- OUTPUT
-------------------------------------------------------------------------------
- process (CLK, RESET, pulse_write_header_fifo_i,counter_pulse_write_header_fifo_i)
+ process (CLK, RESET, pulse_write_header_fifo_i,counter_pulse_write_header_fifo_i)
+ begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ push_read_header_data_i <= '0';
+ elsif (pulse_write_header_fifo_i = '1' and counter_pulse_write_header_fifo_i = X"0000") then
+ push_read_header_data_i <= '1';
+ else
+ push_read_header_data_i <= '0';
+ end if;
+ end if;
+ end process;
+
+-------------------------------------------------------------------------------
+-- register empty flag for fee data
+-------------------------------------------------------------------------------
+ process (CLK, RESET)
begin
if rising_edge(CLK) then
- if (RESET = '1') then
- push_read_header_data_i <= '0';
- elsif (pulse_write_header_fifo_i = '1' and counter_pulse_write_header_fifo_i = X"0000") then
- push_read_header_data_i <= '1';
- else
- push_read_header_data_i <= '0';
- end if;
+-- if (RESET = '1') then
+-- reg_empty_flag_fee_data_fifo_i <= '0';
+-- last_empty_flag_fee_data_fifo_i <= '0';
+-- else
+ last_empty_flag_fee_data_fifo_i <= empty_flag_fee_data_fifo_i;
+ reg_empty_flag_fee_data_fifo_i <= last_empty_flag_fee_data_fifo_i;
+
+-- end if;
end if;
end process;
+
process (CLK, pulse_write_header_fifo_i)
begin
if rising_edge(CLK) then
end if;
end if;
end process;
+
-------------------------------------------------------------------------------
-- I WANT THE FIRST DATAWORD TO APPEAR AT FIFO DATA
--- OUTPUT
+-- OUTPUT. this is important when I gather the first event
-------------------------------------------------------------------------------
- process (CLK, RESET, pulse_write_fee_data_fifo_i)
+ process (CLK, RESET, pulse_write_fee_data_fifo_i, empty_flag_fee_data_fifo_i)
begin
if rising_edge(CLK) then
if (RESET = '1') then
push_read_fee_data_i <= '0';
- elsif (pulse_write_fee_data_fifo_i = '1' and counter_pulse_write_fee_data_fifo_i = X"0000") then
+ elsif (pulse_write_fee_data_fifo_i = '1' and counter_pulse_write_fee_data_fifo_i = X"0000") then
push_read_fee_data_i <= '1';
else
push_read_fee_data_i <= '0';
end if;
end process;
-
-
-------------------------------------------------------------------------------
-- INPUT CONNECTIONS
-------------------------------------------------------------------------------
LVL1_TRG_RELEASE_OUT <= reg_lvl1_busy_i;
IPU_DATA_OUT <= next_data_to_trb_net(31 downto 0);
- IPU_DATAREADY_OUT <= reg_ipu_data_ready;
+ IPU_DATAREADY_OUT <= next_ipu_data_ready;--reg_ipu_data_ready;
IPU_READOUT_FINISHED_OUT <= reg_ipu_finished;
- IPU_LENGTH_OUT <= first_header(51 downto 36);
+ IPU_LENGTH_OUT <= reg_first_header(51 downto 36);
IPU_ERROR_PATTERN_OUT <= x"AAAAAAAA";
--to connect
--reg_debug_register_fsm_header
end if;
end process;
---say if token from first event is back
--counter number of token back
process (CLK, RESET,reg_token_in)
begin
next_write_header_fifo_i <= '0';
next_debug_register_fsm_header <= (others => '0');
next_lvl1_busy_i <= '0';
- data_header_fifo_in_i <= first_header;
+ data_header_fifo_in_i <= reg_first_header;
+
case current_state is
when idle_state =>
next_debug_register_fsm_header <= x"00";
next_write_header_fifo_i <= '0';
- data_header_fifo_in_i <= first_header;
+ data_header_fifo_in_i <= reg_first_header;
next_lvl1_busy_i <= '0';
if (INIT_TDC_READOUT_IN(0) = '1') then
next_state <= wait_for_token;
when wait_for_token =>
next_debug_register_fsm_header <= x"02";
next_write_header_fifo_i <= '0';
- data_header_fifo_in_i <= first_header;
+ data_header_fifo_in_i <= reg_first_header;
next_lvl1_busy_i <= '1';
if (reg_token_in(0) = '1' and almost_empty_flag_fee_data_fifo_i = '0') then
next_state <= send_second_header_state;
when send_second_header_state =>
next_debug_register_fsm_header <= x"03";
next_write_header_fifo_i <= '1'; --write in header fifo
- data_header_fifo_in_i <= first_header;
+ data_header_fifo_in_i <= reg_first_header;
next_lvl1_busy_i <= '1';
next_state <= idle_state;
when busy_header_state =>
next_debug_register_fsm_header <= x"04";
next_write_header_fifo_i <= '0';
- data_header_fifo_in_i <= first_header;
+ data_header_fifo_in_i <= reg_first_header;
next_lvl1_busy_i <= '1';
if (almost_empty_flag_fee_data_fifo_i = '0') then
next_state <= send_second_header_state;
when others =>
next_debug_register_fsm_header <= x"00";
next_write_header_fifo_i <= '0';
- data_header_fifo_in_i <= first_header;
+ data_header_fifo_in_i <= reg_first_header;
next_lvl1_busy_i <= '0';
next_state <= idle_state;
end case;
if (rising_edge(CLK)) then
if RESET = '1' then
current_state_fsm_multiplexer <= idle_state_fsm_multiplexer;
- next_debug_register_fsm_multiplexer <= (others => '0');
+ reg_debug_register_fsm_multiplexer <= (others => '0');
--next_data_to_trb_net <= (others => '0');
reg_read_fee_data_fifo_i <= '0';
reg_read_header_fifo_i <= '0';
reg_lvl1_error_pattern <= (others => '0');
reg_lvl1_trg_release <= '0';
reg_ipu_data <= (others => '0');
- reg_ipu_data_ready <= '0';
+ -- reg_ipu_data_ready <= '0';
reg_ipu_finished <= '0';
-- reg_ipu_length <= (others => '0');
else
reg_lvl1_error_pattern <= next_lvl1_error_pattern;
reg_lvl1_trg_release <= next_lvl1_trg_release;
reg_ipu_data <= next_ipu_data;
- reg_ipu_data_ready <= next_ipu_data_ready;
+ --reg_ipu_data_ready <= next_ipu_data_ready;
reg_ipu_finished <= next_ipu_finished;
-- reg_ipu_length <= next_ipu_length;
end if;
how_many_complete_event_in_fifo_counter,
counter_word_read_from_trbnet, INIT_TDC_READOUT_IN,
word_count_header_fifo, fee_data_fifo_out_i, reg_ipu_read,
- empty_flag_fee_data_fifo_i,reg_flag_in_header,read_header_fifo,
- pulse_ipu_start_readout,counter_token_back)
+ reg_empty_flag_fee_data_fifo_i,reg_flag_in_header,read_header_fifo,
+ pulse_ipu_start_readout,counter_token_back, reg_ipu_start_readout_in,
+ header_data_fifo_out_i )
begin
next_ipu_data_ready <= '0';
next_ipu_finished <= '0';
-- next_ipu_length <= (others => '0');
-
clear_counter_word_read_from_trbnet <= '0';
-
--- push_read_fee_data_i <= '0';
+ push_read_fee_data_1_i <= '0';
+-- push_read_fee_data_i <= '0';
-- push_read_header_data_i <= '0';
case current_state_fsm_multiplexer is
next_read_fee_data_fifo_i <= '0';
next_read_header_fifo_i <= '0';
next_ipu_data_ready <= '0';
- next_data_to_trb_net <= header_data_fifo_out_i(35 downto 0);
+ next_data_to_trb_net <= header_data_fifo_out_i(31 downto 0);
--start readout if IPU requests comes
--if (INIT_TDC_READOUT_IN(0) = '1') then --TRIGGER FROM TRB NET
if (pulse_ipu_start_readout = '1') then
next_read_fee_data_fifo_i <= '0';
next_read_header_fifo_i <= '0';
next_ipu_data_ready <= '0';
- next_data_to_trb_net <= header_data_fifo_out_i(35 downto 0);
+ next_data_to_trb_net <= header_data_fifo_out_i(31 downto 0);
--here I wait only when the first token from the first event is back
if (conv_integer(counter_token_back) >= 1) then
- next_state_fsm_multiplexer <= send_first_and_second_header_state_fsm_multiplexer;
+ -- push_read_header_data_i <= '1';
+ next_state_fsm_multiplexer <= dummy_wait_4_fsm_multiplexer;
else
next_state_fsm_multiplexer <= wait_for_complete_event_fsm_multiplexer;
end if;
+
+ when dummy_wait_4_fsm_multiplexer =>
+ next_debug_register_fsm_multiplexer <= x"02";
+ next_read_fee_data_fifo_i <= '0';
+ next_read_header_fifo_i <= '0';
+ next_ipu_data_ready <= '0';
+ next_data_to_trb_net <= header_data_fifo_out_i(31 downto 0);
+ next_state_fsm_multiplexer <= send_first_and_second_header_state_fsm_multiplexer;
-------------------------------------------------------------------------------
-- FIRST HEADER and SECOND : Connect header_fifo to trbnet.
-- The first and second headers can be sended.
-- to the data fifo
-------------------------------------------------------------------------------
when send_first_and_second_header_state_fsm_multiplexer =>
- next_debug_register_fsm_multiplexer <= x"01";
+ next_debug_register_fsm_multiplexer <= x"03";
next_read_fee_data_fifo_i <= '0';
next_read_header_fifo_i <= '1';
next_ipu_data_ready <= '1'; --trbnet can read
- next_data_to_trb_net <= header_data_fifo_out_i(35 downto 0); --header_fifo
+ next_data_to_trb_net <= header_data_fifo_out_i(31 downto 0); --header_fifo
if (read_header_fifo = '1') then --this read correspond to the header
--read from trbnet
- next_ipu_data_ready <= '0';
+ -- next_ipu_data_ready <= '0';
+ push_read_fee_data_1_i <= '1';
next_state_fsm_multiplexer <= dummy_wait_1_fsm_multiplexer;
else
next_state_fsm_multiplexer <= send_first_and_second_header_state_fsm_multiplexer;
end if;
+--here register header flag
when dummy_wait_1_fsm_multiplexer =>
- next_debug_register_fsm_multiplexer <= x"01";
+ next_debug_register_fsm_multiplexer <= x"04";
next_read_fee_data_fifo_i <= '0';
next_read_header_fifo_i <= '0';
next_ipu_data_ready <= '0'; --trbnet cannot read
- next_data_to_trb_net <= fee_data_fifo_out_i;--header_data_fifo_out_i; --header_fifo
+ next_data_to_trb_net <= fee_data_fifo_out_i(31 downto 0);
next_state_fsm_multiplexer <= send_data_state_fsm_multiplexer;
-
--- when dummy_wait_3_fsm_multiplexer =>
--- next_debug_register_fsm_multiplexer <= x"01";
--- next_read_fee_data_fifo_i <= '0';
--- next_read_header_fifo_i <= '0';
--- next_ipu_data_ready <= '0'; --trbnet can read
--- next_data_to_trb_net <= header_data_fifo_out_i;
--- next_state_fsm_multiplexer <= send_data_state_fsm_multiplexer;
+ -- next_state_fsm_multiplexer <= dummy_wait_3_fsm_multiplexer;
+
+-- when dummy_wait_3_fsm_multiplexer =>
+-- next_debug_register_fsm_multiplexer <= x"01";
+-- next_read_fee_data_fifo_i <= '0';
+-- next_read_header_fifo_i <= '0';
+-- next_ipu_data_ready <= '0';
+-- next_data_to_trb_net <= fee_data_fifo_out_i;
+-- next_state_fsm_multiplexer <= send_data_state_fsm_multiplexer;
-------------------------------------------------------------------------------
-- Connect fee_data_fifo to trbnet.
-- I leave connected till the flag change to next event
-------------------------------------------------------------------------------
when send_data_state_fsm_multiplexer =>
- next_debug_register_fsm_multiplexer <= x"02";
+ next_debug_register_fsm_multiplexer <= x"05";
next_read_fee_data_fifo_i <= '1';
next_read_header_fifo_i <= '0';
next_ipu_data_ready <= '1'; --trbnet can read
- next_data_to_trb_net <= fee_data_fifo_out_i; --data_fifo
+ next_data_to_trb_net <= fee_data_fifo_out_i(31 downto 0); --data_fifo
--chenge state if event you read from the fifo is different from the
--event you are sending or if the fifo does not contain anymore data.
- if ( (fee_data_fifo_out_i(35 downto 32) /= reg_flag_in_header) or
- (empty_flag_fee_data_fifo_i = '1') ) then
+ if ( (fee_data_fifo_out_i(35 downto 32) /= reg_flag_in_header ) or
+ (reg_empty_flag_fee_data_fifo_i = '1') ) then
next_ipu_data_ready <= '0';
+ next_read_fee_data_fifo_i <= '0';
next_state_fsm_multiplexer <= dummy_wait_2_fsm_multiplexer;
else
next_state_fsm_multiplexer <= send_data_state_fsm_multiplexer;
end if;
when dummy_wait_2_fsm_multiplexer =>
- next_debug_register_fsm_multiplexer <= x"02";
+ next_debug_register_fsm_multiplexer <= x"06";
next_read_fee_data_fifo_i <= '0';
next_read_header_fifo_i <= '0';
next_ipu_data_ready <= '0';
- next_data_to_trb_net <= fee_data_fifo_out_i; --data_fifo
+ next_data_to_trb_net <= fee_data_fifo_out_i(31 downto 0); --data_fifo
+ next_ipu_finished <= '1'; --transmission terminated
next_state_fsm_multiplexer <= end_of_event_transfer_fsm_multiplexer;
-
+
when end_of_event_transfer_fsm_multiplexer =>
- next_debug_register_fsm_multiplexer <= x"03";
- next_read_fee_data_fifo_i <= '0';
- next_read_header_fifo_i <= '0';
- next_ipu_data_ready <= '0';
- next_data_to_trb_net <= fee_data_fifo_out_i;
- next_ipu_finished <= '1'; --transmission terminated
+ next_debug_register_fsm_multiplexer <= x"07";
+ next_read_fee_data_fifo_i <= '0';
+ next_read_header_fifo_i <= '0';
+ next_ipu_data_ready <= '0';
+ next_data_to_trb_net <= fee_data_fifo_out_i(31 downto 0);
+ next_ipu_finished <= '1'; --transmission terminated
clear_counter_word_read_from_trbnet <= '1';
- next_state_fsm_multiplexer <= idle_state_fsm_multiplexer;
+ --push_read_fee_data_1_i <= '1';
+ if (reg_ipu_start_readout_in = '0') then
+ next_state_fsm_multiplexer <= idle_state_fsm_multiplexer;
+ else
+ next_state_fsm_multiplexer <= end_of_event_transfer_fsm_multiplexer;
+ end if;
when others =>
- next_debug_register_fsm_multiplexer <= x"00";
- next_data_to_trb_net <= header_data_fifo_out_i(35 downto 0);
+ next_debug_register_fsm_multiplexer <= x"08";
+ next_data_to_trb_net <= header_data_fifo_out_i(31 downto 0);
next_state_fsm_multiplexer <= idle_state_fsm_multiplexer;
end case;
end process;
-
-------------------------------------------------------------------------------
-- EVENT FLAG GENERATOR:
-- For each event I generate a flag (4 bits), which will be used to distinguish
-- the events. The flag marks the dataword and the header.
-------------------------------------------------------------------------------
- process (CLK, RESET)
+ process (CLK, RESET, pulse_init_tdc_readout)
begin
if (rising_edge(CLK)) then
if RESET = '1' then
flag_event_counter <= (others => '0');
- elsif (pulse_reg_lvl1_trg_received = '1') then
+ --WRONG!!!!!!!!!!!!!
+ --elsif (pulse_reg_lvl1_trg_received = '1') then
+ elsif (pulse_init_tdc_readout = '1') then
flag_event_counter <= flag_event_counter + 1;
else
flag_event_counter <= flag_event_counter;
-------------------------------------------------------------------------------
-- Make headers 36 bit
-------------------------------------------------------------------------------
-first_header <= words_in_event & --(16 downto 0)
+first_header <= words_in_event & --(15 downto 0)
flag_event_counter & --(3 downto 0)
"0000" & --(3 downto 0)
reg_lvl1_trg_type & --(3 downto 0)
reg_lvl1_trg_information & --(7 downto 0)
reg_lvl1_trg_number; --(15 downto 0)
-
+ process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ reg_first_header <= (others => '0');
+ else
+ reg_first_header <= first_header;
+ end if;
+ end if;
+ end process;
+
--second_header <= flag_event_counter & x"babe" & words_in_event;
--DEBUG_REGISTER_0 <= received_token_number & sended_token_number;
-
+DEBUG_REGISTER_0 <= x"0" & reg_debug_register_fsm_multiplexer(3 downto 0);
--DEBUG_REGISTER_1 <= reg_debug_register_i;--debug tdc_readout_and_trb_interface
--DEBUG_REGISTER_2 <= "0000" & debug_register_tdc_readout_i;
reg_ipu_number <= (others => '0');
reg_ipu_information <= (others => '0');
--start strobe
- --reg_ipu_start_readout <= '0';
+ reg_ipu_start_readout_in <= '0';
-- reg_ipu_read <= '0';
else
--reg_ipu_read <= IPU_READ_IN;
reg_ipu_number <= IPU_NUMBER_IN;
reg_ipu_information <= IPU_INFORMATION_IN;
--start strobe
- -- reg_ipu_start_readout <= IPU_START_READOUT_IN;
+ reg_ipu_start_readout_in <= IPU_START_READOUT_IN;
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- READ and REGISTER event number
-----------------------------------------------------------------------------
-process (CLK, RESET, current_state_fsm_multiplexer)
+process (CLK, RESET, current_state_fsm_multiplexer,header_data_fifo_out_i)
begin
if (rising_edge(CLK)) then
if (RESET = '1') then
reg_flag_in_header <= (others => '0');
--- elsif (header_data_fifo_out_i(31 downto 16) = x"babe") then
- elsif (current_state_fsm_multiplexer = send_first_and_second_header_state_fsm_multiplexer) then
+ elsif (current_state_fsm_multiplexer = send_first_and_second_header_state_fsm_multiplexer) then
reg_flag_in_header <= header_data_fifo_out_i(35 downto 32);
else
reg_flag_in_header <= reg_flag_in_header;
end if;
end process;
+
-------------------------------------------------------------------------------
-- AVERAGE NUMBER OF DATAWORDS PER EVENT ON THIS BUS.
-------------------------------------------------------------------------------
--- simulated! it is ok and tested in a different design
---
end behavioral;
jspc29 / mdcoep.git / commitdiff