--- /dev/null
+[size] 1272 937
+[pos] -1 -538
+*-25.902828 193000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+@22
+#apl_data_out[47:0] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[47] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[46] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[45] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[44] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[43] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[42] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[41] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[40] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[39] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[38] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[37] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[36] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[35] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[34] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[33] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[32] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[31] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[30] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[29] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[28] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[27] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[26] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[25] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[24] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[23] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[22] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[21] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[20] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[19] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[18] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[17] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[16] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[15] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[14] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[13] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[12] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[11] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[10] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[9] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[8] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[7] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[6] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[5] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[4] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[3] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[2] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[1] trb_net_dummy_apl_api_chain_testbench.APL1.apl_data_out[0]
+@28
+trb_net_dummy_apl_api_chain_testbench.APL1.apl_write_out
+trb_net_dummy_apl_api_chain_testbench.APL1.apl_send_out
+@200
+-
+@28
+trb_net_dummy_apl_api_chain_testbench.API1.int_init_dataready_out
+@22
+trb_net_dummy_apl_api_chain_testbench.API1.int_init_read_in
+@23
+#int_init_data_out[50:0] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[50] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[49] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[48] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[47] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[46] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[45] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[44] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[43] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[42] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[41] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[40] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[39] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[38] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[37] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[36] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[35] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[34] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[33] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[32] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[31] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[30] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[29] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[28] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[27] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[26] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[25] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[24] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[23] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[22] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[21] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[20] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[19] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[18] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[17] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[16] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[15] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[14] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[13] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[12] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[11] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[10] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[9] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[8] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[7] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[6] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[5] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[4] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[3] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[2] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[1] trb_net_dummy_apl_api_chain_testbench.API1.int_init_data_out[0]
--- /dev/null
+vcd dumpfile vcdfile.vcd
+vcd dumpvars -m /APL1/
+vcd dumpvars -m /API1/
+vcd dumpvars -m /API2/
+vcd dumpvars -m /APL2/
+run 1000 ns
+quit
\ No newline at end of file
--- /dev/null
+vcd dumpfile vcdfile.vcd
+vcd dumpvars -m /APL1/
+vcd dumpvars -m /API1/ACTIVE_API/
+vcd dumpvars -m /API1/ACTIVE_API/FIFO_TO_INT/
+vcd dumpvars -m /API1/IOBUF/
+vcd dumpvars -m /API1/IOBUF/INITOBUF/
+vcd dumpvars -m /API1/IOBUF/REPLYIBUF/
+vcd dumpvars -m /API2/IOBUF/INITIBUF/
+run 1000 ns
+quit
\ No newline at end of file
--- /dev/null
+[size] 1272 937
+[pos] -1 -1
+*-25.799541 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+@22
+#apl_data_out[47:0] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[47] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[46] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[45] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[44] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[43] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[42] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[41] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[40] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[39] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[38] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[37] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[36] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[35] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[34] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[33] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[32] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[31] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[30] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[29] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[28] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[27] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[26] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[25] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[24] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[23] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[22] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[21] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[20] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[19] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[18] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[17] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[16] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[15] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[14] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[13] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[12] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[11] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[10] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[9] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[8] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[7] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[6] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[5] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[4] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[3] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[2] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[1] trb_net_dummy_apl_apibuf_testbench.APL1.apl_data_out[0]
+@28
+trb_net_dummy_apl_apibuf_testbench.APL1.apl_write_out
+trb_net_dummy_apl_apibuf_testbench.APL1.apl_send_out
+@200
+-
+@28
+trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_dataready_out
+trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_read_in
+@22
+#int_init_data_out[50:0] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[50] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[49] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[48] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[47] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[46] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[45] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[44] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[43] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[42] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[41] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[40] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[39] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[38] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[37] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[36] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[35] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[34] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[33] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[32] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[31] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[30] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[29] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[28] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[27] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[26] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[25] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[24] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[23] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[22] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[21] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[20] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[19] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[18] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[17] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[16] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[15] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[14] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[13] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[12] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[11] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[10] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[9] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[8] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[7] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[6] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[5] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[4] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[3] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[2] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[1] trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.int_init_data_out[0]
+@28
+trb_net_dummy_apl_apibuf_testbench.API1.ACTIVE_API.fifo_to_int_read
+@200
+-
+@28
+trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_dataready_out
+@22
+#med_data_out[50:0] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[50] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[49] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[48] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[47] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[46] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[45] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[44] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[43] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[42] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[41] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[40] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[39] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[38] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[37] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[36] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[35] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[34] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[33] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[32] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[31] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[30] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[29] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[28] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[27] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[26] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[25] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[24] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[23] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[22] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[21] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[20] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[19] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[18] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[17] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[16] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[15] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[14] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[13] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[12] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[11] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[10] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[9] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[8] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[7] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[6] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[5] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[4] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[3] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[2] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[1] trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_data_out[0]
+@28
+trb_net_dummy_apl_apibuf_testbench.API1.IOBUF.INITOBUF.med_read_in
+@200
+-
+@22
+#stat_locked[15:0] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_locked[15] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_locked[14] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_locked[13] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_locked[12] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_locked[11] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_locked[10] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_locked[9] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_locked[8] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_locked[7] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_locked[6] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_locked[5] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_locked[4] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_locked[3] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_locked[2] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_locked[1] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.stat_locked[0]
+@28
+trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_empty
+trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_write
+trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_read
+trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_read_in
+@22
+#fifo_data_out[50:0] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[50] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[49] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[48] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[47] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[46] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[45] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[44] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[43] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[42] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[41] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[40] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[39] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[38] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[37] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[36] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[35] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[34] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[33] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[32] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[31] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[30] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[29] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[28] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[27] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[26] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[25] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[24] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[23] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[22] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[21] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[20] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[19] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[18] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[17] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[16] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[15] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[14] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[13] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[12] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[11] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[10] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[9] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[8] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[7] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[6] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[5] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[4] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[3] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[2] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[1] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.fifo_data_out[0]
+#int_data_out[50:0] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[50] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[49] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[48] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[47] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[46] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[45] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[44] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[43] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[42] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[41] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[40] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[39] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[38] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[37] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[36] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[35] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[34] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[33] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[32] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[31] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[30] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[29] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[28] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[27] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[26] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[25] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[24] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[23] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[22] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[21] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[20] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[19] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[18] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[17] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[16] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[15] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[14] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[13] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[12] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[11] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[10] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[9] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[8] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[7] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[6] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[5] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[4] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[3] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[2] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[1] trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.int_data_out[0]
+@28
+trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.reg_int_dataready_out
+trb_net_dummy_apl_apibuf_testbench.API2.IOBUF.INITIBUF.reg_eob_out
APL1: trb_net_dummy_apl
generic map (
--- TARGET_ADDRESS => x"0002",
- TARGET_ADDRESS => x"000f",
+ TARGET_ADDRESS => x"0002",
+-- TARGET_ADDRESS => x"000f",
PREFILL_LENGTH => 0,
TRANSFER_LENGTH => 2)
port map (
--- /dev/null
+library ieee;
+
+use ieee.std_logic_1164.all;
+USE ieee.std_logic_signed.ALL;
+USE ieee.std_logic_arith.ALL;
+
+USE std.textio.ALL;
+USE ieee.std_logic_textio.ALL;
+
+entity trb_net_dummy_apl_apibuf_testbench is
+
+end trb_net_dummy_apl_apibuf_testbench;
+
+architecture trb_net_dummy_apl_apibuf_testbench_arch of trb_net_dummy_apl_apibuf_testbench is
+
+ signal clk : std_logic := '0';
+ signal reset : std_logic := '1';
+
+component trb_net_active_apibuf is
+
+ generic (INIT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), if
+ -- the initibuf
+ REPLY_DEPTH : integer := 3; -- or the replyibuf
+ FIFO_TO_INT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1),
+ -- for the direction to
+ -- internal world
+ FIFO_TO_APL_DEPTH : integer := 3; -- direction to application
+ FIFO_TERM_BUFFER_DEPTH : integer := 0 -- fifo for auto-answering of
+ -- the master path, if set to 0
+ -- no buffer is used at all
+ );
+
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- Media direction port
+ MED_INIT_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out
+ --by the media (via the TrbNetIOMultiplexer)
+ MED_INIT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
+ MED_INIT_READ_IN: in STD_LOGIC; -- Media is reading
+ MED_INIT_ERROR_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Status bits
+
+ MED_INIT_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media
+ -- (the IOBUF MUST read)
+ MED_INIT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
+ MED_INIT_READ_OUT: out STD_LOGIC; -- buffer reads a word from media
+ MED_INIT_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits
+
+ MED_REPLY_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out
+ --by the media (via the TrbNetIOMultiplexer)
+ MED_REPLY_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
+ MED_REPLY_READ_IN: in STD_LOGIC; -- Media is reading
+ MED_REPLY_ERROR_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Status bits
+
+ MED_REPLY_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media
+ -- (the IOBUF MUST read)
+ MED_REPLY_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
+ MED_REPLY_READ_OUT: out STD_LOGIC; -- buffer reads a word from media
+ MED_REPLY_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits
+
+ -- APL Transmitter port
+ APL_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network"
+ APL_WRITE_IN: in STD_LOGIC; -- Data word is valid and should be transmitted
+ APL_FIFO_FULL_OUT: out STD_LOGIC; -- Stop transfer, the fifo is full
+ APL_SHORT_TRANSFER_IN: in STD_LOGIC; --
+ APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_SEND_IN: in STD_LOGIC; -- Release sending of the data
+ APL_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of
+ -- the target (only for active APIs)
+
+ -- Receiver port
+ APL_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application"
+ APL_TYP_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
+ APL_DATAREADY_OUT: out STD_LOGIC; -- Data word is valid and might be read out
+ APL_READ_IN: in STD_LOGIC; -- Read data word
+
+ -- APL Control port
+ APL_RUN_OUT: out STD_LOGIC; -- Data transfer is running
+ APL_MY_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- My own address (temporary solution!!!)
+ APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0);
+
+ -- Status and control port => just coming from the iobuf for debugging
+ STAT_GEN: out STD_LOGIC_VECTOR (31 downto 0); -- General Status
+ STAT_LOCKED: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control
+ STAT_INIT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control
+ STAT_REPLY_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- General Status
+ CTRL_GEN: in STD_LOGIC_VECTOR (31 downto 0);
+ CTRL_LOCKED: in STD_LOGIC_VECTOR (31 downto 0);
+ STAT_CTRL_INIT_BUFFER: in STD_LOGIC_VECTOR (31 downto 0);
+ STAT_CTRL_REPLY_BUFFER: in STD_LOGIC_VECTOR (31 downto 0)
+ );
+END component;
+
+
+component trb_net_dummy_apl
+ generic (TARGET_ADDRESS : STD_LOGIC_VECTOR (15 downto 0) := x"ffff";
+ PREFILL_LENGTH : integer := 3;
+ TRANSFER_LENGTH : integer := 6); -- length of dummy data
+
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ -- APL Transmitter port
+ APL_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network"
+ APL_WRITE_OUT: out STD_LOGIC; -- Data word is valid and should be transmitted
+ APL_FIFO_FULL_IN: in STD_LOGIC; -- Stop transfer, the fifo is full
+ APL_SHORT_TRANSFER_OUT: out STD_LOGIC; --
+ APL_DTYPE_OUT: out STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_ERROR_PATTERN_OUT: out STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_SEND_OUT: out STD_LOGIC; -- Release sending of the data
+ APL_TARGET_ADDRESS_OUT: out STD_LOGIC_VECTOR (15 downto 0); -- Address of
+ -- the target (only for active APIs)
+
+ -- Receiver port
+ APL_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application"
+ APL_TYP_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
+ APL_DATAREADY_IN: in STD_LOGIC; -- Data word is valid and might be read out
+ APL_READ_OUT: out STD_LOGIC; -- Read data word
+
+ -- APL Control port
+ APL_RUN_IN: in STD_LOGIC; -- Data transfer is running
+ APL_SEQNR_IN: in STD_LOGIC_VECTOR (7 downto 0)
+ );
+END component;
+
+signal apl_data_out_apl1: STD_LOGIC_VECTOR (47 downto 0);
+signal apl_write_apl1: STD_LOGIC;
+signal apl_fifo_full_apl1: STD_LOGIC;
+signal apl_short_transfer_apl1: STD_LOGIC;
+signal apl_dtype_apl1: STD_LOGIC_VECTOR (3 downto 0);
+signal apl_error_pattern_apl1: STD_LOGIC_VECTOR (31 downto 0);
+signal apl_send_apl1: STD_LOGIC;
+signal apl_target_adress_apl1: STD_LOGIC_VECTOR (15 downto 0);
+signal apl_data_in_apl1: STD_LOGIC_VECTOR (47 downto 0);
+signal apl_typ_apl1: STD_LOGIC_VECTOR (2 downto 0);
+signal apl_dataready_apl1: STD_LOGIC;
+signal apl_read_apl1: STD_LOGIC;
+signal apl_run_apl1: STD_LOGIC;
+signal apl_seqnr_apl1: STD_LOGIC_VECTOR (7 downto 0);
+
+signal apl_data_out_apl2: STD_LOGIC_VECTOR (47 downto 0);
+signal apl_write_apl2: STD_LOGIC;
+signal apl_fifo_full_apl2: STD_LOGIC;
+signal apl_short_transfer_apl2: STD_LOGIC;
+signal apl_dtype_apl2: STD_LOGIC_VECTOR (3 downto 0);
+signal apl_error_pattern_apl2: STD_LOGIC_VECTOR (31 downto 0);
+signal apl_send_apl2: STD_LOGIC;
+signal apl_target_adress_apl2: STD_LOGIC_VECTOR (15 downto 0);
+signal apl_data_in_apl2: STD_LOGIC_VECTOR (47 downto 0);
+signal apl_typ_apl2: STD_LOGIC_VECTOR (2 downto 0);
+signal apl_dataready_apl2: STD_LOGIC;
+signal apl_read_apl2: STD_LOGIC;
+signal apl_run_apl2: STD_LOGIC;
+signal apl_seqnr_apl2: STD_LOGIC_VECTOR (7 downto 0);
+
+signal MED_INIT_DATAREADY_1_to_2: STD_LOGIC;
+signal MED_INIT_DATA_1_to_2: STD_LOGIC_VECTOR (50 downto 0);
+signal MED_INIT_READ_1_to_2: STD_LOGIC;
+signal MED_INIT_DATAREADY_2_to_1: STD_LOGIC;
+signal MED_INIT_DATA_2_to_1: STD_LOGIC_VECTOR (50 downto 0);
+signal MED_INIT_READ_2_to_1: STD_LOGIC;
+signal MED_REPLY_DATAREADY_1_to_2: STD_LOGIC;
+signal MED_REPLY_DATA_1_to_2: STD_LOGIC_VECTOR (50 downto 0);
+signal MED_REPLY_READ_1_to_2: STD_LOGIC;
+signal MED_REPLY_DATAREADY_2_to_1: STD_LOGIC;
+signal MED_REPLY_DATA_2_to_1: STD_LOGIC_VECTOR (50 downto 0);
+signal MED_REPLY_READ_2_to_1: STD_LOGIC;
+
+
+begin
+
+
+ clk <= not clk after 10ns;
+
+
+
+ DO_RESET : process
+ begin
+ reset <= '1';
+ wait for 30ns;
+ reset <= '0';
+ wait;
+ end process DO_RESET;
+
+-------------------------------------------------------------------------------
+-- the 2 APLs
+-------------------------------------------------------------------------------
+
+APL1: trb_net_dummy_apl
+ generic map (
+ TARGET_ADDRESS => x"0002",
+-- TARGET_ADDRESS => x"000f",
+ PREFILL_LENGTH => 0,
+ TRANSFER_LENGTH => 2)
+ port map (
+ CLK => clk,
+ RESET => reset,
+ CLK_EN => '1',
+
+ -- APL Transmitter port
+ APL_DATA_OUT => apl_data_out_apl1,
+ APL_WRITE_OUT => apl_write_apl1,
+ APL_FIFO_FULL_IN => apl_fifo_full_apl1,
+ APL_SHORT_TRANSFER_OUT => apl_short_transfer_apl1,
+ APL_DTYPE_OUT => apl_dtype_apl1,
+ APL_ERROR_PATTERN_OUT => apl_error_pattern_apl1,
+ APL_SEND_OUT => apl_send_apl1,
+ APL_TARGET_ADDRESS_OUT => apl_target_adress_apl1,
+
+ -- Receiver port
+ APL_DATA_IN => apl_data_in_apl1,
+ APL_TYP_IN => apl_typ_apl1,
+ APL_DATAREADY_IN => apl_dataready_apl1,
+ APL_READ_OUT => apl_read_apl1,
+
+ -- APL Control port
+ APL_RUN_IN => apl_run_apl1,
+ APL_SEQNR_IN => apl_seqnr_apl1
+ );
+
+APL2: trb_net_dummy_apl
+ generic map (
+ TARGET_ADDRESS => x"0001",
+ PREFILL_LENGTH => 0,
+ TRANSFER_LENGTH => 2)
+ port map (
+ CLK => clk,
+ RESET => reset,
+ CLK_EN => '1',
+
+ -- APL Transmitter port
+ APL_DATA_OUT => apl_data_out_apl2,
+ APL_WRITE_OUT => apl_write_apl2,
+ APL_FIFO_FULL_IN => apl_fifo_full_apl2,
+ APL_SHORT_TRANSFER_OUT => apl_short_transfer_apl2,
+ APL_DTYPE_OUT => apl_dtype_apl2,
+ APL_ERROR_PATTERN_OUT => apl_error_pattern_apl2,
+ APL_SEND_OUT => apl_send_apl2,
+ APL_TARGET_ADDRESS_OUT => apl_target_adress_apl2,
+
+ -- Receiver port
+ APL_DATA_IN => apl_data_in_apl2,
+ APL_TYP_IN => apl_typ_apl2,
+ APL_DATAREADY_IN => apl_dataready_apl2,
+ APL_READ_OUT => apl_read_apl2,
+
+ -- APL Control port
+ APL_RUN_IN => apl_run_apl2,
+ APL_SEQNR_IN => apl_seqnr_apl2
+ );
+
+-------------------------------------------------------------------------------
+-- the 2 APIs
+-------------------------------------------------------------------------------
+
+API1: trb_net_active_apibuf
+ generic map (
+ FIFO_TERM_BUFFER_DEPTH => 3)
+ port map (
+ CLK => clk,
+ RESET => reset,
+ CLK_EN => '1',
+
+ -- APL Transmitter port
+ APL_DATA_IN => apl_data_out_apl1,
+ APL_WRITE_IN => apl_write_apl1,
+ APL_FIFO_FULL_OUT => apl_fifo_full_apl1,
+ APL_SHORT_TRANSFER_IN => apl_short_transfer_apl1,
+ APL_DTYPE_IN => apl_dtype_apl1,
+ APL_ERROR_PATTERN_IN => apl_error_pattern_apl1,
+ APL_SEND_IN => apl_send_apl1,
+ APL_TARGET_ADDRESS_IN => apl_target_adress_apl1,
+
+ -- Receiver port
+ APL_DATA_OUT => apl_data_in_apl1,
+ APL_TYP_OUT => apl_typ_apl1,
+ APL_DATAREADY_OUT => apl_dataready_apl1,
+ APL_READ_IN => apl_read_apl1,
+
+ -- APL Control port
+ APL_RUN_OUT => apl_run_apl1,
+ APL_SEQNR_OUT => apl_seqnr_apl1,
+ APL_MY_ADDRESS_IN => x"0001",
+
+ MED_INIT_DATAREADY_OUT => MED_INIT_DATAREADY_1_to_2,
+ MED_INIT_DATA_OUT => MED_INIT_DATA_1_to_2,
+ MED_INIT_READ_IN => MED_INIT_READ_1_to_2,
+ MED_INIT_DATAREADY_IN => MED_INIT_DATAREADY_2_to_1,
+ MED_INIT_DATA_IN => MED_INIT_DATA_2_to_1,
+ MED_INIT_ERROR_IN => "000",
+ MED_INIT_READ_OUT => MED_INIT_READ_2_to_1,
+
+ MED_REPLY_DATAREADY_OUT => MED_REPLY_DATAREADY_1_to_2,
+ MED_REPLY_DATA_OUT => MED_REPLY_DATA_1_to_2,
+ MED_REPLY_READ_IN => MED_REPLY_READ_1_to_2,
+ MED_REPLY_DATAREADY_IN => MED_REPLY_DATAREADY_2_to_1,
+ MED_REPLY_DATA_IN => MED_REPLY_DATA_2_to_1,
+ MED_REPLY_ERROR_IN => "000",
+ MED_REPLY_READ_OUT => MED_REPLY_READ_2_to_1,
+
+ CTRL_LOCKED => (others => '0'),
+ CTRL_GEN => (others => '0'),
+
+ STAT_CTRL_INIT_BUFFER => (others => '0'),
+ STAT_CTRL_REPLY_BUFFER => (others => '0')
+ );
+
+API2: trb_net_active_apibuf
+ generic map (
+ FIFO_TERM_BUFFER_DEPTH => 3)
+ port map (
+ CLK => clk,
+ RESET => reset,
+ CLK_EN => '1',
+
+ -- APL Transmitter port
+ APL_DATA_IN => apl_data_out_apl2,
+ APL_WRITE_IN => apl_write_apl2,
+ APL_FIFO_FULL_OUT => apl_fifo_full_apl2,
+ APL_SHORT_TRANSFER_IN => apl_short_transfer_apl2,
+ APL_DTYPE_IN => apl_dtype_apl2,
+ APL_ERROR_PATTERN_IN => apl_error_pattern_apl2,
+ APL_SEND_IN => apl_send_apl2,
+ APL_TARGET_ADDRESS_IN => apl_target_adress_apl2,
+
+ -- Receiver port
+ APL_DATA_OUT => apl_data_in_apl2,
+ APL_TYP_OUT => apl_typ_apl2,
+ APL_DATAREADY_OUT => apl_dataready_apl2,
+ APL_READ_IN => apl_read_apl2,
+
+ -- APL Control port
+ APL_RUN_OUT => apl_run_apl2,
+ APL_SEQNR_OUT => apl_seqnr_apl2,
+ APL_MY_ADDRESS_IN => x"0002",
+
+ MED_INIT_DATAREADY_OUT => MED_INIT_DATAREADY_2_to_1,
+ MED_INIT_DATA_OUT => MED_INIT_DATA_2_to_1,
+ MED_INIT_READ_IN => MED_INIT_READ_2_to_1,
+ MED_INIT_DATAREADY_IN => MED_INIT_DATAREADY_1_to_2,
+ MED_INIT_DATA_IN => MED_INIT_DATA_1_to_2,
+ MED_INIT_ERROR_IN => "000",
+ MED_INIT_READ_OUT => MED_INIT_READ_1_to_2,
+
+ MED_REPLY_DATAREADY_OUT => MED_REPLY_DATAREADY_2_to_1,
+ MED_REPLY_DATA_OUT => MED_REPLY_DATA_2_to_1,
+ MED_REPLY_READ_IN => MED_REPLY_READ_2_to_1,
+ MED_REPLY_DATAREADY_IN => MED_REPLY_DATAREADY_1_to_2,
+ MED_REPLY_DATA_IN => MED_REPLY_DATA_1_to_2,
+ MED_REPLY_ERROR_IN => "000",
+ MED_REPLY_READ_OUT => MED_REPLY_READ_1_to_2,
+
+
+ CTRL_LOCKED => (others => '0'),
+ CTRL_GEN => (others => '0'),
+
+ STAT_CTRL_INIT_BUFFER => (others => '0'),
+ STAT_CTRL_REPLY_BUFFER => (others => '0')
+ );
+
+end trb_net_dummy_apl_apibuf_testbench_arch;
+
+
+-- fuse -prj trb_net_dummy_apl_apibuf_testbench_beh.prj -top trb_net_dummy_apl_apibuf_testbench -o trb_net_dummy_apl_apibuf_testbench
+
+-- trb_net_dummy_apl_apibuf_testbench -tclbatch apl_apibuf_testsim.tcl
+
+-- ntrace select -o on -m / -l this
+-- ntrace start
+-- run 1000 ns
+-- quit
+
+-- isimwave isimwavedata.xwv
+
--- /dev/null
+vhdl work "../trb_net_std.vhd"
+vhdl work "../trb_net_fifo.vhd"
+vhdl work "../xilinx/trb_net_fifo_arch.vhd"
+vhdl work "../xilinx/shift_lut_x16.vhd"
+vhdl work "../trb_net_ibuf.vhd"
+vhdl work "../trb_net_obuf.vhd"
+vhdl work "../trb_net_iobuf.vhd"
+vhdl work "../trb_net_active_api.vhd"
+vhdl work "../trb_net_active_apibuf.vhd"
+vhdl work "trb_net_dummy_apl.vhd"
+vhdl work "trb_net_dummy_apl_apibuf_testbench.vhd"
fifo_to_int_read <= '1';
else
fifo_to_int_read <= '0';
+ -- but keep the old content
+ next_INT_INIT_DATA_OUT <= reg_INT_INIT_DATA_OUT;
end if;
end if; -- fifo_to_int_empty = '0'
end if;
fifo_to_int_read <= '1';
else
fifo_to_int_read <= '0';
+ -- but keep the old content
+ next_INT_INIT_DATA_OUT <= reg_INT_INIT_DATA_OUT;
end if;
end if; -- fifo_to_int_empty = '0'
end if;
-- SHUTDOWN: Empty the pipe
-------------------------------------------------------------------------------
elsif current_state = SHUTDOWN then
+ next_state <= SHUTDOWN;
if fifo_to_int_empty = '0' then
-- data words have to be prepared
next_INT_INIT_DATAREADY_OUT <= '1';
fifo_to_int_read <= '1';
else
fifo_to_int_read <= '0';
+ -- but keep the old content
+ next_INT_INIT_DATA_OUT <= reg_INT_INIT_DATA_OUT;
end if;
- else
+ elsif INT_INIT_READ_IN = '1' and reg_INT_INIT_DATAREADY_OUT = '1' then
-- we are done
next_state <= SEND_TRAILER;
next_INT_INIT_DATAREADY_OUT <= '1';
next_INT_INIT_DATA_OUT(TYPE_POSITION) <= TYPE_TRM;
next_INT_INIT_DATA_OUT(DWORD_POSITION) <= registered_trailer;
+ else
+ -- but keep the old content
+ next_INT_INIT_DATA_OUT <= reg_INT_INIT_DATA_OUT;
end if;
-------------------------------------------------------------------------------
-- SEND_TRAILER
signal fifo_depth : std_logic_vector(7 downto 0);
signal filtered_dataready : std_logic;
-signal filtered_read_out : std_logic;
+signal next_read_out, reg_read_out : std_logic;
signal got_ack_internal, reg_ack_internal : std_logic; --should be raised for 1 cycle when ack
--arrived
begin -- process
filtered_dataready <= '0';
got_ack_internal <= '0';
- filtered_read_out <= '0';
+ next_read_out <= '0';
fifo_write <= '0';
next_rec_buffer_size_out <= current_rec_buffer_size_out;
next_error_state <= current_error_state;
- if MED_DATAREADY_IN = '1' then
+ if MED_DATAREADY_IN = '1' and reg_read_out= '1' then
if MED_DATA_IN(TYPE_POSITION) = TYPE_ACK then
+ -- BUGBUG: this causes trouble if the IBUF is full
got_ack_internal <= '1';
- filtered_read_out <= '1'; -- read from media in any case
if MED_DATA_IN(F1_POSITION) = F1_CHECK_ACK then
next_rec_buffer_size_out <= MED_DATA_IN(BUFFER_SIZE_POSITION);
end if;
elsif fifo_full = '0' and is_locked = '0' then
fifo_write <= '1';
+ next_read_out <= '1';
elsif fifo_full = '1' then
next_error_state <= GOT_OVERFLOW_ERROR;
elsif is_locked = '1' then
else
next_error_state <= GOT_UNDEFINED_ERROR;
end if; -- end TYPE
-
- end if; -- end MED_DATAREADY_IN
+ end if; -- end MED_DATAREADY_IN
+ if fifo_full = '0' and is_locked = '0' then
+ next_read_out <= '1';
+ end if;
end process;
- -- unregistered reaction, because it has to be fast!!!
- MED_READ_OUT <= filtered_read_out;
+ MED_READ_OUT <= reg_read_out;
reg_buffer: process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
current_rec_buffer_size_out <= (others => '0');
- reg_ack_internal <='0';
+ reg_ack_internal <= '0';
+ reg_read_out <= '0';
current_error_state <= IDLE;
elsif CLK_EN = '1' then
current_rec_buffer_size_out <= next_rec_buffer_size_out;
- reg_ack_internal <= got_ack_internal;
+ reg_ack_internal <= got_ack_internal;
+ reg_read_out <= next_read_out;
current_error_state <= next_error_state;
else
current_rec_buffer_size_out <= current_rec_buffer_size_out;
- reg_ack_internal <= reg_ack_internal;
+ reg_ack_internal <= reg_ack_internal;
+ reg_read_out <= reg_read_out;
current_error_state <= current_error_state;
end if;
end if;
end process;
+
+
+
+
+
-- this process controls what will be forwarded to the internal point
- FILTER_DATA_OUT : process (INT_HEADER_IN, fifo_data_out,
- current_last_header, tmp_INT_DATAREADY_OUT)
+ DATA_OUT : process (INT_HEADER_IN, fifo_data_out, reg_INT_DATA_OUT,
+ current_last_header, tmp_INT_DATAREADY_OUT, INT_READ_IN,
+ reg_INT_DATAREADY_OUT, release_locked, is_locked)
begin
- tmp_INT_DATA_OUT <= (others => '0');
- if INT_HEADER_IN = '1' then
- tmp_INT_DATA_OUT <= current_last_header;
- elsif tmp_INT_DATAREADY_OUT ='1' then
- tmp_INT_DATA_OUT <= fifo_data_out;
- else
- tmp_INT_DATA_OUT(TYPE_POSITION) <= TYPE_ILLEGAL;
- end if;
- end process;
+ tmp_INT_DATA_OUT <= reg_INT_DATA_OUT;
+ tmp_INT_DATAREADY_OUT <= reg_INT_DATAREADY_OUT;
+ got_eob_out <= '0';
+ fifo_read <= '0';
+ got_locked <= is_locked;
+ next_last_header <= current_last_header;
+
+ if fifo_empty = '0' then
+ if (INT_READ_IN = '1' and reg_INT_DATAREADY_OUT = '1') or reg_INT_DATAREADY_OUT = '0' then
+ -- next data word can be registered
+ tmp_INT_DATA_OUT <= fifo_data_out;
+ tmp_INT_DATAREADY_OUT <= '1';
+ fifo_read <= '1';
+ if fifo_data_out(TYPE_POSITION) = TYPE_TRM then
+ got_eob_out <= '1';
+ if release_locked = '0' then
+ got_locked <= '1';
+ end if;
+ elsif (fifo_data_out(TYPE_POSITION) = TYPE_EOB) then
+ fifo_read <= '1';
+ got_eob_out <= '1';
+ tmp_INT_DATAREADY_OUT <= '0';
+ -- this should happen only one CLK cycle
+ else -- no TRM, normal read
+ got_eob_out <= '0';
+
+ if fifo_data_out(TYPE_POSITION) = TYPE_HDR then
+ next_last_header <= fifo_data_out;
+ end if;
+ end if;
+ elsif (fifo_data_out(TYPE_POSITION) = TYPE_EOB) then
+ fifo_read <= '1';
+ got_eob_out <= '1';
+ -- this should happen only one CLK cycle
+ end if; -- end valid read
--- calculate the INT_DATAREADY_OUT
- --header transmit will happen 1CLK later due to registering!!
- CALC_INT_DATAREADY_OUT: process (fifo_empty, fifo_data_out)
- begin
- if fifo_empty = '0' and not (fifo_data_out(TYPE_POSITION) = TYPE_EOB) then
- tmp_INT_DATAREADY_OUT <= '1';
else
tmp_INT_DATAREADY_OUT <= '0';
end if;
+
end process;
-
+
+ -- for HDR retransmit we need another solution to do not overwrite the reg_
+ -- DATA word
+-- tmp_INT_DATA_OUT <= (others => '0');
+-- if INT_HEADER_IN = '1' then
+-- tmp_INT_DATA_OUT <= current_last_header;
+-- elsif tmp_INT_DATAREADY_OUT ='1' then
+-- tmp_INT_DATA_OUT <= fifo_data_out;
+-- else
+-- tmp_INT_DATA_OUT(TYPE_POSITION) <= TYPE_ILLEGAL;
+-- end if;
+-- end process;
+
reg_dataout: process(CLK)
begin
if rising_edge(CLK) then
INT_DATAREADY_OUT <= reg_INT_DATAREADY_OUT;
INT_DATA_OUT <= reg_INT_DATA_OUT;
--- this process control the read of the internal point from the fifo
- FILTER_OUT: process (INT_READ_IN, INT_HEADER_IN, fifo_data_out,
- current_last_header, release_locked, is_locked)
-
- begin -- process
- got_locked <= is_locked;
- fifo_read <= '0';
- got_eob_out <= '0';
- next_last_header <= current_last_header;
-
- if INT_READ_IN = '1' then
-
- if fifo_data_out(TYPE_POSITION) = TYPE_TRM then
- got_eob_out <= '1';
- fifo_read <= '1';
- if release_locked = '0' then
- got_locked <= '1';
- end if;
- else -- no TRM, normal read
- got_eob_out <= '0';
- fifo_read <= '1';
-
- if fifo_data_out(TYPE_POSITION) = TYPE_HDR then
- next_last_header <= fifo_data_out;
- end if;
- end if;
-
-
- else -- no external read
- if fifo_data_out(TYPE_POSITION) = TYPE_EOB then
- got_eob_out <= '1';
- fifo_read <= '1'; -- autodestroy EOB
- end if;
- end if; -- INT_READ_IN
- end process;
-
-
release_locked <= CTRL_LOCKED(0);
STAT_LOCKED(0) <= is_locked;
RESET : in std_logic;
CLK_EN : in std_logic;
-- Media direction port
- MED_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out
+ MED_INIT_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out
--by the media (via the TrbNetIOMultiplexer)
- MED_DATA_OUT: out STD_LOGIC_VECTOR (51 downto 0); -- Data word
- MED_READ_IN: in STD_LOGIC; -- Media is reading
- MED_ERROR_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Status bits
- MED_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media
+ MED_INIT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
+ MED_INIT_READ_IN: in STD_LOGIC; -- Media is reading
+ MED_INIT_ERROR_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Status bits
+
+ MED_INIT_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media
-- (the IOBUF MUST read)
- MED_DATA_IN: in STD_LOGIC_VECTOR (51 downto 0); -- Data word
- MED_READ_OUT: out STD_LOGIC; -- buffer reads a word from media
- MED_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits
+ MED_INIT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
+ MED_INIT_READ_OUT: out STD_LOGIC; -- buffer reads a word from media
+ MED_INIT_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits
+
+ MED_REPLY_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out
+ --by the media (via the TrbNetIOMultiplexer)
+ MED_REPLY_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
+ MED_REPLY_READ_IN: in STD_LOGIC; -- Media is reading
+ MED_REPLY_ERROR_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Status bits
+
+ MED_REPLY_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media
+ -- (the IOBUF MUST read)
+ MED_REPLY_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
+ MED_REPLY_READ_OUT: out STD_LOGIC; -- buffer reads a word from media
+ MED_REPLY_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits
+
-- Internal direction port
INT_INIT_DATAREADY_OUT: out STD_LOGIC;
INT_INIT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
INT_INIT_READ_IN: in STD_LOGIC;
- INT_INIT_ERROR_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Status bits
+
INT_INIT_DATAREADY_IN: in STD_LOGIC;
INT_INIT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
INT_INIT_READ_OUT: out STD_LOGIC;
- INT_INIT_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits
+
INT_REPLY_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last
-- header (only for the reply path)
INT_REPLY_DATAREADY_OUT: out STD_LOGIC;
INT_REPLY_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word
INT_REPLY_READ_IN: in STD_LOGIC;
- INT_REPLY_ERROR_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Status bits
+
INT_REPLY_DATAREADY_IN: in STD_LOGIC;
INT_REPLY_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word
INT_REPLY_READ_OUT: out STD_LOGIC;
- INT_REPLY_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits
+
-- Status and control port
STAT_GEN: out STD_LOGIC_VECTOR (31 downto 0); -- General Status
STAT_LOCKED: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control
END component;
-- internal signals for the INITIBUF
- signal INITIBUF_med_dataready_in: STD_LOGIC;
- signal INITIBUF_med_data_in: STD_LOGIC_VECTOR (50 downto 0);
- signal INITIBUF_med_red_out: STD_LOGIC;
- signal INITIBUF_error_in: STD_LOGIC_VECTOR (2 downto 0);
+ signal INITIBUF_error: STD_LOGIC_VECTOR (2 downto 0); -- error watch needed!
signal INITIBUF_stat_locked, INITIBUF_ctrl_locked: STD_LOGIC_VECTOR (15 downto 0);
signal INITIBUF_stat_buffer : STD_LOGIC_VECTOR (31 downto 0);
-- internal signals for the REPLYIBUF
- signal REPLYIBUF_med_dataready_in: STD_LOGIC;
- signal REPLYIBUF_med_data_in: STD_LOGIC_VECTOR (50 downto 0);
- signal REPLYIBUF_med_red_out: STD_LOGIC;
- signal REPLYIBUF_header_in: STD_LOGIC;
- signal REPLYIBUF_error_in: STD_LOGIC_VECTOR (2 downto 0);
+ signal REPLYIBUF_error: STD_LOGIC_VECTOR (2 downto 0); -- error watch needed!
signal REPLYIBUF_stat_locked, REPLYIBUF_ctrl_locked: STD_LOGIC_VECTOR (15 downto 0);
signal REPLYIBUF_stat_buffer : STD_LOGIC_VECTOR (31 downto 0);
-- internal signals for the INITOBUF
- signal INITOBUF_med_dataready_out: STD_LOGIC;
- signal INITOBUF_med_data_out: STD_LOGIC_VECTOR (50 downto 0);
- signal INITOBUF_med_red_in: STD_LOGIC;
- signal INITOBUF_error_out: STD_LOGIC_VECTOR (2 downto 0);
signal INITOBUF_stat_locked, INITOBUF_ctrl_locked: STD_LOGIC_VECTOR (15 downto 0);
signal INITOBUF_stat_buffer, INITOBUF_ctrl_buffer: STD_LOGIC_VECTOR (31 downto 0);
-- internal signals for the REPLYOBUF
- signal REPLYOBUF_med_dataready_out: STD_LOGIC;
- signal REPLYOBUF_med_data_out: STD_LOGIC_VECTOR (50 downto 0);
- signal REPLYOBUF_med_red_in: STD_LOGIC;
- signal REPLYOBUF_error_out: STD_LOGIC_VECTOR (2 downto 0);
signal REPLYOBUF_stat_locked, REPLYOBUF_ctrl_locked: STD_LOGIC_VECTOR (15 downto 0);
signal REPLYOBUF_stat_buffer, REPLYOBUF_ctrl_buffer: STD_LOGIC_VECTOR (31 downto 0);
CLK => CLK,
RESET => RESET,
CLK_EN => CLK_EN,
- MED_DATAREADY_IN => INITIBUF_med_dataready_in,
- MED_DATA_IN => INITIBUF_med_data_in,
- MED_READ_OUT => INITIBUF_med_red_out,
- MED_ERROR_IN => INITIBUF_error_in,
+ MED_DATAREADY_IN => MED_INIT_DATAREADY_IN,
+ MED_DATA_IN => MED_INIT_DATA_IN,
+ MED_READ_OUT => MED_INIT_READ_OUT,
+ MED_ERROR_IN => MED_INIT_ERROR_IN,
INT_HEADER_IN => '0',
INT_DATAREADY_OUT => INT_INIT_DATAREADY_OUT,
INT_DATA_OUT => INT_INIT_DATA_OUT,
INT_READ_IN => INT_INIT_READ_IN,
- INT_ERROR_OUT => INT_INIT_ERROR_OUT,
+ INT_ERROR_OUT => INITIBUF_error,
STAT_LOCKED(15 downto 0) => INITIBUF_stat_locked,
CTRL_LOCKED(15 downto 0) => INITIBUF_ctrl_locked,
STAT_BUFFER(31 downto 0) => INITIBUF_stat_buffer
CLK => CLK,
RESET => RESET,
CLK_EN => CLK_EN,
- MED_DATAREADY_IN => REPLYIBUF_med_dataready_in,
- MED_DATA_IN => REPLYIBUF_med_data_in,
- MED_READ_OUT => REPLYIBUF_med_red_out,
- MED_ERROR_IN => REPLYIBUF_error_in,
- INT_HEADER_IN => REPLYIBUF_header_in,
+ MED_DATAREADY_IN => MED_REPLY_DATAREADY_IN,
+ MED_DATA_IN => MED_REPLY_DATA_IN,
+ MED_READ_OUT => MED_REPLY_READ_OUT,
+ MED_ERROR_IN => MED_REPLY_ERROR_IN,
+ INT_HEADER_IN => INT_REPLY_HEADER_IN,
INT_DATAREADY_OUT => INT_REPLY_DATAREADY_OUT,
INT_DATA_OUT => INT_REPLY_DATA_OUT,
INT_READ_IN => INT_REPLY_READ_IN,
- INT_ERROR_OUT => INT_REPLY_ERROR_OUT,
+ INT_ERROR_OUT => REPLYIBUF_error,
STAT_LOCKED(15 downto 0) => REPLYIBUF_stat_locked,
CTRL_LOCKED(15 downto 0) => REPLYIBUF_ctrl_locked,
STAT_BUFFER(31 downto 0) => REPLYIBUF_stat_buffer
CLK => CLK,
RESET => RESET,
CLK_EN => CLK_EN,
- MED_DATAREADY_OUT => INITOBUF_med_dataready_out,
- MED_DATA_OUT => INITOBUF_med_data_out,
- MED_READ_IN => INITOBUF_med_red_in,
- MED_ERROR_OUT => INITOBUF_error_out,
+ MED_DATAREADY_OUT => MED_INIT_DATAREADY_OUT,
+ MED_DATA_OUT => MED_INIT_DATA_OUT,
+ MED_READ_IN => MED_INIT_READ_IN,
+ MED_ERROR_OUT => MED_INIT_ERROR_OUT,
INT_DATAREADY_IN => INT_INIT_DATAREADY_IN,
INT_DATA_IN => INT_INIT_DATA_IN,
INT_READ_OUT => INT_INIT_READ_OUT,
- INT_ERROR_IN => INT_INIT_ERROR_IN,
+ INT_ERROR_IN => (others => '0'),
STAT_LOCKED(15 downto 0) => INITOBUF_stat_locked,
CTRL_LOCKED(15 downto 0) => INITOBUF_ctrl_locked,
STAT_BUFFER(31 downto 0) => INITOBUF_stat_buffer,
CLK => CLK,
RESET => RESET,
CLK_EN => CLK_EN,
- MED_DATAREADY_OUT => REPLYOBUF_med_dataready_out,
- MED_DATA_OUT => REPLYOBUF_med_data_out,
- MED_READ_IN => REPLYOBUF_med_red_in,
- MED_ERROR_OUT => REPLYOBUF_error_out,
+ MED_DATAREADY_OUT => MED_REPLY_DATAREADY_OUT,
+ MED_DATA_OUT => MED_REPLY_DATA_OUT,
+ MED_READ_IN => MED_REPLY_READ_IN,
+ MED_ERROR_OUT => MED_REPLY_ERROR_OUT,
INT_DATAREADY_IN => INT_REPLY_DATAREADY_IN,
INT_DATA_IN => INT_REPLY_DATA_IN,
INT_READ_OUT => INT_REPLY_READ_OUT,
- INT_ERROR_IN => INT_REPLY_ERROR_IN,
+ INT_ERROR_IN => (others => '0'),
STAT_LOCKED(15 downto 0) => REPLYOBUF_stat_locked,
CTRL_LOCKED(15 downto 0) => REPLYOBUF_ctrl_locked,
STAT_BUFFER(31 downto 0) => REPLYOBUF_stat_buffer,
jspc29 / trbnet.git / commitdiff