--- /dev/null
+
+
+-- channel_0 is in "8b10b" mode
+-- channel_1 is in "Disabled" mode
+-- channel_2 is in "Disabled" mode
+-- channel_3 is in "Disabled" mode
+
+--synopsys translate_off
+
+library pcsa_work;
+use pcsa_work.all;
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity PCSA is
+GENERIC(
+ CONFIG_FILE : String := "serdes_gbe_0_100_ext.txt"
+ );
+port (
+ HDINP0 : in std_logic;
+ HDINN0 : in std_logic;
+ HDINP1 : in std_logic;
+ HDINN1 : in std_logic;
+ HDINP2 : in std_logic;
+ HDINN2 : in std_logic;
+ HDINP3 : in std_logic;
+ HDINN3 : in std_logic;
+ HDOUTP0 : out std_logic;
+ HDOUTN0 : out std_logic;
+ HDOUTP1 : out std_logic;
+ HDOUTN1 : out std_logic;
+ HDOUTP2 : out std_logic;
+ HDOUTN2 : out std_logic;
+ HDOUTP3 : out std_logic;
+ HDOUTN3 : out std_logic;
+ REFCLKP : in std_logic;
+ REFCLKN : in std_logic;
+ RXREFCLKP : in std_logic;
+ RXREFCLKN : in std_logic;
+ FFC_QUAD_RST : in std_logic;
+ FFC_MACRO_RST : in std_logic;
+
+ FFC_LANE_TX_RST0 : in std_logic;
+ FFC_LANE_TX_RST1 : in std_logic;
+ FFC_LANE_TX_RST2 : in std_logic;
+ FFC_LANE_TX_RST3 : in std_logic;
+
+ FFC_LANE_RX_RST0 : in std_logic;
+ FFC_LANE_RX_RST1 : in std_logic;
+ FFC_LANE_RX_RST2 : in std_logic;
+ FFC_LANE_RX_RST3 : in std_logic;
+
+ FFC_PCIE_EI_EN_0 : in std_logic;
+ FFC_PCIE_EI_EN_1 : in std_logic;
+ FFC_PCIE_EI_EN_2 : in std_logic;
+ FFC_PCIE_EI_EN_3 : in std_logic;
+
+ FFC_PCIE_CT_0 : in std_logic;
+ FFC_PCIE_CT_1 : in std_logic;
+ FFC_PCIE_CT_2 : in std_logic;
+ FFC_PCIE_CT_3 : in std_logic;
+
+ FFS_PCIE_CON_0 : out std_logic;
+ FFS_PCIE_CON_1 : out std_logic;
+ FFS_PCIE_CON_2 : out std_logic;
+ FFS_PCIE_CON_3 : out std_logic;
+
+ FFS_PCIE_DONE_0 : out std_logic;
+ FFS_PCIE_DONE_1 : out std_logic;
+ FFS_PCIE_DONE_2 : out std_logic;
+ FFS_PCIE_DONE_3 : out std_logic;
+
+ FFC_PCIE_TX_0 : in std_logic;
+ FFC_PCIE_TX_1 : in std_logic;
+ FFC_PCIE_TX_2 : in std_logic;
+ FFC_PCIE_TX_3 : in std_logic;
+
+ FFC_PCIE_RX_0 : in std_logic;
+ FFC_PCIE_RX_1 : in std_logic;
+ FFC_PCIE_RX_2 : in std_logic;
+ FFC_PCIE_RX_3 : in std_logic;
+
+ FFC_SD_0 : in std_logic;
+ FFC_SD_1 : in std_logic;
+ FFC_SD_2 : in std_logic;
+ FFC_SD_3 : in std_logic;
+
+ FFC_EN_CGA_0 : in std_logic;
+ FFC_EN_CGA_1 : in std_logic;
+ FFC_EN_CGA_2 : in std_logic;
+ FFC_EN_CGA_3 : in std_logic;
+
+ FFC_ALIGN_EN_0 : in std_logic;
+ FFC_ALIGN_EN_1 : in std_logic;
+ FFC_ALIGN_EN_2 : in std_logic;
+ FFC_ALIGN_EN_3 : in std_logic;
+
+ FFC_AB_RESET : in std_logic;
+ FFC_CD_RESET : in std_logic;
+
+ FFS_LS_STATUS_0 : out std_logic;
+ FFS_LS_STATUS_1 : out std_logic;
+ FFS_LS_STATUS_2 : out std_logic;
+ FFS_LS_STATUS_3 : out std_logic;
+
+ FFS_AB_STATUS : out std_logic;
+ FFS_CD_STATUS : out std_logic;
+
+ FFS_AB_ALIGNED : out std_logic;
+ FFS_CD_ALIGNED : out std_logic;
+
+ FFS_RLOS_LO0 : out std_logic;
+ FFS_RLOS_LO1 : out std_logic;
+ FFS_RLOS_LO2 : out std_logic;
+ FFS_RLOS_LO3 : out std_logic;
+
+ FFS_AB_FAILED : out std_logic;
+ FFS_CD_FAILED : out std_logic;
+
+ FFC_FB_LB_0 : in std_logic;
+ FFC_FB_LB_1 : in std_logic;
+ FFC_FB_LB_2 : in std_logic;
+ FFC_FB_LB_3 : in std_logic;
+
+ FFC_SB_INV_RX_0 : in std_logic;
+ FFC_SB_INV_RX_1 : in std_logic;
+ FFC_SB_INV_RX_2 : in std_logic;
+ FFC_SB_INV_RX_3 : in std_logic;
+
+ FFS_CC_ORUN_0 : out std_logic;
+ FFS_CC_ORUN_1 : out std_logic;
+ FFS_CC_ORUN_2 : out std_logic;
+ FFS_CC_ORUN_3 : out std_logic;
+
+ FFS_CC_URUN_0 : out std_logic;
+ FFS_CC_URUN_1 : out std_logic;
+ FFS_CC_URUN_2 : out std_logic;
+ FFS_CC_URUN_3 : out std_logic;
+
+ FFC_CK_CORE_TX : in std_logic;
+ FFC_CK_CORE_RX : in std_logic;
+ RDATAO_7 : out std_logic;
+ RDATAO_6 : out std_logic;
+ RDATAO_5 : out std_logic;
+ RDATAO_4 : out std_logic;
+ RDATAO_3 : out std_logic;
+ RDATAO_2 : out std_logic;
+ RDATAO_1 : out std_logic;
+ RDATAO_0 : out std_logic;
+ INTO : out std_logic;
+
+ ADDRI_7 : in std_logic;
+ ADDRI_6 : in std_logic;
+ ADDRI_5 : in std_logic;
+ ADDRI_4 : in std_logic;
+ ADDRI_3 : in std_logic;
+ ADDRI_2 : in std_logic;
+ ADDRI_1 : in std_logic;
+ ADDRI_0 : in std_logic;
+ WDATAI_7 : in std_logic;
+ WDATAI_6 : in std_logic;
+ WDATAI_5 : in std_logic;
+ WDATAI_4 : in std_logic;
+ WDATAI_3 : in std_logic;
+ WDATAI_2 : in std_logic;
+ WDATAI_1 : in std_logic;
+ WDATAI_0 : in std_logic;
+ RDI : in std_logic;
+ WSTBI : in std_logic;
+
+ CS_CHIF_0 : in std_logic;
+ CS_CHIF_1 : in std_logic;
+ CS_CHIF_2 : in std_logic;
+ CS_CHIF_3 : in std_logic;
+ CS_QIF : in std_logic;
+
+ QUAD_ID_1 : in std_logic;
+ QUAD_ID_0 : in std_logic;
+
+ FF_SYSCLK_P1 : out std_logic;
+
+ FF_SYSCLK0 : out std_logic;
+ FF_SYSCLK1 : out std_logic;
+ FF_SYSCLK2 : out std_logic;
+ FF_SYSCLK3 : out std_logic;
+
+ FF_RXCLK_P1 : out std_logic;
+ FF_RXCLK_P2 : out std_logic;
+
+ FF_RXCLK0 : out std_logic;
+ FF_RXCLK1 : out std_logic;
+ FF_RXCLK2 : out std_logic;
+ FF_RXCLK3 : out std_logic;
+
+ QUAD_CLK : out std_logic;
+
+ GRP_CLK_P1_3 : in std_logic;
+ GRP_CLK_P1_2 : in std_logic;
+ GRP_CLK_P1_1 : in std_logic;
+ GRP_CLK_P1_0 : in std_logic;
+
+ GRP_CLK_P2_3 : in std_logic;
+ GRP_CLK_P2_2 : in std_logic;
+ GRP_CLK_P2_1 : in std_logic;
+ GRP_CLK_P2_0 : in std_logic;
+
+ GRP_START_3 : in std_logic;
+ GRP_START_2 : in std_logic;
+ GRP_START_1 : in std_logic;
+ GRP_START_0 : in std_logic;
+
+ GRP_DONE_3 : in std_logic;
+ GRP_DONE_2 : in std_logic;
+ GRP_DONE_1 : in std_logic;
+ GRP_DONE_0 : in std_logic;
+
+ GRP_DESKEW_ERROR_3 : in std_logic;
+ GRP_DESKEW_ERROR_2 : in std_logic;
+ GRP_DESKEW_ERROR_1 : in std_logic;
+ GRP_DESKEW_ERROR_0 : in std_logic;
+
+ IQA_START_LS : out std_logic;
+ IQA_DONE_LS : out std_logic;
+ IQA_AND_FP1_LS : out std_logic;
+ IQA_AND_FP0_LS : out std_logic;
+ IQA_OR_FP1_LS : out std_logic;
+ IQA_OR_FP0_LS : out std_logic;
+ IQA_RST_N : out std_logic;
+
+ FF_TCLK0 : in std_logic;
+ FF_TCLK1 : in std_logic;
+ FF_TCLK2 : in std_logic;
+ FF_TCLK3 : in std_logic;
+
+ FF_RCLK0 : in std_logic;
+ FF_RCLK1 : in std_logic;
+ FF_RCLK2 : in std_logic;
+ FF_RCLK3 : in std_logic;
+ TCK_FMACP : in std_logic;
+
+ FF_TXD_0_23 : in std_logic;
+ FF_TXD_0_22 : in std_logic;
+ FF_TXD_0_21 : in std_logic;
+ FF_TXD_0_20 : in std_logic;
+ FF_TXD_0_19 : in std_logic;
+ FF_TXD_0_18 : in std_logic;
+ FF_TXD_0_17 : in std_logic;
+ FF_TXD_0_16 : in std_logic;
+ FF_TXD_0_15 : in std_logic;
+ FF_TXD_0_14 : in std_logic;
+ FF_TXD_0_13 : in std_logic;
+ FF_TXD_0_12 : in std_logic;
+ FF_TXD_0_11 : in std_logic;
+ FF_TXD_0_10 : in std_logic;
+ FF_TXD_0_9 : in std_logic;
+ FF_TXD_0_8 : in std_logic;
+ FF_TXD_0_7 : in std_logic;
+ FF_TXD_0_6 : in std_logic;
+ FF_TXD_0_5 : in std_logic;
+ FF_TXD_0_4 : in std_logic;
+ FF_TXD_0_3 : in std_logic;
+ FF_TXD_0_2 : in std_logic;
+ FF_TXD_0_1 : in std_logic;
+ FF_TXD_0_0 : in std_logic;
+ FB_RXD_0_23 : out std_logic;
+ FB_RXD_0_22 : out std_logic;
+ FB_RXD_0_21 : out std_logic;
+ FB_RXD_0_20 : out std_logic;
+ FB_RXD_0_19 : out std_logic;
+ FB_RXD_0_18 : out std_logic;
+ FB_RXD_0_17 : out std_logic;
+ FB_RXD_0_16 : out std_logic;
+ FB_RXD_0_15 : out std_logic;
+ FB_RXD_0_14 : out std_logic;
+ FB_RXD_0_13 : out std_logic;
+ FB_RXD_0_12 : out std_logic;
+ FB_RXD_0_11 : out std_logic;
+ FB_RXD_0_10 : out std_logic;
+ FB_RXD_0_9 : out std_logic;
+ FB_RXD_0_8 : out std_logic;
+ FB_RXD_0_7 : out std_logic;
+ FB_RXD_0_6 : out std_logic;
+ FB_RXD_0_5 : out std_logic;
+ FB_RXD_0_4 : out std_logic;
+ FB_RXD_0_3 : out std_logic;
+ FB_RXD_0_2 : out std_logic;
+ FB_RXD_0_1 : out std_logic;
+ FB_RXD_0_0 : out std_logic;
+ FF_TXD_1_23 : in std_logic;
+ FF_TXD_1_22 : in std_logic;
+ FF_TXD_1_21 : in std_logic;
+ FF_TXD_1_20 : in std_logic;
+ FF_TXD_1_19 : in std_logic;
+ FF_TXD_1_18 : in std_logic;
+ FF_TXD_1_17 : in std_logic;
+ FF_TXD_1_16 : in std_logic;
+ FF_TXD_1_15 : in std_logic;
+ FF_TXD_1_14 : in std_logic;
+ FF_TXD_1_13 : in std_logic;
+ FF_TXD_1_12 : in std_logic;
+ FF_TXD_1_11 : in std_logic;
+ FF_TXD_1_10 : in std_logic;
+ FF_TXD_1_9 : in std_logic;
+ FF_TXD_1_8 : in std_logic;
+ FF_TXD_1_7 : in std_logic;
+ FF_TXD_1_6 : in std_logic;
+ FF_TXD_1_5 : in std_logic;
+ FF_TXD_1_4 : in std_logic;
+ FF_TXD_1_3 : in std_logic;
+ FF_TXD_1_2 : in std_logic;
+ FF_TXD_1_1 : in std_logic;
+ FF_TXD_1_0 : in std_logic;
+ FB_RXD_1_23 : out std_logic;
+ FB_RXD_1_22 : out std_logic;
+ FB_RXD_1_21 : out std_logic;
+ FB_RXD_1_20 : out std_logic;
+ FB_RXD_1_19 : out std_logic;
+ FB_RXD_1_18 : out std_logic;
+ FB_RXD_1_17 : out std_logic;
+ FB_RXD_1_16 : out std_logic;
+ FB_RXD_1_15 : out std_logic;
+ FB_RXD_1_14 : out std_logic;
+ FB_RXD_1_13 : out std_logic;
+ FB_RXD_1_12 : out std_logic;
+ FB_RXD_1_11 : out std_logic;
+ FB_RXD_1_10 : out std_logic;
+ FB_RXD_1_9 : out std_logic;
+ FB_RXD_1_8 : out std_logic;
+ FB_RXD_1_7 : out std_logic;
+ FB_RXD_1_6 : out std_logic;
+ FB_RXD_1_5 : out std_logic;
+ FB_RXD_1_4 : out std_logic;
+ FB_RXD_1_3 : out std_logic;
+ FB_RXD_1_2 : out std_logic;
+ FB_RXD_1_1 : out std_logic;
+ FB_RXD_1_0 : out std_logic;
+ FF_TXD_2_23 : in std_logic;
+ FF_TXD_2_22 : in std_logic;
+ FF_TXD_2_21 : in std_logic;
+ FF_TXD_2_20 : in std_logic;
+ FF_TXD_2_19 : in std_logic;
+ FF_TXD_2_18 : in std_logic;
+ FF_TXD_2_17 : in std_logic;
+ FF_TXD_2_16 : in std_logic;
+ FF_TXD_2_15 : in std_logic;
+ FF_TXD_2_14 : in std_logic;
+ FF_TXD_2_13 : in std_logic;
+ FF_TXD_2_12 : in std_logic;
+ FF_TXD_2_11 : in std_logic;
+ FF_TXD_2_10 : in std_logic;
+ FF_TXD_2_9 : in std_logic;
+ FF_TXD_2_8 : in std_logic;
+ FF_TXD_2_7 : in std_logic;
+ FF_TXD_2_6 : in std_logic;
+ FF_TXD_2_5 : in std_logic;
+ FF_TXD_2_4 : in std_logic;
+ FF_TXD_2_3 : in std_logic;
+ FF_TXD_2_2 : in std_logic;
+ FF_TXD_2_1 : in std_logic;
+ FF_TXD_2_0 : in std_logic;
+ FB_RXD_2_23 : out std_logic;
+ FB_RXD_2_22 : out std_logic;
+ FB_RXD_2_21 : out std_logic;
+ FB_RXD_2_20 : out std_logic;
+ FB_RXD_2_19 : out std_logic;
+ FB_RXD_2_18 : out std_logic;
+ FB_RXD_2_17 : out std_logic;
+ FB_RXD_2_16 : out std_logic;
+ FB_RXD_2_15 : out std_logic;
+ FB_RXD_2_14 : out std_logic;
+ FB_RXD_2_13 : out std_logic;
+ FB_RXD_2_12 : out std_logic;
+ FB_RXD_2_11 : out std_logic;
+ FB_RXD_2_10 : out std_logic;
+ FB_RXD_2_9 : out std_logic;
+ FB_RXD_2_8 : out std_logic;
+ FB_RXD_2_7 : out std_logic;
+ FB_RXD_2_6 : out std_logic;
+ FB_RXD_2_5 : out std_logic;
+ FB_RXD_2_4 : out std_logic;
+ FB_RXD_2_3 : out std_logic;
+ FB_RXD_2_2 : out std_logic;
+ FB_RXD_2_1 : out std_logic;
+ FB_RXD_2_0 : out std_logic;
+ FF_TXD_3_23 : in std_logic;
+ FF_TXD_3_22 : in std_logic;
+ FF_TXD_3_21 : in std_logic;
+ FF_TXD_3_20 : in std_logic;
+ FF_TXD_3_19 : in std_logic;
+ FF_TXD_3_18 : in std_logic;
+ FF_TXD_3_17 : in std_logic;
+ FF_TXD_3_16 : in std_logic;
+ FF_TXD_3_15 : in std_logic;
+ FF_TXD_3_14 : in std_logic;
+ FF_TXD_3_13 : in std_logic;
+ FF_TXD_3_12 : in std_logic;
+ FF_TXD_3_11 : in std_logic;
+ FF_TXD_3_10 : in std_logic;
+ FF_TXD_3_9 : in std_logic;
+ FF_TXD_3_8 : in std_logic;
+ FF_TXD_3_7 : in std_logic;
+ FF_TXD_3_6 : in std_logic;
+ FF_TXD_3_5 : in std_logic;
+ FF_TXD_3_4 : in std_logic;
+ FF_TXD_3_3 : in std_logic;
+ FF_TXD_3_2 : in std_logic;
+ FF_TXD_3_1 : in std_logic;
+ FF_TXD_3_0 : in std_logic;
+ FB_RXD_3_23 : out std_logic;
+ FB_RXD_3_22 : out std_logic;
+ FB_RXD_3_21 : out std_logic;
+ FB_RXD_3_20 : out std_logic;
+ FB_RXD_3_19 : out std_logic;
+ FB_RXD_3_18 : out std_logic;
+ FB_RXD_3_17 : out std_logic;
+ FB_RXD_3_16 : out std_logic;
+ FB_RXD_3_15 : out std_logic;
+ FB_RXD_3_14 : out std_logic;
+ FB_RXD_3_13 : out std_logic;
+ FB_RXD_3_12 : out std_logic;
+ FB_RXD_3_11 : out std_logic;
+ FB_RXD_3_10 : out std_logic;
+ FB_RXD_3_9 : out std_logic;
+ FB_RXD_3_8 : out std_logic;
+ FB_RXD_3_7 : out std_logic;
+ FB_RXD_3_6 : out std_logic;
+ FB_RXD_3_5 : out std_logic;
+ FB_RXD_3_4 : out std_logic;
+ FB_RXD_3_3 : out std_logic;
+ FB_RXD_3_2 : out std_logic;
+ FB_RXD_3_1 : out std_logic;
+ FB_RXD_3_0 : out std_logic;
+ TCK_FMAC : out std_logic;
+ BS4PAD_0 : out std_logic;
+ BS4PAD_1 : out std_logic;
+ BS4PAD_2 : out std_logic;
+ BS4PAD_3 : out std_logic;
+ COUT_21 : out std_logic;
+ COUT_20 : out std_logic;
+ COUT_19 : out std_logic;
+ COUT_18 : out std_logic;
+ COUT_17 : out std_logic;
+ COUT_16 : out std_logic;
+ COUT_15 : out std_logic;
+ COUT_14 : out std_logic;
+ COUT_13 : out std_logic;
+ COUT_12 : out std_logic;
+ COUT_11 : out std_logic;
+ COUT_10 : out std_logic;
+ COUT_9 : out std_logic;
+ COUT_8 : out std_logic;
+ COUT_7 : out std_logic;
+ COUT_6 : out std_logic;
+ COUT_5 : out std_logic;
+ COUT_4 : out std_logic;
+ COUT_3 : out std_logic;
+ COUT_2 : out std_logic;
+ COUT_1 : out std_logic;
+ COUT_0 : out std_logic;
+ CIN_12 : in std_logic;
+ CIN_11 : in std_logic;
+ CIN_10 : in std_logic;
+ CIN_9 : in std_logic;
+ CIN_8 : in std_logic;
+ CIN_7 : in std_logic;
+ CIN_6 : in std_logic;
+ CIN_5 : in std_logic;
+ CIN_4 : in std_logic;
+ CIN_3 : in std_logic;
+ CIN_2 : in std_logic;
+ CIN_1 : in std_logic;
+ CIN_0 : in std_logic;
+ TESTCLK_MACO : in std_logic
+);
+
+end PCSA;
+
+architecture PCSA_arch of PCSA is
+
+component PCSA_sim
+GENERIC(
+ CONFIG_FILE : String
+ );
+port (
+ HDINP0 : in std_logic;
+ HDINN0 : in std_logic;
+ HDINP1 : in std_logic;
+ HDINN1 : in std_logic;
+ HDINP2 : in std_logic;
+ HDINN2 : in std_logic;
+ HDINP3 : in std_logic;
+ HDINN3 : in std_logic;
+ HDOUTP0 : out std_logic;
+ HDOUTN0 : out std_logic;
+ HDOUTP1 : out std_logic;
+ HDOUTN1 : out std_logic;
+ HDOUTP2 : out std_logic;
+ HDOUTN2 : out std_logic;
+ HDOUTP3 : out std_logic;
+ HDOUTN3 : out std_logic;
+ REFCLKP : in std_logic;
+ REFCLKN : in std_logic;
+ RXREFCLKP : in std_logic;
+ RXREFCLKN : in std_logic;
+ FFC_QUAD_RST : in std_logic;
+ FFC_MACRO_RST : in std_logic;
+
+ FFC_LANE_TX_RST0 : in std_logic;
+ FFC_LANE_TX_RST1 : in std_logic;
+ FFC_LANE_TX_RST2 : in std_logic;
+ FFC_LANE_TX_RST3 : in std_logic;
+
+ FFC_LANE_RX_RST0 : in std_logic;
+ FFC_LANE_RX_RST1 : in std_logic;
+ FFC_LANE_RX_RST2 : in std_logic;
+ FFC_LANE_RX_RST3 : in std_logic;
+
+ FFC_PCIE_EI_EN_0 : in std_logic;
+ FFC_PCIE_EI_EN_1 : in std_logic;
+ FFC_PCIE_EI_EN_2 : in std_logic;
+ FFC_PCIE_EI_EN_3 : in std_logic;
+
+ FFC_PCIE_CT_0 : in std_logic;
+ FFC_PCIE_CT_1 : in std_logic;
+ FFC_PCIE_CT_2 : in std_logic;
+ FFC_PCIE_CT_3 : in std_logic;
+
+ FFS_PCIE_CON_0 : out std_logic;
+ FFS_PCIE_CON_1 : out std_logic;
+ FFS_PCIE_CON_2 : out std_logic;
+ FFS_PCIE_CON_3 : out std_logic;
+
+ FFS_PCIE_DONE_0 : out std_logic;
+ FFS_PCIE_DONE_1 : out std_logic;
+ FFS_PCIE_DONE_2 : out std_logic;
+ FFS_PCIE_DONE_3 : out std_logic;
+
+ FFC_PCIE_TX_0 : in std_logic;
+ FFC_PCIE_TX_1 : in std_logic;
+ FFC_PCIE_TX_2 : in std_logic;
+ FFC_PCIE_TX_3 : in std_logic;
+
+ FFC_PCIE_RX_0 : in std_logic;
+ FFC_PCIE_RX_1 : in std_logic;
+ FFC_PCIE_RX_2 : in std_logic;
+ FFC_PCIE_RX_3 : in std_logic;
+
+ FFC_SD_0 : in std_logic;
+ FFC_SD_1 : in std_logic;
+ FFC_SD_2 : in std_logic;
+ FFC_SD_3 : in std_logic;
+
+ FFC_EN_CGA_0 : in std_logic;
+ FFC_EN_CGA_1 : in std_logic;
+ FFC_EN_CGA_2 : in std_logic;
+ FFC_EN_CGA_3 : in std_logic;
+
+ FFC_ALIGN_EN_0 : in std_logic;
+ FFC_ALIGN_EN_1 : in std_logic;
+ FFC_ALIGN_EN_2 : in std_logic;
+ FFC_ALIGN_EN_3 : in std_logic;
+
+ FFC_AB_RESET : in std_logic;
+ FFC_CD_RESET : in std_logic;
+
+ FFS_LS_STATUS_0 : out std_logic;
+ FFS_LS_STATUS_1 : out std_logic;
+ FFS_LS_STATUS_2 : out std_logic;
+ FFS_LS_STATUS_3 : out std_logic;
+
+ FFS_AB_STATUS : out std_logic;
+ FFS_CD_STATUS : out std_logic;
+
+ FFS_AB_ALIGNED : out std_logic;
+ FFS_CD_ALIGNED : out std_logic;
+
+ FFS_AB_FAILED : out std_logic;
+ FFS_CD_FAILED : out std_logic;
+
+ FFS_RLOS_LO0 : out std_logic;
+ FFS_RLOS_LO1 : out std_logic;
+ FFS_RLOS_LO2 : out std_logic;
+ FFS_RLOS_LO3 : out std_logic;
+
+ FFC_FB_LB_0 : in std_logic;
+ FFC_FB_LB_1 : in std_logic;
+ FFC_FB_LB_2 : in std_logic;
+ FFC_FB_LB_3 : in std_logic;
+
+ FFC_SB_INV_RX_0 : in std_logic;
+ FFC_SB_INV_RX_1 : in std_logic;
+ FFC_SB_INV_RX_2 : in std_logic;
+ FFC_SB_INV_RX_3 : in std_logic;
+
+ FFS_CC_ORUN_0 : out std_logic;
+ FFS_CC_ORUN_1 : out std_logic;
+ FFS_CC_ORUN_2 : out std_logic;
+ FFS_CC_ORUN_3 : out std_logic;
+
+ FFS_CC_URUN_0 : out std_logic;
+ FFS_CC_URUN_1 : out std_logic;
+ FFS_CC_URUN_2 : out std_logic;
+ FFS_CC_URUN_3 : out std_logic;
+
+ FFC_CK_CORE_TX : in std_logic;
+ FFC_CK_CORE_RX : in std_logic;
+ RDATAO_7 : out std_logic;
+ RDATAO_6 : out std_logic;
+ RDATAO_5 : out std_logic;
+ RDATAO_4 : out std_logic;
+ RDATAO_3 : out std_logic;
+ RDATAO_2 : out std_logic;
+ RDATAO_1 : out std_logic;
+ RDATAO_0 : out std_logic;
+ INTO : out std_logic;
+
+ ADDRI_7 : in std_logic;
+ ADDRI_6 : in std_logic;
+ ADDRI_5 : in std_logic;
+ ADDRI_4 : in std_logic;
+ ADDRI_3 : in std_logic;
+ ADDRI_2 : in std_logic;
+ ADDRI_1 : in std_logic;
+ ADDRI_0 : in std_logic;
+ WDATAI_7 : in std_logic;
+ WDATAI_6 : in std_logic;
+ WDATAI_5 : in std_logic;
+ WDATAI_4 : in std_logic;
+ WDATAI_3 : in std_logic;
+ WDATAI_2 : in std_logic;
+ WDATAI_1 : in std_logic;
+ WDATAI_0 : in std_logic;
+ RDI : in std_logic;
+ WSTBI : in std_logic;
+
+ CS_CHIF_0 : in std_logic;
+ CS_CHIF_1 : in std_logic;
+ CS_CHIF_2 : in std_logic;
+ CS_CHIF_3 : in std_logic;
+ CS_QIF : in std_logic;
+
+ QUAD_ID_1 : in std_logic;
+ QUAD_ID_0 : in std_logic;
+
+ FF_SYSCLK_P1 : out std_logic;
+
+ FF_SYSCLK0 : out std_logic;
+ FF_SYSCLK1 : out std_logic;
+ FF_SYSCLK2 : out std_logic;
+ FF_SYSCLK3 : out std_logic;
+
+ FF_RXCLK_P1 : out std_logic;
+ FF_RXCLK_P2 : out std_logic;
+
+ FF_RXCLK0 : out std_logic;
+ FF_RXCLK1 : out std_logic;
+ FF_RXCLK2 : out std_logic;
+ FF_RXCLK3 : out std_logic;
+
+ QUAD_CLK : out std_logic;
+
+ GRP_CLK_P1_3 : in std_logic;
+ GRP_CLK_P1_2 : in std_logic;
+ GRP_CLK_P1_1 : in std_logic;
+ GRP_CLK_P1_0 : in std_logic;
+
+ GRP_CLK_P2_3 : in std_logic;
+ GRP_CLK_P2_2 : in std_logic;
+ GRP_CLK_P2_1 : in std_logic;
+ GRP_CLK_P2_0 : in std_logic;
+
+ GRP_START_3 : in std_logic;
+ GRP_START_2 : in std_logic;
+ GRP_START_1 : in std_logic;
+ GRP_START_0 : in std_logic;
+
+ GRP_DONE_3 : in std_logic;
+ GRP_DONE_2 : in std_logic;
+ GRP_DONE_1 : in std_logic;
+ GRP_DONE_0 : in std_logic;
+
+ GRP_DESKEW_ERROR_3 : in std_logic;
+ GRP_DESKEW_ERROR_2 : in std_logic;
+ GRP_DESKEW_ERROR_1 : in std_logic;
+ GRP_DESKEW_ERROR_0 : in std_logic;
+
+ IQA_START_LS : out std_logic;
+ IQA_DONE_LS : out std_logic;
+ IQA_AND_FP1_LS : out std_logic;
+ IQA_AND_FP0_LS : out std_logic;
+ IQA_OR_FP1_LS : out std_logic;
+ IQA_OR_FP0_LS : out std_logic;
+ IQA_RST_N : out std_logic;
+
+ FF_TCLK0 : in std_logic;
+ FF_TCLK1 : in std_logic;
+ FF_TCLK2 : in std_logic;
+ FF_TCLK3 : in std_logic;
+
+ FF_RCLK0 : in std_logic;
+ FF_RCLK1 : in std_logic;
+ FF_RCLK2 : in std_logic;
+ FF_RCLK3 : in std_logic;
+ TCK_FMACP : in std_logic;
+
+ FF_TXD_0_23 : in std_logic;
+ FF_TXD_0_22 : in std_logic;
+ FF_TXD_0_21 : in std_logic;
+ FF_TXD_0_20 : in std_logic;
+ FF_TXD_0_19 : in std_logic;
+ FF_TXD_0_18 : in std_logic;
+ FF_TXD_0_17 : in std_logic;
+ FF_TXD_0_16 : in std_logic;
+ FF_TXD_0_15 : in std_logic;
+ FF_TXD_0_14 : in std_logic;
+ FF_TXD_0_13 : in std_logic;
+ FF_TXD_0_12 : in std_logic;
+ FF_TXD_0_11 : in std_logic;
+ FF_TXD_0_10 : in std_logic;
+ FF_TXD_0_9 : in std_logic;
+ FF_TXD_0_8 : in std_logic;
+ FF_TXD_0_7 : in std_logic;
+ FF_TXD_0_6 : in std_logic;
+ FF_TXD_0_5 : in std_logic;
+ FF_TXD_0_4 : in std_logic;
+ FF_TXD_0_3 : in std_logic;
+ FF_TXD_0_2 : in std_logic;
+ FF_TXD_0_1 : in std_logic;
+ FF_TXD_0_0 : in std_logic;
+ FB_RXD_0_23 : out std_logic;
+ FB_RXD_0_22 : out std_logic;
+ FB_RXD_0_21 : out std_logic;
+ FB_RXD_0_20 : out std_logic;
+ FB_RXD_0_19 : out std_logic;
+ FB_RXD_0_18 : out std_logic;
+ FB_RXD_0_17 : out std_logic;
+ FB_RXD_0_16 : out std_logic;
+ FB_RXD_0_15 : out std_logic;
+ FB_RXD_0_14 : out std_logic;
+ FB_RXD_0_13 : out std_logic;
+ FB_RXD_0_12 : out std_logic;
+ FB_RXD_0_11 : out std_logic;
+ FB_RXD_0_10 : out std_logic;
+ FB_RXD_0_9 : out std_logic;
+ FB_RXD_0_8 : out std_logic;
+ FB_RXD_0_7 : out std_logic;
+ FB_RXD_0_6 : out std_logic;
+ FB_RXD_0_5 : out std_logic;
+ FB_RXD_0_4 : out std_logic;
+ FB_RXD_0_3 : out std_logic;
+ FB_RXD_0_2 : out std_logic;
+ FB_RXD_0_1 : out std_logic;
+ FB_RXD_0_0 : out std_logic;
+ FF_TXD_1_23 : in std_logic;
+ FF_TXD_1_22 : in std_logic;
+ FF_TXD_1_21 : in std_logic;
+ FF_TXD_1_20 : in std_logic;
+ FF_TXD_1_19 : in std_logic;
+ FF_TXD_1_18 : in std_logic;
+ FF_TXD_1_17 : in std_logic;
+ FF_TXD_1_16 : in std_logic;
+ FF_TXD_1_15 : in std_logic;
+ FF_TXD_1_14 : in std_logic;
+ FF_TXD_1_13 : in std_logic;
+ FF_TXD_1_12 : in std_logic;
+ FF_TXD_1_11 : in std_logic;
+ FF_TXD_1_10 : in std_logic;
+ FF_TXD_1_9 : in std_logic;
+ FF_TXD_1_8 : in std_logic;
+ FF_TXD_1_7 : in std_logic;
+ FF_TXD_1_6 : in std_logic;
+ FF_TXD_1_5 : in std_logic;
+ FF_TXD_1_4 : in std_logic;
+ FF_TXD_1_3 : in std_logic;
+ FF_TXD_1_2 : in std_logic;
+ FF_TXD_1_1 : in std_logic;
+ FF_TXD_1_0 : in std_logic;
+ FB_RXD_1_23 : out std_logic;
+ FB_RXD_1_22 : out std_logic;
+ FB_RXD_1_21 : out std_logic;
+ FB_RXD_1_20 : out std_logic;
+ FB_RXD_1_19 : out std_logic;
+ FB_RXD_1_18 : out std_logic;
+ FB_RXD_1_17 : out std_logic;
+ FB_RXD_1_16 : out std_logic;
+ FB_RXD_1_15 : out std_logic;
+ FB_RXD_1_14 : out std_logic;
+ FB_RXD_1_13 : out std_logic;
+ FB_RXD_1_12 : out std_logic;
+ FB_RXD_1_11 : out std_logic;
+ FB_RXD_1_10 : out std_logic;
+ FB_RXD_1_9 : out std_logic;
+ FB_RXD_1_8 : out std_logic;
+ FB_RXD_1_7 : out std_logic;
+ FB_RXD_1_6 : out std_logic;
+ FB_RXD_1_5 : out std_logic;
+ FB_RXD_1_4 : out std_logic;
+ FB_RXD_1_3 : out std_logic;
+ FB_RXD_1_2 : out std_logic;
+ FB_RXD_1_1 : out std_logic;
+ FB_RXD_1_0 : out std_logic;
+ FF_TXD_2_23 : in std_logic;
+ FF_TXD_2_22 : in std_logic;
+ FF_TXD_2_21 : in std_logic;
+ FF_TXD_2_20 : in std_logic;
+ FF_TXD_2_19 : in std_logic;
+ FF_TXD_2_18 : in std_logic;
+ FF_TXD_2_17 : in std_logic;
+ FF_TXD_2_16 : in std_logic;
+ FF_TXD_2_15 : in std_logic;
+ FF_TXD_2_14 : in std_logic;
+ FF_TXD_2_13 : in std_logic;
+ FF_TXD_2_12 : in std_logic;
+ FF_TXD_2_11 : in std_logic;
+ FF_TXD_2_10 : in std_logic;
+ FF_TXD_2_9 : in std_logic;
+ FF_TXD_2_8 : in std_logic;
+ FF_TXD_2_7 : in std_logic;
+ FF_TXD_2_6 : in std_logic;
+ FF_TXD_2_5 : in std_logic;
+ FF_TXD_2_4 : in std_logic;
+ FF_TXD_2_3 : in std_logic;
+ FF_TXD_2_2 : in std_logic;
+ FF_TXD_2_1 : in std_logic;
+ FF_TXD_2_0 : in std_logic;
+ FB_RXD_2_23 : out std_logic;
+ FB_RXD_2_22 : out std_logic;
+ FB_RXD_2_21 : out std_logic;
+ FB_RXD_2_20 : out std_logic;
+ FB_RXD_2_19 : out std_logic;
+ FB_RXD_2_18 : out std_logic;
+ FB_RXD_2_17 : out std_logic;
+ FB_RXD_2_16 : out std_logic;
+ FB_RXD_2_15 : out std_logic;
+ FB_RXD_2_14 : out std_logic;
+ FB_RXD_2_13 : out std_logic;
+ FB_RXD_2_12 : out std_logic;
+ FB_RXD_2_11 : out std_logic;
+ FB_RXD_2_10 : out std_logic;
+ FB_RXD_2_9 : out std_logic;
+ FB_RXD_2_8 : out std_logic;
+ FB_RXD_2_7 : out std_logic;
+ FB_RXD_2_6 : out std_logic;
+ FB_RXD_2_5 : out std_logic;
+ FB_RXD_2_4 : out std_logic;
+ FB_RXD_2_3 : out std_logic;
+ FB_RXD_2_2 : out std_logic;
+ FB_RXD_2_1 : out std_logic;
+ FB_RXD_2_0 : out std_logic;
+ FF_TXD_3_23 : in std_logic;
+ FF_TXD_3_22 : in std_logic;
+ FF_TXD_3_21 : in std_logic;
+ FF_TXD_3_20 : in std_logic;
+ FF_TXD_3_19 : in std_logic;
+ FF_TXD_3_18 : in std_logic;
+ FF_TXD_3_17 : in std_logic;
+ FF_TXD_3_16 : in std_logic;
+ FF_TXD_3_15 : in std_logic;
+ FF_TXD_3_14 : in std_logic;
+ FF_TXD_3_13 : in std_logic;
+ FF_TXD_3_12 : in std_logic;
+ FF_TXD_3_11 : in std_logic;
+ FF_TXD_3_10 : in std_logic;
+ FF_TXD_3_9 : in std_logic;
+ FF_TXD_3_8 : in std_logic;
+ FF_TXD_3_7 : in std_logic;
+ FF_TXD_3_6 : in std_logic;
+ FF_TXD_3_5 : in std_logic;
+ FF_TXD_3_4 : in std_logic;
+ FF_TXD_3_3 : in std_logic;
+ FF_TXD_3_2 : in std_logic;
+ FF_TXD_3_1 : in std_logic;
+ FF_TXD_3_0 : in std_logic;
+ FB_RXD_3_23 : out std_logic;
+ FB_RXD_3_22 : out std_logic;
+ FB_RXD_3_21 : out std_logic;
+ FB_RXD_3_20 : out std_logic;
+ FB_RXD_3_19 : out std_logic;
+ FB_RXD_3_18 : out std_logic;
+ FB_RXD_3_17 : out std_logic;
+ FB_RXD_3_16 : out std_logic;
+ FB_RXD_3_15 : out std_logic;
+ FB_RXD_3_14 : out std_logic;
+ FB_RXD_3_13 : out std_logic;
+ FB_RXD_3_12 : out std_logic;
+ FB_RXD_3_11 : out std_logic;
+ FB_RXD_3_10 : out std_logic;
+ FB_RXD_3_9 : out std_logic;
+ FB_RXD_3_8 : out std_logic;
+ FB_RXD_3_7 : out std_logic;
+ FB_RXD_3_6 : out std_logic;
+ FB_RXD_3_5 : out std_logic;
+ FB_RXD_3_4 : out std_logic;
+ FB_RXD_3_3 : out std_logic;
+ FB_RXD_3_2 : out std_logic;
+ FB_RXD_3_1 : out std_logic;
+ FB_RXD_3_0 : out std_logic;
+ TCK_FMAC : out std_logic;
+ BS4PAD_0 : out std_logic;
+ BS4PAD_1 : out std_logic;
+ BS4PAD_2 : out std_logic;
+ BS4PAD_3 : out std_logic;
+ COUT_21 : out std_logic;
+ COUT_20 : out std_logic;
+ COUT_19 : out std_logic;
+ COUT_18 : out std_logic;
+ COUT_17 : out std_logic;
+ COUT_16 : out std_logic;
+ COUT_15 : out std_logic;
+ COUT_14 : out std_logic;
+ COUT_13 : out std_logic;
+ COUT_12 : out std_logic;
+ COUT_11 : out std_logic;
+ COUT_10 : out std_logic;
+ COUT_9 : out std_logic;
+ COUT_8 : out std_logic;
+ COUT_7 : out std_logic;
+ COUT_6 : out std_logic;
+ COUT_5 : out std_logic;
+ COUT_4 : out std_logic;
+ COUT_3 : out std_logic;
+ COUT_2 : out std_logic;
+ COUT_1 : out std_logic;
+ COUT_0 : out std_logic;
+ CIN_12 : in std_logic;
+ CIN_11 : in std_logic;
+ CIN_10 : in std_logic;
+ CIN_9 : in std_logic;
+ CIN_8 : in std_logic;
+ CIN_7 : in std_logic;
+ CIN_6 : in std_logic;
+ CIN_5 : in std_logic;
+ CIN_4 : in std_logic;
+ CIN_3 : in std_logic;
+ CIN_2 : in std_logic;
+ CIN_1 : in std_logic;
+ CIN_0 : in std_logic;
+ TESTCLK_MACO : in std_logic
+);
+end component;
+
+begin
+
+PCSA_sim_inst : PCSA_sim
+generic map (
+ CONFIG_FILE => CONFIG_FILE)
+port map (
+ HDINP0 => HDINP0,
+ HDINN0 => HDINN0,
+ HDINP1 => HDINP1,
+ HDINN1 => HDINN1,
+ HDINP2 => HDINP2,
+ HDINN2 => HDINN2,
+ HDINP3 => HDINP3,
+ HDINN3 => HDINN3,
+ HDOUTP0 => HDOUTP0,
+ HDOUTN0 => HDOUTN0,
+ HDOUTP1 => HDOUTP1,
+ HDOUTN1 => HDOUTN1,
+ HDOUTP2 => HDOUTP2,
+ HDOUTN2 => HDOUTN2,
+ HDOUTP3 => HDOUTP3,
+ HDOUTN3 => HDOUTN3,
+ REFCLKP => REFCLKP,
+ REFCLKN => REFCLKN,
+ RXREFCLKP => RXREFCLKP,
+ RXREFCLKN => RXREFCLKN,
+ FFC_QUAD_RST => FFC_QUAD_RST,
+ FFC_MACRO_RST => FFC_MACRO_RST,
+ FFC_LANE_TX_RST0 => FFC_LANE_TX_RST0,
+ FFC_LANE_TX_RST1 => FFC_LANE_TX_RST1,
+ FFC_LANE_TX_RST2 => FFC_LANE_TX_RST2,
+ FFC_LANE_TX_RST3 => FFC_LANE_TX_RST3,
+ FFC_LANE_RX_RST0 => FFC_LANE_RX_RST0,
+ FFC_LANE_RX_RST1 => FFC_LANE_RX_RST1,
+ FFC_LANE_RX_RST2 => FFC_LANE_RX_RST2,
+ FFC_LANE_RX_RST3 => FFC_LANE_RX_RST3,
+ FFC_PCIE_EI_EN_0 => FFC_PCIE_EI_EN_0,
+ FFC_PCIE_EI_EN_1 => FFC_PCIE_EI_EN_1,
+ FFC_PCIE_EI_EN_2 => FFC_PCIE_EI_EN_2,
+ FFC_PCIE_EI_EN_3 => FFC_PCIE_EI_EN_3,
+ FFC_PCIE_CT_0 => FFC_PCIE_CT_0,
+ FFC_PCIE_CT_1 => FFC_PCIE_CT_1,
+ FFC_PCIE_CT_2 => FFC_PCIE_CT_2,
+ FFC_PCIE_CT_3 => FFC_PCIE_CT_3,
+ FFS_PCIE_CON_0 => FFS_PCIE_CON_0,
+ FFS_PCIE_CON_1 => FFS_PCIE_CON_1,
+ FFS_PCIE_CON_2 => FFS_PCIE_CON_2,
+ FFS_PCIE_CON_3 => FFS_PCIE_CON_3,
+ FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,
+ FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,
+ FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,
+ FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,
+ FFC_PCIE_TX_0 => FFC_PCIE_TX_0,
+ FFC_PCIE_TX_1 => FFC_PCIE_TX_1,
+ FFC_PCIE_TX_2 => FFC_PCIE_TX_2,
+ FFC_PCIE_TX_3 => FFC_PCIE_TX_3,
+ FFC_PCIE_RX_0 => FFC_PCIE_RX_0,
+ FFC_PCIE_RX_1 => FFC_PCIE_RX_1,
+ FFC_PCIE_RX_2 => FFC_PCIE_RX_2,
+ FFC_PCIE_RX_3 => FFC_PCIE_RX_3,
+ FFC_SD_0 => FFC_SD_0,
+ FFC_SD_1 => FFC_SD_1,
+ FFC_SD_2 => FFC_SD_2,
+ FFC_SD_3 => FFC_SD_3,
+ FFC_EN_CGA_0 => FFC_EN_CGA_0,
+ FFC_EN_CGA_1 => FFC_EN_CGA_1,
+ FFC_EN_CGA_2 => FFC_EN_CGA_2,
+ FFC_EN_CGA_3 => FFC_EN_CGA_3,
+ FFC_ALIGN_EN_0 => FFC_ALIGN_EN_0,
+ FFC_ALIGN_EN_1 => FFC_ALIGN_EN_1,
+ FFC_ALIGN_EN_2 => FFC_ALIGN_EN_2,
+ FFC_ALIGN_EN_3 => FFC_ALIGN_EN_3,
+ FFC_AB_RESET => FFC_AB_RESET,
+ FFC_CD_RESET => FFC_CD_RESET,
+ FFS_LS_STATUS_0 => FFS_LS_STATUS_0,
+ FFS_LS_STATUS_1 => FFS_LS_STATUS_1,
+ FFS_LS_STATUS_2 => FFS_LS_STATUS_2,
+ FFS_LS_STATUS_3 => FFS_LS_STATUS_3,
+ FFS_AB_STATUS => FFS_AB_STATUS,
+ FFS_CD_STATUS => FFS_CD_STATUS,
+ FFS_AB_ALIGNED => FFS_AB_ALIGNED,
+ FFS_CD_ALIGNED => FFS_CD_ALIGNED,
+ FFS_AB_FAILED => FFS_AB_FAILED,
+ FFS_CD_FAILED => FFS_CD_FAILED,
+ FFS_RLOS_LO0 => FFS_RLOS_LO0,
+ FFS_RLOS_LO1 => FFS_RLOS_LO1,
+ FFS_RLOS_LO2 => FFS_RLOS_LO2,
+ FFS_RLOS_LO3 => FFS_RLOS_LO3,
+ FFC_FB_LB_0 => FFC_FB_LB_0,
+ FFC_FB_LB_1 => FFC_FB_LB_1,
+ FFC_FB_LB_2 => FFC_FB_LB_2,
+ FFC_FB_LB_3 => FFC_FB_LB_3,
+ FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,
+ FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,
+ FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,
+ FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,
+ FFS_CC_ORUN_0 => FFS_CC_ORUN_0,
+ FFS_CC_ORUN_1 => FFS_CC_ORUN_1,
+ FFS_CC_ORUN_2 => FFS_CC_ORUN_2,
+ FFS_CC_ORUN_3 => FFS_CC_ORUN_3,
+ FFS_CC_URUN_0 => FFS_CC_URUN_0,
+ FFS_CC_URUN_1 => FFS_CC_URUN_1,
+ FFS_CC_URUN_2 => FFS_CC_URUN_2,
+ FFS_CC_URUN_3 => FFS_CC_URUN_3,
+ FFC_CK_CORE_TX => FFC_CK_CORE_TX,
+ FFC_CK_CORE_RX => FFC_CK_CORE_RX,
+ BS4PAD_0 => BS4PAD_0,
+ BS4PAD_1 => BS4PAD_1,
+ BS4PAD_2 => BS4PAD_2,
+ BS4PAD_3 => BS4PAD_3,
+ RDATAO_7 => RDATAO_7,
+ RDATAO_6 => RDATAO_6,
+ RDATAO_5 => RDATAO_5,
+ RDATAO_4 => RDATAO_4,
+ RDATAO_3 => RDATAO_3,
+ RDATAO_2 => RDATAO_2,
+ RDATAO_1 => RDATAO_1,
+ RDATAO_0 => RDATAO_0,
+ INTO => INTO,
+ ADDRI_7 => ADDRI_7,
+ ADDRI_6 => ADDRI_6,
+ ADDRI_5 => ADDRI_5,
+ ADDRI_4 => ADDRI_4,
+ ADDRI_3 => ADDRI_3,
+ ADDRI_2 => ADDRI_2,
+ ADDRI_1 => ADDRI_1,
+ ADDRI_0 => ADDRI_0,
+ WDATAI_7 => WDATAI_7,
+ WDATAI_6 => WDATAI_6,
+ WDATAI_5 => WDATAI_5,
+ WDATAI_4 => WDATAI_4,
+ WDATAI_3 => WDATAI_3,
+ WDATAI_2 => WDATAI_2,
+ WDATAI_1 => WDATAI_1,
+ WDATAI_0 => WDATAI_0,
+ RDI => RDI,
+ WSTBI => WSTBI,
+ CS_CHIF_0 => CS_CHIF_0,
+ CS_CHIF_1 => CS_CHIF_1,
+ CS_CHIF_2 => CS_CHIF_2,
+ CS_CHIF_3 => CS_CHIF_3,
+ CS_QIF => CS_QIF,
+ QUAD_ID_1 => QUAD_ID_1,
+ QUAD_ID_0 => QUAD_ID_0,
+ FF_SYSCLK_P1 => FF_SYSCLK_P1,
+ FF_SYSCLK0 => FF_SYSCLK0,
+ FF_SYSCLK1 => FF_SYSCLK1,
+ FF_SYSCLK2 => FF_SYSCLK2,
+ FF_SYSCLK3 => FF_SYSCLK3,
+ FF_RXCLK_P1 => FF_RXCLK_P1,
+ FF_RXCLK_P2 => FF_RXCLK_P2,
+ FF_RXCLK0 => FF_RXCLK0,
+ FF_RXCLK1 => FF_RXCLK1,
+ FF_RXCLK2 => FF_RXCLK2,
+ FF_RXCLK3 => FF_RXCLK3,
+ QUAD_CLK => QUAD_CLK,
+ GRP_CLK_P1_3 => GRP_CLK_P1_3,
+ GRP_CLK_P1_2 => GRP_CLK_P1_2,
+ GRP_CLK_P1_1 => GRP_CLK_P1_1,
+ GRP_CLK_P1_0 => GRP_CLK_P1_0,
+ GRP_CLK_P2_3 => GRP_CLK_P2_3,
+ GRP_CLK_P2_2 => GRP_CLK_P2_2,
+ GRP_CLK_P2_1 => GRP_CLK_P2_1,
+ GRP_CLK_P2_0 => GRP_CLK_P2_0,
+ GRP_START_3 => GRP_START_3,
+ GRP_START_2 => GRP_START_2,
+ GRP_START_1 => GRP_START_1,
+ GRP_START_0 => GRP_START_0,
+ GRP_DONE_3 => GRP_DONE_3,
+ GRP_DONE_2 => GRP_DONE_2,
+ GRP_DONE_1 => GRP_DONE_1,
+ GRP_DONE_0 => GRP_DONE_0,
+ GRP_DESKEW_ERROR_3 => GRP_DESKEW_ERROR_3,
+ GRP_DESKEW_ERROR_2 => GRP_DESKEW_ERROR_2,
+ GRP_DESKEW_ERROR_1 => GRP_DESKEW_ERROR_1,
+ GRP_DESKEW_ERROR_0 => GRP_DESKEW_ERROR_0,
+ IQA_START_LS => IQA_START_LS,
+ IQA_DONE_LS => IQA_DONE_LS,
+ IQA_AND_FP1_LS => IQA_AND_FP1_LS,
+ IQA_AND_FP0_LS => IQA_AND_FP0_LS,
+ IQA_OR_FP1_LS => IQA_OR_FP1_LS,
+ IQA_OR_FP0_LS => IQA_OR_FP0_LS,
+ IQA_RST_N => IQA_RST_N,
+ FF_TCLK0 => FF_TCLK0,
+ FF_TCLK1 => FF_TCLK1,
+ FF_TCLK2 => FF_TCLK2,
+ FF_TCLK3 => FF_TCLK3,
+ FF_RCLK0 => FF_RCLK0,
+ FF_RCLK1 => FF_RCLK1,
+ FF_RCLK2 => FF_RCLK2,
+ FF_RCLK3 => FF_RCLK3,
+ TCK_FMACP => TCK_FMACP,
+ FF_TXD_0_23 => FF_TXD_0_23,
+ FF_TXD_0_22 => FF_TXD_0_22,
+ FF_TXD_0_21 => FF_TXD_0_21,
+ FF_TXD_0_20 => FF_TXD_0_20,
+ FF_TXD_0_19 => FF_TXD_0_19,
+ FF_TXD_0_18 => FF_TXD_0_18,
+ FF_TXD_0_17 => FF_TXD_0_17,
+ FF_TXD_0_16 => FF_TXD_0_16,
+ FF_TXD_0_15 => FF_TXD_0_15,
+ FF_TXD_0_14 => FF_TXD_0_14,
+ FF_TXD_0_13 => FF_TXD_0_13,
+ FF_TXD_0_12 => FF_TXD_0_12,
+ FF_TXD_0_11 => FF_TXD_0_11,
+ FF_TXD_0_10 => FF_TXD_0_10,
+ FF_TXD_0_9 => FF_TXD_0_9,
+ FF_TXD_0_8 => FF_TXD_0_8,
+ FF_TXD_0_7 => FF_TXD_0_7,
+ FF_TXD_0_6 => FF_TXD_0_6,
+ FF_TXD_0_5 => FF_TXD_0_5,
+ FF_TXD_0_4 => FF_TXD_0_4,
+ FF_TXD_0_3 => FF_TXD_0_3,
+ FF_TXD_0_2 => FF_TXD_0_2,
+ FF_TXD_0_1 => FF_TXD_0_1,
+ FF_TXD_0_0 => FF_TXD_0_0,
+ FB_RXD_0_23 => FB_RXD_0_23,
+ FB_RXD_0_22 => FB_RXD_0_22,
+ FB_RXD_0_21 => FB_RXD_0_21,
+ FB_RXD_0_20 => FB_RXD_0_20,
+ FB_RXD_0_19 => FB_RXD_0_19,
+ FB_RXD_0_18 => FB_RXD_0_18,
+ FB_RXD_0_17 => FB_RXD_0_17,
+ FB_RXD_0_16 => FB_RXD_0_16,
+ FB_RXD_0_15 => FB_RXD_0_15,
+ FB_RXD_0_14 => FB_RXD_0_14,
+ FB_RXD_0_13 => FB_RXD_0_13,
+ FB_RXD_0_12 => FB_RXD_0_12,
+ FB_RXD_0_11 => FB_RXD_0_11,
+ FB_RXD_0_10 => FB_RXD_0_10,
+ FB_RXD_0_9 => FB_RXD_0_9,
+ FB_RXD_0_8 => FB_RXD_0_8,
+ FB_RXD_0_7 => FB_RXD_0_7,
+ FB_RXD_0_6 => FB_RXD_0_6,
+ FB_RXD_0_5 => FB_RXD_0_5,
+ FB_RXD_0_4 => FB_RXD_0_4,
+ FB_RXD_0_3 => FB_RXD_0_3,
+ FB_RXD_0_2 => FB_RXD_0_2,
+ FB_RXD_0_1 => FB_RXD_0_1,
+ FB_RXD_0_0 => FB_RXD_0_0,
+ FF_TXD_1_23 => FF_TXD_1_23,
+ FF_TXD_1_22 => FF_TXD_1_22,
+ FF_TXD_1_21 => FF_TXD_1_21,
+ FF_TXD_1_20 => FF_TXD_1_20,
+ FF_TXD_1_19 => FF_TXD_1_19,
+ FF_TXD_1_18 => FF_TXD_1_18,
+ FF_TXD_1_17 => FF_TXD_1_17,
+ FF_TXD_1_16 => FF_TXD_1_16,
+ FF_TXD_1_15 => FF_TXD_1_15,
+ FF_TXD_1_14 => FF_TXD_1_14,
+ FF_TXD_1_13 => FF_TXD_1_13,
+ FF_TXD_1_12 => FF_TXD_1_12,
+ FF_TXD_1_11 => FF_TXD_1_11,
+ FF_TXD_1_10 => FF_TXD_1_10,
+ FF_TXD_1_9 => FF_TXD_1_9,
+ FF_TXD_1_8 => FF_TXD_1_8,
+ FF_TXD_1_7 => FF_TXD_1_7,
+ FF_TXD_1_6 => FF_TXD_1_6,
+ FF_TXD_1_5 => FF_TXD_1_5,
+ FF_TXD_1_4 => FF_TXD_1_4,
+ FF_TXD_1_3 => FF_TXD_1_3,
+ FF_TXD_1_2 => FF_TXD_1_2,
+ FF_TXD_1_1 => FF_TXD_1_1,
+ FF_TXD_1_0 => FF_TXD_1_0,
+ FB_RXD_1_23 => FB_RXD_1_23,
+ FB_RXD_1_22 => FB_RXD_1_22,
+ FB_RXD_1_21 => FB_RXD_1_21,
+ FB_RXD_1_20 => FB_RXD_1_20,
+ FB_RXD_1_19 => FB_RXD_1_19,
+ FB_RXD_1_18 => FB_RXD_1_18,
+ FB_RXD_1_17 => FB_RXD_1_17,
+ FB_RXD_1_16 => FB_RXD_1_16,
+ FB_RXD_1_15 => FB_RXD_1_15,
+ FB_RXD_1_14 => FB_RXD_1_14,
+ FB_RXD_1_13 => FB_RXD_1_13,
+ FB_RXD_1_12 => FB_RXD_1_12,
+ FB_RXD_1_11 => FB_RXD_1_11,
+ FB_RXD_1_10 => FB_RXD_1_10,
+ FB_RXD_1_9 => FB_RXD_1_9,
+ FB_RXD_1_8 => FB_RXD_1_8,
+ FB_RXD_1_7 => FB_RXD_1_7,
+ FB_RXD_1_6 => FB_RXD_1_6,
+ FB_RXD_1_5 => FB_RXD_1_5,
+ FB_RXD_1_4 => FB_RXD_1_4,
+ FB_RXD_1_3 => FB_RXD_1_3,
+ FB_RXD_1_2 => FB_RXD_1_2,
+ FB_RXD_1_1 => FB_RXD_1_1,
+ FB_RXD_1_0 => FB_RXD_1_0,
+ FF_TXD_2_23 => FF_TXD_2_23,
+ FF_TXD_2_22 => FF_TXD_2_22,
+ FF_TXD_2_21 => FF_TXD_2_21,
+ FF_TXD_2_20 => FF_TXD_2_20,
+ FF_TXD_2_19 => FF_TXD_2_19,
+ FF_TXD_2_18 => FF_TXD_2_18,
+ FF_TXD_2_17 => FF_TXD_2_17,
+ FF_TXD_2_16 => FF_TXD_2_16,
+ FF_TXD_2_15 => FF_TXD_2_15,
+ FF_TXD_2_14 => FF_TXD_2_14,
+ FF_TXD_2_13 => FF_TXD_2_13,
+ FF_TXD_2_12 => FF_TXD_2_12,
+ FF_TXD_2_11 => FF_TXD_2_11,
+ FF_TXD_2_10 => FF_TXD_2_10,
+ FF_TXD_2_9 => FF_TXD_2_9,
+ FF_TXD_2_8 => FF_TXD_2_8,
+ FF_TXD_2_7 => FF_TXD_2_7,
+ FF_TXD_2_6 => FF_TXD_2_6,
+ FF_TXD_2_5 => FF_TXD_2_5,
+ FF_TXD_2_4 => FF_TXD_2_4,
+ FF_TXD_2_3 => FF_TXD_2_3,
+ FF_TXD_2_2 => FF_TXD_2_2,
+ FF_TXD_2_1 => FF_TXD_2_1,
+ FF_TXD_2_0 => FF_TXD_2_0,
+ FB_RXD_2_23 => FB_RXD_2_23,
+ FB_RXD_2_22 => FB_RXD_2_22,
+ FB_RXD_2_21 => FB_RXD_2_21,
+ FB_RXD_2_20 => FB_RXD_2_20,
+ FB_RXD_2_19 => FB_RXD_2_19,
+ FB_RXD_2_18 => FB_RXD_2_18,
+ FB_RXD_2_17 => FB_RXD_2_17,
+ FB_RXD_2_16 => FB_RXD_2_16,
+ FB_RXD_2_15 => FB_RXD_2_15,
+ FB_RXD_2_14 => FB_RXD_2_14,
+ FB_RXD_2_13 => FB_RXD_2_13,
+ FB_RXD_2_12 => FB_RXD_2_12,
+ FB_RXD_2_11 => FB_RXD_2_11,
+ FB_RXD_2_10 => FB_RXD_2_10,
+ FB_RXD_2_9 => FB_RXD_2_9,
+ FB_RXD_2_8 => FB_RXD_2_8,
+ FB_RXD_2_7 => FB_RXD_2_7,
+ FB_RXD_2_6 => FB_RXD_2_6,
+ FB_RXD_2_5 => FB_RXD_2_5,
+ FB_RXD_2_4 => FB_RXD_2_4,
+ FB_RXD_2_3 => FB_RXD_2_3,
+ FB_RXD_2_2 => FB_RXD_2_2,
+ FB_RXD_2_1 => FB_RXD_2_1,
+ FB_RXD_2_0 => FB_RXD_2_0,
+ FF_TXD_3_23 => FF_TXD_3_23,
+ FF_TXD_3_22 => FF_TXD_3_22,
+ FF_TXD_3_21 => FF_TXD_3_21,
+ FF_TXD_3_20 => FF_TXD_3_20,
+ FF_TXD_3_19 => FF_TXD_3_19,
+ FF_TXD_3_18 => FF_TXD_3_18,
+ FF_TXD_3_17 => FF_TXD_3_17,
+ FF_TXD_3_16 => FF_TXD_3_16,
+ FF_TXD_3_15 => FF_TXD_3_15,
+ FF_TXD_3_14 => FF_TXD_3_14,
+ FF_TXD_3_13 => FF_TXD_3_13,
+ FF_TXD_3_12 => FF_TXD_3_12,
+ FF_TXD_3_11 => FF_TXD_3_11,
+ FF_TXD_3_10 => FF_TXD_3_10,
+ FF_TXD_3_9 => FF_TXD_3_9,
+ FF_TXD_3_8 => FF_TXD_3_8,
+ FF_TXD_3_7 => FF_TXD_3_7,
+ FF_TXD_3_6 => FF_TXD_3_6,
+ FF_TXD_3_5 => FF_TXD_3_5,
+ FF_TXD_3_4 => FF_TXD_3_4,
+ FF_TXD_3_3 => FF_TXD_3_3,
+ FF_TXD_3_2 => FF_TXD_3_2,
+ FF_TXD_3_1 => FF_TXD_3_1,
+ FF_TXD_3_0 => FF_TXD_3_0,
+ FB_RXD_3_23 => FB_RXD_3_23,
+ FB_RXD_3_22 => FB_RXD_3_22,
+ FB_RXD_3_21 => FB_RXD_3_21,
+ FB_RXD_3_20 => FB_RXD_3_20,
+ FB_RXD_3_19 => FB_RXD_3_19,
+ FB_RXD_3_18 => FB_RXD_3_18,
+ FB_RXD_3_17 => FB_RXD_3_17,
+ FB_RXD_3_16 => FB_RXD_3_16,
+ FB_RXD_3_15 => FB_RXD_3_15,
+ FB_RXD_3_14 => FB_RXD_3_14,
+ FB_RXD_3_13 => FB_RXD_3_13,
+ FB_RXD_3_12 => FB_RXD_3_12,
+ FB_RXD_3_11 => FB_RXD_3_11,
+ FB_RXD_3_10 => FB_RXD_3_10,
+ FB_RXD_3_9 => FB_RXD_3_9,
+ FB_RXD_3_8 => FB_RXD_3_8,
+ FB_RXD_3_7 => FB_RXD_3_7,
+ FB_RXD_3_6 => FB_RXD_3_6,
+ FB_RXD_3_5 => FB_RXD_3_5,
+ FB_RXD_3_4 => FB_RXD_3_4,
+ FB_RXD_3_3 => FB_RXD_3_3,
+ FB_RXD_3_2 => FB_RXD_3_2,
+ FB_RXD_3_1 => FB_RXD_3_1,
+ FB_RXD_3_0 => FB_RXD_3_0,
+ TCK_FMAC => TCK_FMAC,
+ COUT_21 => COUT_21,
+ COUT_20 => COUT_20,
+ COUT_19 => COUT_19,
+ COUT_18 => COUT_18,
+ COUT_17 => COUT_17,
+ COUT_16 => COUT_16,
+ COUT_15 => COUT_15,
+ COUT_14 => COUT_14,
+ COUT_13 => COUT_13,
+ COUT_12 => COUT_12,
+ COUT_11 => COUT_11,
+ COUT_10 => COUT_10,
+ COUT_9 => COUT_9,
+ COUT_8 => COUT_8,
+ COUT_7 => COUT_7,
+ COUT_6 => COUT_6,
+ COUT_5 => COUT_5,
+ COUT_4 => COUT_4,
+ COUT_3 => COUT_3,
+ COUT_2 => COUT_2,
+ COUT_1 => COUT_1,
+ COUT_0 => COUT_0,
+ CIN_12 => CIN_12,
+ CIN_11 => CIN_11,
+ CIN_10 => CIN_10,
+ CIN_9 => CIN_9,
+ CIN_8 => CIN_8,
+ CIN_7 => CIN_7,
+ CIN_6 => CIN_6,
+ CIN_5 => CIN_5,
+ CIN_4 => CIN_4,
+ CIN_3 => CIN_3,
+ CIN_2 => CIN_2,
+ CIN_1 => CIN_1,
+ CIN_0 => CIN_0,
+ TESTCLK_MACO => TESTCLK_MACO
+);
+
+end PCSA_arch;
+
+--synopsys translate_on
+
+--synopsys translate_off
+library SC;
+use SC.components.all;
+--synopsys translate_on
+
+library IEEE, STD;
+use IEEE.std_logic_1164.all;
+use STD.TEXTIO.all;
+
+
+entity serdes_gbe_0_100_ext is
+ GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_0_100_ext.txt");
+ port (
+-- serdes clk pins --
+ refclkp, refclkn : in std_logic;
+ rxa_pclk, rxb_pclk : out std_logic;
+ hdinp_0, hdinn_0 : in std_logic;
+ hdoutp_0, hdoutn_0 : out std_logic;
+ tclk_0, rclk_0 : in std_logic;
+ tx_rst_0, rx_rst_0 : in std_logic;
+ ref_0_sclk, rx_0_sclk : out std_logic;
+ txd_0 : in std_logic_vector (15 downto 0);
+ tx_k_0, tx_force_disp_0, tx_disp_sel_0 : in std_logic_vector (1 downto 0);
+ rxd_0 : out std_logic_vector (15 downto 0);
+ rx_k_0, rx_disp_err_detect_0, rx_cv_detect_0 : out std_logic_vector (1 downto 0);
+ tx_crc_init_0 : in std_logic_vector (1 downto 0);
+ rx_crc_eop_0 : out std_logic_vector (1 downto 0);
+ word_align_en_0, mca_align_en_0, felb_0 : in std_logic;
+ lsm_en_0 : in std_logic;
+ lsm_status_0 : out std_logic;
+
+
+
+ mca_resync_01 : in std_logic;
+ quad_rst, serdes_rst : in std_logic;
+ ref_pclk : out std_logic);
+
+end serdes_gbe_0_100_ext;
+
+architecture serdes_gbe_0_100_ext_arch of serdes_gbe_0_100_ext is
+
+component VLO
+port (
+ Z : out std_logic);
+end component;
+
+component VHI
+port (
+ Z : out std_logic);
+end component;
+
+component PCSA
+--synopsys translate_off
+GENERIC(
+ CONFIG_FILE : String
+ );
+--synopsys translate_on
+port (
+ HDINP0 : in std_logic;
+ HDINN0 : in std_logic;
+ HDINP1 : in std_logic;
+ HDINN1 : in std_logic;
+ HDINP2 : in std_logic;
+ HDINN2 : in std_logic;
+ HDINP3 : in std_logic;
+ HDINN3 : in std_logic;
+ HDOUTP0 : out std_logic;
+ HDOUTN0 : out std_logic;
+ HDOUTP1 : out std_logic;
+ HDOUTN1 : out std_logic;
+ HDOUTP2 : out std_logic;
+ HDOUTN2 : out std_logic;
+ HDOUTP3 : out std_logic;
+ HDOUTN3 : out std_logic;
+ REFCLKP : in std_logic;
+ REFCLKN : in std_logic;
+ RXREFCLKP : in std_logic;
+ RXREFCLKN : in std_logic;
+ FFC_QUAD_RST : in std_logic;
+ FFC_MACRO_RST : in std_logic;
+
+ FFC_LANE_TX_RST0 : in std_logic;
+ FFC_LANE_TX_RST1 : in std_logic;
+ FFC_LANE_TX_RST2 : in std_logic;
+ FFC_LANE_TX_RST3 : in std_logic;
+
+ FFC_LANE_RX_RST0 : in std_logic;
+ FFC_LANE_RX_RST1 : in std_logic;
+ FFC_LANE_RX_RST2 : in std_logic;
+ FFC_LANE_RX_RST3 : in std_logic;
+
+ FFC_PCIE_EI_EN_0 : in std_logic;
+ FFC_PCIE_EI_EN_1 : in std_logic;
+ FFC_PCIE_EI_EN_2 : in std_logic;
+ FFC_PCIE_EI_EN_3 : in std_logic;
+
+ FFC_PCIE_CT_0 : in std_logic;
+ FFC_PCIE_CT_1 : in std_logic;
+ FFC_PCIE_CT_2 : in std_logic;
+ FFC_PCIE_CT_3 : in std_logic;
+
+ FFS_PCIE_CON_0 : out std_logic;
+ FFS_PCIE_CON_1 : out std_logic;
+ FFS_PCIE_CON_2 : out std_logic;
+ FFS_PCIE_CON_3 : out std_logic;
+
+ FFS_PCIE_DONE_0 : out std_logic;
+ FFS_PCIE_DONE_1 : out std_logic;
+ FFS_PCIE_DONE_2 : out std_logic;
+ FFS_PCIE_DONE_3 : out std_logic;
+
+ FFC_PCIE_TX_0 : in std_logic;
+ FFC_PCIE_TX_1 : in std_logic;
+ FFC_PCIE_TX_2 : in std_logic;
+ FFC_PCIE_TX_3 : in std_logic;
+
+ FFC_PCIE_RX_0 : in std_logic;
+ FFC_PCIE_RX_1 : in std_logic;
+ FFC_PCIE_RX_2 : in std_logic;
+ FFC_PCIE_RX_3 : in std_logic;
+
+ FFC_SD_0 : in std_logic;
+ FFC_SD_1 : in std_logic;
+ FFC_SD_2 : in std_logic;
+ FFC_SD_3 : in std_logic;
+
+ FFC_EN_CGA_0 : in std_logic;
+ FFC_EN_CGA_1 : in std_logic;
+ FFC_EN_CGA_2 : in std_logic;
+ FFC_EN_CGA_3 : in std_logic;
+
+ FFC_ALIGN_EN_0 : in std_logic;
+ FFC_ALIGN_EN_1 : in std_logic;
+ FFC_ALIGN_EN_2 : in std_logic;
+ FFC_ALIGN_EN_3 : in std_logic;
+
+ FFC_AB_RESET : in std_logic;
+ FFC_CD_RESET : in std_logic;
+
+ FFS_LS_STATUS_0 : out std_logic;
+ FFS_LS_STATUS_1 : out std_logic;
+ FFS_LS_STATUS_2 : out std_logic;
+ FFS_LS_STATUS_3 : out std_logic;
+
+ FFS_AB_STATUS : out std_logic;
+ FFS_CD_STATUS : out std_logic;
+
+ FFS_AB_ALIGNED : out std_logic;
+ FFS_CD_ALIGNED : out std_logic;
+
+ FFS_AB_FAILED : out std_logic;
+ FFS_CD_FAILED : out std_logic;
+
+ FFS_RLOS_LO0 : out std_logic;
+ FFS_RLOS_LO1 : out std_logic;
+ FFS_RLOS_LO2 : out std_logic;
+ FFS_RLOS_LO3 : out std_logic;
+
+ FFC_FB_LB_0 : in std_logic;
+ FFC_FB_LB_1 : in std_logic;
+ FFC_FB_LB_2 : in std_logic;
+ FFC_FB_LB_3 : in std_logic;
+
+ FFC_SB_INV_RX_0 : in std_logic;
+ FFC_SB_INV_RX_1 : in std_logic;
+ FFC_SB_INV_RX_2 : in std_logic;
+ FFC_SB_INV_RX_3 : in std_logic;
+
+ FFS_CC_ORUN_0 : out std_logic;
+ FFS_CC_ORUN_1 : out std_logic;
+ FFS_CC_ORUN_2 : out std_logic;
+ FFS_CC_ORUN_3 : out std_logic;
+
+ FFS_CC_URUN_0 : out std_logic;
+ FFS_CC_URUN_1 : out std_logic;
+ FFS_CC_URUN_2 : out std_logic;
+ FFS_CC_URUN_3 : out std_logic;
+
+ FFC_CK_CORE_TX : in std_logic;
+ FFC_CK_CORE_RX : in std_logic;
+ RDATAO_7 : out std_logic;
+ RDATAO_6 : out std_logic;
+ RDATAO_5 : out std_logic;
+ RDATAO_4 : out std_logic;
+ RDATAO_3 : out std_logic;
+ RDATAO_2 : out std_logic;
+ RDATAO_1 : out std_logic;
+ RDATAO_0 : out std_logic;
+ INTO : out std_logic;
+
+ ADDRI_7 : in std_logic;
+ ADDRI_6 : in std_logic;
+ ADDRI_5 : in std_logic;
+ ADDRI_4 : in std_logic;
+ ADDRI_3 : in std_logic;
+ ADDRI_2 : in std_logic;
+ ADDRI_1 : in std_logic;
+ ADDRI_0 : in std_logic;
+ WDATAI_7 : in std_logic;
+ WDATAI_6 : in std_logic;
+ WDATAI_5 : in std_logic;
+ WDATAI_4 : in std_logic;
+ WDATAI_3 : in std_logic;
+ WDATAI_2 : in std_logic;
+ WDATAI_1 : in std_logic;
+ WDATAI_0 : in std_logic;
+ RDI : in std_logic;
+ WSTBI : in std_logic;
+
+ CS_CHIF_0 : in std_logic;
+ CS_CHIF_1 : in std_logic;
+ CS_CHIF_2 : in std_logic;
+ CS_CHIF_3 : in std_logic;
+ CS_QIF : in std_logic;
+
+ QUAD_ID_1 : in std_logic;
+ QUAD_ID_0 : in std_logic;
+
+ FF_SYSCLK_P1 : out std_logic;
+
+ FF_SYSCLK0 : out std_logic;
+ FF_SYSCLK1 : out std_logic;
+ FF_SYSCLK2 : out std_logic;
+ FF_SYSCLK3 : out std_logic;
+
+ FF_RXCLK_P1 : out std_logic;
+ FF_RXCLK_P2 : out std_logic;
+
+ FF_RXCLK0 : out std_logic;
+ FF_RXCLK1 : out std_logic;
+ FF_RXCLK2 : out std_logic;
+ FF_RXCLK3 : out std_logic;
+
+ QUAD_CLK : out std_logic;
+
+ GRP_CLK_P1_3 : in std_logic;
+ GRP_CLK_P1_2 : in std_logic;
+ GRP_CLK_P1_1 : in std_logic;
+ GRP_CLK_P1_0 : in std_logic;
+
+ GRP_CLK_P2_3 : in std_logic;
+ GRP_CLK_P2_2 : in std_logic;
+ GRP_CLK_P2_1 : in std_logic;
+ GRP_CLK_P2_0 : in std_logic;
+
+ GRP_START_3 : in std_logic;
+ GRP_START_2 : in std_logic;
+ GRP_START_1 : in std_logic;
+ GRP_START_0 : in std_logic;
+
+ GRP_DONE_3 : in std_logic;
+ GRP_DONE_2 : in std_logic;
+ GRP_DONE_1 : in std_logic;
+ GRP_DONE_0 : in std_logic;
+
+ GRP_DESKEW_ERROR_3 : in std_logic;
+ GRP_DESKEW_ERROR_2 : in std_logic;
+ GRP_DESKEW_ERROR_1 : in std_logic;
+ GRP_DESKEW_ERROR_0 : in std_logic;
+
+ IQA_START_LS : out std_logic;
+ IQA_DONE_LS : out std_logic;
+ IQA_AND_FP1_LS : out std_logic;
+ IQA_AND_FP0_LS : out std_logic;
+ IQA_OR_FP1_LS : out std_logic;
+ IQA_OR_FP0_LS : out std_logic;
+ IQA_RST_N : out std_logic;
+
+ FF_TCLK0 : in std_logic;
+ FF_TCLK1 : in std_logic;
+ FF_TCLK2 : in std_logic;
+ FF_TCLK3 : in std_logic;
+
+ FF_RCLK0 : in std_logic;
+ FF_RCLK1 : in std_logic;
+ FF_RCLK2 : in std_logic;
+ FF_RCLK3 : in std_logic;
+ TCK_FMACP : in std_logic;
+
+ FF_TXD_0_23 : in std_logic;
+ FF_TXD_0_22 : in std_logic;
+ FF_TXD_0_21 : in std_logic;
+ FF_TXD_0_20 : in std_logic;
+ FF_TXD_0_19 : in std_logic;
+ FF_TXD_0_18 : in std_logic;
+ FF_TXD_0_17 : in std_logic;
+ FF_TXD_0_16 : in std_logic;
+ FF_TXD_0_15 : in std_logic;
+ FF_TXD_0_14 : in std_logic;
+ FF_TXD_0_13 : in std_logic;
+ FF_TXD_0_12 : in std_logic;
+ FF_TXD_0_11 : in std_logic;
+ FF_TXD_0_10 : in std_logic;
+ FF_TXD_0_9 : in std_logic;
+ FF_TXD_0_8 : in std_logic;
+ FF_TXD_0_7 : in std_logic;
+ FF_TXD_0_6 : in std_logic;
+ FF_TXD_0_5 : in std_logic;
+ FF_TXD_0_4 : in std_logic;
+ FF_TXD_0_3 : in std_logic;
+ FF_TXD_0_2 : in std_logic;
+ FF_TXD_0_1 : in std_logic;
+ FF_TXD_0_0 : in std_logic;
+ FB_RXD_0_23 : out std_logic;
+ FB_RXD_0_22 : out std_logic;
+ FB_RXD_0_21 : out std_logic;
+ FB_RXD_0_20 : out std_logic;
+ FB_RXD_0_19 : out std_logic;
+ FB_RXD_0_18 : out std_logic;
+ FB_RXD_0_17 : out std_logic;
+ FB_RXD_0_16 : out std_logic;
+ FB_RXD_0_15 : out std_logic;
+ FB_RXD_0_14 : out std_logic;
+ FB_RXD_0_13 : out std_logic;
+ FB_RXD_0_12 : out std_logic;
+ FB_RXD_0_11 : out std_logic;
+ FB_RXD_0_10 : out std_logic;
+ FB_RXD_0_9 : out std_logic;
+ FB_RXD_0_8 : out std_logic;
+ FB_RXD_0_7 : out std_logic;
+ FB_RXD_0_6 : out std_logic;
+ FB_RXD_0_5 : out std_logic;
+ FB_RXD_0_4 : out std_logic;
+ FB_RXD_0_3 : out std_logic;
+ FB_RXD_0_2 : out std_logic;
+ FB_RXD_0_1 : out std_logic;
+ FB_RXD_0_0 : out std_logic;
+ FF_TXD_1_23 : in std_logic;
+ FF_TXD_1_22 : in std_logic;
+ FF_TXD_1_21 : in std_logic;
+ FF_TXD_1_20 : in std_logic;
+ FF_TXD_1_19 : in std_logic;
+ FF_TXD_1_18 : in std_logic;
+ FF_TXD_1_17 : in std_logic;
+ FF_TXD_1_16 : in std_logic;
+ FF_TXD_1_15 : in std_logic;
+ FF_TXD_1_14 : in std_logic;
+ FF_TXD_1_13 : in std_logic;
+ FF_TXD_1_12 : in std_logic;
+ FF_TXD_1_11 : in std_logic;
+ FF_TXD_1_10 : in std_logic;
+ FF_TXD_1_9 : in std_logic;
+ FF_TXD_1_8 : in std_logic;
+ FF_TXD_1_7 : in std_logic;
+ FF_TXD_1_6 : in std_logic;
+ FF_TXD_1_5 : in std_logic;
+ FF_TXD_1_4 : in std_logic;
+ FF_TXD_1_3 : in std_logic;
+ FF_TXD_1_2 : in std_logic;
+ FF_TXD_1_1 : in std_logic;
+ FF_TXD_1_0 : in std_logic;
+ FB_RXD_1_23 : out std_logic;
+ FB_RXD_1_22 : out std_logic;
+ FB_RXD_1_21 : out std_logic;
+ FB_RXD_1_20 : out std_logic;
+ FB_RXD_1_19 : out std_logic;
+ FB_RXD_1_18 : out std_logic;
+ FB_RXD_1_17 : out std_logic;
+ FB_RXD_1_16 : out std_logic;
+ FB_RXD_1_15 : out std_logic;
+ FB_RXD_1_14 : out std_logic;
+ FB_RXD_1_13 : out std_logic;
+ FB_RXD_1_12 : out std_logic;
+ FB_RXD_1_11 : out std_logic;
+ FB_RXD_1_10 : out std_logic;
+ FB_RXD_1_9 : out std_logic;
+ FB_RXD_1_8 : out std_logic;
+ FB_RXD_1_7 : out std_logic;
+ FB_RXD_1_6 : out std_logic;
+ FB_RXD_1_5 : out std_logic;
+ FB_RXD_1_4 : out std_logic;
+ FB_RXD_1_3 : out std_logic;
+ FB_RXD_1_2 : out std_logic;
+ FB_RXD_1_1 : out std_logic;
+ FB_RXD_1_0 : out std_logic;
+ FF_TXD_2_23 : in std_logic;
+ FF_TXD_2_22 : in std_logic;
+ FF_TXD_2_21 : in std_logic;
+ FF_TXD_2_20 : in std_logic;
+ FF_TXD_2_19 : in std_logic;
+ FF_TXD_2_18 : in std_logic;
+ FF_TXD_2_17 : in std_logic;
+ FF_TXD_2_16 : in std_logic;
+ FF_TXD_2_15 : in std_logic;
+ FF_TXD_2_14 : in std_logic;
+ FF_TXD_2_13 : in std_logic;
+ FF_TXD_2_12 : in std_logic;
+ FF_TXD_2_11 : in std_logic;
+ FF_TXD_2_10 : in std_logic;
+ FF_TXD_2_9 : in std_logic;
+ FF_TXD_2_8 : in std_logic;
+ FF_TXD_2_7 : in std_logic;
+ FF_TXD_2_6 : in std_logic;
+ FF_TXD_2_5 : in std_logic;
+ FF_TXD_2_4 : in std_logic;
+ FF_TXD_2_3 : in std_logic;
+ FF_TXD_2_2 : in std_logic;
+ FF_TXD_2_1 : in std_logic;
+ FF_TXD_2_0 : in std_logic;
+ FB_RXD_2_23 : out std_logic;
+ FB_RXD_2_22 : out std_logic;
+ FB_RXD_2_21 : out std_logic;
+ FB_RXD_2_20 : out std_logic;
+ FB_RXD_2_19 : out std_logic;
+ FB_RXD_2_18 : out std_logic;
+ FB_RXD_2_17 : out std_logic;
+ FB_RXD_2_16 : out std_logic;
+ FB_RXD_2_15 : out std_logic;
+ FB_RXD_2_14 : out std_logic;
+ FB_RXD_2_13 : out std_logic;
+ FB_RXD_2_12 : out std_logic;
+ FB_RXD_2_11 : out std_logic;
+ FB_RXD_2_10 : out std_logic;
+ FB_RXD_2_9 : out std_logic;
+ FB_RXD_2_8 : out std_logic;
+ FB_RXD_2_7 : out std_logic;
+ FB_RXD_2_6 : out std_logic;
+ FB_RXD_2_5 : out std_logic;
+ FB_RXD_2_4 : out std_logic;
+ FB_RXD_2_3 : out std_logic;
+ FB_RXD_2_2 : out std_logic;
+ FB_RXD_2_1 : out std_logic;
+ FB_RXD_2_0 : out std_logic;
+ FF_TXD_3_23 : in std_logic;
+ FF_TXD_3_22 : in std_logic;
+ FF_TXD_3_21 : in std_logic;
+ FF_TXD_3_20 : in std_logic;
+ FF_TXD_3_19 : in std_logic;
+ FF_TXD_3_18 : in std_logic;
+ FF_TXD_3_17 : in std_logic;
+ FF_TXD_3_16 : in std_logic;
+ FF_TXD_3_15 : in std_logic;
+ FF_TXD_3_14 : in std_logic;
+ FF_TXD_3_13 : in std_logic;
+ FF_TXD_3_12 : in std_logic;
+ FF_TXD_3_11 : in std_logic;
+ FF_TXD_3_10 : in std_logic;
+ FF_TXD_3_9 : in std_logic;
+ FF_TXD_3_8 : in std_logic;
+ FF_TXD_3_7 : in std_logic;
+ FF_TXD_3_6 : in std_logic;
+ FF_TXD_3_5 : in std_logic;
+ FF_TXD_3_4 : in std_logic;
+ FF_TXD_3_3 : in std_logic;
+ FF_TXD_3_2 : in std_logic;
+ FF_TXD_3_1 : in std_logic;
+ FF_TXD_3_0 : in std_logic;
+ FB_RXD_3_23 : out std_logic;
+ FB_RXD_3_22 : out std_logic;
+ FB_RXD_3_21 : out std_logic;
+ FB_RXD_3_20 : out std_logic;
+ FB_RXD_3_19 : out std_logic;
+ FB_RXD_3_18 : out std_logic;
+ FB_RXD_3_17 : out std_logic;
+ FB_RXD_3_16 : out std_logic;
+ FB_RXD_3_15 : out std_logic;
+ FB_RXD_3_14 : out std_logic;
+ FB_RXD_3_13 : out std_logic;
+ FB_RXD_3_12 : out std_logic;
+ FB_RXD_3_11 : out std_logic;
+ FB_RXD_3_10 : out std_logic;
+ FB_RXD_3_9 : out std_logic;
+ FB_RXD_3_8 : out std_logic;
+ FB_RXD_3_7 : out std_logic;
+ FB_RXD_3_6 : out std_logic;
+ FB_RXD_3_5 : out std_logic;
+ FB_RXD_3_4 : out std_logic;
+ FB_RXD_3_3 : out std_logic;
+ FB_RXD_3_2 : out std_logic;
+ FB_RXD_3_1 : out std_logic;
+ FB_RXD_3_0 : out std_logic;
+ TCK_FMAC : out std_logic;
+ BS4PAD_0 : out std_logic;
+ BS4PAD_1 : out std_logic;
+ BS4PAD_2 : out std_logic;
+ BS4PAD_3 : out std_logic;
+ COUT_21 : out std_logic;
+ COUT_20 : out std_logic;
+ COUT_19 : out std_logic;
+ COUT_18 : out std_logic;
+ COUT_17 : out std_logic;
+ COUT_16 : out std_logic;
+ COUT_15 : out std_logic;
+ COUT_14 : out std_logic;
+ COUT_13 : out std_logic;
+ COUT_12 : out std_logic;
+ COUT_11 : out std_logic;
+ COUT_10 : out std_logic;
+ COUT_9 : out std_logic;
+ COUT_8 : out std_logic;
+ COUT_7 : out std_logic;
+ COUT_6 : out std_logic;
+ COUT_5 : out std_logic;
+ COUT_4 : out std_logic;
+ COUT_3 : out std_logic;
+ COUT_2 : out std_logic;
+ COUT_1 : out std_logic;
+ COUT_0 : out std_logic;
+ CIN_12 : in std_logic;
+ CIN_11 : in std_logic;
+ CIN_10 : in std_logic;
+ CIN_9 : in std_logic;
+ CIN_8 : in std_logic;
+ CIN_7 : in std_logic;
+ CIN_6 : in std_logic;
+ CIN_5 : in std_logic;
+ CIN_4 : in std_logic;
+ CIN_3 : in std_logic;
+ CIN_2 : in std_logic;
+ CIN_1 : in std_logic;
+ CIN_0 : in std_logic;
+ TESTCLK_MACO : in std_logic
+);
+end component;
+ attribute IS_ASB: string;
+ attribute IS_ASB of PCSA_INST : label is "or5s00/data/or5s00.acd";
+ attribute CONFIG_FILE: string;
+ attribute CONFIG_FILE of PCSA_INST : label is USER_CONFIG_FILE;
+ attribute CH0_RX_MAXRATE: string;
+ attribute CH0_RX_MAXRATE of PCSA_INST : label is "RXF3";
+ attribute CH1_RX_MAXRATE: string;
+ attribute CH1_RX_MAXRATE of PCSA_INST : label is "RXF3";
+ attribute CH2_RX_MAXRATE: string;
+ attribute CH2_RX_MAXRATE of PCSA_INST : label is "RXF3";
+ attribute CH3_RX_MAXRATE: string;
+ attribute CH3_RX_MAXRATE of PCSA_INST : label is "RXF3";
+ attribute CH0_TX_MAXRATE: string;
+ attribute CH0_TX_MAXRATE of PCSA_INST : label is "TXF2";
+ attribute CH1_TX_MAXRATE: string;
+ attribute CH1_TX_MAXRATE of PCSA_INST : label is "TXF2";
+ attribute CH2_TX_MAXRATE: string;
+ attribute CH2_TX_MAXRATE of PCSA_INST : label is "TXF2";
+ attribute CH3_TX_MAXRATE: string;
+ attribute CH3_TX_MAXRATE of PCSA_INST : label is "TXF2";
+ attribute AMP_BOOST: string;
+ attribute AMP_BOOST of PCSA_INST : label is "DISABLED";
+ attribute black_box_pad_pin: string;
+ attribute black_box_pad_pin of PCSA : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN, RXREFCLKP, RXREFCLKN";
+
+signal fpsc_vlo : std_logic := '0';
+
+begin
+
+vlo_inst : VLO port map(Z => fpsc_vlo);
+
+-- pcs_quad instance
+PCSA_INST : PCSA
+--synopsys translate_off
+ generic map (CONFIG_FILE => USER_CONFIG_FILE)
+--synopsys translate_on
+port map (
+ REFCLKP => refclkp,
+ REFCLKN => refclkn,
+ RXREFCLKP => fpsc_vlo,
+ RXREFCLKN => fpsc_vlo,
+ FFC_CK_CORE_RX => fpsc_vlo,
+ FFC_CK_CORE_TX => fpsc_vlo,
+ CS_CHIF_0 => fpsc_vlo,
+ CS_CHIF_1 => fpsc_vlo,
+ CS_CHIF_2 => fpsc_vlo,
+ CS_CHIF_3 => fpsc_vlo,
+ CS_QIF => fpsc_vlo,
+ QUAD_ID_0 => fpsc_vlo,
+ QUAD_ID_1 => fpsc_vlo,
+ ADDRI_0 => fpsc_vlo,
+ ADDRI_1 => fpsc_vlo,
+ ADDRI_2 => fpsc_vlo,
+ ADDRI_3 => fpsc_vlo,
+ ADDRI_4 => fpsc_vlo,
+ ADDRI_5 => fpsc_vlo,
+ ADDRI_6 => fpsc_vlo,
+ ADDRI_7 => fpsc_vlo,
+ WDATAI_0 => fpsc_vlo,
+ WDATAI_1 => fpsc_vlo,
+ WDATAI_2 => fpsc_vlo,
+ WDATAI_3 => fpsc_vlo,
+ WDATAI_4 => fpsc_vlo,
+ WDATAI_5 => fpsc_vlo,
+ WDATAI_6 => fpsc_vlo,
+ WDATAI_7 => fpsc_vlo,
+ RDI => fpsc_vlo,
+ WSTBI => fpsc_vlo,
+ GRP_CLK_P1_0 => fpsc_vlo,
+ GRP_CLK_P1_1 => fpsc_vlo,
+ GRP_CLK_P1_2 => fpsc_vlo,
+ GRP_CLK_P1_3 => fpsc_vlo,
+ GRP_CLK_P2_0 => fpsc_vlo,
+ GRP_CLK_P2_1 => fpsc_vlo,
+ GRP_CLK_P2_2 => fpsc_vlo,
+ GRP_CLK_P2_3 => fpsc_vlo,
+ GRP_START_0 => fpsc_vlo,
+ GRP_START_1 => fpsc_vlo,
+ GRP_START_2 => fpsc_vlo,
+ GRP_START_3 => fpsc_vlo,
+ GRP_DONE_0 => fpsc_vlo,
+ GRP_DONE_1 => fpsc_vlo,
+ GRP_DONE_2 => fpsc_vlo,
+ GRP_DONE_3 => fpsc_vlo,
+ GRP_DESKEW_ERROR_0 => fpsc_vlo,
+ GRP_DESKEW_ERROR_1 => fpsc_vlo,
+ GRP_DESKEW_ERROR_2 => fpsc_vlo,
+ GRP_DESKEW_ERROR_3 => fpsc_vlo,
+-- to sysbusa
+ RDATAO_0 => open,
+ RDATAO_1 => open,
+ RDATAO_2 => open,
+ RDATAO_3 => open,
+ RDATAO_4 => open,
+ RDATAO_5 => open,
+ RDATAO_6 => open,
+ RDATAO_7 => open,
+ INTO => open,
+ QUAD_CLK => open,
+ IQA_START_LS => open,
+ IQA_DONE_LS => open,
+ IQA_AND_FP1_LS => open,
+ IQA_AND_FP0_LS => open,
+ IQA_OR_FP1_LS => open,
+ IQA_OR_FP0_LS => open,
+ IQA_RST_N => open,
+
+ FF_TXD_0_19 => txd_0(15),
+ FF_TXD_0_18 => txd_0(14),
+ FF_TXD_0_17 => txd_0(13),
+ FF_TXD_0_16 => txd_0(12),
+ FF_TXD_0_15 => txd_0(11),
+ FF_TXD_0_14 => txd_0(10),
+ FF_TXD_0_13 => txd_0(9),
+ FF_TXD_0_12 => txd_0(8),
+ FF_TXD_0_7 => txd_0(7),
+ FF_TXD_0_6 => txd_0(6),
+ FF_TXD_0_5 => txd_0(5),
+ FF_TXD_0_4 => txd_0(4),
+ FF_TXD_0_3 => txd_0(3),
+ FF_TXD_0_2 => txd_0(2),
+ FF_TXD_0_1 => txd_0(1),
+ FF_TXD_0_0 => txd_0(0),
+ FB_RXD_0_19 => rxd_0(15),
+ FB_RXD_0_18 => rxd_0(14),
+ FB_RXD_0_17 => rxd_0(13),
+ FB_RXD_0_16 => rxd_0(12),
+ FB_RXD_0_15 => rxd_0(11),
+ FB_RXD_0_14 => rxd_0(10),
+ FB_RXD_0_13 => rxd_0(9),
+ FB_RXD_0_12 => rxd_0(8),
+ FB_RXD_0_7 => rxd_0(7),
+ FB_RXD_0_6 => rxd_0(6),
+ FB_RXD_0_5 => rxd_0(5),
+ FB_RXD_0_4 => rxd_0(4),
+ FB_RXD_0_3 => rxd_0(3),
+ FB_RXD_0_2 => rxd_0(2),
+ FB_RXD_0_1 => rxd_0(1),
+ FB_RXD_0_0 => rxd_0(0),
+
+ FF_TXD_0_20 => tx_k_0(1),
+ FF_TXD_0_8 => tx_k_0(0),
+ FB_RXD_0_20 => rx_k_0(1),
+ FB_RXD_0_8 => rx_k_0(0),
+
+ FF_TXD_0_21 => tx_force_disp_0(1),
+ FF_TXD_0_9 => tx_force_disp_0(0),
+
+ FF_TXD_0_22 => tx_disp_sel_0(1),
+ FF_TXD_0_10 => tx_disp_sel_0(0),
+
+ FF_TXD_0_23 => tx_crc_init_0(1),
+ FF_TXD_0_11 => tx_crc_init_0(0),
+
+ FB_RXD_0_21 => rx_disp_err_detect_0(1),
+ FB_RXD_0_9 => rx_disp_err_detect_0(0),
+
+ FB_RXD_0_22 => rx_cv_detect_0(1),
+ FB_RXD_0_10 => rx_cv_detect_0(0),
+
+ FB_RXD_0_23 => rx_crc_eop_0(1),
+ FB_RXD_0_11 => rx_crc_eop_0(0),
+
+ FF_TXD_1_19 => fpsc_vlo,
+ FF_TXD_1_18 => fpsc_vlo,
+ FF_TXD_1_17 => fpsc_vlo,
+ FF_TXD_1_16 => fpsc_vlo,
+ FF_TXD_1_15 => fpsc_vlo,
+ FF_TXD_1_14 => fpsc_vlo,
+ FF_TXD_1_13 => fpsc_vlo,
+ FF_TXD_1_12 => fpsc_vlo,
+ FF_TXD_1_7 => fpsc_vlo,
+ FF_TXD_1_6 => fpsc_vlo,
+ FF_TXD_1_5 => fpsc_vlo,
+ FF_TXD_1_4 => fpsc_vlo,
+ FF_TXD_1_3 => fpsc_vlo,
+ FF_TXD_1_2 => fpsc_vlo,
+ FF_TXD_1_1 => fpsc_vlo,
+ FF_TXD_1_0 => fpsc_vlo,
+ FB_RXD_1_19 => open,
+ FB_RXD_1_18 => open,
+ FB_RXD_1_17 => open,
+ FB_RXD_1_16 => open,
+ FB_RXD_1_15 => open,
+ FB_RXD_1_14 => open,
+ FB_RXD_1_13 => open,
+ FB_RXD_1_12 => open,
+ FB_RXD_1_7 => open,
+ FB_RXD_1_6 => open,
+ FB_RXD_1_5 => open,
+ FB_RXD_1_4 => open,
+ FB_RXD_1_3 => open,
+ FB_RXD_1_2 => open,
+ FB_RXD_1_1 => open,
+ FB_RXD_1_0 => open,
+
+ FF_TXD_1_20 => fpsc_vlo,
+ FF_TXD_1_8 => fpsc_vlo,
+ FB_RXD_1_20 => open,
+ FB_RXD_1_8 => open,
+
+ FF_TXD_1_21 => fpsc_vlo,
+ FF_TXD_1_9 => fpsc_vlo,
+
+ FF_TXD_1_22 => fpsc_vlo,
+ FF_TXD_1_10 => fpsc_vlo,
+ FF_TXD_1_23 => fpsc_vlo,
+ FF_TXD_1_11 => fpsc_vlo,
+
+ FB_RXD_1_21 => open,
+ FB_RXD_1_9 => open,
+
+ FB_RXD_1_22 => open,
+ FB_RXD_1_10 => open,
+
+ FB_RXD_1_23 => open,
+ FB_RXD_1_11 => open,
+
+ FF_TXD_2_19 => fpsc_vlo,
+ FF_TXD_2_18 => fpsc_vlo,
+ FF_TXD_2_17 => fpsc_vlo,
+ FF_TXD_2_16 => fpsc_vlo,
+ FF_TXD_2_15 => fpsc_vlo,
+ FF_TXD_2_14 => fpsc_vlo,
+ FF_TXD_2_13 => fpsc_vlo,
+ FF_TXD_2_12 => fpsc_vlo,
+ FF_TXD_2_7 => fpsc_vlo,
+ FF_TXD_2_6 => fpsc_vlo,
+ FF_TXD_2_5 => fpsc_vlo,
+ FF_TXD_2_4 => fpsc_vlo,
+ FF_TXD_2_3 => fpsc_vlo,
+ FF_TXD_2_2 => fpsc_vlo,
+ FF_TXD_2_1 => fpsc_vlo,
+ FF_TXD_2_0 => fpsc_vlo,
+ FB_RXD_2_19 => open,
+ FB_RXD_2_18 => open,
+ FB_RXD_2_17 => open,
+ FB_RXD_2_16 => open,
+ FB_RXD_2_15 => open,
+ FB_RXD_2_14 => open,
+ FB_RXD_2_13 => open,
+ FB_RXD_2_12 => open,
+ FB_RXD_2_7 => open,
+ FB_RXD_2_6 => open,
+ FB_RXD_2_5 => open,
+ FB_RXD_2_4 => open,
+ FB_RXD_2_3 => open,
+ FB_RXD_2_2 => open,
+ FB_RXD_2_1 => open,
+ FB_RXD_2_0 => open,
+
+ FF_TXD_2_20 => fpsc_vlo,
+ FF_TXD_2_8 => fpsc_vlo,
+ FB_RXD_2_20 => open,
+ FB_RXD_2_8 => open,
+
+ FF_TXD_2_21 => fpsc_vlo,
+ FF_TXD_2_9 => fpsc_vlo,
+
+ FF_TXD_2_22 => fpsc_vlo,
+ FF_TXD_2_10 => fpsc_vlo,
+ FF_TXD_2_23 => fpsc_vlo,
+ FF_TXD_2_11 => fpsc_vlo,
+
+ FB_RXD_2_21 => open,
+ FB_RXD_2_9 => open,
+
+ FB_RXD_2_22 => open,
+ FB_RXD_2_10 => open,
+
+ FB_RXD_2_23 => open,
+ FB_RXD_2_11 => open,
+
+ FF_TXD_3_19 => fpsc_vlo,
+ FF_TXD_3_18 => fpsc_vlo,
+ FF_TXD_3_17 => fpsc_vlo,
+ FF_TXD_3_16 => fpsc_vlo,
+ FF_TXD_3_15 => fpsc_vlo,
+ FF_TXD_3_14 => fpsc_vlo,
+ FF_TXD_3_13 => fpsc_vlo,
+ FF_TXD_3_12 => fpsc_vlo,
+ FF_TXD_3_7 => fpsc_vlo,
+ FF_TXD_3_6 => fpsc_vlo,
+ FF_TXD_3_5 => fpsc_vlo,
+ FF_TXD_3_4 => fpsc_vlo,
+ FF_TXD_3_3 => fpsc_vlo,
+ FF_TXD_3_2 => fpsc_vlo,
+ FF_TXD_3_1 => fpsc_vlo,
+ FF_TXD_3_0 => fpsc_vlo,
+ FB_RXD_3_19 => open,
+ FB_RXD_3_18 => open,
+ FB_RXD_3_17 => open,
+ FB_RXD_3_16 => open,
+ FB_RXD_3_15 => open,
+ FB_RXD_3_14 => open,
+ FB_RXD_3_13 => open,
+ FB_RXD_3_12 => open,
+ FB_RXD_3_7 => open,
+ FB_RXD_3_6 => open,
+ FB_RXD_3_5 => open,
+ FB_RXD_3_4 => open,
+ FB_RXD_3_3 => open,
+ FB_RXD_3_2 => open,
+ FB_RXD_3_1 => open,
+ FB_RXD_3_0 => open,
+
+ FF_TXD_3_20 => fpsc_vlo,
+ FF_TXD_3_8 => fpsc_vlo,
+ FB_RXD_3_20 => open,
+ FB_RXD_3_8 => open,
+
+ FF_TXD_3_21 => fpsc_vlo,
+ FF_TXD_3_9 => fpsc_vlo,
+
+ FF_TXD_3_22 => fpsc_vlo,
+ FF_TXD_3_10 => fpsc_vlo,
+ FF_TXD_3_23 => fpsc_vlo,
+ FF_TXD_3_11 => fpsc_vlo,
+
+ FB_RXD_3_21 => open,
+ FB_RXD_3_9 => open,
+
+ FB_RXD_3_22 => open,
+ FB_RXD_3_10 => open,
+
+ FB_RXD_3_23 => open,
+ FB_RXD_3_11 => open,
+
+ HDINP0 => hdinp_0,
+ HDINN0 => hdinn_0,
+ HDOUTP0 => hdoutp_0,
+ HDOUTN0 => hdoutn_0,
+ FF_SYSCLK0 => ref_0_sclk,
+ FF_RXCLK0 => rx_0_sclk,
+ FFC_LANE_TX_RST0 => tx_rst_0,
+ FFC_LANE_RX_RST0 => rx_rst_0,
+ FF_TCLK0 => tclk_0,
+ FF_RCLK0 => rclk_0,
+ HDINP1 => fpsc_vlo,
+ HDINN1 => fpsc_vlo,
+ HDOUTP1 => open,
+ HDOUTN1 => open,
+ FF_SYSCLK1 => open,
+ FF_RXCLK1 => open,
+ FFC_LANE_TX_RST1 => fpsc_vlo,
+ FFC_LANE_RX_RST1 => fpsc_vlo,
+ FF_TCLK1 => fpsc_vlo,
+ FF_RCLK1 => fpsc_vlo,
+ HDINP2 => fpsc_vlo,
+ HDINN2 => fpsc_vlo,
+ HDOUTP2 => open,
+ HDOUTN2 => open,
+ FF_SYSCLK2 => open,
+ FF_RXCLK2 => open,
+ FFC_LANE_TX_RST2 => fpsc_vlo,
+ FFC_LANE_RX_RST2 => fpsc_vlo,
+ FF_TCLK2 => fpsc_vlo,
+ FF_RCLK2 => fpsc_vlo,
+ HDINP3 => fpsc_vlo,
+ HDINN3 => fpsc_vlo,
+ HDOUTP3 => open,
+ HDOUTN3 => open,
+ FF_SYSCLK3 => open,
+ FF_RXCLK3 => open,
+ FFC_LANE_TX_RST3 => fpsc_vlo,
+ FFC_LANE_RX_RST3 => fpsc_vlo,
+ FF_TCLK3 => fpsc_vlo,
+ FF_RCLK3 => fpsc_vlo,
+
+ FFC_PCIE_EI_EN_0 => fpsc_vlo,
+ FFC_PCIE_CT_0 => fpsc_vlo,
+ FFC_PCIE_TX_0 => fpsc_vlo,
+ FFC_PCIE_RX_0 => fpsc_vlo,
+ FFS_PCIE_CON_0 => open,
+ FFS_PCIE_DONE_0 => open,
+ FFC_PCIE_EI_EN_1 => fpsc_vlo,
+ FFC_PCIE_CT_1 => fpsc_vlo,
+ FFC_PCIE_TX_1 => fpsc_vlo,
+ FFC_PCIE_RX_1 => fpsc_vlo,
+ FFS_PCIE_CON_1 => open,
+ FFS_PCIE_DONE_1 => open,
+ FFC_PCIE_EI_EN_2 => fpsc_vlo,
+ FFC_PCIE_CT_2 => fpsc_vlo,
+ FFC_PCIE_TX_2 => fpsc_vlo,
+ FFC_PCIE_RX_2 => fpsc_vlo,
+ FFS_PCIE_CON_2 => open,
+ FFS_PCIE_DONE_2 => open,
+ FFC_PCIE_EI_EN_3 => fpsc_vlo,
+ FFC_PCIE_CT_3 => fpsc_vlo,
+ FFC_PCIE_TX_3 => fpsc_vlo,
+ FFC_PCIE_RX_3 => fpsc_vlo,
+ FFS_PCIE_CON_3 => open,
+ FFS_PCIE_DONE_3 => open,
+
+ FFC_SD_0 => lsm_en_0,
+ FFC_SD_1 => fpsc_vlo,
+ FFC_SD_2 => fpsc_vlo,
+ FFC_SD_3 => fpsc_vlo,
+
+ FFC_EN_CGA_0 => word_align_en_0,
+ FFC_EN_CGA_1 => fpsc_vlo,
+ FFC_EN_CGA_2 => fpsc_vlo,
+ FFC_EN_CGA_3 => fpsc_vlo,
+
+ FFC_ALIGN_EN_0 => mca_align_en_0,
+ FFC_ALIGN_EN_1 => fpsc_vlo,
+ FFC_ALIGN_EN_2 => fpsc_vlo,
+ FFC_ALIGN_EN_3 => fpsc_vlo,
+
+ FFC_FB_LB_0 => felb_0,
+ FFC_FB_LB_1 => fpsc_vlo,
+ FFC_FB_LB_2 => fpsc_vlo,
+ FFC_FB_LB_3 => fpsc_vlo,
+
+ FFS_LS_STATUS_0 => lsm_status_0,
+ FFS_LS_STATUS_1 => open,
+ FFS_LS_STATUS_2 => open,
+ FFS_LS_STATUS_3 => open,
+
+ FFS_CC_ORUN_0 => open,
+ FFS_CC_URUN_0 => open,
+ FFS_CC_ORUN_1 => open,
+ FFS_CC_URUN_1 => open,
+ FFS_CC_ORUN_2 => open,
+ FFS_CC_URUN_2 => open,
+ FFS_CC_ORUN_3 => open,
+ FFS_CC_URUN_3 => open,
+
+ FFC_AB_RESET => mca_resync_01,
+
+ FFS_AB_STATUS => open,
+ FFS_AB_ALIGNED => open,
+ FFS_AB_FAILED => open,
+
+ FFC_CD_RESET => fpsc_vlo,
+ FFS_CD_STATUS => open,
+
+ FFS_CD_ALIGNED => open,
+ FFS_CD_FAILED => open,
+ BS4PAD_0 => open,
+ BS4PAD_1 => open,
+ BS4PAD_2 => open,
+ BS4PAD_3 => open,
+ FFC_SB_INV_RX_0 => fpsc_vlo,
+ FFC_SB_INV_RX_1 => fpsc_vlo,
+ FFC_SB_INV_RX_2 => fpsc_vlo,
+ FFC_SB_INV_RX_3 => fpsc_vlo,
+ TCK_FMAC => open,
+ TCK_FMACP => fpsc_vlo,
+ FF_SYSCLK_P1 => ref_pclk,
+ FF_RXCLK_P1 => rxa_pclk,
+ FF_RXCLK_P2 => rxb_pclk,
+ FFC_QUAD_RST => quad_rst,
+ FFS_RLOS_LO0 => open,
+ FFS_RLOS_LO1 => open,
+ FFS_RLOS_LO2 => open,
+ FFS_RLOS_LO3 => open,
+ COUT_21 => open,
+ COUT_20 => open,
+ COUT_19 => open,
+ COUT_18 => open,
+ COUT_17 => open,
+ COUT_16 => open,
+ COUT_15 => open,
+ COUT_14 => open,
+ COUT_13 => open,
+ COUT_12 => open,
+ COUT_11 => open,
+ COUT_10 => open,
+ COUT_9 => open,
+ COUT_8 => open,
+ COUT_7 => open,
+ COUT_6 => open,
+ COUT_5 => open,
+ COUT_4 => open,
+ COUT_3 => open,
+ COUT_2 => open,
+ COUT_1 => open,
+ COUT_0 => open,
+ CIN_12 => fpsc_vlo,
+ CIN_11 => fpsc_vlo,
+ CIN_10 => fpsc_vlo,
+ CIN_9 => fpsc_vlo,
+ CIN_8 => fpsc_vlo,
+ CIN_7 => fpsc_vlo,
+ CIN_6 => fpsc_vlo,
+ CIN_5 => fpsc_vlo,
+ CIN_4 => fpsc_vlo,
+ CIN_3 => fpsc_vlo,
+ CIN_2 => fpsc_vlo,
+ CIN_1 => fpsc_vlo,
+ CIN_0 => fpsc_vlo,
+ TESTCLK_MACO => fpsc_vlo,
+ FFC_MACRO_RST => serdes_rst);
+
+--synopsys translate_off
+file_read : PROCESS
+VARIABLE open_status : file_open_status;
+FILE config : text;
+BEGIN
+ file_open (open_status, config, USER_CONFIG_FILE, read_mode);
+ IF (open_status = name_error) THEN
+ report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!"
+ severity ERROR;
+ END IF;
+ wait;
+END PROCESS;
+--synopsys translate_on
+
+end serdes_gbe_0_100_ext_arch ;
-library ieee;
-use ieee.std_logic_1164.all;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-library work;
-use work.trb_net_std.all;
-
-package trb_net_components is
-
-
-
---This list of components is sorted alphabetically, ignoring the trb_net or trb_net16 prefix of some component names
-
-
-
-component trb_net16_med_scm_sfp_gbe is
-generic(
- SERDES_NUM : integer range 0 to 3 := 0; -- DO NOT CHANGE
- EXT_CLOCK : integer range 0 to 1 := c_NO; -- DO NOT CHANGE
- USE_200_MHZ: integer range 0 to 1 := c_YES -- DO NOT CHANGE
-);
-port(
- CLK : in std_logic; -- SerDes clock
- SYSCLK : in std_logic; -- fabric clock
- RESET : in std_logic; -- synchronous reset
- CLEAR : in std_logic; -- asynchronous reset
- CLK_EN : in std_logic;
- --Internal Connection
- MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
- MED_DATAREADY_IN : in std_logic;
- MED_READ_OUT : out std_logic;
- MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
- MED_DATAREADY_OUT : out std_logic;
- MED_READ_IN : in std_logic;
- REFCLK2CORE_OUT : out std_logic;
- --SFP Connection
- SD_RXD_P_IN : in std_logic;
- SD_RXD_N_IN : in std_logic;
- SD_TXD_P_OUT : out std_logic;
- SD_TXD_N_OUT : out std_logic;
- SD_REFCLK_P_IN : in std_logic;
- SD_REFCLK_N_IN : in std_logic;
- SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
- SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
- SD_TXDIS_OUT : out std_logic; -- SFP disable
- -- Status and control port
- STAT_OP : out std_logic_vector (15 downto 0);
- CTRL_OP : in std_logic_vector (15 downto 0);
- STAT_DEBUG : out std_logic_vector (63 downto 0);
- CTRL_DEBUG : in std_logic_vector (63 downto 0)
- );
-end component trb_net16_med_scm_sfp_gbe;
-
-
-
-
-
- component adc_ltc2308_readout is
- generic(
- CLOCK_FREQUENCY : integer := 100 --MHz
- );
- port(
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- ADC_SCK : out std_logic;
- ADC_SDI : out std_logic;
- ADC_SDO : in std_logic;
- ADC_CONVST : out std_logic;
-
- DAT_ADDR_IN : in std_logic_vector(5 downto 0);
- DAT_READ_EN_IN : in std_logic;
- DAT_WRITE_EN_IN : in std_logic;
- DAT_DATA_OUT : out std_logic_vector(31 downto 0);
- DAT_DATA_IN : in std_logic_vector(31 downto 0);
- DAT_DATAREADY_OUT : out std_logic;
- DAT_NO_MORE_DATA_OUT : out std_logic;
- DAT_WRITE_ACK_OUT : out std_logic;
- DAT_UNKNOWN_ADDR_OUT : out std_logic;
- DAT_TIMEOUT_IN : in std_logic;
-
- STAT_VOLTAGES_OUT : out std_logic_vector(31 downto 0)
- );
- end component;
-
-
-
-
-
-
- component trb_net16_addresses is
- generic(
- INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";
- INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876";
- INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222";
- INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"
- );
- port(
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- API_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
- API_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
- API_DATAREADY_IN : in std_logic;
- API_READ_OUT : out std_logic;
- RAM_DATA_IN : in std_logic_vector(15 downto 0);
- RAM_DATA_OUT : out std_logic_vector(15 downto 0);
- RAM_ADDR_IN : in std_logic_vector(2 downto 0);
- RAM_WR_IN : in std_logic;
- API_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
- API_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
- API_DATAREADY_OUT : out std_logic;
- API_READ_IN : in std_logic;
- ADDRESS_REJECTED : out std_logic;
- DONT_UNDERSTAND_OUT : out std_logic;
- API_SEND_OUT : out std_logic;
- ADDRESS_OUT : out std_logic_vector(15 downto 0);
- STAT_DEBUG : out std_logic_vector(15 downto 0)
- );
- end component;
-
-
-
-
-
-
- component trb_net16_api_base is
- generic (
- API_TYPE : integer range 0 to 1 := c_API_PASSIVE;
- FIFO_TO_INT_DEPTH : integer range 0 to 6 := 6;--std_FIFO_DEPTH;
- FIFO_TO_APL_DEPTH : integer range 1 to 6 := 6;--std_FIFO_DEPTH;
- FORCE_REPLY : integer range 0 to 1 := std_FORCE_REPLY;
- SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
- USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
- SECURE_MODE_TO_APL: integer range 0 to 1 := c_YES;
- SECURE_MODE_TO_INT: integer range 0 to 1 := c_YES;
- APL_WRITE_ALL_WORDS:integer range 0 to 1 := c_NO;
- ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF";
- BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF";
- BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF"
- );
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- -- APL Transmitter port
- APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- APL_DATAREADY_IN : in std_logic;
- APL_READ_OUT : out std_logic;
- APL_SHORT_TRANSFER_IN : in std_logic;
- APL_DTYPE_IN : in std_logic_vector (3 downto 0);
- APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0);
- APL_SEND_IN : in std_logic;
- APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0);-- the target (only for active APIs)
- -- Receiver port
- APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- APL_TYP_OUT : out std_logic_vector (2 downto 0);
- APL_DATAREADY_OUT : out std_logic;
- APL_READ_IN : in std_logic;
- -- APL Control port
- APL_RUN_OUT : out std_logic;
- APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0);
- APL_SEQNR_OUT : out std_logic_vector (7 downto 0);
- APL_LENGTH_IN : in std_logic_vector (15 downto 0);
- -- Internal direction port
- -- the ports with master or slave in their name are to be mapped by the active api
- -- to the init respectivly the reply path and vice versa in the passive api.
- -- lets define: the "master" path is the path that I send data on.
- -- master_data_out and slave_data_in are only used in active API for termination
- INT_MASTER_DATAREADY_OUT : out std_logic;
- INT_MASTER_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_MASTER_READ_IN : in std_logic;
- INT_MASTER_DATAREADY_IN : in std_logic;
- INT_MASTER_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_MASTER_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_MASTER_READ_OUT : out std_logic;
- INT_SLAVE_DATAREADY_OUT : out std_logic;
- INT_SLAVE_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_SLAVE_READ_IN : in std_logic;
- INT_SLAVE_DATAREADY_IN : in std_logic;
- INT_SLAVE_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_SLAVE_READ_OUT : out std_logic;
- -- Status and control port
- CTRL_SEQNR_RESET : in std_logic;
- STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0);
- STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0)
- );
- end component;
-
-
-
-
- component trb_net16_api_ipu_streaming is
- port(
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- -- Internal direction port
-
- FEE_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- FEE_INIT_DATAREADY_OUT : out std_logic;
- FEE_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- FEE_INIT_READ_IN : in std_logic;
-
- FEE_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- FEE_REPLY_DATAREADY_IN : in std_logic;
- FEE_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- FEE_REPLY_READ_OUT : out std_logic;
-
- CTS_INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- CTS_INIT_DATAREADY_IN : in std_logic;
- CTS_INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- CTS_INIT_READ_OUT : out std_logic;
-
- CTS_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- CTS_REPLY_DATAREADY_OUT : out std_logic;
- CTS_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- CTS_REPLY_READ_IN : in std_logic;
-
- --Event information coming from CTS
- CTS_NUMBER_OUT : out std_logic_vector (15 downto 0);
- CTS_CODE_OUT : out std_logic_vector (7 downto 0);
- CTS_INFORMATION_OUT : out std_logic_vector (7 downto 0);
- CTS_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0);
- CTS_START_READOUT_OUT : out std_logic;
-
- --Information sent to CTS
- --status data, equipped with DHDR
- CTS_DATA_IN : in std_logic_vector (31 downto 0);
- CTS_DATAREADY_IN : in std_logic;
- CTS_READOUT_FINISHED_IN : in std_logic; --no more data, end transfer, send TRM
- CTS_READ_OUT : out std_logic;
- CTS_LENGTH_IN : in std_logic_vector (15 downto 0);
- CTS_STATUS_BITS_IN : in std_logic_vector (31 downto 0);
-
- -- Data from Frontends
- FEE_DATA_OUT : out std_logic_vector (15 downto 0);
- FEE_DATAREADY_OUT : out std_logic;
- FEE_READ_IN : in std_logic; --must be high when idle, otherwise you will never get a dataready
- FEE_STATUS_BITS_OUT : out std_logic_vector (31 downto 0);
- FEE_BUSY_OUT : out std_logic;
-
- MY_ADDRESS_IN : in std_logic_vector (15 downto 0);
- CTRL_SEQNR_RESET : in std_logic
-
- );
- end component;
-
-
-
-
-
- component trb_net_CRC is
- port(
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- DATA_IN : in std_logic_vector(15 downto 0);
- CRC_OUT : out std_logic_vector(15 downto 0);
- CRC_match : out std_logic
- );
- end component;
-
-
- component trb_net_CRC8 is
- port(
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- DATA_IN : in std_logic_vector(7 downto 0);
- CRC_OUT : out std_logic_vector(7 downto 0);
- CRC_match : out std_logic
- );
- end component;
-
- component ddr_off is
- port (
- Clk: in std_logic;
- Data: in std_logic_vector(1 downto 0);
- Q: out std_logic_vector(0 downto 0)
- );
- end component;
-
-
-
- component dll_in100_out100 is
- port (
- clk: in std_logic;
- aluhold: in std_logic;
- clkop: out std_logic;
- clkos: out std_logic;
- lock: out std_logic
- );
- end component;
-
-
- component dll_in200_out100 is
- port (
- clk: in std_logic;
- aluhold: in std_logic;
- clkop: out std_logic;
- clkos: out std_logic;
- lock: out std_logic
- );
- end component;
-
-
- component trb_net16_dummy_fifo is
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0);
- PACKET_NUM_IN : in std_logic_vector(1 downto 0);
- WRITE_ENABLE_IN : in std_logic;
- DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0);
- PACKET_NUM_OUT : out std_logic_vector(1 downto 0);
- READ_ENABLE_IN : in std_logic;
- FULL_OUT : out std_logic;
- EMPTY_OUT : out std_logic
- );
- end component;
-
-
-
-
-
- component trb_net16_endpoint_hades_full is
- generic (
- USE_CHANNEL : channel_config_t := (c_YES,c_YES,c_NO,c_YES);
- IBUF_DEPTH : channel_config_t := (6,6,6,6);
- FIFO_TO_INT_DEPTH : channel_config_t := (6,6,6,6);
- FIFO_TO_APL_DEPTH : channel_config_t := (1,1,1,1);
- IBUF_SECURE_MODE : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
- API_SECURE_MODE_TO_APL : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
- API_SECURE_MODE_TO_INT : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
- OBUF_DATA_COUNT_WIDTH : integer range 0 to 7 := std_DATA_COUNT_WIDTH;
- INIT_CAN_SEND_DATA : channel_config_t := (c_NO,c_NO,c_NO,c_NO);
- REPLY_CAN_SEND_DATA : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
- REPLY_CAN_RECEIVE_DATA : channel_config_t := (c_NO,c_NO,c_NO,c_NO);
- USE_CHECKSUM : channel_config_t := (c_NO,c_YES,c_YES,c_YES);
- APL_WRITE_ALL_WORDS : channel_config_t := (c_NO,c_NO,c_NO,c_NO);
- ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF";
- BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF";
- BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF";
- TIMING_TRIGGER_RAW : integer range 0 to 1 := c_YES;
- REGIO_NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers
- REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers
- --standard values for output registers
- REGIO_INIT_CTRL_REGS : std_logic_vector(2**(4)*32-1 downto 0) := (others => '0');
- --set to 0 for unused ctrl registers to save resources
- REGIO_USED_CTRL_REGS : std_logic_vector(2**(4)-1 downto 0) := (others => '1');
- --set to 0 for each unused bit in a register
- REGIO_USED_CTRL_BITMASK : std_logic_vector(2**(4)*32-1 downto 0) := (others => '1');
- REGIO_USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port
- REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";
- REGIO_INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876";
- REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222";
- REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001";
- REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
- REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";
- REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";
- REGIO_USE_1WIRE_INTERFACE : integer := c_YES; --c_YES,c_NO,c_MONITOR
- REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO;
- CLOCK_FREQUENCY : integer range 1 to 200 := 100
- );
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic := '1';
-
- -- Media direction port
- MED_DATAREADY_OUT : out std_logic;
- MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_READ_IN : in std_logic;
- MED_DATAREADY_IN : in std_logic;
- MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_READ_OUT : out std_logic;
- MED_STAT_OP_IN : in std_logic_vector(15 downto 0);
- MED_CTRL_OP_OUT : out std_logic_vector(15 downto 0);
-
- -- LVL1 trigger APL
- TRG_TIMING_TRG_RECEIVED_IN : in std_logic; --strobe when timing trigger received
-
- LVL1_TRG_DATA_VALID_OUT : out std_logic; --trigger type, number, code, information are valid
- LVL1_TRG_VALID_TIMING_OUT : out std_logic; --valid timing trigger has been received
- LVL1_TRG_VALID_NOTIMING_OUT : out std_logic; --valid trigger without timing trigger has been received
- LVL1_TRG_INVALID_OUT : out std_logic; --the current trigger is invalid (e.g. no timing trigger, no LVL1...)
-
- LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0);
- LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0);
- LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0);
- LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0);
-
- LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0) := x"00000000";
- LVL1_TRG_RELEASE_IN : in std_logic := '0';
- LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); --internally generated trigger number, for informational uses only
-
- --Information about trigger handler errors
- TRG_MULTIPLE_TRG_OUT : out std_logic;
- TRG_TIMEOUT_DETECTED_OUT : out std_logic;
- TRG_SPURIOUS_TRG_OUT : out std_logic;
- TRG_MISSING_TMG_TRG_OUT : out std_logic;
- TRG_SPIKE_DETECTED_OUT : out std_logic;
- --Data Port
- IPU_NUMBER_OUT : out std_logic_vector (15 downto 0);
- IPU_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0);
- IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0);
- --start strobe
- IPU_START_READOUT_OUT : out std_logic;
- --detector data, equipped with DHDR
- IPU_DATA_IN : in std_logic_vector (31 downto 0);
- IPU_DATAREADY_IN : in std_logic;
- --no more data, end transfer, send TRM
- IPU_READOUT_FINISHED_IN : in std_logic;
- --will be low every second cycle due to 32bit -> 16bit conversion
- IPU_READ_OUT : out std_logic;
- IPU_LENGTH_IN : in std_logic_vector (15 downto 0);
- IPU_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0);
-
-
- -- Slow Control Data Port
- REGIO_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
- REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);
- REGIO_REGISTERS_IN : in std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0');
- REGIO_REGISTERS_OUT : out std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
- COMMON_STAT_REG_STROBE : out std_logic_vector(std_COMSTATREG-1 downto 0);
- COMMON_CTRL_REG_STROBE : out std_logic_vector(std_COMCTRLREG-1 downto 0);
- STAT_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0);
- CTRL_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
- --following ports only used when using internal data port
- REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0);
- REGIO_READ_ENABLE_OUT : out std_logic;
- REGIO_WRITE_ENABLE_OUT : out std_logic;
- REGIO_DATA_OUT : out std_logic_vector(32-1 downto 0);
- REGIO_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0');
- REGIO_DATAREADY_IN : in std_logic := '0';
- REGIO_NO_MORE_DATA_IN : in std_logic := '0';
- REGIO_WRITE_ACK_IN : in std_logic := '0';
- REGIO_UNKNOWN_ADDR_IN : in std_logic := '0';
- REGIO_TIMEOUT_OUT : out std_logic;
- --IDRAM is used if no 1-wire interface, onewire used otherwise
- REGIO_IDRAM_DATA_IN : in std_logic_vector(15 downto 0) := (others => '0');
- REGIO_IDRAM_DATA_OUT : out std_logic_vector(15 downto 0);
- REGIO_IDRAM_ADDR_IN : in std_logic_vector(2 downto 0) := "000";
- REGIO_IDRAM_WR_IN : in std_logic := '0';
- REGIO_ONEWIRE_INOUT : inout std_logic; --temperature sensor
- REGIO_ONEWIRE_MONITOR_IN : in std_logic := '0';
- REGIO_ONEWIRE_MONITOR_OUT : out std_logic;
- REGIO_VAR_ENDPOINT_ID : in std_logic_vector(15 downto 0) := (others => '0');
-
- GLOBAL_TIME_OUT : out std_logic_vector(31 downto 0); --global time, microseconds
- LOCAL_TIME_OUT : out std_logic_vector(7 downto 0); --local time running with chip frequency
- TIME_SINCE_LAST_TRG_OUT : out std_logic_vector(31 downto 0); --local time, resetted with each trigger
- TIMER_TICKS_OUT : out std_logic_vector(1 downto 0); --bit 1 ms-tick, 0 us-tick
- --Debugging & Status information
- STAT_DEBUG_IPU : out std_logic_vector (31 downto 0);
- STAT_DEBUG_1 : out std_logic_vector (31 downto 0);
- STAT_DEBUG_2 : out std_logic_vector (31 downto 0);
- MED_STAT_OP : out std_logic_vector (15 downto 0);
- CTRL_MPLEX : in std_logic_vector (31 downto 0) := (others => '0');
- IOBUF_CTRL_GEN : in std_logic_vector (4*32-1 downto 0) := (others => '0');
- STAT_ONEWIRE : out std_logic_vector (31 downto 0);
- STAT_ADDR_DEBUG : out std_logic_vector (15 downto 0);
- DEBUG_LVL1_HANDLER_OUT : out std_logic_vector (15 downto 0)
- );
- end component;
-
-
- component trb_net16_endpoint_hades_full_handler is
- generic (
- IBUF_DEPTH : channel_config_t := (6,6,6,6);
- FIFO_TO_INT_DEPTH : channel_config_t := (6,6,6,6);
- FIFO_TO_APL_DEPTH : channel_config_t := (1,1,1,1);
- APL_WRITE_ALL_WORDS : channel_config_t := (c_NO,c_NO,c_NO,c_NO);
- ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF";
- BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF";
- BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF";
- REGIO_NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers
- REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers
- REGIO_INIT_CTRL_REGS : std_logic_vector(16*32-1 downto 0) := (others => '0');
- REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";
- REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222";
- REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001";
- REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
- REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";
- REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";
- REGIO_USE_1WIRE_INTERFACE : integer := c_YES; --c_YES,c_NO,c_MONITOR
- REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO;
- TIMING_TRIGGER_RAW : integer range 0 to 1 := c_YES;
- CLOCK_FREQUENCY : integer range 1 to 200 := 100;
- --Configure data handler
- DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1;
- DATA_BUFFER_DEPTH : integer range 9 to 14 := 9;
- DATA_BUFFER_WIDTH : integer range 1 to 32 := 31;
- DATA_BUFFER_FULL_THRESH : integer range 0 to 2**14-2 := 2**8;
- TRG_RELEASE_AFTER_DATA : integer range 0 to 1 := c_YES;
- HEADER_BUFFER_DEPTH : integer range 9 to 14 := 9;
- HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-2 := 2**8
- );
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic := '1';
-
- -- Media direction port
- MED_DATAREADY_OUT : out std_logic;
- MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_READ_IN : in std_logic;
- MED_DATAREADY_IN : in std_logic;
- MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_READ_OUT : out std_logic;
- MED_STAT_OP_IN : in std_logic_vector(15 downto 0);
- MED_CTRL_OP_OUT : out std_logic_vector(15 downto 0);
-
- --Timing trigger in
- TRG_TIMING_TRG_RECEIVED_IN : in std_logic;
- --LVL1 trigger to FEE
- LVL1_TRG_DATA_VALID_OUT : out std_logic; --trigger type, number, code, information are valid
- LVL1_VALID_TIMING_TRG_OUT : out std_logic; --valid timing trigger has been received
- LVL1_VALID_NOTIMING_TRG_OUT : out std_logic; --valid trigger without timing trigger has been received
- LVL1_INVALID_TRG_OUT : out std_logic; --the current trigger is invalid (e.g. no timing trigger, no LVL1...)
-
- LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0);
- LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0);
- LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0);
- LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0);
- LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); --internally generated trigger number, for informational uses only
-
- --Response from FEE
- FEE_TRG_RELEASE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
- FEE_TRG_STATUSBITS_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);
- FEE_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);
- FEE_DATA_WRITE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
- FEE_DATA_FINISHED_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
- FEE_DATA_ALMOST_FULL_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
-
- --Information about trigger handler errors
- TRG_MULTIPLE_TRG_OUT : out std_logic;
- TRG_TIMEOUT_DETECTED_OUT : out std_logic;
- TRG_SPURIOUS_TRG_OUT : out std_logic;
- TRG_MISSING_TMG_TRG_OUT : out std_logic;
- TRG_SPIKE_DETECTED_OUT : out std_logic;
-
- --Slow Control Port
- --common registers
- REGIO_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
- REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);
- REGIO_COMMON_STAT_STROBE_OUT : out std_logic_vector(std_COMSTATREG-1 downto 0);
- REGIO_COMMON_CTRL_STROBE_OUT : out std_logic_vector(std_COMCTRLREG-1 downto 0);
- --user defined registers
- REGIO_STAT_REG_IN : in std_logic_vector(2**(REGIO_NUM_STAT_REGS)*32-1 downto 0) := (others => '0');
- REGIO_CTRL_REG_OUT : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)*32-1 downto 0);
- REGIO_STAT_STROBE_OUT : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0);
- REGIO_CTRL_STROBE_OUT : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
- --internal data port
- BUS_ADDR_OUT : out std_logic_vector(16-1 downto 0);
- BUS_DATA_OUT : out std_logic_vector(32-1 downto 0);
- BUS_READ_ENABLE_OUT : out std_logic;
- BUS_WRITE_ENABLE_OUT : out std_logic;
- BUS_TIMEOUT_OUT : out std_logic;
- BUS_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0');
- BUS_DATAREADY_IN : in std_logic := '0';
- BUS_WRITE_ACK_IN : in std_logic := '0';
- BUS_NO_MORE_DATA_IN : in std_logic := '0';
- BUS_UNKNOWN_ADDR_IN : in std_logic := '0';
- --Onewire
- ONEWIRE_INOUT : inout std_logic; --temperature sensor
- ONEWIRE_MONITOR_IN : in std_logic := '0';
- ONEWIRE_MONITOR_OUT : out std_logic;
- --Config endpoint id, if not statically assigned
- REGIO_VAR_ENDPOINT_ID : in std_logic_vector (15 downto 0) := (others => '0');
-
- --Timing registers
- TIME_GLOBAL_OUT : out std_logic_vector (31 downto 0); --global time, microseconds
- TIME_LOCAL_OUT : out std_logic_vector ( 7 downto 0); --local time running with chip frequency
- TIME_SINCE_LAST_TRG_OUT : out std_logic_vector (31 downto 0); --local time, resetted with each trigger
- TIME_TICKS_OUT : out std_logic_vector ( 1 downto 0); --bit 1 ms-tick, 0 us-tick
-
- --Debugging & Status information
- STAT_DEBUG_IPU : out std_logic_vector (31 downto 0);
- STAT_DEBUG_1 : out std_logic_vector (31 downto 0);
- STAT_DEBUG_2 : out std_logic_vector (31 downto 0);
- STAT_DEBUG_DATA_HANDLER_OUT : out std_logic_vector (31 downto 0);
- STAT_DEBUG_IPU_HANDLER_OUT : out std_logic_vector (31 downto 0);
- CTRL_MPLEX : in std_logic_vector (31 downto 0) := (others => '0');
- IOBUF_CTRL_GEN : in std_logic_vector (4*32-1 downto 0) := (others => '0');
- STAT_ONEWIRE : out std_logic_vector (31 downto 0);
- STAT_ADDR_DEBUG : out std_logic_vector (15 downto 0);
- DEBUG_LVL1_HANDLER_OUT : out std_logic_vector (15 downto 0)
- );
- end component;
-
- component trb_net16_endpoint_hades_cts is
- generic(
- USE_CHANNEL : channel_config_t := (c_YES,c_YES,c_NO,c_YES);
- IBUF_DEPTH : channel_config_t := (1,6,6,6);
- FIFO_TO_INT_DEPTH : channel_config_t := (1,1,6,6);
- FIFO_TO_APL_DEPTH : channel_config_t := (1,6,6,6);
- INIT_CAN_SEND_DATA : channel_config_t := (c_YES,c_YES,c_NO,c_NO);
- REPLY_CAN_SEND_DATA : channel_config_t := (c_NO,c_NO,c_NO,c_YES);
- REPLY_CAN_RECEIVE_DATA : channel_config_t := (c_YES,c_YES,c_NO,c_NO);
- USE_CHECKSUM : channel_config_t := (c_NO,c_YES,c_YES,c_YES);
- APL_WRITE_ALL_WORDS : channel_config_t := (c_NO,c_NO,c_NO,c_NO);
- ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF";
- BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF";
- REGIO_NUM_STAT_REGS : integer range 0 to 6 := 2; --log2 of number of status registers
- REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers
- --standard values for output registers
- REGIO_INIT_CTRL_REGS : std_logic_vector(2**(4)*32-1 downto 0) := (others => '0');
- --set to 0 for unused ctrl registers to save resources
- REGIO_USED_CTRL_REGS : std_logic_vector(2**(4)-1 downto 0) := x"0001";
- --set to 0 for each unused bit in a register
- REGIO_USED_CTRL_BITMASK : std_logic_vector(2**(4)*32-1 downto 0) := (others => '1');
- REGIO_USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port
- REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";
- REGIO_INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"0000_0000_0000_0000";
- REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"0000_0000";
- REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001";
- REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
- REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";
- REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"50000000";
- REGIO_USE_1WIRE_INTERFACE: integer := c_YES; --c_YES,c_NO,c_MONITOR
- REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO;
- CLOCK_FREQUENCY : integer range 1 to 200 := 100
- );
- port(
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- -- Media direction port
- MED_DATAREADY_OUT : out std_logic;
- MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_READ_IN : in std_logic;
-
- MED_DATAREADY_IN : in std_logic;
- MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_READ_OUT : out std_logic;
-
- MED_STAT_OP_IN : in std_logic_vector(15 downto 0);
- MED_CTRL_OP_OUT : out std_logic_vector(15 downto 0);
-
- --LVL1 trigger
- TRG_SEND_IN : in std_logic;
- TRG_TYPE_IN : in std_logic_vector (3 downto 0);
- TRG_NUMBER_IN : in std_logic_vector (15 downto 0);
- TRG_INFORMATION_IN : in std_logic_vector (23 downto 0);
- TRG_RND_CODE_IN : in std_logic_vector (7 downto 0);
- TRG_STATUS_BITS_OUT : out std_logic_vector (31 downto 0);
- TRG_BUSY_OUT : out std_logic;
-
- --IPU Channel
- IPU_SEND_IN : in std_logic;
- IPU_TYPE_IN : in std_logic_vector (3 downto 0);
- IPU_NUMBER_IN : in std_logic_vector (15 downto 0);
- IPU_INFORMATION_IN : in std_logic_vector (7 downto 0);
- IPU_RND_CODE_IN : in std_logic_vector (7 downto 0);
- -- Receiver port
- IPU_DATA_OUT : out std_logic_vector (31 downto 0);
- IPU_DATAREADY_OUT : out std_logic;
- IPU_READ_IN : in std_logic;
- IPU_STATUS_BITS_OUT : out std_logic_vector (31 downto 0);
- IPU_BUSY_OUT : out std_logic;
-
- -- Slow Control Data Port
- REGIO_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
- REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);
- REGIO_REGISTERS_IN : in std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0');
- REGIO_REGISTERS_OUT : out std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
- COMMON_STAT_REG_STROBE : out std_logic_vector(std_COMSTATREG-1 downto 0);
- COMMON_CTRL_REG_STROBE : out std_logic_vector(std_COMCTRLREG-1 downto 0);
- STAT_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0);
- CTRL_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
- --following ports only used when using internal data port
- REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0);
- REGIO_READ_ENABLE_OUT : out std_logic;
- REGIO_WRITE_ENABLE_OUT : out std_logic;
- REGIO_DATA_OUT : out std_logic_vector(32-1 downto 0);
- REGIO_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0');
- REGIO_DATAREADY_IN : in std_logic := '0';
- REGIO_NO_MORE_DATA_IN : in std_logic := '0';
- REGIO_WRITE_ACK_IN : in std_logic := '0';
- REGIO_UNKNOWN_ADDR_IN : in std_logic := '0';
- REGIO_TIMEOUT_OUT : out std_logic;
- REGIO_ONEWIRE_INOUT : inout std_logic;
- REGIO_ONEWIRE_MONITOR_OUT : out std_logic;
- REGIO_ONEWIRE_MONITOR_IN : in std_logic;
- REGIO_VAR_ENDPOINT_ID : in std_logic_vector(15 downto 0) := (others => '0');
- TRIGGER_MONITOR_IN : in std_logic := '0'; --strobe when timing trigger received
- GLOBAL_TIME_OUT : out std_logic_vector(31 downto 0); --global time, microseconds
- LOCAL_TIME_OUT : out std_logic_vector(7 downto 0); --local time running with chip frequency
- TIME_SINCE_LAST_TRG_OUT : out std_logic_vector(31 downto 0); --local time, resetted with each trigger
- TIMER_TICKS_OUT : out std_logic_vector(1 downto 0); --bit 1 ms-tick, 0 us-tick
- STAT_DEBUG_1 : out std_logic_vector(31 downto 0);
- STAT_DEBUG_2 : out std_logic_vector(31 downto 0)
- );
-
- end component;
-
-
-
-
- component etrax_interface is
- generic(
- STATUS_REGISTERS : integer := 4;
- CONTROL_REGISTERS : integer := 4
- );
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- --Connection to Etrax
- ETRAX_DATA_BUS_B : out std_logic_vector(17 downto 0);
- ETRAX_DATA_BUS_C : in std_logic_vector(17 downto 0);
- ETRAX_BUS_BUSY : out std_logic;
- --Connection to internal FPGA logic (all addresses above 0x100)
- INTERNAL_DATA_OUT : out std_logic_vector(31 downto 0);
- INTERNAL_DATA_IN : in std_logic_vector(31 downto 0);
- INTERNAL_READ_OUT : out std_logic;
- INTERNAL_WRITE_OUT : out std_logic;
- INTERNAL_DATAREADY_IN : in std_logic;
- INTERNAL_ADDRESS_OUT : out std_logic_vector(15 downto 0);
- --Easy-to-use status and control registers (Addresses 0-15 (stat) and 16-31 (ctrl)
- FPGA_REGISTER_IN : in std_logic_vector(STATUS_REGISTERS*32-1 downto 0);
- FPGA_REGISTER_OUT : out std_logic_vector(CONTROL_REGISTERS*32-1 downto 0);
- --Reset FPGA via Etrax
- EXTERNAL_RESET : out std_logic;
- STAT : out std_logic_vector(15 downto 0)
- );
- end component;
-
-
-
-
-
-
-
-
- component trb_net16_fifo is
- generic (
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+USE IEEE.numeric_std.ALL;\r
+USE IEEE.std_logic_UNSIGNED.ALL;\r
+library work;\r
+use work.trb_net_std.all;\r
+\r
+package trb_net_components is\r
+\r
+\r
+\r
+--This list of components is sorted alphabetically, ignoring the trb_net or trb_net16 prefix of some component names\r
+\r
+\r
+\r
+component trb_net16_med_scm_sfp_gbe is\r
+generic(\r
+ SERDES_NUM : integer range 0 to 3 := 0; -- DO NOT CHANGE\r
+ EXT_CLOCK : integer range 0 to 1 := c_NO; -- DO NOT CHANGE\r
+ USE_200_MHZ: integer range 0 to 1 := c_YES -- DO NOT CHANGE\r
+);\r
+port(\r
+ CLK : in std_logic; -- SerDes clock\r
+ SYSCLK : in std_logic; -- fabric clock\r
+ RESET : in std_logic; -- synchronous reset\r
+ CLEAR : in std_logic; -- asynchronous reset\r
+ CLK_EN : in std_logic;\r
+ --Internal Connection\r
+ MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ MED_DATAREADY_IN : in std_logic;\r
+ MED_READ_OUT : out std_logic;\r
+ MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ MED_DATAREADY_OUT : out std_logic;\r
+ MED_READ_IN : in std_logic;\r
+ REFCLK2CORE_OUT : out std_logic;\r
+ --SFP Connection\r
+ SD_RXD_P_IN : in std_logic;\r
+ SD_RXD_N_IN : in std_logic;\r
+ SD_TXD_P_OUT : out std_logic;\r
+ SD_TXD_N_OUT : out std_logic;\r
+ SD_REFCLK_P_IN : in std_logic;\r
+ SD_REFCLK_N_IN : in std_logic;\r
+ SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)\r
+ SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)\r
+ SD_TXDIS_OUT : out std_logic; -- SFP disable\r
+ -- Status and control port\r
+ STAT_OP : out std_logic_vector (15 downto 0);\r
+ CTRL_OP : in std_logic_vector (15 downto 0);\r
+ STAT_DEBUG : out std_logic_vector (63 downto 0);\r
+ CTRL_DEBUG : in std_logic_vector (63 downto 0)\r
+ );\r
+end component trb_net16_med_scm_sfp_gbe;\r
+\r
+\r
+\r
+\r
+\r
+ component adc_ltc2308_readout is\r
+ generic(\r
+ CLOCK_FREQUENCY : integer := 100 --MHz\r
+ );\r
+ port(\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+\r
+ ADC_SCK : out std_logic;\r
+ ADC_SDI : out std_logic;\r
+ ADC_SDO : in std_logic;\r
+ ADC_CONVST : out std_logic;\r
+\r
+ DAT_ADDR_IN : in std_logic_vector(5 downto 0);\r
+ DAT_READ_EN_IN : in std_logic;\r
+ DAT_WRITE_EN_IN : in std_logic;\r
+ DAT_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ DAT_DATA_IN : in std_logic_vector(31 downto 0);\r
+ DAT_DATAREADY_OUT : out std_logic;\r
+ DAT_NO_MORE_DATA_OUT : out std_logic;\r
+ DAT_WRITE_ACK_OUT : out std_logic;\r
+ DAT_UNKNOWN_ADDR_OUT : out std_logic;\r
+ DAT_TIMEOUT_IN : in std_logic;\r
+\r
+ STAT_VOLTAGES_OUT : out std_logic_vector(31 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net16_addresses is\r
+ generic(\r
+ INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";\r
+ INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876";\r
+ INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222";\r
+ INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"\r
+ );\r
+ port(\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ API_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
+ API_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ API_DATAREADY_IN : in std_logic;\r
+ API_READ_OUT : out std_logic;\r
+ RAM_DATA_IN : in std_logic_vector(15 downto 0);\r
+ RAM_DATA_OUT : out std_logic_vector(15 downto 0);\r
+ RAM_ADDR_IN : in std_logic_vector(2 downto 0);\r
+ RAM_WR_IN : in std_logic;\r
+ API_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
+ API_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ API_DATAREADY_OUT : out std_logic;\r
+ API_READ_IN : in std_logic;\r
+ ADDRESS_REJECTED : out std_logic;\r
+ DONT_UNDERSTAND_OUT : out std_logic;\r
+ API_SEND_OUT : out std_logic;\r
+ ADDRESS_OUT : out std_logic_vector(15 downto 0);\r
+ STAT_DEBUG : out std_logic_vector(15 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net16_api_base is\r
+ generic (\r
+ API_TYPE : integer range 0 to 1 := c_API_PASSIVE;\r
+ FIFO_TO_INT_DEPTH : integer range 0 to 6 := 6;--std_FIFO_DEPTH;\r
+ FIFO_TO_APL_DEPTH : integer range 1 to 6 := 6;--std_FIFO_DEPTH;\r
+ FORCE_REPLY : integer range 0 to 1 := std_FORCE_REPLY;\r
+ SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;\r
+ USE_VENDOR_CORES : integer range 0 to 1 := c_YES;\r
+ SECURE_MODE_TO_APL: integer range 0 to 1 := c_YES;\r
+ SECURE_MODE_TO_INT: integer range 0 to 1 := c_YES;\r
+ APL_WRITE_ALL_WORDS:integer range 0 to 1 := c_NO;\r
+ ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF";\r
+ BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF";\r
+ BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF"\r
+ );\r
+\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+\r
+ -- APL Transmitter port\r
+ APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ APL_DATAREADY_IN : in std_logic;\r
+ APL_READ_OUT : out std_logic;\r
+ APL_SHORT_TRANSFER_IN : in std_logic;\r
+ APL_DTYPE_IN : in std_logic_vector (3 downto 0);\r
+ APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0);\r
+ APL_SEND_IN : in std_logic;\r
+ APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0);-- the target (only for active APIs)\r
+ -- Receiver port\r
+ APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ APL_TYP_OUT : out std_logic_vector (2 downto 0);\r
+ APL_DATAREADY_OUT : out std_logic;\r
+ APL_READ_IN : in std_logic;\r
+ -- APL Control port\r
+ APL_RUN_OUT : out std_logic;\r
+ APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0);\r
+ APL_SEQNR_OUT : out std_logic_vector (7 downto 0);\r
+ APL_LENGTH_IN : in std_logic_vector (15 downto 0);\r
+ -- Internal direction port\r
+ -- the ports with master or slave in their name are to be mapped by the active api\r
+ -- to the init respectivly the reply path and vice versa in the passive api.\r
+ -- lets define: the "master" path is the path that I send data on.\r
+ -- master_data_out and slave_data_in are only used in active API for termination\r
+ INT_MASTER_DATAREADY_OUT : out std_logic;\r
+ INT_MASTER_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ INT_MASTER_READ_IN : in std_logic;\r
+ INT_MASTER_DATAREADY_IN : in std_logic;\r
+ INT_MASTER_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ INT_MASTER_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ INT_MASTER_READ_OUT : out std_logic;\r
+ INT_SLAVE_DATAREADY_OUT : out std_logic;\r
+ INT_SLAVE_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ INT_SLAVE_READ_IN : in std_logic;\r
+ INT_SLAVE_DATAREADY_IN : in std_logic;\r
+ INT_SLAVE_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ INT_SLAVE_READ_OUT : out std_logic;\r
+ -- Status and control port\r
+ CTRL_SEQNR_RESET : in std_logic;\r
+ STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0);\r
+ STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+ component trb_net16_api_ipu_streaming is\r
+ port(\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+\r
+ -- Internal direction port\r
+\r
+ FEE_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ FEE_INIT_DATAREADY_OUT : out std_logic;\r
+ FEE_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ FEE_INIT_READ_IN : in std_logic;\r
+\r
+ FEE_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ FEE_REPLY_DATAREADY_IN : in std_logic;\r
+ FEE_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ FEE_REPLY_READ_OUT : out std_logic;\r
+\r
+ CTS_INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ CTS_INIT_DATAREADY_IN : in std_logic;\r
+ CTS_INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ CTS_INIT_READ_OUT : out std_logic;\r
+\r
+ CTS_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ CTS_REPLY_DATAREADY_OUT : out std_logic;\r
+ CTS_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ CTS_REPLY_READ_IN : in std_logic;\r
+\r
+ --Event information coming from CTS\r
+ CTS_NUMBER_OUT : out std_logic_vector (15 downto 0);\r
+ CTS_CODE_OUT : out std_logic_vector (7 downto 0);\r
+ CTS_INFORMATION_OUT : out std_logic_vector (7 downto 0);\r
+ CTS_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0);\r
+ CTS_START_READOUT_OUT : out std_logic;\r
+\r
+ --Information sent to CTS\r
+ --status data, equipped with DHDR\r
+ CTS_DATA_IN : in std_logic_vector (31 downto 0);\r
+ CTS_DATAREADY_IN : in std_logic;\r
+ CTS_READOUT_FINISHED_IN : in std_logic; --no more data, end transfer, send TRM\r
+ CTS_READ_OUT : out std_logic;\r
+ CTS_LENGTH_IN : in std_logic_vector (15 downto 0);\r
+ CTS_STATUS_BITS_IN : in std_logic_vector (31 downto 0);\r
+\r
+ -- Data from Frontends\r
+ FEE_DATA_OUT : out std_logic_vector (15 downto 0);\r
+ FEE_DATAREADY_OUT : out std_logic;\r
+ FEE_READ_IN : in std_logic; --must be high when idle, otherwise you will never get a dataready\r
+ FEE_STATUS_BITS_OUT : out std_logic_vector (31 downto 0);\r
+ FEE_BUSY_OUT : out std_logic;\r
+\r
+ MY_ADDRESS_IN : in std_logic_vector (15 downto 0);\r
+ CTRL_SEQNR_RESET : in std_logic\r
+\r
+ );\r
+ end component;\r
+\r
+\r
+ component trb_net_bridge_pcie_apl is\r
+ port(\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+\r
+ --TrbNet connect\r
+ APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_DATAREADY_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_READ_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_SHORT_TRANSFER_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_DTYPE_OUT : out std_logic_vector (4*2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_ERROR_PATTERN_OUT : out std_logic_vector (32*2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_SEND_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_TARGET_ADDRESS_OUT : out std_logic_vector (16*2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH*2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_TYP_IN : in std_logic_vector (3*2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_DATAREADY_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_READ_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_RUN_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_SEQNR_IN : in std_logic_vector (8*2**(c_MUX_WIDTH)-1 downto 0);\r
+\r
+ --Internal Data Bus\r
+ BUS_ADDR_IN : in std_logic_vector(31 downto 0);\r
+ BUS_WDAT_IN : in std_logic_vector(63 downto 0);\r
+ BUS_RDAT_OUT : out std_logic_vector(63 downto 0);\r
+ BUS_SEL_IN : in std_logic_vector(7 downto 0);\r
+ BUS_WE_IN : in std_logic;\r
+ BUS_CYC_IN : in std_logic;\r
+ BUS_STB_IN : in std_logic;\r
+ BUS_LOCK_IN : in std_logic;\r
+ BUS_CTI_IN : in std_logic_vector(2 downto 0);\r
+ BUS_ACK_OUT : out std_logic;\r
+\r
+ EXT_TRIGGER_INFO : out std_logic_vector(15 downto 0);\r
+ SEND_RESET_OUT : out std_logic;\r
+ --DMA interface\r
+\r
+ --Debug\r
+ STAT : out std_logic_vector (31 downto 0);\r
+ CTRL : in std_logic_vector (31 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+ component trb_net_bridge_pcie_endpoint is\r
+ generic(\r
+ USE_CHANNELS : channel_config_t := (c_YES,c_YES,c_NO,c_YES);\r
+ AUTO_ANSWER_INCOMING_REQUESTS : channel_config_t := (c_NO,c_NO,c_NO,c_NO)\r
+ );\r
+ port(\r
+ RESET : in std_logic;\r
+ CLK: in std_logic;\r
+\r
+ BUS_ADDR_IN : in std_logic_vector(31 downto 0);\r
+ BUS_WDAT_IN : in std_logic_vector(63 downto 0);\r
+ BUS_RDAT_OUT : out std_logic_vector(63 downto 0);\r
+ BUS_SEL_IN : in std_logic_vector(7 downto 0);\r
+ BUS_WE_IN : in std_logic;\r
+ BUS_CYC_IN : in std_logic;\r
+ BUS_STB_IN : in std_logic;\r
+ BUS_LOCK_IN : in std_logic;\r
+ BUS_CTI_IN : in std_logic_vector(2 downto 0);\r
+ BUS_ACK_OUT : out std_logic;\r
+\r
+ MED_DATAREADY_IN : in STD_LOGIC;\r
+ MED_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);\r
+ MED_READ_OUT : out STD_LOGIC;\r
+\r
+ MED_DATAREADY_OUT : out STD_LOGIC;\r
+ MED_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);\r
+ MED_READ_IN : in STD_LOGIC;\r
+\r
+ MED_ERROR_IN : in std_logic_vector(2 downto 0);\r
+ SEND_RESET_OUT : out std_logic;\r
+ STAT : out std_logic_vector(31 downto 0);\r
+ STAT_ENDP : out std_logic_vector(31 downto 0);\r
+ STAT_API1 : out std_logic_vector(31 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+ component trb_net_CRC is\r
+ port(\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ DATA_IN : in std_logic_vector(15 downto 0);\r
+ CRC_OUT : out std_logic_vector(15 downto 0);\r
+ CRC_match : out std_logic\r
+ );\r
+ end component;\r
+\r
+\r
+ component trb_net_CRC8 is\r
+ port(\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ DATA_IN : in std_logic_vector(7 downto 0);\r
+ CRC_OUT : out std_logic_vector(7 downto 0);\r
+ CRC_match : out std_logic\r
+ );\r
+ end component;\r
+\r
+ component ddr_off is\r
+ port (\r
+ Clk: in std_logic;\r
+ Data: in std_logic_vector(1 downto 0);\r
+ Q: out std_logic_vector(0 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+ component dll_in100_out100 is\r
+ port (\r
+ clk: in std_logic;\r
+ aluhold: in std_logic;\r
+ clkop: out std_logic;\r
+ clkos: out std_logic;\r
+ lock: out std_logic\r
+ );\r
+ end component;\r
+\r
+\r
+ component dll_in200_out100 is\r
+ port (\r
+ clk: in std_logic;\r
+ aluhold: in std_logic;\r
+ clkop: out std_logic;\r
+ clkos: out std_logic;\r
+ lock: out std_logic\r
+ );\r
+ end component;\r
+\r
+\r
+ component trb_net16_dummy_fifo is\r
+ port (\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0);\r
+ PACKET_NUM_IN : in std_logic_vector(1 downto 0);\r
+ WRITE_ENABLE_IN : in std_logic;\r
+ DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0);\r
+ PACKET_NUM_OUT : out std_logic_vector(1 downto 0);\r
+ READ_ENABLE_IN : in std_logic;\r
+ FULL_OUT : out std_logic;\r
+ EMPTY_OUT : out std_logic\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net16_endpoint_hades_full is\r
+ generic (\r
+ USE_CHANNEL : channel_config_t := (c_YES,c_YES,c_NO,c_YES);\r
+ IBUF_DEPTH : channel_config_t := (6,6,6,6);\r
+ FIFO_TO_INT_DEPTH : channel_config_t := (6,6,6,6);\r
+ FIFO_TO_APL_DEPTH : channel_config_t := (1,1,1,1);\r
+ IBUF_SECURE_MODE : channel_config_t := (c_YES,c_YES,c_YES,c_YES);\r
+ API_SECURE_MODE_TO_APL : channel_config_t := (c_YES,c_YES,c_YES,c_YES);\r
+ API_SECURE_MODE_TO_INT : channel_config_t := (c_YES,c_YES,c_YES,c_YES);\r
+ OBUF_DATA_COUNT_WIDTH : integer range 0 to 7 := std_DATA_COUNT_WIDTH;\r
+ INIT_CAN_SEND_DATA : channel_config_t := (c_NO,c_NO,c_NO,c_NO);\r
+ REPLY_CAN_SEND_DATA : channel_config_t := (c_YES,c_YES,c_YES,c_YES);\r
+ REPLY_CAN_RECEIVE_DATA : channel_config_t := (c_NO,c_NO,c_NO,c_NO);\r
+ USE_CHECKSUM : channel_config_t := (c_NO,c_YES,c_YES,c_YES);\r
+ APL_WRITE_ALL_WORDS : channel_config_t := (c_NO,c_NO,c_NO,c_NO);\r
+ ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF";\r
+ BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF";\r
+ BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF";\r
+ TIMING_TRIGGER_RAW : integer range 0 to 1 := c_YES;\r
+ REGIO_NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers\r
+ REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers\r
+ --standard values for output registers\r
+ REGIO_INIT_CTRL_REGS : std_logic_vector(2**(4)*32-1 downto 0) := (others => '0');\r
+ --set to 0 for unused ctrl registers to save resources\r
+ REGIO_USED_CTRL_REGS : std_logic_vector(2**(4)-1 downto 0) := (others => '1');\r
+ --set to 0 for each unused bit in a register\r
+ REGIO_USED_CTRL_BITMASK : std_logic_vector(2**(4)*32-1 downto 0) := (others => '1');\r
+ REGIO_USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port\r
+ REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";\r
+ REGIO_INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876";\r
+ REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222";\r
+ REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001";\r
+ REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";\r
+ REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";\r
+ REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";\r
+ REGIO_USE_1WIRE_INTERFACE : integer := c_YES; --c_YES,c_NO,c_MONITOR\r
+ REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO;\r
+ CLOCK_FREQUENCY : integer range 1 to 200 := 100\r
+ );\r
+\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic := '1';\r
+\r
+ -- Media direction port\r
+ MED_DATAREADY_OUT : out std_logic;\r
+ MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_READ_IN : in std_logic;\r
+ MED_DATAREADY_IN : in std_logic;\r
+ MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_READ_OUT : out std_logic;\r
+ MED_STAT_OP_IN : in std_logic_vector(15 downto 0);\r
+ MED_CTRL_OP_OUT : out std_logic_vector(15 downto 0);\r
+\r
+ -- LVL1 trigger APL\r
+ TRG_TIMING_TRG_RECEIVED_IN : in std_logic; --strobe when timing trigger received\r
+\r
+ LVL1_TRG_DATA_VALID_OUT : out std_logic; --trigger type, number, code, information are valid\r
+ LVL1_TRG_VALID_TIMING_OUT : out std_logic; --valid timing trigger has been received\r
+ LVL1_TRG_VALID_NOTIMING_OUT : out std_logic; --valid trigger without timing trigger has been received\r
+ LVL1_TRG_INVALID_OUT : out std_logic; --the current trigger is invalid (e.g. no timing trigger, no LVL1...)\r
+\r
+ LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0);\r
+ LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0);\r
+ LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0);\r
+ LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0);\r
+\r
+ LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0) := x"00000000";\r
+ LVL1_TRG_RELEASE_IN : in std_logic := '0';\r
+ LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); --internally generated trigger number, for informational uses only\r
+\r
+ --Information about trigger handler errors\r
+ TRG_MULTIPLE_TRG_OUT : out std_logic;\r
+ TRG_TIMEOUT_DETECTED_OUT : out std_logic;\r
+ TRG_SPURIOUS_TRG_OUT : out std_logic;\r
+ TRG_MISSING_TMG_TRG_OUT : out std_logic;\r
+ TRG_SPIKE_DETECTED_OUT : out std_logic;\r
+ --Data Port\r
+ IPU_NUMBER_OUT : out std_logic_vector (15 downto 0);\r
+ IPU_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0);\r
+ IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0);\r
+ --start strobe\r
+ IPU_START_READOUT_OUT : out std_logic;\r
+ --detector data, equipped with DHDR\r
+ IPU_DATA_IN : in std_logic_vector (31 downto 0);\r
+ IPU_DATAREADY_IN : in std_logic;\r
+ --no more data, end transfer, send TRM\r
+ IPU_READOUT_FINISHED_IN : in std_logic;\r
+ --will be low every second cycle due to 32bit -> 16bit conversion\r
+ IPU_READ_OUT : out std_logic;\r
+ IPU_LENGTH_IN : in std_logic_vector (15 downto 0);\r
+ IPU_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0);\r
+\r
+\r
+ -- Slow Control Data Port\r
+ REGIO_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');\r
+ REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);\r
+ REGIO_REGISTERS_IN : in std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0');\r
+ REGIO_REGISTERS_OUT : out std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0);\r
+ COMMON_STAT_REG_STROBE : out std_logic_vector(std_COMSTATREG-1 downto 0);\r
+ COMMON_CTRL_REG_STROBE : out std_logic_vector(std_COMCTRLREG-1 downto 0);\r
+ STAT_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0);\r
+ CTRL_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0);\r
+ --following ports only used when using internal data port\r
+ REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0);\r
+ REGIO_READ_ENABLE_OUT : out std_logic;\r
+ REGIO_WRITE_ENABLE_OUT : out std_logic;\r
+ REGIO_DATA_OUT : out std_logic_vector(32-1 downto 0);\r
+ REGIO_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0');\r
+ REGIO_DATAREADY_IN : in std_logic := '0';\r
+ REGIO_NO_MORE_DATA_IN : in std_logic := '0';\r
+ REGIO_WRITE_ACK_IN : in std_logic := '0';\r
+ REGIO_UNKNOWN_ADDR_IN : in std_logic := '0';\r
+ REGIO_TIMEOUT_OUT : out std_logic;\r
+ --IDRAM is used if no 1-wire interface, onewire used otherwise\r
+ REGIO_IDRAM_DATA_IN : in std_logic_vector(15 downto 0) := (others => '0');\r
+ REGIO_IDRAM_DATA_OUT : out std_logic_vector(15 downto 0);\r
+ REGIO_IDRAM_ADDR_IN : in std_logic_vector(2 downto 0) := "000";\r
+ REGIO_IDRAM_WR_IN : in std_logic := '0';\r
+ REGIO_ONEWIRE_INOUT : inout std_logic; --temperature sensor\r
+ REGIO_ONEWIRE_MONITOR_IN : in std_logic := '0';\r
+ REGIO_ONEWIRE_MONITOR_OUT : out std_logic;\r
+ REGIO_VAR_ENDPOINT_ID : in std_logic_vector(15 downto 0) := (others => '0');\r
+\r
+ GLOBAL_TIME_OUT : out std_logic_vector(31 downto 0); --global time, microseconds\r
+ LOCAL_TIME_OUT : out std_logic_vector(7 downto 0); --local time running with chip frequency\r
+ TIME_SINCE_LAST_TRG_OUT : out std_logic_vector(31 downto 0); --local time, resetted with each trigger\r
+ TIMER_TICKS_OUT : out std_logic_vector(1 downto 0); --bit 1 ms-tick, 0 us-tick\r
+ --Debugging & Status information\r
+ STAT_DEBUG_IPU : out std_logic_vector (31 downto 0);\r
+ STAT_DEBUG_1 : out std_logic_vector (31 downto 0);\r
+ STAT_DEBUG_2 : out std_logic_vector (31 downto 0);\r
+ MED_STAT_OP : out std_logic_vector (15 downto 0);\r
+ CTRL_MPLEX : in std_logic_vector (31 downto 0) := (others => '0');\r
+ IOBUF_CTRL_GEN : in std_logic_vector (4*32-1 downto 0) := (others => '0');\r
+ STAT_ONEWIRE : out std_logic_vector (31 downto 0);\r
+ STAT_ADDR_DEBUG : out std_logic_vector (15 downto 0);\r
+ DEBUG_LVL1_HANDLER_OUT : out std_logic_vector (15 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+ component trb_net16_endpoint_hades_full_handler is\r
+ generic (\r
+ IBUF_DEPTH : channel_config_t := (6,6,6,6);\r
+ FIFO_TO_INT_DEPTH : channel_config_t := (6,6,6,6);\r
+ FIFO_TO_APL_DEPTH : channel_config_t := (1,1,1,1);\r
+ APL_WRITE_ALL_WORDS : channel_config_t := (c_NO,c_NO,c_NO,c_NO);\r
+ ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF";\r
+ BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF";\r
+ BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF";\r
+ REGIO_NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers\r
+ REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers\r
+ REGIO_INIT_CTRL_REGS : std_logic_vector(16*32-1 downto 0) := (others => '0');\r
+ REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";\r
+ REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222";\r
+ REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001";\r
+ REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";\r
+ REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";\r
+ REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";\r
+ REGIO_USE_1WIRE_INTERFACE : integer := c_YES; --c_YES,c_NO,c_MONITOR\r
+ REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO;\r
+ TIMING_TRIGGER_RAW : integer range 0 to 1 := c_YES;\r
+ CLOCK_FREQUENCY : integer range 1 to 200 := 100;\r
+ --Configure data handler\r
+ DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1;\r
+ DATA_BUFFER_DEPTH : integer range 9 to 14 := 9;\r
+ DATA_BUFFER_WIDTH : integer range 1 to 32 := 31;\r
+ DATA_BUFFER_FULL_THRESH : integer range 0 to 2**14-2 := 2**8;\r
+ TRG_RELEASE_AFTER_DATA : integer range 0 to 1 := c_YES;\r
+ HEADER_BUFFER_DEPTH : integer range 9 to 14 := 9;\r
+ HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-2 := 2**8\r
+ );\r
+\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic := '1';\r
+\r
+ -- Media direction port\r
+ MED_DATAREADY_OUT : out std_logic;\r
+ MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_READ_IN : in std_logic;\r
+ MED_DATAREADY_IN : in std_logic;\r
+ MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_READ_OUT : out std_logic;\r
+ MED_STAT_OP_IN : in std_logic_vector(15 downto 0);\r
+ MED_CTRL_OP_OUT : out std_logic_vector(15 downto 0);\r
+\r
+ --Timing trigger in\r
+ TRG_TIMING_TRG_RECEIVED_IN : in std_logic;\r
+ --LVL1 trigger to FEE\r
+ LVL1_TRG_DATA_VALID_OUT : out std_logic; --trigger type, number, code, information are valid\r
+ LVL1_VALID_TIMING_TRG_OUT : out std_logic; --valid timing trigger has been received\r
+ LVL1_VALID_NOTIMING_TRG_OUT : out std_logic; --valid trigger without timing trigger has been received\r
+ LVL1_INVALID_TRG_OUT : out std_logic; --the current trigger is invalid (e.g. no timing trigger, no LVL1...)\r
+\r
+ LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0);\r
+ LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0);\r
+ LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0);\r
+ LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0);\r
+ LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); --internally generated trigger number, for informational uses only\r
+\r
+ --Response from FEE\r
+ FEE_TRG_RELEASE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
+ FEE_TRG_STATUSBITS_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);\r
+ FEE_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);\r
+ FEE_DATA_WRITE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
+ FEE_DATA_FINISHED_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
+ FEE_DATA_ALMOST_FULL_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
+\r
+ --Information about trigger handler errors\r
+ TRG_MULTIPLE_TRG_OUT : out std_logic;\r
+ TRG_TIMEOUT_DETECTED_OUT : out std_logic;\r
+ TRG_SPURIOUS_TRG_OUT : out std_logic;\r
+ TRG_MISSING_TMG_TRG_OUT : out std_logic;\r
+ TRG_SPIKE_DETECTED_OUT : out std_logic;\r
+\r
+ --Slow Control Port\r
+ --common registers\r
+ REGIO_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');\r
+ REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);\r
+ REGIO_COMMON_STAT_STROBE_OUT : out std_logic_vector(std_COMSTATREG-1 downto 0);\r
+ REGIO_COMMON_CTRL_STROBE_OUT : out std_logic_vector(std_COMCTRLREG-1 downto 0);\r
+ --user defined registers\r
+ REGIO_STAT_REG_IN : in std_logic_vector(2**(REGIO_NUM_STAT_REGS)*32-1 downto 0) := (others => '0');\r
+ REGIO_CTRL_REG_OUT : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)*32-1 downto 0);\r
+ REGIO_STAT_STROBE_OUT : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0);\r
+ REGIO_CTRL_STROBE_OUT : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0);\r
+ --internal data port\r
+ BUS_ADDR_OUT : out std_logic_vector(16-1 downto 0);\r
+ BUS_DATA_OUT : out std_logic_vector(32-1 downto 0);\r
+ BUS_READ_ENABLE_OUT : out std_logic;\r
+ BUS_WRITE_ENABLE_OUT : out std_logic;\r
+ BUS_TIMEOUT_OUT : out std_logic;\r
+ BUS_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0');\r
+ BUS_DATAREADY_IN : in std_logic := '0';\r
+ BUS_WRITE_ACK_IN : in std_logic := '0';\r
+ BUS_NO_MORE_DATA_IN : in std_logic := '0';\r
+ BUS_UNKNOWN_ADDR_IN : in std_logic := '0';\r
+ --Onewire\r
+ ONEWIRE_INOUT : inout std_logic; --temperature sensor\r
+ ONEWIRE_MONITOR_IN : in std_logic := '0';\r
+ ONEWIRE_MONITOR_OUT : out std_logic;\r
+ --Config endpoint id, if not statically assigned\r
+ REGIO_VAR_ENDPOINT_ID : in std_logic_vector (15 downto 0) := (others => '0');\r
+\r
+ --Timing registers\r
+ TIME_GLOBAL_OUT : out std_logic_vector (31 downto 0); --global time, microseconds\r
+ TIME_LOCAL_OUT : out std_logic_vector ( 7 downto 0); --local time running with chip frequency\r
+ TIME_SINCE_LAST_TRG_OUT : out std_logic_vector (31 downto 0); --local time, resetted with each trigger\r
+ TIME_TICKS_OUT : out std_logic_vector ( 1 downto 0); --bit 1 ms-tick, 0 us-tick\r
+\r
+ --Debugging & Status information\r
+ STAT_DEBUG_IPU : out std_logic_vector (31 downto 0);\r
+ STAT_DEBUG_1 : out std_logic_vector (31 downto 0);\r
+ STAT_DEBUG_2 : out std_logic_vector (31 downto 0);\r
+ STAT_DEBUG_DATA_HANDLER_OUT : out std_logic_vector (31 downto 0);\r
+ STAT_DEBUG_IPU_HANDLER_OUT : out std_logic_vector (31 downto 0);\r
+ CTRL_MPLEX : in std_logic_vector (31 downto 0) := (others => '0');\r
+ IOBUF_CTRL_GEN : in std_logic_vector (4*32-1 downto 0) := (others => '0');\r
+ STAT_ONEWIRE : out std_logic_vector (31 downto 0);\r
+ STAT_ADDR_DEBUG : out std_logic_vector (15 downto 0);\r
+ DEBUG_LVL1_HANDLER_OUT : out std_logic_vector (15 downto 0)\r
+ );\r
+ end component;\r
+\r
+ component trb_net16_endpoint_hades_cts is\r
+ generic(\r
+ USE_CHANNEL : channel_config_t := (c_YES,c_YES,c_NO,c_YES);\r
+ IBUF_DEPTH : channel_config_t := (1,6,6,6);\r
+ FIFO_TO_INT_DEPTH : channel_config_t := (1,1,6,6);\r
+ FIFO_TO_APL_DEPTH : channel_config_t := (1,6,6,6);\r
+ INIT_CAN_SEND_DATA : channel_config_t := (c_YES,c_YES,c_NO,c_NO);\r
+ REPLY_CAN_SEND_DATA : channel_config_t := (c_NO,c_NO,c_NO,c_YES);\r
+ REPLY_CAN_RECEIVE_DATA : channel_config_t := (c_YES,c_YES,c_NO,c_NO);\r
+ USE_CHECKSUM : channel_config_t := (c_NO,c_YES,c_YES,c_YES);\r
+ APL_WRITE_ALL_WORDS : channel_config_t := (c_NO,c_NO,c_NO,c_NO);\r
+ ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF";\r
+ BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF";\r
+ REGIO_NUM_STAT_REGS : integer range 0 to 6 := 2; --log2 of number of status registers\r
+ REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers\r
+ --standard values for output registers\r
+ REGIO_INIT_CTRL_REGS : std_logic_vector(2**(4)*32-1 downto 0) := (others => '0');\r
+ --set to 0 for unused ctrl registers to save resources\r
+ REGIO_USED_CTRL_REGS : std_logic_vector(2**(4)-1 downto 0) := x"0001";\r
+ --set to 0 for each unused bit in a register\r
+ REGIO_USED_CTRL_BITMASK : std_logic_vector(2**(4)*32-1 downto 0) := (others => '1');\r
+ REGIO_USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port\r
+ REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";\r
+ REGIO_INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"0000_0000_0000_0000";\r
+ REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"0000_0000";\r
+ REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001";\r
+ REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";\r
+ REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";\r
+ REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"50000000";\r
+ REGIO_USE_1WIRE_INTERFACE: integer := c_YES; --c_YES,c_NO,c_MONITOR\r
+ REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO;\r
+ CLOCK_FREQUENCY : integer range 1 to 200 := 100\r
+ );\r
+ port(\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+\r
+ -- Media direction port\r
+ MED_DATAREADY_OUT : out std_logic;\r
+ MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_READ_IN : in std_logic;\r
+\r
+ MED_DATAREADY_IN : in std_logic;\r
+ MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_READ_OUT : out std_logic;\r
+\r
+ MED_STAT_OP_IN : in std_logic_vector(15 downto 0);\r
+ MED_CTRL_OP_OUT : out std_logic_vector(15 downto 0);\r
+\r
+ --LVL1 trigger\r
+ TRG_SEND_IN : in std_logic;\r
+ TRG_TYPE_IN : in std_logic_vector (3 downto 0);\r
+ TRG_NUMBER_IN : in std_logic_vector (15 downto 0);\r
+ TRG_INFORMATION_IN : in std_logic_vector (23 downto 0);\r
+ TRG_RND_CODE_IN : in std_logic_vector (7 downto 0);\r
+ TRG_STATUS_BITS_OUT : out std_logic_vector (31 downto 0);\r
+ TRG_BUSY_OUT : out std_logic;\r
+\r
+ --IPU Channel\r
+ IPU_SEND_IN : in std_logic;\r
+ IPU_TYPE_IN : in std_logic_vector (3 downto 0);\r
+ IPU_NUMBER_IN : in std_logic_vector (15 downto 0);\r
+ IPU_INFORMATION_IN : in std_logic_vector (7 downto 0);\r
+ IPU_RND_CODE_IN : in std_logic_vector (7 downto 0);\r
+ -- Receiver port\r
+ IPU_DATA_OUT : out std_logic_vector (31 downto 0);\r
+ IPU_DATAREADY_OUT : out std_logic;\r
+ IPU_READ_IN : in std_logic;\r
+ IPU_STATUS_BITS_OUT : out std_logic_vector (31 downto 0);\r
+ IPU_BUSY_OUT : out std_logic;\r
+\r
+ -- Slow Control Data Port\r
+ REGIO_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');\r
+ REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);\r
+ REGIO_REGISTERS_IN : in std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0');\r
+ REGIO_REGISTERS_OUT : out std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0);\r
+ COMMON_STAT_REG_STROBE : out std_logic_vector(std_COMSTATREG-1 downto 0);\r
+ COMMON_CTRL_REG_STROBE : out std_logic_vector(std_COMCTRLREG-1 downto 0);\r
+ STAT_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0);\r
+ CTRL_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0);\r
+ --following ports only used when using internal data port\r
+ REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0);\r
+ REGIO_READ_ENABLE_OUT : out std_logic;\r
+ REGIO_WRITE_ENABLE_OUT : out std_logic;\r
+ REGIO_DATA_OUT : out std_logic_vector(32-1 downto 0);\r
+ REGIO_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0');\r
+ REGIO_DATAREADY_IN : in std_logic := '0';\r
+ REGIO_NO_MORE_DATA_IN : in std_logic := '0';\r
+ REGIO_WRITE_ACK_IN : in std_logic := '0';\r
+ REGIO_UNKNOWN_ADDR_IN : in std_logic := '0';\r
+ REGIO_TIMEOUT_OUT : out std_logic;\r
+ REGIO_ONEWIRE_INOUT : inout std_logic;\r
+ REGIO_ONEWIRE_MONITOR_OUT : out std_logic;\r
+ REGIO_ONEWIRE_MONITOR_IN : in std_logic;\r
+ REGIO_VAR_ENDPOINT_ID : in std_logic_vector(15 downto 0) := (others => '0');\r
+ TRIGGER_MONITOR_IN : in std_logic := '0'; --strobe when timing trigger received\r
+ GLOBAL_TIME_OUT : out std_logic_vector(31 downto 0); --global time, microseconds\r
+ LOCAL_TIME_OUT : out std_logic_vector(7 downto 0); --local time running with chip frequency\r
+ TIME_SINCE_LAST_TRG_OUT : out std_logic_vector(31 downto 0); --local time, resetted with each trigger\r
+ TIMER_TICKS_OUT : out std_logic_vector(1 downto 0); --bit 1 ms-tick, 0 us-tick\r
+ STAT_DEBUG_1 : out std_logic_vector(31 downto 0);\r
+ STAT_DEBUG_2 : out std_logic_vector(31 downto 0)\r
+ );\r
+\r
+ end component;\r
+\r
+\r
+\r
+\r
+ component etrax_interface is\r
+ generic(\r
+ STATUS_REGISTERS : integer := 4;\r
+ CONTROL_REGISTERS : integer := 4\r
+ );\r
+ port (\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ --Connection to Etrax\r
+ ETRAX_DATA_BUS_B : out std_logic_vector(17 downto 0);\r
+ ETRAX_DATA_BUS_C : in std_logic_vector(17 downto 0);\r
+ ETRAX_BUS_BUSY : out std_logic;\r
+ --Connection to internal FPGA logic (all addresses above 0x100)\r
+ INTERNAL_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ INTERNAL_DATA_IN : in std_logic_vector(31 downto 0);\r
+ INTERNAL_READ_OUT : out std_logic;\r
+ INTERNAL_WRITE_OUT : out std_logic;\r
+ INTERNAL_DATAREADY_IN : in std_logic;\r
+ INTERNAL_ADDRESS_OUT : out std_logic_vector(15 downto 0);\r
+ --Easy-to-use status and control registers (Addresses 0-15 (stat) and 16-31 (ctrl)\r
+ FPGA_REGISTER_IN : in std_logic_vector(STATUS_REGISTERS*32-1 downto 0);\r
+ FPGA_REGISTER_OUT : out std_logic_vector(CONTROL_REGISTERS*32-1 downto 0);\r
+ --Reset FPGA via Etrax\r
+ EXTERNAL_RESET : out std_logic;\r
+ STAT : out std_logic_vector(15 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net16_fifo is\r
+ generic (\r
USE_VENDOR_CORES : integer range 0 to 1 := c_NO;\r
- USE_DATA_COUNT : integer range 0 to 1 := c_NO;
- DEPTH : integer := 6
- );
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0);
- PACKET_NUM_IN : in std_logic_vector(1 downto 0);
- WRITE_ENABLE_IN : in std_logic;
- DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0);
- PACKET_NUM_OUT : out std_logic_vector(1 downto 0);
+ USE_DATA_COUNT : integer range 0 to 1 := c_NO;\r
+ DEPTH : integer := 6\r
+ );\r
+ port (\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0);\r
+ PACKET_NUM_IN : in std_logic_vector(1 downto 0);\r
+ WRITE_ENABLE_IN : in std_logic;\r
+ DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0);\r
+ PACKET_NUM_OUT : out std_logic_vector(1 downto 0);\r
READ_ENABLE_IN : in std_logic;\r
- DATA_COUNT_OUT : out std_logic_vector(10 downto 0);
- FULL_OUT : out std_logic;
- EMPTY_OUT : out std_logic
- );
- end component;
-
-
-
-
-
- component trb_net_fifo_16bit_bram_dualport is
- generic(
- USE_STATUS_FLAGS : integer := c_YES
- );
- port( read_clock_in : in std_logic;
- write_clock_in : in std_logic;
- read_enable_in : in std_logic;
- write_enable_in : in std_logic;
- fifo_gsr_in : in std_logic;
- write_data_in : in std_logic_vector(17 downto 0);
- read_data_out : out std_logic_vector(17 downto 0);
- full_out : out std_logic;
- empty_out : out std_logic;
- fifostatus_out : out std_logic_vector(3 downto 0);
- valid_read_out : out std_logic;
- almost_empty_out : out std_logic;
- almost_full_out : out std_logic
- );
- end component;
-
-
-
-
-
-
- component fifo_dualclock_width_16_reg is
- port (
- Data: in std_logic_vector(17 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(17 downto 0);
- Empty: out std_logic;
- Full: out std_logic);
- end component;
-
-
-
-
--- component trb_net16_gbe_buf is
--- generic(
--- DO_SIMULATION : integer range 0 to 1 := 1;
--- USE_125MHZ_EXTCLK : integer range 0 to 1 := 1
--- );
--- port(
--- CLK : in std_logic;
--- TEST_CLK : in std_logic; -- only for simulation!
--- CLK_125_TX_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode
--- CLK_125_RX_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode
--- RESET : in std_logic;
--- GSR_N : in std_logic;
--- -- Debug
--- STAGE_STAT_REGS_OUT : out std_logic_vector(31 downto 0);
--- STAGE_CTRL_REGS_IN : in std_logic_vector(31 downto 0);
--- -- configuration interface
--- IP_CFG_START_IN : in std_logic;
--- IP_CFG_BANK_SEL_IN : in std_logic_vector(3 downto 0);
--- IP_CFG_DONE_OUT : out std_logic;
--- IP_CFG_MEM_ADDR_OUT : out std_logic_vector(7 downto 0);
--- IP_CFG_MEM_DATA_IN : in std_logic_vector(31 downto 0);
--- IP_CFG_MEM_CLK_OUT : out std_logic;
--- MR_RESET_IN : in std_logic;
--- MR_MODE_IN : in std_logic;
--- MR_RESTART_IN : in std_logic;
--- -- gk 29.03.10
--- SLV_ADDR_IN : in std_logic_vector(7 downto 0);
--- SLV_READ_IN : in std_logic;
--- SLV_WRITE_IN : in std_logic;
--- SLV_BUSY_OUT : out std_logic;
--- SLV_ACK_OUT : out std_logic;
--- SLV_DATA_IN : in std_logic_vector(31 downto 0);
--- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
--- -- gk 22.04.10
--- -- registers setup interface
--- BUS_ADDR_IN : in std_logic_vector(7 downto 0);
--- BUS_DATA_IN : in std_logic_vector(31 downto 0);
--- BUS_DATA_OUT : out std_logic_vector(31 downto 0); -- gk 26.04.10
--- BUS_WRITE_EN_IN : in std_logic; -- gk 26.04.10
--- BUS_READ_EN_IN : in std_logic; -- gk 26.04.10
--- BUS_ACK_OUT : out std_logic; -- gk 26.04.10
--- -- gk 23.04.10
--- LED_PACKET_SENT_OUT : out std_logic;
--- LED_AN_DONE_N_OUT : out std_logic;
--- -- CTS interface
--- CTS_NUMBER_IN : in std_logic_vector (15 downto 0);
--- CTS_CODE_IN : in std_logic_vector (7 downto 0);
--- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0);
--- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);
--- CTS_START_READOUT_IN : in std_logic;
--- CTS_DATA_OUT : out std_logic_vector (31 downto 0);
--- CTS_DATAREADY_OUT : out std_logic;
--- CTS_READOUT_FINISHED_OUT : out std_logic;
--- CTS_READ_IN : in std_logic;
--- CTS_LENGTH_OUT : out std_logic_vector (15 downto 0);
--- CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
--- -- Data payload interface
--- FEE_DATA_IN : in std_logic_vector (15 downto 0);
--- FEE_DATAREADY_IN : in std_logic;
--- FEE_READ_OUT : out std_logic;
--- FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0);
--- FEE_BUSY_IN : in std_logic;
--- --SFP Connection
--- SFP_RXD_P_IN : in std_logic;
--- SFP_RXD_N_IN : in std_logic;
--- SFP_TXD_P_OUT : out std_logic;
--- SFP_TXD_N_OUT : out std_logic;
--- SFP_REFCLK_P_IN : in std_logic;
--- SFP_REFCLK_N_IN : in std_logic;
--- SFP_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
--- SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
--- SFP_TXDIS_OUT : out std_logic; -- SFP disable
--- -- debug ports
--- ANALYZER_DEBUG_OUT : out std_logic_vector(63 downto 0)
--- );
--- end component;
-
-
-
- component handler_data is
- generic(
- DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1;
- DATA_BUFFER_DEPTH : integer range 9 to 14 := 9;
- DATA_BUFFER_WIDTH : integer range 1 to 32 := 32;
- DATA_BUFFER_FULL_THRESH : integer range 0 to 2**14-1 := 2**8;
- TRG_RELEASE_AFTER_DATA : integer range 0 to 1 := c_YES;
- HEADER_BUFFER_DEPTH : integer range 9 to 14 := 9;
- HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-1 := 2**8
- );
- port(
- CLOCK : in std_logic;
- RESET : in std_logic;
-
- --LVL1 Handler
- LVL1_VALID_TRIGGER_IN : in std_logic; --received valid trigger, readout starts
- LVL1_TRG_DATA_VALID_IN : in std_logic; --TRG Info valid & FEE busy
- LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); --trigger type
- LVL1_TRG_INFO_IN : in std_logic_vector(23 downto 0); --further trigger details
- LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0);
- LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); --trigger number
- LVL1_STATUSBITS_OUT : out std_logic_vector(31 downto 0);
- LVL1_TRG_RELEASE_OUT : out std_logic;
-
- --FEE
- FEE_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);
- FEE_DATA_WRITE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
- FEE_DATA_FINISHED_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
- FEE_DATA_ALMOST_FULL_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
-
- --IPU Handler
- IPU_DATA_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);
- IPU_DATA_READ_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
- IPU_DATA_EMPTY_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
- IPU_DATA_LENGTH_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER*16-1 downto 0);
- IPU_DATA_FLAGS_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER*4-1 downto 0);
-
- IPU_HDR_DATA_OUT : out std_logic_vector(31 downto 0);
- IPU_HDR_DATA_READ_IN : in std_logic;
- IPU_HDR_DATA_EMPTY_OUT : out std_logic;
-
- TMG_TRG_ERROR_IN : in std_logic;
- --Status
- STAT_DATA_BUFFER_LEVEL : out std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);
- STAT_HEADER_BUFFER_LEVEL : out std_logic_vector(31 downto 0);
-
- --Debug
- DEBUG_OUT : out std_logic_vector(31 downto 0)
- );
-
- end component;
-
-
-
-
-
- component handler_ipu is
- generic(
- DATA_INTERFACE_NUMBER : integer range 1 to 7 := 1
- );
- port(
- CLOCK : in std_logic;
- RESET : in std_logic;
-
- --From Data Handler
- DAT_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);
- DAT_DATA_READ_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
- DAT_DATA_EMPTY_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
- DAT_DATA_LENGTH_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*16-1 downto 0);
- DAT_DATA_FLAGS_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*4-1 downto 0);
- DAT_HDR_DATA_IN : in std_logic_vector(31 downto 0);
- DAT_HDR_DATA_READ_OUT : out std_logic;
- DAT_HDR_DATA_EMPTY_IN : in std_logic;
-
- --To IPU Channel
- IPU_NUMBER_IN : in std_logic_vector (15 downto 0);
- IPU_INFORMATION_IN : in std_logic_vector (7 downto 0);
- IPU_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);
- IPU_START_READOUT_IN : in std_logic;
- IPU_DATA_OUT : out std_logic_vector (31 downto 0);
- IPU_DATAREADY_OUT : out std_logic;
- IPU_READOUT_FINISHED_OUT : out std_logic;
- IPU_READ_IN : in std_logic;
- IPU_LENGTH_OUT : out std_logic_vector (15 downto 0);
- IPU_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
-
- --Debug
- STATUS_OUT : out std_logic_vector(31 downto 0)
- );
-
- end component;
-
-
-
- component handler_lvl1 is
- generic(
- TIMING_TRIGGER_RAW : integer range 0 to 1 := c_YES
- );
- port(
- RESET : in std_logic;
- RESET_STATS_IN : in std_logic;
- CLOCK : in std_logic;
- --Timing Trigger
- LVL1_TIMING_TRG_IN : in std_logic; --raw trigger signal input, min. 80 ns or strobe, see generics
- LVL1_PSEUDO_TMG_TRG_IN : in std_logic; --strobe for dummy timing trigger
- --LVL1_handler connection
- LVL1_TRG_RECEIVED_IN : in std_logic;
- LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0);
- LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);
- LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0);
- LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0);
- LVL1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); --errorbits to CTS
- LVL1_TRG_RELEASE_OUT : out std_logic := '0'; --release to CTS
-
- LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); -- increased after trigger release
- LVL1_INT_TRG_LOAD_IN : in std_logic; -- load internal trigger counter
- LVL1_INT_TRG_COUNTER_IN : in std_logic_vector(15 downto 0); -- load value for internal trigger counter
-
- --FEE logic / Data Handler
- LVL1_TRG_DATA_VALID_OUT : out std_logic; -- trigger type, number, code, information are valid
- LVL1_VALID_TIMING_TRG_OUT : out std_logic; -- valid timing trigger has been received
- LVL1_VALID_NOTIMING_TRG_OUT : out std_logic; -- valid trigger without timing trigger has been received
- LVL1_INVALID_TRG_OUT : out std_logic; -- the current trigger is invalid (e.g. no timing trigger, no LVL1...)
- LVL1_MULTIPLE_TRG_OUT : out std_logic; -- more than one timing trigger detected
- LVL1_DELAY_OUT : out std_logic_vector(15 downto 0);
- LVL1_TIMEOUT_DETECTED_OUT : out std_logic; -- gk 11.09.10
- LVL1_SPURIOUS_TRG_OUT : out std_logic; -- gk 11.09.10
- LVL1_MISSING_TMG_TRG_OUT : out std_logic; -- gk 11.09.10
- SPIKE_DETECTED_OUT : out std_logic; -- gk 12.09.10
-
- LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); -- error pattern from FEE
- LVL1_TRG_RELEASE_IN : in std_logic := '0'; -- trigger release from FEE
-
- --Stat/Control
- STATUS_OUT : out std_logic_vector (63 downto 0); -- bits for status registers
- TRG_ENABLE_IN : in std_logic; -- trigger enable flag
- TRG_INVERT_IN : in std_logic; -- trigger invert flag
- COUNTERS_STATUS_OUT : out std_logic_vector (63 downto 0);
- --Debug
- DEBUG_OUT : out std_logic_vector (15 downto 0)
- );
- end component;
-
-
-
-
-
- component handler_trigger_and_data is
- generic(
- DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1;
- DATA_BUFFER_DEPTH : integer range 9 to 14 := 9;
- DATA_BUFFER_WIDTH : integer range 1 to 32 := 32;
- DATA_BUFFER_FULL_THRESH : integer range 0 to 2**14-1 := 2**8;
- TRG_RELEASE_AFTER_DATA : integer range 0 to 1 := c_YES;
- HEADER_BUFFER_DEPTH : integer range 9 to 14 := 9;
- HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-1 := 2**8
- );
- port(
- CLOCK : in std_logic;
- RESET : in std_logic;
- RESET_IPU : in std_logic;
-
- --To Endpoint
- --Timing Trigger (registered)
- LVL1_VALID_TRIGGER_IN : in std_logic;
- LVL1_INT_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);
- --LVL1_handler connection
- LVL1_TRG_DATA_VALID_IN : in std_logic;
- LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0);
- LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);
- LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0);
- LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0);
- LVL1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0);
- LVL1_TRG_RELEASE_OUT : out std_logic;
-
- --IPU channel
- IPU_NUMBER_IN : in std_logic_vector(15 downto 0);
- IPU_INFORMATION_IN : in std_logic_vector(7 downto 0);
- IPU_READOUT_TYPE_IN : in std_logic_vector(3 downto 0);
- IPU_START_READOUT_IN : in std_logic;
- IPU_DATA_OUT : out std_logic_vector(31 downto 0);
- IPU_DATAREADY_OUT : out std_logic;
- IPU_READOUT_FINISHED_OUT : out std_logic;
- IPU_READ_IN : in std_logic;
- IPU_LENGTH_OUT : out std_logic_vector(15 downto 0);
- IPU_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0);
-
- --To FEE
- --FEE to Trigger
- FEE_TRG_RELEASE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
- FEE_TRG_STATUSBITS_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);
-
- --Data Input from FEE
- FEE_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);
- FEE_DATA_WRITE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
- FEE_DATA_FINISHED_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
- FEE_DATA_ALMOST_FULL_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
-
- TMG_TRG_ERROR_IN : in std_logic;
- --Status Registers
- STATUS_OUT : out std_logic_vector(127 downto 0);
- STAT_DATA_BUFFER_LEVEL : out std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);
- STAT_HEADER_BUFFER_LEVEL : out std_logic_vector(31 downto 0);
- TIMER_TICKS_IN : in std_logic_vector(1 downto 0);
- STATISTICS_DATA_OUT : out std_logic_vector(31 downto 0);
- STATISTICS_ADDR_IN : in std_logic_vector(4 downto 0);
- STATISTICS_READY_OUT : out std_logic;
- STATISTICS_READ_IN : in std_logic;
- STATISTICS_UNKNOWN_OUT : out std_logic;
-
- --Debug
- DEBUG_DATA_HANDLER_OUT : out std_logic_vector(31 downto 0);
- DEBUG_IPU_HANDLER_OUT : out std_logic_vector(31 downto 0)
-
- );
- end component;
-
-
-
-
-
-
-
- component trb_net16_ibuf is
- generic (
- DEPTH : integer range 0 to 7 := c_FIFO_BRAM;
- USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
- USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE;
- USE_CHECKSUM : integer range 0 to 1 := c_YES;
- SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
- INIT_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES;
- REPLY_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_DATAREADY_IN : in std_logic;
- MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
- MED_READ_OUT : out std_logic;
- MED_ERROR_IN : in std_logic_vector (2 downto 0);
- -- Internal direction port
- INT_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_INIT_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
- INT_INIT_DATAREADY_OUT : out std_logic;
- INT_INIT_READ_IN : in std_logic;
- INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_REPLY_PACKET_NUM_OUT: out std_logic_vector(c_NUM_WIDTH-1 downto 0);
- INT_REPLY_DATAREADY_OUT : out std_logic;
- INT_REPLY_READ_IN : in std_logic;
- INT_ERROR_OUT : out std_logic_vector (2 downto 0);
- -- Status and control port
- STAT_BUFFER_COUNTER : out std_logic_vector (31 downto 0);
- STAT_DATA_COUNTER : out std_logic_vector (31 downto 0);
- STAT_BUFFER : out std_logic_vector (31 downto 0);
- CTRL_STAT : in std_logic_vector (15 downto 0)
- );
- end component;
-
-
-
-
-
-
- component fifo_36x512 is
- port (
- Data: in std_logic_vector(35 downto 0);
- Clock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- Q: out std_logic_vector(35 downto 0);
- Empty: out std_logic;
- Full: out std_logic
- );
- end component;
-
-\r
---component fifo_var_oreg is
- --generic(
- --FIFO_WIDTH : integer range 1 to 64 := 36;
- --FIFO_DEPTH : integer range 1 to 16 := 8
- --);
- --port(
- --Data : in std_logic_vector(FIFO_WIDTH-1 downto 0);
- --Clock : in std_logic;
- --WrEn : in std_logic;
- --RdEn : in std_logic;
- --Reset : in std_logic;
- --AmFullThresh : in std_logic_vector(FIFO_DEPTH-1 downto 0);
- --Q : out std_logic_vector(FIFO_WIDTH-1 downto 0);
- --WCNT : out std_logic_vector(FIFO_DEPTH downto 0);
- --Empty : out std_logic;
- --Full : out std_logic;
- --AlmostFull : out std_logic
- --);
---end component;
-
-
-
- component trb_net16_iobuf is
- generic (
- IBUF_DEPTH : integer range 0 to 6 := c_FIFO_BRAM;--std_FIFO_DEPTH;
- IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;--std_IBUF_SECURE_MODE;
- SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
- SBUF_VERSION_OBUF : integer range 0 to 6 := std_SBUF_VERSION;
- OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH;
- USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE;
- USE_CHECKSUM : integer range 0 to 1 := c_YES;
- USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
- INIT_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES;
- REPLY_CAN_RECEIVE_DATA: integer range 0 to 1 := c_YES;
- INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES;
- REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_INIT_DATAREADY_OUT : out std_logic;
- MED_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_INIT_READ_IN : in std_logic;
- MED_REPLY_DATAREADY_OUT : out std_logic;
- MED_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_REPLY_READ_IN : in std_logic;
- MED_DATAREADY_IN : in std_logic;
- MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_READ_OUT : out std_logic;
- MED_ERROR_IN : in std_logic_vector (2 downto 0);
- -- Internal direction port
- INT_INIT_DATAREADY_OUT : out std_logic;
- INT_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_INIT_READ_IN : in std_logic;
- INT_INIT_DATAREADY_IN : in std_logic;
- INT_INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_INIT_READ_OUT : out std_logic;
- INT_REPLY_DATAREADY_OUT : out std_logic;
- INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_REPLY_READ_IN : in std_logic;
- INT_REPLY_DATAREADY_IN : in std_logic;
- INT_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_REPLY_READ_OUT : out std_logic;
- -- Status and control port
- STAT_GEN : out std_logic_vector (31 downto 0);
- STAT_IBUF_BUFFER : out std_logic_vector (31 downto 0);
- CTRL_GEN : in std_logic_vector (31 downto 0);
- CTRL_OBUF_settings : in std_logic_vector (31 downto 0) := (others => '0');
- STAT_INIT_OBUF_DEBUG : out std_logic_vector (31 downto 0);
- STAT_REPLY_OBUF_DEBUG : out std_logic_vector (31 downto 0);
- STAT_BUFFER_COUNTER : out std_logic_vector (31 downto 0);
- STAT_DATA_COUNTER : out std_logic_vector (31 downto 0);
- TIMER_TICKS_IN : in std_logic_vector (1 downto 0);
- CTRL_STAT : in std_logic_vector (15 downto 0)
- );
- end component;
-
-
-
-
-
-
- component trb_net16_io_multiplexer is
- generic(
- USE_INPUT_SBUF : multiplexer_config_t := (others => c_NO)
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_DATAREADY_IN : in STD_LOGIC;
- MED_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);
- MED_READ_OUT : out STD_LOGIC;
- MED_DATAREADY_OUT : out STD_LOGIC;
- MED_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);
- MED_READ_IN : in STD_LOGIC;
- -- Internal direction port
- INT_DATA_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0);
- INT_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto 0);
- INT_DATAREADY_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0);
- INT_READ_IN : in STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0);
- INT_DATAREADY_IN : in STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0);
- INT_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH*(2**c_MUX_WIDTH)-1 downto 0);
- INT_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH*(2**c_MUX_WIDTH)-1 downto 0);
- INT_READ_OUT : out STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0);
- -- Status and control port
- CTRL : in STD_LOGIC_VECTOR (31 downto 0);
- STAT : out STD_LOGIC_VECTOR (31 downto 0)
- );
- end component;
-
-
-
-
-
- component trb_net16_ipudata is
- generic(
- DO_CHECKS : integer range c_NO to c_YES := c_YES
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Port to API
- API_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- API_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- API_DATAREADY_OUT : out std_logic;
- API_READ_IN : in std_logic;
- API_SHORT_TRANSFER_OUT : out std_logic;
- API_DTYPE_OUT : out std_logic_vector (3 downto 0);
- API_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
- API_SEND_OUT : out std_logic;
- -- Receiver port
- API_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- API_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- API_TYP_IN : in std_logic_vector (2 downto 0);
- API_DATAREADY_IN : in std_logic;
- API_READ_OUT : out std_logic;
- -- APL Control port
- API_RUN_IN : in std_logic;
- API_SEQNR_IN : in std_logic_vector (7 downto 0);
- API_LENGTH_OUT : out std_logic_vector (15 downto 0);
- MY_ADDRESS_IN : in std_logic_vector (15 downto 0);
-
- --Information received with request
- IPU_NUMBER_OUT : out std_logic_vector (15 downto 0);
- IPU_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0);
- IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0);
- IPU_CODE_OUT : out std_logic_vector (7 downto 0);
- --start strobe
- IPU_START_READOUT_OUT: out std_logic;
- --detector data, equipped with DHDR
- IPU_DATA_IN : in std_logic_vector (31 downto 0);
- IPU_DATAREADY_IN : in std_logic;
- --no more data, end transfer, send TRM
- IPU_READOUT_FINISHED_IN : in std_logic;
- --will be low every second cycle due to 32bit -> 16bit conversion
- IPU_READ_OUT : out std_logic;
- IPU_LENGTH_IN : in std_logic_vector (15 downto 0);
- IPU_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0);
-
- STAT_DEBUG : out std_logic_vector(31 downto 0)
- );
- end component;
-
-component trb_net16_gbe_buf is
-generic(
- DO_SIMULATION : integer range 0 to 1 := 1;
- USE_125MHZ_EXTCLK : integer range 0 to 1 := 1
-);
-port(
- CLK : in std_logic;
- TEST_CLK : in std_logic; -- only for simulation!
- CLK_125_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode
- RESET : in std_logic;
- GSR_N : in std_logic;
- -- Debug
- STAGE_STAT_REGS_OUT : out std_logic_vector(31 downto 0);
- STAGE_CTRL_REGS_IN : in std_logic_vector(31 downto 0);
- -- configuration interface
- IP_CFG_START_IN : in std_logic;
- IP_CFG_BANK_SEL_IN : in std_logic_vector(3 downto 0);
- IP_CFG_DONE_OUT : out std_logic;
- IP_CFG_MEM_ADDR_OUT : out std_logic_vector(7 downto 0);
- IP_CFG_MEM_DATA_IN : in std_logic_vector(31 downto 0);
- IP_CFG_MEM_CLK_OUT : out std_logic;
- MR_RESET_IN : in std_logic;
- MR_MODE_IN : in std_logic;
- MR_RESTART_IN : in std_logic;
- -- gk 29.03.10
- SLV_ADDR_IN : in std_logic_vector(7 downto 0);
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_BUSY_OUT : out std_logic;
- SLV_ACK_OUT : out std_logic;
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
- -- gk 22.04.10
- -- registers setup interface
- BUS_ADDR_IN : in std_logic_vector(7 downto 0);
- BUS_DATA_IN : in std_logic_vector(31 downto 0);
- BUS_DATA_OUT : out std_logic_vector(31 downto 0); -- gk 26.04.10
- BUS_WRITE_EN_IN : in std_logic; -- gk 26.04.10
- BUS_READ_EN_IN : in std_logic; -- gk 26.04.10
- BUS_ACK_OUT : out std_logic; -- gk 26.04.10
- -- gk 23.04.10
- LED_PACKET_SENT_OUT : out std_logic;
- LED_AN_DONE_N_OUT : out std_logic;
- -- CTS interface
- CTS_NUMBER_IN : in std_logic_vector (15 downto 0);
- CTS_CODE_IN : in std_logic_vector (7 downto 0);
- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0);
- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);
- CTS_START_READOUT_IN : in std_logic;
- CTS_DATA_OUT : out std_logic_vector (31 downto 0);
- CTS_DATAREADY_OUT : out std_logic;
- CTS_READOUT_FINISHED_OUT : out std_logic;
- CTS_READ_IN : in std_logic;
- CTS_LENGTH_OUT : out std_logic_vector (15 downto 0);
- CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
- -- Data payload interface
- FEE_DATA_IN : in std_logic_vector (15 downto 0);
- FEE_DATAREADY_IN : in std_logic;
- FEE_READ_OUT : out std_logic;
- FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0);
- FEE_BUSY_IN : in std_logic;
- --SFP Connection
- SFP_RXD_P_IN : in std_logic;
- SFP_RXD_N_IN : in std_logic;
- SFP_TXD_P_OUT : out std_logic;
- SFP_TXD_N_OUT : out std_logic;
- SFP_REFCLK_P_IN : in std_logic;
- SFP_REFCLK_N_IN : in std_logic;
- SFP_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
- SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
- SFP_TXDIS_OUT : out std_logic; -- SFP disable
- -- debug ports
- ANALYZER_DEBUG_OUT : out std_logic_vector(63 downto 0)
-);
-end component;
-
-
-
-
- component ipu_dummy is
- port( CLK_IN : in std_logic; -- 100MHz local clock
- CLEAR_IN : in std_logic;
- RESET_IN : in std_logic; -- synchronous reset
- -- Slow control signals
- MIN_COUNT_IN : in std_logic_vector(15 downto 0); -- minimum counter value
- MAX_COUNT_IN : in std_logic_vector(15 downto 0); -- maximum counter value
- CTRL_IN : in std_logic_vector(7 downto 0); -- control bits from slow control
- -- IPU channel connections
- IPU_NUMBER_IN : in std_logic_vector(15 downto 0); -- trigger tag
- IPU_INFORMATION_IN : in std_logic_vector(7 downto 0); -- trigger information
- IPU_START_READOUT_IN : in std_logic; -- gimme data!
- IPU_DATA_OUT : out std_logic_vector(31 downto 0); -- detector data, equipped with DHDR
- IPU_DATAREADY_OUT : out std_logic; -- data is valid
- IPU_READOUT_FINISHED_OUT : out std_logic; -- no more data, end transfer, send TRM
- IPU_READ_IN : in std_logic; -- read strobe, low every second cycle
- IPU_LENGTH_OUT : out std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?)
- IPU_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); -- error pattern
- -- DHDR buffer
- LVL1_FIFO_RD_OUT : out std_logic;
- LVL1_FIFO_EMPTY_IN : in std_logic;
- LVL1_FIFO_NUMBER_IN : in std_logic_vector(15 downto 0);
- LVL1_FIFO_CODE_IN : in std_logic_vector(7 downto 0);
- LVL1_FIFO_INFORMATION_IN : in std_logic_vector(7 downto 0);
- LVL1_FIFO_TYPE_IN : in std_logic_vector(3 downto 0);
- -- Debug signals
- DBG_BSM_OUT : out std_logic_vector(7 downto 0);
- DBG_OUT : out std_logic_vector(31 downto 0)
- );
- end component;
-
-
-
-
-
- component trb_net16_lsm_sfp is
- generic(
- CHECK_FOR_CV : integer := c_YES
- );
- port(
- SYSCLK : in std_logic; -- fabric clock
- RESET : in std_logic; -- synchronous reset
- CLEAR : in std_logic; -- asynchronous reset, connect to '0' if not needed / available
- -- status signals
- SFP_MISSING_IN : in std_logic; -- SFP Present ('0' = no SFP mounted, '1' = SFP in place)
- SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
- SD_LINK_OK_IN : in std_logic; -- SerDes Link OK ('0' = not linked, '1' link established)
- SD_LOS_IN : in std_logic; -- SerDes Loss Of Signal ('0' = OK, '1' = signal lost)
- SD_TXCLK_BAD_IN : in std_logic; -- SerDes Tx Clock locked ('0' = locked, '1' = not locked)
- SD_RXCLK_BAD_IN : in std_logic; -- SerDes Rx Clock locked ('0' = locked, '1' = not locked)
- SD_RETRY_IN : in std_logic; -- '0' = handle byte swapping in logic, '1' = simply restart link and hope
- SD_ALIGNMENT_IN : in std_logic_vector(1 downto 0); -- SerDes Byte alignment ("10" = swapped, "01" = correct)
- SD_CV_IN : in std_logic_vector(1 downto 0); -- SerDes Code Violation ("00" = OK, everything else = BAD)
- -- control signals
- FULL_RESET_OUT : out std_logic; -- full reset AKA quad_reset
- LANE_RESET_OUT : out std_logic; -- partial reset AKA lane_reset
- TX_ALLOW_OUT : out std_logic; -- allow normal transmit operation
- RX_ALLOW_OUT : out std_logic; -- allow normal receive operation
- SWAP_BYTES_OUT : out std_logic; -- bytes need swapping ('0' = correct order, '1' = swapped order)
- -- debug signals
- STAT_OP : out std_logic_vector(15 downto 0);
- CTRL_OP : in std_logic_vector(15 downto 0);
- STAT_DEBUG : out std_logic_vector(31 downto 0)
- );
- end component;
-
-
-
-
-
-
-
-
- component trb_net16_med_8_SDR_OS is
- generic(
- TRANSMISSION_CLOCK_DIV: integer range 1 to 10 := 1
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- INT_DATAREADY_OUT : out std_logic;
- INT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_READ_IN : in std_logic;
-
- INT_DATAREADY_IN : in std_logic;
- INT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_READ_OUT : out std_logic;
-
- -- Media direction port
- TX_DATA_OUT : out std_logic_vector (7 downto 0);
- TX_CLK_OUT : out std_logic;
- TX_CTRL_OUT : out std_logic_vector (1 downto 0);
- RX_DATA_IN : in std_logic_vector (7 downto 0);
- RX_CLK_IN : in std_logic;
- RX_CTRL_IN : in std_logic_vector (1 downto 0);
-
- -- Status and control port
- STAT_OP: out std_logic_vector (15 downto 0);
- CTRL_OP: in std_logic_vector (15 downto 0);
-
- STAT: out std_logic_vector (31 downto 0);
- CTRL: in std_logic_vector (31 downto 0)
- );
- end component;
-
-
-
-
-
-
-
- component trb_net16_med_ecp_fot is
- port(
- CLK : in std_logic;
- CLK_25 : in std_logic;
- CLK_EN : in std_logic;
- RESET : in std_logic;
- CLEAR : in std_logic;
-
- --Internal Connection
- MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
- MED_DATAREADY_IN : in std_logic;
- MED_READ_OUT : out std_logic;
- MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
- MED_DATAREADY_OUT : out std_logic;
- MED_READ_IN : in std_logic;
-
- --SFP Connection
- TXP : out std_logic;
- TXN : out std_logic;
- RXP : in std_logic;
- RXN : in std_logic;
- SD : in std_logic;
-
- -- Status and control port
- STAT_OP : out std_logic_vector (15 downto 0);
- CTRL_OP : in std_logic_vector (15 downto 0);
- STAT_REG_OUT : out std_logic_vector(127 downto 0);
- STAT_DEBUG : out std_logic_vector (63 downto 0);
- CTRL_DEBUG : in std_logic_vector (15 downto 0)
- );
- end component;
-
-
-
-
-
-
-
-
- component trb_net16_med_ecp_fot_4 is
- generic(
- REVERSE_ORDER : integer range 0 to 1 := c_NO
- -- USED_PORTS : std_logic-vector(3 downto 0) := "1111"
- );
- port(
- CLK : in std_logic;
- CLK_25 : in std_logic;
- CLK_EN : in std_logic;
- RESET : in std_logic;
- --Internal Connection
- MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH*4-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH*4-1 downto 0);
- MED_DATAREADY_IN : in std_logic_vector(3 downto 0);
- MED_READ_OUT : out std_logic_vector(3 downto 0);
- MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH*4-1 downto 0);
- MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH*4-1 downto 0);
- MED_DATAREADY_OUT : out std_logic_vector(3 downto 0);
- MED_READ_IN : in std_logic_vector(3 downto 0);
- --SFP Connection
- TXP : out std_logic_vector(3 downto 0);
- TXN : out std_logic_vector(3 downto 0);
- RXP : in std_logic_vector(3 downto 0);
- RXN : in std_logic_vector(3 downto 0);
- SD : in std_logic_vector(3 downto 0);
- -- Status and control port
- STAT_OP : out std_logic_vector (63 downto 0);
- CTRL_OP : in std_logic_vector (63 downto 0);
- STAT_REG_OUT : out std_logic_vector(127 downto 0);
- STAT_DEBUG : out std_logic_vector (255 downto 0);
- CTRL_DEBUG : in std_logic_vector (63 downto 0)
- );
- end component;
-
-
-
-
-
- component trb_net16_med_ecp_fot_4_ctc is
- generic(
- REVERSE_ORDER : integer range 0 to 1 := c_NO
- -- USED_PORTS : std_logic-vector(3 downto 0) := "1111"
- );
- port(
- CLK : in std_logic;
- CLK_25 : in std_logic;
- CLK_EN : in std_logic;
- RESET : in std_logic;
- CLEAR : in std_logic;
- --Internal Connection
- MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH*4-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH*4-1 downto 0);
- MED_DATAREADY_IN : in std_logic_vector(3 downto 0);
- MED_READ_OUT : out std_logic_vector(3 downto 0);
- MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH*4-1 downto 0);
- MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH*4-1 downto 0);
- MED_DATAREADY_OUT : out std_logic_vector(3 downto 0);
- MED_READ_IN : in std_logic_vector(3 downto 0);
-
- --SFP Connection
- TXP : out std_logic_vector(3 downto 0);
- TXN : out std_logic_vector(3 downto 0);
- RXP : in std_logic_vector(3 downto 0);
- RXN : in std_logic_vector(3 downto 0);
- SD : in std_logic_vector(3 downto 0);
-
- -- Status and control port
- STAT_OP : out std_logic_vector (63 downto 0);
- CTRL_OP : in std_logic_vector (63 downto 0);
- STAT_REG_OUT : out std_logic_vector (511 downto 0);
- STAT_DEBUG : out std_logic_vector (255 downto 0);
- CTRL_DEBUG : in std_logic_vector (63 downto 0)
- );
- end component;
-
-
-
-
-
- component trb_net16_med_ecp_sfp is
- generic(
- SERDES_NUM : integer range 0 to 3 := 0;
- EXT_CLOCK : integer range 0 to 1 := c_NO
- );
- port(
- CLK : in std_logic; -- SerDes clock
- SYSCLK : in std_logic; -- fabric clock
- RESET : in std_logic; -- synchronous reset
- CLEAR : in std_logic; -- asynchronous reset
- CLK_EN : in std_logic;
- --Internal Connection
- MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
- MED_DATAREADY_IN : in std_logic;
- MED_READ_OUT : out std_logic;
- MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
- MED_DATAREADY_OUT : out std_logic;
- MED_READ_IN : in std_logic;
- REFCLK2CORE_OUT : out std_logic;
- --SFP Connection
- SD_RXD_P_IN : in std_logic;
- SD_RXD_N_IN : in std_logic;
- SD_TXD_P_OUT : out std_logic;
- SD_TXD_N_OUT : out std_logic;
- SD_REFCLK_P_IN : in std_logic;
- SD_REFCLK_N_IN : in std_logic;
- SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
- SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
- SD_TXDIS_OUT : out std_logic; -- SFP disable
- -- Status and control port
- STAT_OP : out std_logic_vector (15 downto 0);
- CTRL_OP : in std_logic_vector (15 downto 0);
- STAT_DEBUG : out std_logic_vector (63 downto 0);
- CTRL_DEBUG : in std_logic_vector (63 downto 0)
- );
- end component;
-
-
-
-
-
- component trb_net16_med_ecp_sfp_gbe is
- generic(
- SERDES_NUM : integer range 0 to 3 := 0;
- EXT_CLOCK : integer range 0 to 1 := c_NO;
- USE_200_MHZ : integer range 0 to 1 := c_NO
- );
- port(
- CLK : in std_logic; -- SerDes clock
- SYSCLK : in std_logic; -- fabric clock
- RESET : in std_logic; -- synchronous reset
- CLEAR : in std_logic; -- asynchronous reset
- CLK_EN : in std_logic;
- --Internal Connection
- MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
- MED_DATAREADY_IN : in std_logic;
- MED_READ_OUT : out std_logic;
- MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
- MED_DATAREADY_OUT : out std_logic;
- MED_READ_IN : in std_logic;
- REFCLK2CORE_OUT : out std_logic;
- --SFP Connection
- SD_RXD_P_IN : in std_logic;
- SD_RXD_N_IN : in std_logic;
- SD_TXD_P_OUT : out std_logic;
- SD_TXD_N_OUT : out std_logic;
- SD_REFCLK_P_IN : in std_logic;
- SD_REFCLK_N_IN : in std_logic;
- SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
- SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
- SD_TXDIS_OUT : out std_logic; -- SFP disable
- -- Status and control port
- STAT_OP : out std_logic_vector (15 downto 0);
- CTRL_OP : in std_logic_vector (15 downto 0);
- STAT_DEBUG : out std_logic_vector (63 downto 0);
- CTRL_DEBUG : in std_logic_vector (63 downto 0)
- );
- end component;
-
-
-
-
- component trb_net16_med_ecp_sfp_4 is
- generic(
- REVERSE_ORDER : integer range 0 to 1 := c_NO
- -- USED_PORTS : std_logic-vector(3 downto 0) := "1111"
- );
- port(
- CLK : in std_logic; -- SerDes clock
- SYSCLK : in std_logic; -- fabric clock
- RESET : in std_logic; -- synchronous reset
- CLEAR : in std_logic; -- asynchronous reset
- CLK_EN : in std_logic;
- --Internal Connection
- MED_DATA_IN : in std_logic_vector(4*c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector(4*c_NUM_WIDTH-1 downto 0);
- MED_DATAREADY_IN : in std_logic_vector(3 downto 0);
- MED_READ_OUT : out std_logic_vector(3 downto 0);
- MED_DATA_OUT : out std_logic_vector(4*c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT : out std_logic_vector(4*c_NUM_WIDTH-1 downto 0);
- MED_DATAREADY_OUT : out std_logic_vector(3 downto 0);
- MED_READ_IN : in std_logic_vector(3 downto 0);
- REFCLK2CORE_OUT : out std_logic;
- --SFP Connection
- SD_RXD_P_IN : in std_logic_vector(3 downto 0);
- SD_RXD_N_IN : in std_logic_vector(3 downto 0);
- SD_TXD_P_OUT : out std_logic_vector(3 downto 0);
- SD_TXD_N_OUT : out std_logic_vector(3 downto 0);
- SD_REFCLK_P_IN : in std_logic;
- SD_REFCLK_N_IN : in std_logic;
- SD_PRSNT_N_IN : in std_logic_vector(3 downto 0);
- SD_LOS_IN : in std_logic_vector(3 downto 0);
- SD_TXDIS_OUT : out std_logic_vector(3 downto 0);
- -- Status and control port
- STAT_OP : out std_logic_vector (4*16-1 downto 0);
- CTRL_OP : in std_logic_vector (4*16-1 downto 0);
- STAT_DEBUG : out std_logic_vector (63 downto 0);
- CTRL_DEBUG : in std_logic_vector (63 downto 0)
- );
- end component;
-
-
-
- component trb_net16_med_ecp_sfp_4_gbe is
- generic(
- REVERSE_ORDER : integer range 0 to 1 := c_NO
- -- USED_PORTS : std_logic-vector(3 downto 0) := "1111"
- );
- port(
- CLK : in std_logic; -- SerDes clock
- SYSCLK : in std_logic; -- fabric clock
- RESET : in std_logic; -- synchronous reset
- CLEAR : in std_logic; -- asynchronous reset
- CLK_EN : in std_logic;
- --Internal Connection
- MED_DATA_IN : in std_logic_vector(4*c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector(4*c_NUM_WIDTH-1 downto 0);
- MED_DATAREADY_IN : in std_logic_vector(3 downto 0);
- MED_READ_OUT : out std_logic_vector(3 downto 0);
- MED_DATA_OUT : out std_logic_vector(4*c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT : out std_logic_vector(4*c_NUM_WIDTH-1 downto 0);
- MED_DATAREADY_OUT : out std_logic_vector(3 downto 0);
- MED_READ_IN : in std_logic_vector(3 downto 0);
- REFCLK2CORE_OUT : out std_logic;
- --SFP Connection
- SD_RXD_P_IN : in std_logic_vector(3 downto 0);
- SD_RXD_N_IN : in std_logic_vector(3 downto 0);
- SD_TXD_P_OUT : out std_logic_vector(3 downto 0);
- SD_TXD_N_OUT : out std_logic_vector(3 downto 0);
- SD_REFCLK_P_IN : in std_logic;
- SD_REFCLK_N_IN : in std_logic;
- SD_PRSNT_N_IN : in std_logic_vector(3 downto 0);
- SD_LOS_IN : in std_logic_vector(3 downto 0);
- SD_TXDIS_OUT : out std_logic_vector(3 downto 0);
- -- Status and control port
- STAT_OP : out std_logic_vector (4*16-1 downto 0);
- CTRL_OP : in std_logic_vector (4*16-1 downto 0);
- STAT_DEBUG : out std_logic_vector (63 downto 0);
- CTRL_DEBUG : in std_logic_vector (63 downto 0)
- );
- end component;
-
-
-
-
-
- component trb_net16_med_16_CC is
- port(
- CLK : in std_logic;
- CLK_EN : in std_logic;
- RESET : in std_logic;
-
- --Internal Connection
- MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
- MED_DATAREADY_IN : in std_logic;
- MED_READ_OUT : out std_logic;
- MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
- MED_DATAREADY_OUT : out std_logic;
- MED_READ_IN : in std_logic;
-
- DATA_OUT : out std_logic_vector(15 downto 0);
- DATA_VALID_OUT : out std_logic;
- DATA_CTRL_OUT : out std_logic;
- DATA_IN : in std_logic_vector(15 downto 0);
- DATA_VALID_IN : in std_logic;
- DATA_CTRL_IN : in std_logic;
-
- STAT_OP : out std_logic_vector(15 downto 0);
- CTRL_OP : in std_logic_vector(15 downto 0);
- STAT_DEBUG : out std_logic_vector(63 downto 0)
- );
- end component;
-
-
-
-
- component trb_net16_med_16_IC is
- generic(
- DATA_CLK_OUT_PHASE : std_logic := '1'
- );
- port(
- CLK : in std_logic;
- CLK_EN : in std_logic;
- RESET : in std_logic;
-
- --Internal Connection
- MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
- MED_DATAREADY_IN : in std_logic;
- MED_READ_OUT : out std_logic;
- MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
- MED_DATAREADY_OUT : out std_logic;
- MED_READ_IN : in std_logic;
-
- DATA_OUT : out std_logic_vector(15 downto 0);
- DATA_VALID_OUT : out std_logic;
- DATA_CTRL_OUT : out std_logic;
- DATA_CLK_OUT : out std_logic;
- DATA_IN : in std_logic_vector(15 downto 0);
- DATA_VALID_IN : in std_logic;
- DATA_CTRL_IN : in std_logic;
- DATA_CLK_IN : in std_logic;
-
- STAT_OP : out std_logic_vector(15 downto 0);
- CTRL_OP : in std_logic_vector(15 downto 0);
- STAT_DEBUG : out std_logic_vector(63 downto 0)
- );
- end component;
-
-
-
-
- component trb_net16_med_tlk is
- port (
- RESET : in std_logic;
- CLK : in std_logic;
- TLK_CLK : in std_logic;
- TLK_ENABLE : out std_logic;
- TLK_LCKREFN : out std_logic;
- TLK_LOOPEN : out std_logic;
- TLK_PRBSEN : out std_logic;
- TLK_RXD : in std_logic_vector(15 downto 0);
- TLK_RX_CLK : in std_logic;
- TLK_RX_DV : in std_logic;
- TLK_RX_ER : in std_logic;
- TLK_TXD : out std_logic_vector(15 downto 0);
- TLK_TX_EN : out std_logic;
- TLK_TX_ER : out std_logic;
- SFP_LOS : in std_logic;
- SFP_TX_DIS : out std_logic;
- MED_DATAREADY_IN : in std_logic;
- MED_READ_IN : in std_logic;
- MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_DATAREADY_OUT : out std_logic;
- MED_READ_OUT : out std_logic;
- MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- STAT : out std_logic_vector (63 downto 0);
- STAT_MONITOR : out std_logic_vector ( 100 downto 0);
- STAT_OP : out std_logic_vector (15 downto 0);
- CTRL_OP : in std_logic_vector (15 downto 0)
- --connect STAT(0) to LED
- );
- end component;
-
-
-
-
-
- component trb_net_onewire is
- generic(
- USE_TEMPERATURE_READOUT : integer range 0 to 1 := 1;
- CLK_PERIOD : integer := 10 --clk period in ns
- );
- port(
- CLK : in std_logic;
- RESET : in std_logic;
- READOUT_ENABLE_IN : in std_logic := '1';
- --connection to 1-wire interface
- ONEWIRE : inout std_logic;
- MONITOR_OUT : out std_logic;
- --connection to id ram, according to memory map in TrbNetRegIO
- DATA_OUT : out std_logic_vector(15 downto 0);
- ADDR_OUT : out std_logic_vector(2 downto 0);
- WRITE_OUT: out std_logic;
- TEMP_OUT : out std_logic_vector(11 downto 0);
- STAT : out std_logic_vector(31 downto 0)
- );
- end component;
-
-
-
-
-
-
- component trb_net_onewire_listener is
- port(
- CLK : in std_logic;
- CLK_EN : in std_logic;
- RESET : in std_logic;
- MONITOR_IN : in std_logic;
- DATA_OUT : out std_logic_vector(15 downto 0);
- ADDR_OUT : out std_logic_vector(2 downto 0);
- WRITE_OUT: out std_logic;
- TEMP_OUT : out std_logic_vector(11 downto 0);
- STAT : out std_logic_vector(31 downto 0)
- );
- end component;
-
-
-
-
-
-
- component trb_net16_obuf is
- generic (
- DATA_COUNT_WIDTH : integer := 5;
- USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE;
- USE_CHECKSUM : integer range 0 to 1 := c_YES;
- SBUF_VERSION : integer range 0 to 6 := std_SBUF_VERSION
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_DATAREADY_OUT: out std_logic;
- MED_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_READ_IN: in std_logic;
- -- Internal direction port
- INT_DATAREADY_IN: in std_logic;
- INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_READ_OUT: out std_logic;
- -- Status and control port
- STAT_BUFFER: out std_logic_vector (31 downto 0);
- CTRL_BUFFER: in std_logic_vector (31 downto 0);
- CTRL_SETTINGS : in std_logic_vector (15 downto 0);
- STAT_DEBUG : out std_logic_vector (31 downto 0);
- TIMER_TICKS_IN : in std_logic_vector (1 downto 0)
- );
- end component;
-
-
-
-
-
-
-
-
- component trb_net16_obuf_nodata is
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_DATAREADY_OUT: out std_logic;
- MED_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_READ_IN: in std_logic;
- --STAT
- STAT_BUFFER: out std_logic_vector (31 downto 0);
- CTRL_BUFFER: in std_logic_vector (31 downto 0);
- STAT_DEBUG : out std_logic_vector (31 downto 0)
- );
- end component;
-
-
-
-
- component pll_in100_out100 is
- port (
- CLK: in std_logic;
- CLKOP: out std_logic;
- CLKOS: out std_logic;
- LOCK: out std_logic
- );
- end component;
-
-
-
- component pll_in100_out20 is
- port (
- CLK: in std_logic;
- CLKOP: out std_logic;
- LOCK: out std_logic
- );
- end component;
-
-
- component pll_in200_out100 is
- port (
- CLK: in std_logic;
- CLKOP: out std_logic;
- CLKOS: out std_logic;
- LOCK: out std_logic
- );
- end component;
-
-
- component pll_in100_out25 is
- port (
- CLK: in std_logic;
- CLKOP: out std_logic;
- LOCK: out std_logic
- );
- end component;
-
-
- component pll25 is
- port(
- CLK : in std_logic;
- RESET : in std_logic;
- CLKOP : out std_logic;
- CLKOK : out std_logic;
- LOCK : out std_logic
- );
- end component;
-
-
-
-
-
-
- component pll_in25_out100 is
- port (
- CLK: in std_logic;
- CLKOP: out std_logic;
- LOCK: out std_logic
- );
- end component;
-
-
-
-
-
-
- component trb_net_pattern_gen is
- generic (
- WIDTH : integer := 6
- );
- port(
- INPUT_IN : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
- RESULT_OUT: out STD_LOGIC_VECTOR (2**WIDTH-1 downto 0)
- );
- end component;
-
-
-
-
-
-
- component trb_net_priority_arbiter is
- generic (
- WIDTH : integer := 2
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- INPUT_IN : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
- RESULT_OUT: out STD_LOGIC_VECTOR (WIDTH-1 downto 0);
- ENABLE : in std_logic;
- CTRL: in STD_LOGIC_VECTOR (9 downto 0)
- );
- end component;
-
-
-
- component pulse_sync is
- port(
- CLK_A_IN : in std_logic;
- RESET_A_IN : in std_logic;
- PULSE_A_IN : in std_logic;
- CLK_B_IN : in std_logic;
- RESET_B_IN : in std_logic;
- PULSE_B_OUT : out std_logic
- );
- end component;
-
-
-
- component ram_dp is
- generic(
- depth : integer := 3;
- width : integer := 16
- );
- port(
- CLK : in std_logic;
- wr1 : in std_logic;
- a1 : in std_logic_vector(depth-1 downto 0);
- dout1 : out std_logic_vector(width-1 downto 0);
- din1 : in std_logic_vector(width-1 downto 0);
- a2 : in std_logic_vector(depth-1 downto 0);
- dout2 : out std_logic_vector(width-1 downto 0)
- );
- end component;
-
-
-
-
- component ram_dp_rw
- generic(
- depth : integer := 3;
- width : integer := 16
- );
- port(
- CLK : in std_logic;
- wr1 : in std_logic;
- a1 : in std_logic_vector(depth-1 downto 0);
- din1 : in std_logic_vector(width-1 downto 0);
- a2 : in std_logic_vector(depth-1 downto 0);
- dout2 : out std_logic_vector(width-1 downto 0)
- );
- end component;
-
-
-
-
- component trb_net16_regIO is
- generic (
- NUM_STAT_REGS : integer range 0 to 6 := 4; --log2 of number of status registers
- NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers
- --standard values for output registers
- INIT_CTRL_REGS : std_logic_vector(2**(4)*32-1 downto 0) := (others => '0');
- --set to 0 for unused ctrl registers to save resources
- USED_CTRL_REGS : std_logic_vector(2**(4)-1 downto 0) := (others => '1');
- --set to 0 for each unused bit in a register
- USED_CTRL_BITMASK : std_logic_vector(2**(4)*32-1 downto 0) := (others => '1');
- USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port
- INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";
- INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876";
- INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222";
- INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001";
- COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
- COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";
- HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";
- CLOCK_FREQ : integer range 1 to 200 := 100 --MHz
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Port to API
- API_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- API_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- API_DATAREADY_OUT : out std_logic;
- API_READ_IN : in std_logic;
- API_SHORT_TRANSFER_OUT : out std_logic;
- API_DTYPE_OUT : out std_logic_vector (3 downto 0);
- API_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
- API_SEND_OUT : out std_logic;
- -- Receiver port
- API_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- API_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- API_TYP_IN : in std_logic_vector (2 downto 0);
- API_DATAREADY_IN : in std_logic;
- API_READ_OUT : out std_logic;
- -- APL Control port
- API_RUN_IN : in std_logic;
- API_SEQNR_IN : in std_logic_vector (7 downto 0);
-
- --Port to write Unique ID (-> 1-wire)
- IDRAM_DATA_IN : in std_logic_vector(15 downto 0);
- IDRAM_DATA_OUT : out std_logic_vector(15 downto 0);
- IDRAM_ADDR_IN : in std_logic_vector(2 downto 0);
- IDRAM_WR_IN : in std_logic;
-
- --Informations
- MY_ADDRESS_OUT : out std_logic_vector(15 downto 0);
- TRIGGER_MONITOR : in std_logic;
- GLOBAL_TIME : out std_logic_vector(31 downto 0); --global time, microseconds
- LOCAL_TIME : out std_logic_vector(7 downto 0); --local time running with chip frequency
- TIME_SINCE_LAST_TRG : out std_logic_vector(31 downto 0); --local time, resetted with each trigger
- TIMER_US_TICK : out std_logic; --1 tick every microsecond
- TIMER_MS_TICK : out std_logic; --1 tick every 1024 microseconds
-
- --Common Register in / out
- COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REG_WIDTH-1 downto 0);
- COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*c_REGIO_REG_WIDTH-1 downto 0);
- --Custom Register in / out
- REGISTERS_IN : in std_logic_vector(c_REGIO_REG_WIDTH*2**(NUM_STAT_REGS)-1 downto 0);
- REGISTERS_OUT : out std_logic_vector(c_REGIO_REG_WIDTH*2**(NUM_CTRL_REGS)-1 downto 0);
- COMMON_STAT_REG_STROBE : out std_logic_vector((std_COMSTATREG)-1 downto 0);
- COMMON_CTRL_REG_STROBE : out std_logic_vector((std_COMCTRLREG)-1 downto 0);
- STAT_REG_STROBE : out std_logic_vector(2**(NUM_STAT_REGS)-1 downto 0);
- CTRL_REG_STROBE : out std_logic_vector(2**(NUM_CTRL_REGS)-1 downto 0);
- --Internal Data Port
- DAT_ADDR_OUT : out std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0);
- DAT_READ_ENABLE_OUT : out std_logic;
- DAT_WRITE_ENABLE_OUT: out std_logic;
- DAT_DATA_OUT : out std_logic_vector(c_REGIO_REG_WIDTH-1 downto 0);
- DAT_DATA_IN : in std_logic_vector(c_REGIO_REG_WIDTH-1 downto 0);
- DAT_DATAREADY_IN : in std_logic;
- DAT_NO_MORE_DATA_IN : in std_logic;
- DAT_WRITE_ACK_IN : in std_logic;
- DAT_UNKNOWN_ADDR_IN : in std_logic;
- DAT_TIMEOUT_OUT : out std_logic;
-
- --Additional write access to ctrl registers
- STAT : out std_logic_vector(31 downto 0);
- STAT_ADDR_DEBUG : out std_logic_vector(15 downto 0)
- );
- end component;
-
-
-
-
-
- component trb_net16_regio_bus_handler is
- generic(
- PORT_NUMBER : integer range 1 to c_BUS_HANDLER_MAX_PORTS := 3;
- PORT_ADDRESSES : c_BUS_HANDLER_ADDR_t := (others => (others => '0'));
- PORT_ADDR_MASK : c_BUS_HANDLER_WIDTH_t := (others => 0)
- );
- port(
- CLK : in std_logic;
- RESET : in std_logic;
- DAT_ADDR_IN : in std_logic_vector(15 downto 0); -- address bus
- DAT_DATA_IN : in std_logic_vector(31 downto 0); -- data from TRB endpoint
- DAT_DATA_OUT : out std_logic_vector(31 downto 0); -- data to TRB endpoint
- DAT_READ_ENABLE_IN : in std_logic; -- read pulse
- DAT_WRITE_ENABLE_IN : in std_logic; -- write pulse
- DAT_TIMEOUT_IN : in std_logic; -- access timed out
- DAT_DATAREADY_OUT : out std_logic; -- your data, master, as requested
- DAT_WRITE_ACK_OUT : out std_logic; -- data accepted
- DAT_NO_MORE_DATA_OUT : out std_logic; -- don't disturb me now
- DAT_UNKNOWN_ADDR_OUT : out std_logic; -- noone here to answer your request
-
- BUS_ADDR_OUT : out std_logic_vector(PORT_NUMBER*16-1 downto 0);
- BUS_DATA_OUT : out std_logic_vector(PORT_NUMBER*32-1 downto 0);
- BUS_READ_ENABLE_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0);
- BUS_WRITE_ENABLE_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0);
- BUS_TIMEOUT_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0);
-
- BUS_DATA_IN : in std_logic_vector(32*PORT_NUMBER-1 downto 0);
- BUS_DATAREADY_IN : in std_logic_vector(PORT_NUMBER-1 downto 0);
- BUS_WRITE_ACK_IN : in std_logic_vector(PORT_NUMBER-1 downto 0);
- BUS_NO_MORE_DATA_IN : in std_logic_vector(PORT_NUMBER-1 downto 0);
- BUS_UNKNOWN_ADDR_IN : in std_logic_vector(PORT_NUMBER-1 downto 0);
-
- STAT_DEBUG : out std_logic_vector(31 downto 0)
- );
- end component;
-
-
-
-
- component trb_net_reset_handler is
- generic(
- RESET_DELAY : std_logic_vector(15 downto 0) := x"1fff"
- );
- port(
- CLEAR_IN : in std_logic; -- reset input (high active, async)
- CLEAR_N_IN : in std_logic; -- reset input (low active, async)
- CLK_IN : in std_logic; -- raw master clock, NOT from PLL/DLL!
- SYSCLK_IN : in std_logic; -- PLL/DLL remastered clock
- PLL_LOCKED_IN : in std_logic; -- master PLL lock signal (async)
- RESET_IN : in std_logic; -- general reset signal (SYSCLK)
- TRB_RESET_IN : in std_logic; -- TRBnet reset signal (SYSCLK)
- CLEAR_OUT : out std_logic; -- async reset out, USE WITH CARE!
- RESET_OUT : out std_logic; -- synchronous reset out (SYSCLK)
- DEBUG_OUT : out std_logic_vector(15 downto 0)
- );
- end component;
-
-
-
- component rom_16x8 is
- generic(
- INIT0 : std_logic_vector(15 downto 0) := x"0000";
- INIT1 : std_logic_vector(15 downto 0) := x"0000";
- INIT2 : std_logic_vector(15 downto 0) := x"0000";
- INIT3 : std_logic_vector(15 downto 0) := x"0000";
- INIT4 : std_logic_vector(15 downto 0) := x"0000";
- INIT5 : std_logic_vector(15 downto 0) := x"0000";
- INIT6 : std_logic_vector(15 downto 0) := x"0000";
- INIT7 : std_logic_vector(15 downto 0) := x"0000"
- );
- port(
- CLK : in std_logic;
- a : in std_logic_vector(2 downto 0);
- dout : out std_logic_vector(15 downto 0)
- );
- end component;
-
-
-
- component trb_net16_rx_control is
- port(
- RESET_IN : in std_logic;
- QUAD_RST_IN : in std_logic;
- -- raw data from SerDes receive path
- CLK_IN : in std_logic;
- RX_DATA_IN : in std_logic_vector(7 downto 0);
- RX_K_IN : in std_logic;
- RX_CV_IN : in std_logic;
- RX_DISP_ERR_IN : in std_logic;
- RX_ALLOW_IN : in std_logic;
- -- media interface
- SYSCLK_IN : in std_logic; -- 100MHz master clock
- MED_DATA_OUT : out std_logic_vector(15 downto 0);
- MED_DATAREADY_OUT : out std_logic;
- MED_READ_IN : in std_logic;
- MED_PACKET_NUM_OUT : out std_logic_vector(2 downto 0);
- -- request retransmission in case of error while receiving
- REQUEST_RETRANSMIT_OUT : out std_logic; -- one pulse
- REQUEST_POSITION_OUT : out std_logic_vector( 7 downto 0);
- -- command decoding
- START_RETRANSMIT_OUT : out std_logic;
- START_POSITION_OUT : out std_logic_vector( 7 downto 0);
- -- reset handling
- SEND_RESET_WORDS_OUT : out std_logic;
- MAKE_TRBNET_RESET_OUT : out std_logic;
- -- Status signals
- PACKET_TIMEOUT_OUT : out std_logic;
- ENABLE_CORRECTION_IN : in std_logic;
- -- Debugging
- DEBUG_OUT : out std_logic_vector(31 downto 0);
- STAT_REG_OUT : out std_logic_vector(95 downto 0)
- );
- end component;
-
-
-
-
- component trb_net16_sbuf is
- generic (
- VERSION : integer := 0
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- port to combinatorial logic
- COMB_DATAREADY_IN : in STD_LOGIC; --comb logic provides data word
- COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle
- COMB_READ_IN : in STD_LOGIC; --comb logic IS reading
- COMB_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
- COMB_PACKET_NUM_IN: in STD_LOGIC_VECTOR(c_NUM_WIDTH-1 downto 0);
- -- Port to synchronous output.
- SYN_DATAREADY_OUT : out STD_LOGIC;
- SYN_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
- SYN_PACKET_NUM_OUT: out STD_LOGIC_VECTOR(c_NUM_WIDTH-1 downto 0);
- SYN_READ_IN : in STD_LOGIC;
- -- Status and control port
- DEBUG_OUT : out std_logic_vector(15 downto 0);
- STAT_BUFFER : out STD_LOGIC
- );
- end component;
-
-
-
-
-
- component trb_net_sbuf is
- generic (
- DATA_WIDTH : integer := 18;
- VERSION: integer := std_SBUF_VERSION);
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- port to combinatorial logic
- COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word
- COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle
- COMB_READ_IN: in STD_LOGIC; --comb logic IS reading
- COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
- SYN_DATAREADY_OUT: out STD_LOGIC;
- SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
- SYN_READ_IN: in STD_LOGIC;
- STAT_BUFFER: out STD_LOGIC
- );
- end component;
-
-
- component trb_net_sbuf2 is
- generic (
- DATA_WIDTH : integer := 18
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- port to combinatorial logic
- COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word
- COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle
- COMB_READ_IN: in STD_LOGIC; --comb logic IS reading
- COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
- SYN_DATAREADY_OUT: out STD_LOGIC;
- SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
- SYN_READ_IN: in STD_LOGIC;
- STAT_BUFFER: out STD_LOGIC
- );
- end component;
-
- component trb_net_sbuf3 is
- generic (
- DATA_WIDTH : integer := 18
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- port to combinatorial logic
- COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word
- COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle
- COMB_READ_IN: in STD_LOGIC; --comb logic IS reading
- COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
- SYN_DATAREADY_OUT: out STD_LOGIC;
- SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
- SYN_READ_IN: in STD_LOGIC;
- STAT_BUFFER: out STD_LOGIC
- );
- end component;
-
- component trb_net_sbuf4 is
- generic (
- DATA_WIDTH : integer := 18
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- port to combinatorial logic
- COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word
- COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle
- COMB_READ_IN: in STD_LOGIC; --comb logic IS reading
- COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
- SYN_DATAREADY_OUT: out STD_LOGIC;
- SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
- SYN_READ_IN: in STD_LOGIC;
- STAT_BUFFER: out STD_LOGIC
- );
- end component;
-
- component trb_net_sbuf5 is
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- input
- COMB_DATAREADY_IN : in std_logic;
- COMB_next_READ_OUT : out std_logic;
- COMB_DATA_IN : in std_logic_vector(18 downto 0);
- -- output
- SYN_DATAREADY_OUT : out std_logic;
- SYN_DATA_OUT : out std_logic_vector(18 downto 0); -- Data word
- SYN_READ_IN : in std_logic;
- -- Status and control port
- DEBUG : out std_logic_vector(7 downto 0);
- DEBUG_BSM : out std_logic_vector(3 downto 0);
- DEBUG_WCNT : out std_logic_vector(4 downto 0);
- STAT_BUFFER : out std_logic
- );
- end component;
-
- component trb_net_sbuf6 is
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- input
- COMB_DATAREADY_IN : in std_logic;
- COMB_next_READ_OUT : out std_logic;
- COMB_DATA_IN : in std_logic_vector(18 downto 0);
- -- output
- SYN_DATAREADY_OUT : out std_logic;
- SYN_DATA_OUT : out std_logic_vector(18 downto 0);
- SYN_READ_IN : in std_logic;
- -- Status and control port
- DEBUG : out std_logic_vector(7 downto 0);
- DEBUG_BSM : out std_logic_vector(3 downto 0);
- DEBUG_WCNT : out std_logic_vector(4 downto 0);
- STAT_BUFFER : out std_logic
- );
- end component;
-
- component slv_mac_memory is
- port(
- CLK : in std_logic;
- RESET : in std_logic;
- BUSY_IN : in std_logic;
- -- Slave bus
- SLV_ADDR_IN : in std_logic_vector(7 downto 0);
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_BUSY_OUT : out std_logic;
- SLV_ACK_OUT : out std_logic;
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
- -- I/O to the backend
- MEM_CLK_IN : in std_logic;
- MEM_ADDR_IN : in std_logic_vector(7 downto 0);
- MEM_DATA_OUT : out std_logic_vector(31 downto 0);
- -- Status lines
- STAT : out std_logic_vector(31 downto 0) -- DEBUG
- );
- end component;
-
-
-
- component slv_register is
- generic(
- RESET_VALUE : std_logic_vector(31 downto 0) := x"0000_0000"
- );
- port(
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
- BUSY_IN : in std_logic;
- -- Slave bus
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_BUSY_OUT : out std_logic;
- SLV_ACK_OUT : out std_logic;
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
- -- I/O to the backend
- REG_DATA_IN : in std_logic_vector(31 downto 0);
- REG_DATA_OUT : out std_logic_vector(31 downto 0);
- -- Status lines
- STAT : out std_logic_vector(31 downto 0) -- DEBUG
- );
- end component;
-
-
-
- component spi_databus_memory is
- port(
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
- -- Slave bus
- BUS_ADDR_IN : in std_logic_vector(5 downto 0);
- BUS_READ_IN : in std_logic;
- BUS_WRITE_IN : in std_logic;
- BUS_ACK_OUT : out std_logic;
- BUS_DATA_IN : in std_logic_vector(31 downto 0);
- BUS_DATA_OUT : out std_logic_vector(31 downto 0);
- -- state machine connections
- BRAM_ADDR_IN : in std_logic_vector(7 downto 0);
- BRAM_WR_D_OUT : out std_logic_vector(7 downto 0);
- BRAM_RD_D_IN : in std_logic_vector(7 downto 0);
- BRAM_WE_IN : in std_logic;
- -- Status lines
- STAT : out std_logic_vector(63 downto 0) -- DEBUG
- );
- end component;
-
-
- component spi_dpram_32_to_8 is
- port (
- DataInA: in std_logic_vector(31 downto 0);
- DataInB: in std_logic_vector(7 downto 0);
- AddressA: in std_logic_vector(5 downto 0);
- AddressB: in std_logic_vector(7 downto 0);
- ClockA: in std_logic;
- ClockB: in std_logic;
- ClockEnA: in std_logic;
- ClockEnB: in std_logic;
- WrA: in std_logic;
- WrB: in std_logic;
- ResetA: in std_logic;
- ResetB: in std_logic;
- QA: out std_logic_vector(31 downto 0);
- QB: out std_logic_vector(7 downto 0));
- end component;
-
-
- component spi_slim is
- port(
- SYSCLK : in std_logic; -- 100MHz sysclock
- RESET : in std_logic; -- synchronous reset
- -- Command interface
- START_IN : in std_logic; -- one start pulse
- BUSY_OUT : out std_logic; -- SPI transactions are ongoing
- CMD_IN : in std_logic_vector(7 downto 0); -- SPI command byte
- ADL_IN : in std_logic_vector(7 downto 0); -- low address byte
- ADM_IN : in std_logic_vector(7 downto 0); -- mid address byte
- ADH_IN : in std_logic_vector(7 downto 0); -- high address byte
- MAX_IN : in std_logic_vector(7 downto 0); -- number of bytes to write / read (PP/RDCMD)
- TXDATA_IN : in std_logic_vector(7 downto 0); -- byte to be transmitted next
- TX_RD_OUT : out std_logic;
- RXDATA_OUT : out std_logic_vector(7 downto 0); -- current received byte
- RX_WR_OUT : out std_logic;
- TX_RX_A_OUT : out std_logic_vector(7 downto 0); -- memory block counter for PP/RDCMD
- -- SPI interface
- SPI_SCK_OUT : out std_logic;
- SPI_CS_OUT : out std_logic;
- SPI_SDI_IN : in std_logic;
- SPI_SDO_OUT : out std_logic;
- -- DEBUG
- CLK_EN_OUT : out std_logic;
- BSM_OUT : out std_logic_vector(7 downto 0);
- DEBUG_OUT : out std_logic_vector(31 downto 0)
- );
- end component;
-
-
-
-
-
- component spi_master is
- port(
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
- -- Slave bus
- BUS_READ_IN : in std_logic;
- BUS_WRITE_IN : in std_logic;
- BUS_BUSY_OUT : out std_logic;
- BUS_ACK_OUT : out std_logic;
- BUS_ADDR_IN : in std_logic_vector(0 downto 0);
- BUS_DATA_IN : in std_logic_vector(31 downto 0);
- BUS_DATA_OUT : out std_logic_vector(31 downto 0);
- -- SPI connections
- SPI_CS_OUT : out std_logic;
- SPI_SDI_IN : in std_logic;
- SPI_SDO_OUT : out std_logic;
- SPI_SCK_OUT : out std_logic;
- -- BRAM for read/write data
- BRAM_A_OUT : out std_logic_vector(7 downto 0);
- BRAM_WR_D_IN : in std_logic_vector(7 downto 0);
- BRAM_RD_D_OUT : out std_logic_vector(7 downto 0);
- BRAM_WE_OUT : out std_logic;
- -- Status lines
- STAT : out std_logic_vector(31 downto 0) -- DEBUG
- );
- end component;
-
-
-
-
-
-
- component signal_sync is
- generic(
- WIDTH : integer := 1; --
- DEPTH : integer := 3
- );
- port(
- RESET : in std_logic; --Reset is neceessary to avoid optimization to shift register
- CLK0 : in std_logic; --clock for first FF
- CLK1 : in std_logic; --Clock for other FF
- D_IN : in std_logic_vector(WIDTH-1 downto 0); --Data input
- D_OUT : out std_logic_vector(WIDTH-1 downto 0) --Data output
- );
- end component;
-
-
-
-
-
-
-
- component trb_net16_term is
- generic (
- USE_APL_PORT : integer range 0 to 1 := c_YES;
- --even when 0, ERROR_PACKET_IN is used for automatic replys
- SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE
- --if secure_mode is not used, apl must provide error pattern and dtype until
- --next trigger comes in. In secure mode these need to be available while relase_trg is high
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- INT_DATAREADY_OUT : out std_logic;
- INT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_READ_IN : in std_logic;
-
- INT_DATAREADY_IN : in std_logic;
- INT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_READ_OUT : out std_logic;
- APL_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0)
- );
- end component;
-
-
-
-
-
- component trb_net16_term_buf is
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- MED_INIT_DATAREADY_OUT : out std_logic;
- MED_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- MED_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_INIT_READ_IN : in std_logic;
- MED_REPLY_DATAREADY_OUT : out std_logic;
- MED_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- MED_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_REPLY_READ_IN : in std_logic;
- MED_DATAREADY_IN : in std_logic;
- MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_READ_OUT : out std_logic
- );
- end component;
-
-
-
-
-
- component trb_net16_term_ibuf is
- generic(
- SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE;
- SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_DATAREADY_IN: in std_logic;
- MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN :in std_logic_vector(c_NUM_WIDTH-1 downto 0);
- MED_READ_OUT: out std_logic;
- MED_ERROR_IN: in std_logic_vector (2 downto 0);
- -- Internal direction port
- INT_DATAREADY_OUT: out std_logic;
- INT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_PACKET_NUM_OUT:out std_logic_vector(c_NUM_WIDTH-1 downto 0);
- INT_READ_IN: in std_logic;
- INT_ERROR_OUT: out std_logic_vector (2 downto 0);
- -- Status and control port
- STAT_BUFFER: out std_logic_vector (31 downto 0)
- );
- end component;
-
-
-
-
- component trb_net16_trigger is
- generic (
- USE_TRG_PORT : integer range 0 to 1 := c_YES;
- --even when NO, ERROR_PACKET_IN is used for automatic replys
- SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE
- --if secure_mode is not used, apl must provide error pattern and dtype until
- --next trigger comes in. In secure mode these need to be available while relase_trg is high only
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- INT_DATAREADY_OUT: out std_logic;
- INT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_READ_IN: in std_logic;
-
- INT_DATAREADY_IN: in std_logic;
- INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_READ_OUT: out std_logic;
-
- -- Trigger information output
- TRG_TYPE_OUT : out std_logic_vector (3 downto 0);
- TRG_NUMBER_OUT : out std_logic_vector (15 downto 0);
- TRG_CODE_OUT : out std_logic_vector (7 downto 0);
- TRG_INFORMATION_OUT : out std_logic_vector (23 downto 0);
- TRG_RECEIVED_OUT : out std_logic;
- TRG_RELEASE_IN : in std_logic;
- TRG_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0)
- );
- end component;
-
-
-
- component trb_net16_tx_control is
- port(
- TXCLK_IN : in std_logic;
- RXCLK_IN : in std_logic;
- SYSCLK_IN : in std_logic;
- RESET_IN : in std_logic;
-
- TX_DATA_IN : in std_logic_vector(15 downto 0);
- TX_PACKET_NUMBER_IN : in std_logic_vector(2 downto 0);
- TX_WRITE_IN : in std_logic;
- TX_READ_OUT : out std_logic;
-
- TX_DATA_OUT : out std_logic_vector( 7 downto 0);
- TX_K_OUT : out std_logic;
-
- REQUEST_RETRANSMIT_IN : in std_logic;
- REQUEST_POSITION_IN : in std_logic_vector( 7 downto 0);
-
- START_RETRANSMIT_IN : in std_logic;
- START_POSITION_IN : in std_logic_vector( 7 downto 0);
-
- SEND_LINK_RESET_IN : in std_logic;
- TX_ALLOW_IN : in std_logic;
-
- DEBUG_OUT : out std_logic_vector(31 downto 0);
- STAT_REG_OUT : out std_logic_vector(31 downto 0)
- );
- end component;
-
-
-
-
- component wide_adder_17x16 is
- generic(
- SIZE : integer := 16;
- WORDS: integer := 17 --fixed
- );
- port(
- CLK : in std_logic;
- CLK_EN : in std_logic;
- RESET : in std_logic;
- INPUT_IN : in std_logic_vector(SIZE*WORDS-1 downto 0);
- START_IN : in std_logic;
- VAL_ENABLE_IN: in std_logic_vector(WORDS-1 downto 0);
- RESULT_OUT : out std_logic_vector(SIZE-1 downto 0);
- OVERFLOW_OUT : out std_logic;
- READY_OUT : out std_logic
- );
- end component;
-
-
- component trb_net_bridge_etrax_apl is
- port(
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*2**(c_MUX_WIDTH)-1 downto 0);
- APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*2**(c_MUX_WIDTH)-1 downto 0);
- APL_DATAREADY_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);
- APL_READ_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);
- APL_SHORT_TRANSFER_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);
- APL_DTYPE_OUT : out std_logic_vector (4*2**(c_MUX_WIDTH)-1 downto 0);
- APL_ERROR_PATTERN_OUT : out std_logic_vector (32*2**(c_MUX_WIDTH)-1 downto 0);
- APL_SEND_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);
- APL_TARGET_ADDRESS_OUT : out std_logic_vector (16*2**(c_MUX_WIDTH)-1 downto 0);
- APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH*2**(c_MUX_WIDTH)-1 downto 0);
- APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*2**(c_MUX_WIDTH)-1 downto 0);
- APL_TYP_IN : in std_logic_vector (3*2**(c_MUX_WIDTH)-1 downto 0);
- APL_DATAREADY_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);
- APL_READ_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);
- APL_RUN_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);
- APL_SEQNR_IN : in std_logic_vector (8*2**(c_MUX_WIDTH)-1 downto 0);
- CPU_READ : in STD_LOGIC;
- CPU_WRITE : in STD_LOGIC;
- CPU_DATA_OUT : out STD_LOGIC_VECTOR (31 downto 0);
- CPU_DATA_IN : in STD_LOGIC_VECTOR (31 downto 0);
- CPU_DATAREADY_OUT : out std_logic;
- CPU_ADDRESS : in STD_LOGIC_VECTOR (15 downto 0);
- STAT : out std_logic_vector (31 downto 0);
- CTRL : in std_logic_vector (31 downto 0)
- );
- end component;
-
-
+ DATA_COUNT_OUT : out std_logic_vector(10 downto 0);\r
+ FULL_OUT : out std_logic;\r
+ EMPTY_OUT : out std_logic\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net_fifo_16bit_bram_dualport is\r
+ generic(\r
+ USE_STATUS_FLAGS : integer := c_YES\r
+ );\r
+ port( read_clock_in : in std_logic;\r
+ write_clock_in : in std_logic;\r
+ read_enable_in : in std_logic;\r
+ write_enable_in : in std_logic;\r
+ fifo_gsr_in : in std_logic;\r
+ write_data_in : in std_logic_vector(17 downto 0);\r
+ read_data_out : out std_logic_vector(17 downto 0);\r
+ full_out : out std_logic;\r
+ empty_out : out std_logic;\r
+ fifostatus_out : out std_logic_vector(3 downto 0);\r
+ valid_read_out : out std_logic;\r
+ almost_empty_out : out std_logic;\r
+ almost_full_out : out std_logic\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+\r
+ component fifo_dualclock_width_16_reg is\r
+ port (\r
+ Data: in std_logic_vector(17 downto 0);\r
+ WrClock: in std_logic;\r
+ RdClock: in std_logic;\r
+ WrEn: in std_logic;\r
+ RdEn: in std_logic;\r
+ Reset: in std_logic;\r
+ RPReset: in std_logic;\r
+ Q: out std_logic_vector(17 downto 0);\r
+ Empty: out std_logic;\r
+ Full: out std_logic);\r
+ end component;\r
+\r
+\r
+\r
+\r
+-- component trb_net16_gbe_buf is\r
+-- generic(\r
+-- DO_SIMULATION : integer range 0 to 1 := 1;\r
+-- USE_125MHZ_EXTCLK : integer range 0 to 1 := 1\r
+-- );\r
+-- port(\r
+-- CLK : in std_logic;\r
+-- TEST_CLK : in std_logic; -- only for simulation!\r
+-- CLK_125_TX_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode\r
+-- CLK_125_RX_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode\r
+-- RESET : in std_logic;\r
+-- GSR_N : in std_logic;\r
+-- -- Debug\r
+-- STAGE_STAT_REGS_OUT : out std_logic_vector(31 downto 0);\r
+-- STAGE_CTRL_REGS_IN : in std_logic_vector(31 downto 0);\r
+-- -- configuration interface\r
+-- IP_CFG_START_IN : in std_logic;\r
+-- IP_CFG_BANK_SEL_IN : in std_logic_vector(3 downto 0);\r
+-- IP_CFG_DONE_OUT : out std_logic;\r
+-- IP_CFG_MEM_ADDR_OUT : out std_logic_vector(7 downto 0);\r
+-- IP_CFG_MEM_DATA_IN : in std_logic_vector(31 downto 0);\r
+-- IP_CFG_MEM_CLK_OUT : out std_logic;\r
+-- MR_RESET_IN : in std_logic;\r
+-- MR_MODE_IN : in std_logic;\r
+-- MR_RESTART_IN : in std_logic;\r
+-- -- gk 29.03.10\r
+-- SLV_ADDR_IN : in std_logic_vector(7 downto 0);\r
+-- SLV_READ_IN : in std_logic;\r
+-- SLV_WRITE_IN : in std_logic;\r
+-- SLV_BUSY_OUT : out std_logic;\r
+-- SLV_ACK_OUT : out std_logic;\r
+-- SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+-- SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+-- -- gk 22.04.10\r
+-- -- registers setup interface\r
+-- BUS_ADDR_IN : in std_logic_vector(7 downto 0);\r
+-- BUS_DATA_IN : in std_logic_vector(31 downto 0);\r
+-- BUS_DATA_OUT : out std_logic_vector(31 downto 0); -- gk 26.04.10\r
+-- BUS_WRITE_EN_IN : in std_logic; -- gk 26.04.10\r
+-- BUS_READ_EN_IN : in std_logic; -- gk 26.04.10\r
+-- BUS_ACK_OUT : out std_logic; -- gk 26.04.10\r
+-- -- gk 23.04.10\r
+-- LED_PACKET_SENT_OUT : out std_logic;\r
+-- LED_AN_DONE_N_OUT : out std_logic;\r
+-- -- CTS interface\r
+-- CTS_NUMBER_IN : in std_logic_vector (15 downto 0);\r
+-- CTS_CODE_IN : in std_logic_vector (7 downto 0);\r
+-- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0);\r
+-- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);\r
+-- CTS_START_READOUT_IN : in std_logic;\r
+-- CTS_DATA_OUT : out std_logic_vector (31 downto 0);\r
+-- CTS_DATAREADY_OUT : out std_logic;\r
+-- CTS_READOUT_FINISHED_OUT : out std_logic;\r
+-- CTS_READ_IN : in std_logic;\r
+-- CTS_LENGTH_OUT : out std_logic_vector (15 downto 0);\r
+-- CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);\r
+-- -- Data payload interface\r
+-- FEE_DATA_IN : in std_logic_vector (15 downto 0);\r
+-- FEE_DATAREADY_IN : in std_logic;\r
+-- FEE_READ_OUT : out std_logic;\r
+-- FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0);\r
+-- FEE_BUSY_IN : in std_logic;\r
+-- --SFP Connection\r
+-- SFP_RXD_P_IN : in std_logic;\r
+-- SFP_RXD_N_IN : in std_logic;\r
+-- SFP_TXD_P_OUT : out std_logic;\r
+-- SFP_TXD_N_OUT : out std_logic;\r
+-- SFP_REFCLK_P_IN : in std_logic;\r
+-- SFP_REFCLK_N_IN : in std_logic;\r
+-- SFP_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)\r
+-- SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)\r
+-- SFP_TXDIS_OUT : out std_logic; -- SFP disable\r
+-- -- debug ports\r
+-- ANALYZER_DEBUG_OUT : out std_logic_vector(63 downto 0)\r
+-- );\r
+-- end component;\r
+\r
+\r
+\r
+ component handler_data is\r
+ generic(\r
+ DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1;\r
+ DATA_BUFFER_DEPTH : integer range 9 to 14 := 9;\r
+ DATA_BUFFER_WIDTH : integer range 1 to 32 := 32;\r
+ DATA_BUFFER_FULL_THRESH : integer range 0 to 2**14-1 := 2**8;\r
+ TRG_RELEASE_AFTER_DATA : integer range 0 to 1 := c_YES;\r
+ HEADER_BUFFER_DEPTH : integer range 9 to 14 := 9;\r
+ HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-1 := 2**8\r
+ );\r
+ port(\r
+ CLOCK : in std_logic;\r
+ RESET : in std_logic;\r
+\r
+ --LVL1 Handler\r
+ LVL1_VALID_TRIGGER_IN : in std_logic; --received valid trigger, readout starts\r
+ LVL1_TRG_DATA_VALID_IN : in std_logic; --TRG Info valid & FEE busy\r
+ LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); --trigger type\r
+ LVL1_TRG_INFO_IN : in std_logic_vector(23 downto 0); --further trigger details\r
+ LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0);\r
+ LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); --trigger number\r
+ LVL1_STATUSBITS_OUT : out std_logic_vector(31 downto 0);\r
+ LVL1_TRG_RELEASE_OUT : out std_logic;\r
+\r
+ --FEE\r
+ FEE_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);\r
+ FEE_DATA_WRITE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
+ FEE_DATA_FINISHED_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
+ FEE_DATA_ALMOST_FULL_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
+\r
+ --IPU Handler\r
+ IPU_DATA_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);\r
+ IPU_DATA_READ_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
+ IPU_DATA_EMPTY_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
+ IPU_DATA_LENGTH_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER*16-1 downto 0);\r
+ IPU_DATA_FLAGS_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER*4-1 downto 0);\r
+\r
+ IPU_HDR_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ IPU_HDR_DATA_READ_IN : in std_logic;\r
+ IPU_HDR_DATA_EMPTY_OUT : out std_logic;\r
+\r
+ TMG_TRG_ERROR_IN : in std_logic;\r
+ --Status\r
+ STAT_DATA_BUFFER_LEVEL : out std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);\r
+ STAT_HEADER_BUFFER_LEVEL : out std_logic_vector(31 downto 0);\r
+\r
+ --Debug\r
+ DEBUG_OUT : out std_logic_vector(31 downto 0)\r
+ );\r
+\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+ component handler_ipu is\r
+ generic(\r
+ DATA_INTERFACE_NUMBER : integer range 1 to 7 := 1\r
+ );\r
+ port(\r
+ CLOCK : in std_logic;\r
+ RESET : in std_logic;\r
+\r
+ --From Data Handler\r
+ DAT_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);\r
+ DAT_DATA_READ_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
+ DAT_DATA_EMPTY_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
+ DAT_DATA_LENGTH_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*16-1 downto 0);\r
+ DAT_DATA_FLAGS_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*4-1 downto 0);\r
+ DAT_HDR_DATA_IN : in std_logic_vector(31 downto 0);\r
+ DAT_HDR_DATA_READ_OUT : out std_logic;\r
+ DAT_HDR_DATA_EMPTY_IN : in std_logic;\r
+\r
+ --To IPU Channel\r
+ IPU_NUMBER_IN : in std_logic_vector (15 downto 0);\r
+ IPU_INFORMATION_IN : in std_logic_vector (7 downto 0);\r
+ IPU_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);\r
+ IPU_START_READOUT_IN : in std_logic;\r
+ IPU_DATA_OUT : out std_logic_vector (31 downto 0);\r
+ IPU_DATAREADY_OUT : out std_logic;\r
+ IPU_READOUT_FINISHED_OUT : out std_logic;\r
+ IPU_READ_IN : in std_logic;\r
+ IPU_LENGTH_OUT : out std_logic_vector (15 downto 0);\r
+ IPU_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);\r
+\r
+ --Debug\r
+ STATUS_OUT : out std_logic_vector(31 downto 0)\r
+ );\r
+\r
+ end component;\r
+\r
+\r
+\r
+ component handler_lvl1 is\r
+ generic(\r
+ TIMING_TRIGGER_RAW : integer range 0 to 1 := c_YES\r
+ );\r
+ port(\r
+ RESET : in std_logic;\r
+ RESET_STATS_IN : in std_logic;\r
+ CLOCK : in std_logic;\r
+ --Timing Trigger\r
+ LVL1_TIMING_TRG_IN : in std_logic; --raw trigger signal input, min. 80 ns or strobe, see generics\r
+ LVL1_PSEUDO_TMG_TRG_IN : in std_logic; --strobe for dummy timing trigger\r
+ --LVL1_handler connection\r
+ LVL1_TRG_RECEIVED_IN : in std_logic;\r
+ LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0);\r
+ LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);\r
+ LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0);\r
+ LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0);\r
+ LVL1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); --errorbits to CTS\r
+ LVL1_TRG_RELEASE_OUT : out std_logic := '0'; --release to CTS\r
+\r
+ LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); -- increased after trigger release\r
+ LVL1_INT_TRG_LOAD_IN : in std_logic; -- load internal trigger counter\r
+ LVL1_INT_TRG_COUNTER_IN : in std_logic_vector(15 downto 0); -- load value for internal trigger counter\r
+\r
+ --FEE logic / Data Handler\r
+ LVL1_TRG_DATA_VALID_OUT : out std_logic; -- trigger type, number, code, information are valid\r
+ LVL1_VALID_TIMING_TRG_OUT : out std_logic; -- valid timing trigger has been received\r
+ LVL1_VALID_NOTIMING_TRG_OUT : out std_logic; -- valid trigger without timing trigger has been received\r
+ LVL1_INVALID_TRG_OUT : out std_logic; -- the current trigger is invalid (e.g. no timing trigger, no LVL1...)\r
+ LVL1_MULTIPLE_TRG_OUT : out std_logic; -- more than one timing trigger detected\r
+ LVL1_DELAY_OUT : out std_logic_vector(15 downto 0);\r
+ LVL1_TIMEOUT_DETECTED_OUT : out std_logic; -- gk 11.09.10\r
+ LVL1_SPURIOUS_TRG_OUT : out std_logic; -- gk 11.09.10\r
+ LVL1_MISSING_TMG_TRG_OUT : out std_logic; -- gk 11.09.10\r
+ SPIKE_DETECTED_OUT : out std_logic; -- gk 12.09.10\r
+\r
+ LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); -- error pattern from FEE\r
+ LVL1_TRG_RELEASE_IN : in std_logic := '0'; -- trigger release from FEE\r
+\r
+ --Stat/Control\r
+ STATUS_OUT : out std_logic_vector (63 downto 0); -- bits for status registers\r
+ TRG_ENABLE_IN : in std_logic; -- trigger enable flag\r
+ TRG_INVERT_IN : in std_logic; -- trigger invert flag\r
+ COUNTERS_STATUS_OUT : out std_logic_vector (63 downto 0);\r
+ --Debug\r
+ DEBUG_OUT : out std_logic_vector (15 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+ component handler_trigger_and_data is\r
+ generic(\r
+ DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1;\r
+ DATA_BUFFER_DEPTH : integer range 9 to 14 := 9;\r
+ DATA_BUFFER_WIDTH : integer range 1 to 32 := 32;\r
+ DATA_BUFFER_FULL_THRESH : integer range 0 to 2**14-1 := 2**8;\r
+ TRG_RELEASE_AFTER_DATA : integer range 0 to 1 := c_YES;\r
+ HEADER_BUFFER_DEPTH : integer range 9 to 14 := 9;\r
+ HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-1 := 2**8\r
+ );\r
+ port(\r
+ CLOCK : in std_logic;\r
+ RESET : in std_logic;\r
+ RESET_IPU : in std_logic;\r
+\r
+ --To Endpoint\r
+ --Timing Trigger (registered)\r
+ LVL1_VALID_TRIGGER_IN : in std_logic;\r
+ LVL1_INT_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);\r
+ --LVL1_handler connection\r
+ LVL1_TRG_DATA_VALID_IN : in std_logic;\r
+ LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0);\r
+ LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);\r
+ LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0);\r
+ LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0);\r
+ LVL1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0);\r
+ LVL1_TRG_RELEASE_OUT : out std_logic;\r
+\r
+ --IPU channel\r
+ IPU_NUMBER_IN : in std_logic_vector(15 downto 0);\r
+ IPU_INFORMATION_IN : in std_logic_vector(7 downto 0);\r
+ IPU_READOUT_TYPE_IN : in std_logic_vector(3 downto 0);\r
+ IPU_START_READOUT_IN : in std_logic;\r
+ IPU_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ IPU_DATAREADY_OUT : out std_logic;\r
+ IPU_READOUT_FINISHED_OUT : out std_logic;\r
+ IPU_READ_IN : in std_logic;\r
+ IPU_LENGTH_OUT : out std_logic_vector(15 downto 0);\r
+ IPU_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0);\r
+\r
+ --To FEE\r
+ --FEE to Trigger\r
+ FEE_TRG_RELEASE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
+ FEE_TRG_STATUSBITS_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);\r
+\r
+ --Data Input from FEE\r
+ FEE_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);\r
+ FEE_DATA_WRITE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
+ FEE_DATA_FINISHED_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
+ FEE_DATA_ALMOST_FULL_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
+\r
+ TMG_TRG_ERROR_IN : in std_logic;\r
+ --Status Registers\r
+ STATUS_OUT : out std_logic_vector(127 downto 0);\r
+ STAT_DATA_BUFFER_LEVEL : out std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);\r
+ STAT_HEADER_BUFFER_LEVEL : out std_logic_vector(31 downto 0);\r
+ TIMER_TICKS_IN : in std_logic_vector(1 downto 0);\r
+ STATISTICS_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ STATISTICS_ADDR_IN : in std_logic_vector(4 downto 0);\r
+ STATISTICS_READY_OUT : out std_logic;\r
+ STATISTICS_READ_IN : in std_logic;\r
+ STATISTICS_UNKNOWN_OUT : out std_logic;\r
+\r
+ --Debug\r
+ DEBUG_DATA_HANDLER_OUT : out std_logic_vector(31 downto 0);\r
+ DEBUG_IPU_HANDLER_OUT : out std_logic_vector(31 downto 0)\r
+\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net16_ibuf is\r
+ generic (\r
+ DEPTH : integer range 0 to 7 := c_FIFO_BRAM;\r
+ USE_VENDOR_CORES : integer range 0 to 1 := c_YES;\r
+ USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE;\r
+ USE_CHECKSUM : integer range 0 to 1 := c_YES;\r
+ SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;\r
+ INIT_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES;\r
+ REPLY_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES\r
+ );\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ -- Media direction port\r
+ MED_DATAREADY_IN : in std_logic;\r
+ MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ MED_READ_OUT : out std_logic;\r
+ MED_ERROR_IN : in std_logic_vector (2 downto 0);\r
+ -- Internal direction port\r
+ INT_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ INT_INIT_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ INT_INIT_DATAREADY_OUT : out std_logic;\r
+ INT_INIT_READ_IN : in std_logic;\r
+ INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ INT_REPLY_PACKET_NUM_OUT: out std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ INT_REPLY_DATAREADY_OUT : out std_logic;\r
+ INT_REPLY_READ_IN : in std_logic;\r
+ INT_ERROR_OUT : out std_logic_vector (2 downto 0);\r
+ -- Status and control port\r
+ STAT_BUFFER_COUNTER : out std_logic_vector (31 downto 0);\r
+ STAT_DATA_COUNTER : out std_logic_vector (31 downto 0);\r
+ STAT_BUFFER : out std_logic_vector (31 downto 0);\r
+ CTRL_STAT : in std_logic_vector (15 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+\r
+ component fifo_36x512 is\r
+ port (\r
+ Data: in std_logic_vector(35 downto 0);\r
+ Clock: in std_logic;\r
+ WrEn: in std_logic;\r
+ RdEn: in std_logic;\r
+ Reset: in std_logic;\r
+ Q: out std_logic_vector(35 downto 0);\r
+ Empty: out std_logic;\r
+ Full: out std_logic\r
+ );\r
+ end component;\r
+\r
+\r
+--component fifo_var_oreg is\r
+ --generic(\r
+ --FIFO_WIDTH : integer range 1 to 64 := 36;\r
+ --FIFO_DEPTH : integer range 1 to 16 := 8\r
+ --);\r
+ --port(\r
+ --Data : in std_logic_vector(FIFO_WIDTH-1 downto 0);\r
+ --Clock : in std_logic;\r
+ --WrEn : in std_logic;\r
+ --RdEn : in std_logic;\r
+ --Reset : in std_logic;\r
+ --AmFullThresh : in std_logic_vector(FIFO_DEPTH-1 downto 0);\r
+ --Q : out std_logic_vector(FIFO_WIDTH-1 downto 0);\r
+ --WCNT : out std_logic_vector(FIFO_DEPTH downto 0);\r
+ --Empty : out std_logic;\r
+ --Full : out std_logic;\r
+ --AlmostFull : out std_logic\r
+ --);\r
+--end component;\r
+\r
+\r
+\r
+ component trb_net16_iobuf is\r
+ generic (\r
+ IBUF_DEPTH : integer range 0 to 6 := c_FIFO_BRAM;--std_FIFO_DEPTH;\r
+ IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;--std_IBUF_SECURE_MODE;\r
+ SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;\r
+ SBUF_VERSION_OBUF : integer range 0 to 6 := std_SBUF_VERSION;\r
+ OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH;\r
+ USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE;\r
+ USE_CHECKSUM : integer range 0 to 1 := c_YES;\r
+ USE_VENDOR_CORES : integer range 0 to 1 := c_YES;\r
+ INIT_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES;\r
+ REPLY_CAN_RECEIVE_DATA: integer range 0 to 1 := c_YES;\r
+ INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES;\r
+ REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES\r
+ );\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ -- Media direction port\r
+ MED_INIT_DATAREADY_OUT : out std_logic;\r
+ MED_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_INIT_READ_IN : in std_logic;\r
+ MED_REPLY_DATAREADY_OUT : out std_logic;\r
+ MED_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_REPLY_READ_IN : in std_logic;\r
+ MED_DATAREADY_IN : in std_logic;\r
+ MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_READ_OUT : out std_logic;\r
+ MED_ERROR_IN : in std_logic_vector (2 downto 0);\r
+ -- Internal direction port\r
+ INT_INIT_DATAREADY_OUT : out std_logic;\r
+ INT_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ INT_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ INT_INIT_READ_IN : in std_logic;\r
+ INT_INIT_DATAREADY_IN : in std_logic;\r
+ INT_INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ INT_INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ INT_INIT_READ_OUT : out std_logic;\r
+ INT_REPLY_DATAREADY_OUT : out std_logic;\r
+ INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ INT_REPLY_READ_IN : in std_logic;\r
+ INT_REPLY_DATAREADY_IN : in std_logic;\r
+ INT_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ INT_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ INT_REPLY_READ_OUT : out std_logic;\r
+ -- Status and control port\r
+ STAT_GEN : out std_logic_vector (31 downto 0);\r
+ STAT_IBUF_BUFFER : out std_logic_vector (31 downto 0);\r
+ CTRL_GEN : in std_logic_vector (31 downto 0);\r
+ CTRL_OBUF_settings : in std_logic_vector (31 downto 0) := (others => '0');\r
+ STAT_INIT_OBUF_DEBUG : out std_logic_vector (31 downto 0);\r
+ STAT_REPLY_OBUF_DEBUG : out std_logic_vector (31 downto 0);\r
+ STAT_BUFFER_COUNTER : out std_logic_vector (31 downto 0);\r
+ STAT_DATA_COUNTER : out std_logic_vector (31 downto 0);\r
+ TIMER_TICKS_IN : in std_logic_vector (1 downto 0);\r
+ CTRL_STAT : in std_logic_vector (15 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net16_io_multiplexer is\r
+ generic(\r
+ USE_INPUT_SBUF : multiplexer_config_t := (others => c_NO)\r
+ );\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ -- Media direction port\r
+ MED_DATAREADY_IN : in STD_LOGIC;\r
+ MED_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);\r
+ MED_READ_OUT : out STD_LOGIC;\r
+ MED_DATAREADY_OUT : out STD_LOGIC;\r
+ MED_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);\r
+ MED_READ_IN : in STD_LOGIC;\r
+ -- Internal direction port\r
+ INT_DATA_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0);\r
+ INT_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto 0);\r
+ INT_DATAREADY_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0);\r
+ INT_READ_IN : in STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0);\r
+ INT_DATAREADY_IN : in STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0);\r
+ INT_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH*(2**c_MUX_WIDTH)-1 downto 0);\r
+ INT_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH*(2**c_MUX_WIDTH)-1 downto 0);\r
+ INT_READ_OUT : out STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0);\r
+ -- Status and control port\r
+ CTRL : in STD_LOGIC_VECTOR (31 downto 0);\r
+ STAT : out STD_LOGIC_VECTOR (31 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net16_ipudata is\r
+ generic(\r
+ DO_CHECKS : integer range c_NO to c_YES := c_YES\r
+ );\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ -- Port to API\r
+ API_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ API_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ API_DATAREADY_OUT : out std_logic;\r
+ API_READ_IN : in std_logic;\r
+ API_SHORT_TRANSFER_OUT : out std_logic;\r
+ API_DTYPE_OUT : out std_logic_vector (3 downto 0);\r
+ API_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);\r
+ API_SEND_OUT : out std_logic;\r
+ -- Receiver port\r
+ API_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ API_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ API_TYP_IN : in std_logic_vector (2 downto 0);\r
+ API_DATAREADY_IN : in std_logic;\r
+ API_READ_OUT : out std_logic;\r
+ -- APL Control port\r
+ API_RUN_IN : in std_logic;\r
+ API_SEQNR_IN : in std_logic_vector (7 downto 0);\r
+ API_LENGTH_OUT : out std_logic_vector (15 downto 0);\r
+ MY_ADDRESS_IN : in std_logic_vector (15 downto 0);\r
+\r
+ --Information received with request\r
+ IPU_NUMBER_OUT : out std_logic_vector (15 downto 0);\r
+ IPU_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0);\r
+ IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0);\r
+ IPU_CODE_OUT : out std_logic_vector (7 downto 0);\r
+ --start strobe\r
+ IPU_START_READOUT_OUT: out std_logic;\r
+ --detector data, equipped with DHDR\r
+ IPU_DATA_IN : in std_logic_vector (31 downto 0);\r
+ IPU_DATAREADY_IN : in std_logic;\r
+ --no more data, end transfer, send TRM\r
+ IPU_READOUT_FINISHED_IN : in std_logic;\r
+ --will be low every second cycle due to 32bit -> 16bit conversion\r
+ IPU_READ_OUT : out std_logic;\r
+ IPU_LENGTH_IN : in std_logic_vector (15 downto 0);\r
+ IPU_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0);\r
+\r
+ STAT_DEBUG : out std_logic_vector(31 downto 0)\r
+ );\r
+ end component;\r
+\r
+component trb_net16_gbe_buf is\r
+generic(\r
+ DO_SIMULATION : integer range 0 to 1 := 1;\r
+ USE_125MHZ_EXTCLK : integer range 0 to 1 := 1\r
+);\r
+port(\r
+ CLK : in std_logic;\r
+ TEST_CLK : in std_logic; -- only for simulation!\r
+ CLK_125_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode\r
+ RESET : in std_logic;\r
+ GSR_N : in std_logic;\r
+ -- Debug\r
+ STAGE_STAT_REGS_OUT : out std_logic_vector(31 downto 0);\r
+ STAGE_CTRL_REGS_IN : in std_logic_vector(31 downto 0);\r
+ -- configuration interface\r
+ IP_CFG_START_IN : in std_logic;\r
+ IP_CFG_BANK_SEL_IN : in std_logic_vector(3 downto 0);\r
+ IP_CFG_DONE_OUT : out std_logic;\r
+ IP_CFG_MEM_ADDR_OUT : out std_logic_vector(7 downto 0);\r
+ IP_CFG_MEM_DATA_IN : in std_logic_vector(31 downto 0);\r
+ IP_CFG_MEM_CLK_OUT : out std_logic;\r
+ MR_RESET_IN : in std_logic;\r
+ MR_MODE_IN : in std_logic;\r
+ MR_RESTART_IN : in std_logic;\r
+ -- gk 29.03.10\r
+ SLV_ADDR_IN : in std_logic_vector(7 downto 0);\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_BUSY_OUT : out std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- gk 22.04.10\r
+ -- registers setup interface\r
+ BUS_ADDR_IN : in std_logic_vector(7 downto 0);\r
+ BUS_DATA_IN : in std_logic_vector(31 downto 0);\r
+ BUS_DATA_OUT : out std_logic_vector(31 downto 0); -- gk 26.04.10\r
+ BUS_WRITE_EN_IN : in std_logic; -- gk 26.04.10\r
+ BUS_READ_EN_IN : in std_logic; -- gk 26.04.10\r
+ BUS_ACK_OUT : out std_logic; -- gk 26.04.10\r
+ -- gk 23.04.10\r
+ LED_PACKET_SENT_OUT : out std_logic;\r
+ LED_AN_DONE_N_OUT : out std_logic;\r
+ -- CTS interface\r
+ CTS_NUMBER_IN : in std_logic_vector (15 downto 0);\r
+ CTS_CODE_IN : in std_logic_vector (7 downto 0);\r
+ CTS_INFORMATION_IN : in std_logic_vector (7 downto 0);\r
+ CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);\r
+ CTS_START_READOUT_IN : in std_logic;\r
+ CTS_DATA_OUT : out std_logic_vector (31 downto 0);\r
+ CTS_DATAREADY_OUT : out std_logic;\r
+ CTS_READOUT_FINISHED_OUT : out std_logic;\r
+ CTS_READ_IN : in std_logic;\r
+ CTS_LENGTH_OUT : out std_logic_vector (15 downto 0);\r
+ CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);\r
+ -- Data payload interface\r
+ FEE_DATA_IN : in std_logic_vector (15 downto 0);\r
+ FEE_DATAREADY_IN : in std_logic;\r
+ FEE_READ_OUT : out std_logic;\r
+ FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0);\r
+ FEE_BUSY_IN : in std_logic;\r
+ --SFP Connection\r
+ SFP_RXD_P_IN : in std_logic;\r
+ SFP_RXD_N_IN : in std_logic;\r
+ SFP_TXD_P_OUT : out std_logic;\r
+ SFP_TXD_N_OUT : out std_logic;\r
+ SFP_REFCLK_P_IN : in std_logic;\r
+ SFP_REFCLK_N_IN : in std_logic;\r
+ SFP_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)\r
+ SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)\r
+ SFP_TXDIS_OUT : out std_logic; -- SFP disable\r
+ -- debug ports\r
+ ANALYZER_DEBUG_OUT : out std_logic_vector(63 downto 0)\r
+);\r
+end component;\r
+\r
+\r
+\r
+\r
+ component ipu_dummy is\r
+ port( CLK_IN : in std_logic; -- 100MHz local clock\r
+ CLEAR_IN : in std_logic;\r
+ RESET_IN : in std_logic; -- synchronous reset\r
+ -- Slow control signals\r
+ MIN_COUNT_IN : in std_logic_vector(15 downto 0); -- minimum counter value\r
+ MAX_COUNT_IN : in std_logic_vector(15 downto 0); -- maximum counter value\r
+ CTRL_IN : in std_logic_vector(7 downto 0); -- control bits from slow control\r
+ -- IPU channel connections\r
+ IPU_NUMBER_IN : in std_logic_vector(15 downto 0); -- trigger tag\r
+ IPU_INFORMATION_IN : in std_logic_vector(7 downto 0); -- trigger information\r
+ IPU_START_READOUT_IN : in std_logic; -- gimme data!\r
+ IPU_DATA_OUT : out std_logic_vector(31 downto 0); -- detector data, equipped with DHDR\r
+ IPU_DATAREADY_OUT : out std_logic; -- data is valid\r
+ IPU_READOUT_FINISHED_OUT : out std_logic; -- no more data, end transfer, send TRM\r
+ IPU_READ_IN : in std_logic; -- read strobe, low every second cycle\r
+ IPU_LENGTH_OUT : out std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?)\r
+ IPU_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); -- error pattern\r
+ -- DHDR buffer\r
+ LVL1_FIFO_RD_OUT : out std_logic;\r
+ LVL1_FIFO_EMPTY_IN : in std_logic;\r
+ LVL1_FIFO_NUMBER_IN : in std_logic_vector(15 downto 0);\r
+ LVL1_FIFO_CODE_IN : in std_logic_vector(7 downto 0);\r
+ LVL1_FIFO_INFORMATION_IN : in std_logic_vector(7 downto 0);\r
+ LVL1_FIFO_TYPE_IN : in std_logic_vector(3 downto 0);\r
+ -- Debug signals\r
+ DBG_BSM_OUT : out std_logic_vector(7 downto 0);\r
+ DBG_OUT : out std_logic_vector(31 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net16_lsm_sfp is\r
+ generic(\r
+ CHECK_FOR_CV : integer := c_YES\r
+ );\r
+ port(\r
+ SYSCLK : in std_logic; -- fabric clock\r
+ RESET : in std_logic; -- synchronous reset\r
+ CLEAR : in std_logic; -- asynchronous reset, connect to '0' if not needed / available\r
+ -- status signals\r
+ SFP_MISSING_IN : in std_logic; -- SFP Present ('0' = no SFP mounted, '1' = SFP in place)\r
+ SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)\r
+ SD_LINK_OK_IN : in std_logic; -- SerDes Link OK ('0' = not linked, '1' link established)\r
+ SD_LOS_IN : in std_logic; -- SerDes Loss Of Signal ('0' = OK, '1' = signal lost)\r
+ SD_TXCLK_BAD_IN : in std_logic; -- SerDes Tx Clock locked ('0' = locked, '1' = not locked)\r
+ SD_RXCLK_BAD_IN : in std_logic; -- SerDes Rx Clock locked ('0' = locked, '1' = not locked)\r
+ SD_RETRY_IN : in std_logic; -- '0' = handle byte swapping in logic, '1' = simply restart link and hope\r
+ SD_ALIGNMENT_IN : in std_logic_vector(1 downto 0); -- SerDes Byte alignment ("10" = swapped, "01" = correct)\r
+ SD_CV_IN : in std_logic_vector(1 downto 0); -- SerDes Code Violation ("00" = OK, everything else = BAD)\r
+ -- control signals\r
+ FULL_RESET_OUT : out std_logic; -- full reset AKA quad_reset\r
+ LANE_RESET_OUT : out std_logic; -- partial reset AKA lane_reset\r
+ TX_ALLOW_OUT : out std_logic; -- allow normal transmit operation\r
+ RX_ALLOW_OUT : out std_logic; -- allow normal receive operation\r
+ SWAP_BYTES_OUT : out std_logic; -- bytes need swapping ('0' = correct order, '1' = swapped order)\r
+ -- debug signals\r
+ STAT_OP : out std_logic_vector(15 downto 0);\r
+ CTRL_OP : in std_logic_vector(15 downto 0);\r
+ STAT_DEBUG : out std_logic_vector(31 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net16_med_8_SDR_OS is\r
+ generic(\r
+ TRANSMISSION_CLOCK_DIV: integer range 1 to 10 := 1\r
+ );\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+\r
+ INT_DATAREADY_OUT : out std_logic;\r
+ INT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ INT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ INT_READ_IN : in std_logic;\r
+\r
+ INT_DATAREADY_IN : in std_logic;\r
+ INT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ INT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ INT_READ_OUT : out std_logic;\r
+\r
+ -- Media direction port\r
+ TX_DATA_OUT : out std_logic_vector (7 downto 0);\r
+ TX_CLK_OUT : out std_logic;\r
+ TX_CTRL_OUT : out std_logic_vector (1 downto 0);\r
+ RX_DATA_IN : in std_logic_vector (7 downto 0);\r
+ RX_CLK_IN : in std_logic;\r
+ RX_CTRL_IN : in std_logic_vector (1 downto 0);\r
+\r
+ -- Status and control port\r
+ STAT_OP: out std_logic_vector (15 downto 0);\r
+ CTRL_OP: in std_logic_vector (15 downto 0);\r
+\r
+ STAT: out std_logic_vector (31 downto 0);\r
+ CTRL: in std_logic_vector (31 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net16_med_ecp_fot is\r
+ port(\r
+ CLK : in std_logic;\r
+ CLK_25 : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ RESET : in std_logic;\r
+ CLEAR : in std_logic;\r
+\r
+ --Internal Connection\r
+ MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ MED_DATAREADY_IN : in std_logic;\r
+ MED_READ_OUT : out std_logic;\r
+ MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ MED_DATAREADY_OUT : out std_logic;\r
+ MED_READ_IN : in std_logic;\r
+\r
+ --SFP Connection\r
+ TXP : out std_logic;\r
+ TXN : out std_logic;\r
+ RXP : in std_logic;\r
+ RXN : in std_logic;\r
+ SD : in std_logic;\r
+\r
+ -- Status and control port\r
+ STAT_OP : out std_logic_vector (15 downto 0);\r
+ CTRL_OP : in std_logic_vector (15 downto 0);\r
+ STAT_REG_OUT : out std_logic_vector(127 downto 0);\r
+ STAT_DEBUG : out std_logic_vector (63 downto 0);\r
+ CTRL_DEBUG : in std_logic_vector (15 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net16_med_ecp_fot_4 is\r
+ generic(\r
+ REVERSE_ORDER : integer range 0 to 1 := c_NO\r
+ -- USED_PORTS : std_logic-vector(3 downto 0) := "1111"\r
+ );\r
+ port(\r
+ CLK : in std_logic;\r
+ CLK_25 : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ RESET : in std_logic;\r
+ --Internal Connection\r
+ MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH*4-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH*4-1 downto 0);\r
+ MED_DATAREADY_IN : in std_logic_vector(3 downto 0);\r
+ MED_READ_OUT : out std_logic_vector(3 downto 0);\r
+ MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH*4-1 downto 0);\r
+ MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH*4-1 downto 0);\r
+ MED_DATAREADY_OUT : out std_logic_vector(3 downto 0);\r
+ MED_READ_IN : in std_logic_vector(3 downto 0);\r
+ --SFP Connection\r
+ TXP : out std_logic_vector(3 downto 0);\r
+ TXN : out std_logic_vector(3 downto 0);\r
+ RXP : in std_logic_vector(3 downto 0);\r
+ RXN : in std_logic_vector(3 downto 0);\r
+ SD : in std_logic_vector(3 downto 0);\r
+ -- Status and control port\r
+ STAT_OP : out std_logic_vector (63 downto 0);\r
+ CTRL_OP : in std_logic_vector (63 downto 0);\r
+ STAT_REG_OUT : out std_logic_vector(127 downto 0);\r
+ STAT_DEBUG : out std_logic_vector (255 downto 0);\r
+ CTRL_DEBUG : in std_logic_vector (63 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net16_med_ecp_fot_4_ctc is\r
+ generic(\r
+ REVERSE_ORDER : integer range 0 to 1 := c_NO\r
+ -- USED_PORTS : std_logic-vector(3 downto 0) := "1111"\r
+ );\r
+ port(\r
+ CLK : in std_logic;\r
+ CLK_25 : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ RESET : in std_logic;\r
+ CLEAR : in std_logic;\r
+ --Internal Connection\r
+ MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH*4-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH*4-1 downto 0);\r
+ MED_DATAREADY_IN : in std_logic_vector(3 downto 0);\r
+ MED_READ_OUT : out std_logic_vector(3 downto 0);\r
+ MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH*4-1 downto 0);\r
+ MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH*4-1 downto 0);\r
+ MED_DATAREADY_OUT : out std_logic_vector(3 downto 0);\r
+ MED_READ_IN : in std_logic_vector(3 downto 0);\r
+\r
+ --SFP Connection\r
+ TXP : out std_logic_vector(3 downto 0);\r
+ TXN : out std_logic_vector(3 downto 0);\r
+ RXP : in std_logic_vector(3 downto 0);\r
+ RXN : in std_logic_vector(3 downto 0);\r
+ SD : in std_logic_vector(3 downto 0);\r
+\r
+ -- Status and control port\r
+ STAT_OP : out std_logic_vector (63 downto 0);\r
+ CTRL_OP : in std_logic_vector (63 downto 0);\r
+ STAT_REG_OUT : out std_logic_vector (511 downto 0);\r
+ STAT_DEBUG : out std_logic_vector (255 downto 0);\r
+ CTRL_DEBUG : in std_logic_vector (63 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net16_med_ecp_sfp is\r
+ generic(\r
+ SERDES_NUM : integer range 0 to 3 := 0;\r
+ EXT_CLOCK : integer range 0 to 1 := c_NO\r
+ );\r
+ port(\r
+ CLK : in std_logic; -- SerDes clock\r
+ SYSCLK : in std_logic; -- fabric clock\r
+ RESET : in std_logic; -- synchronous reset\r
+ CLEAR : in std_logic; -- asynchronous reset\r
+ CLK_EN : in std_logic;\r
+ --Internal Connection\r
+ MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ MED_DATAREADY_IN : in std_logic;\r
+ MED_READ_OUT : out std_logic;\r
+ MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ MED_DATAREADY_OUT : out std_logic;\r
+ MED_READ_IN : in std_logic;\r
+ REFCLK2CORE_OUT : out std_logic;\r
+ --SFP Connection\r
+ SD_RXD_P_IN : in std_logic;\r
+ SD_RXD_N_IN : in std_logic;\r
+ SD_TXD_P_OUT : out std_logic;\r
+ SD_TXD_N_OUT : out std_logic;\r
+ SD_REFCLK_P_IN : in std_logic;\r
+ SD_REFCLK_N_IN : in std_logic;\r
+ SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)\r
+ SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)\r
+ SD_TXDIS_OUT : out std_logic; -- SFP disable\r
+ -- Status and control port\r
+ STAT_OP : out std_logic_vector (15 downto 0);\r
+ CTRL_OP : in std_logic_vector (15 downto 0);\r
+ STAT_DEBUG : out std_logic_vector (63 downto 0);\r
+ CTRL_DEBUG : in std_logic_vector (63 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net16_med_ecp_sfp_gbe is\r
+ generic(\r
+ SERDES_NUM : integer range 0 to 3 := 0;\r
+ EXT_CLOCK : integer range 0 to 1 := c_NO;\r
+ USE_200_MHZ : integer range 0 to 1 := c_NO\r
+ );\r
+ port(\r
+ CLK : in std_logic; -- SerDes clock\r
+ SYSCLK : in std_logic; -- fabric clock\r
+ RESET : in std_logic; -- synchronous reset\r
+ CLEAR : in std_logic; -- asynchronous reset\r
+ CLK_EN : in std_logic;\r
+ --Internal Connection\r
+ MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ MED_DATAREADY_IN : in std_logic;\r
+ MED_READ_OUT : out std_logic;\r
+ MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ MED_DATAREADY_OUT : out std_logic;\r
+ MED_READ_IN : in std_logic;\r
+ REFCLK2CORE_OUT : out std_logic;\r
+ --SFP Connection\r
+ SD_RXD_P_IN : in std_logic;\r
+ SD_RXD_N_IN : in std_logic;\r
+ SD_TXD_P_OUT : out std_logic;\r
+ SD_TXD_N_OUT : out std_logic;\r
+ SD_REFCLK_P_IN : in std_logic;\r
+ SD_REFCLK_N_IN : in std_logic;\r
+ SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)\r
+ SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)\r
+ SD_TXDIS_OUT : out std_logic; -- SFP disable\r
+ -- Status and control port\r
+ STAT_OP : out std_logic_vector (15 downto 0);\r
+ CTRL_OP : in std_logic_vector (15 downto 0);\r
+ STAT_DEBUG : out std_logic_vector (63 downto 0);\r
+ CTRL_DEBUG : in std_logic_vector (63 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+ component trb_net16_med_ecp_sfp_4 is\r
+ generic(\r
+ REVERSE_ORDER : integer range 0 to 1 := c_NO\r
+ -- USED_PORTS : std_logic-vector(3 downto 0) := "1111"\r
+ );\r
+ port(\r
+ CLK : in std_logic; -- SerDes clock\r
+ SYSCLK : in std_logic; -- fabric clock\r
+ RESET : in std_logic; -- synchronous reset\r
+ CLEAR : in std_logic; -- asynchronous reset\r
+ CLK_EN : in std_logic;\r
+ --Internal Connection\r
+ MED_DATA_IN : in std_logic_vector(4*c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector(4*c_NUM_WIDTH-1 downto 0);\r
+ MED_DATAREADY_IN : in std_logic_vector(3 downto 0);\r
+ MED_READ_OUT : out std_logic_vector(3 downto 0);\r
+ MED_DATA_OUT : out std_logic_vector(4*c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_OUT : out std_logic_vector(4*c_NUM_WIDTH-1 downto 0);\r
+ MED_DATAREADY_OUT : out std_logic_vector(3 downto 0);\r
+ MED_READ_IN : in std_logic_vector(3 downto 0);\r
+ REFCLK2CORE_OUT : out std_logic;\r
+ --SFP Connection\r
+ SD_RXD_P_IN : in std_logic_vector(3 downto 0);\r
+ SD_RXD_N_IN : in std_logic_vector(3 downto 0);\r
+ SD_TXD_P_OUT : out std_logic_vector(3 downto 0);\r
+ SD_TXD_N_OUT : out std_logic_vector(3 downto 0);\r
+ SD_REFCLK_P_IN : in std_logic;\r
+ SD_REFCLK_N_IN : in std_logic;\r
+ SD_PRSNT_N_IN : in std_logic_vector(3 downto 0);\r
+ SD_LOS_IN : in std_logic_vector(3 downto 0);\r
+ SD_TXDIS_OUT : out std_logic_vector(3 downto 0);\r
+ -- Status and control port\r
+ STAT_OP : out std_logic_vector (4*16-1 downto 0);\r
+ CTRL_OP : in std_logic_vector (4*16-1 downto 0);\r
+ STAT_DEBUG : out std_logic_vector (63 downto 0);\r
+ CTRL_DEBUG : in std_logic_vector (63 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+ component trb_net16_med_ecp_sfp_4_gbe is\r
+ generic(\r
+ REVERSE_ORDER : integer range 0 to 1 := c_NO\r
+ -- USED_PORTS : std_logic-vector(3 downto 0) := "1111"\r
+ );\r
+ port(\r
+ CLK : in std_logic; -- SerDes clock\r
+ SYSCLK : in std_logic; -- fabric clock\r
+ RESET : in std_logic; -- synchronous reset\r
+ CLEAR : in std_logic; -- asynchronous reset\r
+ CLK_EN : in std_logic;\r
+ --Internal Connection\r
+ MED_DATA_IN : in std_logic_vector(4*c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector(4*c_NUM_WIDTH-1 downto 0);\r
+ MED_DATAREADY_IN : in std_logic_vector(3 downto 0);\r
+ MED_READ_OUT : out std_logic_vector(3 downto 0);\r
+ MED_DATA_OUT : out std_logic_vector(4*c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_OUT : out std_logic_vector(4*c_NUM_WIDTH-1 downto 0);\r
+ MED_DATAREADY_OUT : out std_logic_vector(3 downto 0);\r
+ MED_READ_IN : in std_logic_vector(3 downto 0);\r
+ REFCLK2CORE_OUT : out std_logic;\r
+ --SFP Connection\r
+ SD_RXD_P_IN : in std_logic_vector(3 downto 0);\r
+ SD_RXD_N_IN : in std_logic_vector(3 downto 0);\r
+ SD_TXD_P_OUT : out std_logic_vector(3 downto 0);\r
+ SD_TXD_N_OUT : out std_logic_vector(3 downto 0);\r
+ SD_REFCLK_P_IN : in std_logic;\r
+ SD_REFCLK_N_IN : in std_logic;\r
+ SD_PRSNT_N_IN : in std_logic_vector(3 downto 0);\r
+ SD_LOS_IN : in std_logic_vector(3 downto 0);\r
+ SD_TXDIS_OUT : out std_logic_vector(3 downto 0);\r
+ -- Status and control port\r
+ STAT_OP : out std_logic_vector (4*16-1 downto 0);\r
+ CTRL_OP : in std_logic_vector (4*16-1 downto 0);\r
+ STAT_DEBUG : out std_logic_vector (63 downto 0);\r
+ CTRL_DEBUG : in std_logic_vector (63 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net16_med_16_CC is\r
+ port(\r
+ CLK : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ RESET : in std_logic;\r
+\r
+ --Internal Connection\r
+ MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ MED_DATAREADY_IN : in std_logic;\r
+ MED_READ_OUT : out std_logic;\r
+ MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ MED_DATAREADY_OUT : out std_logic;\r
+ MED_READ_IN : in std_logic;\r
+\r
+ DATA_OUT : out std_logic_vector(15 downto 0);\r
+ DATA_VALID_OUT : out std_logic;\r
+ DATA_CTRL_OUT : out std_logic;\r
+ DATA_IN : in std_logic_vector(15 downto 0);\r
+ DATA_VALID_IN : in std_logic;\r
+ DATA_CTRL_IN : in std_logic;\r
+\r
+ STAT_OP : out std_logic_vector(15 downto 0);\r
+ CTRL_OP : in std_logic_vector(15 downto 0);\r
+ STAT_DEBUG : out std_logic_vector(63 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+ component trb_net16_med_16_IC is\r
+ generic(\r
+ DATA_CLK_OUT_PHASE : std_logic := '1'\r
+ );\r
+ port(\r
+ CLK : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ RESET : in std_logic;\r
+\r
+ --Internal Connection\r
+ MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ MED_DATAREADY_IN : in std_logic;\r
+ MED_READ_OUT : out std_logic;\r
+ MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ MED_DATAREADY_OUT : out std_logic;\r
+ MED_READ_IN : in std_logic;\r
+\r
+ DATA_OUT : out std_logic_vector(15 downto 0);\r
+ DATA_VALID_OUT : out std_logic;\r
+ DATA_CTRL_OUT : out std_logic;\r
+ DATA_CLK_OUT : out std_logic;\r
+ DATA_IN : in std_logic_vector(15 downto 0);\r
+ DATA_VALID_IN : in std_logic;\r
+ DATA_CTRL_IN : in std_logic;\r
+ DATA_CLK_IN : in std_logic;\r
+\r
+ STAT_OP : out std_logic_vector(15 downto 0);\r
+ CTRL_OP : in std_logic_vector(15 downto 0);\r
+ STAT_DEBUG : out std_logic_vector(63 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+ component trb_net16_med_tlk is\r
+ port (\r
+ RESET : in std_logic;\r
+ CLK : in std_logic;\r
+ TLK_CLK : in std_logic;\r
+ TLK_ENABLE : out std_logic;\r
+ TLK_LCKREFN : out std_logic;\r
+ TLK_LOOPEN : out std_logic;\r
+ TLK_PRBSEN : out std_logic;\r
+ TLK_RXD : in std_logic_vector(15 downto 0);\r
+ TLK_RX_CLK : in std_logic;\r
+ TLK_RX_DV : in std_logic;\r
+ TLK_RX_ER : in std_logic;\r
+ TLK_TXD : out std_logic_vector(15 downto 0);\r
+ TLK_TX_EN : out std_logic;\r
+ TLK_TX_ER : out std_logic;\r
+ SFP_LOS : in std_logic;\r
+ SFP_TX_DIS : out std_logic;\r
+ MED_DATAREADY_IN : in std_logic;\r
+ MED_READ_IN : in std_logic;\r
+ MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_DATAREADY_OUT : out std_logic;\r
+ MED_READ_OUT : out std_logic;\r
+ MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ STAT : out std_logic_vector (63 downto 0);\r
+ STAT_MONITOR : out std_logic_vector ( 100 downto 0);\r
+ STAT_OP : out std_logic_vector (15 downto 0);\r
+ CTRL_OP : in std_logic_vector (15 downto 0)\r
+ --connect STAT(0) to LED\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net_onewire is\r
+ generic(\r
+ USE_TEMPERATURE_READOUT : integer range 0 to 1 := 1;\r
+ CLK_PERIOD : integer := 10 --clk period in ns\r
+ );\r
+ port(\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ READOUT_ENABLE_IN : in std_logic := '1';\r
+ --connection to 1-wire interface\r
+ ONEWIRE : inout std_logic;\r
+ MONITOR_OUT : out std_logic;\r
+ --connection to id ram, according to memory map in TrbNetRegIO\r
+ DATA_OUT : out std_logic_vector(15 downto 0);\r
+ ADDR_OUT : out std_logic_vector(2 downto 0);\r
+ WRITE_OUT: out std_logic;\r
+ TEMP_OUT : out std_logic_vector(11 downto 0);\r
+ STAT : out std_logic_vector(31 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net_onewire_listener is\r
+ port(\r
+ CLK : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ RESET : in std_logic;\r
+ MONITOR_IN : in std_logic;\r
+ DATA_OUT : out std_logic_vector(15 downto 0);\r
+ ADDR_OUT : out std_logic_vector(2 downto 0);\r
+ WRITE_OUT: out std_logic;\r
+ TEMP_OUT : out std_logic_vector(11 downto 0);\r
+ STAT : out std_logic_vector(31 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net16_obuf is\r
+ generic (\r
+ DATA_COUNT_WIDTH : integer := 5;\r
+ USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE;\r
+ USE_CHECKSUM : integer range 0 to 1 := c_YES;\r
+ SBUF_VERSION : integer range 0 to 6 := std_SBUF_VERSION\r
+ );\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ -- Media direction port\r
+ MED_DATAREADY_OUT: out std_logic;\r
+ MED_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_READ_IN: in std_logic;\r
+ -- Internal direction port\r
+ INT_DATAREADY_IN: in std_logic;\r
+ INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ INT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ INT_READ_OUT: out std_logic;\r
+ -- Status and control port\r
+ STAT_BUFFER: out std_logic_vector (31 downto 0);\r
+ CTRL_BUFFER: in std_logic_vector (31 downto 0);\r
+ CTRL_SETTINGS : in std_logic_vector (15 downto 0);\r
+ STAT_DEBUG : out std_logic_vector (31 downto 0);\r
+ TIMER_TICKS_IN : in std_logic_vector (1 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net16_obuf_nodata is\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ -- Media direction port\r
+ MED_DATAREADY_OUT: out std_logic;\r
+ MED_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_READ_IN: in std_logic;\r
+ --STAT\r
+ STAT_BUFFER: out std_logic_vector (31 downto 0);\r
+ CTRL_BUFFER: in std_logic_vector (31 downto 0);\r
+ STAT_DEBUG : out std_logic_vector (31 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+ component pll_in100_out100 is\r
+ port (\r
+ CLK: in std_logic;\r
+ CLKOP: out std_logic;\r
+ CLKOS: out std_logic;\r
+ LOCK: out std_logic\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+ component pll_in100_out20 is\r
+ port (\r
+ CLK: in std_logic;\r
+ CLKOP: out std_logic;\r
+ LOCK: out std_logic\r
+ );\r
+ end component;\r
+\r
+\r
+ component pll_in200_out100 is\r
+ port (\r
+ CLK: in std_logic;\r
+ CLKOP: out std_logic;\r
+ CLKOS: out std_logic;\r
+ LOCK: out std_logic\r
+ );\r
+ end component;\r
+\r
+\r
+ component pll_in100_out25 is\r
+ port (\r
+ CLK: in std_logic;\r
+ CLKOP: out std_logic;\r
+ LOCK: out std_logic\r
+ );\r
+ end component;\r
+\r
+\r
+ component pll25 is\r
+ port(\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLKOP : out std_logic;\r
+ CLKOK : out std_logic;\r
+ LOCK : out std_logic\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+\r
+ component pll_in25_out100 is\r
+ port (\r
+ CLK: in std_logic;\r
+ CLKOP: out std_logic;\r
+ LOCK: out std_logic\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net_pattern_gen is\r
+ generic (\r
+ WIDTH : integer := 6\r
+ );\r
+ port(\r
+ INPUT_IN : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);\r
+ RESULT_OUT: out STD_LOGIC_VECTOR (2**WIDTH-1 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net_priority_arbiter is\r
+ generic (\r
+ WIDTH : integer := 2\r
+ );\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ INPUT_IN : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);\r
+ RESULT_OUT: out STD_LOGIC_VECTOR (WIDTH-1 downto 0);\r
+ ENABLE : in std_logic;\r
+ CTRL: in STD_LOGIC_VECTOR (9 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+ component pulse_sync is\r
+ port(\r
+ CLK_A_IN : in std_logic;\r
+ RESET_A_IN : in std_logic;\r
+ PULSE_A_IN : in std_logic;\r
+ CLK_B_IN : in std_logic;\r
+ RESET_B_IN : in std_logic;\r
+ PULSE_B_OUT : out std_logic\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+ component ram_dp is\r
+ generic(\r
+ depth : integer := 3;\r
+ width : integer := 16\r
+ );\r
+ port(\r
+ CLK : in std_logic;\r
+ wr1 : in std_logic;\r
+ a1 : in std_logic_vector(depth-1 downto 0);\r
+ dout1 : out std_logic_vector(width-1 downto 0);\r
+ din1 : in std_logic_vector(width-1 downto 0);\r
+ a2 : in std_logic_vector(depth-1 downto 0);\r
+ dout2 : out std_logic_vector(width-1 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+ component ram_dp_rw\r
+ generic(\r
+ depth : integer := 3;\r
+ width : integer := 16\r
+ );\r
+ port(\r
+ CLK : in std_logic;\r
+ wr1 : in std_logic;\r
+ a1 : in std_logic_vector(depth-1 downto 0);\r
+ din1 : in std_logic_vector(width-1 downto 0);\r
+ a2 : in std_logic_vector(depth-1 downto 0);\r
+ dout2 : out std_logic_vector(width-1 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+ component trb_net16_regIO is\r
+ generic (\r
+ NUM_STAT_REGS : integer range 0 to 6 := 4; --log2 of number of status registers\r
+ NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers\r
+ --standard values for output registers\r
+ INIT_CTRL_REGS : std_logic_vector(2**(4)*32-1 downto 0) := (others => '0');\r
+ --set to 0 for unused ctrl registers to save resources\r
+ USED_CTRL_REGS : std_logic_vector(2**(4)-1 downto 0) := (others => '1');\r
+ --set to 0 for each unused bit in a register\r
+ USED_CTRL_BITMASK : std_logic_vector(2**(4)*32-1 downto 0) := (others => '1');\r
+ USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port\r
+ INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";\r
+ INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876";\r
+ INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222";\r
+ INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001";\r
+ COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";\r
+ COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";\r
+ HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";\r
+ CLOCK_FREQ : integer range 1 to 200 := 100 --MHz\r
+ );\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ -- Port to API\r
+ API_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ API_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ API_DATAREADY_OUT : out std_logic;\r
+ API_READ_IN : in std_logic;\r
+ API_SHORT_TRANSFER_OUT : out std_logic;\r
+ API_DTYPE_OUT : out std_logic_vector (3 downto 0);\r
+ API_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);\r
+ API_SEND_OUT : out std_logic;\r
+ -- Receiver port\r
+ API_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ API_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ API_TYP_IN : in std_logic_vector (2 downto 0);\r
+ API_DATAREADY_IN : in std_logic;\r
+ API_READ_OUT : out std_logic;\r
+ -- APL Control port\r
+ API_RUN_IN : in std_logic;\r
+ API_SEQNR_IN : in std_logic_vector (7 downto 0);\r
+\r
+ --Port to write Unique ID (-> 1-wire)\r
+ IDRAM_DATA_IN : in std_logic_vector(15 downto 0);\r
+ IDRAM_DATA_OUT : out std_logic_vector(15 downto 0);\r
+ IDRAM_ADDR_IN : in std_logic_vector(2 downto 0);\r
+ IDRAM_WR_IN : in std_logic;\r
+\r
+ --Informations\r
+ MY_ADDRESS_OUT : out std_logic_vector(15 downto 0);\r
+ TRIGGER_MONITOR : in std_logic;\r
+ GLOBAL_TIME : out std_logic_vector(31 downto 0); --global time, microseconds\r
+ LOCAL_TIME : out std_logic_vector(7 downto 0); --local time running with chip frequency\r
+ TIME_SINCE_LAST_TRG : out std_logic_vector(31 downto 0); --local time, resetted with each trigger\r
+ TIMER_US_TICK : out std_logic; --1 tick every microsecond\r
+ TIMER_MS_TICK : out std_logic; --1 tick every 1024 microseconds\r
+\r
+ --Common Register in / out\r
+ COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REG_WIDTH-1 downto 0);\r
+ COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*c_REGIO_REG_WIDTH-1 downto 0);\r
+ --Custom Register in / out\r
+ REGISTERS_IN : in std_logic_vector(c_REGIO_REG_WIDTH*2**(NUM_STAT_REGS)-1 downto 0);\r
+ REGISTERS_OUT : out std_logic_vector(c_REGIO_REG_WIDTH*2**(NUM_CTRL_REGS)-1 downto 0);\r
+ COMMON_STAT_REG_STROBE : out std_logic_vector((std_COMSTATREG)-1 downto 0);\r
+ COMMON_CTRL_REG_STROBE : out std_logic_vector((std_COMCTRLREG)-1 downto 0);\r
+ STAT_REG_STROBE : out std_logic_vector(2**(NUM_STAT_REGS)-1 downto 0);\r
+ CTRL_REG_STROBE : out std_logic_vector(2**(NUM_CTRL_REGS)-1 downto 0);\r
+ --Internal Data Port\r
+ DAT_ADDR_OUT : out std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0);\r
+ DAT_READ_ENABLE_OUT : out std_logic;\r
+ DAT_WRITE_ENABLE_OUT: out std_logic;\r
+ DAT_DATA_OUT : out std_logic_vector(c_REGIO_REG_WIDTH-1 downto 0);\r
+ DAT_DATA_IN : in std_logic_vector(c_REGIO_REG_WIDTH-1 downto 0);\r
+ DAT_DATAREADY_IN : in std_logic;\r
+ DAT_NO_MORE_DATA_IN : in std_logic;\r
+ DAT_WRITE_ACK_IN : in std_logic;\r
+ DAT_UNKNOWN_ADDR_IN : in std_logic;\r
+ DAT_TIMEOUT_OUT : out std_logic;\r
+\r
+ --Additional write access to ctrl registers\r
+ STAT : out std_logic_vector(31 downto 0);\r
+ STAT_ADDR_DEBUG : out std_logic_vector(15 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net16_regio_bus_handler is\r
+ generic(\r
+ PORT_NUMBER : integer range 1 to c_BUS_HANDLER_MAX_PORTS := 3;\r
+ PORT_ADDRESSES : c_BUS_HANDLER_ADDR_t := (others => (others => '0'));\r
+ PORT_ADDR_MASK : c_BUS_HANDLER_WIDTH_t := (others => 0)\r
+ );\r
+ port(\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ DAT_ADDR_IN : in std_logic_vector(15 downto 0); -- address bus\r
+ DAT_DATA_IN : in std_logic_vector(31 downto 0); -- data from TRB endpoint\r
+ DAT_DATA_OUT : out std_logic_vector(31 downto 0); -- data to TRB endpoint\r
+ DAT_READ_ENABLE_IN : in std_logic; -- read pulse\r
+ DAT_WRITE_ENABLE_IN : in std_logic; -- write pulse\r
+ DAT_TIMEOUT_IN : in std_logic; -- access timed out\r
+ DAT_DATAREADY_OUT : out std_logic; -- your data, master, as requested\r
+ DAT_WRITE_ACK_OUT : out std_logic; -- data accepted\r
+ DAT_NO_MORE_DATA_OUT : out std_logic; -- don't disturb me now\r
+ DAT_UNKNOWN_ADDR_OUT : out std_logic; -- noone here to answer your request\r
+\r
+ BUS_ADDR_OUT : out std_logic_vector(PORT_NUMBER*16-1 downto 0);\r
+ BUS_DATA_OUT : out std_logic_vector(PORT_NUMBER*32-1 downto 0);\r
+ BUS_READ_ENABLE_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0);\r
+ BUS_WRITE_ENABLE_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0);\r
+ BUS_TIMEOUT_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0);\r
+\r
+ BUS_DATA_IN : in std_logic_vector(32*PORT_NUMBER-1 downto 0);\r
+ BUS_DATAREADY_IN : in std_logic_vector(PORT_NUMBER-1 downto 0);\r
+ BUS_WRITE_ACK_IN : in std_logic_vector(PORT_NUMBER-1 downto 0);\r
+ BUS_NO_MORE_DATA_IN : in std_logic_vector(PORT_NUMBER-1 downto 0);\r
+ BUS_UNKNOWN_ADDR_IN : in std_logic_vector(PORT_NUMBER-1 downto 0);\r
+\r
+ STAT_DEBUG : out std_logic_vector(31 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+ component trb_net_reset_handler is\r
+ generic(\r
+ RESET_DELAY : std_logic_vector(15 downto 0) := x"1fff"\r
+ );\r
+ port(\r
+ CLEAR_IN : in std_logic; -- reset input (high active, async)\r
+ CLEAR_N_IN : in std_logic; -- reset input (low active, async)\r
+ CLK_IN : in std_logic; -- raw master clock, NOT from PLL/DLL!\r
+ SYSCLK_IN : in std_logic; -- PLL/DLL remastered clock\r
+ PLL_LOCKED_IN : in std_logic; -- master PLL lock signal (async)\r
+ RESET_IN : in std_logic; -- general reset signal (SYSCLK)\r
+ TRB_RESET_IN : in std_logic; -- TRBnet reset signal (SYSCLK)\r
+ CLEAR_OUT : out std_logic; -- async reset out, USE WITH CARE!\r
+ RESET_OUT : out std_logic; -- synchronous reset out (SYSCLK)\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+ component rom_16x8 is\r
+ generic(\r
+ INIT0 : std_logic_vector(15 downto 0) := x"0000";\r
+ INIT1 : std_logic_vector(15 downto 0) := x"0000";\r
+ INIT2 : std_logic_vector(15 downto 0) := x"0000";\r
+ INIT3 : std_logic_vector(15 downto 0) := x"0000";\r
+ INIT4 : std_logic_vector(15 downto 0) := x"0000";\r
+ INIT5 : std_logic_vector(15 downto 0) := x"0000";\r
+ INIT6 : std_logic_vector(15 downto 0) := x"0000";\r
+ INIT7 : std_logic_vector(15 downto 0) := x"0000"\r
+ );\r
+ port(\r
+ CLK : in std_logic;\r
+ a : in std_logic_vector(2 downto 0);\r
+ dout : out std_logic_vector(15 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+ component trb_net16_rx_control is\r
+ port(\r
+ RESET_IN : in std_logic;\r
+ QUAD_RST_IN : in std_logic;\r
+ -- raw data from SerDes receive path\r
+ CLK_IN : in std_logic;\r
+ RX_DATA_IN : in std_logic_vector(7 downto 0);\r
+ RX_K_IN : in std_logic;\r
+ RX_CV_IN : in std_logic;\r
+ RX_DISP_ERR_IN : in std_logic;\r
+ RX_ALLOW_IN : in std_logic;\r
+ -- media interface\r
+ SYSCLK_IN : in std_logic; -- 100MHz master clock\r
+ MED_DATA_OUT : out std_logic_vector(15 downto 0);\r
+ MED_DATAREADY_OUT : out std_logic;\r
+ MED_READ_IN : in std_logic;\r
+ MED_PACKET_NUM_OUT : out std_logic_vector(2 downto 0);\r
+ -- request retransmission in case of error while receiving\r
+ REQUEST_RETRANSMIT_OUT : out std_logic; -- one pulse\r
+ REQUEST_POSITION_OUT : out std_logic_vector( 7 downto 0);\r
+ -- command decoding\r
+ START_RETRANSMIT_OUT : out std_logic;\r
+ START_POSITION_OUT : out std_logic_vector( 7 downto 0);\r
+ -- reset handling\r
+ SEND_RESET_WORDS_OUT : out std_logic;\r
+ MAKE_TRBNET_RESET_OUT : out std_logic;\r
+ -- Status signals\r
+ PACKET_TIMEOUT_OUT : out std_logic;\r
+ ENABLE_CORRECTION_IN : in std_logic;\r
+ -- Debugging\r
+ DEBUG_OUT : out std_logic_vector(31 downto 0);\r
+ STAT_REG_OUT : out std_logic_vector(95 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+ component trb_net16_sbuf is\r
+ generic (\r
+ VERSION : integer := 0\r
+ );\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ -- port to combinatorial logic\r
+ COMB_DATAREADY_IN : in STD_LOGIC; --comb logic provides data word\r
+ COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle\r
+ COMB_READ_IN : in STD_LOGIC; --comb logic IS reading\r
+ COMB_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);\r
+ COMB_PACKET_NUM_IN: in STD_LOGIC_VECTOR(c_NUM_WIDTH-1 downto 0);\r
+ -- Port to synchronous output.\r
+ SYN_DATAREADY_OUT : out STD_LOGIC;\r
+ SYN_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);\r
+ SYN_PACKET_NUM_OUT: out STD_LOGIC_VECTOR(c_NUM_WIDTH-1 downto 0);\r
+ SYN_READ_IN : in STD_LOGIC;\r
+ -- Status and control port\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0);\r
+ STAT_BUFFER : out STD_LOGIC\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net_sbuf is\r
+ generic (\r
+ DATA_WIDTH : integer := 18;\r
+ VERSION: integer := std_SBUF_VERSION);\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ -- port to combinatorial logic\r
+ COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word\r
+ COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle\r
+ COMB_READ_IN: in STD_LOGIC; --comb logic IS reading\r
+ COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);\r
+ SYN_DATAREADY_OUT: out STD_LOGIC;\r
+ SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);\r
+ SYN_READ_IN: in STD_LOGIC;\r
+ STAT_BUFFER: out STD_LOGIC\r
+ );\r
+ end component;\r
+\r
+\r
+ component trb_net_sbuf2 is\r
+ generic (\r
+ DATA_WIDTH : integer := 18\r
+ );\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ -- port to combinatorial logic\r
+ COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word\r
+ COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle\r
+ COMB_READ_IN: in STD_LOGIC; --comb logic IS reading\r
+ COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);\r
+ SYN_DATAREADY_OUT: out STD_LOGIC;\r
+ SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);\r
+ SYN_READ_IN: in STD_LOGIC;\r
+ STAT_BUFFER: out STD_LOGIC\r
+ );\r
+ end component;\r
+\r
+ component trb_net_sbuf3 is\r
+ generic (\r
+ DATA_WIDTH : integer := 18\r
+ );\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ -- port to combinatorial logic\r
+ COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word\r
+ COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle\r
+ COMB_READ_IN: in STD_LOGIC; --comb logic IS reading\r
+ COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);\r
+ SYN_DATAREADY_OUT: out STD_LOGIC;\r
+ SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);\r
+ SYN_READ_IN: in STD_LOGIC;\r
+ STAT_BUFFER: out STD_LOGIC\r
+ );\r
+ end component;\r
+\r
+ component trb_net_sbuf4 is\r
+ generic (\r
+ DATA_WIDTH : integer := 18\r
+ );\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ -- port to combinatorial logic\r
+ COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word\r
+ COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle\r
+ COMB_READ_IN: in STD_LOGIC; --comb logic IS reading\r
+ COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);\r
+ SYN_DATAREADY_OUT: out STD_LOGIC;\r
+ SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);\r
+ SYN_READ_IN: in STD_LOGIC;\r
+ STAT_BUFFER: out STD_LOGIC\r
+ );\r
+ end component;\r
+\r
+ component trb_net_sbuf5 is\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ -- input\r
+ COMB_DATAREADY_IN : in std_logic;\r
+ COMB_next_READ_OUT : out std_logic;\r
+ COMB_DATA_IN : in std_logic_vector(18 downto 0);\r
+ -- output\r
+ SYN_DATAREADY_OUT : out std_logic;\r
+ SYN_DATA_OUT : out std_logic_vector(18 downto 0); -- Data word\r
+ SYN_READ_IN : in std_logic;\r
+ -- Status and control port\r
+ DEBUG : out std_logic_vector(7 downto 0);\r
+ DEBUG_BSM : out std_logic_vector(3 downto 0);\r
+ DEBUG_WCNT : out std_logic_vector(4 downto 0);\r
+ STAT_BUFFER : out std_logic\r
+ );\r
+ end component;\r
+\r
+ component trb_net_sbuf6 is\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ -- input\r
+ COMB_DATAREADY_IN : in std_logic;\r
+ COMB_next_READ_OUT : out std_logic;\r
+ COMB_DATA_IN : in std_logic_vector(18 downto 0);\r
+ -- output\r
+ SYN_DATAREADY_OUT : out std_logic;\r
+ SYN_DATA_OUT : out std_logic_vector(18 downto 0);\r
+ SYN_READ_IN : in std_logic;\r
+ -- Status and control port\r
+ DEBUG : out std_logic_vector(7 downto 0);\r
+ DEBUG_BSM : out std_logic_vector(3 downto 0);\r
+ DEBUG_WCNT : out std_logic_vector(4 downto 0);\r
+ STAT_BUFFER : out std_logic\r
+ );\r
+ end component;\r
+\r
+ component slv_mac_memory is\r
+ port(\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ BUSY_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_ADDR_IN : in std_logic_vector(7 downto 0);\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_BUSY_OUT : out std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- I/O to the backend\r
+ MEM_CLK_IN : in std_logic;\r
+ MEM_ADDR_IN : in std_logic_vector(7 downto 0);\r
+ MEM_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+ component slv_register is\r
+ generic(\r
+ RESET_VALUE : std_logic_vector(31 downto 0) := x"0000_0000"\r
+ );\r
+ port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ BUSY_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_BUSY_OUT : out std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- I/O to the backend\r
+ REG_DATA_IN : in std_logic_vector(31 downto 0);\r
+ REG_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+ component spi_databus_memory is\r
+ port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ BUS_ADDR_IN : in std_logic_vector(5 downto 0);\r
+ BUS_READ_IN : in std_logic;\r
+ BUS_WRITE_IN : in std_logic;\r
+ BUS_ACK_OUT : out std_logic;\r
+ BUS_DATA_IN : in std_logic_vector(31 downto 0);\r
+ BUS_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- state machine connections\r
+ BRAM_ADDR_IN : in std_logic_vector(7 downto 0);\r
+ BRAM_WR_D_OUT : out std_logic_vector(7 downto 0);\r
+ BRAM_RD_D_IN : in std_logic_vector(7 downto 0);\r
+ BRAM_WE_IN : in std_logic;\r
+ -- Status lines\r
+ STAT : out std_logic_vector(63 downto 0) -- DEBUG\r
+ );\r
+ end component;\r
+\r
+\r
+ component spi_dpram_32_to_8 is\r
+ port (\r
+ DataInA: in std_logic_vector(31 downto 0);\r
+ DataInB: in std_logic_vector(7 downto 0);\r
+ AddressA: in std_logic_vector(5 downto 0);\r
+ AddressB: in std_logic_vector(7 downto 0);\r
+ ClockA: in std_logic;\r
+ ClockB: in std_logic;\r
+ ClockEnA: in std_logic;\r
+ ClockEnB: in std_logic;\r
+ WrA: in std_logic;\r
+ WrB: in std_logic;\r
+ ResetA: in std_logic;\r
+ ResetB: in std_logic;\r
+ QA: out std_logic_vector(31 downto 0);\r
+ QB: out std_logic_vector(7 downto 0));\r
+ end component;\r
+\r
+\r
+ component spi_slim is\r
+ port(\r
+ SYSCLK : in std_logic; -- 100MHz sysclock\r
+ RESET : in std_logic; -- synchronous reset\r
+ -- Command interface\r
+ START_IN : in std_logic; -- one start pulse\r
+ BUSY_OUT : out std_logic; -- SPI transactions are ongoing\r
+ CMD_IN : in std_logic_vector(7 downto 0); -- SPI command byte\r
+ ADL_IN : in std_logic_vector(7 downto 0); -- low address byte\r
+ ADM_IN : in std_logic_vector(7 downto 0); -- mid address byte\r
+ ADH_IN : in std_logic_vector(7 downto 0); -- high address byte\r
+ MAX_IN : in std_logic_vector(7 downto 0); -- number of bytes to write / read (PP/RDCMD)\r
+ TXDATA_IN : in std_logic_vector(7 downto 0); -- byte to be transmitted next\r
+ TX_RD_OUT : out std_logic;\r
+ RXDATA_OUT : out std_logic_vector(7 downto 0); -- current received byte\r
+ RX_WR_OUT : out std_logic;\r
+ TX_RX_A_OUT : out std_logic_vector(7 downto 0); -- memory block counter for PP/RDCMD\r
+ -- SPI interface\r
+ SPI_SCK_OUT : out std_logic;\r
+ SPI_CS_OUT : out std_logic;\r
+ SPI_SDI_IN : in std_logic;\r
+ SPI_SDO_OUT : out std_logic;\r
+ -- DEBUG\r
+ CLK_EN_OUT : out std_logic;\r
+ BSM_OUT : out std_logic_vector(7 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(31 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+ component spi_master is\r
+ port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ BUS_READ_IN : in std_logic;\r
+ BUS_WRITE_IN : in std_logic;\r
+ BUS_BUSY_OUT : out std_logic;\r
+ BUS_ACK_OUT : out std_logic;\r
+ BUS_ADDR_IN : in std_logic_vector(0 downto 0);\r
+ BUS_DATA_IN : in std_logic_vector(31 downto 0);\r
+ BUS_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- SPI connections\r
+ SPI_CS_OUT : out std_logic;\r
+ SPI_SDI_IN : in std_logic;\r
+ SPI_SDO_OUT : out std_logic;\r
+ SPI_SCK_OUT : out std_logic;\r
+ -- BRAM for read/write data\r
+ BRAM_A_OUT : out std_logic_vector(7 downto 0);\r
+ BRAM_WR_D_IN : in std_logic_vector(7 downto 0);\r
+ BRAM_RD_D_OUT : out std_logic_vector(7 downto 0);\r
+ BRAM_WE_OUT : out std_logic;\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+\r
+ component signal_sync is\r
+ generic(\r
+ WIDTH : integer := 1; --\r
+ DEPTH : integer := 3\r
+ );\r
+ port(\r
+ RESET : in std_logic; --Reset is neceessary to avoid optimization to shift register\r
+ CLK0 : in std_logic; --clock for first FF\r
+ CLK1 : in std_logic; --Clock for other FF\r
+ D_IN : in std_logic_vector(WIDTH-1 downto 0); --Data input\r
+ D_OUT : out std_logic_vector(WIDTH-1 downto 0) --Data output\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net16_term is\r
+ generic (\r
+ USE_APL_PORT : integer range 0 to 1 := c_YES;\r
+ --even when 0, ERROR_PACKET_IN is used for automatic replys\r
+ SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE\r
+ --if secure_mode is not used, apl must provide error pattern and dtype until\r
+ --next trigger comes in. In secure mode these need to be available while relase_trg is high\r
+ );\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+\r
+ INT_DATAREADY_OUT : out std_logic;\r
+ INT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word\r
+ INT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ INT_READ_IN : in std_logic;\r
+\r
+ INT_DATAREADY_IN : in std_logic;\r
+ INT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word\r
+ INT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ INT_READ_OUT : out std_logic;\r
+ APL_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net16_term_buf is\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ MED_INIT_DATAREADY_OUT : out std_logic;\r
+ MED_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word\r
+ MED_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_INIT_READ_IN : in std_logic;\r
+ MED_REPLY_DATAREADY_OUT : out std_logic;\r
+ MED_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word\r
+ MED_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_REPLY_READ_IN : in std_logic;\r
+ MED_DATAREADY_IN : in std_logic;\r
+ MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word\r
+ MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_READ_OUT : out std_logic\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net16_term_ibuf is\r
+ generic(\r
+ SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE;\r
+ SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION\r
+ );\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ -- Media direction port\r
+ MED_DATAREADY_IN: in std_logic;\r
+ MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN :in std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ MED_READ_OUT: out std_logic;\r
+ MED_ERROR_IN: in std_logic_vector (2 downto 0);\r
+ -- Internal direction port\r
+ INT_DATAREADY_OUT: out std_logic;\r
+ INT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ INT_PACKET_NUM_OUT:out std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ INT_READ_IN: in std_logic;\r
+ INT_ERROR_OUT: out std_logic_vector (2 downto 0);\r
+ -- Status and control port\r
+ STAT_BUFFER: out std_logic_vector (31 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+ component trb_net16_trigger is\r
+ generic (\r
+ USE_TRG_PORT : integer range 0 to 1 := c_YES;\r
+ --even when NO, ERROR_PACKET_IN is used for automatic replys\r
+ SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE\r
+ --if secure_mode is not used, apl must provide error pattern and dtype until\r
+ --next trigger comes in. In secure mode these need to be available while relase_trg is high only\r
+ );\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+\r
+ INT_DATAREADY_OUT: out std_logic;\r
+ INT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ INT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ INT_READ_IN: in std_logic;\r
+\r
+ INT_DATAREADY_IN: in std_logic;\r
+ INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ INT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ INT_READ_OUT: out std_logic;\r
+\r
+ -- Trigger information output\r
+ TRG_TYPE_OUT : out std_logic_vector (3 downto 0);\r
+ TRG_NUMBER_OUT : out std_logic_vector (15 downto 0);\r
+ TRG_CODE_OUT : out std_logic_vector (7 downto 0);\r
+ TRG_INFORMATION_OUT : out std_logic_vector (23 downto 0);\r
+ TRG_RECEIVED_OUT : out std_logic;\r
+ TRG_RELEASE_IN : in std_logic;\r
+ TRG_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+ component trb_net16_tx_control is\r
+ port(\r
+ TXCLK_IN : in std_logic;\r
+ RXCLK_IN : in std_logic;\r
+ SYSCLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+\r
+ TX_DATA_IN : in std_logic_vector(15 downto 0);\r
+ TX_PACKET_NUMBER_IN : in std_logic_vector(2 downto 0);\r
+ TX_WRITE_IN : in std_logic;\r
+ TX_READ_OUT : out std_logic;\r
+\r
+ TX_DATA_OUT : out std_logic_vector( 7 downto 0);\r
+ TX_K_OUT : out std_logic;\r
+\r
+ REQUEST_RETRANSMIT_IN : in std_logic;\r
+ REQUEST_POSITION_IN : in std_logic_vector( 7 downto 0);\r
+\r
+ START_RETRANSMIT_IN : in std_logic;\r
+ START_POSITION_IN : in std_logic_vector( 7 downto 0);\r
+\r
+ SEND_LINK_RESET_IN : in std_logic;\r
+ TX_ALLOW_IN : in std_logic;\r
+\r
+ DEBUG_OUT : out std_logic_vector(31 downto 0);\r
+ STAT_REG_OUT : out std_logic_vector(31 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+ component wide_adder_17x16 is\r
+ generic(\r
+ SIZE : integer := 16;\r
+ WORDS: integer := 17 --fixed\r
+ );\r
+ port(\r
+ CLK : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ RESET : in std_logic;\r
+ INPUT_IN : in std_logic_vector(SIZE*WORDS-1 downto 0);\r
+ START_IN : in std_logic;\r
+ VAL_ENABLE_IN: in std_logic_vector(WORDS-1 downto 0);\r
+ RESULT_OUT : out std_logic_vector(SIZE-1 downto 0);\r
+ OVERFLOW_OUT : out std_logic;\r
+ READY_OUT : out std_logic\r
+ );\r
+ end component;\r
+\r
+\r
+ component trb_net_bridge_etrax_apl is\r
+ port(\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_DATAREADY_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_READ_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_SHORT_TRANSFER_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_DTYPE_OUT : out std_logic_vector (4*2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_ERROR_PATTERN_OUT : out std_logic_vector (32*2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_SEND_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_TARGET_ADDRESS_OUT : out std_logic_vector (16*2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH*2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_TYP_IN : in std_logic_vector (3*2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_DATAREADY_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_READ_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_RUN_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_SEQNR_IN : in std_logic_vector (8*2**(c_MUX_WIDTH)-1 downto 0);\r
+ CPU_READ : in STD_LOGIC;\r
+ CPU_WRITE : in STD_LOGIC;\r
+ CPU_DATA_OUT : out STD_LOGIC_VECTOR (31 downto 0);\r
+ CPU_DATA_IN : in STD_LOGIC_VECTOR (31 downto 0);\r
+ CPU_DATAREADY_OUT : out std_logic;\r
+ CPU_ADDRESS : in STD_LOGIC_VECTOR (15 downto 0);\r
+ STAT : out std_logic_vector (31 downto 0);\r
+ CTRL : in std_logic_vector (31 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
end package;
\ No newline at end of file
jspc29 / trbnet.git / commitdiff