--- /dev/null
+library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+library work;
+ use work.trb_net_std.all;
+
+entity stretched_OR_trigger is
+generic(
+ INPUT_WIDTH : integer := 32
+);
+port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+
+ INPUT : in std_logic_vector(INPUT_WIDTH-1 downto 0);
+ OUTPUT : out std_logic;
+
+ BUS_RX : in CTRLBUS_RX;
+ BUS_TX : out CTRLBUS_TX
+);
+end entity;
+
+architecture behaviour of stretched_OR_trigger is
+ signal input_or : std_logic;
+ signal input_inv : std_logic_vector(INPUT_WIDTH-1 downto 0);
+ signal invert : std_logic_vector(31 downto 0) := x"00000000";
+ signal enable : std_logic_vector(31 downto 0) := x"00000000";
+ signal or_long : std_logic := '0';
+ signal stretch : std_logic_vector(3 downto 0) := x"0";
+ signal or_long_r : std_logic;
+ signal cnt : unsigned (4 downto 0) := "00000";
+
+begin
+ input_inv <= ((INPUT xor invert(INPUT_WIDTH-1 downto 0)) and enable(INPUT_WIDTH-1 downto 0));
+ input_or <= or_all( input_inv);
+
+ or_long <= (or_long or input_or) and (not cnt(4));
+
+ OUTPUT <= input_or when stretch = x"0" else
+ or_long;
+
+ or_long_r <= or_long when rising_edge(CLK);
+
+ THE_TRIGGER_CONTROL : process
+ begin
+ wait until rising_edge(CLK);
+
+ if RESET = '1' then
+ cnt <= "00000";
+ else
+ if or_long_r = '1' and cnt(4) = '0' then -- trigger is high
+ cnt <= cnt - 1;
+ else
+ cnt <= ('0' & unsigned(stretch)) - 1;
+ end if;
+ -- deactivate high signal of trigger after configured delay
+ -- 1 stretch bit = 10ns
+ -- stretch from 10 to 150ns
+ -- Stretch begins with first clock edge, but signal is async high.
+ -- So stretch of 10ns could be between 10.00ns to 19.99ns long, etc.
+ end if;
+ end process;
+
+ proc_reg : process
+ begin
+ wait until rising_edge(CLK);
+ BUS_TX.ack <= '0';
+ BUS_TX.nack <= '0';
+ BUS_TX.unknown <= '0';
+
+ if BUS_RX.write = '1' then
+ BUS_TX.ack <= '1';
+ case BUS_RX.addr(1 downto 0) is
+ when "00" =>
+ stretch <= BUS_RX.data(3 downto 0);
+ when "01" =>
+ invert <= BUS_RX.data;
+ when "10" =>
+ enable <= BUS_RX.data;
+
+ when others =>
+ BUS_TX.ack <= '0';
+ BUS_TX.unknown <= '1';
+ end case;
+ elsif BUS_RX.read = '1' then
+ BUS_TX.ack <= '1';
+ case BUS_RX.addr(1 downto 0) is
+ when "00" => BUS_TX.data(3 downto 0) <= stretch;
+
+ when "01" => BUS_TX.data <= invert;
+
+ when "10" => BUS_TX.data <= enable;
+
+ when others => BUS_TX.ack <= '0';
+ BUS_TX.unknown <= '1';
+ end case;
+ end if;
+ end process;
+
+end architecture;
+
entity dirich5s is
port(
CLOCK_CORE : in std_logic; --Main Oscillator
- CLOCK_IN : in std_logic; --external Clock
TRIG_IN : in std_logic; --Reference Time
CLOCK_CAL : in std_logic; --on-board calibration oscillator
INPUT : in std_logic_vector(32 downto 1);
-- PWM : out std_logic_vector(32 downto 1);
+ ASYNC_OR : out std_logic; -- asynch OR of all 32 inputs
+
--Additional IO
SIG : inout std_logic_vector(5 downto 1);
--1:master ready, 2: slave ready, 3-4 trigger, 5 reset
signal readout_rx : READOUT_RX;
signal readout_tx : readout_tx_array_t(0 to 0);
- signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in : CTRLBUS_TX;
- signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out : CTRLBUS_RX;
+ signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in , busOrTrigger_tx : CTRLBUS_TX;
+ signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out, busOrTrigger_rx : CTRLBUS_RX;
signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
generic map(
- PORT_NUMBER => 5,
- PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"a000", 4 => x"c000", others => x"0000"),
- PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 8, 4 => 12, others => 0),
+ PORT_NUMBER => 6,
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"a000", 4 => x"c000", 5 => x"e000", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 8, 4 => 12, 5 => 2, others => 0),
PORT_MASK_ENABLE => 1
)
port map(
BUS_RX(2) => bustc_rx, --Clock switch
BUS_RX(3) => busthresh_rx,
BUS_RX(4) => bustdc_rx,
+ BUS_RX(5) => busOrTrigger_rx,
BUS_TX(0) => bustools_tx,
BUS_TX(1) => bussci_tx,
BUS_TX(2) => bustc_tx,
BUS_TX(3) => busthresh_tx,
BUS_TX(4) => bustdc_tx,
+ BUS_TX(5) => busOrTrigger_tx,
STAT_DEBUG => open
);
---------------------------------------------------------------------------
-- PWM / Thresh
---------------------------------------------------------------------------
-gen_pwm: if DIRICH_VERSION = 1 generate
- THE_PWM_GEN : entity work.pwm_generator
- port map(
- CLK => clk_sys,
- CLK_FAST => CLOCK_IN,
- BUS_RX => busthresh_rx,
- BUS_TX => busthresh_tx,
- TEMP_IN => timer.temperature,
- PWM => pwm_i
- );
-
--- PWM <= pwm_i;
-end generate;
-gen_DAC : if DIRICH_VERSION = 2 generate
MOSI_OUT <= spi_mosi(1 downto 0);
SCLK_OUT <= spi_clk(1 downto 0);
CS_OUT <= spi_cs(1 downto 0);
spi_miso(1 downto 0) <= MISO_IN;
-end generate;
+
+
+---------------------------------------------------------------------------
+-- ASYNCHRONOUS OR OF ALL INPUTS
+---------------------------------------------------------------------------
+
+--ASYNC_OR <= or_all(INPUT(32 downto 1));
+
+THE_OR_TRIGGER: entity work.stretched_OR_trigger
+port map (
+ CLK => clk_sys,
+ RESET => reset_i,
+
+ INPUT => INPUT(32 downto 1),
+ OUTPUT => ASYNC_OR,
+
+ BUS_RX => busOrTrigger_rx,
+ BUS_TX => busOrTrigger_tx
+);
+
---------------------------------------------------------------------------
-- I/O
jspc29 / dirich.git / commitdiff