\item[0x9008: \filename{Send\_Token\_To\_MB} status register] The status register of the entity that sends and receives the token to the MBO. Bits 3..0 show the status of the state machine.
\end{description}
+
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsection{MDC AddOn Connections}
+\subsection{Board Positions}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+
+\subsubsection{MDC OEP Positions}
+Figure \ref{fig:mdcoeppositions} shows the positions of each OEP on the chambers.
+
+\begin{figure}[ht]
+ \centering
+ \includegraphics[width=\textwidth]{mdcplanesoep.png}
+ \caption[Position of OEPs]{Position of OEP numbers (and old MBO numbering scheme) for each of the four chamber types.}
+ \label{fig:mdcoeppositions}
+\end{figure}
+
+\subsubsection{MDC AddOn Connections}
\label{mdcaddonconnections}
-Since the length of optical cables is far from optimal, the ports to which they are connected are also quite sub-optimal. Table \ref{MDCPortMap} shows what is connected where. This table is meant for DAQ operators, thus numbering starts with 0.
+Since the length of optical cables is far from optimal, the ports to which they are connected are also quite sub-optimal. Table \ref{MDCPortMap} shows what is connected where. This table is meant for DAQ operators and to easily translate network addresses to positions, thus numbering starts with 0.
+
+To get the real network address of the hub FPGAs, the FPGA number (1--4) has to be added to the address in the left column. Boards 1000 -- 1050 are located on the platform next to RICH, boards 1010 -- 1030 are mounted in the right corner of the mainframe, boards 1000, 1040 and 1050 are mounted in the left corner of the mainframe.
+
\begin{sidewaystable}
\begin{center}
1150 & \multicolumn{4}{c|}{P2 S5 0-F} & \multicolumn{4}{c|}{P3 S5 0-F} \\
\hline
\end{tabular}
-\caption{Connected OEPs on each MDC AddOn FPGA. Plane (P) and Sector (S) numbers are counted starting at 0. Port numbers refer to the bit numbers inside the Hub status and control registers. Port 0 is always the uplink. To get the real network address of the hub FPGAs, the FPGA number (1--4) has to be added to the address in the left column.}
+\caption{Connected OEPs on each MDC AddOn FPGA. Plane (P) and Sector (S) numbers are counted starting at 0. Port numbers refer to the bit numbers inside the Hub status and control registers. Port 0 is always the uplink.}
\label{MDCPortMap}
\end{center}
\end{sidewaystable}
2**6 addresses, i.e. from 0x8000 to 0x803F.
The behaviour on the data busses is identical to the original RegIO interface. Connecting to the
-different address spaces can be done in a convenient form as shown in the following piece of code:
+different address spaces can be done in a convenient form.
-\lstset { caption ={Excerpt from the regio\_bus\_handler used in MDC OEP.}}
-\begin{lstlisting}
-THE_REGIO_BUS_HANDLER : trb_net16_regio_bus_handler
-generic map(
- PORT_NUMBER => 6,
- PORT_ADDRESSES =>
- (0 => x"A000", 1 => x"8000", others => x"0000"),
- PORT_ADDR_MASK =>
- (0 => 8, 1 => 6, others => 0)
- )
-port map(
- clk => clk_100,
- reset => reset_internal,
---I/O to RegIO
- dat_addr_in => regio_addr_out,
- dat_data_in => regio_data_out,
- dat_data_out => regio_data_in,
- dat_read_enable_in => regio_read_enable_out,
- dat_write_enable_in => regio_write_enable_out,
- dat_timeout_in => regio_timeout_out,
- dat_dataready_out => regio_dataready_in,
- dat_write_ack_out => regio_write_ack_in,
- dat_no_more_data_out => regio_no_more_data_in,
- dat_unknown_addr_out => regio_unknown_addr_in,
---Bus Handler (Threshold memory)
- bus_read_enable_out(0) => thresh_mem_read,
- bus_write_enable_out(0) => thresh_mem_write,
- bus_data_out(0*32+15 downto 0*32) => thresh_mem_data,
- bus_data_out(0*32+31 downto 0*32+16)=> open,
- bus_addr_out(0*16+8 downto 0*16) => thresh_mem_addr,
- bus_addr_out(0*16+15 downto 0*16+9) => open,
- bus_timeout_out(0) => open,
- bus_data_in(0*32+15 downto 0*32) => thresh_mem_data_out,
- bus_data_in(0*32+31 downto 0*32+16) => x"0000",
- bus_dataready_in(0) => last_reg_regio_read,
- bus_write_ack_in(0) => reg_regio_write,
- bus_no_more_data_in(0) => '0',
- bus_unknown_addr_in(0) => '0',
---Bus Handler (ADC)
- bus_read_enable_out(1) => adc_read,
- bus_write_enable_out(1) => adc_write,
- bus_data_out(1*32+31 downto 1*32) => adc_data_in,
- bus_addr_out(1*16+5 downto 1*16) => adc_addr,
- bus_addr_out(1*16+15 downto 1*16+6) => open,
- bus_timeout_out(1) => adc_timeout,
- bus_data_in(1*32+31 downto 1*32) => adc_data_out,
- bus_dataready_in(1) => adc_dataready,
- bus_write_ack_in(1) => adc_write_ack,
- bus_no_more_data_in(1) => adc_no_more_data,
- bus_unknown_addr_in(1) => adc_unknown_addr,
- [...]
-\end{lstlisting}
\subsection{Register Map}
40 & information ROM 0 & ROM0 & Compile Time (set by generic) (r)\\
41 & information ROM 1 & ROM1 & Design Version (set by generic) (r) \\
42 & information ROM 2 & ROM2 & Hardware Information (set by generic) (r)\\
-50 & global time & TIME & Global Time (r/w)\\
+50 & global time & TME & Global Time (r/w)\\
51 & time since trigger & TSTR & Time since last timing trigger (r)\\
-80 -- BF & user status registers & --- & User status registers \\
-C0 -- FF & user control registers & --- & User control registers \\
+80 -- BF & user status registers & SRn & User status registers \\
+C0 -- FF & user control registers & CRn & User control registers \\
0100 -- 6FFF & reserved & --- & Reserved addresses on internal data port (e.g. for monitoring and other features)\\
7000 -- 7FFF & endpoint monitoring & --- & Monitoring Registers for Endpoint\\
8000 -- FFFF & user defined & --- & User defined address space on the internal data bus \\
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