DEBUG_OUT(0) <= fr_rd_en;
DEBUG_OUT(1) <= fr_frame_valid;
DEBUG_OUT(2) <= fr_get_frame;
- DEBUG_OUT(3) <= monitor_dropped(0);
- DEBUG_OUT(4) <= monitor_dropped(1);
MONITOR_RX_FRAMES_OUT <= monitor_rx_frames;
MONITOR_RX_BYTES_OUT <= monitor_rx_bytes;
--
MAKE_RESET_OUT : out std_logic;
--
- STATUS_OUT : out std_logic_vector(15 downto 0);
+ STATUS_OUT : out std_logic_vector(7 downto 0);
DEBUG_OUT : out std_logic_vector(31 downto 0)
);
end entity gbe_wrapper_fifo;
-- debug(127 downto 64) are local
-- debug(63 downto 0) are media interface
- --DEBUG_OUT <= debug;
+ DEBUG_OUT <= monitor_gen_dbg(95 downto 64);
mac_0 <= MC_UNIQUE_ID_IN(15 downto 8) & MC_UNIQUE_ID_IN(23 downto 16) & MC_UNIQUE_ID_IN(31 downto 24) & x"0" & MC_UNIQUE_ID_IN(35 downto 32) & x"7ada";
ISSUE_REBOOT_OUT <= '0' when issue_reboot = '0' else '1';
- STATUS_OUT(7 downto 0) <= (others => '0');
- STATUS_OUT(8) <= dhcp_done; -- DHCP has completed
- STATUS_OUT(15 downto 9) <= (others => '0');
+ STATUS_OUT(7 downto 1) <= (others => '0');
+ STATUS_OUT(0) <= dhcp_done; -- DHCP has completed
gbe_inst : entity work.gbe_logic_wrapper
generic map(
MONITOR_DROPPED_OUT => monitor_dropped,
MONITOR_GEN_DBG_OUT => monitor_gen_dbg,
MAKE_RESET_OUT => make_reset0,
- DEBUG_OUT => DEBUG_OUT
+ DEBUG_OUT => open --DEBUG_OUT
);
BUS_IP_TX.ack <= busip0.ack when rising_edge(CLK_125_IN);
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-use work.trb_net_gbe_components.all;
-use work.trb_net_gbe_protocols.all;
-
---********
--- here all frame checking has to be done, if the frame fits into protocol standards
--- if so FR_FRAME_VALID_OUT is asserted after having received all bytes of a frame
--- otherwise, after receiving all bytes, FR_FRAME_VALID_OUT keeps low and the fifo is cleared
--- also a part of addresses assignment has to be done here
-
-entity trb_net16_gbe_frame_receiver is
-port (
- CLK : in std_logic; -- system clock
- RESET : in std_logic;
- LINK_OK_IN : in std_logic;
- ALLOW_RX_IN : in std_logic;
- MY_MAC_IN : in std_logic_vector(47 downto 0);
---
- MY_TRBNET_ADDRESS_IN : in std_logic_vector(15 downto 0) := (others => '0');
- ISSUE_REBOOT_OUT : out std_logic;
--- input signals from TS_MAC
- MAC_RX_EOF_IN : in std_logic;
- MAC_RX_ER_IN : in std_logic;
- MAC_RXD_IN : in std_logic_vector(7 downto 0);
- MAC_RX_EN_IN : in std_logic;
- MAC_RX_FIFO_ERR_IN : in std_logic; -- UNUSED
- MAC_RX_FIFO_FULL_OUT : out std_logic;
- MAC_RX_STAT_EN_IN : in std_logic;
- MAC_RX_STAT_VEC_IN : in std_logic_vector(31 downto 0); -- UNUSED
--- output signal to control logic
- FR_Q_OUT : out std_logic_vector(8 downto 0);
- FR_RD_EN_IN : in std_logic;
- FR_FRAME_VALID_OUT : out std_logic;
- FR_GET_FRAME_IN : in std_logic;
- FR_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
- FR_FRAME_PROTO_OUT : out std_logic_vector(15 downto 0);
- FR_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- FR_ALLOWED_TYPES_IN : in std_logic_vector(31 downto 0);
- FR_ALLOWED_IP_IN : in std_logic_vector(31 downto 0);
- FR_ALLOWED_UDP_IN : in std_logic_vector(31 downto 0);
- FR_VLAN_ID_IN : in std_logic_vector(31 downto 0);
---
- FR_SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0);
- FR_DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0);
- FR_SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0);
- FR_DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0);
- FR_SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0);
- FR_DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0);
---
- MONITOR_RX_BYTES_OUT : out std_logic_vector(31 downto 0);
- MONITOR_RX_FRAMES_OUT : out std_logic_vector(31 downto 0);
- MONITOR_DROPPED_OUT : out std_logic_vector(31 downto 0)
-);
-end trb_net16_gbe_frame_receiver;
-
-architecture trb_net16_gbe_frame_receiver of trb_net16_gbe_frame_receiver is
-
-attribute syn_encoding : string;
-type filter_states is (IDLE, REMOVE_DEST, REMOVE_SRC, REMOVE_TYPE, SAVE_FRAME, DROP_FRAME,
- REMOVE_VID, REMOVE_VTYPE, REMOVE_IP, REMOVE_UDP, DECIDE, CLEANUP);
-signal filter_current_state, filter_next_state : filter_states;
-attribute syn_encoding of filter_current_state : signal is "onehot";
-
-signal fifo_wr_en : std_logic;
-signal rx_bytes_ctr : std_logic_vector(15 downto 0);
-signal frame_valid_q : std_logic;
-signal delayed_frame_valid : std_logic;
-signal delayed_frame_valid_q : std_logic;
-
-signal rec_fifo_empty : std_logic;
-signal rec_fifo_full : std_logic;
-signal sizes_fifo_full : std_logic;
-signal sizes_fifo_empty : std_logic;
-
-signal remove_ctr : unsigned(7 downto 0);
-signal new_frame : std_logic;
-signal new_frame_lock : std_logic := '0';
-signal saved_frame_type : std_logic_vector(15 downto 0);
-signal saved_vid : std_logic_vector(15 downto 0) := (others => '0');
-signal saved_src_mac : std_logic_vector(47 downto 0);
-signal saved_dest_mac : std_logic_vector(47 downto 0);
-signal frame_type_valid : std_logic;
-signal saved_proto : std_logic_vector(7 downto 0);
-signal saved_src_ip : std_logic_vector(31 downto 0);
-signal saved_dest_ip : std_logic_vector(31 downto 0);
-signal saved_src_udp : std_logic_vector(15 downto 0);
-signal saved_dest_udp : std_logic_vector(15 downto 0);
-
-signal error_frames_ctr : unsigned(15 downto 0);
-signal dbg_rec_frames : unsigned(31 downto 0);
-signal dbg_drp_frames : unsigned(31 downto 0);
-signal mon_rec_bytes : unsigned(31 downto 0);
-
-signal state : std_logic_vector(3 downto 0);
-
-signal rx_data : std_logic_vector(8 downto 0);
-signal fr_q : std_logic_vector(8 downto 0);
-
-signal fr_src_ip : std_logic_vector(31 downto 0);
-signal fr_dest_ip : std_logic_vector(31 downto 0);
-signal fr_dest_udp : std_logic_vector(15 downto 0);
-signal fr_src_udp : std_logic_vector(15 downto 0);
-signal fr_frame_size : std_logic_vector(15 downto 0);
-signal fr_frame_proto : std_logic_vector(15 downto 0);
-signal fr_dest_mac : std_logic_vector(47 downto 0);
-signal fr_src_mac : std_logic_vector(47 downto 0);
-signal fr_ip_proto : std_logic_vector(7 downto 0);
-
-attribute syn_preserve : boolean;
-attribute syn_keep : boolean;
-attribute syn_keep of rec_fifo_empty, rec_fifo_full, state, sizes_fifo_empty, sizes_fifo_full : signal is true;
-attribute syn_preserve of rec_fifo_empty, rec_fifo_full, state, sizes_fifo_empty, sizes_fifo_full : signal is true;
-
-begin
-
--- new_frame is asserted when first byte of the frame arrives
-THE_NEW_FRAME_PROC: process( CLK )
-begin
- if( rising_edge(CLK) )then
- if ( (LINK_OK_IN = '0') or (MAC_RX_EOF_IN = '1') ) then
- new_frame <= '0';
- new_frame_lock <= '0';
- elsif( (new_frame_lock = '0') and (MAC_RX_EN_IN = '1') ) then
- new_frame <= '1';
- new_frame_lock <= '1';
- else
- new_frame <= '0';
- new_frame_lock <= new_frame_lock;
- end if;
- end if;
-end process THE_NEW_FRAME_PROC;
-
-THE_FILTER_MACHINE_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if( RESET = '1' ) then
- filter_current_state <= IDLE;
- else
- filter_current_state <= filter_next_state;
- end if;
- end if;
-end process THE_FILTER_MACHINE_PROC;
-
-THE_FILTER_MACHINE : process( filter_current_state, saved_frame_type, LINK_OK_IN, saved_proto, MY_MAC_IN,
- saved_dest_mac, remove_ctr, new_frame, MAC_RX_EOF_IN, frame_type_valid, ALLOW_RX_IN)
-begin
- case filter_current_state is
-
- when IDLE =>
- state <= x"1";
- if( (new_frame = '1') and (ALLOW_RX_IN = '1') and (LINK_OK_IN = '1') ) then
- filter_next_state <= REMOVE_DEST;
- else
- filter_next_state <= IDLE;
- end if;
-
- -- frames arrive without preamble!
- when REMOVE_DEST =>
- state <= x"3";
- if( remove_ctr = x"03" ) then -- counter starts with a delay that's why only 3
- -- destination MAC address filtering here
- if( (saved_dest_mac = MY_MAC_IN) or (saved_dest_mac = x"ffffffffffff") ) then -- must accept broadcasts for ARP
- filter_next_state <= REMOVE_SRC;
- else
- filter_next_state <= DECIDE;
- end if;
- else
- filter_next_state <= REMOVE_DEST;
- end if;
-
- when REMOVE_SRC =>
- state <= x"4";
- if( remove_ctr = x"09" ) then
- filter_next_state <= REMOVE_TYPE;
- else
- filter_next_state <= REMOVE_SRC;
- end if;
-
- when REMOVE_TYPE =>
- state <= x"5";
- if( remove_ctr = x"0b" ) then
- if( saved_frame_type = x"8100" ) then -- VLAN tagged frame
- filter_next_state <= REMOVE_VID;
- else -- no VLAN tag
- if( saved_frame_type = x"0800" ) then -- in case of IP continue removing headers
- filter_next_state <= REMOVE_IP;
- else
- filter_next_state <= DECIDE;
- end if;
- end if;
- else
- filter_next_state <= REMOVE_TYPE;
- end if;
-
- when REMOVE_VID =>
- state <= x"a";
- if( remove_ctr = x"0d" ) then
- filter_next_state <= REMOVE_VTYPE;
- else
- filter_next_state <= REMOVE_VID;
- end if;
-
- when REMOVE_VTYPE =>
- state <= x"b";
- if( remove_ctr = x"0f" ) then
- if( saved_frame_type = x"0800" ) then -- in case of IP continue removing headers
- filter_next_state <= REMOVE_IP;
- else
- filter_next_state <= DECIDE;
- end if;
- else
- filter_next_state <= REMOVE_VTYPE;
- end if;
-
- when REMOVE_IP =>
- state <= x"c";
- if( remove_ctr = x"11" ) then
- if( saved_proto = x"11" ) then -- forced to recognize udp only, TODO check all protocols
- filter_next_state <= REMOVE_UDP;
- else
- filter_next_state <= DECIDE; -- changed from drop
- end if;
- else
- filter_next_state <= REMOVE_IP;
- end if;
-
- when REMOVE_UDP =>
- state <= x"d";
- if( remove_ctr = x"19" ) then
- filter_next_state <= DECIDE;
- else
- filter_next_state <= REMOVE_UDP;
- end if;
-
- when DECIDE =>
- state <= x"6";
- if ( frame_type_valid = '1' ) then
- filter_next_state <= SAVE_FRAME;
- elsif( saved_frame_type = x"0806" ) then
- -- ARP?
- filter_next_state <= SAVE_FRAME;
- else
- filter_next_state <= DROP_FRAME;
- end if;
-
- when SAVE_FRAME =>
- state <= x"7";
- if( MAC_RX_EOF_IN = '1' ) then
- filter_next_state <= CLEANUP;
- else
- filter_next_state <= SAVE_FRAME;
- end if;
-
- when DROP_FRAME =>
- state <= x"8";
- if( MAC_RX_EOF_IN = '1' ) then
- filter_next_state <= CLEANUP;
- else
- filter_next_state <= DROP_FRAME;
- end if;
-
- when CLEANUP =>
- state <= x"9";
- filter_next_state <= IDLE;
-
- when others => null;
-
- end case;
-end process THE_FILTER_MACHINE;
-
--- counts the bytes to be removed from the ethernet headers fields
-REMOVE_CTR_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if( (filter_current_state = IDLE) or
- (filter_current_state = REMOVE_VTYPE and remove_ctr = x"0f") or
- (filter_current_state = REMOVE_TYPE and remove_ctr = x"0b") ) then
- remove_ctr <= (others => '1');
- elsif( (MAC_RX_EN_IN = '1') and (filter_current_state /= IDLE) ) then
- remove_ctr <= remove_ctr + 1;
- else
- remove_ctr <= remove_ctr;
- end if;
- end if;
-end process REMOVE_CTR_PROC;
-
-THE_SAVED_PROTO_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( filter_current_state = CLEANUP ) then
- saved_proto <= (others => '0');
- elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"07") ) then
- saved_proto <= MAC_RXD_IN;
- else
- saved_proto <= saved_proto;
- end if;
- end if;
-end process THE_SAVED_PROTO_PROC;
-
-THE_SAVED_SRC_IP_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( filter_current_state = CLEANUP ) then
- saved_src_ip <= (others => '0');
- elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"0a") ) then
- saved_src_ip(7 downto 0) <= MAC_RXD_IN;
- elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"0b") ) then
- saved_src_ip(15 downto 8) <= MAC_RXD_IN;
- elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"0c") ) then
- saved_src_ip(23 downto 16) <= MAC_RXD_IN;
- elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"0d") ) then
- saved_src_ip(31 downto 24) <= MAC_RXD_IN;
- else
- saved_src_ip <= saved_src_ip;
- end if;
- end if;
-end process THE_SAVED_SRC_IP_PROC;
-
-THE_SAVED_DEST_IP_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( filter_current_state = CLEANUP ) then
- saved_dest_ip <= (others => '0');
- elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"0e") ) then
- saved_dest_ip(7 downto 0) <= MAC_RXD_IN;
- elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"0f") ) then
- saved_dest_ip(15 downto 8) <= MAC_RXD_IN;
- elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"10") ) then
- saved_dest_ip(23 downto 16) <= MAC_RXD_IN;
- elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"11") ) then
- saved_dest_ip(31 downto 24) <= MAC_RXD_IN;
- else
- saved_dest_ip <= saved_dest_ip;
- end if;
- end if;
-end process THE_SAVED_DEST_IP_PROC;
-
-THE_SAVED_SRC_UDP_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( filter_current_state = CLEANUP ) then
- saved_src_udp <= (others => '0');
- elsif( (filter_current_state = REMOVE_UDP) and (remove_ctr = x"12") ) then
- saved_src_udp(15 downto 8) <= MAC_RXD_IN;
- elsif( (filter_current_state = REMOVE_UDP) and (remove_ctr = x"13") ) then
- saved_src_udp(7 downto 0) <= MAC_RXD_IN;
- else
- saved_src_udp <= saved_src_udp;
- end if;
- end if;
-end process THE_SAVED_SRC_UDP_PROC;
-
-THE_SAVED_DEST_UDP_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( filter_current_state = CLEANUP ) then
- saved_dest_udp <= (others => '0');
- elsif( (filter_current_state = REMOVE_UDP) and (remove_ctr = x"14") ) then
- saved_dest_udp(15 downto 8) <= MAC_RXD_IN;
- elsif( (filter_current_state = REMOVE_UDP) and (remove_ctr = x"15") ) then
- saved_dest_udp(7 downto 0) <= MAC_RXD_IN;
- else
- saved_dest_udp <= saved_dest_udp;
- end if;
- end if;
-end process THE_SAVED_DEST_UDP_PROC;
-
--- saves the destination mac address of the incoming frame
-THE_SAVED_DEST_MAC_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( filter_current_state = CLEANUP ) then
- saved_dest_mac <= (others => '0');
- elsif( (filter_current_state = IDLE) and (MAC_RX_EN_IN = '1') and (new_frame = '0') ) then
- saved_dest_mac(7 downto 0) <= MAC_RXD_IN;
- elsif( (filter_current_state = IDLE) and (new_frame = '1') and (ALLOW_RX_IN = '1') ) then
- saved_dest_mac(15 downto 8) <= MAC_RXD_IN;
- elsif( (filter_current_state = REMOVE_DEST) and (remove_ctr = x"FF") ) then
- saved_dest_mac(23 downto 16) <= MAC_RXD_IN;
- elsif( (filter_current_state = REMOVE_DEST) and (remove_ctr = x"00") ) then
- saved_dest_mac(31 downto 24) <= MAC_RXD_IN;
- elsif( (filter_current_state = REMOVE_DEST) and (remove_ctr = x"01") ) then
- saved_dest_mac(39 downto 32) <= MAC_RXD_IN;
- elsif( (filter_current_state = REMOVE_DEST) and (remove_ctr = x"02") ) then
- saved_dest_mac(47 downto 40) <= MAC_RXD_IN;
- else
- saved_dest_mac <= saved_dest_mac;
- end if;
- end if;
-end process THE_SAVED_DEST_MAC_PROC;
-
--- saves the source mac address of the incoming frame
-THE_SAVED_SRC_MAC_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( filter_current_state = CLEANUP ) then
- saved_src_mac <= (others => '0');
- elsif( (filter_current_state = REMOVE_DEST) and (remove_ctr = x"03") )then
- saved_src_mac(7 downto 0) <= MAC_RXD_IN;
- elsif( (filter_current_state = REMOVE_SRC) and (remove_ctr = x"04") ) then
- saved_src_mac(15 downto 8) <= MAC_RXD_IN;
- elsif( (filter_current_state = REMOVE_SRC) and (remove_ctr = x"05") ) then
- saved_src_mac(23 downto 16) <= MAC_RXD_IN;
- elsif( (filter_current_state = REMOVE_SRC) and (remove_ctr = x"06") ) then
- saved_src_mac(31 downto 24) <= MAC_RXD_IN;
- elsif( (filter_current_state = REMOVE_SRC) and (remove_ctr = x"07") ) then
- saved_src_mac(39 downto 32) <= MAC_RXD_IN;
- elsif( (filter_current_state = REMOVE_SRC) and (remove_ctr = x"08") ) then
- saved_src_mac(47 downto 40) <= MAC_RXD_IN;
- else
- saved_src_mac <= saved_src_mac;
- end if;
- end if;
-end process THE_SAVED_SRC_MAC_PROC;
-
--- saves the frame type of the incoming frame for futher check
-THE_SAVED_FRAME_TYPE_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( filter_current_state = CLEANUP ) then
- saved_frame_type <= (others => '0');
- elsif( (filter_current_state = REMOVE_SRC) and (remove_ctr = x"09") ) then
- saved_frame_type(15 downto 8) <= MAC_RXD_IN;
- elsif( (filter_current_state = REMOVE_TYPE) and (remove_ctr = x"0a") ) then
- saved_frame_type(7 downto 0) <= MAC_RXD_IN;
- -- two more cases for VLAN tagged frame
- elsif( (filter_current_state = REMOVE_VID) and (remove_ctr = x"0d") ) then
- saved_frame_type(15 downto 8) <= MAC_RXD_IN;
- elsif( (filter_current_state = REMOVE_VTYPE) and (remove_ctr = x"0e") ) then
- saved_frame_type(7 downto 0) <= MAC_RXD_IN;
- else
- saved_frame_type <= saved_frame_type;
- end if;
- end if;
-end process THE_SAVED_FRAME_TYPE_PROC;
-
--- saves VLAN id when tagged frame spotted
-THE_SAVED_VID_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( filter_current_state = CLEANUP ) then
- saved_vid <= (others => '0');
- elsif( (filter_current_state = REMOVE_TYPE) and (remove_ctr = x"0b") and (saved_frame_type = x"8100") ) then
- saved_vid(15 downto 8) <= MAC_RXD_IN;
- elsif( (filter_current_state = REMOVE_VID) and (remove_ctr = x"0c") ) then
- saved_vid(7 downto 0) <= MAC_RXD_IN;
- else
- saved_vid <= saved_vid;
- end if;
- end if;
-end process THE_SAVED_VID_PROC;
-
-THE_TYPE_VALIDATOR: trb_net16_gbe_type_validator
-port map(
- CLK => CLK,
- RESET => RESET,
- FRAME_TYPE_IN => saved_frame_type,
- SAVED_VLAN_ID_IN => saved_vid,
- ALLOWED_TYPES_IN => FR_ALLOWED_TYPES_IN,
- VLAN_ID_IN => FR_VLAN_ID_IN,
- -- IP level
- IP_PROTOCOLS_IN => saved_proto,
- ALLOWED_IP_PROTOCOLS_IN => FR_ALLOWED_IP_IN,
- -- UDP level
- UDP_PROTOCOL_IN => saved_dest_udp,
- ALLOWED_UDP_PROTOCOLS_IN => FR_ALLOWED_UDP_IN,
- --
- VALID_OUT => frame_type_valid
-);
-
-THE_RECEIVE_FIFO: fifo_4096x9
-port map(
- Data => rx_data,
- WrClock => CLK,
- RdClock => CLK,
- WrEn => fifo_wr_en,
- RdEn => FR_RD_EN_IN,
- Reset => RESET,
- RPReset => RESET,
- Q => fr_q,
- Empty => rec_fifo_empty,
- Full => rec_fifo_full
-);
-
--- killer ping
-THE_KILLER_PING_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if( (filter_current_state = SAVE_FRAME) and (saved_proto = x"01") and (saved_frame_type = x"0800") and
- (rx_bytes_ctr = x"001A") and (rx_data(7 downto 0) = MY_TRBNET_ADDRESS_IN(7 downto 0)) and
- (MAC_RXD_IN = MY_TRBNET_ADDRESS_IN(15 downto 8)) ) then
- ISSUE_REBOOT_OUT <= '1';
- else
- ISSUE_REBOOT_OUT <= '0';
- end if;
- end if;
-end process;
-
-THE_RX_FIFO_SYNC: process( CLK )
-begin
- if rising_edge(CLK) then
-
- rx_data(8) <= MAC_RX_EOF_IN;
- rx_data(7 downto 0) <= MAC_RXD_IN;
-
- if( MAC_RX_EN_IN = '1' ) then
- if ( filter_current_state = SAVE_FRAME ) then
- fifo_wr_en <= '1';
- elsif( (filter_current_state = REMOVE_VTYPE) and (remove_ctr = x"f") ) then
- fifo_wr_en <= '1';
- elsif( (filter_current_state = DECIDE) and (frame_type_valid = '1') ) then
- fifo_wr_en <= '1';
- else
- fifo_wr_en <= '0';
- end if;
- else
- fifo_wr_en <= '0';
- end if;
-
- MAC_RX_FIFO_FULL_OUT <= rec_fifo_full;
- end if;
-end process THE_RX_FIFO_SYNC;
-
-THE_SIZES_FIFO: fifo_512x32
-port map(
- Data(15 downto 0) => rx_bytes_ctr,
- Data(31 downto 16) => saved_frame_type,
- WrClock => CLK,
- RdClock => CLK,
- WrEn => frame_valid_q,
- RdEn => FR_GET_FRAME_IN,
- Reset => RESET,
- RPReset => RESET,
- Q(15 downto 0) => fr_frame_size,
- Q(31 downto 16) => fr_frame_proto,
- Empty => sizes_fifo_empty,
- Full => sizes_fifo_full
-);
-
-THE_MACS_FIFO: fifo_512x72
-port map(
- Data(47 downto 0) => saved_src_mac,
- Data(63 downto 48) => saved_src_udp,
- Data(71 downto 64) => (others => '0'),
- WrClock => CLK,
- RdClock => CLK,
- WrEn => frame_valid_q,
- RdEn => FR_GET_FRAME_IN,
- Reset => RESET,
- RPReset => RESET,
- Q(47 downto 0) => fr_src_mac,
- Q(63 downto 48) => fr_src_udp,
- Q(71 downto 64) => open,
- Empty => open,
- Full => open
-);
-
-THE_MACD_FIFO: fifo_512x72
-port map(
- Data(47 downto 0) => saved_dest_mac,
- Data(63 downto 48) => saved_dest_udp,
- Data(71 downto 64) => (others => '0'),
- WrClock => CLK,
- RdClock => CLK,
- WrEn => frame_valid_q,
- RdEn => FR_GET_FRAME_IN,
- Reset => RESET,
- RPReset => RESET,
- Q(47 downto 0) => fr_dest_mac,
- Q(63 downto 48) => fr_dest_udp,
- Q(71 downto 64) => open,
- Empty => open,
- Full => open
-);
-
-THE_IP_FIFO: fifo_512x72
-port map(
- Data(31 downto 0) => saved_src_ip,
- Data(63 downto 32) => saved_dest_ip,
- Data(71 downto 64) => saved_proto,
- WrClock => CLK,
- RdClock => CLK,
- WrEn => frame_valid_q,
- RdEn => FR_GET_FRAME_IN,
- Reset => RESET,
- RPReset => RESET,
- Q(31 downto 0) => fr_src_ip,
- Q(63 downto 32) => fr_dest_ip,
- Q(71 downto 64) => fr_ip_proto,
- Empty => open,
- Full => open
-);
-
-THE_SYNC_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- FR_SRC_IP_ADDRESS_OUT <= fr_src_ip;
- FR_DEST_IP_ADDRESS_OUT <= fr_dest_ip;
- FR_IP_PROTOCOL_OUT <= fr_ip_proto;
- FR_DEST_UDP_PORT_OUT <= fr_dest_udp;
- FR_DEST_MAC_ADDRESS_OUT <= fr_dest_mac;
- FR_SRC_MAC_ADDRESS_OUT <= fr_src_mac;
- FR_SRC_UDP_PORT_OUT <= fr_src_udp;
- FR_FRAME_PROTO_OUT <= fr_frame_proto;
- FR_FRAME_SIZE_OUT <= fr_frame_size;
- FR_Q_OUT <= fr_q;
- --
- delayed_frame_valid <= MAC_RX_EOF_IN;
- delayed_frame_valid_q <= delayed_frame_valid;
- end if;
-end process THE_SYNC_PROC;
-
-THE_FRAME_VALID_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if( (MAC_RX_EOF_IN = '1') and (ALLOW_RX_IN = '1') and (frame_type_valid = '1') ) then
- frame_valid_q <= '1';
- else
- frame_valid_q <= '0';
- end if;
- end if;
-end process THE_FRAME_VALID_PROC;
-
-THE_RX_BYTES_CTR_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( (RESET = '1') or (delayed_frame_valid_q = '1') ) then
- rx_bytes_ctr <= x"0001";
- elsif( fifo_wr_en = '1' ) then
- rx_bytes_ctr <= rx_bytes_ctr + 1;
- end if;
- end if;
-end process THE_RX_BYTES_CTR_PROC;
-
-THE_ERROR_FRAMES_CTR_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( RESET = '1' ) then
- error_frames_ctr <= (others => '0');
- elsif( MAC_RX_ER_IN = '1' ) then
- error_frames_ctr <= error_frames_ctr + 1;
- end if;
- end if;
-end process THE_ERROR_FRAMES_CTR_PROC;
-
-FR_FRAME_VALID_OUT <= frame_valid_q when rising_edge(CLK);
-
-THE_RECEIVED_FRAMES_CTR: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( RESET = '1' ) then
- dbg_rec_frames <= (others => '0');
- elsif( MAC_RX_EOF_IN = '1' ) then
- dbg_rec_frames <= dbg_rec_frames + 1;
- end if;
- end if;
-end process THE_RECEIVED_FRAMES_CTR;
-
-THE_DROPPED_FRAMES_CTR: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if ( RESET = '1' ) then
- dbg_drp_frames <= (others => '0');
- elsif( (filter_current_state = DECIDE) and (frame_type_valid = '0') ) then
- dbg_drp_frames <= dbg_drp_frames + 1;
- end if;
- end if;
-end process THE_DROPPED_FRAMES_CTR;
-
---MONITOR_DROPPED_OUT <= std_logic_vector(dbg_drp_frames);
-MONITOR_RX_FRAMES_OUT <= std_logic_vector(dbg_rec_frames);
-MONITOR_RX_BYTES_OUT <= std_logic_vector(mon_rec_bytes);
-
-MONITOR_DROPPED_OUT(0) <= rec_fifo_empty;
-MONITOR_DROPPED_OUT(1) <= fifo_wr_en;
-
-THE_MON_REC_BYTES_PROC: process(CLK)
-begin
- if( rising_edge(CLK) ) then
- if ( RESET = '1' ) then
- mon_rec_bytes <= (others => '0');
- elsif( fifo_wr_en = '1' ) then
- mon_rec_bytes <= mon_rec_bytes + x"1";
- else
- mon_rec_bytes <= mon_rec_bytes;
- end if;
- end if;
-end process;
-
-end trb_net16_gbe_frame_receiver;
-
-
+LIBRARY IEEE;\r
+USE IEEE.std_logic_1164.ALL;\r
+USE IEEE.numeric_std.ALL;\r
+USE IEEE.std_logic_UNSIGNED.ALL;\r
+\r
+library work;\r
+use work.trb_net_std.all;\r
+use work.trb_net_components.all;\r
+use work.trb_net16_hub_func.all;\r
+use work.trb_net_gbe_components.all;\r
+use work.trb_net_gbe_protocols.all;\r
+\r
+--********\r
+-- here all frame checking has to be done, if the frame fits into protocol standards\r
+-- if so FR_FRAME_VALID_OUT is asserted after having received all bytes of a frame\r
+-- otherwise, after receiving all bytes, FR_FRAME_VALID_OUT keeps low and the fifo is cleared\r
+-- also a part of addresses assignment has to be done here\r
+\r
+-- This entity receives an Ethernet frame, disassembles it and checks if the frame has tobe processed.\r
+-- In case, decoded information from header is stored in FIFOs and next stage is informed about available\r
+-- data by FR_FRAME_VALID_OUT.\r
+\r
+entity trb_net16_gbe_frame_receiver is\r
+port (\r
+ CLK : in std_logic; -- system clock\r
+ RESET : in std_logic;\r
+ LINK_OK_IN : in std_logic;\r
+ ALLOW_RX_IN : in std_logic;\r
+ MY_MAC_IN : in std_logic_vector(47 downto 0);\r
+--\r
+ MY_TRBNET_ADDRESS_IN : in std_logic_vector(15 downto 0) := (others => '0');\r
+ ISSUE_REBOOT_OUT : out std_logic;\r
+-- input signals from TS_MAC\r
+ MAC_RX_EOF_IN : in std_logic; -- End Of Frame\r
+ MAC_RX_ER_IN : in std_logic; -- only for statistics\r
+ MAC_RXD_IN : in std_logic_vector(7 downto 0); -- RX data\r
+ MAC_RX_EN_IN : in std_logic; -- write signal\r
+ MAC_RX_FIFO_ERR_IN : in std_logic; -- UNUSED\r
+ MAC_RX_FIFO_FULL_OUT : out std_logic; -- not really needed\r
+ MAC_RX_STAT_EN_IN : in std_logic; -- UNUSED\r
+ MAC_RX_STAT_VEC_IN : in std_logic_vector(31 downto 0); -- UNUSED\r
+-- output signal to control logic\r
+ FR_Q_OUT : out std_logic_vector(8 downto 0);\r
+ FR_RD_EN_IN : in std_logic;\r
+ FR_FRAME_VALID_OUT : out std_logic;\r
+ FR_GET_FRAME_IN : in std_logic;\r
+ FR_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);\r
+ FR_FRAME_PROTO_OUT : out std_logic_vector(15 downto 0);\r
+ FR_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);\r
+ FR_ALLOWED_TYPES_IN : in std_logic_vector(31 downto 0);\r
+ FR_ALLOWED_IP_IN : in std_logic_vector(31 downto 0);\r
+ FR_ALLOWED_UDP_IN : in std_logic_vector(31 downto 0);\r
+ FR_VLAN_ID_IN : in std_logic_vector(31 downto 0);\r
+--\r
+ FR_SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0);\r
+ FR_DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0);\r
+ FR_SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0);\r
+ FR_DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0);\r
+ FR_SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0);\r
+ FR_DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0);\r
+--\r
+ MONITOR_RX_BYTES_OUT : out std_logic_vector(31 downto 0);\r
+ MONITOR_RX_FRAMES_OUT : out std_logic_vector(31 downto 0);\r
+ MONITOR_DROPPED_OUT : out std_logic_vector(31 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+);\r
+end trb_net16_gbe_frame_receiver;\r
+\r
+architecture trb_net16_gbe_frame_receiver of trb_net16_gbe_frame_receiver is\r
+\r
+attribute syn_encoding : string;\r
+type filter_states is (IDLE, REMOVE_DEST, REMOVE_SRC, REMOVE_TYPE, SAVE_FRAME, DROP_FRAME,\r
+ REMOVE_VID, REMOVE_VTYPE, REMOVE_IP, REMOVE_UDP, DECIDE, CLEANUP);\r
+signal filter_current_state, filter_next_state : filter_states;\r
+attribute syn_encoding of filter_current_state : signal is "onehot";\r
+\r
+signal fifo_wr_en : std_logic;\r
+signal rx_bytes_ctr : std_logic_vector(15 downto 0);\r
+signal frame_valid_q : std_logic;\r
+signal delayed_frame_valid : std_logic;\r
+signal delayed_frame_valid_q : std_logic;\r
+\r
+signal rec_fifo_empty : std_logic;\r
+signal rec_fifo_full : std_logic;\r
+signal sizes_fifo_full : std_logic;\r
+signal sizes_fifo_empty : std_logic;\r
+\r
+signal remove_ctr : unsigned(7 downto 0);\r
+signal new_frame : std_logic;\r
+signal new_frame_lock : std_logic := '0';\r
+signal saved_frame_type : std_logic_vector(15 downto 0);\r
+signal saved_vid : std_logic_vector(15 downto 0) := (others => '0');\r
+signal saved_src_mac : std_logic_vector(47 downto 0);\r
+signal saved_dest_mac : std_logic_vector(47 downto 0);\r
+signal frame_type_valid : std_logic;\r
+signal saved_proto : std_logic_vector(7 downto 0);\r
+signal saved_src_ip : std_logic_vector(31 downto 0);\r
+signal saved_dest_ip : std_logic_vector(31 downto 0);\r
+signal saved_src_udp : std_logic_vector(15 downto 0);\r
+signal saved_dest_udp : std_logic_vector(15 downto 0);\r
+\r
+signal error_frames_ctr : unsigned(15 downto 0);\r
+signal dbg_rec_frames : unsigned(31 downto 0);\r
+signal dbg_drp_frames : unsigned(31 downto 0);\r
+signal mon_rec_bytes : unsigned(31 downto 0);\r
+\r
+signal state : std_logic_vector(3 downto 0);\r
+\r
+signal rx_data : std_logic_vector(8 downto 0);\r
+signal fr_q : std_logic_vector(8 downto 0);\r
+\r
+signal fr_src_ip : std_logic_vector(31 downto 0);\r
+signal fr_dest_ip : std_logic_vector(31 downto 0);\r
+signal fr_dest_udp : std_logic_vector(15 downto 0);\r
+signal fr_src_udp : std_logic_vector(15 downto 0);\r
+signal fr_frame_size : std_logic_vector(15 downto 0);\r
+signal fr_frame_proto : std_logic_vector(15 downto 0);\r
+signal fr_dest_mac : std_logic_vector(47 downto 0);\r
+signal fr_src_mac : std_logic_vector(47 downto 0);\r
+signal fr_ip_proto : std_logic_vector(7 downto 0);\r
+\r
+signal xxx0 : std_logic_vector(7 downto 0);\r
+signal xxx1 : std_logic_vector(7 downto 0);\r
+\r
+attribute syn_preserve : boolean;\r
+attribute syn_keep : boolean;\r
+attribute syn_keep of rec_fifo_empty, rec_fifo_full, state, sizes_fifo_empty, sizes_fifo_full : signal is true;\r
+attribute syn_preserve of rec_fifo_empty, rec_fifo_full, state, sizes_fifo_empty, sizes_fifo_full : signal is true;\r
+\r
+begin\r
+\r
+-- new_frame is asserted when first byte of the frame arrives\r
+THE_NEW_FRAME_PROC: process( CLK )\r
+begin\r
+ if( rising_edge(CLK) )then\r
+ if ( (LINK_OK_IN = '0') or (MAC_RX_EOF_IN = '1') ) then\r
+ new_frame <= '0';\r
+ new_frame_lock <= '0';\r
+ elsif( (new_frame_lock = '0') and (MAC_RX_EN_IN = '1') ) then\r
+ new_frame <= '1';\r
+ new_frame_lock <= '1';\r
+ else\r
+ new_frame <= '0';\r
+ new_frame_lock <= new_frame_lock;\r
+ end if;\r
+ end if;\r
+end process THE_NEW_FRAME_PROC;\r
+\r
+THE_FILTER_MACHINE_PROC: process( CLK )\r
+begin\r
+ if( rising_edge(CLK) ) then\r
+ if( RESET = '1' ) then\r
+ filter_current_state <= IDLE;\r
+ else\r
+ filter_current_state <= filter_next_state;\r
+ end if;\r
+ end if;\r
+end process THE_FILTER_MACHINE_PROC;\r
+\r
+THE_FILTER_MACHINE : process( filter_current_state, saved_frame_type, LINK_OK_IN, saved_proto, MY_MAC_IN,\r
+ saved_dest_mac, remove_ctr, new_frame, MAC_RX_EOF_IN, frame_type_valid, ALLOW_RX_IN)\r
+begin\r
+ case filter_current_state is\r
+\r
+ when IDLE =>\r
+ state <= x"1";\r
+ if( (new_frame = '1') and (ALLOW_RX_IN = '1') and (LINK_OK_IN = '1') ) then\r
+ filter_next_state <= REMOVE_DEST;\r
+ else\r
+ filter_next_state <= IDLE;\r
+ end if;\r
+\r
+ -- frames arrive without preamble!\r
+ when REMOVE_DEST =>\r
+ state <= x"3";\r
+ if( remove_ctr = x"03" ) then -- counter starts with a delay that's why only 3\r
+ -- destination MAC address filtering here\r
+ if( (saved_dest_mac = MY_MAC_IN) or (saved_dest_mac = x"ffffffffffff") ) then -- must accept broadcasts for ARP\r
+ filter_next_state <= REMOVE_SRC;\r
+ else\r
+ filter_next_state <= DECIDE;\r
+ end if;\r
+ else\r
+ filter_next_state <= REMOVE_DEST;\r
+ end if;\r
+\r
+ when REMOVE_SRC =>\r
+ state <= x"4";\r
+ if( remove_ctr = x"09" ) then\r
+ filter_next_state <= REMOVE_TYPE;\r
+ else\r
+ filter_next_state <= REMOVE_SRC;\r
+ end if;\r
+\r
+ when REMOVE_TYPE =>\r
+ state <= x"5";\r
+ if( remove_ctr = x"0b" ) then\r
+ if( saved_frame_type = x"8100" ) then -- VLAN tagged frame\r
+ filter_next_state <= REMOVE_VID;\r
+ else -- no VLAN tag\r
+ if( saved_frame_type = x"0800" ) then -- in case of IP continue removing headers\r
+ filter_next_state <= REMOVE_IP;\r
+ else\r
+ filter_next_state <= DECIDE;\r
+ end if;\r
+ end if;\r
+ else\r
+ filter_next_state <= REMOVE_TYPE;\r
+ end if;\r
+\r
+ when REMOVE_VID =>\r
+ state <= x"a";\r
+ if( remove_ctr = x"0d" ) then\r
+ filter_next_state <= REMOVE_VTYPE;\r
+ else\r
+ filter_next_state <= REMOVE_VID;\r
+ end if;\r
+\r
+ when REMOVE_VTYPE =>\r
+ state <= x"b";\r
+ if( remove_ctr = x"0f" ) then\r
+ if( saved_frame_type = x"0800" ) then -- in case of IP continue removing headers\r
+ filter_next_state <= REMOVE_IP;\r
+ else\r
+ filter_next_state <= DECIDE;\r
+ end if;\r
+ else\r
+ filter_next_state <= REMOVE_VTYPE;\r
+ end if;\r
+\r
+ when REMOVE_IP =>\r
+ state <= x"c";\r
+ if( remove_ctr = x"11" ) then\r
+ if( saved_proto = x"11" ) then -- forced to recognize udp only, TODO check all protocols\r
+ filter_next_state <= REMOVE_UDP;\r
+ else\r
+ filter_next_state <= DECIDE; -- changed from drop\r
+ end if;\r
+ else\r
+ filter_next_state <= REMOVE_IP;\r
+ end if;\r
+\r
+ when REMOVE_UDP =>\r
+ state <= x"d";\r
+ if( remove_ctr = x"19" ) then\r
+ filter_next_state <= DECIDE;\r
+ else\r
+ filter_next_state <= REMOVE_UDP;\r
+ end if;\r
+\r
+ when DECIDE =>\r
+ state <= x"6";\r
+ if ( frame_type_valid = '1' ) then\r
+ filter_next_state <= SAVE_FRAME;\r
+ elsif( saved_frame_type = x"0806" ) then\r
+ -- ARP?\r
+ filter_next_state <= SAVE_FRAME;\r
+ else\r
+ filter_next_state <= DROP_FRAME;\r
+ end if;\r
+\r
+ when SAVE_FRAME =>\r
+ state <= x"7";\r
+ if( MAC_RX_EOF_IN = '1' ) then\r
+ filter_next_state <= CLEANUP;\r
+ else\r
+ filter_next_state <= SAVE_FRAME;\r
+ end if;\r
+\r
+ when DROP_FRAME =>\r
+ state <= x"8";\r
+ if( MAC_RX_EOF_IN = '1' ) then\r
+ filter_next_state <= CLEANUP;\r
+ else\r
+ filter_next_state <= DROP_FRAME;\r
+ end if;\r
+\r
+ when CLEANUP =>\r
+ state <= x"9";\r
+ filter_next_state <= IDLE;\r
+\r
+ when others => null;\r
+\r
+ end case;\r
+end process THE_FILTER_MACHINE;\r
+\r
+-- counts the bytes to be removed from the ethernet headers fields\r
+REMOVE_CTR_PROC: process( CLK )\r
+begin\r
+ if( rising_edge(CLK) ) then\r
+ if ( (filter_current_state = IDLE) or\r
+ ((filter_current_state = REMOVE_VTYPE) and (remove_ctr = x"0f")) or\r
+ ((filter_current_state = REMOVE_TYPE) and (remove_ctr = x"0b") and (saved_frame_type /= x"8100")) ) then\r
+ remove_ctr <= (others => '1');\r
+ elsif( (MAC_RX_EN_IN = '1') and (filter_current_state /= IDLE) ) then\r
+ remove_ctr <= remove_ctr + 1;\r
+ else\r
+ remove_ctr <= remove_ctr;\r
+ end if;\r
+ end if;\r
+end process REMOVE_CTR_PROC;\r
+\r
+THE_SAVED_PROTO_PROC: process( CLK )\r
+begin\r
+ if( rising_edge(CLK) ) then\r
+ if ( filter_current_state = CLEANUP ) then\r
+ saved_proto <= (others => '0');\r
+ elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"07") ) then\r
+ saved_proto <= MAC_RXD_IN;\r
+ else\r
+ saved_proto <= saved_proto;\r
+ end if;\r
+ end if;\r
+end process THE_SAVED_PROTO_PROC;\r
+\r
+-- saves the destination mac address of the incoming frame\r
+THE_SAVED_DEST_MAC_PROC: process( CLK )\r
+begin\r
+ if( rising_edge(CLK) ) then\r
+ if ( filter_current_state = CLEANUP ) then\r
+ saved_dest_mac <= (others => '0');\r
+ elsif( (filter_current_state = IDLE) and (MAC_RX_EN_IN = '1') and (new_frame = '0') ) then\r
+ saved_dest_mac(7 downto 0) <= MAC_RXD_IN;\r
+ elsif( (filter_current_state = IDLE) and (new_frame = '1') and (ALLOW_RX_IN = '1') ) then\r
+ saved_dest_mac(15 downto 8) <= MAC_RXD_IN;\r
+ elsif( (filter_current_state = REMOVE_DEST) and (remove_ctr = x"FF") ) then\r
+ saved_dest_mac(23 downto 16) <= MAC_RXD_IN;\r
+ elsif( (filter_current_state = REMOVE_DEST) and (remove_ctr = x"00") ) then\r
+ saved_dest_mac(31 downto 24) <= MAC_RXD_IN;\r
+ elsif( (filter_current_state = REMOVE_DEST) and (remove_ctr = x"01") ) then\r
+ saved_dest_mac(39 downto 32) <= MAC_RXD_IN;\r
+ elsif( (filter_current_state = REMOVE_DEST) and (remove_ctr = x"02") ) then\r
+ saved_dest_mac(47 downto 40) <= MAC_RXD_IN;\r
+ else\r
+ saved_dest_mac <= saved_dest_mac;\r
+ end if;\r
+ end if;\r
+end process THE_SAVED_DEST_MAC_PROC;\r
+\r
+-- saves the source mac address of the incoming frame\r
+THE_SAVED_SRC_MAC_PROC: process( CLK )\r
+begin\r
+ if( rising_edge(CLK) ) then\r
+ if ( filter_current_state = CLEANUP ) then\r
+ saved_src_mac <= (others => '0');\r
+ elsif( (filter_current_state = REMOVE_DEST) and (remove_ctr = x"03") )then\r
+ saved_src_mac(7 downto 0) <= MAC_RXD_IN;\r
+ elsif( (filter_current_state = REMOVE_SRC) and (remove_ctr = x"04") ) then\r
+ saved_src_mac(15 downto 8) <= MAC_RXD_IN;\r
+ elsif( (filter_current_state = REMOVE_SRC) and (remove_ctr = x"05") ) then\r
+ saved_src_mac(23 downto 16) <= MAC_RXD_IN;\r
+ elsif( (filter_current_state = REMOVE_SRC) and (remove_ctr = x"06") ) then\r
+ saved_src_mac(31 downto 24) <= MAC_RXD_IN;\r
+ elsif( (filter_current_state = REMOVE_SRC) and (remove_ctr = x"07") ) then\r
+ saved_src_mac(39 downto 32) <= MAC_RXD_IN;\r
+ elsif( (filter_current_state = REMOVE_SRC) and (remove_ctr = x"08") ) then\r
+ saved_src_mac(47 downto 40) <= MAC_RXD_IN;\r
+ else\r
+ saved_src_mac <= saved_src_mac;\r
+ end if;\r
+ end if;\r
+end process THE_SAVED_SRC_MAC_PROC;\r
+\r
+-- saves the frame type of the incoming frame for futher check\r
+THE_SAVED_FRAME_TYPE_PROC: process( CLK )\r
+begin\r
+ if( rising_edge(CLK) ) then\r
+ if ( filter_current_state = CLEANUP ) then\r
+ saved_frame_type <= (others => '0');\r
+ elsif( (filter_current_state = REMOVE_SRC) and (remove_ctr = x"09") ) then\r
+ saved_frame_type(15 downto 8) <= MAC_RXD_IN;\r
+ elsif( (filter_current_state = REMOVE_TYPE) and (remove_ctr = x"0a") ) then\r
+ saved_frame_type(7 downto 0) <= MAC_RXD_IN;\r
+ -- two more cases for VLAN tagged frame\r
+ elsif( (filter_current_state = REMOVE_VID) and (remove_ctr = x"0d") ) then\r
+ saved_frame_type(15 downto 8) <= MAC_RXD_IN;\r
+ elsif( (filter_current_state = REMOVE_VTYPE) and (remove_ctr = x"0e") ) then\r
+ saved_frame_type(7 downto 0) <= MAC_RXD_IN;\r
+ else\r
+ saved_frame_type <= saved_frame_type;\r
+ end if;\r
+ end if;\r
+end process THE_SAVED_FRAME_TYPE_PROC;\r
+\r
+THE_SAVED_SRC_IP_PROC: process( CLK )\r
+begin\r
+ if( rising_edge(CLK) ) then\r
+ if ( filter_current_state = CLEANUP ) then\r
+ saved_src_ip <= (others => '0');\r
+ elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"0a") ) then\r
+ saved_src_ip(7 downto 0) <= MAC_RXD_IN;\r
+ elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"0b") ) then\r
+ saved_src_ip(15 downto 8) <= MAC_RXD_IN;\r
+ elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"0c") ) then\r
+ saved_src_ip(23 downto 16) <= MAC_RXD_IN;\r
+ elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"0d") ) then\r
+ saved_src_ip(31 downto 24) <= MAC_RXD_IN;\r
+ else\r
+ saved_src_ip <= saved_src_ip;\r
+ end if;\r
+ end if;\r
+end process THE_SAVED_SRC_IP_PROC;\r
+\r
+THE_SAVED_DEST_IP_PROC: process( CLK )\r
+begin\r
+ if( rising_edge(CLK) ) then\r
+ if ( filter_current_state = CLEANUP ) then\r
+ saved_dest_ip <= (others => '0');\r
+ elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"0e") ) then\r
+ saved_dest_ip(7 downto 0) <= MAC_RXD_IN;\r
+ elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"0f") ) then\r
+ saved_dest_ip(15 downto 8) <= MAC_RXD_IN;\r
+ elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"10") ) then\r
+ saved_dest_ip(23 downto 16) <= MAC_RXD_IN;\r
+ elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"11") ) then\r
+ saved_dest_ip(31 downto 24) <= MAC_RXD_IN;\r
+ else\r
+ saved_dest_ip <= saved_dest_ip;\r
+ end if;\r
+ end if;\r
+end process THE_SAVED_DEST_IP_PROC;\r
+\r
+THE_SAVED_SRC_UDP_PROC: process( CLK )\r
+begin\r
+ if( rising_edge(CLK) ) then\r
+ if ( filter_current_state = CLEANUP ) then\r
+ saved_src_udp <= (others => '0');\r
+ elsif( (filter_current_state = REMOVE_UDP) and (remove_ctr = x"12") ) then\r
+ saved_src_udp(15 downto 8) <= MAC_RXD_IN;\r
+ elsif( (filter_current_state = REMOVE_UDP) and (remove_ctr = x"13") ) then\r
+ saved_src_udp(7 downto 0) <= MAC_RXD_IN;\r
+ else\r
+ saved_src_udp <= saved_src_udp;\r
+ end if;\r
+ end if;\r
+end process THE_SAVED_SRC_UDP_PROC;\r
+\r
+THE_SAVED_DEST_UDP_PROC: process( CLK )\r
+begin\r
+ if( rising_edge(CLK) ) then\r
+ if ( filter_current_state = CLEANUP ) then\r
+ saved_dest_udp <= (others => '0');\r
+ elsif( (filter_current_state = REMOVE_UDP) and (remove_ctr = x"14") ) then\r
+ saved_dest_udp(15 downto 8) <= MAC_RXD_IN;\r
+ elsif( (filter_current_state = REMOVE_UDP) and (remove_ctr = x"15") ) then\r
+ saved_dest_udp(7 downto 0) <= MAC_RXD_IN;\r
+ else\r
+ saved_dest_udp <= saved_dest_udp;\r
+ end if;\r
+ end if;\r
+end process THE_SAVED_DEST_UDP_PROC;\r
+\r
+-- saves VLAN id when tagged frame spotted\r
+THE_SAVED_VID_PROC: process( CLK )\r
+begin\r
+ if( rising_edge(CLK) ) then\r
+ if ( filter_current_state = CLEANUP ) then\r
+ saved_vid <= (others => '0');\r
+ elsif( (filter_current_state = REMOVE_TYPE) and (remove_ctr = x"0b") and (saved_frame_type = x"8100") ) then\r
+ saved_vid(15 downto 8) <= MAC_RXD_IN;\r
+ elsif( (filter_current_state = REMOVE_VID) and (remove_ctr = x"0c") ) then\r
+ saved_vid(7 downto 0) <= MAC_RXD_IN;\r
+ else\r
+ saved_vid <= saved_vid;\r
+ end if;\r
+ end if;\r
+end process THE_SAVED_VID_PROC;\r
+\r
+THE_TYPE_VALIDATOR: trb_net16_gbe_type_validator\r
+port map(\r
+ CLK => CLK,\r
+ RESET => RESET,\r
+ FRAME_TYPE_IN => saved_frame_type,\r
+ ALLOWED_TYPES_IN => FR_ALLOWED_TYPES_IN,\r
+ SAVED_VLAN_ID_IN => saved_vid,\r
+ VLAN_ID_IN => FR_VLAN_ID_IN,\r
+ -- IP level\r
+ IP_PROTOCOLS_IN => saved_proto,\r
+ ALLOWED_IP_PROTOCOLS_IN => FR_ALLOWED_IP_IN,\r
+ -- UDP level\r
+ UDP_PROTOCOL_IN => saved_dest_udp,\r
+ ALLOWED_UDP_PROTOCOLS_IN => FR_ALLOWED_UDP_IN,\r
+ --\r
+ VALID_OUT => frame_type_valid\r
+);\r
+\r
+THE_RECEIVE_FIFO: fifo_4096x9\r
+port map(\r
+ Data => rx_data,\r
+ WrClock => CLK,\r
+ RdClock => CLK,\r
+ WrEn => fifo_wr_en,\r
+ RdEn => FR_RD_EN_IN,\r
+ Reset => RESET,\r
+ RPReset => RESET,\r
+ Q => fr_q,\r
+ Empty => rec_fifo_empty,\r
+ Full => rec_fifo_full\r
+);\r
+\r
+-- killer ping\r
+THE_KILLER_PING_PROC: process( CLK )\r
+begin\r
+ if( rising_edge(CLK) ) then\r
+ if( (filter_current_state = SAVE_FRAME) and (saved_proto = x"01") and (saved_frame_type = x"0800") and\r
+ (rx_bytes_ctr = x"001A") and (rx_data(7 downto 0) = MY_TRBNET_ADDRESS_IN(7 downto 0)) and\r
+ (MAC_RXD_IN = MY_TRBNET_ADDRESS_IN(15 downto 8)) ) then\r
+ ISSUE_REBOOT_OUT <= '1';\r
+ else\r
+ ISSUE_REBOOT_OUT <= '0';\r
+ end if;\r
+ end if;\r
+end process;\r
+\r
+THE_RX_FIFO_SYNC: process( CLK )\r
+begin\r
+ if rising_edge(CLK) then\r
+\r
+ rx_data(8) <= MAC_RX_EOF_IN;\r
+ rx_data(7 downto 0) <= MAC_RXD_IN;\r
+\r
+ if( MAC_RX_EN_IN = '1' ) then\r
+ if ( filter_current_state = SAVE_FRAME ) then\r
+ fifo_wr_en <= '1';\r
+-- elsif( (filter_current_state = REMOVE_VTYPE) and (remove_ctr = x"0f") ) then\r
+-- fifo_wr_en <= '1';\r
+ elsif( (filter_current_state = DECIDE) and (frame_type_valid = '1') ) then\r
+ fifo_wr_en <= '1';\r
+ else\r
+ fifo_wr_en <= '0';\r
+ end if;\r
+ else\r
+ fifo_wr_en <= '0';\r
+ end if;\r
+\r
+ MAC_RX_FIFO_FULL_OUT <= rec_fifo_full;\r
+ end if;\r
+end process THE_RX_FIFO_SYNC;\r
+\r
+THE_SIZES_FIFO: fifo_512x32\r
+port map(\r
+ Data(15 downto 0) => rx_bytes_ctr,\r
+ Data(31 downto 16) => saved_frame_type,\r
+ WrClock => CLK,\r
+ RdClock => CLK,\r
+ WrEn => frame_valid_q,\r
+ RdEn => FR_GET_FRAME_IN,\r
+ Reset => RESET,\r
+ RPReset => RESET,\r
+ Q(15 downto 0) => fr_frame_size,\r
+ Q(31 downto 16) => fr_frame_proto,\r
+ Empty => sizes_fifo_empty,\r
+ Full => sizes_fifo_full\r
+);\r
+\r
+THE_MACS_FIFO: fifo_512x72\r
+port map(\r
+ Data(47 downto 0) => saved_src_mac,\r
+ Data(63 downto 48) => saved_src_udp,\r
+ Data(71 downto 64) => (others => '0'),\r
+ WrClock => CLK,\r
+ RdClock => CLK,\r
+ WrEn => frame_valid_q,\r
+ RdEn => FR_GET_FRAME_IN,\r
+ Reset => RESET,\r
+ RPReset => RESET,\r
+ Q(47 downto 0) => fr_src_mac,\r
+ Q(63 downto 48) => fr_src_udp,\r
+ Q(71 downto 64) => xxx0, --open,\r
+ Empty => open,\r
+ Full => open\r
+);\r
+\r
+THE_MACD_FIFO: fifo_512x72\r
+port map(\r
+ Data(47 downto 0) => saved_dest_mac,\r
+ Data(63 downto 48) => saved_dest_udp,\r
+ Data(71 downto 64) => (others => '0'),\r
+ WrClock => CLK,\r
+ RdClock => CLK,\r
+ WrEn => frame_valid_q,\r
+ RdEn => FR_GET_FRAME_IN,\r
+ Reset => RESET,\r
+ RPReset => RESET,\r
+ Q(47 downto 0) => fr_dest_mac,\r
+ Q(63 downto 48) => fr_dest_udp,\r
+ Q(71 downto 64) => xxx1, --open,\r
+ Empty => open,\r
+ Full => open\r
+);\r
+\r
+THE_IP_FIFO: fifo_512x72\r
+port map(\r
+ Data(31 downto 0) => saved_src_ip,\r
+ Data(63 downto 32) => saved_dest_ip,\r
+ Data(71 downto 64) => saved_proto,\r
+ WrClock => CLK,\r
+ RdClock => CLK,\r
+ WrEn => frame_valid_q,\r
+ RdEn => FR_GET_FRAME_IN,\r
+ Reset => RESET,\r
+ RPReset => RESET,\r
+ Q(31 downto 0) => fr_src_ip,\r
+ Q(63 downto 32) => fr_dest_ip,\r
+ Q(71 downto 64) => fr_ip_proto,\r
+ Empty => open,\r
+ Full => open\r
+);\r
+\r
+THE_SYNC_PROC: process( CLK )\r
+begin\r
+ if( rising_edge(CLK) ) then\r
+ FR_SRC_IP_ADDRESS_OUT <= fr_src_ip;\r
+ FR_DEST_IP_ADDRESS_OUT <= fr_dest_ip;\r
+ FR_IP_PROTOCOL_OUT <= fr_ip_proto;\r
+ FR_DEST_UDP_PORT_OUT <= fr_dest_udp;\r
+ FR_DEST_MAC_ADDRESS_OUT <= fr_dest_mac;\r
+ FR_SRC_MAC_ADDRESS_OUT <= fr_src_mac;\r
+ FR_SRC_UDP_PORT_OUT <= fr_src_udp;\r
+ FR_FRAME_PROTO_OUT <= fr_frame_proto;\r
+ FR_FRAME_SIZE_OUT <= fr_frame_size;\r
+ FR_Q_OUT <= fr_q;\r
+ --\r
+ delayed_frame_valid <= MAC_RX_EOF_IN;\r
+ delayed_frame_valid_q <= delayed_frame_valid;\r
+ end if;\r
+end process THE_SYNC_PROC;\r
+\r
+THE_FRAME_VALID_PROC: process( CLK )\r
+begin\r
+ if( rising_edge(CLK) ) then\r
+ if( (MAC_RX_EOF_IN = '1') and (ALLOW_RX_IN = '1') and (frame_type_valid = '1') ) then\r
+ frame_valid_q <= '1';\r
+ else\r
+ frame_valid_q <= '0';\r
+ end if;\r
+ end if;\r
+end process THE_FRAME_VALID_PROC;\r
+\r
+THE_RX_BYTES_CTR_PROC: process( CLK )\r
+begin\r
+ if( rising_edge(CLK) ) then\r
+ if ( (RESET = '1') or (delayed_frame_valid_q = '1') ) then\r
+ rx_bytes_ctr <= x"0001";\r
+ elsif( fifo_wr_en = '1' ) then\r
+ rx_bytes_ctr <= rx_bytes_ctr + 1;\r
+ end if;\r
+ end if;\r
+end process THE_RX_BYTES_CTR_PROC;\r
+\r
+THE_ERROR_FRAMES_CTR_PROC: process( CLK )\r
+begin\r
+ if( rising_edge(CLK) ) then\r
+ if ( RESET = '1' ) then\r
+ error_frames_ctr <= (others => '0');\r
+ elsif( MAC_RX_ER_IN = '1' ) then\r
+ error_frames_ctr <= error_frames_ctr + 1;\r
+ end if;\r
+ end if;\r
+end process THE_ERROR_FRAMES_CTR_PROC;\r
+\r
+FR_FRAME_VALID_OUT <= frame_valid_q when rising_edge(CLK);\r
+\r
+THE_RECEIVED_FRAMES_CTR: process( CLK )\r
+begin\r
+ if( rising_edge(CLK) ) then\r
+ if ( RESET = '1' ) then\r
+ dbg_rec_frames <= (others => '0');\r
+ elsif( MAC_RX_EOF_IN = '1' ) then\r
+ dbg_rec_frames <= dbg_rec_frames + 1;\r
+ end if;\r
+ end if;\r
+end process THE_RECEIVED_FRAMES_CTR;\r
+\r
+THE_DROPPED_FRAMES_CTR: process( CLK )\r
+begin\r
+ if( rising_edge(CLK) ) then\r
+ if ( RESET = '1' ) then\r
+ dbg_drp_frames <= (others => '0');\r
+ elsif( (filter_current_state = DECIDE) and (frame_type_valid = '0') ) then\r
+ dbg_drp_frames <= dbg_drp_frames + 1;\r
+ end if;\r
+ end if;\r
+end process THE_DROPPED_FRAMES_CTR;\r
+\r
+MONITOR_DROPPED_OUT <= std_logic_vector(dbg_drp_frames);\r
+MONITOR_RX_FRAMES_OUT <= std_logic_vector(dbg_rec_frames);\r
+MONITOR_RX_BYTES_OUT <= std_logic_vector(mon_rec_bytes);\r
+\r
+THE_MON_REC_BYTES_PROC: process(CLK)\r
+begin\r
+ if( rising_edge(CLK) ) then\r
+ if ( RESET = '1' ) then\r
+ mon_rec_bytes <= (others => '0');\r
+ elsif( fifo_wr_en = '1' ) then\r
+ mon_rec_bytes <= mon_rec_bytes + x"1";\r
+ else\r
+ mon_rec_bytes <= mon_rec_bytes;\r
+ end if;\r
+ end if;\r
+end process;\r
+\r
+end trb_net16_gbe_frame_receiver;\r
+\r
+\r
-- reacts to incoming gbe slow control commands
--
-
entity trb_net16_gbe_main_control is
generic(
RX_PATH_ENABLE : integer range 0 to 1 := 1;
DO_SIMULATION : integer range 0 to 1 := 0;
-
+ --
INCLUDE_READOUT : std_logic := '0';
INCLUDE_SLOWCTRL : std_logic := '0';
INCLUDE_DHCP : std_logic := '0';
INCLUDE_ARP : std_logic := '0';
INCLUDE_PING : std_logic := '0';
INCLUDE_FWD : std_logic := '0';
-
+ --
READOUT_BUFFER_SIZE : integer range 1 to 4;
SLOWCTRL_BUFFER_SIZE : integer range 1 to 4
);
CLK : in std_logic; -- system clock
CLK_125 : in std_logic;
RESET : in std_logic;
-
+ --
MC_LINK_OK_OUT : out std_logic;
MC_RESET_LINK_IN : in std_logic;
MC_IDLE_TOO_LONG_OUT : out std_logic;
RC_RD_EN_OUT : out std_logic;
RC_FRAME_SIZE_IN : in std_logic_vector(15 downto 0);
RC_FRAME_PROTO_IN : in std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
-
+ --
RC_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
RC_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
RC_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
RC_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
RC_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
RC_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
-
-- signals to/from transmit controller
TC_TRANSMIT_CTRL_OUT : out std_logic;
TC_DATA_OUT : out std_logic_vector(8 downto 0);
TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
TC_IDENT_OUT : out std_logic_vector(15 downto 0);
TC_TRANSMIT_DONE_IN : in std_logic;
-
-- signals to/from sgmii/gbe pcs_an_complete
PCS_AN_COMPLETE_IN : in std_logic;
-
-- signals to/from hub
GSC_CLK_IN : in std_logic;
GSC_INIT_DATAREADY_OUT : out std_logic;
GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0);
GSC_REPLY_READ_OUT : out std_logic;
GSC_BUSY_IN : in std_logic;
-
+ --
RESET_TRBNET_IN : in std_logic;
RESET_SCTRL_IN : in std_logic;
-- signal for data readout
SLV_ACK_OUT : out std_logic;
SLV_DATA_IN : in std_logic_vector(31 downto 0);
SLV_DATA_OUT : out std_logic_vector(31 downto 0);
-
+ --
CFG_GBE_ENABLE_IN : in std_logic;
CFG_IPU_ENABLE_IN : in std_logic;
CFG_MULT_ENABLE_IN : in std_logic;
CFG_MAX_QUEUE_IN : in std_logic_vector(15 downto 0);
CFG_MAX_SUBS_IN_QUEUE_IN : in std_logic_vector(15 downto 0);
CFG_MAX_SINGLE_SUB_IN : in std_logic_vector(15 downto 0);
-
CFG_ADDITIONAL_HDR_IN : in std_logic;
CFG_MAX_REPLY_SIZE_IN : in std_logic_vector(31 downto 0);
-
CFG_AUTO_THROTTLE_IN : in std_logic;
CFG_THROTTLE_PAUSE_IN : in std_logic_vector(15 downto 0);
-
MAKE_RESET_OUT : out std_logic;
-
-- Forwarder
FWD_DST_MAC_IN : in std_logic_vector(47 downto 0);
FWD_DST_IP_IN : in std_logic_vector(31 downto 0);
FWD_EOP_IN : in std_logic;
FWD_READY_OUT : out std_logic;
FWD_FULL_OUT : out std_logic;
-
-- signal to/from Host interface of TriSpeed MAC
TSM_HADDR_OUT : out std_logic_vector(7 downto 0);
TSM_HDATA_OUT : out std_logic_vector(7 downto 0);
TSM_HDATA_EN_N_IN : in std_logic;
TSM_RX_STAT_VEC_IN : in std_logic_vector(31 downto 0);
TSM_RX_STAT_EN_IN : in std_logic;
-
+ --
MAC_READY_CONF_IN : in std_logic;
MAC_RECONF_OUT : out std_logic;
-
+ --
MONITOR_SELECT_REC_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
MONITOR_SELECT_REC_BYTES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
MONITOR_SELECT_SENT_BYTES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
MONITOR_SELECT_DROP_IN_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
MONITOR_SELECT_DROP_OUT_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
MONITOR_SELECT_GEN_DBG_OUT : out std_logic_vector(2 * c_MAX_PROTOCOLS * 32 - 1 downto 0);
-
+ --
DATA_HIST_OUT : out hist_array;
SCTRL_HIST_OUT : out hist_array;
-
+ --
DEBUG_OUT : out std_logic_vector(63 downto 0)
);
end trb_net16_gbe_main_control;
proto_select <= RC_FRAME_PROTO_IN when disable_redirect = '0' else (others => '0');
-- gk 07.11.11
- DISABLE_REDIRECT_PROC : process(CLK)
+ DISABLE_REDIRECT_PROC: process( CLK )
begin
- if rising_edge(CLK) then
- if (RESET = '1') then
+ if( rising_edge(CLK) ) then
+ if ( RESET = '1' ) then
disable_redirect <= '0';
- elsif (redirect_current_state = CHECK_TYPE) then
- if (link_current_state /= ACTIVE and link_current_state /= GET_ADDRESS) then
+ elsif( redirect_current_state = CHECK_TYPE ) then
+ if ( (link_current_state /= ACTIVE) and (link_current_state /= GET_ADDRESS) ) then
disable_redirect <= '1';
- elsif (link_current_state = GET_ADDRESS and RC_FRAME_PROTO_IN /= "10") then
+ elsif( (link_current_state = GET_ADDRESS) and (RC_FRAME_PROTO_IN /= "10") ) then -- x"10" ?!?!?
disable_redirect <= '1';
else
disable_redirect <= '0';
end process DISABLE_REDIRECT_PROC;
-- warning
- SYNC_PROC : process(CLK)
+ SYNC_PROC: process( CLK )
begin
- if rising_edge(CLK) then
+ if( rising_edge(CLK) ) then
rc_data_local <= RC_DATA_IN;
end if;
end process SYNC_PROC;
- REDIRECT_MACHINE_PROC : process(RESET, CLK)
+ REDIRECT_MACHINE_PROC: process( CLK )
begin
- if RESET = '1' then
- redirect_current_state <= IDLE;
- elsif rising_edge(CLK) then
- if RX_PATH_ENABLE = 1 then
+ if( rising_edge(CLK) ) then
+ if ( RESET = '1' ) then
+ redirect_current_state <= IDLE;
+ elsif( RX_PATH_ENABLE = 1 ) then
redirect_current_state <= redirect_next_state;
else
redirect_current_state <= IDLE;
case redirect_current_state is
when IDLE =>
redirect_state <= x"1";
- if (RC_FRAME_WAITING_IN = '1') then
+ if( RC_FRAME_WAITING_IN = '1' ) then
redirect_next_state <= CHECK_TYPE;
else
redirect_next_state <= IDLE;
when CHECK_TYPE =>
redirect_state <= x"2";
- if (link_current_state = ACTIVE) then
+ if ( link_current_state = ACTIVE ) then
redirect_next_state <= CHECK_BUSY;
- elsif (link_current_state = GET_ADDRESS and RC_FRAME_PROTO_IN = "10") then
+ elsif( (link_current_state = GET_ADDRESS) and (RC_FRAME_PROTO_IN = "10") ) then
redirect_next_state <= CHECK_BUSY;
else
redirect_next_state <= DROP;
when DROP =>
redirect_state <= x"3";
- if (loaded_bytes_ctr = RC_FRAME_SIZE_IN - x"1") then
+ if( loaded_bytes_ctr = RC_FRAME_SIZE_IN - x"1" ) then
redirect_next_state <= WAIT_ONE;
else
redirect_next_state <= DROP;
when CHECK_BUSY =>
redirect_state <= x"4";
- if (or_all(ps_busy and RC_FRAME_PROTO_IN) = '0') then
+ if( or_all(ps_busy and RC_FRAME_PROTO_IN) = '0' ) then
redirect_next_state <= LOAD;
else
redirect_next_state <= BUSY;
when LOAD =>
redirect_state <= x"5";
- if (loaded_bytes_ctr = RC_FRAME_SIZE_IN - x"1") then
+ if( loaded_bytes_ctr = RC_FRAME_SIZE_IN - x"1" ) then
redirect_next_state <= WAIT_ONE;
else
redirect_next_state <= LOAD;
when BUSY =>
redirect_state <= x"6";
- if (or_all(ps_busy and RC_FRAME_PROTO_IN) = '0') then
+ if( or_all(ps_busy and RC_FRAME_PROTO_IN) = '0' ) then
redirect_next_state <= LOAD;
else
redirect_next_state <= BUSY;
LOADED_BYTES_CTR_PROC : process(CLK)
begin
if rising_edge(CLK) then
- if (redirect_current_state = IDLE) then
+ if ( redirect_current_state = IDLE) then
loaded_bytes_ctr <= (others => '0');
- elsif (redirect_current_state = LOAD or redirect_current_state = DROP) and (rc_rd_en = '1') then
+ elsif( ((redirect_current_state = LOAD) or (redirect_current_state = DROP)) and (rc_rd_en = '1') )then
loaded_bytes_ctr <= loaded_bytes_ctr + x"1";
else
loaded_bytes_ctr <= loaded_bytes_ctr;
signal load_current_state, load_next_state : load_states;
attribute syn_encoding of load_current_state : signal is "onehot";
-signal frames_received_ctr : std_logic_vector(31 downto 0);
-signal frames_readout_ctr : std_logic_vector(31 downto 0);
-signal bytes_rec_ctr : std_logic_vector(31 downto 0);
+signal frames_received_ctr : unsigned(31 downto 0);
+signal frames_readout_ctr : unsigned(31 downto 0);
+signal bytes_rec_ctr : unsigned(31 downto 0);
signal state : std_logic_vector(3 downto 0);
signal proto_code : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
when READY => -- wait for reading out the whole frame
state <= x"3";
- if (RC_LOADING_DONE_IN = '1') then
+ if( RC_LOADING_DONE_IN = '1' ) then
load_next_state <= IDLE;
else
load_next_state <= READY;
if ( RESET = '1' ) then
frames_received_ctr <= (others => '0');
elsif( FR_FRAME_VALID_IN = '1' ) then
- frames_received_ctr <= frames_received_ctr + x"1";
+ frames_received_ctr <= frames_received_ctr + 1;
else
frames_received_ctr <= frames_received_ctr;
end if;
if ( RESET = '1' ) then
frames_readout_ctr <= (others => '0');
elsif( RC_LOADING_DONE_IN = '1' ) then
- frames_readout_ctr <= frames_readout_ctr + x"1";
+ frames_readout_ctr <= frames_readout_ctr + 1;
else
frames_readout_ctr <= frames_readout_ctr;
end if;
if ( RESET = '1' ) then
bytes_rec_ctr <= (others => '0');
elsif( FR_FRAME_VALID_IN = '1' ) then
- bytes_rec_ctr <= bytes_rec_ctr + FR_FRAME_SIZE_IN;
+ bytes_rec_ctr <= bytes_rec_ctr + unsigned(FR_FRAME_SIZE_IN);
else
bytes_rec_ctr <= bytes_rec_ctr;
end if;
SAVED_PROTO_PROC : process( CLK )
begin
if( rising_edge(CLK) ) then
- if (load_current_state = READY) then
+ if( load_current_state = READY ) then
if( and_all(proto_code) = '0' ) then
saved_proto <= proto_code;
else
end process SAVED_PROTO_PROC;
end trb_net16_gbe_receive_control;
-
-
entity trb_net16_gbe_type_validator is
port (
- CLK : in std_logic; -- 125MHz clock input
- RESET : in std_logic;
- -- ethernet level
- FRAME_TYPE_IN : in std_logic_vector(15 downto 0); -- recovered frame type
- SAVED_VLAN_ID_IN : in std_logic_vector(15 downto 0); -- recovered vlan id
- ALLOWED_TYPES_IN : in std_logic_vector(31 downto 0); -- signal from gbe_setup
- VLAN_ID_IN : in std_logic_vector(31 downto 0); -- two values from gbe setup
-
- -- IP level
- IP_PROTOCOLS_IN : in std_logic_vector(7 downto 0);
- ALLOWED_IP_PROTOCOLS_IN : in std_logic_vector(31 downto 0);
-
- -- UDP level
- UDP_PROTOCOL_IN : in std_logic_vector(15 downto 0);
- ALLOWED_UDP_PROTOCOLS_IN : in std_logic_vector(31 downto 0);
-
- VALID_OUT : out std_logic
+ CLK : in std_logic; -- 125MHz clock input
+ RESET : in std_logic;
+ -- ethernet level
+ FRAME_TYPE_IN : in std_logic_vector(15 downto 0); -- recovered frame type
+ SAVED_VLAN_ID_IN : in std_logic_vector(15 downto 0); -- recovered vlan id
+ ALLOWED_TYPES_IN : in std_logic_vector(31 downto 0); -- signal from gbe_setup
+ VLAN_ID_IN : in std_logic_vector(31 downto 0); -- two values from gbe setup
+ -- IP level
+ IP_PROTOCOLS_IN : in std_logic_vector(7 downto 0);
+ ALLOWED_IP_PROTOCOLS_IN : in std_logic_vector(31 downto 0);
+ -- UDP level
+ UDP_PROTOCOL_IN : in std_logic_vector(15 downto 0);
+ ALLOWED_UDP_PROTOCOLS_IN : in std_logic_vector(31 downto 0);
+ -- result
+ VALID_OUT : out std_logic
);
end trb_net16_gbe_type_validator;
signal zeros : std_logic_vector(c_MAX_FRAME_TYPES - 1 downto 0);
begin
-
- zeros <= (others => '0');
+
+ zeros <= (others => '0');
--- DO NOT TOUCH
+-- checks for allowed IP protocols (UDP, ICMP)
IP_RESULTS_GEN : for i in 0 to c_MAX_IP_PROTOCOLS - 1 generate
process(CLK)
begin
- if rising_edge(CLK) then
- if IP_PROTOCOLS(i) = IP_PROTOCOLS_IN and ALLOWED_IP_PROTOCOLS_IN(i) = '1' then
- ip_result(i) <= '1';
- else
- ip_result(i) <= '0';
- end if;
- end if;
+ if( rising_edge(CLK) ) then
+ if( (IP_PROTOCOLS(i) = IP_PROTOCOLS_IN) and (ALLOWED_IP_PROTOCOLS_IN(i) = '1') )then
+ ip_result(i) <= '1';
+ else
+ ip_result(i) <= '0';
+ end if;
+ end if;
end process;
end generate IP_RESULTS_GEN;
+-- checks for allowed UDP destination ports (DHCP, SCTRL)
UDP_RESULTS_GEN : for i in 0 to c_MAX_UDP_PROTOCOLS - 1 generate
process(CLK)
begin
- if rising_edge(CLK) then
- if UDP_PROTOCOLS(i) = UDP_PROTOCOL_IN and ALLOWED_UDP_PROTOCOLS_IN(i) = '1' then
- udp_result(i) <= '1';
- else
- udp_result(i) <= '0';
- end if;
- end if;
+ if( rising_edge(CLK) ) then
+ if( (UDP_PROTOCOLS(i) = UDP_PROTOCOL_IN) and (ALLOWED_UDP_PROTOCOLS_IN(i) = '1') ) then
+ udp_result(i) <= '1';
+ else
+ udp_result(i) <= '0';
+ end if;
+ end if;
end process;
end generate UDP_RESULTS_GEN;
-
-RESULT_GEN : for i in 0 to c_MAX_FRAME_TYPES - 1 generate
+-- checks for allowed frame type (IPv4, ARP)
+FRAME_RESULTS_GEN : for i in 0 to c_MAX_FRAME_TYPES - 1 generate
process(CLK)
begin
- if rising_edge(CLK) then
- if FRAME_TYPES(i) = FRAME_TYPE_IN and ALLOWED_TYPES_IN(i) = '1' then
- result(i) <= '1';
- else
- result(i) <= '0';
- end if;
- end if;
+ if( rising_edge(CLK) ) then
+ if( (FRAME_TYPES(i) = FRAME_TYPE_IN) and (ALLOWED_TYPES_IN(i) = '1') ) then
+ result(i) <= '1';
+ else
+ result(i) <= '0';
+ end if;
+ end if;
end process;
-end generate RESULT_GEN;
+end generate FRAME_RESULTS_GEN;
PARTIALLY_VALID_PROC : process(CLK)
begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- partially_valid <= '0';
- elsif (FRAME_TYPE_IN = x"0800") then -- ip frame
- if (IP_PROTOCOLS_IN = x"11") then -- in case of udp inside ip
- partially_valid <= or_all(udp_result);
- elsif (IP_PROTOCOLS_IN = x"01" or IP_PROTOCOLS_IN = x"dd" or IP_PROTOCOLS_IN = x"ee") then -- in case of ICMP
- partially_valid <= '1';
- else -- do not accept other protocols than udp and icmp inside ip
- partially_valid <= '0';
- end if;
- elsif (result /= zeros) then-- other frame
- partially_valid <= '1';
- else
- partially_valid <= '0';
- end if;
- end if;
+ if( rising_edge(CLK) ) then
+ if ( RESET = '1' ) then
+ partially_valid <= '0';
+ elsif( FRAME_TYPE_IN = x"0800" ) then -- ip frame
+ if ( IP_PROTOCOLS_IN = x"11" ) then -- in case of udp inside ip
+ partially_valid <= or_all(udp_result);
+ elsif( (IP_PROTOCOLS_IN = x"01") or (IP_PROTOCOLS_IN = x"dd") or (IP_PROTOCOLS_IN = x"ee") ) then -- in case of ICMP
+ partially_valid <= '1';
+ else -- do not accept other protocols than udp and icmp inside ip
+ partially_valid <= '0';
+ end if;
+ elsif( result /= zeros ) then-- other frame
+ partially_valid <= '1';
+ else
+ partially_valid <= '0';
+ end if;
+ end if;
end process PARTIALLY_VALID_PROC;
VALID_OUT_PROC : process(CLK)
begin
- if rising_edge(CLK) then
- if (partially_valid = '1') then
- if (SAVED_VLAN_ID_IN = x"0000") then
- VALID_OUT <= '1';
- elsif (VLAN_ID_IN = x"0000_0000") then
- VALID_OUT <= '0';
- elsif (SAVED_VLAN_ID_IN = VLAN_ID_IN(15 downto 0) or SAVED_VLAN_ID_IN = VLAN_ID_IN(31 downto 16)) then
- VALID_OUT <= '1';
- else
- VALID_OUT <= '0';
- end if;
- else
- VALID_OUT <= '0';
- end if;
- end if;
+ if rising_edge(CLK) then
+ if( partially_valid = '1' ) then
+ if ( SAVED_VLAN_ID_IN = x"0000" ) then
+ VALID_OUT <= '1';
+ elsif( VLAN_ID_IN = x"0000_0000" ) then
+ VALID_OUT <= '0';
+ elsif( (SAVED_VLAN_ID_IN = VLAN_ID_IN(15 downto 0)) or (SAVED_VLAN_ID_IN = VLAN_ID_IN(31 downto 16)) ) then
+ VALID_OUT <= '1';
+ else
+ VALID_OUT <= '0';
+ end if;
+ else
+ VALID_OUT <= '0';
+ end if;
+ end if;
end process VALID_OUT_PROC;
end trb_net16_gbe_type_validator;
component trb_net16_gbe_type_validator is
port (
- CLK : in std_logic;
- RESET : in std_logic;
- FRAME_TYPE_IN : in std_logic_vector(15 downto 0); -- recovered frame type
- SAVED_VLAN_ID_IN : in std_logic_vector(15 downto 0); -- recovered vlan id
- ALLOWED_TYPES_IN : in std_logic_vector(31 downto 0); -- signal from gbe_setup
- VLAN_ID_IN : in std_logic_vector(31 downto 0); -- two values from gbe setup
-
- -- IP level
- IP_PROTOCOLS_IN : in std_logic_vector(7 downto 0);
- ALLOWED_IP_PROTOCOLS_IN : in std_logic_vector(31 downto 0);
-
- -- UDP level
- UDP_PROTOCOL_IN : in std_logic_vector(15 downto 0);
- ALLOWED_UDP_PROTOCOLS_IN : in std_logic_vector(31 downto 0);
-
- VALID_OUT : out std_logic
+ CLK : in std_logic; -- 125MHz clock input
+ RESET : in std_logic;
+ -- ethernet level
+ FRAME_TYPE_IN : in std_logic_vector(15 downto 0); -- recovered frame type
+ ALLOWED_TYPES_IN : in std_logic_vector(31 downto 0); -- signal from gbe_setup
+ SAVED_VLAN_ID_IN : in std_logic_vector(15 downto 0); -- recovered vlan id
+ VLAN_ID_IN : in std_logic_vector(31 downto 0); -- two values from gbe setup
+ -- IP level
+ IP_PROTOCOLS_IN : in std_logic_vector(7 downto 0);
+ ALLOWED_IP_PROTOCOLS_IN : in std_logic_vector(31 downto 0);
+ -- UDP level
+ UDP_PROTOCOL_IN : in std_logic_vector(15 downto 0);
+ ALLOWED_UDP_PROTOCOLS_IN : in std_logic_vector(31 downto 0);
+ -- result
+ VALID_OUT : out std_logic
);
end component;
FRAMES_RECEIVED_OUT : out std_logic_vector(31 downto 0);
BYTES_RECEIVED_OUT : out std_logic_vector(31 downto 0);
-
DEBUG_OUT : out std_logic_vector(63 downto 0)
);
end component;
--
MONITOR_RX_BYTES_OUT : out std_logic_vector(31 downto 0);
MONITOR_RX_FRAMES_OUT : out std_logic_vector(31 downto 0);
- MONITOR_DROPPED_OUT : out std_logic_vector(31 downto 0)
+ MONITOR_DROPPED_OUT : out std_logic_vector(31 downto 0);
+ DEBUG_OUT : out std_logic_vector(15 downto 0)
);
end component;
use work.trb_net_std.all;
package trb_net_gbe_protocols is
- type hist_array is array (31 downto 0) of std_logic_vector(31 downto 0);
-
- --signal g_SIMULATE : integer range 0 to 1 := 0;
-
- ---- g_MY_IP is being set by DHCP Response Constructor
- --signal g_MY_IP : std_logic_vector(31 downto 0);
- ---- g_MY_MAC is being set by Main Controller
- --signal g_MY_MAC : std_logic_vector(47 downto 0) := x"001122334455";
-
- constant c_MAX_FRAME_TYPES : integer range 1 to 16 := 2;
- constant c_MAX_PROTOCOLS : integer range 1 to 16 := 6; --5; --4; --5;
- constant c_MAX_IP_PROTOCOLS : integer range 1 to 16 := 2;
- constant c_MAX_UDP_PROTOCOLS : integer range 1 to 16 := 4;
-
- type frame_types_a is array (c_MAX_FRAME_TYPES - 1 downto 0) of std_logic_vector(15 downto 0);
- constant FRAME_TYPES : frame_types_a := (x"0800", x"0806");
- -- IPv4, ARP
-
- type ip_protos_a is array (c_MAX_IP_PROTOCOLS - 1 downto 0) of std_logic_vector(7 downto 0);
- constant IP_PROTOCOLS : ip_protos_a := (x"11", x"01");
- -- UDP, ICMP
-
- -- this are the destination ports of the incoming packet
- type udp_protos_a is array (c_MAX_UDP_PROTOCOLS - 1 downto 0) of std_logic_vector(15 downto 0);
- constant UDP_PROTOCOLS : udp_protos_a := (x"0044", x"6590", x"7530", x"7531"); --x"6590", x"7530", x"7531"); --x"61a8", x"7530", x"7531");
- -- DHCP client, SCTRL, STATs
-
--- component trb_net16_gbe_response_constructor_Forward is
--- port (
--- CLK : in std_logic; -- system clock
--- RESET : in std_logic;
---
--- -- INTERFACE
--- MY_MAC_IN : in std_logic_vector(47 downto 0);
--- MY_IP_IN : in std_logic_vector(31 downto 0);
--- PS_DATA_IN : in std_logic_vector(8 downto 0);
--- PS_WR_EN_IN : in std_logic;
--- PS_ACTIVATE_IN : in std_logic;
--- PS_RESPONSE_READY_OUT : out std_logic;
--- PS_BUSY_OUT : out std_logic;
--- PS_SELECTED_IN : in std_logic;
--- PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
--- PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
--- PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
--- PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
--- PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
--- PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
---
--- TC_RD_EN_IN : in std_logic;
--- TC_DATA_OUT : out std_logic_vector(8 downto 0);
--- TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
--- TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
--- TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
--- TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
--- TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
--- TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
--- TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
--- TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
--- TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
---
--- TC_BUSY_IN : in std_logic;
---
--- RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0);
--- SENT_FRAMES_OUT : out std_logic_vector(15 downto 0);
--- -- END OF INTERFACE
---
--- FWD_DATA_IN : in std_logic_vector(7 downto 0);
--- FWD_DATA_VALID_IN : in std_logic;
--- FWD_SOP_IN : in std_logic;
--- FWD_EOP_IN : in std_logic;
--- FWD_READY_OUT : out std_logic;
--- FWD_FULL_OUT : out std_logic;
---
--- -- debug
--- DEBUG_OUT : out std_logic_vector(31 downto 0)
--- );
--- end component;
+ type hist_array is array (31 downto 0) of std_logic_vector(31 downto 0);
+
+ -- number of "protocols" supported
+ constant c_MAX_PROTOCOLS : integer range 1 to 16 := 6;
+ -- READOUT, SLOWCTRL, PING, ARP, DHCP, FWD ???
+
+ constant c_MAX_FRAME_TYPES : integer range 1 to 16 := 2;
+ type frame_types_a is array (c_MAX_FRAME_TYPES - 1 downto 0) of std_logic_vector(15 downto 0);
+ constant FRAME_TYPES : frame_types_a := (x"0800", x"0806");
+ -- IPv4, ARP
+
+ constant c_MAX_IP_PROTOCOLS : integer range 1 to 16 := 2;
+ type ip_protos_a is array (c_MAX_IP_PROTOCOLS - 1 downto 0) of std_logic_vector(7 downto 0);
+ constant IP_PROTOCOLS : ip_protos_a := (x"11", x"01");
+ -- UDP, ICMP
+
+ -- this are the destination ports of the incoming packet
+ constant c_MAX_UDP_PROTOCOLS : integer range 1 to 16 := 4;
+ type udp_protos_a is array (c_MAX_UDP_PROTOCOLS - 1 downto 0) of std_logic_vector(15 downto 0);
+ constant UDP_PROTOCOLS : udp_protos_a := (x"0044", x"6590", x"7530", x"7531");
+ -- DHCP client, SCTRL, STATs
+
+-------------------------------------------------------------------------------------------------------
+-------------------------------------------------------------------------------------------------------
+-------------------------------------------------------------------------------------------------------
+-------------------------------------------------------------------------------------------------------
component trb_net16_gbe_response_constructor_ARP is
generic(STAT_ADDRESS_BASE : integer := 0
TC_IDENT_OUT <= x"1" & sent_frames(11 downto 0);
-
-- **** statistics
--REC_FRAMES_PROC : process(CLK)
--begin
end if;
end if;
end process SENT_FRAMES_PROC;
---
---RECEIVED_FRAMES_OUT <= rec_frames;
---SENT_FRAMES_OUT <= sent_frames;
---
---STATS_MACHINE_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- stats_current_state <= IDLE;
--- else
--- stats_current_state <= stats_next_state;
--- end if;
--- end if;
---end process STATS_MACHINE_PROC;
---
---STATS_MACHINE : process(stats_current_state, STAT_DATA_ACK_IN, PS_DATA_IN, construct_current_state, receive_current_state)
---begin
---
--- case (stats_current_state) is
---
--- when IDLE =>
--- if (receive_current_state = SAVE_VALUES and PS_DATA_IN(8) = '1') or (construct_current_state = CLEANUP) or (receive_current_state = DISCARD and PS_DATA_IN(8) = '1') then
--- stats_next_state <= LOAD_SENT;
--- else
--- stats_next_state <= IDLE;
--- end if;
---
--- when LOAD_SENT =>
--- if (STAT_DATA_ACK_IN = '1') then
--- stats_next_state <= LOAD_RECEIVED;
--- else
--- stats_next_state <= LOAD_SENT;
--- end if;
---
--- when LOAD_RECEIVED =>
--- if (STAT_DATA_ACK_IN = '1') then
--- stats_next_state <= LOAD_DISCARDED;
--- else
--- stats_next_state <= LOAD_RECEIVED;
--- end if;
---
--- when LOAD_DISCARDED =>
--- if (STAT_DATA_ACK_IN = '1') then
--- stats_next_state <= CLEANUP;
--- else
--- stats_next_state <= LOAD_DISCARDED;
--- end if;
---
--- when CLEANUP =>
--- stats_next_state <= IDLE;
---
--- end case;
---
---end process STATS_MACHINE;
---
---SELECTOR : process(CLK)
---begin
--- if rising_edge(CLK) then
--- case(stats_current_state) is
---
--- when LOAD_SENT =>
--- stat_data_temp <= x"0101" & sent_frames;
--- STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE, 8));
---
--- when LOAD_RECEIVED =>
--- stat_data_temp <= x"0102" & rec_frames;
--- STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE + 1, 8));
---
--- when LOAD_DISCARDED =>
--- stat_data_temp <= x"0103" & discarded_ctr;
--- STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE + 2, 8));
---
--- when others =>
--- stat_data_temp <= (others => '0');
--- STAT_ADDR_OUT <= (others => '0');
---
--- end case;
--- end if;
---
---end process SELECTOR;
---
---STAT_DATA_OUT(7 downto 0) <= stat_data_temp(31 downto 24);
---STAT_DATA_OUT(15 downto 8) <= stat_data_temp(23 downto 16);
---STAT_DATA_OUT(23 downto 16) <= stat_data_temp(15 downto 8);
---STAT_DATA_OUT(31 downto 24) <= stat_data_temp(7 downto 0);
---
---STAT_SYNC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (stats_current_state /= IDLE and stats_current_state /= CLEANUP) then
--- STAT_DATA_RDY_OUT <= '1';
--- else
--- STAT_DATA_RDY_OUT <= '0';
--- end if;
--- end if;
---end process STAT_SYNC;
--- ****
-
-- **** debug
process(CLK)
end if;
end process;
---DEBUG_OUT(15 downto 12) <= (others => '0');
---DEBUG_OUT(31 downto 16) <= discarded_ctr;
---
---DISCARDED_CTR_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- discarded_ctr <= (others => '0');
--- elsif (receive_current_state = DISCARD and PS_DATA_IN(8) = '1') then
--- discarded_ctr <= discarded_ctr + x"1";
--- end if;
--- end if;
---end process DISCARDED_CTR_PROC;
-- ****
end trb_net16_gbe_response_constructor_DHCP;
FIFO_DATA_IN : in std_logic_vector(4 * 9 - 1 downto 0) := (others => '0');
FRAME_START_IN : in std_logic_vector(3 downto 0) := (others => '0');
-- SFP Connection
- SD_PRSNT_N_IN : in std_logic_vector(3 downto 0) := (others => '0');
- SD_LOS_IN : in std_logic_vector(3 downto 0) := (others => '0');
+ SD_PRSNT_N_IN : in std_logic_vector(3 downto 0) := (others => '1');
+ SD_LOS_IN : in std_logic_vector(3 downto 0) := (others => '1');
SD_TXDIS_OUT : out std_logic_vector(3 downto 0);
-- SerDes control
TX_PLOL_LOL_OUT : out std_logic;
--- /dev/null
+[Device]
+Family=ecp5um5g
+PartType=LFE5UM5G-85F
+PartName=LFE5UM5G-85F-8BG381C
+SpeedGrade=8
+Package=CABGA381
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO
+CoreRevision=5.1
+ModuleName=fifo_4k_9
+SourceFormat=vhdl
+ParameterFileVersion=1.0
+Date=07/13/2022
+Time=09:12:48
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=4096
+Width=9
+regout=0
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=1
+PfMode=Static - Single Threshold
+PfAssert=4092
+PfDeassert=506
+Reset=Async
+Reset1=Async
+RDataCount=0
+EnECC=0
+EnFWFT=0
+
+[Command]
+cmd_line= -w -n fifo_4k_9 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00g -type ebfifo -sync_mode -depth 4096 -width 9 -no_enable -pe -1 -pf 4092 -reset_rel ASYNC
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454
+-- Module Version: 5.1
+--/opt/lattice/diamond/3.12/ispfpga/bin/lin64/scuba -w -n fifo_4k_9 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00g -type ebfifo -sync_mode -depth 4096 -width 9 -no_enable -pe -1 -pf 4092 -reset_rel ASYNC -fdc /home/michaelb/DEEPSEA/ECP5-5G/fifos/fifo_4k_9/fifo_4k_9.fdc
+
+-- Wed Jul 13 09:12:50 2022
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity fifo_4k_9 is
+ port (
+ Data: in std_logic_vector(8 downto 0);
+ Clock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ Q: out std_logic_vector(8 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic;
+ AlmostFull: out std_logic);
+end fifo_4k_9;
+
+architecture Structure of fifo_4k_9 is
+
+ -- internal signal declarations
+ signal invout_2: std_logic;
+ signal invout_1: std_logic;
+ signal rden_i_inv: std_logic;
+ signal invout_0: std_logic;
+ signal r_nw_inv: std_logic;
+ signal r_nw: std_logic;
+ signal fcnt_en_inv: std_logic;
+ signal fcnt_en: std_logic;
+ signal empty_i: std_logic;
+ signal empty_d: std_logic;
+ signal full_i: std_logic;
+ signal full_d: std_logic;
+ signal ifcount_0: std_logic;
+ signal ifcount_1: std_logic;
+ signal bdcnt_bctr_ci: std_logic;
+ signal ifcount_2: std_logic;
+ signal ifcount_3: std_logic;
+ signal co0: std_logic;
+ signal ifcount_4: std_logic;
+ signal ifcount_5: std_logic;
+ signal co1: std_logic;
+ signal ifcount_6: std_logic;
+ signal ifcount_7: std_logic;
+ signal co2: std_logic;
+ signal ifcount_8: std_logic;
+ signal ifcount_9: std_logic;
+ signal co3: std_logic;
+ signal ifcount_10: std_logic;
+ signal ifcount_11: std_logic;
+ signal co4: std_logic;
+ signal ifcount_12: std_logic;
+ signal co6: std_logic;
+ signal co5: std_logic;
+ signal cmp_ci: std_logic;
+ signal rden_i: std_logic;
+ signal co0_1: std_logic;
+ signal co1_1: std_logic;
+ signal co2_1: std_logic;
+ signal co3_1: std_logic;
+ signal co4_1: std_logic;
+ signal co5_1: std_logic;
+ signal cmp_le_1: std_logic;
+ signal cmp_le_1_c: std_logic;
+ signal cmp_ci_1: std_logic;
+ signal co0_2: std_logic;
+ signal co1_2: std_logic;
+ signal co2_2: std_logic;
+ signal co3_2: std_logic;
+ signal co4_2: std_logic;
+ signal wren_i: std_logic;
+ signal co5_2: std_logic;
+ signal wren_i_inv: std_logic;
+ signal cmp_ge_d1: std_logic;
+ signal cmp_ge_d1_c: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal w_ctr_ci: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal co0_3: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_3: std_logic;
+ signal iwcount_4: std_logic;
+ signal iwcount_5: std_logic;
+ signal co1_3: std_logic;
+ signal wcount_4: std_logic;
+ signal wcount_5: std_logic;
+ signal iwcount_6: std_logic;
+ signal iwcount_7: std_logic;
+ signal co2_3: std_logic;
+ signal wcount_6: std_logic;
+ signal wcount_7: std_logic;
+ signal iwcount_8: std_logic;
+ signal iwcount_9: std_logic;
+ signal co3_3: std_logic;
+ signal wcount_8: std_logic;
+ signal wcount_9: std_logic;
+ signal iwcount_10: std_logic;
+ signal iwcount_11: std_logic;
+ signal co4_3: std_logic;
+ signal wcount_10: std_logic;
+ signal wcount_11: std_logic;
+ signal iwcount_12: std_logic;
+ signal co6_1: std_logic;
+ signal co5_3: std_logic;
+ signal wcount_12: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal r_ctr_ci: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal co0_4: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal ircount_4: std_logic;
+ signal ircount_5: std_logic;
+ signal co1_4: std_logic;
+ signal rcount_4: std_logic;
+ signal rcount_5: std_logic;
+ signal ircount_6: std_logic;
+ signal ircount_7: std_logic;
+ signal co2_4: std_logic;
+ signal rcount_6: std_logic;
+ signal rcount_7: std_logic;
+ signal ircount_8: std_logic;
+ signal ircount_9: std_logic;
+ signal co3_4: std_logic;
+ signal rcount_8: std_logic;
+ signal rcount_9: std_logic;
+ signal ircount_10: std_logic;
+ signal ircount_11: std_logic;
+ signal co4_4: std_logic;
+ signal rcount_10: std_logic;
+ signal rcount_11: std_logic;
+ signal ircount_12: std_logic;
+ signal co6_2: std_logic;
+ signal co5_4: std_logic;
+ signal rcount_12: std_logic;
+ signal mdout1_1_0: std_logic;
+ signal mdout1_0_0: std_logic;
+ signal mdout1_1_1: std_logic;
+ signal mdout1_0_1: std_logic;
+ signal mdout1_1_2: std_logic;
+ signal mdout1_0_2: std_logic;
+ signal mdout1_1_3: std_logic;
+ signal mdout1_0_3: std_logic;
+ signal mdout1_1_4: std_logic;
+ signal mdout1_0_4: std_logic;
+ signal mdout1_1_5: std_logic;
+ signal mdout1_0_5: std_logic;
+ signal mdout1_1_6: std_logic;
+ signal mdout1_0_6: std_logic;
+ signal mdout1_1_7: std_logic;
+ signal mdout1_0_7: std_logic;
+ signal rcount_11_ff: std_logic;
+ signal mdout1_1_8: std_logic;
+ signal mdout1_0_8: std_logic;
+ signal cmp_ci_2: std_logic;
+ signal fcnt_en_inv_inv: std_logic;
+ signal cnt_con: std_logic;
+ signal fcount_0: std_logic;
+ signal fcount_1: std_logic;
+ signal co0_5: std_logic;
+ signal cnt_con_inv: std_logic;
+ signal fcount_2: std_logic;
+ signal fcount_3: std_logic;
+ signal co1_5: std_logic;
+ signal fcount_4: std_logic;
+ signal fcount_5: std_logic;
+ signal co2_5: std_logic;
+ signal fcount_6: std_logic;
+ signal fcount_7: std_logic;
+ signal co3_5: std_logic;
+ signal fcount_8: std_logic;
+ signal fcount_9: std_logic;
+ signal co4_5: std_logic;
+ signal fcount_10: std_logic;
+ signal fcount_11: std_logic;
+ signal co5_5: std_logic;
+ signal fcount_12: std_logic;
+ signal af_d: std_logic;
+ signal scuba_vhi: std_logic;
+ signal scuba_vlo: std_logic;
+ signal af_d_c: std_logic;
+
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute GSR : string;
+ attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_4k_9.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is "";
+ attribute MEM_LPC_FILE of pdp_ram_1_0_0 : label is "fifo_4k_9.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_1_0_0 : label is "";
+ attribute GSR of FF_42 : label is "ENABLED";
+ attribute GSR of FF_41 : label is "ENABLED";
+ attribute GSR of FF_40 : label is "ENABLED";
+ attribute GSR of FF_39 : label is "ENABLED";
+ attribute GSR of FF_38 : label is "ENABLED";
+ attribute GSR of FF_37 : label is "ENABLED";
+ attribute GSR of FF_36 : label is "ENABLED";
+ attribute GSR of FF_35 : label is "ENABLED";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ AND2_t4: AND2
+ port map (A=>WrEn, B=>invout_2, Z=>wren_i);
+
+ INV_8: INV
+ port map (A=>full_i, Z=>invout_2);
+
+ AND2_t3: AND2
+ port map (A=>RdEn, B=>invout_1, Z=>rden_i);
+
+ INV_7: INV
+ port map (A=>empty_i, Z=>invout_1);
+
+ AND2_t2: AND2
+ port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
+
+ XOR2_t1: XOR2
+ port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
+
+ INV_6: INV
+ port map (A=>rden_i, Z=>rden_i_inv);
+
+ INV_5: INV
+ port map (A=>wren_i, Z=>wren_i_inv);
+
+ LUT4_1: ROM16X1A
+ generic map (initval=> X"3232")
+ port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i,
+ AD0=>empty_i, DO0=>empty_d);
+
+ LUT4_0: ROM16X1A
+ generic map (initval=> X"3232")
+ port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
+ AD0=>full_i, DO0=>full_d);
+
+ AND2_t0: AND2
+ port map (A=>rden_i, B=>invout_0, Z=>r_nw);
+
+ INV_4: INV
+ port map (A=>wren_i, Z=>invout_0);
+
+ INV_3: INV
+ port map (A=>fcnt_en, Z=>fcnt_en_inv);
+
+ INV_2: INV
+ port map (A=>cnt_con, Z=>cnt_con_inv);
+
+ INV_1: INV
+ port map (A=>r_nw, Z=>r_nw_inv);
+
+ INV_0: INV
+ port map (A=>fcnt_en_inv, Z=>fcnt_en_inv_inv);
+
+ pdp_ram_0_0_1: DP16KD
+ generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "ASYNC",
+ CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo,
+ DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5),
+ DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1),
+ DIA0=>Data(0), ADA13=>wcount_10, ADA12=>wcount_9,
+ ADA11=>wcount_8, ADA10=>wcount_7, ADA9=>wcount_6,
+ ADA8=>wcount_5, ADA7=>wcount_4, ADA6=>wcount_3,
+ ADA5=>wcount_2, ADA4=>wcount_1, ADA3=>wcount_0,
+ ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo,
+ CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
+ CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>wcount_11,
+ RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB0=>scuba_vlo, ADB13=>rcount_10, ADB12=>rcount_9,
+ ADB11=>rcount_8, ADB10=>rcount_7, ADB9=>rcount_6,
+ ADB8=>rcount_5, ADB7=>rcount_4, ADB6=>rcount_3,
+ ADB5=>rcount_2, ADB4=>rcount_1, ADB3=>rcount_0,
+ ADB2=>scuba_vlo, ADB1=>scuba_vlo, ADB0=>scuba_vlo,
+ CEB=>rden_i, OCEB=>rden_i, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>rcount_11,
+ RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open,
+ DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open,
+ DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open,
+ DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open,
+ DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open,
+ DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open,
+ DOB10=>open, DOB9=>open, DOB8=>mdout1_0_8, DOB7=>mdout1_0_7,
+ DOB6=>mdout1_0_6, DOB5=>mdout1_0_5, DOB4=>mdout1_0_4,
+ DOB3=>mdout1_0_3, DOB2=>mdout1_0_2, DOB1=>mdout1_0_1,
+ DOB0=>mdout1_0_0);
+
+ pdp_ram_1_0_0: DP16KD
+ generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "ASYNC",
+ CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo,
+ DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5),
+ DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1),
+ DIA0=>Data(0), ADA13=>wcount_10, ADA12=>wcount_9,
+ ADA11=>wcount_8, ADA10=>wcount_7, ADA9=>wcount_6,
+ ADA8=>wcount_5, ADA7=>wcount_4, ADA6=>wcount_3,
+ ADA5=>wcount_2, ADA4=>wcount_1, ADA3=>wcount_0,
+ ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo,
+ CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
+ CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>wcount_11,
+ RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB0=>scuba_vlo, ADB13=>rcount_10, ADB12=>rcount_9,
+ ADB11=>rcount_8, ADB10=>rcount_7, ADB9=>rcount_6,
+ ADB8=>rcount_5, ADB7=>rcount_4, ADB6=>rcount_3,
+ ADB5=>rcount_2, ADB4=>rcount_1, ADB3=>rcount_0,
+ ADB2=>scuba_vlo, ADB1=>scuba_vlo, ADB0=>scuba_vlo,
+ CEB=>rden_i, OCEB=>rden_i, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>rcount_11,
+ RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open,
+ DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open,
+ DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open,
+ DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open,
+ DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open,
+ DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open,
+ DOB10=>open, DOB9=>open, DOB8=>mdout1_1_8, DOB7=>mdout1_1_7,
+ DOB6=>mdout1_1_6, DOB5=>mdout1_1_5, DOB4=>mdout1_1_4,
+ DOB3=>mdout1_1_3, DOB2=>mdout1_1_2, DOB1=>mdout1_1_1,
+ DOB0=>mdout1_1_0);
+
+ FF_42: FD1P3DX
+ port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_0);
+
+ FF_41: FD1P3DX
+ port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_1);
+
+ FF_40: FD1P3DX
+ port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_2);
+
+ FF_39: FD1P3DX
+ port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_3);
+
+ FF_38: FD1P3DX
+ port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_4);
+
+ FF_37: FD1P3DX
+ port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_5);
+
+ FF_36: FD1P3DX
+ port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_6);
+
+ FF_35: FD1P3DX
+ port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_7);
+
+ FF_34: FD1P3DX
+ port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_8);
+
+ FF_33: FD1P3DX
+ port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_9);
+
+ FF_32: FD1P3DX
+ port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_10);
+
+ FF_31: FD1P3DX
+ port map (D=>ifcount_11, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_11);
+
+ FF_30: FD1P3DX
+ port map (D=>ifcount_12, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_12);
+
+ FF_29: FD1S3BX
+ port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
+
+ FF_28: FD1S3DX
+ port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
+
+ FF_27: FD1P3DX
+ port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_0);
+
+ FF_26: FD1P3DX
+ port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_25: FD1P3DX
+ port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_24: FD1P3DX
+ port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_23: FD1P3DX
+ port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_22: FD1P3DX
+ port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_5);
+
+ FF_21: FD1P3DX
+ port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_6);
+
+ FF_20: FD1P3DX
+ port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_7);
+
+ FF_19: FD1P3DX
+ port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_8);
+
+ FF_18: FD1P3DX
+ port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_9);
+
+ FF_17: FD1P3DX
+ port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_10);
+
+ FF_16: FD1P3DX
+ port map (D=>iwcount_11, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_11);
+
+ FF_15: FD1P3DX
+ port map (D=>iwcount_12, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_12);
+
+ FF_14: FD1P3DX
+ port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_0);
+
+ FF_13: FD1P3DX
+ port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_1);
+
+ FF_12: FD1P3DX
+ port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_2);
+
+ FF_11: FD1P3DX
+ port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_3);
+
+ FF_10: FD1P3DX
+ port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_4);
+
+ FF_9: FD1P3DX
+ port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_5);
+
+ FF_8: FD1P3DX
+ port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_6);
+
+ FF_7: FD1P3DX
+ port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_7);
+
+ FF_6: FD1P3DX
+ port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_8);
+
+ FF_5: FD1P3DX
+ port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_9);
+
+ FF_4: FD1P3DX
+ port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_10);
+
+ FF_3: FD1P3DX
+ port map (D=>ircount_11, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_11);
+
+ FF_2: FD1P3DX
+ port map (D=>ircount_12, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_12);
+
+ FF_1: FD1P3DX
+ port map (D=>rcount_11, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+ Q=>rcount_11_ff);
+
+ FF_0: FD1S3DX
+ port map (D=>af_d, CK=>Clock, CD=>Reset, Q=>AlmostFull);
+
+ bdcnt_bctr_cia: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>'X', S0=>open, S1=>open, COUT=>bdcnt_bctr_ci);
+
+ bdcnt_bctr_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>cnt_con, B1=>cnt_con,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>bdcnt_bctr_ci, S0=>ifcount_0, S1=>ifcount_1, COUT=>co0);
+
+ bdcnt_bctr_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con, B1=>cnt_con,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co0, S0=>ifcount_2, S1=>ifcount_3, COUT=>co1);
+
+ bdcnt_bctr_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>cnt_con, B1=>cnt_con,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co1, S0=>ifcount_4, S1=>ifcount_5, COUT=>co2);
+
+ bdcnt_bctr_3: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>cnt_con, B1=>cnt_con,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co2, S0=>ifcount_6, S1=>ifcount_7, COUT=>co3);
+
+ bdcnt_bctr_4: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>cnt_con, B1=>cnt_con,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co3, S0=>ifcount_8, S1=>ifcount_9, COUT=>co4);
+
+ bdcnt_bctr_5: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_10, A1=>fcount_11, B0=>cnt_con, B1=>cnt_con,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co4, S0=>ifcount_10, S1=>ifcount_11, COUT=>co5);
+
+ bdcnt_bctr_6: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_12, A1=>scuba_vlo, B0=>cnt_con, B1=>cnt_con,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co5, S0=>ifcount_12, S1=>open, COUT=>co6);
+
+ e_cmp_ci_a: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci);
+
+ e_cmp_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>rden_i, A1=>scuba_vlo, B0=>fcount_0, B1=>fcount_1,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>cmp_ci, S0=>open, S1=>open, COUT=>co0_1);
+
+ e_cmp_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_2,
+ B1=>fcount_3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co0_1, S0=>open, S1=>open, COUT=>co1_1);
+
+ e_cmp_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_4,
+ B1=>fcount_5, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co1_1, S0=>open, S1=>open, COUT=>co2_1);
+
+ e_cmp_3: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_6,
+ B1=>fcount_7, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co2_1, S0=>open, S1=>open, COUT=>co3_1);
+
+ e_cmp_4: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_8,
+ B1=>fcount_9, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co3_1, S0=>open, S1=>open, COUT=>co4_1);
+
+ e_cmp_5: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_10,
+ B1=>fcount_11, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co4_1, S0=>open, S1=>open, COUT=>co5_1);
+
+ e_cmp_6: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_12,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co5_1, S0=>open, S1=>open,
+ COUT=>cmp_le_1_c);
+
+ a0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>cmp_le_1_c, S0=>cmp_le_1, S1=>open,
+ COUT=>open);
+
+ g_cmp_ci_a: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_1);
+
+ g_cmp_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>cmp_ci_1, S0=>open, S1=>open, COUT=>co0_2);
+
+ g_cmp_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co0_2, S0=>open, S1=>open, COUT=>co1_2);
+
+ g_cmp_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co1_2, S0=>open, S1=>open, COUT=>co2_2);
+
+ g_cmp_3: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co2_2, S0=>open, S1=>open, COUT=>co3_2);
+
+ g_cmp_4: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co3_2, S0=>open, S1=>open, COUT=>co4_2);
+
+ g_cmp_5: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_10, A1=>fcount_11, B0=>wren_i, B1=>wren_i,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co4_2, S0=>open, S1=>open, COUT=>co5_2);
+
+ g_cmp_6: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_12, A1=>scuba_vlo, B0=>wren_i_inv,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co5_2, S0=>open, S1=>open,
+ COUT=>cmp_ge_d1_c);
+
+ a1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>cmp_ge_d1_c, S0=>cmp_ge_d1, S1=>open,
+ COUT=>open);
+
+ w_ctr_cia: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>w_ctr_ci);
+
+ w_ctr_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>w_ctr_ci, S0=>iwcount_0, S1=>iwcount_1,
+ COUT=>co0_3);
+
+ w_ctr_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>wcount_2, A1=>wcount_3, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co0_3, S0=>iwcount_2, S1=>iwcount_3,
+ COUT=>co1_3);
+
+ w_ctr_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>wcount_4, A1=>wcount_5, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co1_3, S0=>iwcount_4, S1=>iwcount_5,
+ COUT=>co2_3);
+
+ w_ctr_3: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>wcount_6, A1=>wcount_7, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co2_3, S0=>iwcount_6, S1=>iwcount_7,
+ COUT=>co3_3);
+
+ w_ctr_4: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>wcount_8, A1=>wcount_9, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co3_3, S0=>iwcount_8, S1=>iwcount_9,
+ COUT=>co4_3);
+
+ w_ctr_5: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>wcount_10, A1=>wcount_11, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co4_3, S0=>iwcount_10, S1=>iwcount_11,
+ COUT=>co5_3);
+
+ w_ctr_6: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>wcount_12, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co5_3, S0=>iwcount_12, S1=>open,
+ COUT=>co6_1);
+
+ r_ctr_cia: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>r_ctr_ci);
+
+ r_ctr_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>r_ctr_ci, S0=>ircount_0, S1=>ircount_1,
+ COUT=>co0_4);
+
+ r_ctr_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>rcount_2, A1=>rcount_3, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co0_4, S0=>ircount_2, S1=>ircount_3,
+ COUT=>co1_4);
+
+ r_ctr_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>rcount_4, A1=>rcount_5, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co1_4, S0=>ircount_4, S1=>ircount_5,
+ COUT=>co2_4);
+
+ r_ctr_3: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>rcount_6, A1=>rcount_7, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co2_4, S0=>ircount_6, S1=>ircount_7,
+ COUT=>co3_4);
+
+ r_ctr_4: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>rcount_8, A1=>rcount_9, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co3_4, S0=>ircount_8, S1=>ircount_9,
+ COUT=>co4_4);
+
+ r_ctr_5: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>rcount_10, A1=>rcount_11, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co4_4, S0=>ircount_10, S1=>ircount_11,
+ COUT=>co5_4);
+
+ r_ctr_6: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>rcount_12, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co5_4, S0=>ircount_12, S1=>open,
+ COUT=>co6_2);
+
+ mux_8: MUX21
+ port map (D0=>mdout1_0_0, D1=>mdout1_1_0, SD=>rcount_11_ff,
+ Z=>Q(0));
+
+ mux_7: MUX21
+ port map (D0=>mdout1_0_1, D1=>mdout1_1_1, SD=>rcount_11_ff,
+ Z=>Q(1));
+
+ mux_6: MUX21
+ port map (D0=>mdout1_0_2, D1=>mdout1_1_2, SD=>rcount_11_ff,
+ Z=>Q(2));
+
+ mux_5: MUX21
+ port map (D0=>mdout1_0_3, D1=>mdout1_1_3, SD=>rcount_11_ff,
+ Z=>Q(3));
+
+ mux_4: MUX21
+ port map (D0=>mdout1_0_4, D1=>mdout1_1_4, SD=>rcount_11_ff,
+ Z=>Q(4));
+
+ mux_3: MUX21
+ port map (D0=>mdout1_0_5, D1=>mdout1_1_5, SD=>rcount_11_ff,
+ Z=>Q(5));
+
+ mux_2: MUX21
+ port map (D0=>mdout1_0_6, D1=>mdout1_1_6, SD=>rcount_11_ff,
+ Z=>Q(6));
+
+ mux_1: MUX21
+ port map (D0=>mdout1_0_7, D1=>mdout1_1_7, SD=>rcount_11_ff,
+ Z=>Q(7));
+
+ mux_0: MUX21
+ port map (D0=>mdout1_0_8, D1=>mdout1_1_8, SD=>rcount_11_ff,
+ Z=>Q(8));
+
+ af_cmp_ci_a: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_2);
+
+ af_cmp_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>fcnt_en_inv_inv,
+ B1=>cnt_con, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>cmp_ci_2, S0=>open, S1=>open,
+ COUT=>co0_5);
+
+ af_cmp_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con_inv,
+ B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co0_5, S0=>open, S1=>open, COUT=>co1_5);
+
+ af_cmp_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vhi,
+ B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co1_5, S0=>open, S1=>open, COUT=>co2_5);
+
+ af_cmp_3: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vhi,
+ B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co2_5, S0=>open, S1=>open, COUT=>co3_5);
+
+ af_cmp_4: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vhi,
+ B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co3_5, S0=>open, S1=>open, COUT=>co4_5);
+
+ af_cmp_5: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_10, A1=>fcount_11, B0=>scuba_vhi,
+ B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co4_5, S0=>open, S1=>open, COUT=>co5_5);
+
+ af_cmp_6: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_12, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co5_5, S0=>open, S1=>open, COUT=>af_d_c);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>af_d_c, S0=>af_d, S1=>open, COUT=>open);
+
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
--- /dev/null
+[Device]
+Family=ecp5um5g
+PartType=LFE5UM5G-85F
+PartName=LFE5UM5G-85F-8BG381C
+SpeedGrade=8
+Package=CABGA381
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=RAM_DP
+CoreRevision=6.5
+ModuleName=rb_4k_9
+SourceFormat=vhdl
+ParameterFileVersion=1.0
+Date=07/13/2022
+Time=09:14:51
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+RAddress=4096
+RData=9
+WAddress=4096
+WData=9
+enByte=0
+ByteSize=9
+OutputEn=0
+ClockEn=0
+Optimization=Speed
+Reset=Async
+Reset1=Async
+Init=0
+MemFile=
+MemFormat=bin
+EnECC=0
+Pipeline=0
+init_data=0
+
+[FilesGenerated]
+=mem
+
+[Command]
+cmd_line= -w -n rb_4k_9 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00g -type ramdps -device LFE5UM5G-85F -raddr_width 12 -rwidth 9 -waddr_width 12 -wwidth 9 -rnum_words 4096 -wnum_words 4096 -cascade -1 -mem_init0
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454
+-- Module Version: 6.5
+--/opt/lattice/diamond/3.12/ispfpga/bin/lin64/scuba -w -n rb_4k_9 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00g -type bram -wp 10 -rp 0011 -rdata_width 9 -data_width 9 -num_rows 4096 -cascade -1 -mem_init0 -fdc /home/michaelb/DEEPSEA/ECP5-5G/fifos/rb_4k_9/rb_4k_9.fdc
+
+-- Wed Jul 13 09:14:52 2022
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity rb_4k_9 is
+ port (
+ WrAddress: in std_logic_vector(11 downto 0);
+ RdAddress: in std_logic_vector(11 downto 0);
+ Data: in std_logic_vector(8 downto 0);
+ WE: in std_logic;
+ RdClock: in std_logic;
+ RdClockEn: in std_logic;
+ Reset: in std_logic;
+ WrClock: in std_logic;
+ WrClockEn: in std_logic;
+ Q: out std_logic_vector(8 downto 0));
+end rb_4k_9;
+
+architecture Structure of rb_4k_9 is
+
+ -- internal signal declarations
+ signal scuba_vhi: std_logic;
+ signal scuba_vlo: std_logic;
+ signal mdout1_1_0: std_logic;
+ signal mdout1_0_0: std_logic;
+ signal mdout1_1_1: std_logic;
+ signal mdout1_0_1: std_logic;
+ signal mdout1_1_2: std_logic;
+ signal mdout1_0_2: std_logic;
+ signal mdout1_1_3: std_logic;
+ signal mdout1_0_3: std_logic;
+ signal mdout1_1_4: std_logic;
+ signal mdout1_0_4: std_logic;
+ signal mdout1_1_5: std_logic;
+ signal mdout1_0_5: std_logic;
+ signal mdout1_1_6: std_logic;
+ signal mdout1_0_6: std_logic;
+ signal mdout1_1_7: std_logic;
+ signal mdout1_0_7: std_logic;
+ signal raddr11_ff: std_logic;
+ signal mdout1_1_8: std_logic;
+ signal mdout1_0_8: std_logic;
+
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute GSR : string;
+ attribute MEM_LPC_FILE of rb_4k_9_0_0_1 : label is "rb_4k_9.lpc";
+ attribute MEM_INIT_FILE of rb_4k_9_0_0_1 : label is "INIT_ALL_0s";
+ attribute MEM_LPC_FILE of rb_4k_9_1_0_0 : label is "rb_4k_9.lpc";
+ attribute MEM_INIT_FILE of rb_4k_9_1_0_0 : label is "INIT_ALL_0s";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ rb_4k_9_0_0_1: DP16KD
+ generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC",
+ INITVAL_3F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_0F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_0E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_0D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_0C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_0B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_0A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_09=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_08=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_07=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_06=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_05=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_04=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_03=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_02=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_01=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_00=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo,
+ DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5),
+ DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1),
+ DIA0=>Data(0), ADA13=>WrAddress(10), ADA12=>WrAddress(9),
+ ADA11=>WrAddress(8), ADA10=>WrAddress(7), ADA9=>WrAddress(6),
+ ADA8=>WrAddress(5), ADA7=>WrAddress(4), ADA6=>WrAddress(3),
+ ADA5=>WrAddress(2), ADA4=>WrAddress(1), ADA3=>WrAddress(0),
+ ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo,
+ CEA=>WrClockEn, OCEA=>WrClockEn, CLKA=>WrClock, WEA=>WE,
+ CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>WrAddress(11),
+ RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB0=>scuba_vlo, ADB13=>RdAddress(10), ADB12=>RdAddress(9),
+ ADB11=>RdAddress(8), ADB10=>RdAddress(7), ADB9=>RdAddress(6),
+ ADB8=>RdAddress(5), ADB7=>RdAddress(4), ADB6=>RdAddress(3),
+ ADB5=>RdAddress(2), ADB4=>RdAddress(1), ADB3=>RdAddress(0),
+ ADB2=>scuba_vlo, ADB1=>scuba_vlo, ADB0=>scuba_vlo,
+ CEB=>RdClockEn, OCEB=>RdClockEn, CLKB=>RdClock,
+ WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo,
+ CSB0=>RdAddress(11), RSTB=>Reset, DOA17=>open, DOA16=>open,
+ DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open,
+ DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open,
+ DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open,
+ DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open,
+ DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open,
+ DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_0_8,
+ DOB7=>mdout1_0_7, DOB6=>mdout1_0_6, DOB5=>mdout1_0_5,
+ DOB4=>mdout1_0_4, DOB3=>mdout1_0_3, DOB2=>mdout1_0_2,
+ DOB1=>mdout1_0_1, DOB0=>mdout1_0_0);
+
+ rb_4k_9_1_0_0: DP16KD
+ generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC",
+ INITVAL_3F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_0F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_0E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_0D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_0C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_0B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_0A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_09=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_08=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_07=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_06=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_05=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_04=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_03=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_02=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_01=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_00=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo,
+ DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5),
+ DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1),
+ DIA0=>Data(0), ADA13=>WrAddress(10), ADA12=>WrAddress(9),
+ ADA11=>WrAddress(8), ADA10=>WrAddress(7), ADA9=>WrAddress(6),
+ ADA8=>WrAddress(5), ADA7=>WrAddress(4), ADA6=>WrAddress(3),
+ ADA5=>WrAddress(2), ADA4=>WrAddress(1), ADA3=>WrAddress(0),
+ ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo,
+ CEA=>WrClockEn, OCEA=>WrClockEn, CLKA=>WrClock, WEA=>WE,
+ CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>WrAddress(11),
+ RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB0=>scuba_vlo, ADB13=>RdAddress(10), ADB12=>RdAddress(9),
+ ADB11=>RdAddress(8), ADB10=>RdAddress(7), ADB9=>RdAddress(6),
+ ADB8=>RdAddress(5), ADB7=>RdAddress(4), ADB6=>RdAddress(3),
+ ADB5=>RdAddress(2), ADB4=>RdAddress(1), ADB3=>RdAddress(0),
+ ADB2=>scuba_vlo, ADB1=>scuba_vlo, ADB0=>scuba_vlo,
+ CEB=>RdClockEn, OCEB=>RdClockEn, CLKB=>RdClock,
+ WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo,
+ CSB0=>RdAddress(11), RSTB=>Reset, DOA17=>open, DOA16=>open,
+ DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open,
+ DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open,
+ DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open,
+ DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open,
+ DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open,
+ DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_1_8,
+ DOB7=>mdout1_1_7, DOB6=>mdout1_1_6, DOB5=>mdout1_1_5,
+ DOB4=>mdout1_1_4, DOB3=>mdout1_1_3, DOB2=>mdout1_1_2,
+ DOB1=>mdout1_1_1, DOB0=>mdout1_1_0);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ FF_0: FD1P3DX
+ port map (D=>RdAddress(11), SP=>RdClockEn, CK=>RdClock,
+ CD=>scuba_vlo, Q=>raddr11_ff);
+
+ mux_8: MUX21
+ port map (D0=>mdout1_0_0, D1=>mdout1_1_0, SD=>raddr11_ff,
+ Z=>Q(0));
+
+ mux_7: MUX21
+ port map (D0=>mdout1_0_1, D1=>mdout1_1_1, SD=>raddr11_ff,
+ Z=>Q(1));
+
+ mux_6: MUX21
+ port map (D0=>mdout1_0_2, D1=>mdout1_1_2, SD=>raddr11_ff,
+ Z=>Q(2));
+
+ mux_5: MUX21
+ port map (D0=>mdout1_0_3, D1=>mdout1_1_3, SD=>raddr11_ff,
+ Z=>Q(3));
+
+ mux_4: MUX21
+ port map (D0=>mdout1_0_4, D1=>mdout1_1_4, SD=>raddr11_ff,
+ Z=>Q(4));
+
+ mux_3: MUX21
+ port map (D0=>mdout1_0_5, D1=>mdout1_1_5, SD=>raddr11_ff,
+ Z=>Q(5));
+
+ mux_2: MUX21
+ port map (D0=>mdout1_0_6, D1=>mdout1_1_6, SD=>raddr11_ff,
+ Z=>Q(6));
+
+ mux_1: MUX21
+ port map (D0=>mdout1_0_7, D1=>mdout1_1_7, SD=>raddr11_ff,
+ Z=>Q(7));
+
+ mux_0: MUX21
+ port map (D0=>mdout1_0_8, D1=>mdout1_1_8, SD=>raddr11_ff,
+ Z=>Q(8));
+
+end Structure;
--- /dev/null
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb_net_gbe_components.all;
+use work.med_sync_define_RS.all;
+
+entity gbe_med_fifo_single is
+ port (
+ RESET : in std_logic;
+ RESET_N : in std_logic;
+ CLEAR : in std_logic;
+ CLEAR_N : in std_logic;
+ CLK_125 : in std_logic;
+ -- FIFO interface RX
+ FIFO_DATA_OUT : out std_logic_vector(8 downto 0);
+ FIFO_FULL_IN : in std_logic := '0';
+ FIFO_WR_OUT : out std_logic;
+ FRAME_REQ_IN : in std_logic := '0';
+ FRAME_ACK_OUT : out std_logic;
+ FRAME_AVAIL_OUT : out std_logic;
+ FRAME_START_OUT : out std_logic;
+ -- FIFO interface TX
+ FIFO_FULL_OUT : out std_logic;
+ FIFO_WR_IN : in std_logic := '0';
+ FIFO_DATA_IN : in std_logic_vector(8 downto 0) := (others => '0');
+ FRAME_START_IN : in std_logic := '0';
+ --SFP Connection
+ SD_PRSNT_N_IN : in std_logic := '1';
+ SD_LOS_IN : in std_logic := '1';
+ SD_TXDIS_OUT : out std_logic;
+ -- Status
+ PCS_AN_READY_OUT : out std_logic; -- for internal SCTRL
+ LINK_ACTIVE_OUT : out std_logic; -- for internal SCTRL
+ -- Debug
+ STATUS_OUT : out std_logic_vector(7 downto 0);
+ DEBUG_OUT : out std_logic_vector(63 downto 0)
+ );
+end entity gbe_med_fifo_single;
+
+architecture RTL of gbe_med_fifo_single is
+
+ component sgmii_gbe_core -- checked for ECP5-5G core
+ port(
+ rst_n : in std_logic;
+ signal_detect : in std_logic;
+ gbe_mode : in std_logic;
+ sgmii_mode : in std_logic;
+ operational_rate : in std_logic_vector(1 downto 0);
+ debug_link_timer_short : in std_logic;
+
+ force_isolate : in std_logic;
+ force_loopback : in std_logic;
+ force_unidir : in std_logic;
+
+ rx_compensation_err : out std_logic;
+
+ ctc_drop_flag : out std_logic;
+ ctc_add_flag : out std_logic;
+ an_link_ok : out std_logic;
+
+ tx_clk_125 : in std_logic;
+ tx_clock_enable_source : out std_logic;
+ tx_clock_enable_sink : in std_logic;
+ tx_d : in std_logic_vector(7 downto 0);
+ tx_en : in std_logic;
+ tx_er : in std_logic;
+ rx_clk_125 : in std_logic;
+ rx_clock_enable_source : out std_logic;
+ rx_clock_enable_sink : in std_logic;
+ rx_d : out std_logic_vector(7 downto 0);
+ rx_dv : out std_logic;
+ rx_er : out std_logic;
+ col : out std_logic;
+ crs : out std_logic;
+ tx_data : out std_logic_vector(7 downto 0);
+ tx_kcntl : out std_logic;
+ tx_disparity_cntl : out std_logic;
+
+ xmit_autoneg : out std_logic;
+
+ serdes_recovered_clk : in std_logic;
+ rx_data : in std_logic_vector(7 downto 0);
+ rx_even : in std_logic;
+ rx_kcntl : in std_logic;
+ rx_disp_err : in std_logic;
+ rx_cv_err : in std_logic;
+ rx_err_decode_mode : in std_logic;
+ mr_an_complete : out std_logic;
+ mr_page_rx : out std_logic;
+ mr_lp_adv_ability : out std_logic_vector(15 downto 0);
+ mr_main_reset : in std_logic;
+ mr_an_enable : in std_logic;
+ mr_restart_an : in std_logic;
+ mr_adv_ability : in std_logic_vector(15 downto 0)
+ );
+ end component;
+
+ component tsmac_gbe -- checked for ECP5-5G core
+ port(
+ --------------- clock and reset port declarations ------------------
+ hclk : in std_logic;
+ txmac_clk : in std_logic;
+ rxmac_clk : in std_logic;
+ reset_n : in std_logic;
+ ------------------- Input signals to the GMII ----------------
+ rxd : in std_logic_vector(7 downto 0);
+ rx_dv : in std_logic;
+ rx_er : in std_logic;
+ -------------------- Input signals to the CPU I/F -------------------
+ haddr : in std_logic_vector(7 downto 0);
+ hdatain : in std_logic_vector(7 downto 0);
+ hcs_n : in std_logic;
+ hwrite_n : in std_logic;
+ hread_n : in std_logic;
+ ---------------- Input signals to the Tx MAC FIFO I/F ---------------
+ tx_fifodata : in std_logic_vector(7 downto 0);
+ tx_fifoavail : in std_logic;
+ tx_fifoeof : in std_logic;
+ tx_fifoempty : in std_logic;
+ tx_sndpaustim : in std_logic_vector(15 downto 0);
+ tx_sndpausreq : in std_logic;
+ tx_fifoctrl : in std_logic;
+ ---------------- Input signals to the Rx MAC FIFO I/F ---------------
+ rx_fifo_full : in std_logic;
+ ignore_pkt : in std_logic;
+ -------------------- Output signals from the GMII -----------------------
+ txd : out std_logic_vector(7 downto 0);
+ tx_en : out std_logic;
+ tx_er : out std_logic;
+ -------------------- Output signals from the CPU I/F -------------------
+ hdataout : out std_logic_vector(7 downto 0);
+ hdataout_en_n : out std_logic;
+ hready_n : out std_logic;
+ cpu_if_gbit_en : out std_logic;
+ ---------------- Output signals from the Tx MAC FIFO I/F ---------------
+ tx_macread : out std_logic;
+ tx_discfrm : out std_logic;
+ tx_staten : out std_logic;
+ tx_done : out std_logic;
+ tx_statvec : out std_logic_vector(30 downto 0);
+ ---------------- Output signals from the Rx MAC FIFO I/F ---------------
+ rx_fifo_error : out std_logic;
+ rx_stat_vector : out std_logic_vector(31 downto 0);
+ rx_dbout : out std_logic_vector(7 downto 0);
+ rx_write : out std_logic;
+ rx_stat_en : out std_logic;
+ rx_eof : out std_logic;
+ rx_error : out std_logic
+ );
+ end component;
+
+ signal sd_rx_clk : std_logic;
+ signal sd_tx_kcntl : std_logic_vector(0 downto 0);
+ signal sd_tx_data : std_logic_vector(7 downto 0);
+ signal xmit : std_logic_vector(0 downto 0);
+ signal sd_tx_correct_disp : std_logic_vector(0 downto 0);
+ signal sd_rx_data : std_logic_vector(7 downto 0);
+ signal sd_rx_kcntl : std_logic_vector(0 downto 0);
+ signal sd_rx_disp_error : std_logic_vector(0 downto 0);
+ signal sd_rx_cv_error : std_logic_vector(0 downto 0);
+ signal lsm_status : std_logic;
+ signal rx_clk_en : std_logic;
+ signal tx_clk_en : std_logic;
+ signal operational_rate : std_logic_vector(1 downto 0);
+ signal an_complete : std_logic;
+ signal mr_page_rx : std_logic;
+ signal mr_lp_adv_ability : std_logic_vector(15 downto 0);
+ signal mr_main_reset : std_logic;
+ signal mr_restart_an : std_logic;
+ signal mr_adv_ability : std_logic_vector(15 downto 0);
+ signal mr_an_enable : std_logic;
+ signal an_link_ok : std_logic;
+ signal pcs_rxd : std_logic_vector(7 downto 0);
+ signal pcs_rx_en : std_logic;
+ signal pcs_rx_er : std_logic;
+ signal pcs_txd : std_logic_vector(7 downto 0);
+ signal pcs_tx_en : std_logic;
+ signal pcs_tx_er : std_logic;
+ signal tsm_hdataout_en_n : std_logic;
+ signal tsm_hready_n : std_logic;
+ signal tsm_hread_n : std_logic;
+ signal tsm_hwrite_n : std_logic;
+ signal tsm_hcs_n : std_logic;
+ signal tsm_hdata : std_logic_vector(7 downto 0);
+ signal tsm_haddr : std_logic_vector(7 downto 0);
+
+ signal mac_ready_conf : std_logic;
+ signal mac_reconf : std_logic;
+ signal link_active : std_logic;
+
+ signal link_rx_ready : std_logic;
+ signal rx_los_low : std_logic;
+ signal rx_cdr_lol : std_logic;
+ signal rx_pcs_rst : std_logic;
+ signal rx_pcs_rst_q : std_logic;
+ signal rx_serdes_rst : std_logic;
+ signal rx_serdes_rst_q : std_logic;
+ signal tx_pcs_rst : std_logic;
+ signal link_tx_ready : std_logic;
+ signal pll_lol : std_logic;
+
+ signal mac_tx_data : std_logic_vector(7 downto 0);
+ signal mac_rx_data : std_logic_vector(7 downto 0);
+ signal mac_fifoavail : std_logic;
+ signal mac_fifoeof : std_logic;
+ signal mac_fifoempty : std_logic;
+ signal mac_rx_fifofull : std_logic;
+ signal mac_tx_read : std_logic;
+ signal mac_tx_done : std_logic;
+ signal mac_rx_wr : std_logic;
+ signal mac_rx_eof : std_logic;
+ signal mac_rx_err : std_logic;
+
+ signal debug : std_logic_vector(63 downto 0);
+
+ -- for replacing register interface
+ signal delay_q : std_logic_vector(7 downto 0);
+ signal pulse : std_logic;
+
+ signal led_timer : unsigned(19 downto 0);
+ signal led_timer_done_x : std_logic;
+ signal led_timer_done : std_logic;
+ signal led_activity_x : std_logic;
+ signal led_activity : std_logic_vector(1 downto 0);
+
+ signal SD_RXD_P : std_logic;
+ signal SD_RXD_N : std_logic;
+ signal SD_TXD_P : std_logic;
+ signal SD_TXD_N : std_logic;
+
+ signal fifo_full_i : std_logic;
+
+begin
+
+ -- Some notes on clocks: the SerDes uses TX and RX bridge FIFO, with RX FIFO being clocked on
+ -- both read and write side by rx_pclk, and TX FIFO being clocked on write side by txi_clk.
+ -- For TX, we can use local 125MHz clock.
+ -- For RX, the SGMII core implements the CTC FIFO, and by clocking SGMII also by local 125MHz
+ -- (except serdes_recovered_clk, which goes to rx_pclk) we have *everthing* behind the SGMII
+ -- on local 125MHz clock.
+
+ gbe_serdes: entity serdes_gbe
+ port map(
+ -- external I/Os
+ hdinp => SD_RXD_P,
+ hdinn => SD_RXD_N,
+ hdoutp => SD_TXD_P,
+ hdoutn => SD_TXD_N,
+ -- clocks
+ pll_refclki => CLK_125, -- TX reference clock for PLL
+ rxrefclk => CLK_125, -- RX reference clock for CDR
+ txi_clk => CLK_125, -- feeds the TX FIFO
+ tx_pclk => open, -- not really needed
+ rx_pclk => sd_rx_clk, -- recovered RX clock, also used on FIFO!
+ -- TX channel
+ txdata => sd_tx_data,
+ tx_k => sd_tx_kcntl,
+ tx_disp_correct => sd_tx_correct_disp,
+ xmit => xmit, -- not used, should not harm
+ -- RX channel
+ rxdata => sd_rx_data,
+ rx_k => sd_rx_kcntl,
+ rx_disp_err => sd_rx_disp_error,
+ rx_cv_err => sd_rx_cv_error,
+ lsm_status_s => lsm_status,
+ signal_detect_c => '1', -- enable internal LSM
+ -- Status signals
+ pll_lol => pll_lol,
+ rx_cdr_lol_s => rx_cdr_lol,
+ rx_los_low_s => rx_los_low,
+ -- Power control
+ rx_pwrup_c => '1',
+ tx_pwrup_c => '1',
+ serdes_pdb => '1', -- DUAL is powered up
+ -- Resets
+ sli_rst => CLEAR, --'0', -- soft logic reset (?)
+ rst_dual_c => CLEAR,
+ rx_pcs_rst_c => rx_pcs_rst_q,
+ rx_serdes_rst_c => rx_serdes_rst_q,
+ tx_pcs_rst_c => tx_pcs_rst,
+ serdes_rst_dual_c => '0',
+ tx_serdes_rst_c => '0'
+ );
+
+ SD_TXDIS_OUT <= '0';
+
+ -- RSL for TX of SerDes, based on extRSL logic
+ THE_MAIN_TX_RST: main_tx_reset_RS
+ port map (
+ CLEAR => CLEAR,
+ CLK_REF => CLK_125,
+ TX_PLL_LOL_IN => pll_lol,
+ TX_CLOCK_AVAIL_IN => '1', -- not needed here
+ TX_PCS_RST_CH_C_OUT => tx_pcs_rst,
+ SYNC_TX_QUAD_OUT => open, --not needed here
+ LINK_TX_READY_OUT => link_tx_ready,
+ STATE_OUT => open
+ );
+
+ -- RSL for RX of SerDes, based on extRSL logic
+ -- CAVEAT: reset signals MUST BE sync'ed to recovered RX clock!
+ THE_MAIN_RX_RST: main_rx_reset_RS
+ port map(
+ CLEAR => CLEAR,
+ CLK_REF => CLK_125,
+ CDR_LOL_IN => rx_cdr_lol,
+ CV_IN => sd_rx_cv_error(0),
+ LSM_IN => lsm_status,
+ LOS_IN => rx_los_low,
+ WAP_ZERO_IN => '1', -- not needed here
+ -- outputs
+ WAP_REQ_OUT => open, -- not needed here
+ RX_SERDES_RST_OUT => rx_serdes_rst, -- CLK_REF based
+ RX_PCS_RST_OUT => rx_pcs_rst, -- CLK_REF based
+ LINK_RX_READY_OUT => link_rx_ready, -- CLK_REF based
+ STATE_OUT => open
+ );
+
+ -- reset signals for RX SerDes need to be sync'ed to real RX clock for ECP5
+ SYNC_RST_SIGS: entity work.signal_sync
+ generic map( WIDTH => 2 )
+ port map(
+ RESET => '0',
+ CLK0 => sd_rx_clk,
+ CLK1 => sd_rx_clk,
+ D_IN(0) => rx_pcs_rst,
+ D_IN(1) => rx_serdes_rst,
+ D_OUT(0) => rx_pcs_rst_q,
+ D_OUT(1) => rx_serdes_rst_q
+ );
+
+ -- SGMII core
+ SGMII_GBE_PCS : sgmii_gbe_core
+ port map(
+ rst_n => CLEAR_N, --RESET_N,
+ signal_detect => link_rx_ready,
+ gbe_mode => '1',
+ sgmii_mode => '0',
+ operational_rate => operational_rate,
+ debug_link_timer_short => '0',
+ force_isolate => '0',
+ force_loopback => '0',
+ force_unidir => '0',
+ rx_compensation_err => open,
+ ctc_drop_flag => open,
+ ctc_add_flag => open,
+ an_link_ok => an_link_ok,
+ -- MAC interface
+ tx_clk_125 => CLK_125,
+ tx_clock_enable_source => tx_clk_en,
+ tx_clock_enable_sink => tx_clk_en,
+ tx_d => pcs_txd, -- TX data from MAC
+ tx_en => pcs_tx_en, -- TX data enable from MAC
+ tx_er => pcs_tx_er, -- TX error from MAC
+ rx_clk_125 => CLK_125,
+ rx_clock_enable_source => rx_clk_en,
+ rx_clock_enable_sink => rx_clk_en,
+ rx_d => pcs_rxd, -- RX data to MAC
+ rx_dv => pcs_rx_en, -- RX data enable to MAC
+ rx_er => pcs_rx_er, -- RX error to MAC
+ col => open,
+ crs => open,
+ -- SerDes interface
+ tx_data => sd_tx_data, -- TX data to SerDes
+ tx_kcntl => sd_tx_kcntl(0), -- TX komma control to SerDes
+ tx_disparity_cntl => sd_tx_correct_disp(0), -- idle parity state control in IPG (to SerDes)
+ xmit_autoneg => xmit(0),
+ serdes_recovered_clk => sd_rx_clk, -- 125MHz recovered from receive bit stream
+ rx_data => sd_rx_data, -- RX data from SerDes
+ rx_kcntl => sd_rx_kcntl(0), -- RX komma control from SerDes
+ rx_err_decode_mode => '0', -- receive error control mode fixed to normal
+ rx_even => '0', -- unused (receive error control mode = normal, tie to GND)
+ rx_disp_err => sd_rx_disp_error(0), -- RX disparity error from SerDes
+ rx_cv_err => sd_rx_cv_error(0), -- RX code violation error from SerDes
+ -- Autonegotiation stuff
+ mr_an_complete => an_complete,
+ mr_page_rx => mr_page_rx,
+ mr_lp_adv_ability => mr_lp_adv_ability,
+ mr_main_reset => mr_main_reset,
+ mr_an_enable => mr_an_enable,
+ mr_restart_an => mr_restart_an,
+ mr_adv_ability => mr_adv_ability
+ );
+
+--- SIMPLE ---
+ operational_rate <= b"10";
+--- /SIMPLE ---
+
+--- SIMPLE ---
+ mr_main_reset <= CLEAR;
+ mr_restart_an <= pulse;
+ mr_an_enable <= link_rx_ready;
+ mr_adv_ability <= x"0020";
+
+ SYNC_PROC: process( CLK_125 )
+ begin
+ if( rising_edge(CLK_125) ) then
+ delay_q <= delay_q(6 downto 0) & link_rx_ready;
+ end if;
+ end process SYNC_PROC;
+
+ pulse <= not delay_q(7) and delay_q(6);
+--- /SIMPLE ---
+
+ -- "Good" debugging pins
+ debug(7 downto 0) <= pcs_txd;
+ debug(15 downto 8) <= pcs_rxd;
+ debug(16) <= pcs_tx_en;
+ debug(17) <= pcs_rx_en;
+ debug(18) <= pcs_tx_er;
+ debug(19) <= pcs_rx_er;
+ -- "Bad" debugging pins
+ debug(20) <= mr_restart_an;
+ debug(21) <= mr_page_rx;
+ debug(22) <= an_complete;
+ debug(23) <= link_rx_ready;
+ debug(24) <= link_tx_ready;
+ debug(25) <= xmit(0);
+ debug(26) <= sd_tx_correct_disp(0);
+ debug(27) <= mac_ready_conf;
+ debug(28) <= mac_reconf;
+ debug(29) <= link_active;
+ debug(30) <= fifo_full_i;
+ debug(31) <= mac_rx_fifofull;
+ debug(32) <= '0';
+ debug(33) <= CLK_125;
+
+ MAC: tsmac_gbe
+ port map(
+ ----------------- clock and reset port declarations ------------------
+ hclk => CLK_125,
+ txmac_clk => CLK_125,
+ rxmac_clk => CLK_125,
+ reset_n => CLEAR_N, --RESET_N,
+ ------------------- Input signals to the GMII ----------------
+ rxd => pcs_rxd,
+ rx_dv => pcs_rx_en,
+ rx_er => pcs_rx_er,
+ -------------------- Input signals to the CPU I/F -------------------
+ haddr => tsm_haddr,
+ hdatain => tsm_hdata,
+ hcs_n => tsm_hcs_n,
+ hwrite_n => tsm_hwrite_n,
+ hread_n => tsm_hread_n,
+ ---------------- Input signals to the Tx MAC FIFO I/F ---------------
+ tx_fifodata => mac_tx_data,
+ tx_fifoavail => mac_fifoavail,
+ tx_fifoeof => mac_fifoeof,
+ tx_fifoempty => mac_fifoempty,
+ tx_sndpaustim => x"0000",
+ tx_sndpausreq => '0',
+ tx_fifoctrl => '0', -- always data frame
+ ---------------- Input signals to the Rx MAC FIFO I/F ---------------
+ rx_fifo_full => mac_rx_fifofull,
+ ignore_pkt => '0',
+ ---------------- Output signals from the GMII -----------------------
+ txd => pcs_txd,
+ tx_en => pcs_tx_en,
+ tx_er => pcs_tx_er,
+ ----------------- Output signals from the CPU I/F -------------------
+ hdataout => open,
+ hdataout_en_n => tsm_hdataout_en_n,
+ hready_n => tsm_hready_n,
+ cpu_if_gbit_en => open,
+ ------------- Output signals from the Tx MAC FIFO I/F ---------------
+ tx_macread => mac_tx_read,
+ tx_discfrm => open,
+ tx_staten => open,
+ tx_statvec => open,
+ tx_done => mac_tx_done,
+ ------------- Output signals from the Rx MAC FIFO I/F ---------------
+ rx_fifo_error => open,
+ rx_stat_vector => open,
+ rx_dbout => mac_rx_data,
+ rx_write => mac_rx_wr,
+ rx_stat_en => open,
+ rx_eof => mac_rx_eof,
+ rx_error => mac_rx_err
+ );
+
+ TSMAC_CONTROLLER : trb_net16_gbe_mac_control
+ port map(
+ CLK => CLK_125,
+ RESET => RESET,
+ -- signals to/from main controller
+ MC_TSMAC_READY_OUT => mac_ready_conf,
+ MC_RECONF_IN => mac_reconf,
+ MC_GBE_EN_IN => '1',
+ MC_RX_DISCARD_FCS => '0',
+ MC_PROMISC_IN => '1',
+ MC_MAC_ADDR_IN => (others => '0'),
+ -- signal to/from Host interface of TriSpeed MAC
+ TSM_HADDR_OUT => tsm_haddr,
+ TSM_HDATA_OUT => tsm_hdata,
+ TSM_HCS_N_OUT => tsm_hcs_n,
+ TSM_HWRITE_N_OUT => tsm_hwrite_n,
+ TSM_HREAD_N_OUT => tsm_hread_n,
+ TSM_HREADY_N_IN => tsm_hready_n,
+ TSM_HDATA_EN_N_IN => tsm_hdataout_en_n,
+ -- Debug
+ DEBUG_OUT => open
+ );
+
+ -- initializes MAC after AN is complete
+ THE_FW_GBE_LSM: entity gbe_lsm
+ port map(
+ CLK => CLK_125,
+ RESET => RESET,
+ --
+ MAC_AN_COMPLETE_IN => an_complete,
+ MAC_READY_CONF_IN => mac_ready_conf,
+ MAC_RECONF_OUT => mac_reconf,
+ --
+ LINK_ACTIVE_OUT => link_active,
+ --
+ DEBUG => open
+ );
+
+ -- RX ringbuffer
+ THE_FW_RB: entity rx_rb
+ port map(
+ CLK => CLK_125,
+ RESET => RESET,
+ -- MAC interface (RX)
+ MAC_RX_DATA_IN => mac_rx_data,
+ MAC_RX_WR_IN => mac_rx_wr,
+ MAC_RX_EOF_IN => mac_rx_eof,
+ MAC_RX_ERROR_IN => mac_rx_err,
+ MAC_RX_FIFOFULL_OUT => mac_rx_fifofull,
+ -- FIFO interface (TX)
+ FIFO_FULL_IN => FIFO_FULL_IN,
+ FIFO_WR_OUT => FIFO_WR_OUT,
+ FIFO_Q_OUT => FIFO_DATA_OUT,
+ FRAME_REQ_IN => FRAME_REQ_IN,
+ FRAME_ACK_OUT => FRAME_ACK_OUT,
+ FRAME_AVAIL_OUT => FRAME_AVAIL_OUT,
+ FRAME_START_OUT => FRAME_START_OUT,
+ --
+ DEBUG => open
+ );
+
+ -- TX FIFO
+ THE_FW_FIFO: entity tx_fifo
+ port map(
+ CLK => CLK_125,
+ RESET => RESET,
+ -- MAC interface
+ MAC_TX_DATA_OUT => mac_tx_data,
+ MAC_TX_READ_IN => mac_tx_read,
+ MAC_FIFOEOF_OUT => mac_fifoeof,
+ MAC_FIFOEMPTY_OUT => mac_fifoempty,
+ MAC_FIFOAVAIL_OUT => mac_fifoavail,
+ MAC_TX_DONE_IN => mac_tx_done, -- not used
+ -- FIFO interface
+ FIFO_FULL_OUT => fifo_full_i, --FIFO_FULL_OUT,
+ FIFO_WR_IN => FIFO_WR_IN,
+ FIFO_D_IN => FIFO_DATA_IN,
+ -- Link stuff
+ FRAME_START_IN => FRAME_START_IN,
+ LINK_ACTIVE_IN => link_active,
+ --
+ DEBUG => open
+ );
+
+ FIFO_FULL_OUT <= fifo_full_i;
+
+ PCS_AN_READY_OUT <= an_complete; -- needed for internal SCTRL
+ LINK_ACTIVE_OUT <= link_active;
+
+ -- Status signals
+ STATUS_OUT(7) <= '0'; -- unused
+ STATUS_OUT(6) <= link_active; -- link is active
+ STATUS_OUT(5) <= led_activity(1); -- long LED signal for activity
+ STATUS_OUT(4) <= pcs_rx_en; -- SerDes RX activity
+ STATUS_OUT(3) <= pcs_tx_en; -- SerDes TX activity
+ STATUS_OUT(2) <= an_complete; -- GbE Autonegotiation completed
+ STATUS_OUT(1) <= link_rx_ready; -- SerDes Rx channel operational
+ STATUS_OUT(0) <= link_tx_ready; -- SerDes TX channel operational
+
+ THE_LED_TIMER_PROC: process( CLK_125 )
+ begin
+ if( rising_edge(CLK_125) ) then
+ led_timer_done <= led_timer_done_x;
+ led_timer <= led_timer + 1;
+ end if;
+ end process THE_LED_TIMER_PROC;
+
+ led_timer_done_x <= '1' when (std_logic_vector(led_timer) = x"fffff") else '0';
+
+ led_activity_x <= pcs_rx_en or pcs_tx_en;
+
+ THE_LED_ACT_PROC: process( CLK_125 )
+ begin
+ if( rising_edge(CLK_125) ) then
+ if( led_activity_x = '1' ) then
+ led_activity(0) <= '1';
+ end if;
+ if( led_timer_done = '1' ) then
+ led_activity <= led_activity(0) & '0';
+ end if;
+ end if;
+ end process THE_LED_ACT_PROC;
+
+ --------------------------------------------------------------------
+ --------------------------------------------------------------------
+ DEBUG_OUT <= debug;
+ -- debug(19..0) are on INTCOM
+ -- debug(33..20) are on GPIO
+ -- 33 = CLK2 (white/green)
+ -- 32 = CLK1 (white/blue)
+ --------------------------------------------------------------------
+ --------------------------------------------------------------------
+
+-- -- "Good" debugging pins
+-- debug(7 downto 0) <= sd_tx_data;
+-- debug(15 downto 8) <= sd_rx_data;
+-- debug(16) <= sd_tx_kcntl(0);
+-- debug(17) <= sd_rx_kcntl(0);
+-- debug(18) <= RESET;
+-- debug(19) <= CLEAR;
+-- -- "Bad" debugging pins
+-- debug(20) <= pll_lol;
+-- debug(21) <= rx_cdr_lol;
+-- debug(22) <= rx_los_low;
+-- debug(23) <= sd_rx_cv_error(0);
+-- debug(24) <= lsm_status;
+-- debug(25) <= mr_main_reset;
+-- debug(26) <= mr_an_enable;
+-- debug(27) <= mr_restart_an;
+-- debug(28) <= mr_page_rx;
+-- debug(29) <= an_complete;
+-- debug(30) <= an_link_ok;
+-- debug(31) <= link_active;
+-- debug(32) <= '0';
+-- debug(33) <= CLK_125;
+
+end architecture RTL;
jspc29 / trbnet.git / commitdiff