adding a register to read the mupix clock speed

diff --git a/mupix/Mupix8/sources/Datapath/MuPixDataLink_new.vhd b/mupix/Mupix8/sources/Datapath/MuPixDataLink_new.vhd
index e681891dcb7cc2546776df5130413cf3899a65e1..cbe3b63350ff5afb870afb09de3fb6cccfdeafcd 100644 (file)
--- a/mupix/Mupix8/sources/Datapath/MuPixDataLink_new.vhd
+++ b/mupix/Mupix8/sources/Datapath/MuPixDataLink_new.vhd
@@ -17,7 +17,7 @@ entity MupixDataLinkWithUnpacker is
     g_clock_speed       : clk_speed_t          := c_40MHz
     );
   port(
-    sysclk               : in  std_logic;  --trb system clock (typically 100 MHz) 
+    sysclk               : in  std_logic;  --trb system clock (typically 100 MHz)
     dataclk              : in  std_logic;  --mupix link clock from FPGA PLL(50 - 150 MHz)
     rst                  : in  std_logic;  --synchronous reset
     clear                : in  std_logic;  --asynchronous reset
@@ -156,6 +156,9 @@ architecture rtl of MupixDataLinkWithUnpacker is
   signal unpacker_valid_i  : std_logic_vector(c_links - 1 downto 0) := (others => '0');
   signal unpacker_hit_en_i : std_logic_vector(3 downto 0);
 
+  -- clock speed register
+  constant clk_speed_mhz     : integer range 0 to 127 := clk_speed_to_mhz(g_clock_speed);
+
   -- slow control resets
   signal reset_counters_i : std_logic := '0';
   signal reset_quad_i     : std_logic := '0';
@@ -625,7 +628,7 @@ begin
             when x"0163" =>
               slv_ack_out           <= '1';
               serdes_channel_select <= to_integer(unsigned(SLV_DATA_IN_i(1 downto 0)));
-            when x"016c" => 
+            when x"016c" =>
                 fifo_enable_i <= SLV_DATA_IN_i(3 downto 0);
                 slv_ack_out   <= '1';
             when others =>
@@ -661,6 +664,9 @@ begin
             when x"016b" =>
               slv_ack_out              <= '1';
               slv_data_out(7 downto 0) <= unpacker_valid_i & (link_sync_flag_i and not rx_dataerror_sync);
+            when x"016d" =>
+              slv_ack_out <= '1';
+              slv_data_out <= std_logic_vector(to_unsigned(clk_speed_mhz, 32));
             when others =>
               slv_unknown_addr_out <= '1';
           end case;

diff --git a/mupix/Mupix8/sources/constants.vhd b/mupix/Mupix8/sources/constants.vhd
index c936f36aa2cccb85b9ec2b06c6a3021f9fdaaf5c..beab60154b10820f1941767df10261c77cb54eb1 100644 (file)
--- a/mupix/Mupix8/sources/constants.vhd
+++ b/mupix/Mupix8/sources/constants.vhd
@@ -19,4 +19,25 @@ package Constants is
   constant c_80MHz  : clk_speed_t := 2;
   constant c_125MHz : clk_speed_t := 3;
 
+  function clk_speed_to_mhz(speed_constant : clk_speed_t) return integer;
+
 end package Constants;
+
+package body Constants is
+
+  function clk_speed_to_mhz(speed_constant : clk_speed_t) return integer is
+    begin
+      if speed_constant = c_40MHz then
+        return 40;
+      elsif speed_constant = c_60MHz then
+        return 60;
+      elsif speed_constant = c_80MHz then
+        return 80;
+      elsif speed_constant = c_125MHz then
+        return 125;
+      else
+        return 0;
+      end if;
+    end clk_speed_to_mhz;
+
+end Constants;