small changes to trb_net_apimbuf_fast_lvds.vhd, Jan

diff --git a/trb_net_apimbuf_fast_lvds.vhd b/trb_net_apimbuf_fast_lvds.vhd
index 4b2bd5d643801434efbd6136da00b7b87c93eb0c..0fcf5516afe8b6af1c69182cd9b2594885d58332 100644 (file)
--- a/trb_net_apimbuf_fast_lvds.vhd
+++ b/trb_net_apimbuf_fast_lvds.vhd
@@ -14,7 +14,7 @@ USE IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 entity trb_net_apimbuf_fast_lvds is
   generic (
-    API_TYPE : integer range 0 to 1 := 1  --0: passive, 1: active api
+    API_TYPE : integer range 0 to 1 := 0  --0: passive, 1: active api
     );
   port(
     CLK    : in std_logic;      
@@ -282,20 +282,6 @@ architecture trb_net_apimbuf_fast_lvds_arch of trb_net_apimbuf_fast_lvds is
 -----------------------------------------------------------------------
 --API signals
 -----------------------------------------------------------------------
-  signal API_apl_data_out_IN : std_logic_vector(47 downto 0);
-  signal API_apl_write_IN : std_logic;
-  signal API_apl_fifo_full_OUT : std_logic;
-  signal API_apl_short_transfer_IN : std_logic;
-  signal API_apl_dtype_IN : std_logic_vector(3 downto 0);
-  signal API_apl_error_pattern_IN : std_logic_vector(31 downto 0);
-  signal API_apl_send_IN : std_logic;
-  signal API_apl_target_address_IN : std_logic_vector(15 downto 0);
-  signal API_APL_DATA_OUT : std_logic_vector(47 downto 0);
-  signal API_APL_TYP_OUT : std_logic_vector(2 downto 0);
-  signal API_APL_DATAREADY_OUT : std_logic;
-  signal API_APL_READ_IN : std_logic;
-  signal API_APL_RUN_OUT : std_logic;
-  signal API_APL_SEQNR_OUT : std_logic_vector(7 downto 0);
   signal API_MED_DATAREADY_OUT : std_logic;
   signal API_MED_DATA_OUT : std_logic_vector(51 downto 0);
   signal API_MED_READ_IN : std_logic;
@@ -307,48 +293,11 @@ architecture trb_net_apimbuf_fast_lvds_arch of trb_net_apimbuf_fast_lvds is
   signal API_ctrl : std_logic_vector(31 downto 0);
   
   signal C5518_D55_DATA_IN, C5518_D55_DATA_OUT : std_logic_vector(55 downto 0);
------------------------------------------------------------------------
---APL signals
------------------------------------------------------------------------ 
-  signal APL1_DATA_OUT: STD_LOGIC_VECTOR (47 downto 0);
-  signal APL1_WRITE_OUT: STD_LOGIC;
-  signal APL1_FIFO_FULL_IN: STD_LOGIC;
-  signal APL1_SHORT_TRANSFER_OUT: STD_LOGIC;
-  signal APL1_DTYPE_OUT: STD_LOGIC_VECTOR (3 downto 0);
-  signal APL1_ERROR_PATTERN_OUT: STD_LOGIC_VECTOR (31 downto 0);
-  signal APL1_SEND_OUT: STD_LOGIC;
-  signal APL1_TARGET_ADDRESS_OUT: STD_LOGIC_VECTOR (15 downto 0); 
-  signal APL1_DATA_IN: STD_LOGIC_VECTOR (47 downto 0);
-  signal APL1_TYP_IN: STD_LOGIC_VECTOR (2 downto 0);
-  signal APL1_DATAREADY_IN: STD_LOGIC; 
-  signal APL1_READ_OUT: STD_LOGIC;
-  signal APL1_RUN_IN: STD_LOGIC;
-  signal APL1_SEQNR_IN: STD_LOGIC_VECTOR (7 downto 0);
 
 -----------------------------------------------------------------------
 --Control signals
 ----------------------------------------------------------------------- 
-  signal apl1_reset, next_apl1_reset: std_logic;
-  signal CTRL_reg_apl1, next_CTRL_reg_apl1: std_logic_vector(31 downto 0);
-                          -- Bit 0: switches apl on/off
-  signal STAT_reg_apl1, next_STAT_reg_apl1 : std_logic_vector(31 downto 0);
-  signal STAT_reg_lvds1 : std_logic_vector(31 downto 0);
-  signal CTRL_reg_lvds1, next_CTRL_reg_lvds1 : std_logic_vector(31 downto 0);
-  signal CTRL_reg_global, next_CTRL_reg_global : std_logic_vector(31 downto 0);
-
-  signal next_buf_DATA_OUT, buf_DATA_OUT: std_logic_vector(31 downto 0);
-
-  signal API1_STAT_GEN: std_logic_vector(31 downto 0);
-  signal API1_STAT_LOCKED: std_logic_vector(31 downto 0);
-  signal API1_STAT_INIT_BUFFER: std_logic_vector(31 downto 0);
-  signal API1_STAT_REPLY_BUFFER: std_logic_vector(31 downto 0);
-  signal CTRL_reg_lvds_output_select, next_CTRL_reg_lvds_output_select: std_logic_vector(31 downto 0);
-  signal STAT_CUSTOM, next_STAT_CUSTOM: std_logic_vector(31 downto 0);
-  signal std_LVDS_out: std_logic_vector(31 downto 0);
-  signal API1_STAT_api_control_signals: std_logic_vector(31 downto 0); 
-  signal buf_LVDS_OUT, comb_LVDS_OUT: std_logic_vector(31 downto 0);
-  signal API1_API_STAT_FIFO_TO_INT: std_logic_vector(31 downto 0);
-  signal API1_API_STAT_FIFO_TO_APL: std_logic_vector(31 downto 0);  
+
   
   
 begin
@@ -463,7 +412,7 @@ begin
         MED_DATAREADY_OUT => API_MED_DATAREADY_OUT,
         MED_DATA_OUT      => API_MED_DATA_OUT,
         MED_READ_IN       => API_MED_READ_IN,
-        MED_ERROR_IN      => API_MED_ERROR_IN,
+        MED_ERROR_IN      => LVDS_INT_ERROR_OUT,
         MED_DATAREADY_IN  => API_MED_DATAREADY_IN,
         MED_DATA_IN       => API_MED_DATA_IN,
         MED_READ_OUT      => API_MED_READ_OUT,