<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="dpram_32x512" module="RAM_DP" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 02 19 17:49:10.530" version="6.1" type="Module" synthesis="synplify" source_format="VHDL">
+<DiamondModule name="dpram_32x512" module="RAM_DP" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 02 20 17:02:38.118" version="6.1" type="Module" synthesis="synplify" source_format="VHDL">
<Package>
- <File name="" type="mem" modified="2015 02 19 17:49:10.000"/>
- <File name="dpram_32x512.lpc" type="lpc" modified="2015 02 19 17:49:08.000"/>
- <File name="dpram_32x512.vhd" type="top_level_vhdl" modified="2015 02 19 17:49:08.000"/>
- <File name="dpram_32x512_tmpl.vhd" type="template_vhdl" modified="2015 02 19 17:49:08.000"/>
- <File name="tb_dpram_32x512_tmpl.vhd" type="testbench_vhdl" modified="2015 02 19 17:49:08.000"/>
+ <File name="" type="mem" modified="2015 02 20 17:02:37.000"/>
+ <File name="dpram_32x512.lpc" type="lpc" modified="2015 02 20 17:02:35.000"/>
+ <File name="dpram_32x512.vhd" type="top_level_vhdl" modified="2015 02 20 17:02:36.000"/>
+ <File name="dpram_32x512_tmpl.vhd" type="template_vhdl" modified="2015 02 20 17:02:36.000"/>
+ <File name="tb_dpram_32x512_tmpl.vhd" type="testbench_vhdl" modified="2015 02 20 17:02:36.000"/>
</Package>
</DiamondModule>
-- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
-- Module Version: 6.1
---/home/soft/lattice/diamond/2.1_x64/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 10 -rp 0011 -rdata_width 32 -data_width 32 -num_rows 512 -outdata REGISTERED -cascade -1 -e
+--/home/soft/lattice/diamond/2.1_x64/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 10 -rp 0011 -rdata_width 32 -data_width 32 -num_rows 512 -cascade -1 -e
--- Thu Feb 19 17:49:08 2015
+-- Fri Feb 20 17:02:36 2015
library IEEE;
use IEEE.std_logic_1164.all;
dpram_32x512_0_0_0: PDPW16KC
generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED",
- REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
+ REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),