update included features table

diff --git a/trb3/IncludedFeaturesTable.tex b/trb3/IncludedFeaturesTable.tex
index 3f319ef037422f0ff3199e78bef08d6347e792f4..17ebc347731d71b4cd638d1a6f4fbd1c2121c281 100644 (file)
--- a/trb3/IncludedFeaturesTable.tex
+++ b/trb3/IncludedFeaturesTable.tex
@@ -6,7 +6,7 @@
 \hline\hline
 1 & \multicolumn{3}{X|}{``Central'' - For a normal central FPGA design with Cts and/or GbE}\\
  & 3 -- 0   & ExtModule   & Type of external trigger module (0: none, 1: CBM MBS, 2: Mainz M2)\\ 
- & 11 -- 8  & DoubleEdge  & See table 2.\\
+ & 14 -- 8  & DoubleEdge  & See table 2.\\
  & 15       & TDC         & The design contains a TDC module. \\
  & 16       & GbeData     & Event data is sent via GbE \\
  & 17       & GbeCtrl     & FPGA accepts slow-control messages via GbE \\
@@ -34,12 +34,11 @@ Through Clock Manager (cbmtof only)\\
  & 7 -- 0   & Pinout      & Which pin-out is being used for the TDC inputs. 0: flexible by multiplexers, 1: default 
 1-to-1, 2: every second input (e.g. Padiwa Amps fast-only), 3: every fourth input (HPTDC very high speed mode), 128: 32pin AddOn, 129: 4conn, 130: 2x KEL on-board, 131: ADA plus test signals, 132: ADA every fourth input\\
  & 11 -- 8  & DoubleEdge  & Double edge setup: 0: single edge only, 1: same channel, 2: alternating channels, 3: same 
-channel with stretcher \\
+channel with stretcher, 5: clocked TDC, both edges, no stretcher \\
  & 14 -- 12 & RingBuffer  & Ring Buffer size: 0:12 words, 1:44 words, 2:76 
 words, 3:108 words, 7:dynamic \\
  & 15       & TDC         & Contains a TDC \\
- & 18 -- 16 & ReadoutModule & Number of readout modules minus 1 \\
- & 55 -- 40 &             & See table 1\\
+ & 55 -- 16 &             & See table 1\\
 \hline\hline
 3 & \multicolumn{3}{X|}{``MVD'' - For CBM-MVD designs.}\\
  & 7 -- 0   & Sensors     & Number of sensor inputs \\