MULTICYCLE FROM CLKNET "CLK_EXT_c" TO CLKNET "clk_100_i_c" 2 X ;
LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_0_200_ctc.THE_SERDES/PCSD_INST" SITE "PCSA" ;
+LOCATE COMP "gen_norm_uplink/THE_MEDIA_UPLINK/gen_serdes_0_200_ctc.THE_SERDES/PCSD_INST" SITE "PCSA" ;
+LOCATE COMP "gen_sync_uplink/THE_MEDIA_UPLINK/THE_SERDES/PCSD_INST" SITE "PCSA" ;
#################################################################
# Clock I/O
add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd"
add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd"
add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd"
-
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload.vhd"
add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd"
add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_0.vhd"
###############
--- /dev/null
+#!/usr/bin/perl
+use Data::Dumper;
+use warnings;
+use strict;
+use FileHandle;
+use Getopt::Long;
+
+###################################################################################
+#Settings for this project
+my $TOPNAME = "cbmtof"; #Name of top-level entity
+my $lm_license_file_for_synplify = "1702\@hadeb05.gsi.de"; #"27000\@lxcad01.gsi.de";
+my $lm_license_file_for_par = "1702\@hadeb05.gsi.de";
+
+my $lattice_path = '/d/jspc29/lattice/diamond/3.4_x64';
+my $synplify_path = '/d/jspc29/lattice/synplify/J-2014.09-SP2/';
+my $lattice_bin_path = "$lattice_path/bin/lin64"; # note the lin/lin64 at the end, no isfgpa needed
+###################################################################################
+
+###################################################################################
+#Options for the script
+my $help = "";
+my $isMultiPar = 0; # set it to zero for single par run on the local machine
+my $nrNodes = 0; # set it to one for single par run on the local machine
+my $all = 1;
+my $syn = 0;
+my $map = 0;
+my $par = 0;
+my $timing = 0;
+my $bitgen = 0;
+
+my $result = GetOptions (
+ "h|help" => \$help,
+ "m|mpar=i" => \$nrNodes,
+ "a|all" => \$all,
+ "s|syn" => \$syn,
+ "mp|map" => \$map,
+ "p|par" => \$par,
+ "t|timing" => \$timing,
+ "b|bitgen" => \$bitgen,
+ );
+
+if($help) {
+ print "Usage: compile_priph_gsi.de <OPTIONS><ARGUMENTS>\n\n";
+ print "-h --help\tPrints the usage manual.\n";
+ print "-a --all\tRun all compile script. By default the script is going to rung the whole process.\n";
+ print "-s --syn\tRun synthesis part of the compile script.\n";
+ print "-mp --map\tRun map part of the compile script.\n";
+ print "-p --par\tRun par part of the compile script.\n";
+ print "-t --timing\tRun timing analysis part of the compile script.\n";
+ print "-b --bitgen\tRun bit generation part of the compile script.\n";
+ print "-m --mpar\tSwitch for multi par. \"-m <number_of_nodes>\" (Default = off)\n";
+ print "\t\tThe node list file name has to be edited in the script. (Default = nodes_lxhadeb07.txt)\n";
+ print "\n";
+ exit;
+}
+
+if ($nrNodes!=0){
+ $isMultiPar=1;
+}
+if ($syn!=0 || $map!=0 || $par!=0 || $timing!=0 || $bitgen!=0){
+ $all=0;
+}
+###################################################################################
+
+
+
+# source the standard lattice environment
+# $ENV{bindir}="$lattice_bin_path";
+# open my $SOURCE, "bash -c '. $lattice_bin_path/diamond_env >& /dev/null; env'|" or
+# die "Can't fork: $!";
+# while (<$SOURCE>) {
+# if (/^(.*)=(.*)/) {
+# $ENV{$1} = ${2} ;
+# }
+# }
+# close $SOURCE;
+
+
+$ENV{'PAR_DESIGN_NAME'}=$TOPNAME;
+$ENV{'SYNPLIFY'}=$synplify_path;
+$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1;
+$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify;
+
+
+my $FAMILYNAME="LatticeECP3";
+my $DEVICENAME="LFE3-150EA";
+my $PACKAGE="FPBGA672";
+my $SPEEDGRADE="8";
+
+my $WORKDIR = "workdir";
+unless(-d $WORKDIR) {
+ mkdir $WORKDIR or die "can't create workdir '$WORKDIR': $!";
+}
+
+system("ln -sfT $lattice_path $WORKDIR/lattice-diamond");
+
+#create full lpf file
+system("cp ../base/$TOPNAME.lpf $WORKDIR/$TOPNAME.lpf");
+system("cat currentRelease/trbnet_constraints.lpf >> $WORKDIR/$TOPNAME.lpf");
+system("cat currentRelease/tdc_constraints_64.lpf >> $WORKDIR/$TOPNAME.lpf");
+system("cat currentRelease/unimportant_lines_constraints.lpf >> $WORKDIR/$TOPNAME.lpf");
+system("cat unimportant_lines_constraints.lpf >> $WORKDIR/$TOPNAME.lpf");
+
+
+#generate timestamp
+my $t=time;
+my $fh = new FileHandle(">version.vhd");
+die "could not open file" if (! defined $fh);
+print $fh <<EOF;
+
+--## attention, automatically generated. Don't change by hand.
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+use ieee.numeric_std.all;
+
+package version is
+
+ constant VERSION_NUMBER_TIME : integer := $t;
+
+end package version;
+EOF
+$fh->close;
+
+system("env| grep LM_");
+my $r = "";
+my $c = "";
+my @a = ();
+my $tpmap = $TOPNAME . "_map" ;
+
+if($syn==1 || $all==1){
+# $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj";
+ $c="$lattice_path/bin/lin64/synpwrap -fg -options -batch $TOPNAME.prj";
+ $r=execute($c, "do_not_exit" );
+}
+
+chdir $WORKDIR;
+
+if($syn==1 || $all==1){
+ $fh = new FileHandle("<$TOPNAME".".srr");
+ @a = <$fh>;
+ $fh -> close;
+
+ foreach (@a)
+ {
+ if(/\@E:/)
+ {
+ print "\n";
+ $c="cat $TOPNAME.srr | grep \"\@E\"";
+ system($c);
+ print "\n\n";
+ exit 129;
+ }
+ }
+}
+
+$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par;
+
+if($map==1 || $all==1){
+ $c=qq| edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |;
+ execute($c);
+
+ $c=qq|edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|;
+ execute($c);
+
+ $c=qq|ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|;
+ execute($c);
+
+ $c=qq|map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|;
+ execute($c);
+
+ $c=qq|htmlrpt -mrp $TOPNAME.mrp $TOPNAME|;
+ execute($c);
+
+ $fh = new FileHandle("<$TOPNAME"."_mrp.html");
+ @a = <$fh>;
+ $fh -> close;
+ foreach (@a)
+ {
+ if(/FC_|HitInvert|ff_en_/)
+ {
+ print "\n\n";
+ print "#################################################\n";
+ print "# !!!Possible Placement Errors!!! #\n";
+ print "#################################################\n\n";
+
+ my $c="egrep 'WARNING.*hitBuf_|Channels/hit_buf_RNO|WARNING.*FC_|Channels/Channel200/SimAdderNo_FC|WARNING.*ff_en_|Channels/Channel200/ff_array_en_i_1_i'"." $TOPNAME"."_mrp.html";
+ system($c);
+ last;
+ }
+ }
+}
+
+if($par==1 || $all==1){
+ system("rm $TOPNAME.ncd");
+ #$c=qq|mpartrce -p "../$TOPNAME.p2t" -log "$TOPNAME.log" -o "$TOPNAME.rpt" -pr "$TOPNAME.prf" -tf "$TOPNAME.pt" "|.$TOPNAME.qq|_map.ncd" "$TOPNAME.ncd"|;
+ #$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|;
+ if ($isMultiPar)
+ {
+ #$c=qq|par -m ../nodes_lxhadeb07.txt -n $nrNodes -stopzero -w -l 5 -t 1 -e 100 -exp parDisablePgroup=0:parUseNBR=1:parCDP=1:parPathBased=ON $tpmap.ncd $TOPNAME.dir $TOPNAME.prf|;
+ #$c=qq|par -m ../nodes_lxhadeb07.txt -n $nrNodes -stopzero -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parDisablePgroup=0:parUseNBR=1:parCDP=0:parCDR=0:parPathBased=ON $tpmap.ncd $TOPNAME.dir $TOPNAME.prf|;
+ $c=qq|par -m ../nodes_lxhadeb07.txt -n $nrNodes -w -l 5 -t 1 $tpmap.ncd $TOPNAME.dir $TOPNAME.prf|;
+ execute($c);
+ # find and copy the .ncd file which has met the timing constraints
+ $fh = new FileHandle("<$TOPNAME".".par");
+ my @a = <$fh>;
+ my $isSuccess = 0;
+ $fh -> close;
+ foreach (@a)
+ {
+ my @line = split(' ', $_);
+ if(@line && ($line[2] =~ m/^[0-9]+$/) && ($line[3] =~ m/^[0-9]+$/))
+ {
+ if(($line[2] == 0) && ($line[3] == 0))
+ {
+ print "Copying $line[0].ncd file to workdir\n";
+ my $c="cp $TOPNAME.dir/$line[0].ncd $TOPNAME.ncd";
+ system($c);
+ print "\n\n";
+ $isSuccess = 1;
+ last;
+ }
+ }
+ }
+
+ if (!$isSuccess){
+ print "\n\n";
+ print "#################################################\n";
+ print "# !!!PAR not succesfull!!! #\n";
+ print "#################################################\n\n";
+ exit 129;
+ }
+ }
+ else
+ {
+ #$c=qq|par -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=ON $tpmap.ncd $TOPNAME.dir $TOPNAME.prf|;
+ $c=qq|par -w -l 5 -t 1 $tpmap.ncd $TOPNAME.dir $TOPNAME.prf|;
+ execute($c);
+ my $c="cp $TOPNAME.dir/5_1.ncd $TOPNAME.ncd";
+ system($c);
+ }
+ my $c="cat $TOPNAME.par";
+ system($c);
+
+}
+
+
+if($timing==1 || $all==1){
+ # IOR IO Timing Report
+ $c=qq|iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|;
+ execute($c);
+
+ # TWR Timing Report
+ $c=qq|trce -c -v 65 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|;
+ execute($c);
+
+ $c=qq|trce -hld -c -v 65 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|;
+ execute($c);
+
+ $c=qq|ltxt2ptxt $TOPNAME.ncd|;
+ execute($c);
+
+ my $c="cat $TOPNAME.par";
+ system($c);
+
+}
+
+if($bitgen==1 || $all==1){
+ $c=qq|bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No $TOPNAME.ncd $TOPNAME.bit $TOPNAME.prf|;
+ # $c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|;
+ execute($c);
+}
+
+$c=qq|htmlrpt -mrp $TOPNAME.mrp -mtwr $TOPNAME.twr.hold -ptwr $TOPNAME.twr.setup $TOPNAME|;
+execute($c);
+
+$c=qq|firefox $TOPNAME.html|;
+execute($c);
+
+chdir "..";
+exit;
+
+sub execute {
+ my ($c, $op) = @_;
+ #print "option: $op \n";
+ $op = "" if(!$op);
+ print "\n\ncommand to execute: $c \n";
+ $r=system($c);
+ if($r) {
+ print "$!";
+ if($op ne "do_not_exit") {
+ exit;
+ }
+ }
+ return $r;
+}
--TDC settings
constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement
- constant NUM_TDC_CHANNELS : integer range 1 to 65 := 33; -- number of tdc channels per module
+ constant NUM_TDC_CHANNELS : integer range 1 to 65 := 5; -- number of tdc channels per module
constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons
constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3
-- 0: single edge only,
--Run wih 125 MHz instead of 100 MHz, use received clock from serdes or external clock input
constant USE_125_MHZ : integer := c_NO; --not implemented yet!
- constant USE_RXCLOCK : integer := c_NO; --not implemented yet!
+ constant USE_RXCLOCK : integer := c_YES; --not implemented yet!
constant USE_EXTERNALCLOCK : integer := c_YES;
constant USE_CLK_MANAGER_REF_TIME : integer := c_YES; --reference time through clk manager or direct
signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
signal clk_tdc_i : std_logic; --clock for the TDC
signal clk_osc_int : std_logic; -- clock for calibrating the tdc, 2.5 MHz, via internal osscilator
+ signal clk_100_osc : std_logic;
+ signal rx_clock_100 : std_logic;
+ signal rx_clock_200 : std_logic;
signal clk_cal : std_logic; -- clock for calibrating the tdc, 100 MHz, via pll
signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
signal pll_lock_1 : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
CLEAR_IN => '0', -- reset input (high active, async)
CLEAR_N_IN => '1', -- reset input (low active, async)
CLK_IN => clk_200_i, -- raw master clock, NOT from PLL/DLL!
- SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock
+ SYSCLK_IN => clk_100_osc, -- PLL/DLL remastered clock
PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)
RESET_IN => '0', -- general reset signal (SYSCLK)
TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK)
port map (
CLK => CLK_OSC,
RESET => '0',
- CLKOP => clk_100_i, -- 100 MHz
+ CLKOP => clk_100_osc, -- 100 MHz
CLKOK => clk_200_i, -- 200 MHz, bypass
LOCK => pll_lock_1);
clk_cal <= clk_100_i;
- TDC_Clock_Int : if USE_EXTERNALCLOCK = 0 generate
+ TDC_Clock_Int : if USE_EXTERNALCLOCK = 0 and USE_RXCLOCK = 0 generate
clk_tdc_i <= CLK_OSC; -- Oscillator used for the time measurement
end generate TDC_Clock_Int;
- TDC_Clock_Ext : if USE_EXTERNALCLOCK = 1 generate
+ TDC_Clock_Ext : if USE_EXTERNALCLOCK = 1 and USE_RXCLOCK = 0 generate
clk_tdc_i <= CLK_EXT; -- External Clock used for the time measurement
end generate TDC_Clock_Ext;
+ TDC_Clock_Rx : if USE_EXTERNALCLOCK = 0 and USE_RXCLOCK = 1 generate
+ clk_tdc_i <= rx_clock_200; -- Recovered Clock used for the time measurement
+ end generate;
+
---------------------------------------------------------------------------
-- The TrbNet media interface (to other FPGA)
---------------------------------------------------------------------------
+gen_norm_uplink : if USE_RXCLOCK = c_NO generate
THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp
generic map(
SERDES_NUM => 0, --number of serdes in quad
STAT_DEBUG => med_stat_debug,
CTRL_DEBUG => (others => '0')
);
+ clk_100_i <= clk_100_osc;
+end generate;
+
+gen_sync_uplink : if USE_RXCLOCK = c_YES generate
+ THE_MEDIA_UPLINK : med_ecp3_sfp_sync
+ generic map(
+ SERDES_NUM => 0, --number of serdes in quad
+ IS_SYNC_SLAVE => c_YES
+ )
+ port map(
+ CLK => clk_200_i,
+ SYSCLK => clk_100_i,
+ RESET => reset_i,
+ CLEAR => clear_i,
+ --Internal Connection for TrbNet data -> not used a.t.m.
+ MED_DATA_IN => med_data_out,
+ MED_PACKET_NUM_IN => med_packet_num_out,
+ MED_DATAREADY_IN => med_dataready_out,
+ MED_READ_OUT => med_read_in,
+ MED_DATA_OUT => med_data_in,
+ MED_PACKET_NUM_OUT => med_packet_num_in,
+ MED_DATAREADY_OUT => med_dataready_in,
+ MED_READ_IN => med_read_out,
+ CLK_RX_HALF_OUT => rx_clock_100,
+ CLK_RX_FULL_OUT => rx_clock_200,
+
+ RX_DLM => open,
+ RX_DLM_WORD => open,
+ TX_DLM => '0',
+ TX_DLM_WORD => (others => '0'),
+ --SFP Connection
+ SD_RXD_P_IN => SERDES_RX(0),
+ SD_RXD_N_IN => SERDES_RX(1),
+ SD_TXD_P_OUT => SERDES_TX(0),
+ SD_TXD_N_OUT => SERDES_TX(1),
+ SD_REFCLK_P_IN => open,
+ SD_REFCLK_N_IN => open,
+ SD_PRSNT_N_IN => SFP_MOD(0),
+ SD_LOS_IN => SFP_LOS,
+ SD_TXDIS_OUT => SFP_TXDIS,
+
+ SCI_DATA_IN => (others => '0'),
+ SCI_DATA_OUT => open,
+ SCI_ADDR => (others => '0'),
+ SCI_READ => '0',
+ SCI_WRITE => '0',
+ SCI_ACK => open,
+ SCI_NACK => open,
+ -- Status and control port
+ STAT_OP => med_stat_op,
+ CTRL_OP => med_ctrl_op,
+ STAT_DEBUG => med_stat_debug,
+ CTRL_DEBUG => (others => '0')
+ );
+ clk_100_i <= rx_clock_100;
+end generate;
+
---------------------------------------------------------------------------
-- Endpoint
jspc29 / trb3.git / commitdiff