-- USED_PORTS : std_logic-vector(3 downto 0) := "1111"
);
port(
- CLK : in std_logic; -- SerDes clock
- SYSCLK : in std_logic; -- fabric clock
+ CLK : in std_logic; -- SerDes clock
+ SYSCLK : in std_logic; -- fabric clock
RESET : in std_logic; -- synchronous reset
CLEAR : in std_logic; -- asynchronous reset
CLK_EN : in std_logic;
SD_REFCLK_N_IN : in std_logic;
SD_PRSNT_N_IN : in std_logic_vector(3 downto 0); -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
SD_LOS_IN : in std_logic_vector(3 downto 0); -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+ SD_TXDIS_OUT : out std_logic; -- SFP disable
-- Status and control port
STAT_OP : out std_logic_vector (4*16-1 downto 0);
CTRL_OP : in std_logic_vector (4*16-1 downto 0);
signal rx_data : std_logic_vector(4*16-1 downto 0);
signal rx_k : std_logic_vector(7 downto 0);
signal link_ok : std_logic_vector(3 downto 0);
-
+ signal comb_rx_data : std_logic_vector(4*16 downto 0); -- original signals from SFP
+ signal comb_rx_k : std_logic_vector(7 downto 0); -- original signals from SFP
signal ff_rxhalfclk : std_logic_vector(3 downto 0);
signal ff_txhalfclk : std_logic;
--rx fifo signals
signal last_fifo_tx_empty : std_logic_vector(3 downto 0);
--link status
signal rx_k_q : std_logic_vector(4*2-1 downto 0);
+ signal tx_k_q : std_logic_vector(4*2-1 downto 0);
signal ffs_plol : std_logic;
signal quad_rst : std_logic_vector(3 downto 0);
signal lane_rst : std_logic_vector(3 downto 0);
signal tx_allow : std_logic_vector(3 downto 0);
signal rx_allow : std_logic_vector(3 downto 0);
+ signal rx_allow_qrx : std_logic_vector(3 downto 0);
+ signal tx_allow_qtx : std_logic_vector(3 downto 0);
signal rx_allow_q : std_logic_vector(3 downto 0); -- clock domain changed signal
signal tx_allow_q : std_logic_vector(3 downto 0);
)
port map(
RESET => RESET,
- D_IN => rx_k(i*2+1 downto i*2),
+ D_IN => comb_rx_k(i*2+1 downto i*2),
CLK0 => ff_rxhalfclk(i),
CLK1 => SYSCLK,
D_OUT => rx_k_q(i*2+1 downto i*2)
);
+ THE_TX_K_SYNC: signal_sync
+ generic map(
+ DEPTH => 3,
+ WIDTH => 2
+ )
+ port map(
+ RESET => RESET,
+ D_IN => tx_k(i*2+1 downto i*2),
+ CLK0 => ff_txhalfclk,
+ CLK1 => SYSCLK,
+ D_OUT => tx_k_q(i*2+1 downto i*2)
+ );
+
+
+ -- delay line for RX_K and RX_DATA (directly from SFP to fabric logic)
+ THE_RX_DATA_DELAY: signal_sync
+ generic map(
+ DEPTH => 2,
+ WIDTH => 16
+ )
+ port map(
+ RESET => reset,
+ D_IN => comb_rx_data(i*16+15 downto i*16),
+ CLK0 => ff_rxhalfclk(i),
+ CLK1 => ff_rxhalfclk(i),
+ D_OUT => rx_data(i*16+15 downto i*16)
+ );
+
+ THE_RX_K_DELAY: signal_sync
+ generic map(
+ DEPTH => 2,
+ WIDTH => 2
+ )
+ port map(
+ RESET => reset,
+ D_IN => comb_rx_k(i*2+1 downto i*2),
+ CLK0 => ff_rxhalfclk(i),
+ CLK1 => ff_rxhalfclk(i),
+ D_OUT => rx_k(i*2+1 downto i*2)
+ );
+
+ THE_RX_ALLOW_SYNC: signal_sync -- really needed?!?
+ generic map(
+ DEPTH => 2,
+ WIDTH => 2
+ )
+ port map(
+ RESET => RESET,
+ D_IN(0) => rx_allow(i),
+ D_IN(1) => tx_allow(i),
+ CLK0 => sysclk,
+ CLK1 => sysclk,
+ D_OUT(0) => rx_allow_q(i),
+ D_OUT(1) => tx_allow_q(i)
+ );
+
+ THE_RX_ALLOW_SYNC_RX: signal_sync -- really needed?!?
+ generic map(
+ DEPTH => 2,
+ WIDTH => 1
+ )
+ port map(
+ RESET => RESET,
+ D_IN(0) => rx_allow(i),
+ CLK0 => ff_rxhalfclk(i),
+ CLK1 => ff_rxhalfclk(i),
+ D_OUT(0) => rx_allow_qrx(i)
+ );
+
+ THE_TX_ALLOW_SYNC_TX: signal_sync -- really needed?!?
+ generic map(
+ DEPTH => 2,
+ WIDTH => 1
+ )
+ port map(
+ RESET => RESET,
+ D_IN(0) => tx_allow(i),
+ CLK0 => ff_txhalfclk,
+ CLK1 => ff_txhalfclk,
+ D_OUT(0) => tx_allow_qtx(i)
+ );
+
+
----------------------------------------------------------------------------------------------------------
-- NEW STATEMACHINE START
----------------------------------------------------------------------------------------------------------
CTRL_OP => FSM_CTRL_OP(i*16+15 downto i*16),
STAT_DEBUG => FSM_STAT_DEBUG(i*32+31 downto i*32)
);
+
+
+ sd_txdis_out <= quad_rst(0);
----------------------------------------------------------------------------------------------------------
-- NEW STATEMACHINE STOP
----------------------------------------------------------------------------------------------------------
ff_txiclk_ch0 => ff_txhalfclk,
ff_ebrd_clk_0 => ff_rxhalfclk(0),
ff_txdata_ch0 => tx_data(15 downto 0),
- ff_rxdata_ch0 => rx_data(15 downto 0),
+ ff_rxdata_ch0 => comb_rx_data(15 downto 0),
ff_tx_k_cntrl_ch0 => tx_k(1 downto 0),
- ff_rx_k_cntrl_ch0 => rx_k(1 downto 0),
+ ff_rx_k_cntrl_ch0 => comb_rx_k(1 downto 0),
ff_rxhalfclk_ch0 => ff_rxhalfclk(0),
ff_force_disp_ch0 => "00",
ff_disp_sel_ch0 => "00",
ff_txiclk_ch1 => ff_txhalfclk,
ff_ebrd_clk_1 => ff_rxhalfclk(1),
ff_txdata_ch1 => tx_data(31 downto 16),
- ff_rxdata_ch1 => rx_data(31 downto 16),
+ ff_rxdata_ch1 => comb_rx_data(31 downto 16),
ff_tx_k_cntrl_ch1 => tx_k(3 downto 2),
- ff_rx_k_cntrl_ch1 => rx_k(3 downto 2),
+ ff_rx_k_cntrl_ch1 => comb_rx_k(3 downto 2),
ff_rxhalfclk_ch1 => ff_rxhalfclk(1),
ff_force_disp_ch1 => "00",
ff_disp_sel_ch1 => "00",
ff_txiclk_ch2 => ff_txhalfclk,
ff_ebrd_clk_2 => ff_rxhalfclk(2),
ff_txdata_ch2 => tx_data(47 downto 32),
- ff_rxdata_ch2 => rx_data(47 downto 32),
+ ff_rxdata_ch2 => comb_rx_data(47 downto 32),
ff_tx_k_cntrl_ch2 => tx_k(5 downto 4),
- ff_rx_k_cntrl_ch2 => rx_k(5 downto 4),
+ ff_rx_k_cntrl_ch2 => comb_rx_k(5 downto 4),
ff_rxhalfclk_ch2 => ff_rxhalfclk(2),
ff_force_disp_ch2 => "00",
ff_disp_sel_ch2 => "00",
ff_txiclk_ch3 => ff_txhalfclk,
ff_ebrd_clk_3 => ff_rxhalfclk(3),
ff_txdata_ch3 => tx_data(63 downto 48),
- ff_rxdata_ch3 => rx_data(63 downto 48),
+ ff_rxdata_ch3 => comb_rx_data(63 downto 48),
ff_tx_k_cntrl_ch3 => tx_k(7 downto 6),
- ff_rx_k_cntrl_ch3 => rx_k(7 downto 6),
+ ff_rx_k_cntrl_ch3 => comb_rx_k(7 downto 6),
ff_rxhalfclk_ch3 => ff_rxhalfclk(3),
ff_force_disp_ch3 => "00",
ff_disp_sel_ch3 => "00",
ff_txiclk_ch0 => ff_txhalfclk,
ff_ebrd_clk_0 => ff_rxhalfclk(3),
ff_txdata_ch0 => tx_data(63 downto 48),
- ff_rxdata_ch0 => rx_data(63 downto 48),
+ ff_rxdata_ch0 => comb_rx_data(63 downto 48),
ff_tx_k_cntrl_ch0 => tx_k(7 downto 6),
- ff_rx_k_cntrl_ch0 => rx_k(7 downto 6),
+ ff_rx_k_cntrl_ch0 => comb_rx_k(7 downto 6),
ff_rxhalfclk_ch0 => ff_rxhalfclk(3),
ff_force_disp_ch0 => "00",
ff_disp_sel_ch0 => "00",
ff_txiclk_ch1 => ff_txhalfclk,
ff_ebrd_clk_1 => ff_rxhalfclk(2),
ff_txdata_ch1 => tx_data(47 downto 32),
- ff_rxdata_ch1 => rx_data(47 downto 32),
+ ff_rxdata_ch1 => comb_rx_data(47 downto 32),
ff_tx_k_cntrl_ch1 => tx_k(5 downto 4),
- ff_rx_k_cntrl_ch1 => rx_k(5 downto 4),
+ ff_rx_k_cntrl_ch1 => comb_rx_k(5 downto 4),
ff_rxhalfclk_ch1 => ff_rxhalfclk(2),
ff_force_disp_ch1 => "00",
ff_disp_sel_ch1 => "00",
ff_txiclk_ch2 => ff_txhalfclk,
ff_ebrd_clk_2 => ff_rxhalfclk(1),
ff_txdata_ch2 => tx_data(31 downto 16),
- ff_rxdata_ch2 => rx_data(31 downto 16),
+ ff_rxdata_ch2 => comb_rx_data(31 downto 16),
ff_tx_k_cntrl_ch2 => tx_k(3 downto 2),
- ff_rx_k_cntrl_ch2 => rx_k(3 downto 2),
+ ff_rx_k_cntrl_ch2 => comb_rx_k(3 downto 2),
ff_rxhalfclk_ch2 => ff_rxhalfclk(1),
ff_force_disp_ch2 => "00",
ff_disp_sel_ch2 => "00",
ff_txiclk_ch3 => ff_txhalfclk,
ff_ebrd_clk_3 => ff_rxhalfclk(0),
ff_txdata_ch3 => tx_data(15 downto 0),
- ff_rxdata_ch3 => rx_data(15 downto 0),
+ ff_rxdata_ch3 => comb_rx_data(15 downto 0),
ff_tx_k_cntrl_ch3 => tx_k(1 downto 0),
- ff_rx_k_cntrl_ch3 => rx_k(1 downto 0),
+ ff_rx_k_cntrl_ch3 => comb_rx_k(1 downto 0),
ff_rxhalfclk_ch3 => ff_rxhalfclk(0),
ff_force_disp_ch3 => "00",
ff_disp_sel_ch3 => "00",
if( swap_bytes(i) = '0' ) then
fifo_rx_din(i*18+17 downto i*18) <= rx_k(i*2+1) & rx_k(i*2) & rx_data(i*16+15 downto i*16+8)
& rx_data(i*16+7 downto i*16);
- fifo_rx_wr_en(i) <= not rx_k(i*2) and rx_allow_q(i) and link_ok(i);
+ fifo_rx_wr_en(i) <= not rx_k(i*2) and rx_allow_qrx(i) and link_ok(i);
else
fifo_rx_din(i*18+17 downto i*18) <= rx_k(i*2+0) & last_rx(i*9+8) & rx_data(i*16+7 downto i*16+0)
& last_rx(i*9+7 downto i*9+0);
- fifo_rx_wr_en(i) <= not last_rx(i*9+8) and rx_allow_q(i) and link_ok(i);
+ fifo_rx_wr_en(i) <= not last_rx(i*9+8) and rx_allow_qrx(i) and link_ok(i);
end if;
end if;
end process;
- buf_med_data_out(i*16+15 downto i*16) <= fifo_rx_dout(i*18+15 downto i*18);
- buf_med_dataready_out(i) <= not fifo_rx_dout(i*18+17) and not fifo_rx_dout(i*18+16)
- and not last_fifo_rx_empty(i) and rx_allow(i);
+ buf_med_data_out(i*16+15 downto i*16) <= fifo_rx_dout(i*18+15 downto i*18);
+ buf_med_dataready_out(i) <= not fifo_rx_dout(i*18+17) and not fifo_rx_dout(i*18+16)
+ and not last_fifo_rx_empty(i) and rx_allow_q(i);
buf_med_packet_num_out(i*3+2 downto i*3) <= rx_counter(i*3+2 downto i*3);
- med_read_out(i) <= tx_allow_q(i);
+ med_read_out(i) <= tx_allow_q(i);
THE_SYNC_PROC: process( SYSCLK )
begin
begin
if( rising_edge(SYSCLK) ) then
last_fifo_rx_empty(i) <= fifo_rx_empty(i);
- if RESET = '1' or rx_allow(i) = '0' then
+ if RESET = '1' or rx_allow_q(i) = '0' then
rx_counter(i*3+2 downto i*3) <= c_H0;
else
if( buf_med_dataready_out(i) = '1' ) then
fifo_tx_reset(i) <= reset or not tx_allow_q(i);
fifo_tx_din(i*18+17 downto i*18) <= med_packet_num_in(i*3+2) & med_packet_num_in(i*3+0)& med_data_in(i*16+15 downto i*16);
fifo_tx_wr_en(i) <= med_dataready_in(i) and tx_allow(i);
- fifo_tx_rd_en(i) <= tx_allow_q(i);
+ fifo_tx_rd_en(i) <= tx_allow_qtx(i);
- THE_tx_allow_SYNC: signal_sync
- generic map(
- DEPTH => 2,
- WIDTH => 1
- )
- port map(
- RESET => RESET,
- D_IN(0) => tx_allow(i),
- CLK0 => SYSCLK,
- CLK1 => ff_txhalfclk,
- D_OUT(0) => tx_allow_q(i)
- );
-
- THE_rx_allow_SYNC: signal_sync
- generic map(
- DEPTH => 2,
- WIDTH => 1
- )
- port map(
- RESET => RESET,
- D_IN(0) => rx_allow(i),
- CLK0 => SYSCLK,
- CLK1 => ff_rxhalfclk(i),
- D_OUT(0) => rx_allow_q(i)
- );
THE_SERDES_INPUT_PROC: process( ff_txhalfclk )
begin
if( rising_edge(ff_txhalfclk) ) then
last_fifo_tx_empty(i) <= fifo_tx_empty(i);
- if( (last_fifo_tx_empty(i) = '1') or (tx_allow(i) = '0') ) then
+ if( (last_fifo_tx_empty(i) = '1') or (tx_allow_qtx(i) = '0') ) then
tx_data(i*16+15 downto i*16) <= x"c5bc";
tx_k(i*2+1 downto i*2) <= "01";
else
elsif( led_counter = 0 ) then
rx_led(i) <= '0';
end if;
- if( last_fifo_tx_empty(i) = '0') then
+ if( tx_k_q(i*2) = '0') then
tx_led(i) <= '1';
elsif led_counter = 0 then
tx_led(i) <= '0';
library work;
use work.trb_net_std.all;
+use work.trb_net_components.all;
entity trb_net16_iobuf is
attribute HGROUP of trb_net16_iobuf_arch : architecture is "IOBUF_group";
- component trb_net16_obuf is
- generic (
- DATA_COUNT_WIDTH : integer := 5;
- USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE;
- USE_CHECKSUM : integer range 0 to 1 := c_YES;
- SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_DATAREADY_OUT: out std_logic;
- MED_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_READ_IN: in std_logic;
- -- Internal direction port
- INT_DATAREADY_IN: in std_logic;
- INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_READ_OUT: out std_logic;
- -- Status and control port
- STAT_BUFFER: out std_logic_vector (31 downto 0);
- CTRL_BUFFER: in std_logic_vector (31 downto 0);
- STAT_DEBUG : out std_logic_vector (31 downto 0)
- );
- end component;
- component trb_net16_obuf_nodata is
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_DATAREADY_OUT: out std_logic;
- MED_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_READ_IN: in std_logic;
- --STAT
- STAT_BUFFER: out std_logic_vector (31 downto 0);
- CTRL_BUFFER: in std_logic_vector (31 downto 0);
- STAT_DEBUG : out std_logic_vector (31 downto 0)
- );
- end component;
-
- component trb_net16_ibuf is
- generic (
- DEPTH : integer range 0 to 7 := c_FIFO_BRAM;
- USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
- USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE;
- USE_CHECKSUM : integer range 0 to 1 := c_YES;
- SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
- SECURE_MODE : integer range 0 to 1 := c_YES;
- INIT_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES;
- REPLY_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_DATAREADY_IN : in std_logic;
- MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
- MED_READ_OUT : out std_logic;
- MED_ERROR_IN : in std_logic_vector (2 downto 0);
- -- Internal direction port
- INT_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_INIT_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
- INT_INIT_DATAREADY_OUT : out std_logic;
- INT_INIT_READ_IN : in std_logic;
- INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_REPLY_PACKET_NUM_OUT: out std_logic_vector(c_NUM_WIDTH-1 downto 0);
- INT_REPLY_DATAREADY_OUT : out std_logic;
- INT_REPLY_READ_IN : in std_logic;
- INT_ERROR_OUT : out std_logic_vector (2 downto 0);
- -- Status and control port
- STAT_BUFFER_COUNTER : out std_logic_vector (31 downto 0);
- STAT_BUFFER : out std_logic_vector (31 downto 0)
- );
- end component;
-
- component trb_net16_term_ibuf is
- generic(
- SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE;
- SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_DATAREADY_IN: in std_logic;
- MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN :in std_logic_vector(c_NUM_WIDTH-1 downto 0);
- MED_READ_OUT: out std_logic;
- MED_ERROR_IN: in std_logic_vector (2 downto 0);
- -- Internal direction port
- INT_DATAREADY_OUT: out std_logic;
- INT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_PACKET_NUM_OUT:out std_logic_vector(c_NUM_WIDTH-1 downto 0);
- INT_READ_IN: in std_logic;
- INT_ERROR_OUT: out std_logic_vector (2 downto 0);
- -- Status and control port
- STAT_BUFFER: out std_logic_vector (31 downto 0)
- );
- end component;
-- internal signals for the INITIBUF
signal IBUF_error: STD_LOGIC_VECTOR (2 downto 0); -- error watch needed!
jspc29 / trbnet.git / commitdiff